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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / init.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/slab.h>
18
19 #include "ath9k.h"
20
21 static char *dev_info = "ath9k";
22
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
27
28 static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
29 module_param_named(debug, ath9k_debug, uint, 0);
30 MODULE_PARM_DESC(debug, "Debugging mask");
31
32 int ath9k_modparam_nohwcrypt;
33 module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
34 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
35
36 int led_blink;
37 module_param_named(blink, led_blink, int, 0444);
38 MODULE_PARM_DESC(blink, "Enable LED blink on activity");
39
40 static int ath9k_btcoex_enable;
41 module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
42 MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
43
44 int ath9k_pm_qos_value = ATH9K_PM_QOS_DEFAULT_VALUE;
45 module_param_named(pmqos, ath9k_pm_qos_value, int, S_IRUSR | S_IRGRP | S_IROTH);
46 MODULE_PARM_DESC(pmqos, "User specified PM-QOS value");
47
48 bool is_ath9k_unloaded;
49 /* We use the hw_value as an index into our private channel structure */
50
51 #define CHAN2G(_freq, _idx) { \
52 .band = IEEE80211_BAND_2GHZ, \
53 .center_freq = (_freq), \
54 .hw_value = (_idx), \
55 .max_power = 20, \
56 }
57
58 #define CHAN5G(_freq, _idx) { \
59 .band = IEEE80211_BAND_5GHZ, \
60 .center_freq = (_freq), \
61 .hw_value = (_idx), \
62 .max_power = 20, \
63 }
64
65 /* Some 2 GHz radios are actually tunable on 2312-2732
66 * on 5 MHz steps, we support the channels which we know
67 * we have calibration data for all cards though to make
68 * this static */
69 static const struct ieee80211_channel ath9k_2ghz_chantable[] = {
70 CHAN2G(2412, 0), /* Channel 1 */
71 CHAN2G(2417, 1), /* Channel 2 */
72 CHAN2G(2422, 2), /* Channel 3 */
73 CHAN2G(2427, 3), /* Channel 4 */
74 CHAN2G(2432, 4), /* Channel 5 */
75 CHAN2G(2437, 5), /* Channel 6 */
76 CHAN2G(2442, 6), /* Channel 7 */
77 CHAN2G(2447, 7), /* Channel 8 */
78 CHAN2G(2452, 8), /* Channel 9 */
79 CHAN2G(2457, 9), /* Channel 10 */
80 CHAN2G(2462, 10), /* Channel 11 */
81 CHAN2G(2467, 11), /* Channel 12 */
82 CHAN2G(2472, 12), /* Channel 13 */
83 CHAN2G(2484, 13), /* Channel 14 */
84 };
85
86 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
87 * on 5 MHz steps, we support the channels which we know
88 * we have calibration data for all cards though to make
89 * this static */
90 static const struct ieee80211_channel ath9k_5ghz_chantable[] = {
91 /* _We_ call this UNII 1 */
92 CHAN5G(5180, 14), /* Channel 36 */
93 CHAN5G(5200, 15), /* Channel 40 */
94 CHAN5G(5220, 16), /* Channel 44 */
95 CHAN5G(5240, 17), /* Channel 48 */
96 /* _We_ call this UNII 2 */
97 CHAN5G(5260, 18), /* Channel 52 */
98 CHAN5G(5280, 19), /* Channel 56 */
99 CHAN5G(5300, 20), /* Channel 60 */
100 CHAN5G(5320, 21), /* Channel 64 */
101 /* _We_ call this "Middle band" */
102 CHAN5G(5500, 22), /* Channel 100 */
103 CHAN5G(5520, 23), /* Channel 104 */
104 CHAN5G(5540, 24), /* Channel 108 */
105 CHAN5G(5560, 25), /* Channel 112 */
106 CHAN5G(5580, 26), /* Channel 116 */
107 CHAN5G(5600, 27), /* Channel 120 */
108 CHAN5G(5620, 28), /* Channel 124 */
109 CHAN5G(5640, 29), /* Channel 128 */
110 CHAN5G(5660, 30), /* Channel 132 */
111 CHAN5G(5680, 31), /* Channel 136 */
112 CHAN5G(5700, 32), /* Channel 140 */
113 /* _We_ call this UNII 3 */
114 CHAN5G(5745, 33), /* Channel 149 */
115 CHAN5G(5765, 34), /* Channel 153 */
116 CHAN5G(5785, 35), /* Channel 157 */
117 CHAN5G(5805, 36), /* Channel 161 */
118 CHAN5G(5825, 37), /* Channel 165 */
119 };
120
121 /* Atheros hardware rate code addition for short premble */
122 #define SHPCHECK(__hw_rate, __flags) \
123 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04 ) : 0)
124
125 #define RATE(_bitrate, _hw_rate, _flags) { \
126 .bitrate = (_bitrate), \
127 .flags = (_flags), \
128 .hw_value = (_hw_rate), \
129 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \
130 }
131
132 static struct ieee80211_rate ath9k_legacy_rates[] = {
133 RATE(10, 0x1b, 0),
134 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE),
135 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE),
136 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE),
137 RATE(60, 0x0b, 0),
138 RATE(90, 0x0f, 0),
139 RATE(120, 0x0a, 0),
140 RATE(180, 0x0e, 0),
141 RATE(240, 0x09, 0),
142 RATE(360, 0x0d, 0),
143 RATE(480, 0x08, 0),
144 RATE(540, 0x0c, 0),
145 };
146
147 static void ath9k_deinit_softc(struct ath_softc *sc);
148
149 /*
150 * Read and write, they both share the same lock. We do this to serialize
151 * reads and writes on Atheros 802.11n PCI devices only. This is required
152 * as the FIFO on these devices can only accept sanely 2 requests.
153 */
154
155 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
156 {
157 struct ath_hw *ah = (struct ath_hw *) hw_priv;
158 struct ath_common *common = ath9k_hw_common(ah);
159 struct ath_softc *sc = (struct ath_softc *) common->priv;
160
161 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
162 unsigned long flags;
163 spin_lock_irqsave(&sc->sc_serial_rw, flags);
164 iowrite32(val, sc->mem + reg_offset);
165 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
166 } else
167 iowrite32(val, sc->mem + reg_offset);
168 }
169
170 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
171 {
172 struct ath_hw *ah = (struct ath_hw *) hw_priv;
173 struct ath_common *common = ath9k_hw_common(ah);
174 struct ath_softc *sc = (struct ath_softc *) common->priv;
175 u32 val;
176
177 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
178 unsigned long flags;
179 spin_lock_irqsave(&sc->sc_serial_rw, flags);
180 val = ioread32(sc->mem + reg_offset);
181 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
182 } else
183 val = ioread32(sc->mem + reg_offset);
184 return val;
185 }
186
187 static const struct ath_ops ath9k_common_ops = {
188 .read = ath9k_ioread32,
189 .write = ath9k_iowrite32,
190 };
191
192 /**************************/
193 /* Initialization */
194 /**************************/
195
196 static void setup_ht_cap(struct ath_softc *sc,
197 struct ieee80211_sta_ht_cap *ht_info)
198 {
199 struct ath_hw *ah = sc->sc_ah;
200 struct ath_common *common = ath9k_hw_common(ah);
201 u8 tx_streams, rx_streams;
202 int i, max_streams;
203
204 ht_info->ht_supported = true;
205 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
206 IEEE80211_HT_CAP_SM_PS |
207 IEEE80211_HT_CAP_SGI_40 |
208 IEEE80211_HT_CAP_DSSSCCK40;
209
210 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_LDPC)
211 ht_info->cap |= IEEE80211_HT_CAP_LDPC_CODING;
212
213 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20)
214 ht_info->cap |= IEEE80211_HT_CAP_SGI_20;
215
216 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
217 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
218
219 if (AR_SREV_9485(ah))
220 max_streams = 1;
221 else if (AR_SREV_9300_20_OR_LATER(ah))
222 max_streams = 3;
223 else
224 max_streams = 2;
225
226 if (AR_SREV_9280_20_OR_LATER(ah)) {
227 if (max_streams >= 2)
228 ht_info->cap |= IEEE80211_HT_CAP_TX_STBC;
229 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
230 }
231
232 /* set up supported mcs set */
233 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
234 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, max_streams);
235 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, max_streams);
236
237 ath_dbg(common, ATH_DBG_CONFIG,
238 "TX streams %d, RX streams: %d\n",
239 tx_streams, rx_streams);
240
241 if (tx_streams != rx_streams) {
242 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
243 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
244 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
245 }
246
247 for (i = 0; i < rx_streams; i++)
248 ht_info->mcs.rx_mask[i] = 0xff;
249
250 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
251 }
252
253 static int ath9k_reg_notifier(struct wiphy *wiphy,
254 struct regulatory_request *request)
255 {
256 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
257 struct ath_softc *sc = hw->priv;
258 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
259
260 return ath_reg_notifier_apply(wiphy, request, reg);
261 }
262
263 /*
264 * This function will allocate both the DMA descriptor structure, and the
265 * buffers it contains. These are used to contain the descriptors used
266 * by the system.
267 */
268 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
269 struct list_head *head, const char *name,
270 int nbuf, int ndesc, bool is_tx)
271 {
272 #define DS2PHYS(_dd, _ds) \
273 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
274 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
275 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
276 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
277 u8 *ds;
278 struct ath_buf *bf;
279 int i, bsize, error, desc_len;
280
281 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
282 name, nbuf, ndesc);
283
284 INIT_LIST_HEAD(head);
285
286 if (is_tx)
287 desc_len = sc->sc_ah->caps.tx_desc_len;
288 else
289 desc_len = sizeof(struct ath_desc);
290
291 /* ath_desc must be a multiple of DWORDs */
292 if ((desc_len % 4) != 0) {
293 ath_err(common, "ath_desc not DWORD aligned\n");
294 BUG_ON((desc_len % 4) != 0);
295 error = -ENOMEM;
296 goto fail;
297 }
298
299 dd->dd_desc_len = desc_len * nbuf * ndesc;
300
301 /*
302 * Need additional DMA memory because we can't use
303 * descriptors that cross the 4K page boundary. Assume
304 * one skipped descriptor per 4K page.
305 */
306 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
307 u32 ndesc_skipped =
308 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
309 u32 dma_len;
310
311 while (ndesc_skipped) {
312 dma_len = ndesc_skipped * desc_len;
313 dd->dd_desc_len += dma_len;
314
315 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
316 }
317 }
318
319 /* allocate descriptors */
320 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
321 &dd->dd_desc_paddr, GFP_KERNEL);
322 if (dd->dd_desc == NULL) {
323 error = -ENOMEM;
324 goto fail;
325 }
326 ds = (u8 *) dd->dd_desc;
327 ath_dbg(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
328 name, ds, (u32) dd->dd_desc_len,
329 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
330
331 /* allocate buffers */
332 bsize = sizeof(struct ath_buf) * nbuf;
333 bf = kzalloc(bsize, GFP_KERNEL);
334 if (bf == NULL) {
335 error = -ENOMEM;
336 goto fail2;
337 }
338 dd->dd_bufptr = bf;
339
340 for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
341 bf->bf_desc = ds;
342 bf->bf_daddr = DS2PHYS(dd, ds);
343
344 if (!(sc->sc_ah->caps.hw_caps &
345 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
346 /*
347 * Skip descriptor addresses which can cause 4KB
348 * boundary crossing (addr + length) with a 32 dword
349 * descriptor fetch.
350 */
351 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
352 BUG_ON((caddr_t) bf->bf_desc >=
353 ((caddr_t) dd->dd_desc +
354 dd->dd_desc_len));
355
356 ds += (desc_len * ndesc);
357 bf->bf_desc = ds;
358 bf->bf_daddr = DS2PHYS(dd, ds);
359 }
360 }
361 list_add_tail(&bf->list, head);
362 }
363 return 0;
364 fail2:
365 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
366 dd->dd_desc_paddr);
367 fail:
368 memset(dd, 0, sizeof(*dd));
369 return error;
370 #undef ATH_DESC_4KB_BOUND_CHECK
371 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
372 #undef DS2PHYS
373 }
374
375 void ath9k_init_crypto(struct ath_softc *sc)
376 {
377 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
378 int i = 0;
379
380 /* Get the hardware key cache size. */
381 common->keymax = sc->sc_ah->caps.keycache_size;
382 if (common->keymax > ATH_KEYMAX) {
383 ath_dbg(common, ATH_DBG_ANY,
384 "Warning, using only %u entries in %u key cache\n",
385 ATH_KEYMAX, common->keymax);
386 common->keymax = ATH_KEYMAX;
387 }
388
389 /*
390 * Reset the key cache since some parts do not
391 * reset the contents on initial power up.
392 */
393 for (i = 0; i < common->keymax; i++)
394 ath_hw_keyreset(common, (u16) i);
395
396 /*
397 * Check whether the separate key cache entries
398 * are required to handle both tx+rx MIC keys.
399 * With split mic keys the number of stations is limited
400 * to 27 otherwise 59.
401 */
402 if (sc->sc_ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA)
403 common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
404 }
405
406 static int ath9k_init_btcoex(struct ath_softc *sc)
407 {
408 struct ath_txq *txq;
409 int r;
410
411 switch (sc->sc_ah->btcoex_hw.scheme) {
412 case ATH_BTCOEX_CFG_NONE:
413 break;
414 case ATH_BTCOEX_CFG_2WIRE:
415 ath9k_hw_btcoex_init_2wire(sc->sc_ah);
416 break;
417 case ATH_BTCOEX_CFG_3WIRE:
418 ath9k_hw_btcoex_init_3wire(sc->sc_ah);
419 r = ath_init_btcoex_timer(sc);
420 if (r)
421 return -1;
422 txq = sc->tx.txq_map[WME_AC_BE];
423 ath9k_hw_init_btcoex_hw(sc->sc_ah, txq->axq_qnum);
424 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
425 break;
426 default:
427 WARN_ON(1);
428 break;
429 }
430
431 return 0;
432 }
433
434 static int ath9k_init_queues(struct ath_softc *sc)
435 {
436 int i = 0;
437
438 sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
439 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
440
441 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
442 ath_cabq_update(sc);
443
444 for (i = 0; i < WME_NUM_AC; i++) {
445 sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
446 sc->tx.txq_map[i]->mac80211_qnum = i;
447 }
448 return 0;
449 }
450
451 static int ath9k_init_channels_rates(struct ath_softc *sc)
452 {
453 void *channels;
454
455 BUILD_BUG_ON(ARRAY_SIZE(ath9k_2ghz_chantable) +
456 ARRAY_SIZE(ath9k_5ghz_chantable) !=
457 ATH9K_NUM_CHANNELS);
458
459 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) {
460 channels = kmemdup(ath9k_2ghz_chantable,
461 sizeof(ath9k_2ghz_chantable), GFP_KERNEL);
462 if (!channels)
463 return -ENOMEM;
464
465 sc->sbands[IEEE80211_BAND_2GHZ].channels = channels;
466 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
467 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
468 ARRAY_SIZE(ath9k_2ghz_chantable);
469 sc->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates;
470 sc->sbands[IEEE80211_BAND_2GHZ].n_bitrates =
471 ARRAY_SIZE(ath9k_legacy_rates);
472 }
473
474 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) {
475 channels = kmemdup(ath9k_5ghz_chantable,
476 sizeof(ath9k_5ghz_chantable), GFP_KERNEL);
477 if (!channels) {
478 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
479 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
480 return -ENOMEM;
481 }
482
483 sc->sbands[IEEE80211_BAND_5GHZ].channels = channels;
484 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
485 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
486 ARRAY_SIZE(ath9k_5ghz_chantable);
487 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
488 ath9k_legacy_rates + 4;
489 sc->sbands[IEEE80211_BAND_5GHZ].n_bitrates =
490 ARRAY_SIZE(ath9k_legacy_rates) - 4;
491 }
492 return 0;
493 }
494
495 static void ath9k_init_misc(struct ath_softc *sc)
496 {
497 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
498 int i = 0;
499
500 setup_timer(&common->ani.timer, ath_ani_calibrate, (unsigned long)sc);
501
502 sc->config.txpowlimit = ATH_TXPOWER_MAX;
503
504 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
505 sc->sc_flags |= SC_OP_TXAGGR;
506 sc->sc_flags |= SC_OP_RXAGGR;
507 }
508
509 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
510 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
511
512 ath9k_hw_set_diversity(sc->sc_ah, true);
513 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
514
515 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
516
517 sc->beacon.slottime = ATH9K_SLOT_TIME_9;
518
519 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
520 sc->beacon.bslot[i] = NULL;
521
522 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
523 sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
524 }
525
526 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
527 const struct ath_bus_ops *bus_ops)
528 {
529 struct ath_hw *ah = NULL;
530 struct ath_common *common;
531 int ret = 0, i;
532 int csz = 0;
533
534 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
535 if (!ah)
536 return -ENOMEM;
537
538 ah->hw = sc->hw;
539 ah->hw_version.devid = devid;
540 ah->hw_version.subsysid = subsysid;
541 sc->sc_ah = ah;
542
543 if (!sc->dev->platform_data)
544 ah->ah_flags |= AH_USE_EEPROM;
545
546 common = ath9k_hw_common(ah);
547 common->ops = &ath9k_common_ops;
548 common->bus_ops = bus_ops;
549 common->ah = ah;
550 common->hw = sc->hw;
551 common->priv = sc;
552 common->debug_mask = ath9k_debug;
553 common->btcoex_enabled = ath9k_btcoex_enable == 1;
554 spin_lock_init(&common->cc_lock);
555
556 spin_lock_init(&sc->sc_serial_rw);
557 spin_lock_init(&sc->sc_pm_lock);
558 mutex_init(&sc->mutex);
559 #ifdef CONFIG_ATH9K_DEBUGFS
560 spin_lock_init(&sc->nodes_lock);
561 INIT_LIST_HEAD(&sc->nodes);
562 #endif
563 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
564 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
565 (unsigned long)sc);
566
567 /*
568 * Cache line size is used to size and align various
569 * structures used to communicate with the hardware.
570 */
571 ath_read_cachesize(common, &csz);
572 common->cachelsz = csz << 2; /* convert to bytes */
573
574 /* Initializes the hardware for all supported chipsets */
575 ret = ath9k_hw_init(ah);
576 if (ret)
577 goto err_hw;
578
579 ret = ath9k_init_queues(sc);
580 if (ret)
581 goto err_queues;
582
583 ret = ath9k_init_btcoex(sc);
584 if (ret)
585 goto err_btcoex;
586
587 ret = ath9k_init_channels_rates(sc);
588 if (ret)
589 goto err_btcoex;
590
591 ath9k_init_crypto(sc);
592 ath9k_init_misc(sc);
593
594 return 0;
595
596 err_btcoex:
597 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
598 if (ATH_TXQ_SETUP(sc, i))
599 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
600 err_queues:
601 ath9k_hw_deinit(ah);
602 err_hw:
603
604 kfree(ah);
605 sc->sc_ah = NULL;
606
607 return ret;
608 }
609
610 static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
611 {
612 struct ieee80211_supported_band *sband;
613 struct ieee80211_channel *chan;
614 struct ath_hw *ah = sc->sc_ah;
615 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
616 int i;
617
618 sband = &sc->sbands[band];
619 for (i = 0; i < sband->n_channels; i++) {
620 chan = &sband->channels[i];
621 ah->curchan = &ah->channels[chan->hw_value];
622 ath9k_cmn_update_ichannel(ah->curchan, chan, NL80211_CHAN_HT20);
623 ath9k_hw_set_txpowerlimit(ah, MAX_RATE_POWER, true);
624 chan->max_power = reg->max_power_level / 2;
625 }
626 }
627
628 static void ath9k_init_txpower_limits(struct ath_softc *sc)
629 {
630 struct ath_hw *ah = sc->sc_ah;
631 struct ath9k_channel *curchan = ah->curchan;
632
633 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
634 ath9k_init_band_txpower(sc, IEEE80211_BAND_2GHZ);
635 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
636 ath9k_init_band_txpower(sc, IEEE80211_BAND_5GHZ);
637
638 ah->curchan = curchan;
639 }
640
641 void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
642 {
643 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
644
645 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
646 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
647 IEEE80211_HW_SIGNAL_DBM |
648 IEEE80211_HW_SUPPORTS_PS |
649 IEEE80211_HW_PS_NULLFUNC_STACK |
650 IEEE80211_HW_SPECTRUM_MGMT |
651 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
652
653 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
654 hw->flags |= IEEE80211_HW_AMPDU_AGGREGATION;
655
656 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
657 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
658
659 hw->wiphy->interface_modes =
660 BIT(NL80211_IFTYPE_P2P_GO) |
661 BIT(NL80211_IFTYPE_P2P_CLIENT) |
662 BIT(NL80211_IFTYPE_AP) |
663 BIT(NL80211_IFTYPE_WDS) |
664 BIT(NL80211_IFTYPE_STATION) |
665 BIT(NL80211_IFTYPE_ADHOC) |
666 BIT(NL80211_IFTYPE_MESH_POINT);
667
668 if (AR_SREV_5416(sc->sc_ah))
669 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
670
671 hw->queues = 4;
672 hw->max_rates = 4;
673 hw->channel_change_time = 5000;
674 hw->max_listen_interval = 10;
675 hw->max_rate_tries = 10;
676 hw->sta_data_size = sizeof(struct ath_node);
677 hw->vif_data_size = sizeof(struct ath_vif);
678
679 #ifdef CONFIG_ATH9K_RATE_CONTROL
680 hw->rate_control_algorithm = "ath9k_rate_control";
681 #endif
682
683 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
684 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
685 &sc->sbands[IEEE80211_BAND_2GHZ];
686 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
687 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
688 &sc->sbands[IEEE80211_BAND_5GHZ];
689
690 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
691 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
692 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
693 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
694 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
695 }
696
697 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
698 }
699
700 int ath9k_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
701 const struct ath_bus_ops *bus_ops)
702 {
703 struct ieee80211_hw *hw = sc->hw;
704 struct ath_common *common;
705 struct ath_hw *ah;
706 int error = 0;
707 struct ath_regulatory *reg;
708
709 /* Bring up device */
710 error = ath9k_init_softc(devid, sc, subsysid, bus_ops);
711 if (error != 0)
712 goto error_init;
713
714 ah = sc->sc_ah;
715 common = ath9k_hw_common(ah);
716 ath9k_set_hw_capab(sc, hw);
717
718 /* Initialize regulatory */
719 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
720 ath9k_reg_notifier);
721 if (error)
722 goto error_regd;
723
724 reg = &common->regulatory;
725
726 /* Setup TX DMA */
727 error = ath_tx_init(sc, ATH_TXBUF);
728 if (error != 0)
729 goto error_tx;
730
731 /* Setup RX DMA */
732 error = ath_rx_init(sc, ATH_RXBUF);
733 if (error != 0)
734 goto error_rx;
735
736 ath9k_init_txpower_limits(sc);
737
738 /* Register with mac80211 */
739 error = ieee80211_register_hw(hw);
740 if (error)
741 goto error_register;
742
743 error = ath9k_init_debug(ah);
744 if (error) {
745 ath_err(common, "Unable to create debugfs files\n");
746 goto error_world;
747 }
748
749 /* Handle world regulatory */
750 if (!ath_is_world_regd(reg)) {
751 error = regulatory_hint(hw->wiphy, reg->alpha2);
752 if (error)
753 goto error_world;
754 }
755
756 INIT_WORK(&sc->hw_check_work, ath_hw_check);
757 INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
758 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
759
760 ath_init_leds(sc);
761 ath_start_rfkill_poll(sc);
762
763 pm_qos_add_request(&sc->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
764 PM_QOS_DEFAULT_VALUE);
765
766 return 0;
767
768 error_world:
769 ieee80211_unregister_hw(hw);
770 error_register:
771 ath_rx_cleanup(sc);
772 error_rx:
773 ath_tx_cleanup(sc);
774 error_tx:
775 /* Nothing */
776 error_regd:
777 ath9k_deinit_softc(sc);
778 error_init:
779 return error;
780 }
781
782 /*****************************/
783 /* De-Initialization */
784 /*****************************/
785
786 static void ath9k_deinit_softc(struct ath_softc *sc)
787 {
788 int i = 0;
789
790 if (sc->sbands[IEEE80211_BAND_2GHZ].channels)
791 kfree(sc->sbands[IEEE80211_BAND_2GHZ].channels);
792
793 if (sc->sbands[IEEE80211_BAND_5GHZ].channels)
794 kfree(sc->sbands[IEEE80211_BAND_5GHZ].channels);
795
796 if ((sc->btcoex.no_stomp_timer) &&
797 sc->sc_ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
798 ath_gen_timer_free(sc->sc_ah, sc->btcoex.no_stomp_timer);
799
800 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
801 if (ATH_TXQ_SETUP(sc, i))
802 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
803
804 ath9k_hw_deinit(sc->sc_ah);
805
806 kfree(sc->sc_ah);
807 sc->sc_ah = NULL;
808 }
809
810 void ath9k_deinit_device(struct ath_softc *sc)
811 {
812 struct ieee80211_hw *hw = sc->hw;
813
814 ath9k_ps_wakeup(sc);
815
816 wiphy_rfkill_stop_polling(sc->hw->wiphy);
817 ath_deinit_leds(sc);
818
819 ath9k_ps_restore(sc);
820
821 ieee80211_unregister_hw(hw);
822 pm_qos_remove_request(&sc->pm_qos_req);
823 ath_rx_cleanup(sc);
824 ath_tx_cleanup(sc);
825 ath9k_deinit_softc(sc);
826 }
827
828 void ath_descdma_cleanup(struct ath_softc *sc,
829 struct ath_descdma *dd,
830 struct list_head *head)
831 {
832 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
833 dd->dd_desc_paddr);
834
835 INIT_LIST_HEAD(head);
836 kfree(dd->dd_bufptr);
837 memset(dd, 0, sizeof(*dd));
838 }
839
840 /************************/
841 /* Module Hooks */
842 /************************/
843
844 static int __init ath9k_init(void)
845 {
846 int error;
847
848 /* Register rate control algorithm */
849 error = ath_rate_control_register();
850 if (error != 0) {
851 printk(KERN_ERR
852 "ath9k: Unable to register rate control "
853 "algorithm: %d\n",
854 error);
855 goto err_out;
856 }
857
858 error = ath_pci_init();
859 if (error < 0) {
860 printk(KERN_ERR
861 "ath9k: No PCI devices found, driver not installed.\n");
862 error = -ENODEV;
863 goto err_rate_unregister;
864 }
865
866 error = ath_ahb_init();
867 if (error < 0) {
868 error = -ENODEV;
869 goto err_pci_exit;
870 }
871
872 return 0;
873
874 err_pci_exit:
875 ath_pci_exit();
876
877 err_rate_unregister:
878 ath_rate_control_unregister();
879 err_out:
880 return error;
881 }
882 module_init(ath9k_init);
883
884 static void __exit ath9k_exit(void)
885 {
886 is_ath9k_unloaded = true;
887 ath_ahb_exit();
888 ath_pci_exit();
889 ath_rate_control_unregister();
890 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
891 }
892 module_exit(ath9k_exit);
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