2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \
21 MS(ads->ds_rxstatus0, AR_RxRate) : \
22 (ads->ds_rxstatus3 >> 2) & 0xFF)
24 #define set11nTries(_series, _index) \
25 (SM((_series)[_index].Tries, AR_XmitDataTries##_index))
27 #define set11nRate(_series, _index) \
28 (SM((_series)[_index].Rate, AR_XmitRate##_index))
30 #define set11nPktDurRTSCTS(_series, _index) \
31 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \
32 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \
33 AR_RTSCTSQual##_index : 0))
35 #define set11nRateFlags(_series, _index) \
36 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \
37 AR_2040_##_index : 0) \
38 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \
40 |SM((_series)[_index].ChSel, AR_ChainSel##_index))
42 #define CCK_SIFS_TIME 10
43 #define CCK_PREAMBLE_BITS 144
44 #define CCK_PLCP_BITS 48
46 #define OFDM_SIFS_TIME 16
47 #define OFDM_PREAMBLE_TIME 20
48 #define OFDM_PLCP_BITS 22
49 #define OFDM_SYMBOL_TIME 4
51 #define OFDM_SIFS_TIME_HALF 32
52 #define OFDM_PREAMBLE_TIME_HALF 40
53 #define OFDM_PLCP_BITS_HALF 22
54 #define OFDM_SYMBOL_TIME_HALF 8
56 #define OFDM_SIFS_TIME_QUARTER 64
57 #define OFDM_PREAMBLE_TIME_QUARTER 80
58 #define OFDM_PLCP_BITS_QUARTER 22
59 #define OFDM_SYMBOL_TIME_QUARTER 16
63 #define INIT_CWMIN_11B 31
64 #define INIT_CWMAX 1023
65 #define INIT_SH_RETRY 10
66 #define INIT_LG_RETRY 10
67 #define INIT_SSH_RETRY 32
68 #define INIT_SLG_RETRY 32
70 #define ATH9K_SLOT_TIME_6 6
71 #define ATH9K_SLOT_TIME_9 9
72 #define ATH9K_SLOT_TIME_20 20
74 #define ATH9K_TXERR_XRETRY 0x01
75 #define ATH9K_TXERR_FILT 0x02
76 #define ATH9K_TXERR_FIFO 0x04
77 #define ATH9K_TXERR_XTXOP 0x08
78 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
79 #define ATH9K_TX_ACKED 0x20
80 #define ATH9K_TXERR_MASK \
81 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \
82 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED)
84 #define ATH9K_TX_BA 0x01
85 #define ATH9K_TX_PWRMGMT 0x02
86 #define ATH9K_TX_DESC_CFG_ERR 0x04
87 #define ATH9K_TX_DATA_UNDERRUN 0x08
88 #define ATH9K_TX_DELIM_UNDERRUN 0x10
89 #define ATH9K_TX_SW_ABORTED 0x40
90 #define ATH9K_TX_SW_FILTERED 0x80
93 #define MIN_TX_FIFO_THRESHOLD 0x1
96 * Single stream device AR9285 and AR9271 require 2 KB
97 * to work around a hardware issue, all other devices
98 * have can use the max 4 KB limit.
100 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1)
102 struct ath_tx_status
{
128 struct ath_rx_status
{
153 struct ath_htc_rx_status
{
179 #define ATH9K_RXERR_CRC 0x01
180 #define ATH9K_RXERR_PHY 0x02
181 #define ATH9K_RXERR_FIFO 0x04
182 #define ATH9K_RXERR_DECRYPT 0x08
183 #define ATH9K_RXERR_MIC 0x10
185 #define ATH9K_RX_MORE 0x01
186 #define ATH9K_RX_MORE_AGGR 0x02
187 #define ATH9K_RX_GI 0x04
188 #define ATH9K_RX_2040 0x08
189 #define ATH9K_RX_DELIM_CRC_PRE 0x10
190 #define ATH9K_RX_DELIM_CRC_POST 0x20
191 #define ATH9K_RX_DECRYPT_BUSY 0x40
193 #define ATH9K_RXKEYIX_INVALID ((u8)-1)
194 #define ATH9K_TXKEYIX_INVALID ((u32)-1)
197 ATH9K_PHYERR_UNDERRUN
= 0, /* Transmit underrun */
198 ATH9K_PHYERR_TIMING
= 1, /* Timing error */
199 ATH9K_PHYERR_PARITY
= 2, /* Illegal parity */
200 ATH9K_PHYERR_RATE
= 3, /* Illegal rate */
201 ATH9K_PHYERR_LENGTH
= 4, /* Illegal length */
202 ATH9K_PHYERR_RADAR
= 5, /* Radar detect */
203 ATH9K_PHYERR_SERVICE
= 6, /* Illegal service */
204 ATH9K_PHYERR_TOR
= 7, /* Transmit override receive */
206 ATH9K_PHYERR_OFDM_TIMING
= 17,
207 ATH9K_PHYERR_OFDM_SIGNAL_PARITY
= 18,
208 ATH9K_PHYERR_OFDM_RATE_ILLEGAL
= 19,
209 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL
= 20,
210 ATH9K_PHYERR_OFDM_POWER_DROP
= 21,
211 ATH9K_PHYERR_OFDM_SERVICE
= 22,
212 ATH9K_PHYERR_OFDM_RESTART
= 23,
213 ATH9K_PHYERR_FALSE_RADAR_EXT
= 24,
215 ATH9K_PHYERR_CCK_TIMING
= 25,
216 ATH9K_PHYERR_CCK_HEADER_CRC
= 26,
217 ATH9K_PHYERR_CCK_RATE_ILLEGAL
= 27,
218 ATH9K_PHYERR_CCK_SERVICE
= 30,
219 ATH9K_PHYERR_CCK_RESTART
= 31,
220 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL
= 32,
221 ATH9K_PHYERR_CCK_POWER_DROP
= 33,
223 ATH9K_PHYERR_HT_CRC_ERROR
= 34,
224 ATH9K_PHYERR_HT_LENGTH_ILLEGAL
= 35,
225 ATH9K_PHYERR_HT_RATE_ILLEGAL
= 36,
227 ATH9K_PHYERR_MAX
= 37,
237 struct ath_tx_status tx
;
238 struct ath_rx_status rx
;
244 #define ds_txstat ds_us.tx
245 #define ds_rxstat ds_us.rx
246 #define ds_stat ds_us.stats
248 #define ATH9K_TXDESC_CLRDMASK 0x0001
249 #define ATH9K_TXDESC_NOACK 0x0002
250 #define ATH9K_TXDESC_RTSENA 0x0004
251 #define ATH9K_TXDESC_CTSENA 0x0008
252 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for
253 * the descriptor its marked on. We take a tx interrupt to reap
254 * descriptors when the h/w hits an EOL condition or
255 * when the descriptor is specifically marked to generate
256 * an interrupt with this flag. Descriptors should be
257 * marked periodically to insure timely replenishing of the
258 * supply needed for sending frames. Defering interrupts
259 * reduces system load and potentially allows more concurrent
260 * work to be done but if done to aggressively can cause
261 * senders to backup. When the hardware queue is left too
262 * large rate control information may also be too out of
263 * date. An Alternative for this is TX interrupt mitigation
264 * but this needs more testing. */
265 #define ATH9K_TXDESC_INTREQ 0x0010
266 #define ATH9K_TXDESC_VEOL 0x0020
267 #define ATH9K_TXDESC_EXT_ONLY 0x0040
268 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
269 #define ATH9K_TXDESC_VMF 0x0100
270 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
271 #define ATH9K_TXDESC_CAB 0x0400
273 #define ATH9K_RXDESC_INTREQ 0x0020
317 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds))
318 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds))
320 #define ds_ctl2 u.tx.ctl2
321 #define ds_ctl3 u.tx.ctl3
322 #define ds_ctl4 u.tx.ctl4
323 #define ds_ctl5 u.tx.ctl5
324 #define ds_ctl6 u.tx.ctl6
325 #define ds_ctl7 u.tx.ctl7
326 #define ds_ctl8 u.tx.ctl8
327 #define ds_ctl9 u.tx.ctl9
328 #define ds_ctl10 u.tx.ctl10
329 #define ds_ctl11 u.tx.ctl11
331 #define ds_txstatus0 u.tx.status0
332 #define ds_txstatus1 u.tx.status1
333 #define ds_txstatus2 u.tx.status2
334 #define ds_txstatus3 u.tx.status3
335 #define ds_txstatus4 u.tx.status4
336 #define ds_txstatus5 u.tx.status5
337 #define ds_txstatus6 u.tx.status6
338 #define ds_txstatus7 u.tx.status7
339 #define ds_txstatus8 u.tx.status8
340 #define ds_txstatus9 u.tx.status9
342 #define ds_rxstatus0 u.rx.status0
343 #define ds_rxstatus1 u.rx.status1
344 #define ds_rxstatus2 u.rx.status2
345 #define ds_rxstatus3 u.rx.status3
346 #define ds_rxstatus4 u.rx.status4
347 #define ds_rxstatus5 u.rx.status5
348 #define ds_rxstatus6 u.rx.status6
349 #define ds_rxstatus7 u.rx.status7
350 #define ds_rxstatus8 u.rx.status8
352 #define AR_FrameLen 0x00000fff
353 #define AR_VirtMoreFrag 0x00001000
354 #define AR_TxCtlRsvd00 0x0000e000
355 #define AR_XmitPower 0x003f0000
356 #define AR_XmitPower_S 16
357 #define AR_RTSEnable 0x00400000
358 #define AR_VEOL 0x00800000
359 #define AR_ClrDestMask 0x01000000
360 #define AR_TxCtlRsvd01 0x1e000000
361 #define AR_TxIntrReq 0x20000000
362 #define AR_DestIdxValid 0x40000000
363 #define AR_CTSEnable 0x80000000
365 #define AR_BufLen 0x00000fff
366 #define AR_TxMore 0x00001000
367 #define AR_DestIdx 0x000fe000
368 #define AR_DestIdx_S 13
369 #define AR_FrameType 0x00f00000
370 #define AR_FrameType_S 20
371 #define AR_NoAck 0x01000000
372 #define AR_InsertTS 0x02000000
373 #define AR_CorruptFCS 0x04000000
374 #define AR_ExtOnly 0x08000000
375 #define AR_ExtAndCtl 0x10000000
376 #define AR_MoreAggr 0x20000000
377 #define AR_IsAggr 0x40000000
379 #define AR_BurstDur 0x00007fff
380 #define AR_BurstDur_S 0
381 #define AR_DurUpdateEna 0x00008000
382 #define AR_XmitDataTries0 0x000f0000
383 #define AR_XmitDataTries0_S 16
384 #define AR_XmitDataTries1 0x00f00000
385 #define AR_XmitDataTries1_S 20
386 #define AR_XmitDataTries2 0x0f000000
387 #define AR_XmitDataTries2_S 24
388 #define AR_XmitDataTries3 0xf0000000
389 #define AR_XmitDataTries3_S 28
391 #define AR_XmitRate0 0x000000ff
392 #define AR_XmitRate0_S 0
393 #define AR_XmitRate1 0x0000ff00
394 #define AR_XmitRate1_S 8
395 #define AR_XmitRate2 0x00ff0000
396 #define AR_XmitRate2_S 16
397 #define AR_XmitRate3 0xff000000
398 #define AR_XmitRate3_S 24
400 #define AR_PacketDur0 0x00007fff
401 #define AR_PacketDur0_S 0
402 #define AR_RTSCTSQual0 0x00008000
403 #define AR_PacketDur1 0x7fff0000
404 #define AR_PacketDur1_S 16
405 #define AR_RTSCTSQual1 0x80000000
407 #define AR_PacketDur2 0x00007fff
408 #define AR_PacketDur2_S 0
409 #define AR_RTSCTSQual2 0x00008000
410 #define AR_PacketDur3 0x7fff0000
411 #define AR_PacketDur3_S 16
412 #define AR_RTSCTSQual3 0x80000000
414 #define AR_AggrLen 0x0000ffff
415 #define AR_AggrLen_S 0
416 #define AR_TxCtlRsvd60 0x00030000
417 #define AR_PadDelim 0x03fc0000
418 #define AR_PadDelim_S 18
419 #define AR_EncrType 0x0c000000
420 #define AR_EncrType_S 26
421 #define AR_TxCtlRsvd61 0xf0000000
423 #define AR_2040_0 0x00000001
424 #define AR_GI0 0x00000002
425 #define AR_ChainSel0 0x0000001c
426 #define AR_ChainSel0_S 2
427 #define AR_2040_1 0x00000020
428 #define AR_GI1 0x00000040
429 #define AR_ChainSel1 0x00000380
430 #define AR_ChainSel1_S 7
431 #define AR_2040_2 0x00000400
432 #define AR_GI2 0x00000800
433 #define AR_ChainSel2 0x00007000
434 #define AR_ChainSel2_S 12
435 #define AR_2040_3 0x00008000
436 #define AR_GI3 0x00010000
437 #define AR_ChainSel3 0x000e0000
438 #define AR_ChainSel3_S 17
439 #define AR_RTSCTSRate 0x0ff00000
440 #define AR_RTSCTSRate_S 20
441 #define AR_TxCtlRsvd70 0xf0000000
443 #define AR_TxRSSIAnt00 0x000000ff
444 #define AR_TxRSSIAnt00_S 0
445 #define AR_TxRSSIAnt01 0x0000ff00
446 #define AR_TxRSSIAnt01_S 8
447 #define AR_TxRSSIAnt02 0x00ff0000
448 #define AR_TxRSSIAnt02_S 16
449 #define AR_TxStatusRsvd00 0x3f000000
450 #define AR_TxBaStatus 0x40000000
451 #define AR_TxStatusRsvd01 0x80000000
454 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was
455 * transmitted successfully. If clear, no ACK or BA was received to indicate
456 * successful transmission when we were expecting an ACK or BA.
458 #define AR_FrmXmitOK 0x00000001
459 #define AR_ExcessiveRetries 0x00000002
460 #define AR_FIFOUnderrun 0x00000004
461 #define AR_Filtered 0x00000008
462 #define AR_RTSFailCnt 0x000000f0
463 #define AR_RTSFailCnt_S 4
464 #define AR_DataFailCnt 0x00000f00
465 #define AR_DataFailCnt_S 8
466 #define AR_VirtRetryCnt 0x0000f000
467 #define AR_VirtRetryCnt_S 12
468 #define AR_TxDelimUnderrun 0x00010000
469 #define AR_TxDataUnderrun 0x00020000
470 #define AR_DescCfgErr 0x00040000
471 #define AR_TxTimerExpired 0x00080000
472 #define AR_TxStatusRsvd10 0xfff00000
474 #define AR_SendTimestamp ds_txstatus2
475 #define AR_BaBitmapLow ds_txstatus3
476 #define AR_BaBitmapHigh ds_txstatus4
478 #define AR_TxRSSIAnt10 0x000000ff
479 #define AR_TxRSSIAnt10_S 0
480 #define AR_TxRSSIAnt11 0x0000ff00
481 #define AR_TxRSSIAnt11_S 8
482 #define AR_TxRSSIAnt12 0x00ff0000
483 #define AR_TxRSSIAnt12_S 16
484 #define AR_TxRSSICombined 0xff000000
485 #define AR_TxRSSICombined_S 24
487 #define AR_TxEVM0 ds_txstatus5
488 #define AR_TxEVM1 ds_txstatus6
489 #define AR_TxEVM2 ds_txstatus7
491 #define AR_TxDone 0x00000001
492 #define AR_SeqNum 0x00001ffe
493 #define AR_SeqNum_S 1
494 #define AR_TxStatusRsvd80 0x0001e000
495 #define AR_TxOpExceeded 0x00020000
496 #define AR_TxStatusRsvd81 0x001c0000
497 #define AR_FinalTxIdx 0x00600000
498 #define AR_FinalTxIdx_S 21
499 #define AR_TxStatusRsvd82 0x01800000
500 #define AR_PowerMgmt 0x02000000
501 #define AR_TxStatusRsvd83 0xfc000000
503 #define AR_RxCTLRsvd00 0xffffffff
505 #define AR_BufLen 0x00000fff
506 #define AR_RxCtlRsvd00 0x00001000
507 #define AR_RxIntrReq 0x00002000
508 #define AR_RxCtlRsvd01 0xffffc000
510 #define AR_RxRSSIAnt00 0x000000ff
511 #define AR_RxRSSIAnt00_S 0
512 #define AR_RxRSSIAnt01 0x0000ff00
513 #define AR_RxRSSIAnt01_S 8
514 #define AR_RxRSSIAnt02 0x00ff0000
515 #define AR_RxRSSIAnt02_S 16
516 #define AR_RxRate 0xff000000
517 #define AR_RxRate_S 24
518 #define AR_RxStatusRsvd00 0xff000000
520 #define AR_DataLen 0x00000fff
521 #define AR_RxMore 0x00001000
522 #define AR_NumDelim 0x003fc000
523 #define AR_NumDelim_S 14
524 #define AR_RxStatusRsvd10 0xff800000
526 #define AR_RcvTimestamp ds_rxstatus2
528 #define AR_GI 0x00000001
529 #define AR_2040 0x00000002
530 #define AR_Parallel40 0x00000004
531 #define AR_Parallel40_S 2
532 #define AR_RxStatusRsvd30 0x000000f8
533 #define AR_RxAntenna 0xffffff00
534 #define AR_RxAntenna_S 8
536 #define AR_RxRSSIAnt10 0x000000ff
537 #define AR_RxRSSIAnt10_S 0
538 #define AR_RxRSSIAnt11 0x0000ff00
539 #define AR_RxRSSIAnt11_S 8
540 #define AR_RxRSSIAnt12 0x00ff0000
541 #define AR_RxRSSIAnt12_S 16
542 #define AR_RxRSSICombined 0xff000000
543 #define AR_RxRSSICombined_S 24
545 #define AR_RxEVM0 ds_rxstatus4
546 #define AR_RxEVM1 ds_rxstatus5
547 #define AR_RxEVM2 ds_rxstatus6
549 #define AR_RxDone 0x00000001
550 #define AR_RxFrameOK 0x00000002
551 #define AR_CRCErr 0x00000004
552 #define AR_DecryptCRCErr 0x00000008
553 #define AR_PHYErr 0x00000010
554 #define AR_MichaelErr 0x00000020
555 #define AR_PreDelimCRCErr 0x00000040
556 #define AR_RxStatusRsvd70 0x00000080
557 #define AR_RxKeyIdxValid 0x00000100
558 #define AR_KeyIdx 0x0000fe00
559 #define AR_KeyIdx_S 9
560 #define AR_PHYErrCode 0x0000ff00
561 #define AR_PHYErrCode_S 8
562 #define AR_RxMoreAggr 0x00010000
563 #define AR_RxAggr 0x00020000
564 #define AR_PostDelimCRCErr 0x00040000
565 #define AR_RxStatusRsvd71 0x3ff80000
566 #define AR_DecryptBusyErr 0x40000000
567 #define AR_KeyMiss 0x80000000
569 enum ath9k_tx_queue
{
570 ATH9K_TX_QUEUE_INACTIVE
= 0,
572 ATH9K_TX_QUEUE_BEACON
,
574 ATH9K_TX_QUEUE_UAPSD
,
575 ATH9K_TX_QUEUE_PSPOLL
578 #define ATH9K_NUM_TX_QUEUES 10
580 enum ath9k_tx_queue_subtype
{
588 enum ath9k_tx_queue_flags
{
589 TXQ_FLAG_TXOKINT_ENABLE
= 0x0001,
590 TXQ_FLAG_TXERRINT_ENABLE
= 0x0001,
591 TXQ_FLAG_TXDESCINT_ENABLE
= 0x0002,
592 TXQ_FLAG_TXEOLINT_ENABLE
= 0x0004,
593 TXQ_FLAG_TXURNINT_ENABLE
= 0x0008,
594 TXQ_FLAG_BACKOFF_DISABLE
= 0x0010,
595 TXQ_FLAG_COMPRESSION_ENABLE
= 0x0020,
596 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE
= 0x0040,
597 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE
= 0x0080,
600 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
601 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
603 #define ATH9K_DECOMP_MASK_SIZE 128
604 #define ATH9K_READY_TIME_LO_BOUND 50
605 #define ATH9K_READY_TIME_HI_BOUND 96
607 enum ath9k_pkt_type
{
608 ATH9K_PKT_TYPE_NORMAL
= 0,
610 ATH9K_PKT_TYPE_PSPOLL
,
611 ATH9K_PKT_TYPE_BEACON
,
612 ATH9K_PKT_TYPE_PROBE_RESP
,
613 ATH9K_PKT_TYPE_CHIRP
,
614 ATH9K_PKT_TYPE_GRP_POLL
,
617 struct ath9k_tx_queue_info
{
619 enum ath9k_tx_queue tqi_type
;
620 enum ath9k_tx_queue_subtype tqi_subtype
;
621 enum ath9k_tx_queue_flags tqi_qflags
;
629 u32 tqi_cbrOverflowLimit
;
636 enum ath9k_rx_filter
{
637 ATH9K_RX_FILTER_UCAST
= 0x00000001,
638 ATH9K_RX_FILTER_MCAST
= 0x00000002,
639 ATH9K_RX_FILTER_BCAST
= 0x00000004,
640 ATH9K_RX_FILTER_CONTROL
= 0x00000008,
641 ATH9K_RX_FILTER_BEACON
= 0x00000010,
642 ATH9K_RX_FILTER_PROM
= 0x00000020,
643 ATH9K_RX_FILTER_PROBEREQ
= 0x00000080,
644 ATH9K_RX_FILTER_PHYERR
= 0x00000100,
645 ATH9K_RX_FILTER_MYBEACON
= 0x00000200,
646 ATH9K_RX_FILTER_COMP_BAR
= 0x00000400,
647 ATH9K_RX_FILTER_PSPOLL
= 0x00004000,
648 ATH9K_RX_FILTER_PHYRADAR
= 0x00002000,
649 ATH9K_RX_FILTER_MCAST_BCAST_ALL
= 0x00008000,
652 #define ATH9K_RATESERIES_RTS_CTS 0x0001
653 #define ATH9K_RATESERIES_2040 0x0002
654 #define ATH9K_RATESERIES_HALFGI 0x0004
656 struct ath9k_11n_rate_series
{
664 struct ath9k_keyval
{
668 u8 kv_val
[16]; /* TK */
669 u8 kv_mic
[8]; /* Michael MIC key */
670 u8 kv_txmic
[8]; /* Michael MIC TX key (used only if the hardware
671 * supports both MIC keys in the same key cache entry;
672 * in that case, kv_mic is the RX key) */
675 enum ath9k_key_type
{
676 ATH9K_KEY_TYPE_CLEAR
,
683 ATH9K_CIPHER_WEP
= 0,
684 ATH9K_CIPHER_AES_OCB
= 1,
685 ATH9K_CIPHER_AES_CCM
= 2,
686 ATH9K_CIPHER_CKIP
= 3,
687 ATH9K_CIPHER_TKIP
= 4,
688 ATH9K_CIPHER_CLR
= 5,
689 ATH9K_CIPHER_MIC
= 127
693 struct ath9k_channel
;
695 u32
ath9k_hw_gettxbuf(struct ath_hw
*ah
, u32 q
);
696 void ath9k_hw_puttxbuf(struct ath_hw
*ah
, u32 q
, u32 txdp
);
697 void ath9k_hw_txstart(struct ath_hw
*ah
, u32 q
);
698 u32
ath9k_hw_numtxpending(struct ath_hw
*ah
, u32 q
);
699 bool ath9k_hw_updatetxtriglevel(struct ath_hw
*ah
, bool bIncTrigLevel
);
700 bool ath9k_hw_stoptxdma(struct ath_hw
*ah
, u32 q
);
701 void ath9k_hw_filltxdesc(struct ath_hw
*ah
, struct ath_desc
*ds
,
702 u32 segLen
, bool firstSeg
,
703 bool lastSeg
, const struct ath_desc
*ds0
);
704 void ath9k_hw_cleartxdesc(struct ath_hw
*ah
, struct ath_desc
*ds
);
705 int ath9k_hw_txprocdesc(struct ath_hw
*ah
, struct ath_desc
*ds
);
706 void ath9k_hw_set11n_txdesc(struct ath_hw
*ah
, struct ath_desc
*ds
,
707 u32 pktLen
, enum ath9k_pkt_type type
, u32 txPower
,
708 u32 keyIx
, enum ath9k_key_type keyType
, u32 flags
);
709 void ath9k_hw_set11n_ratescenario(struct ath_hw
*ah
, struct ath_desc
*ds
,
710 struct ath_desc
*lastds
,
711 u32 durUpdateEn
, u32 rtsctsRate
,
713 struct ath9k_11n_rate_series series
[],
714 u32 nseries
, u32 flags
);
715 void ath9k_hw_set11n_aggr_first(struct ath_hw
*ah
, struct ath_desc
*ds
,
717 void ath9k_hw_set11n_aggr_middle(struct ath_hw
*ah
, struct ath_desc
*ds
,
719 void ath9k_hw_set11n_aggr_last(struct ath_hw
*ah
, struct ath_desc
*ds
);
720 void ath9k_hw_clr11n_aggr(struct ath_hw
*ah
, struct ath_desc
*ds
);
721 void ath9k_hw_set11n_burstduration(struct ath_hw
*ah
, struct ath_desc
*ds
,
723 void ath9k_hw_set11n_virtualmorefrag(struct ath_hw
*ah
, struct ath_desc
*ds
,
725 void ath9k_hw_gettxintrtxqs(struct ath_hw
*ah
, u32
*txqs
);
726 bool ath9k_hw_set_txq_props(struct ath_hw
*ah
, int q
,
727 const struct ath9k_tx_queue_info
*qinfo
);
728 bool ath9k_hw_get_txq_props(struct ath_hw
*ah
, int q
,
729 struct ath9k_tx_queue_info
*qinfo
);
730 int ath9k_hw_setuptxqueue(struct ath_hw
*ah
, enum ath9k_tx_queue type
,
731 const struct ath9k_tx_queue_info
*qinfo
);
732 bool ath9k_hw_releasetxqueue(struct ath_hw
*ah
, u32 q
);
733 bool ath9k_hw_resettxqueue(struct ath_hw
*ah
, u32 q
);
734 int ath9k_hw_rxprocdesc(struct ath_hw
*ah
, struct ath_desc
*ds
,
735 u32 pa
, struct ath_desc
*nds
, u64 tsf
);
736 void ath9k_hw_setuprxdesc(struct ath_hw
*ah
, struct ath_desc
*ds
,
737 u32 size
, u32 flags
);
738 bool ath9k_hw_setrxabort(struct ath_hw
*ah
, bool set
);
739 void ath9k_hw_putrxbuf(struct ath_hw
*ah
, u32 rxdp
);
740 void ath9k_hw_rxena(struct ath_hw
*ah
);
741 void ath9k_hw_startpcureceive(struct ath_hw
*ah
);
742 void ath9k_hw_stoppcurecv(struct ath_hw
*ah
);
743 bool ath9k_hw_stopdmarecv(struct ath_hw
*ah
);
744 int ath9k_hw_beaconq_setup(struct ath_hw
*ah
);