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ath9k: Fix p2p address management
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23 {
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55 }
56
57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
58 {
59 bool pending = false;
60
61 spin_lock_bh(&txq->axq_lock);
62
63 if (txq->axq_depth)
64 pending = true;
65
66 if (txq->mac80211_qnum >= 0) {
67 struct list_head *list;
68
69 list = &sc->cur_chan->acq[txq->mac80211_qnum];
70 if (!list_empty(list))
71 pending = true;
72 }
73 spin_unlock_bh(&txq->axq_lock);
74 return pending;
75 }
76
77 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
78 {
79 unsigned long flags;
80 bool ret;
81
82 spin_lock_irqsave(&sc->sc_pm_lock, flags);
83 ret = ath9k_hw_setpower(sc->sc_ah, mode);
84 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
85
86 return ret;
87 }
88
89 void ath_ps_full_sleep(unsigned long data)
90 {
91 struct ath_softc *sc = (struct ath_softc *) data;
92 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
93 bool reset;
94
95 spin_lock(&common->cc_lock);
96 ath_hw_cycle_counters_update(common);
97 spin_unlock(&common->cc_lock);
98
99 ath9k_hw_setrxabort(sc->sc_ah, 1);
100 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
101
102 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
103 }
104
105 void ath9k_ps_wakeup(struct ath_softc *sc)
106 {
107 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
108 unsigned long flags;
109 enum ath9k_power_mode power_mode;
110
111 spin_lock_irqsave(&sc->sc_pm_lock, flags);
112 if (++sc->ps_usecount != 1)
113 goto unlock;
114
115 del_timer_sync(&sc->sleep_timer);
116 power_mode = sc->sc_ah->power_mode;
117 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
118
119 /*
120 * While the hardware is asleep, the cycle counters contain no
121 * useful data. Better clear them now so that they don't mess up
122 * survey data results.
123 */
124 if (power_mode != ATH9K_PM_AWAKE) {
125 spin_lock(&common->cc_lock);
126 ath_hw_cycle_counters_update(common);
127 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
128 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
129 spin_unlock(&common->cc_lock);
130 }
131
132 unlock:
133 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
134 }
135
136 void ath9k_ps_restore(struct ath_softc *sc)
137 {
138 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
139 enum ath9k_power_mode mode;
140 unsigned long flags;
141
142 spin_lock_irqsave(&sc->sc_pm_lock, flags);
143 if (--sc->ps_usecount != 0)
144 goto unlock;
145
146 if (sc->ps_idle) {
147 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
148 goto unlock;
149 }
150
151 if (sc->ps_enabled &&
152 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
153 PS_WAIT_FOR_CAB |
154 PS_WAIT_FOR_PSPOLL_DATA |
155 PS_WAIT_FOR_TX_ACK |
156 PS_WAIT_FOR_ANI))) {
157 mode = ATH9K_PM_NETWORK_SLEEP;
158 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
159 ath9k_btcoex_stop_gen_timer(sc);
160 } else {
161 goto unlock;
162 }
163
164 spin_lock(&common->cc_lock);
165 ath_hw_cycle_counters_update(common);
166 spin_unlock(&common->cc_lock);
167
168 ath9k_hw_setpower(sc->sc_ah, mode);
169
170 unlock:
171 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
172 }
173
174 static void __ath_cancel_work(struct ath_softc *sc)
175 {
176 cancel_work_sync(&sc->paprd_work);
177 cancel_delayed_work_sync(&sc->tx_complete_work);
178 cancel_delayed_work_sync(&sc->hw_pll_work);
179
180 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
181 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
182 cancel_work_sync(&sc->mci_work);
183 #endif
184 }
185
186 void ath_cancel_work(struct ath_softc *sc)
187 {
188 __ath_cancel_work(sc);
189 cancel_work_sync(&sc->hw_reset_work);
190 }
191
192 void ath_restart_work(struct ath_softc *sc)
193 {
194 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
195
196 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
197 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
198 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
199
200 ath_start_ani(sc);
201 }
202
203 static bool ath_prepare_reset(struct ath_softc *sc)
204 {
205 struct ath_hw *ah = sc->sc_ah;
206 bool ret = true;
207
208 ieee80211_stop_queues(sc->hw);
209 ath_stop_ani(sc);
210 ath9k_hw_disable_interrupts(ah);
211
212 if (!ath_drain_all_txq(sc))
213 ret = false;
214
215 if (!ath_stoprecv(sc))
216 ret = false;
217
218 return ret;
219 }
220
221 static bool ath_complete_reset(struct ath_softc *sc, bool start)
222 {
223 struct ath_hw *ah = sc->sc_ah;
224 struct ath_common *common = ath9k_hw_common(ah);
225 unsigned long flags;
226
227 ath9k_calculate_summary_state(sc, sc->cur_chan);
228 ath_startrecv(sc);
229 ath9k_cmn_update_txpow(ah, sc->curtxpow,
230 sc->cur_chan->txpower, &sc->curtxpow);
231 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
232
233 if (!sc->cur_chan->offchannel && start) {
234 /* restore per chanctx TSF timer */
235 if (sc->cur_chan->tsf_val) {
236 u32 offset;
237
238 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
239 NULL);
240 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
241 }
242
243
244 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
245 goto work;
246
247 if (ah->opmode == NL80211_IFTYPE_STATION &&
248 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
249 spin_lock_irqsave(&sc->sc_pm_lock, flags);
250 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
251 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
252 } else {
253 ath9k_set_beacon(sc);
254 }
255 work:
256 ath_restart_work(sc);
257 ath_txq_schedule_all(sc);
258 }
259
260 sc->gtt_cnt = 0;
261
262 ath9k_hw_set_interrupts(ah);
263 ath9k_hw_enable_interrupts(ah);
264
265 if (!ath9k_is_chanctx_enabled())
266 ieee80211_wake_queues(sc->hw);
267 else
268 ath9k_chanctx_wake_queues(sc);
269
270 ath9k_p2p_ps_timer(sc);
271
272 return true;
273 }
274
275 int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
276 {
277 struct ath_hw *ah = sc->sc_ah;
278 struct ath_common *common = ath9k_hw_common(ah);
279 struct ath9k_hw_cal_data *caldata = NULL;
280 bool fastcc = true;
281 int r;
282
283 __ath_cancel_work(sc);
284
285 tasklet_disable(&sc->intr_tq);
286 spin_lock_bh(&sc->sc_pcu_lock);
287
288 if (!sc->cur_chan->offchannel) {
289 fastcc = false;
290 caldata = &sc->cur_chan->caldata;
291 }
292
293 if (!hchan) {
294 fastcc = false;
295 hchan = ah->curchan;
296 }
297
298 if (!ath_prepare_reset(sc))
299 fastcc = false;
300
301 if (ath9k_is_chanctx_enabled())
302 fastcc = false;
303
304 spin_lock_bh(&sc->chan_lock);
305 sc->cur_chandef = sc->cur_chan->chandef;
306 spin_unlock_bh(&sc->chan_lock);
307
308 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
309 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
310
311 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
312 if (r) {
313 ath_err(common,
314 "Unable to reset channel, reset status %d\n", r);
315
316 ath9k_hw_enable_interrupts(ah);
317 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
318
319 goto out;
320 }
321
322 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
323 sc->cur_chan->offchannel)
324 ath9k_mci_set_txpower(sc, true, false);
325
326 if (!ath_complete_reset(sc, true))
327 r = -EIO;
328
329 out:
330 spin_unlock_bh(&sc->sc_pcu_lock);
331 tasklet_enable(&sc->intr_tq);
332
333 return r;
334 }
335
336 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
337 struct ieee80211_vif *vif)
338 {
339 struct ath_node *an;
340 an = (struct ath_node *)sta->drv_priv;
341
342 an->sc = sc;
343 an->sta = sta;
344 an->vif = vif;
345 memset(&an->key_idx, 0, sizeof(an->key_idx));
346
347 ath_tx_node_init(sc, an);
348
349 ath_dynack_node_init(sc->sc_ah, an);
350 }
351
352 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
353 {
354 struct ath_node *an = (struct ath_node *)sta->drv_priv;
355 ath_tx_node_cleanup(sc, an);
356
357 ath_dynack_node_deinit(sc->sc_ah, an);
358 }
359
360 void ath9k_tasklet(unsigned long data)
361 {
362 struct ath_softc *sc = (struct ath_softc *)data;
363 struct ath_hw *ah = sc->sc_ah;
364 struct ath_common *common = ath9k_hw_common(ah);
365 enum ath_reset_type type;
366 unsigned long flags;
367 u32 status = sc->intrstatus;
368 u32 rxmask;
369
370 ath9k_ps_wakeup(sc);
371 spin_lock(&sc->sc_pcu_lock);
372
373 if (status & ATH9K_INT_FATAL) {
374 type = RESET_TYPE_FATAL_INT;
375 ath9k_queue_reset(sc, type);
376
377 /*
378 * Increment the ref. counter here so that
379 * interrupts are enabled in the reset routine.
380 */
381 atomic_inc(&ah->intr_ref_cnt);
382 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
383 goto out;
384 }
385
386 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
387 (status & ATH9K_INT_BB_WATCHDOG)) {
388 spin_lock(&common->cc_lock);
389 ath_hw_cycle_counters_update(common);
390 ar9003_hw_bb_watchdog_dbg_info(ah);
391 spin_unlock(&common->cc_lock);
392
393 if (ar9003_hw_bb_watchdog_check(ah)) {
394 type = RESET_TYPE_BB_WATCHDOG;
395 ath9k_queue_reset(sc, type);
396
397 /*
398 * Increment the ref. counter here so that
399 * interrupts are enabled in the reset routine.
400 */
401 atomic_inc(&ah->intr_ref_cnt);
402 ath_dbg(common, RESET,
403 "BB_WATCHDOG: Skipping interrupts\n");
404 goto out;
405 }
406 }
407
408 if (status & ATH9K_INT_GTT) {
409 sc->gtt_cnt++;
410
411 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
412 type = RESET_TYPE_TX_GTT;
413 ath9k_queue_reset(sc, type);
414 atomic_inc(&ah->intr_ref_cnt);
415 ath_dbg(common, RESET,
416 "GTT: Skipping interrupts\n");
417 goto out;
418 }
419 }
420
421 spin_lock_irqsave(&sc->sc_pm_lock, flags);
422 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
423 /*
424 * TSF sync does not look correct; remain awake to sync with
425 * the next Beacon.
426 */
427 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
428 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
429 }
430 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
431
432 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
433 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
434 ATH9K_INT_RXORN);
435 else
436 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
437
438 if (status & rxmask) {
439 /* Check for high priority Rx first */
440 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
441 (status & ATH9K_INT_RXHP))
442 ath_rx_tasklet(sc, 0, true);
443
444 ath_rx_tasklet(sc, 0, false);
445 }
446
447 if (status & ATH9K_INT_TX) {
448 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
449 /*
450 * For EDMA chips, TX completion is enabled for the
451 * beacon queue, so if a beacon has been transmitted
452 * successfully after a GTT interrupt, the GTT counter
453 * gets reset to zero here.
454 */
455 sc->gtt_cnt = 0;
456
457 ath_tx_edma_tasklet(sc);
458 } else {
459 ath_tx_tasklet(sc);
460 }
461
462 wake_up(&sc->tx_wait);
463 }
464
465 if (status & ATH9K_INT_GENTIMER)
466 ath_gen_timer_isr(sc->sc_ah);
467
468 ath9k_btcoex_handle_interrupt(sc, status);
469
470 /* re-enable hardware interrupt */
471 ath9k_hw_enable_interrupts(ah);
472 out:
473 spin_unlock(&sc->sc_pcu_lock);
474 ath9k_ps_restore(sc);
475 }
476
477 irqreturn_t ath_isr(int irq, void *dev)
478 {
479 #define SCHED_INTR ( \
480 ATH9K_INT_FATAL | \
481 ATH9K_INT_BB_WATCHDOG | \
482 ATH9K_INT_RXORN | \
483 ATH9K_INT_RXEOL | \
484 ATH9K_INT_RX | \
485 ATH9K_INT_RXLP | \
486 ATH9K_INT_RXHP | \
487 ATH9K_INT_TX | \
488 ATH9K_INT_BMISS | \
489 ATH9K_INT_CST | \
490 ATH9K_INT_GTT | \
491 ATH9K_INT_TSFOOR | \
492 ATH9K_INT_GENTIMER | \
493 ATH9K_INT_MCI)
494
495 struct ath_softc *sc = dev;
496 struct ath_hw *ah = sc->sc_ah;
497 struct ath_common *common = ath9k_hw_common(ah);
498 enum ath9k_int status;
499 u32 sync_cause = 0;
500 bool sched = false;
501
502 /*
503 * The hardware is not ready/present, don't
504 * touch anything. Note this can happen early
505 * on if the IRQ is shared.
506 */
507 if (test_bit(ATH_OP_INVALID, &common->op_flags))
508 return IRQ_NONE;
509
510 /* shared irq, not for us */
511
512 if (!ath9k_hw_intrpend(ah))
513 return IRQ_NONE;
514
515 if (test_bit(ATH_OP_HW_RESET, &common->op_flags)) {
516 ath9k_hw_kill_interrupts(ah);
517 return IRQ_HANDLED;
518 }
519
520 /*
521 * Figure out the reason(s) for the interrupt. Note
522 * that the hal returns a pseudo-ISR that may include
523 * bits we haven't explicitly enabled so we mask the
524 * value to insure we only process bits we requested.
525 */
526 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
527 ath9k_debug_sync_cause(sc, sync_cause);
528 status &= ah->imask; /* discard unasked-for bits */
529
530 /*
531 * If there are no status bits set, then this interrupt was not
532 * for me (should have been caught above).
533 */
534 if (!status)
535 return IRQ_NONE;
536
537 /* Cache the status */
538 sc->intrstatus = status;
539
540 if (status & SCHED_INTR)
541 sched = true;
542
543 /*
544 * If a FATAL or RXORN interrupt is received, we have to reset the
545 * chip immediately.
546 */
547 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
548 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
549 goto chip_reset;
550
551 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
552 (status & ATH9K_INT_BB_WATCHDOG))
553 goto chip_reset;
554
555 #ifdef CONFIG_ATH9K_WOW
556 if (status & ATH9K_INT_BMISS) {
557 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
558 atomic_inc(&sc->wow_got_bmiss_intr);
559 atomic_dec(&sc->wow_sleep_proc_intr);
560 }
561 }
562 #endif
563
564 if (status & ATH9K_INT_SWBA)
565 tasklet_schedule(&sc->bcon_tasklet);
566
567 if (status & ATH9K_INT_TXURN)
568 ath9k_hw_updatetxtriglevel(ah, true);
569
570 if (status & ATH9K_INT_RXEOL) {
571 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
572 ath9k_hw_set_interrupts(ah);
573 }
574
575 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
576 if (status & ATH9K_INT_TIM_TIMER) {
577 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
578 goto chip_reset;
579 /* Clear RxAbort bit so that we can
580 * receive frames */
581 ath9k_setpower(sc, ATH9K_PM_AWAKE);
582 spin_lock(&sc->sc_pm_lock);
583 ath9k_hw_setrxabort(sc->sc_ah, 0);
584 sc->ps_flags |= PS_WAIT_FOR_BEACON;
585 spin_unlock(&sc->sc_pm_lock);
586 }
587
588 chip_reset:
589
590 ath_debug_stat_interrupt(sc, status);
591
592 if (sched) {
593 /* turn off every interrupt */
594 ath9k_hw_disable_interrupts(ah);
595 tasklet_schedule(&sc->intr_tq);
596 }
597
598 return IRQ_HANDLED;
599
600 #undef SCHED_INTR
601 }
602
603 int ath_reset(struct ath_softc *sc)
604 {
605 int r;
606
607 ath9k_ps_wakeup(sc);
608 r = ath_reset_internal(sc, NULL);
609 ath9k_ps_restore(sc);
610
611 return r;
612 }
613
614 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
615 {
616 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
617 #ifdef CONFIG_ATH9K_DEBUGFS
618 RESET_STAT_INC(sc, type);
619 #endif
620 set_bit(ATH_OP_HW_RESET, &common->op_flags);
621 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
622 }
623
624 void ath_reset_work(struct work_struct *work)
625 {
626 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
627
628 ath_reset(sc);
629 }
630
631 /**********************/
632 /* mac80211 callbacks */
633 /**********************/
634
635 static int ath9k_start(struct ieee80211_hw *hw)
636 {
637 struct ath_softc *sc = hw->priv;
638 struct ath_hw *ah = sc->sc_ah;
639 struct ath_common *common = ath9k_hw_common(ah);
640 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
641 struct ath_chanctx *ctx = sc->cur_chan;
642 struct ath9k_channel *init_channel;
643 int r;
644
645 ath_dbg(common, CONFIG,
646 "Starting driver with initial channel: %d MHz\n",
647 curchan->center_freq);
648
649 ath9k_ps_wakeup(sc);
650 mutex_lock(&sc->mutex);
651
652 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
653 sc->cur_chandef = hw->conf.chandef;
654
655 /* Reset SERDES registers */
656 ath9k_hw_configpcipowersave(ah, false);
657
658 /*
659 * The basic interface to setting the hardware in a good
660 * state is ``reset''. On return the hardware is known to
661 * be powered up and with interrupts disabled. This must
662 * be followed by initialization of the appropriate bits
663 * and then setup of the interrupt mask.
664 */
665 spin_lock_bh(&sc->sc_pcu_lock);
666
667 atomic_set(&ah->intr_ref_cnt, -1);
668
669 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
670 if (r) {
671 ath_err(common,
672 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
673 r, curchan->center_freq);
674 ah->reset_power_on = false;
675 }
676
677 /* Setup our intr mask. */
678 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
679 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
680 ATH9K_INT_GLOBAL;
681
682 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
683 ah->imask |= ATH9K_INT_RXHP |
684 ATH9K_INT_RXLP;
685 else
686 ah->imask |= ATH9K_INT_RX;
687
688 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
689 ah->imask |= ATH9K_INT_BB_WATCHDOG;
690
691 /*
692 * Enable GTT interrupts only for AR9003/AR9004 chips
693 * for now.
694 */
695 if (AR_SREV_9300_20_OR_LATER(ah))
696 ah->imask |= ATH9K_INT_GTT;
697
698 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
699 ah->imask |= ATH9K_INT_CST;
700
701 ath_mci_enable(sc);
702
703 clear_bit(ATH_OP_INVALID, &common->op_flags);
704 sc->sc_ah->is_monitoring = false;
705
706 if (!ath_complete_reset(sc, false))
707 ah->reset_power_on = false;
708
709 if (ah->led_pin >= 0) {
710 ath9k_hw_cfg_output(ah, ah->led_pin,
711 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
712 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
713 }
714
715 /*
716 * Reset key cache to sane defaults (all entries cleared) instead of
717 * semi-random values after suspend/resume.
718 */
719 ath9k_cmn_init_crypto(sc->sc_ah);
720
721 ath9k_hw_reset_tsf(ah);
722
723 spin_unlock_bh(&sc->sc_pcu_lock);
724
725 mutex_unlock(&sc->mutex);
726
727 ath9k_ps_restore(sc);
728
729 return 0;
730 }
731
732 static void ath9k_tx(struct ieee80211_hw *hw,
733 struct ieee80211_tx_control *control,
734 struct sk_buff *skb)
735 {
736 struct ath_softc *sc = hw->priv;
737 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
738 struct ath_tx_control txctl;
739 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
740 unsigned long flags;
741
742 if (sc->ps_enabled) {
743 /*
744 * mac80211 does not set PM field for normal data frames, so we
745 * need to update that based on the current PS mode.
746 */
747 if (ieee80211_is_data(hdr->frame_control) &&
748 !ieee80211_is_nullfunc(hdr->frame_control) &&
749 !ieee80211_has_pm(hdr->frame_control)) {
750 ath_dbg(common, PS,
751 "Add PM=1 for a TX frame while in PS mode\n");
752 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
753 }
754 }
755
756 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
757 /*
758 * We are using PS-Poll and mac80211 can request TX while in
759 * power save mode. Need to wake up hardware for the TX to be
760 * completed and if needed, also for RX of buffered frames.
761 */
762 ath9k_ps_wakeup(sc);
763 spin_lock_irqsave(&sc->sc_pm_lock, flags);
764 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
765 ath9k_hw_setrxabort(sc->sc_ah, 0);
766 if (ieee80211_is_pspoll(hdr->frame_control)) {
767 ath_dbg(common, PS,
768 "Sending PS-Poll to pick a buffered frame\n");
769 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
770 } else {
771 ath_dbg(common, PS, "Wake up to complete TX\n");
772 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
773 }
774 /*
775 * The actual restore operation will happen only after
776 * the ps_flags bit is cleared. We are just dropping
777 * the ps_usecount here.
778 */
779 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
780 ath9k_ps_restore(sc);
781 }
782
783 /*
784 * Cannot tx while the hardware is in full sleep, it first needs a full
785 * chip reset to recover from that
786 */
787 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
788 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
789 goto exit;
790 }
791
792 memset(&txctl, 0, sizeof(struct ath_tx_control));
793 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
794 txctl.sta = control->sta;
795
796 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
797
798 if (ath_tx_start(hw, skb, &txctl) != 0) {
799 ath_dbg(common, XMIT, "TX failed\n");
800 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
801 goto exit;
802 }
803
804 return;
805 exit:
806 ieee80211_free_txskb(hw, skb);
807 }
808
809 static void ath9k_stop(struct ieee80211_hw *hw)
810 {
811 struct ath_softc *sc = hw->priv;
812 struct ath_hw *ah = sc->sc_ah;
813 struct ath_common *common = ath9k_hw_common(ah);
814 bool prev_idle;
815
816 ath9k_deinit_channel_context(sc);
817
818 mutex_lock(&sc->mutex);
819
820 ath_cancel_work(sc);
821
822 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
823 ath_dbg(common, ANY, "Device not present\n");
824 mutex_unlock(&sc->mutex);
825 return;
826 }
827
828 /* Ensure HW is awake when we try to shut it down. */
829 ath9k_ps_wakeup(sc);
830
831 spin_lock_bh(&sc->sc_pcu_lock);
832
833 /* prevent tasklets to enable interrupts once we disable them */
834 ah->imask &= ~ATH9K_INT_GLOBAL;
835
836 /* make sure h/w will not generate any interrupt
837 * before setting the invalid flag. */
838 ath9k_hw_disable_interrupts(ah);
839
840 spin_unlock_bh(&sc->sc_pcu_lock);
841
842 /* we can now sync irq and kill any running tasklets, since we already
843 * disabled interrupts and not holding a spin lock */
844 synchronize_irq(sc->irq);
845 tasklet_kill(&sc->intr_tq);
846 tasklet_kill(&sc->bcon_tasklet);
847
848 prev_idle = sc->ps_idle;
849 sc->ps_idle = true;
850
851 spin_lock_bh(&sc->sc_pcu_lock);
852
853 if (ah->led_pin >= 0) {
854 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
855 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
856 }
857
858 ath_prepare_reset(sc);
859
860 if (sc->rx.frag) {
861 dev_kfree_skb_any(sc->rx.frag);
862 sc->rx.frag = NULL;
863 }
864
865 if (!ah->curchan)
866 ah->curchan = ath9k_cmn_get_channel(hw, ah,
867 &sc->cur_chan->chandef);
868
869 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
870 ath9k_hw_phy_disable(ah);
871
872 ath9k_hw_configpcipowersave(ah, true);
873
874 spin_unlock_bh(&sc->sc_pcu_lock);
875
876 ath9k_ps_restore(sc);
877
878 set_bit(ATH_OP_INVALID, &common->op_flags);
879 sc->ps_idle = prev_idle;
880
881 mutex_unlock(&sc->mutex);
882
883 ath_dbg(common, CONFIG, "Driver halt\n");
884 }
885
886 static bool ath9k_uses_beacons(int type)
887 {
888 switch (type) {
889 case NL80211_IFTYPE_AP:
890 case NL80211_IFTYPE_ADHOC:
891 case NL80211_IFTYPE_MESH_POINT:
892 return true;
893 default:
894 return false;
895 }
896 }
897
898 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
899 u8 *mac, struct ieee80211_vif *vif)
900 {
901 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
902 int i;
903
904 if (iter_data->has_hw_macaddr) {
905 for (i = 0; i < ETH_ALEN; i++)
906 iter_data->mask[i] &=
907 ~(iter_data->hw_macaddr[i] ^ mac[i]);
908 } else {
909 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
910 iter_data->has_hw_macaddr = true;
911 }
912
913 if (!vif->bss_conf.use_short_slot)
914 iter_data->slottime = ATH9K_SLOT_TIME_20;
915
916 switch (vif->type) {
917 case NL80211_IFTYPE_AP:
918 iter_data->naps++;
919 break;
920 case NL80211_IFTYPE_STATION:
921 iter_data->nstations++;
922 if (avp->assoc && !iter_data->primary_sta)
923 iter_data->primary_sta = vif;
924 break;
925 case NL80211_IFTYPE_ADHOC:
926 iter_data->nadhocs++;
927 if (vif->bss_conf.enable_beacon)
928 iter_data->beacons = true;
929 break;
930 case NL80211_IFTYPE_MESH_POINT:
931 iter_data->nmeshes++;
932 if (vif->bss_conf.enable_beacon)
933 iter_data->beacons = true;
934 break;
935 case NL80211_IFTYPE_WDS:
936 iter_data->nwds++;
937 break;
938 default:
939 break;
940 }
941 }
942
943 static void ath9k_update_bssid_mask(struct ath_softc *sc,
944 struct ath_chanctx *ctx,
945 struct ath9k_vif_iter_data *iter_data)
946 {
947 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
948 struct ath_vif *avp;
949 int i;
950
951 if (!ath9k_is_chanctx_enabled())
952 return;
953
954 list_for_each_entry(avp, &ctx->vifs, list) {
955 if (ctx->nvifs_assigned != 1)
956 continue;
957
958 if (!avp->vif->p2p || !iter_data->has_hw_macaddr)
959 continue;
960
961 ether_addr_copy(common->curbssid, avp->bssid);
962
963 /* perm_addr will be used as the p2p device address. */
964 for (i = 0; i < ETH_ALEN; i++)
965 iter_data->mask[i] &=
966 ~(iter_data->hw_macaddr[i] ^
967 sc->hw->wiphy->perm_addr[i]);
968 }
969 }
970
971 /* Called with sc->mutex held. */
972 void ath9k_calculate_iter_data(struct ath_softc *sc,
973 struct ath_chanctx *ctx,
974 struct ath9k_vif_iter_data *iter_data)
975 {
976 struct ath_vif *avp;
977
978 /*
979 * Pick the MAC address of the first interface as the new hardware
980 * MAC address. The hardware will use it together with the BSSID mask
981 * when matching addresses.
982 */
983 memset(iter_data, 0, sizeof(*iter_data));
984 memset(&iter_data->mask, 0xff, ETH_ALEN);
985 iter_data->slottime = ATH9K_SLOT_TIME_9;
986
987 list_for_each_entry(avp, &ctx->vifs, list)
988 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
989
990 ath9k_update_bssid_mask(sc, ctx, iter_data);
991 }
992
993 static void ath9k_set_assoc_state(struct ath_softc *sc,
994 struct ieee80211_vif *vif, bool changed)
995 {
996 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
997 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
998 unsigned long flags;
999
1000 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1001
1002 ether_addr_copy(common->curbssid, avp->bssid);
1003 common->curaid = avp->aid;
1004 ath9k_hw_write_associd(sc->sc_ah);
1005
1006 if (changed) {
1007 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1008 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1009
1010 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1011 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1012 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1013 }
1014
1015 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1016 ath9k_mci_update_wlan_channels(sc, false);
1017
1018 ath_dbg(common, CONFIG,
1019 "Primary Station interface: %pM, BSSID: %pM\n",
1020 vif->addr, common->curbssid);
1021 }
1022
1023 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1024 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1025 {
1026 struct ath_hw *ah = sc->sc_ah;
1027 struct ath_common *common = ath9k_hw_common(ah);
1028 struct ieee80211_vif *vif = NULL;
1029
1030 ath9k_ps_wakeup(sc);
1031
1032 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1033 vif = sc->offchannel.scan_vif;
1034 else
1035 vif = sc->offchannel.roc_vif;
1036
1037 if (WARN_ON(!vif))
1038 goto exit;
1039
1040 eth_zero_addr(common->curbssid);
1041 eth_broadcast_addr(common->bssidmask);
1042 ether_addr_copy(common->macaddr, vif->addr);
1043 common->curaid = 0;
1044 ah->opmode = vif->type;
1045 ah->imask &= ~ATH9K_INT_SWBA;
1046 ah->imask &= ~ATH9K_INT_TSFOOR;
1047 ah->slottime = ATH9K_SLOT_TIME_9;
1048
1049 ath_hw_setbssidmask(common);
1050 ath9k_hw_setopmode(ah);
1051 ath9k_hw_write_associd(sc->sc_ah);
1052 ath9k_hw_set_interrupts(ah);
1053 ath9k_hw_init_global_settings(ah);
1054
1055 exit:
1056 ath9k_ps_restore(sc);
1057 }
1058 #endif
1059
1060 /* Called with sc->mutex held. */
1061 void ath9k_calculate_summary_state(struct ath_softc *sc,
1062 struct ath_chanctx *ctx)
1063 {
1064 struct ath_hw *ah = sc->sc_ah;
1065 struct ath_common *common = ath9k_hw_common(ah);
1066 struct ath9k_vif_iter_data iter_data;
1067 struct ath_beacon_config *cur_conf;
1068
1069 ath_chanctx_check_active(sc, ctx);
1070
1071 if (ctx != sc->cur_chan)
1072 return;
1073
1074 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1075 if (ctx == &sc->offchannel.chan)
1076 return ath9k_set_offchannel_state(sc);
1077 #endif
1078
1079 ath9k_ps_wakeup(sc);
1080 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1081
1082 if (iter_data.has_hw_macaddr)
1083 ether_addr_copy(common->macaddr, iter_data.hw_macaddr);
1084
1085 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1086 ath_hw_setbssidmask(common);
1087
1088 if (iter_data.naps > 0) {
1089 cur_conf = &ctx->beacon;
1090 ath9k_hw_set_tsfadjust(ah, true);
1091 ah->opmode = NL80211_IFTYPE_AP;
1092 if (cur_conf->enable_beacon)
1093 iter_data.beacons = true;
1094 } else {
1095 ath9k_hw_set_tsfadjust(ah, false);
1096
1097 if (iter_data.nmeshes)
1098 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1099 else if (iter_data.nwds)
1100 ah->opmode = NL80211_IFTYPE_AP;
1101 else if (iter_data.nadhocs)
1102 ah->opmode = NL80211_IFTYPE_ADHOC;
1103 else
1104 ah->opmode = NL80211_IFTYPE_STATION;
1105 }
1106
1107 ath9k_hw_setopmode(ah);
1108
1109 ctx->switch_after_beacon = false;
1110 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1111 ah->imask |= ATH9K_INT_TSFOOR;
1112 else {
1113 ah->imask &= ~ATH9K_INT_TSFOOR;
1114 if (iter_data.naps == 1 && iter_data.beacons)
1115 ctx->switch_after_beacon = true;
1116 }
1117
1118 ah->imask &= ~ATH9K_INT_SWBA;
1119 if (ah->opmode == NL80211_IFTYPE_STATION) {
1120 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1121
1122 if (iter_data.primary_sta) {
1123 iter_data.beacons = true;
1124 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1125 changed);
1126 ctx->primary_sta = iter_data.primary_sta;
1127 } else {
1128 ctx->primary_sta = NULL;
1129 memset(common->curbssid, 0, ETH_ALEN);
1130 common->curaid = 0;
1131 ath9k_hw_write_associd(sc->sc_ah);
1132 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1133 ath9k_mci_update_wlan_channels(sc, true);
1134 }
1135 } else if (iter_data.beacons) {
1136 ah->imask |= ATH9K_INT_SWBA;
1137 }
1138 ath9k_hw_set_interrupts(ah);
1139
1140 if (iter_data.beacons)
1141 set_bit(ATH_OP_BEACONS, &common->op_flags);
1142 else
1143 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1144
1145 if (ah->slottime != iter_data.slottime) {
1146 ah->slottime = iter_data.slottime;
1147 ath9k_hw_init_global_settings(ah);
1148 }
1149
1150 if (iter_data.primary_sta)
1151 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1152 else
1153 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1154
1155 ath_dbg(common, CONFIG,
1156 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1157 common->macaddr, common->curbssid, common->bssidmask);
1158
1159 ath9k_ps_restore(sc);
1160 }
1161
1162 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1163 struct ieee80211_vif *vif)
1164 {
1165 int i;
1166
1167 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1168 vif->hw_queue[i] = i;
1169
1170 if (vif->type == NL80211_IFTYPE_AP)
1171 vif->cab_queue = hw->queues - 2;
1172 else
1173 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1174 }
1175
1176 static int ath9k_add_interface(struct ieee80211_hw *hw,
1177 struct ieee80211_vif *vif)
1178 {
1179 struct ath_softc *sc = hw->priv;
1180 struct ath_hw *ah = sc->sc_ah;
1181 struct ath_common *common = ath9k_hw_common(ah);
1182 struct ath_vif *avp = (void *)vif->drv_priv;
1183 struct ath_node *an = &avp->mcast_node;
1184
1185 mutex_lock(&sc->mutex);
1186
1187 if (config_enabled(CONFIG_ATH9K_TX99)) {
1188 if (sc->cur_chan->nvifs >= 1) {
1189 mutex_unlock(&sc->mutex);
1190 return -EOPNOTSUPP;
1191 }
1192 sc->tx99_vif = vif;
1193 }
1194
1195 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1196 sc->cur_chan->nvifs++;
1197
1198 if (ath9k_uses_beacons(vif->type))
1199 ath9k_beacon_assign_slot(sc, vif);
1200
1201 avp->vif = vif;
1202 if (!ath9k_is_chanctx_enabled()) {
1203 avp->chanctx = sc->cur_chan;
1204 list_add_tail(&avp->list, &avp->chanctx->vifs);
1205 }
1206
1207 ath9k_assign_hw_queues(hw, vif);
1208
1209 an->sc = sc;
1210 an->sta = NULL;
1211 an->vif = vif;
1212 an->no_ps_filter = true;
1213 ath_tx_node_init(sc, an);
1214
1215 mutex_unlock(&sc->mutex);
1216 return 0;
1217 }
1218
1219 static int ath9k_change_interface(struct ieee80211_hw *hw,
1220 struct ieee80211_vif *vif,
1221 enum nl80211_iftype new_type,
1222 bool p2p)
1223 {
1224 struct ath_softc *sc = hw->priv;
1225 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1226 struct ath_vif *avp = (void *)vif->drv_priv;
1227
1228 mutex_lock(&sc->mutex);
1229
1230 if (config_enabled(CONFIG_ATH9K_TX99)) {
1231 mutex_unlock(&sc->mutex);
1232 return -EOPNOTSUPP;
1233 }
1234
1235 ath_dbg(common, CONFIG, "Change Interface\n");
1236
1237 if (ath9k_uses_beacons(vif->type))
1238 ath9k_beacon_remove_slot(sc, vif);
1239
1240 vif->type = new_type;
1241 vif->p2p = p2p;
1242
1243 if (ath9k_uses_beacons(vif->type))
1244 ath9k_beacon_assign_slot(sc, vif);
1245
1246 ath9k_assign_hw_queues(hw, vif);
1247 ath9k_calculate_summary_state(sc, avp->chanctx);
1248
1249 mutex_unlock(&sc->mutex);
1250 return 0;
1251 }
1252
1253 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1254 struct ieee80211_vif *vif)
1255 {
1256 struct ath_softc *sc = hw->priv;
1257 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1258 struct ath_vif *avp = (void *)vif->drv_priv;
1259
1260 ath_dbg(common, CONFIG, "Detach Interface\n");
1261
1262 mutex_lock(&sc->mutex);
1263
1264 ath9k_p2p_remove_vif(sc, vif);
1265
1266 sc->cur_chan->nvifs--;
1267 sc->tx99_vif = NULL;
1268 if (!ath9k_is_chanctx_enabled())
1269 list_del(&avp->list);
1270
1271 if (ath9k_uses_beacons(vif->type))
1272 ath9k_beacon_remove_slot(sc, vif);
1273
1274 ath_tx_node_cleanup(sc, &avp->mcast_node);
1275
1276 mutex_unlock(&sc->mutex);
1277 }
1278
1279 static void ath9k_enable_ps(struct ath_softc *sc)
1280 {
1281 struct ath_hw *ah = sc->sc_ah;
1282 struct ath_common *common = ath9k_hw_common(ah);
1283
1284 if (config_enabled(CONFIG_ATH9K_TX99))
1285 return;
1286
1287 sc->ps_enabled = true;
1288 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1289 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1290 ah->imask |= ATH9K_INT_TIM_TIMER;
1291 ath9k_hw_set_interrupts(ah);
1292 }
1293 ath9k_hw_setrxabort(ah, 1);
1294 }
1295 ath_dbg(common, PS, "PowerSave enabled\n");
1296 }
1297
1298 static void ath9k_disable_ps(struct ath_softc *sc)
1299 {
1300 struct ath_hw *ah = sc->sc_ah;
1301 struct ath_common *common = ath9k_hw_common(ah);
1302
1303 if (config_enabled(CONFIG_ATH9K_TX99))
1304 return;
1305
1306 sc->ps_enabled = false;
1307 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1308 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1309 ath9k_hw_setrxabort(ah, 0);
1310 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1311 PS_WAIT_FOR_CAB |
1312 PS_WAIT_FOR_PSPOLL_DATA |
1313 PS_WAIT_FOR_TX_ACK);
1314 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1315 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1316 ath9k_hw_set_interrupts(ah);
1317 }
1318 }
1319 ath_dbg(common, PS, "PowerSave disabled\n");
1320 }
1321
1322 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
1323 {
1324 struct ath_softc *sc = hw->priv;
1325 struct ath_hw *ah = sc->sc_ah;
1326 struct ath_common *common = ath9k_hw_common(ah);
1327 u32 rxfilter;
1328
1329 if (config_enabled(CONFIG_ATH9K_TX99))
1330 return;
1331
1332 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1333 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1334 return;
1335 }
1336
1337 ath9k_ps_wakeup(sc);
1338 rxfilter = ath9k_hw_getrxfilter(ah);
1339 ath9k_hw_setrxfilter(ah, rxfilter |
1340 ATH9K_RX_FILTER_PHYRADAR |
1341 ATH9K_RX_FILTER_PHYERR);
1342
1343 /* TODO: usually this should not be neccesary, but for some reason
1344 * (or in some mode?) the trigger must be called after the
1345 * configuration, otherwise the register will have its values reset
1346 * (on my ar9220 to value 0x01002310)
1347 */
1348 ath9k_spectral_scan_config(hw, sc->spectral_mode);
1349 ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
1350 ath9k_ps_restore(sc);
1351 }
1352
1353 int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
1354 enum spectral_mode spectral_mode)
1355 {
1356 struct ath_softc *sc = hw->priv;
1357 struct ath_hw *ah = sc->sc_ah;
1358 struct ath_common *common = ath9k_hw_common(ah);
1359
1360 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1361 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1362 return -1;
1363 }
1364
1365 switch (spectral_mode) {
1366 case SPECTRAL_DISABLED:
1367 sc->spec_config.enabled = 0;
1368 break;
1369 case SPECTRAL_BACKGROUND:
1370 /* send endless samples.
1371 * TODO: is this really useful for "background"?
1372 */
1373 sc->spec_config.endless = 1;
1374 sc->spec_config.enabled = 1;
1375 break;
1376 case SPECTRAL_CHANSCAN:
1377 case SPECTRAL_MANUAL:
1378 sc->spec_config.endless = 0;
1379 sc->spec_config.enabled = 1;
1380 break;
1381 default:
1382 return -1;
1383 }
1384
1385 ath9k_ps_wakeup(sc);
1386 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
1387 ath9k_ps_restore(sc);
1388
1389 sc->spectral_mode = spectral_mode;
1390
1391 return 0;
1392 }
1393
1394 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1395 {
1396 struct ath_softc *sc = hw->priv;
1397 struct ath_hw *ah = sc->sc_ah;
1398 struct ath_common *common = ath9k_hw_common(ah);
1399 struct ieee80211_conf *conf = &hw->conf;
1400 struct ath_chanctx *ctx = sc->cur_chan;
1401
1402 ath9k_ps_wakeup(sc);
1403 mutex_lock(&sc->mutex);
1404
1405 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1406 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1407 if (sc->ps_idle) {
1408 ath_cancel_work(sc);
1409 ath9k_stop_btcoex(sc);
1410 } else {
1411 ath9k_start_btcoex(sc);
1412 /*
1413 * The chip needs a reset to properly wake up from
1414 * full sleep
1415 */
1416 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1417 }
1418 }
1419
1420 /*
1421 * We just prepare to enable PS. We have to wait until our AP has
1422 * ACK'd our null data frame to disable RX otherwise we'll ignore
1423 * those ACKs and end up retransmitting the same null data frames.
1424 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1425 */
1426 if (changed & IEEE80211_CONF_CHANGE_PS) {
1427 unsigned long flags;
1428 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1429 if (conf->flags & IEEE80211_CONF_PS)
1430 ath9k_enable_ps(sc);
1431 else
1432 ath9k_disable_ps(sc);
1433 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1434 }
1435
1436 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1437 if (conf->flags & IEEE80211_CONF_MONITOR) {
1438 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1439 sc->sc_ah->is_monitoring = true;
1440 } else {
1441 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1442 sc->sc_ah->is_monitoring = false;
1443 }
1444 }
1445
1446 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1447 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1448 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1449 }
1450
1451 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1452 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1453 sc->cur_chan->txpower = 2 * conf->power_level;
1454 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1455 sc->cur_chan->txpower, &sc->curtxpow);
1456 }
1457
1458 mutex_unlock(&sc->mutex);
1459 ath9k_ps_restore(sc);
1460
1461 return 0;
1462 }
1463
1464 #define SUPPORTED_FILTERS \
1465 (FIF_PROMISC_IN_BSS | \
1466 FIF_ALLMULTI | \
1467 FIF_CONTROL | \
1468 FIF_PSPOLL | \
1469 FIF_OTHER_BSS | \
1470 FIF_BCN_PRBRESP_PROMISC | \
1471 FIF_PROBE_REQ | \
1472 FIF_FCSFAIL)
1473
1474 /* FIXME: sc->sc_full_reset ? */
1475 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1476 unsigned int changed_flags,
1477 unsigned int *total_flags,
1478 u64 multicast)
1479 {
1480 struct ath_softc *sc = hw->priv;
1481 u32 rfilt;
1482
1483 changed_flags &= SUPPORTED_FILTERS;
1484 *total_flags &= SUPPORTED_FILTERS;
1485
1486 spin_lock_bh(&sc->chan_lock);
1487 sc->cur_chan->rxfilter = *total_flags;
1488 spin_unlock_bh(&sc->chan_lock);
1489
1490 ath9k_ps_wakeup(sc);
1491 rfilt = ath_calcrxfilter(sc);
1492 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1493 ath9k_ps_restore(sc);
1494
1495 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1496 rfilt);
1497 }
1498
1499 static int ath9k_sta_add(struct ieee80211_hw *hw,
1500 struct ieee80211_vif *vif,
1501 struct ieee80211_sta *sta)
1502 {
1503 struct ath_softc *sc = hw->priv;
1504 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1505 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1506 struct ieee80211_key_conf ps_key = { };
1507 int key;
1508
1509 ath_node_attach(sc, sta, vif);
1510
1511 if (vif->type != NL80211_IFTYPE_AP &&
1512 vif->type != NL80211_IFTYPE_AP_VLAN)
1513 return 0;
1514
1515 key = ath_key_config(common, vif, sta, &ps_key);
1516 if (key > 0) {
1517 an->ps_key = key;
1518 an->key_idx[0] = key;
1519 }
1520
1521 return 0;
1522 }
1523
1524 static void ath9k_del_ps_key(struct ath_softc *sc,
1525 struct ieee80211_vif *vif,
1526 struct ieee80211_sta *sta)
1527 {
1528 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1529 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1530 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1531
1532 if (!an->ps_key)
1533 return;
1534
1535 ath_key_delete(common, &ps_key);
1536 an->ps_key = 0;
1537 an->key_idx[0] = 0;
1538 }
1539
1540 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1541 struct ieee80211_vif *vif,
1542 struct ieee80211_sta *sta)
1543 {
1544 struct ath_softc *sc = hw->priv;
1545
1546 ath9k_del_ps_key(sc, vif, sta);
1547 ath_node_detach(sc, sta);
1548
1549 return 0;
1550 }
1551
1552 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1553 struct ath_node *an,
1554 bool set)
1555 {
1556 int i;
1557
1558 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1559 if (!an->key_idx[i])
1560 continue;
1561 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1562 }
1563 }
1564
1565 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1566 struct ieee80211_vif *vif,
1567 enum sta_notify_cmd cmd,
1568 struct ieee80211_sta *sta)
1569 {
1570 struct ath_softc *sc = hw->priv;
1571 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1572
1573 switch (cmd) {
1574 case STA_NOTIFY_SLEEP:
1575 an->sleeping = true;
1576 ath_tx_aggr_sleep(sta, sc, an);
1577 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1578 break;
1579 case STA_NOTIFY_AWAKE:
1580 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1581 an->sleeping = false;
1582 ath_tx_aggr_wakeup(sc, an);
1583 break;
1584 }
1585 }
1586
1587 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1588 struct ieee80211_vif *vif, u16 queue,
1589 const struct ieee80211_tx_queue_params *params)
1590 {
1591 struct ath_softc *sc = hw->priv;
1592 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1593 struct ath_txq *txq;
1594 struct ath9k_tx_queue_info qi;
1595 int ret = 0;
1596
1597 if (queue >= IEEE80211_NUM_ACS)
1598 return 0;
1599
1600 txq = sc->tx.txq_map[queue];
1601
1602 ath9k_ps_wakeup(sc);
1603 mutex_lock(&sc->mutex);
1604
1605 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1606
1607 qi.tqi_aifs = params->aifs;
1608 qi.tqi_cwmin = params->cw_min;
1609 qi.tqi_cwmax = params->cw_max;
1610 qi.tqi_burstTime = params->txop * 32;
1611
1612 ath_dbg(common, CONFIG,
1613 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1614 queue, txq->axq_qnum, params->aifs, params->cw_min,
1615 params->cw_max, params->txop);
1616
1617 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1618 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1619 if (ret)
1620 ath_err(common, "TXQ Update failed\n");
1621
1622 mutex_unlock(&sc->mutex);
1623 ath9k_ps_restore(sc);
1624
1625 return ret;
1626 }
1627
1628 static int ath9k_set_key(struct ieee80211_hw *hw,
1629 enum set_key_cmd cmd,
1630 struct ieee80211_vif *vif,
1631 struct ieee80211_sta *sta,
1632 struct ieee80211_key_conf *key)
1633 {
1634 struct ath_softc *sc = hw->priv;
1635 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1636 struct ath_node *an = NULL;
1637 int ret = 0, i;
1638
1639 if (ath9k_modparam_nohwcrypt)
1640 return -ENOSPC;
1641
1642 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1643 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1644 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1645 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1646 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1647 /*
1648 * For now, disable hw crypto for the RSN IBSS group keys. This
1649 * could be optimized in the future to use a modified key cache
1650 * design to support per-STA RX GTK, but until that gets
1651 * implemented, use of software crypto for group addressed
1652 * frames is a acceptable to allow RSN IBSS to be used.
1653 */
1654 return -EOPNOTSUPP;
1655 }
1656
1657 mutex_lock(&sc->mutex);
1658 ath9k_ps_wakeup(sc);
1659 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1660 if (sta)
1661 an = (struct ath_node *)sta->drv_priv;
1662
1663 switch (cmd) {
1664 case SET_KEY:
1665 if (sta)
1666 ath9k_del_ps_key(sc, vif, sta);
1667
1668 key->hw_key_idx = 0;
1669 ret = ath_key_config(common, vif, sta, key);
1670 if (ret >= 0) {
1671 key->hw_key_idx = ret;
1672 /* push IV and Michael MIC generation to stack */
1673 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1674 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1675 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1676 if (sc->sc_ah->sw_mgmt_crypto &&
1677 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1678 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1679 ret = 0;
1680 }
1681 if (an && key->hw_key_idx) {
1682 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1683 if (an->key_idx[i])
1684 continue;
1685 an->key_idx[i] = key->hw_key_idx;
1686 break;
1687 }
1688 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1689 }
1690 break;
1691 case DISABLE_KEY:
1692 ath_key_delete(common, key);
1693 if (an) {
1694 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1695 if (an->key_idx[i] != key->hw_key_idx)
1696 continue;
1697 an->key_idx[i] = 0;
1698 break;
1699 }
1700 }
1701 key->hw_key_idx = 0;
1702 break;
1703 default:
1704 ret = -EINVAL;
1705 }
1706
1707 ath9k_ps_restore(sc);
1708 mutex_unlock(&sc->mutex);
1709
1710 return ret;
1711 }
1712
1713 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1714 struct ieee80211_vif *vif,
1715 struct ieee80211_bss_conf *bss_conf,
1716 u32 changed)
1717 {
1718 #define CHECK_ANI \
1719 (BSS_CHANGED_ASSOC | \
1720 BSS_CHANGED_IBSS | \
1721 BSS_CHANGED_BEACON_ENABLED)
1722
1723 struct ath_softc *sc = hw->priv;
1724 struct ath_hw *ah = sc->sc_ah;
1725 struct ath_common *common = ath9k_hw_common(ah);
1726 struct ath_vif *avp = (void *)vif->drv_priv;
1727 int slottime;
1728
1729 ath9k_ps_wakeup(sc);
1730 mutex_lock(&sc->mutex);
1731
1732 if (changed & BSS_CHANGED_ASSOC) {
1733 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1734 bss_conf->bssid, bss_conf->assoc);
1735
1736 ether_addr_copy(avp->bssid, bss_conf->bssid);
1737 avp->aid = bss_conf->aid;
1738 avp->assoc = bss_conf->assoc;
1739
1740 ath9k_calculate_summary_state(sc, avp->chanctx);
1741
1742 if (ath9k_is_chanctx_enabled()) {
1743 if (bss_conf->assoc)
1744 ath_chanctx_event(sc, vif,
1745 ATH_CHANCTX_EVENT_ASSOC);
1746 }
1747 }
1748
1749 if (changed & BSS_CHANGED_IBSS) {
1750 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1751 common->curaid = bss_conf->aid;
1752 ath9k_hw_write_associd(sc->sc_ah);
1753 }
1754
1755 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1756 (changed & BSS_CHANGED_BEACON_INT) ||
1757 (changed & BSS_CHANGED_BEACON_INFO)) {
1758 ath9k_beacon_config(sc, vif, changed);
1759 if (changed & BSS_CHANGED_BEACON_ENABLED)
1760 ath9k_calculate_summary_state(sc, avp->chanctx);
1761 }
1762
1763 if ((avp->chanctx == sc->cur_chan) &&
1764 (changed & BSS_CHANGED_ERP_SLOT)) {
1765 if (bss_conf->use_short_slot)
1766 slottime = 9;
1767 else
1768 slottime = 20;
1769 if (vif->type == NL80211_IFTYPE_AP) {
1770 /*
1771 * Defer update, so that connected stations can adjust
1772 * their settings at the same time.
1773 * See beacon.c for more details
1774 */
1775 sc->beacon.slottime = slottime;
1776 sc->beacon.updateslot = UPDATE;
1777 } else {
1778 ah->slottime = slottime;
1779 ath9k_hw_init_global_settings(ah);
1780 }
1781 }
1782
1783 if (changed & BSS_CHANGED_P2P_PS)
1784 ath9k_p2p_bss_info_changed(sc, vif);
1785
1786 if (changed & CHECK_ANI)
1787 ath_check_ani(sc);
1788
1789 mutex_unlock(&sc->mutex);
1790 ath9k_ps_restore(sc);
1791
1792 #undef CHECK_ANI
1793 }
1794
1795 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1796 {
1797 struct ath_softc *sc = hw->priv;
1798 u64 tsf;
1799
1800 mutex_lock(&sc->mutex);
1801 ath9k_ps_wakeup(sc);
1802 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1803 ath9k_ps_restore(sc);
1804 mutex_unlock(&sc->mutex);
1805
1806 return tsf;
1807 }
1808
1809 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1810 struct ieee80211_vif *vif,
1811 u64 tsf)
1812 {
1813 struct ath_softc *sc = hw->priv;
1814
1815 mutex_lock(&sc->mutex);
1816 ath9k_ps_wakeup(sc);
1817 ath9k_hw_settsf64(sc->sc_ah, tsf);
1818 ath9k_ps_restore(sc);
1819 mutex_unlock(&sc->mutex);
1820 }
1821
1822 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1823 {
1824 struct ath_softc *sc = hw->priv;
1825
1826 mutex_lock(&sc->mutex);
1827
1828 ath9k_ps_wakeup(sc);
1829 ath9k_hw_reset_tsf(sc->sc_ah);
1830 ath9k_ps_restore(sc);
1831
1832 mutex_unlock(&sc->mutex);
1833 }
1834
1835 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1836 struct ieee80211_vif *vif,
1837 enum ieee80211_ampdu_mlme_action action,
1838 struct ieee80211_sta *sta,
1839 u16 tid, u16 *ssn, u8 buf_size)
1840 {
1841 struct ath_softc *sc = hw->priv;
1842 bool flush = false;
1843 int ret = 0;
1844
1845 mutex_lock(&sc->mutex);
1846
1847 switch (action) {
1848 case IEEE80211_AMPDU_RX_START:
1849 break;
1850 case IEEE80211_AMPDU_RX_STOP:
1851 break;
1852 case IEEE80211_AMPDU_TX_START:
1853 ath9k_ps_wakeup(sc);
1854 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1855 if (!ret)
1856 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1857 ath9k_ps_restore(sc);
1858 break;
1859 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1860 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1861 flush = true;
1862 case IEEE80211_AMPDU_TX_STOP_CONT:
1863 ath9k_ps_wakeup(sc);
1864 ath_tx_aggr_stop(sc, sta, tid);
1865 if (!flush)
1866 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1867 ath9k_ps_restore(sc);
1868 break;
1869 case IEEE80211_AMPDU_TX_OPERATIONAL:
1870 ath9k_ps_wakeup(sc);
1871 ath_tx_aggr_resume(sc, sta, tid);
1872 ath9k_ps_restore(sc);
1873 break;
1874 default:
1875 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1876 }
1877
1878 mutex_unlock(&sc->mutex);
1879
1880 return ret;
1881 }
1882
1883 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1884 struct survey_info *survey)
1885 {
1886 struct ath_softc *sc = hw->priv;
1887 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1888 struct ieee80211_supported_band *sband;
1889 struct ieee80211_channel *chan;
1890 int pos;
1891
1892 if (config_enabled(CONFIG_ATH9K_TX99))
1893 return -EOPNOTSUPP;
1894
1895 spin_lock_bh(&common->cc_lock);
1896 if (idx == 0)
1897 ath_update_survey_stats(sc);
1898
1899 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1900 if (sband && idx >= sband->n_channels) {
1901 idx -= sband->n_channels;
1902 sband = NULL;
1903 }
1904
1905 if (!sband)
1906 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1907
1908 if (!sband || idx >= sband->n_channels) {
1909 spin_unlock_bh(&common->cc_lock);
1910 return -ENOENT;
1911 }
1912
1913 chan = &sband->channels[idx];
1914 pos = chan->hw_value;
1915 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1916 survey->channel = chan;
1917 spin_unlock_bh(&common->cc_lock);
1918
1919 return 0;
1920 }
1921
1922 static void ath9k_enable_dynack(struct ath_softc *sc)
1923 {
1924 #ifdef CONFIG_ATH9K_DYNACK
1925 u32 rfilt;
1926 struct ath_hw *ah = sc->sc_ah;
1927
1928 ath_dynack_reset(ah);
1929
1930 ah->dynack.enabled = true;
1931 rfilt = ath_calcrxfilter(sc);
1932 ath9k_hw_setrxfilter(ah, rfilt);
1933 #endif
1934 }
1935
1936 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
1937 s16 coverage_class)
1938 {
1939 struct ath_softc *sc = hw->priv;
1940 struct ath_hw *ah = sc->sc_ah;
1941
1942 if (config_enabled(CONFIG_ATH9K_TX99))
1943 return;
1944
1945 mutex_lock(&sc->mutex);
1946
1947 if (coverage_class >= 0) {
1948 ah->coverage_class = coverage_class;
1949 if (ah->dynack.enabled) {
1950 u32 rfilt;
1951
1952 ah->dynack.enabled = false;
1953 rfilt = ath_calcrxfilter(sc);
1954 ath9k_hw_setrxfilter(ah, rfilt);
1955 }
1956 ath9k_ps_wakeup(sc);
1957 ath9k_hw_init_global_settings(ah);
1958 ath9k_ps_restore(sc);
1959 } else if (!ah->dynack.enabled) {
1960 ath9k_enable_dynack(sc);
1961 }
1962
1963 mutex_unlock(&sc->mutex);
1964 }
1965
1966 static bool ath9k_has_tx_pending(struct ath_softc *sc)
1967 {
1968 int i, npend = 0;
1969
1970 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1971 if (!ATH_TXQ_SETUP(sc, i))
1972 continue;
1973
1974 if (!sc->tx.txq[i].axq_depth)
1975 continue;
1976
1977 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1978 if (npend)
1979 break;
1980 }
1981
1982 return !!npend;
1983 }
1984
1985 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1986 u32 queues, bool drop)
1987 {
1988 struct ath_softc *sc = hw->priv;
1989
1990 mutex_lock(&sc->mutex);
1991 __ath9k_flush(hw, queues, drop);
1992 mutex_unlock(&sc->mutex);
1993 }
1994
1995 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1996 {
1997 struct ath_softc *sc = hw->priv;
1998 struct ath_hw *ah = sc->sc_ah;
1999 struct ath_common *common = ath9k_hw_common(ah);
2000 int timeout = HZ / 5; /* 200 ms */
2001 bool drain_txq;
2002 int i;
2003
2004 cancel_delayed_work_sync(&sc->tx_complete_work);
2005
2006 if (ah->ah_flags & AH_UNPLUGGED) {
2007 ath_dbg(common, ANY, "Device has been unplugged!\n");
2008 return;
2009 }
2010
2011 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2012 ath_dbg(common, ANY, "Device not present\n");
2013 return;
2014 }
2015
2016 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
2017 timeout) > 0)
2018 drop = false;
2019
2020 if (drop) {
2021 ath9k_ps_wakeup(sc);
2022 spin_lock_bh(&sc->sc_pcu_lock);
2023 drain_txq = ath_drain_all_txq(sc);
2024 spin_unlock_bh(&sc->sc_pcu_lock);
2025
2026 if (!drain_txq)
2027 ath_reset(sc);
2028
2029 ath9k_ps_restore(sc);
2030 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
2031 ieee80211_wake_queue(sc->hw,
2032 sc->cur_chan->hw_queue_base + i);
2033 }
2034 }
2035
2036 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2037 }
2038
2039 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2040 {
2041 struct ath_softc *sc = hw->priv;
2042 int i;
2043
2044 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2045 if (!ATH_TXQ_SETUP(sc, i))
2046 continue;
2047
2048 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
2049 return true;
2050 }
2051 return false;
2052 }
2053
2054 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2055 {
2056 struct ath_softc *sc = hw->priv;
2057 struct ath_hw *ah = sc->sc_ah;
2058 struct ieee80211_vif *vif;
2059 struct ath_vif *avp;
2060 struct ath_buf *bf;
2061 struct ath_tx_status ts;
2062 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2063 int status;
2064
2065 vif = sc->beacon.bslot[0];
2066 if (!vif)
2067 return 0;
2068
2069 if (!vif->bss_conf.enable_beacon)
2070 return 0;
2071
2072 avp = (void *)vif->drv_priv;
2073
2074 if (!sc->beacon.tx_processed && !edma) {
2075 tasklet_disable(&sc->bcon_tasklet);
2076
2077 bf = avp->av_bcbuf;
2078 if (!bf || !bf->bf_mpdu)
2079 goto skip;
2080
2081 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2082 if (status == -EINPROGRESS)
2083 goto skip;
2084
2085 sc->beacon.tx_processed = true;
2086 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2087
2088 skip:
2089 tasklet_enable(&sc->bcon_tasklet);
2090 }
2091
2092 return sc->beacon.tx_last;
2093 }
2094
2095 static int ath9k_get_stats(struct ieee80211_hw *hw,
2096 struct ieee80211_low_level_stats *stats)
2097 {
2098 struct ath_softc *sc = hw->priv;
2099 struct ath_hw *ah = sc->sc_ah;
2100 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2101
2102 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2103 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2104 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2105 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2106 return 0;
2107 }
2108
2109 static u32 fill_chainmask(u32 cap, u32 new)
2110 {
2111 u32 filled = 0;
2112 int i;
2113
2114 for (i = 0; cap && new; i++, cap >>= 1) {
2115 if (!(cap & BIT(0)))
2116 continue;
2117
2118 if (new & BIT(0))
2119 filled |= BIT(i);
2120
2121 new >>= 1;
2122 }
2123
2124 return filled;
2125 }
2126
2127 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2128 {
2129 if (AR_SREV_9300_20_OR_LATER(ah))
2130 return true;
2131
2132 switch (val & 0x7) {
2133 case 0x1:
2134 case 0x3:
2135 case 0x7:
2136 return true;
2137 case 0x2:
2138 return (ah->caps.rx_chainmask == 1);
2139 default:
2140 return false;
2141 }
2142 }
2143
2144 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2145 {
2146 struct ath_softc *sc = hw->priv;
2147 struct ath_hw *ah = sc->sc_ah;
2148
2149 if (ah->caps.rx_chainmask != 1)
2150 rx_ant |= tx_ant;
2151
2152 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2153 return -EINVAL;
2154
2155 sc->ant_rx = rx_ant;
2156 sc->ant_tx = tx_ant;
2157
2158 if (ah->caps.rx_chainmask == 1)
2159 return 0;
2160
2161 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2162 if (AR_SREV_9100(ah))
2163 ah->rxchainmask = 0x7;
2164 else
2165 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2166
2167 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2168 ath9k_cmn_reload_chainmask(ah);
2169
2170 return 0;
2171 }
2172
2173 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2174 {
2175 struct ath_softc *sc = hw->priv;
2176
2177 *tx_ant = sc->ant_tx;
2178 *rx_ant = sc->ant_rx;
2179 return 0;
2180 }
2181
2182 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2183 {
2184 struct ath_softc *sc = hw->priv;
2185 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2186 set_bit(ATH_OP_SCANNING, &common->op_flags);
2187 }
2188
2189 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2190 {
2191 struct ath_softc *sc = hw->priv;
2192 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2193 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2194 }
2195
2196 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2197
2198 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2199 struct ieee80211_scan_request *hw_req)
2200 {
2201 struct cfg80211_scan_request *req = &hw_req->req;
2202 struct ath_softc *sc = hw->priv;
2203 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2204 int ret = 0;
2205
2206 mutex_lock(&sc->mutex);
2207
2208 if (WARN_ON(sc->offchannel.scan_req)) {
2209 ret = -EBUSY;
2210 goto out;
2211 }
2212
2213 ath9k_ps_wakeup(sc);
2214 set_bit(ATH_OP_SCANNING, &common->op_flags);
2215 sc->offchannel.scan_vif = vif;
2216 sc->offchannel.scan_req = req;
2217 sc->offchannel.scan_idx = 0;
2218
2219 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2220 vif->addr);
2221
2222 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2223 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2224 ath_offchannel_next(sc);
2225 }
2226
2227 out:
2228 mutex_unlock(&sc->mutex);
2229
2230 return ret;
2231 }
2232
2233 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2234 struct ieee80211_vif *vif)
2235 {
2236 struct ath_softc *sc = hw->priv;
2237 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2238
2239 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2240
2241 mutex_lock(&sc->mutex);
2242 del_timer_sync(&sc->offchannel.timer);
2243 ath_scan_complete(sc, true);
2244 mutex_unlock(&sc->mutex);
2245 }
2246
2247 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2248 struct ieee80211_vif *vif,
2249 struct ieee80211_channel *chan, int duration,
2250 enum ieee80211_roc_type type)
2251 {
2252 struct ath_softc *sc = hw->priv;
2253 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2254 int ret = 0;
2255
2256 mutex_lock(&sc->mutex);
2257
2258 if (WARN_ON(sc->offchannel.roc_vif)) {
2259 ret = -EBUSY;
2260 goto out;
2261 }
2262
2263 ath9k_ps_wakeup(sc);
2264 sc->offchannel.roc_vif = vif;
2265 sc->offchannel.roc_chan = chan;
2266 sc->offchannel.roc_duration = duration;
2267
2268 ath_dbg(common, CHAN_CTX,
2269 "RoC request on vif: %pM, type: %d duration: %d\n",
2270 vif->addr, type, duration);
2271
2272 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2273 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2274 ath_offchannel_next(sc);
2275 }
2276
2277 out:
2278 mutex_unlock(&sc->mutex);
2279
2280 return ret;
2281 }
2282
2283 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2284 {
2285 struct ath_softc *sc = hw->priv;
2286 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2287
2288 mutex_lock(&sc->mutex);
2289
2290 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2291 del_timer_sync(&sc->offchannel.timer);
2292
2293 if (sc->offchannel.roc_vif) {
2294 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2295 ath_roc_complete(sc, true);
2296 }
2297
2298 mutex_unlock(&sc->mutex);
2299
2300 return 0;
2301 }
2302
2303 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2304 struct ieee80211_chanctx_conf *conf)
2305 {
2306 struct ath_softc *sc = hw->priv;
2307 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2308 struct ath_chanctx *ctx, **ptr;
2309 int pos;
2310
2311 mutex_lock(&sc->mutex);
2312
2313 ath_for_each_chanctx(sc, ctx) {
2314 if (ctx->assigned)
2315 continue;
2316
2317 ptr = (void *) conf->drv_priv;
2318 *ptr = ctx;
2319 ctx->assigned = true;
2320 pos = ctx - &sc->chanctx[0];
2321 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2322
2323 ath_dbg(common, CHAN_CTX,
2324 "Add channel context: %d MHz\n",
2325 conf->def.chan->center_freq);
2326
2327 ath_chanctx_set_channel(sc, ctx, &conf->def);
2328 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_ASSIGN);
2329
2330 mutex_unlock(&sc->mutex);
2331 return 0;
2332 }
2333
2334 mutex_unlock(&sc->mutex);
2335 return -ENOSPC;
2336 }
2337
2338
2339 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2340 struct ieee80211_chanctx_conf *conf)
2341 {
2342 struct ath_softc *sc = hw->priv;
2343 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2344 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2345
2346 mutex_lock(&sc->mutex);
2347
2348 ath_dbg(common, CHAN_CTX,
2349 "Remove channel context: %d MHz\n",
2350 conf->def.chan->center_freq);
2351
2352 ctx->assigned = false;
2353 ctx->hw_queue_base = -1;
2354 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2355
2356 mutex_unlock(&sc->mutex);
2357 }
2358
2359 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2360 struct ieee80211_chanctx_conf *conf,
2361 u32 changed)
2362 {
2363 struct ath_softc *sc = hw->priv;
2364 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2365 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2366
2367 mutex_lock(&sc->mutex);
2368 ath_dbg(common, CHAN_CTX,
2369 "Change channel context: %d MHz\n",
2370 conf->def.chan->center_freq);
2371 ath_chanctx_set_channel(sc, ctx, &conf->def);
2372 mutex_unlock(&sc->mutex);
2373 }
2374
2375 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2376 struct ieee80211_vif *vif,
2377 struct ieee80211_chanctx_conf *conf)
2378 {
2379 struct ath_softc *sc = hw->priv;
2380 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2381 struct ath_vif *avp = (void *)vif->drv_priv;
2382 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2383 int i;
2384
2385 mutex_lock(&sc->mutex);
2386
2387 ath_dbg(common, CHAN_CTX,
2388 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2389 vif->addr, vif->type, vif->p2p,
2390 conf->def.chan->center_freq);
2391
2392 avp->chanctx = ctx;
2393 ctx->nvifs_assigned++;
2394 list_add_tail(&avp->list, &ctx->vifs);
2395 ath9k_calculate_summary_state(sc, ctx);
2396 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2397 vif->hw_queue[i] = ctx->hw_queue_base + i;
2398
2399 mutex_unlock(&sc->mutex);
2400
2401 return 0;
2402 }
2403
2404 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2405 struct ieee80211_vif *vif,
2406 struct ieee80211_chanctx_conf *conf)
2407 {
2408 struct ath_softc *sc = hw->priv;
2409 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2410 struct ath_vif *avp = (void *)vif->drv_priv;
2411 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2412 int ac;
2413
2414 mutex_lock(&sc->mutex);
2415
2416 ath_dbg(common, CHAN_CTX,
2417 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2418 vif->addr, vif->type, vif->p2p,
2419 conf->def.chan->center_freq);
2420
2421 avp->chanctx = NULL;
2422 ctx->nvifs_assigned--;
2423 list_del(&avp->list);
2424 ath9k_calculate_summary_state(sc, ctx);
2425 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2426 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2427
2428 mutex_unlock(&sc->mutex);
2429 }
2430
2431 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2432 struct ieee80211_vif *vif)
2433 {
2434 struct ath_softc *sc = hw->priv;
2435 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2436 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2437 bool changed = false;
2438
2439 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2440 return;
2441
2442 if (!avp->chanctx)
2443 return;
2444
2445 mutex_lock(&sc->mutex);
2446
2447 spin_lock_bh(&sc->chan_lock);
2448 if (sc->next_chan || (sc->cur_chan != avp->chanctx)) {
2449 sc->next_chan = avp->chanctx;
2450 changed = true;
2451 }
2452 ath_dbg(common, CHAN_CTX,
2453 "%s: Set chanctx state to FORCE_ACTIVE, changed: %d\n",
2454 __func__, changed);
2455 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2456 spin_unlock_bh(&sc->chan_lock);
2457
2458 if (changed)
2459 ath_chanctx_set_next(sc, true);
2460
2461 mutex_unlock(&sc->mutex);
2462 }
2463
2464 void ath9k_fill_chanctx_ops(void)
2465 {
2466 if (!ath9k_is_chanctx_enabled())
2467 return;
2468
2469 ath9k_ops.hw_scan = ath9k_hw_scan;
2470 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2471 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2472 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2473 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2474 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2475 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2476 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2477 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2478 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2479 }
2480
2481 #endif
2482
2483 struct ieee80211_ops ath9k_ops = {
2484 .tx = ath9k_tx,
2485 .start = ath9k_start,
2486 .stop = ath9k_stop,
2487 .add_interface = ath9k_add_interface,
2488 .change_interface = ath9k_change_interface,
2489 .remove_interface = ath9k_remove_interface,
2490 .config = ath9k_config,
2491 .configure_filter = ath9k_configure_filter,
2492 .sta_add = ath9k_sta_add,
2493 .sta_remove = ath9k_sta_remove,
2494 .sta_notify = ath9k_sta_notify,
2495 .conf_tx = ath9k_conf_tx,
2496 .bss_info_changed = ath9k_bss_info_changed,
2497 .set_key = ath9k_set_key,
2498 .get_tsf = ath9k_get_tsf,
2499 .set_tsf = ath9k_set_tsf,
2500 .reset_tsf = ath9k_reset_tsf,
2501 .ampdu_action = ath9k_ampdu_action,
2502 .get_survey = ath9k_get_survey,
2503 .rfkill_poll = ath9k_rfkill_poll_state,
2504 .set_coverage_class = ath9k_set_coverage_class,
2505 .flush = ath9k_flush,
2506 .tx_frames_pending = ath9k_tx_frames_pending,
2507 .tx_last_beacon = ath9k_tx_last_beacon,
2508 .release_buffered_frames = ath9k_release_buffered_frames,
2509 .get_stats = ath9k_get_stats,
2510 .set_antenna = ath9k_set_antenna,
2511 .get_antenna = ath9k_get_antenna,
2512
2513 #ifdef CONFIG_ATH9K_WOW
2514 .suspend = ath9k_suspend,
2515 .resume = ath9k_resume,
2516 .set_wakeup = ath9k_set_wakeup,
2517 #endif
2518
2519 #ifdef CONFIG_ATH9K_DEBUGFS
2520 .get_et_sset_count = ath9k_get_et_sset_count,
2521 .get_et_stats = ath9k_get_et_stats,
2522 .get_et_strings = ath9k_get_et_strings,
2523 #endif
2524
2525 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2526 .sta_add_debugfs = ath9k_sta_add_debugfs,
2527 #endif
2528 .sw_scan_start = ath9k_sw_scan_start,
2529 .sw_scan_complete = ath9k_sw_scan_complete,
2530 };
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