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ath9k_hw: remove a useless WARN_ON
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58 }
59
60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61 {
62 bool pending = false;
63
64 spin_lock_bh(&txq->axq_lock);
65
66 if (txq->axq_depth || !list_empty(&txq->axq_acq))
67 pending = true;
68
69 spin_unlock_bh(&txq->axq_lock);
70 return pending;
71 }
72
73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
74 {
75 unsigned long flags;
76 bool ret;
77
78 spin_lock_irqsave(&sc->sc_pm_lock, flags);
79 ret = ath9k_hw_setpower(sc->sc_ah, mode);
80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
81
82 return ret;
83 }
84
85 void ath9k_ps_wakeup(struct ath_softc *sc)
86 {
87 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
88 unsigned long flags;
89 enum ath9k_power_mode power_mode;
90
91 spin_lock_irqsave(&sc->sc_pm_lock, flags);
92 if (++sc->ps_usecount != 1)
93 goto unlock;
94
95 power_mode = sc->sc_ah->power_mode;
96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
97
98 /*
99 * While the hardware is asleep, the cycle counters contain no
100 * useful data. Better clear them now so that they don't mess up
101 * survey data results.
102 */
103 if (power_mode != ATH9K_PM_AWAKE) {
104 spin_lock(&common->cc_lock);
105 ath_hw_cycle_counters_update(common);
106 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
107 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
108 spin_unlock(&common->cc_lock);
109 }
110
111 unlock:
112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
113 }
114
115 void ath9k_ps_restore(struct ath_softc *sc)
116 {
117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
118 enum ath9k_power_mode mode;
119 unsigned long flags;
120 bool reset;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (--sc->ps_usecount != 0)
124 goto unlock;
125
126 if (sc->ps_idle) {
127 ath9k_hw_setrxabort(sc->sc_ah, 1);
128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
129 mode = ATH9K_PM_FULL_SLEEP;
130 } else if (sc->ps_enabled &&
131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
132 PS_WAIT_FOR_CAB |
133 PS_WAIT_FOR_PSPOLL_DATA |
134 PS_WAIT_FOR_TX_ACK |
135 PS_WAIT_FOR_ANI))) {
136 mode = ATH9K_PM_NETWORK_SLEEP;
137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
138 ath9k_btcoex_stop_gen_timer(sc);
139 } else {
140 goto unlock;
141 }
142
143 spin_lock(&common->cc_lock);
144 ath_hw_cycle_counters_update(common);
145 spin_unlock(&common->cc_lock);
146
147 ath9k_hw_setpower(sc->sc_ah, mode);
148
149 unlock:
150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
151 }
152
153 static void __ath_cancel_work(struct ath_softc *sc)
154 {
155 cancel_work_sync(&sc->paprd_work);
156 cancel_work_sync(&sc->hw_check_work);
157 cancel_delayed_work_sync(&sc->tx_complete_work);
158 cancel_delayed_work_sync(&sc->hw_pll_work);
159
160 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
161 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
162 cancel_work_sync(&sc->mci_work);
163 #endif
164 }
165
166 static void ath_cancel_work(struct ath_softc *sc)
167 {
168 __ath_cancel_work(sc);
169 cancel_work_sync(&sc->hw_reset_work);
170 }
171
172 static void ath_restart_work(struct ath_softc *sc)
173 {
174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
175
176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
177 AR_SREV_9550(sc->sc_ah))
178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
180
181 ath_start_rx_poll(sc, 3);
182 ath_start_ani(sc);
183 }
184
185 static bool ath_prepare_reset(struct ath_softc *sc, bool flush)
186 {
187 struct ath_hw *ah = sc->sc_ah;
188 bool ret = true;
189
190 ieee80211_stop_queues(sc->hw);
191
192 sc->hw_busy_count = 0;
193 ath_stop_ani(sc);
194 del_timer_sync(&sc->rx_poll_timer);
195
196 ath9k_debug_samp_bb_mac(sc);
197 ath9k_hw_disable_interrupts(ah);
198
199 if (!ath_drain_all_txq(sc))
200 ret = false;
201
202 if (!ath_stoprecv(sc))
203 ret = false;
204
205 if (!flush) {
206 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
207 ath_rx_tasklet(sc, 1, true);
208 ath_rx_tasklet(sc, 1, false);
209 } else {
210 ath_flushrecv(sc);
211 }
212
213 return ret;
214 }
215
216 static bool ath_complete_reset(struct ath_softc *sc, bool start)
217 {
218 struct ath_hw *ah = sc->sc_ah;
219 struct ath_common *common = ath9k_hw_common(ah);
220 unsigned long flags;
221
222 if (ath_startrecv(sc) != 0) {
223 ath_err(common, "Unable to restart recv logic\n");
224 return false;
225 }
226
227 ath9k_cmn_update_txpow(ah, sc->curtxpow,
228 sc->config.txpowlimit, &sc->curtxpow);
229
230 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
231 ath9k_hw_set_interrupts(ah);
232 ath9k_hw_enable_interrupts(ah);
233
234 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
235 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
236 goto work;
237
238 ath9k_set_beacon(sc);
239
240 if (ah->opmode == NL80211_IFTYPE_STATION &&
241 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
242 spin_lock_irqsave(&sc->sc_pm_lock, flags);
243 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
244 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
245 }
246 work:
247 ath_restart_work(sc);
248 }
249
250 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
251 ath_ant_comb_update(sc);
252
253 ieee80211_wake_queues(sc->hw);
254
255 return true;
256 }
257
258 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
259 {
260 struct ath_hw *ah = sc->sc_ah;
261 struct ath_common *common = ath9k_hw_common(ah);
262 struct ath9k_hw_cal_data *caldata = NULL;
263 bool fastcc = true;
264 bool flush = false;
265 int r;
266
267 __ath_cancel_work(sc);
268
269 spin_lock_bh(&sc->sc_pcu_lock);
270
271 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
272 fastcc = false;
273 caldata = &sc->caldata;
274 }
275
276 if (!hchan) {
277 fastcc = false;
278 flush = true;
279 hchan = ah->curchan;
280 }
281
282 if (!ath_prepare_reset(sc, flush))
283 fastcc = false;
284
285 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
286 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
287
288 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
289 if (r) {
290 ath_err(common,
291 "Unable to reset channel, reset status %d\n", r);
292 goto out;
293 }
294
295 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
296 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
297 ath9k_mci_set_txpower(sc, true, false);
298
299 if (!ath_complete_reset(sc, true))
300 r = -EIO;
301
302 out:
303 spin_unlock_bh(&sc->sc_pcu_lock);
304 return r;
305 }
306
307
308 /*
309 * Set/change channels. If the channel is really being changed, it's done
310 * by reseting the chip. To accomplish this we must first cleanup any pending
311 * DMA, then restart stuff.
312 */
313 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
314 struct ath9k_channel *hchan)
315 {
316 int r;
317
318 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
319 return -EIO;
320
321 r = ath_reset_internal(sc, hchan);
322
323 return r;
324 }
325
326 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
327 struct ieee80211_vif *vif)
328 {
329 struct ath_node *an;
330 u8 density;
331 an = (struct ath_node *)sta->drv_priv;
332
333 an->sc = sc;
334 an->sta = sta;
335 an->vif = vif;
336
337 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
338 ath_tx_node_init(sc, an);
339 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
340 sta->ht_cap.ampdu_factor);
341 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
342 an->mpdudensity = density;
343 }
344 }
345
346 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
347 {
348 struct ath_node *an = (struct ath_node *)sta->drv_priv;
349
350 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
351 ath_tx_node_cleanup(sc, an);
352 }
353
354 void ath9k_tasklet(unsigned long data)
355 {
356 struct ath_softc *sc = (struct ath_softc *)data;
357 struct ath_hw *ah = sc->sc_ah;
358 struct ath_common *common = ath9k_hw_common(ah);
359 enum ath_reset_type type;
360 unsigned long flags;
361 u32 status = sc->intrstatus;
362 u32 rxmask;
363
364 ath9k_ps_wakeup(sc);
365 spin_lock(&sc->sc_pcu_lock);
366
367 if ((status & ATH9K_INT_FATAL) ||
368 (status & ATH9K_INT_BB_WATCHDOG)) {
369
370 if (status & ATH9K_INT_FATAL)
371 type = RESET_TYPE_FATAL_INT;
372 else
373 type = RESET_TYPE_BB_WATCHDOG;
374
375 ath9k_queue_reset(sc, type);
376 goto out;
377 }
378
379 spin_lock_irqsave(&sc->sc_pm_lock, flags);
380 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
381 /*
382 * TSF sync does not look correct; remain awake to sync with
383 * the next Beacon.
384 */
385 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
386 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
387 }
388 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
389
390 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
391 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
392 ATH9K_INT_RXORN);
393 else
394 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
395
396 if (status & rxmask) {
397 /* Check for high priority Rx first */
398 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
399 (status & ATH9K_INT_RXHP))
400 ath_rx_tasklet(sc, 0, true);
401
402 ath_rx_tasklet(sc, 0, false);
403 }
404
405 if (status & ATH9K_INT_TX) {
406 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
407 ath_tx_edma_tasklet(sc);
408 else
409 ath_tx_tasklet(sc);
410 }
411
412 ath9k_btcoex_handle_interrupt(sc, status);
413
414 out:
415 /* re-enable hardware interrupt */
416 ath9k_hw_enable_interrupts(ah);
417
418 spin_unlock(&sc->sc_pcu_lock);
419 ath9k_ps_restore(sc);
420 }
421
422 irqreturn_t ath_isr(int irq, void *dev)
423 {
424 #define SCHED_INTR ( \
425 ATH9K_INT_FATAL | \
426 ATH9K_INT_BB_WATCHDOG | \
427 ATH9K_INT_RXORN | \
428 ATH9K_INT_RXEOL | \
429 ATH9K_INT_RX | \
430 ATH9K_INT_RXLP | \
431 ATH9K_INT_RXHP | \
432 ATH9K_INT_TX | \
433 ATH9K_INT_BMISS | \
434 ATH9K_INT_CST | \
435 ATH9K_INT_TSFOOR | \
436 ATH9K_INT_GENTIMER | \
437 ATH9K_INT_MCI)
438
439 struct ath_softc *sc = dev;
440 struct ath_hw *ah = sc->sc_ah;
441 struct ath_common *common = ath9k_hw_common(ah);
442 enum ath9k_int status;
443 bool sched = false;
444
445 /*
446 * The hardware is not ready/present, don't
447 * touch anything. Note this can happen early
448 * on if the IRQ is shared.
449 */
450 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
451 return IRQ_NONE;
452
453 /* shared irq, not for us */
454
455 if (!ath9k_hw_intrpend(ah))
456 return IRQ_NONE;
457
458 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
459 ath9k_hw_kill_interrupts(ah);
460 return IRQ_HANDLED;
461 }
462
463 /*
464 * Figure out the reason(s) for the interrupt. Note
465 * that the hal returns a pseudo-ISR that may include
466 * bits we haven't explicitly enabled so we mask the
467 * value to insure we only process bits we requested.
468 */
469 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
470 status &= ah->imask; /* discard unasked-for bits */
471
472 /*
473 * If there are no status bits set, then this interrupt was not
474 * for me (should have been caught above).
475 */
476 if (!status)
477 return IRQ_NONE;
478
479 /* Cache the status */
480 sc->intrstatus = status;
481
482 if (status & SCHED_INTR)
483 sched = true;
484
485 /*
486 * If a FATAL or RXORN interrupt is received, we have to reset the
487 * chip immediately.
488 */
489 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
490 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
491 goto chip_reset;
492
493 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
494 (status & ATH9K_INT_BB_WATCHDOG)) {
495
496 spin_lock(&common->cc_lock);
497 ath_hw_cycle_counters_update(common);
498 ar9003_hw_bb_watchdog_dbg_info(ah);
499 spin_unlock(&common->cc_lock);
500
501 goto chip_reset;
502 }
503 #ifdef CONFIG_PM_SLEEP
504 if (status & ATH9K_INT_BMISS) {
505 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
506 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
507 atomic_inc(&sc->wow_got_bmiss_intr);
508 atomic_dec(&sc->wow_sleep_proc_intr);
509 }
510 }
511 #endif
512 if (status & ATH9K_INT_SWBA)
513 tasklet_schedule(&sc->bcon_tasklet);
514
515 if (status & ATH9K_INT_TXURN)
516 ath9k_hw_updatetxtriglevel(ah, true);
517
518 if (status & ATH9K_INT_RXEOL) {
519 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
520 ath9k_hw_set_interrupts(ah);
521 }
522
523 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
524 if (status & ATH9K_INT_TIM_TIMER) {
525 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
526 goto chip_reset;
527 /* Clear RxAbort bit so that we can
528 * receive frames */
529 ath9k_setpower(sc, ATH9K_PM_AWAKE);
530 spin_lock(&sc->sc_pm_lock);
531 ath9k_hw_setrxabort(sc->sc_ah, 0);
532 sc->ps_flags |= PS_WAIT_FOR_BEACON;
533 spin_unlock(&sc->sc_pm_lock);
534 }
535
536 chip_reset:
537
538 ath_debug_stat_interrupt(sc, status);
539
540 if (sched) {
541 /* turn off every interrupt */
542 ath9k_hw_disable_interrupts(ah);
543 tasklet_schedule(&sc->intr_tq);
544 }
545
546 return IRQ_HANDLED;
547
548 #undef SCHED_INTR
549 }
550
551 static int ath_reset(struct ath_softc *sc)
552 {
553 int i, r;
554
555 ath9k_ps_wakeup(sc);
556
557 r = ath_reset_internal(sc, NULL);
558
559 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
560 if (!ATH_TXQ_SETUP(sc, i))
561 continue;
562
563 spin_lock_bh(&sc->tx.txq[i].axq_lock);
564 ath_txq_schedule(sc, &sc->tx.txq[i]);
565 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
566 }
567
568 ath9k_ps_restore(sc);
569
570 return r;
571 }
572
573 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
574 {
575 #ifdef CONFIG_ATH9K_DEBUGFS
576 RESET_STAT_INC(sc, type);
577 #endif
578 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
579 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
580 }
581
582 void ath_reset_work(struct work_struct *work)
583 {
584 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
585
586 ath_reset(sc);
587 }
588
589 /**********************/
590 /* mac80211 callbacks */
591 /**********************/
592
593 static int ath9k_start(struct ieee80211_hw *hw)
594 {
595 struct ath_softc *sc = hw->priv;
596 struct ath_hw *ah = sc->sc_ah;
597 struct ath_common *common = ath9k_hw_common(ah);
598 struct ieee80211_channel *curchan = hw->conf.channel;
599 struct ath9k_channel *init_channel;
600 int r;
601
602 ath_dbg(common, CONFIG,
603 "Starting driver with initial channel: %d MHz\n",
604 curchan->center_freq);
605
606 ath9k_ps_wakeup(sc);
607 mutex_lock(&sc->mutex);
608
609 init_channel = ath9k_cmn_get_curchannel(hw, ah);
610
611 /* Reset SERDES registers */
612 ath9k_hw_configpcipowersave(ah, false);
613
614 /*
615 * The basic interface to setting the hardware in a good
616 * state is ``reset''. On return the hardware is known to
617 * be powered up and with interrupts disabled. This must
618 * be followed by initialization of the appropriate bits
619 * and then setup of the interrupt mask.
620 */
621 spin_lock_bh(&sc->sc_pcu_lock);
622
623 atomic_set(&ah->intr_ref_cnt, -1);
624
625 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
626 if (r) {
627 ath_err(common,
628 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
629 r, curchan->center_freq);
630 ah->reset_power_on = false;
631 }
632
633 /* Setup our intr mask. */
634 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
635 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
636 ATH9K_INT_GLOBAL;
637
638 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
639 ah->imask |= ATH9K_INT_RXHP |
640 ATH9K_INT_RXLP |
641 ATH9K_INT_BB_WATCHDOG;
642 else
643 ah->imask |= ATH9K_INT_RX;
644
645 ah->imask |= ATH9K_INT_GTT;
646
647 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
648 ah->imask |= ATH9K_INT_CST;
649
650 ath_mci_enable(sc);
651
652 clear_bit(SC_OP_INVALID, &sc->sc_flags);
653 sc->sc_ah->is_monitoring = false;
654
655 if (!ath_complete_reset(sc, false))
656 ah->reset_power_on = false;
657
658 if (ah->led_pin >= 0) {
659 ath9k_hw_cfg_output(ah, ah->led_pin,
660 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
661 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
662 }
663
664 /*
665 * Reset key cache to sane defaults (all entries cleared) instead of
666 * semi-random values after suspend/resume.
667 */
668 ath9k_cmn_init_crypto(sc->sc_ah);
669
670 spin_unlock_bh(&sc->sc_pcu_lock);
671
672 mutex_unlock(&sc->mutex);
673
674 ath9k_ps_restore(sc);
675
676 return 0;
677 }
678
679 static void ath9k_tx(struct ieee80211_hw *hw,
680 struct ieee80211_tx_control *control,
681 struct sk_buff *skb)
682 {
683 struct ath_softc *sc = hw->priv;
684 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
685 struct ath_tx_control txctl;
686 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
687 unsigned long flags;
688
689 if (sc->ps_enabled) {
690 /*
691 * mac80211 does not set PM field for normal data frames, so we
692 * need to update that based on the current PS mode.
693 */
694 if (ieee80211_is_data(hdr->frame_control) &&
695 !ieee80211_is_nullfunc(hdr->frame_control) &&
696 !ieee80211_has_pm(hdr->frame_control)) {
697 ath_dbg(common, PS,
698 "Add PM=1 for a TX frame while in PS mode\n");
699 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
700 }
701 }
702
703 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
704 /*
705 * We are using PS-Poll and mac80211 can request TX while in
706 * power save mode. Need to wake up hardware for the TX to be
707 * completed and if needed, also for RX of buffered frames.
708 */
709 ath9k_ps_wakeup(sc);
710 spin_lock_irqsave(&sc->sc_pm_lock, flags);
711 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
712 ath9k_hw_setrxabort(sc->sc_ah, 0);
713 if (ieee80211_is_pspoll(hdr->frame_control)) {
714 ath_dbg(common, PS,
715 "Sending PS-Poll to pick a buffered frame\n");
716 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
717 } else {
718 ath_dbg(common, PS, "Wake up to complete TX\n");
719 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
720 }
721 /*
722 * The actual restore operation will happen only after
723 * the ps_flags bit is cleared. We are just dropping
724 * the ps_usecount here.
725 */
726 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
727 ath9k_ps_restore(sc);
728 }
729
730 /*
731 * Cannot tx while the hardware is in full sleep, it first needs a full
732 * chip reset to recover from that
733 */
734 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
735 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
736 goto exit;
737 }
738
739 memset(&txctl, 0, sizeof(struct ath_tx_control));
740 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
741 txctl.sta = control->sta;
742
743 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
744
745 if (ath_tx_start(hw, skb, &txctl) != 0) {
746 ath_dbg(common, XMIT, "TX failed\n");
747 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
748 goto exit;
749 }
750
751 return;
752 exit:
753 ieee80211_free_txskb(hw, skb);
754 }
755
756 static void ath9k_stop(struct ieee80211_hw *hw)
757 {
758 struct ath_softc *sc = hw->priv;
759 struct ath_hw *ah = sc->sc_ah;
760 struct ath_common *common = ath9k_hw_common(ah);
761 bool prev_idle;
762
763 mutex_lock(&sc->mutex);
764
765 ath_cancel_work(sc);
766 del_timer_sync(&sc->rx_poll_timer);
767
768 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
769 ath_dbg(common, ANY, "Device not present\n");
770 mutex_unlock(&sc->mutex);
771 return;
772 }
773
774 /* Ensure HW is awake when we try to shut it down. */
775 ath9k_ps_wakeup(sc);
776
777 spin_lock_bh(&sc->sc_pcu_lock);
778
779 /* prevent tasklets to enable interrupts once we disable them */
780 ah->imask &= ~ATH9K_INT_GLOBAL;
781
782 /* make sure h/w will not generate any interrupt
783 * before setting the invalid flag. */
784 ath9k_hw_disable_interrupts(ah);
785
786 spin_unlock_bh(&sc->sc_pcu_lock);
787
788 /* we can now sync irq and kill any running tasklets, since we already
789 * disabled interrupts and not holding a spin lock */
790 synchronize_irq(sc->irq);
791 tasklet_kill(&sc->intr_tq);
792 tasklet_kill(&sc->bcon_tasklet);
793
794 prev_idle = sc->ps_idle;
795 sc->ps_idle = true;
796
797 spin_lock_bh(&sc->sc_pcu_lock);
798
799 if (ah->led_pin >= 0) {
800 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
801 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
802 }
803
804 ath_prepare_reset(sc, true);
805
806 if (sc->rx.frag) {
807 dev_kfree_skb_any(sc->rx.frag);
808 sc->rx.frag = NULL;
809 }
810
811 if (!ah->curchan)
812 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
813
814 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
815 ath9k_hw_phy_disable(ah);
816
817 ath9k_hw_configpcipowersave(ah, true);
818
819 spin_unlock_bh(&sc->sc_pcu_lock);
820
821 ath9k_ps_restore(sc);
822
823 set_bit(SC_OP_INVALID, &sc->sc_flags);
824 sc->ps_idle = prev_idle;
825
826 mutex_unlock(&sc->mutex);
827
828 ath_dbg(common, CONFIG, "Driver halt\n");
829 }
830
831 bool ath9k_uses_beacons(int type)
832 {
833 switch (type) {
834 case NL80211_IFTYPE_AP:
835 case NL80211_IFTYPE_ADHOC:
836 case NL80211_IFTYPE_MESH_POINT:
837 return true;
838 default:
839 return false;
840 }
841 }
842
843 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
844 {
845 struct ath9k_vif_iter_data *iter_data = data;
846 int i;
847
848 if (iter_data->hw_macaddr)
849 for (i = 0; i < ETH_ALEN; i++)
850 iter_data->mask[i] &=
851 ~(iter_data->hw_macaddr[i] ^ mac[i]);
852
853 switch (vif->type) {
854 case NL80211_IFTYPE_AP:
855 iter_data->naps++;
856 break;
857 case NL80211_IFTYPE_STATION:
858 iter_data->nstations++;
859 break;
860 case NL80211_IFTYPE_ADHOC:
861 iter_data->nadhocs++;
862 break;
863 case NL80211_IFTYPE_MESH_POINT:
864 iter_data->nmeshes++;
865 break;
866 case NL80211_IFTYPE_WDS:
867 iter_data->nwds++;
868 break;
869 default:
870 break;
871 }
872 }
873
874 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
875 {
876 struct ath_softc *sc = data;
877 struct ath_vif *avp = (void *)vif->drv_priv;
878
879 if (vif->type != NL80211_IFTYPE_STATION)
880 return;
881
882 if (avp->primary_sta_vif)
883 ath9k_set_assoc_state(sc, vif);
884 }
885
886 /* Called with sc->mutex held. */
887 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
888 struct ieee80211_vif *vif,
889 struct ath9k_vif_iter_data *iter_data)
890 {
891 struct ath_softc *sc = hw->priv;
892 struct ath_hw *ah = sc->sc_ah;
893 struct ath_common *common = ath9k_hw_common(ah);
894
895 /*
896 * Use the hardware MAC address as reference, the hardware uses it
897 * together with the BSSID mask when matching addresses.
898 */
899 memset(iter_data, 0, sizeof(*iter_data));
900 iter_data->hw_macaddr = common->macaddr;
901 memset(&iter_data->mask, 0xff, ETH_ALEN);
902
903 if (vif)
904 ath9k_vif_iter(iter_data, vif->addr, vif);
905
906 /* Get list of all active MAC addresses */
907 ieee80211_iterate_active_interfaces_atomic(
908 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
909 ath9k_vif_iter, iter_data);
910 }
911
912 /* Called with sc->mutex held. */
913 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
914 struct ieee80211_vif *vif)
915 {
916 struct ath_softc *sc = hw->priv;
917 struct ath_hw *ah = sc->sc_ah;
918 struct ath_common *common = ath9k_hw_common(ah);
919 struct ath9k_vif_iter_data iter_data;
920 enum nl80211_iftype old_opmode = ah->opmode;
921
922 ath9k_calculate_iter_data(hw, vif, &iter_data);
923
924 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
925 ath_hw_setbssidmask(common);
926
927 if (iter_data.naps > 0) {
928 ath9k_hw_set_tsfadjust(ah, true);
929 ah->opmode = NL80211_IFTYPE_AP;
930 } else {
931 ath9k_hw_set_tsfadjust(ah, false);
932
933 if (iter_data.nmeshes)
934 ah->opmode = NL80211_IFTYPE_MESH_POINT;
935 else if (iter_data.nwds)
936 ah->opmode = NL80211_IFTYPE_AP;
937 else if (iter_data.nadhocs)
938 ah->opmode = NL80211_IFTYPE_ADHOC;
939 else
940 ah->opmode = NL80211_IFTYPE_STATION;
941 }
942
943 ath9k_hw_setopmode(ah);
944
945 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
946 ah->imask |= ATH9K_INT_TSFOOR;
947 else
948 ah->imask &= ~ATH9K_INT_TSFOOR;
949
950 ath9k_hw_set_interrupts(ah);
951
952 /*
953 * If we are changing the opmode to STATION,
954 * a beacon sync needs to be done.
955 */
956 if (ah->opmode == NL80211_IFTYPE_STATION &&
957 old_opmode == NL80211_IFTYPE_AP &&
958 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
959 ieee80211_iterate_active_interfaces_atomic(
960 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
961 ath9k_sta_vif_iter, sc);
962 }
963 }
964
965 static int ath9k_add_interface(struct ieee80211_hw *hw,
966 struct ieee80211_vif *vif)
967 {
968 struct ath_softc *sc = hw->priv;
969 struct ath_hw *ah = sc->sc_ah;
970 struct ath_common *common = ath9k_hw_common(ah);
971
972 mutex_lock(&sc->mutex);
973
974 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
975 sc->nvifs++;
976
977 ath9k_ps_wakeup(sc);
978 ath9k_calculate_summary_state(hw, vif);
979 ath9k_ps_restore(sc);
980
981 if (ath9k_uses_beacons(vif->type))
982 ath9k_beacon_assign_slot(sc, vif);
983
984 mutex_unlock(&sc->mutex);
985 return 0;
986 }
987
988 static int ath9k_change_interface(struct ieee80211_hw *hw,
989 struct ieee80211_vif *vif,
990 enum nl80211_iftype new_type,
991 bool p2p)
992 {
993 struct ath_softc *sc = hw->priv;
994 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
995
996 ath_dbg(common, CONFIG, "Change Interface\n");
997 mutex_lock(&sc->mutex);
998
999 if (ath9k_uses_beacons(vif->type))
1000 ath9k_beacon_remove_slot(sc, vif);
1001
1002 vif->type = new_type;
1003 vif->p2p = p2p;
1004
1005 ath9k_ps_wakeup(sc);
1006 ath9k_calculate_summary_state(hw, vif);
1007 ath9k_ps_restore(sc);
1008
1009 if (ath9k_uses_beacons(vif->type))
1010 ath9k_beacon_assign_slot(sc, vif);
1011
1012 mutex_unlock(&sc->mutex);
1013 return 0;
1014 }
1015
1016 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1017 struct ieee80211_vif *vif)
1018 {
1019 struct ath_softc *sc = hw->priv;
1020 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1021
1022 ath_dbg(common, CONFIG, "Detach Interface\n");
1023
1024 mutex_lock(&sc->mutex);
1025
1026 sc->nvifs--;
1027
1028 if (ath9k_uses_beacons(vif->type))
1029 ath9k_beacon_remove_slot(sc, vif);
1030
1031 ath9k_ps_wakeup(sc);
1032 ath9k_calculate_summary_state(hw, NULL);
1033 ath9k_ps_restore(sc);
1034
1035 mutex_unlock(&sc->mutex);
1036 }
1037
1038 static void ath9k_enable_ps(struct ath_softc *sc)
1039 {
1040 struct ath_hw *ah = sc->sc_ah;
1041 struct ath_common *common = ath9k_hw_common(ah);
1042
1043 sc->ps_enabled = true;
1044 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1045 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1046 ah->imask |= ATH9K_INT_TIM_TIMER;
1047 ath9k_hw_set_interrupts(ah);
1048 }
1049 ath9k_hw_setrxabort(ah, 1);
1050 }
1051 ath_dbg(common, PS, "PowerSave enabled\n");
1052 }
1053
1054 static void ath9k_disable_ps(struct ath_softc *sc)
1055 {
1056 struct ath_hw *ah = sc->sc_ah;
1057 struct ath_common *common = ath9k_hw_common(ah);
1058
1059 sc->ps_enabled = false;
1060 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1061 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1062 ath9k_hw_setrxabort(ah, 0);
1063 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1064 PS_WAIT_FOR_CAB |
1065 PS_WAIT_FOR_PSPOLL_DATA |
1066 PS_WAIT_FOR_TX_ACK);
1067 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1068 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1069 ath9k_hw_set_interrupts(ah);
1070 }
1071 }
1072 ath_dbg(common, PS, "PowerSave disabled\n");
1073 }
1074
1075 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
1076 {
1077 struct ath_softc *sc = hw->priv;
1078 struct ath_hw *ah = sc->sc_ah;
1079 struct ath_common *common = ath9k_hw_common(ah);
1080 u32 rxfilter;
1081
1082 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1083 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1084 return;
1085 }
1086
1087 ath9k_ps_wakeup(sc);
1088 rxfilter = ath9k_hw_getrxfilter(ah);
1089 ath9k_hw_setrxfilter(ah, rxfilter |
1090 ATH9K_RX_FILTER_PHYRADAR |
1091 ATH9K_RX_FILTER_PHYERR);
1092
1093 /* TODO: usually this should not be neccesary, but for some reason
1094 * (or in some mode?) the trigger must be called after the
1095 * configuration, otherwise the register will have its values reset
1096 * (on my ar9220 to value 0x01002310)
1097 */
1098 ath9k_spectral_scan_config(hw, sc->spectral_mode);
1099 ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
1100 ath9k_ps_restore(sc);
1101 }
1102
1103 int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
1104 enum spectral_mode spectral_mode)
1105 {
1106 struct ath_softc *sc = hw->priv;
1107 struct ath_hw *ah = sc->sc_ah;
1108 struct ath_common *common = ath9k_hw_common(ah);
1109 struct ath_spec_scan param;
1110
1111 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1112 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1113 return -1;
1114 }
1115
1116 /* NOTE: this will generate a few samples ...
1117 *
1118 * TODO: review default parameters, and/or define an interface to set
1119 * them.
1120 */
1121 param.enabled = 1;
1122 param.short_repeat = true;
1123 param.count = 8;
1124 param.endless = false;
1125 param.period = 0xFF;
1126 param.fft_period = 0xF;
1127
1128 switch (spectral_mode) {
1129 case SPECTRAL_DISABLED:
1130 param.enabled = 0;
1131 break;
1132 case SPECTRAL_BACKGROUND:
1133 /* send endless samples.
1134 * TODO: is this really useful for "background"?
1135 */
1136 param.endless = 1;
1137 break;
1138 case SPECTRAL_CHANSCAN:
1139 break;
1140 case SPECTRAL_MANUAL:
1141 break;
1142 default:
1143 return -1;
1144 }
1145
1146 ath9k_ps_wakeup(sc);
1147 ath9k_hw_ops(ah)->spectral_scan_config(ah, &param);
1148 ath9k_ps_restore(sc);
1149
1150 sc->spectral_mode = spectral_mode;
1151
1152 return 0;
1153 }
1154
1155 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1156 {
1157 struct ath_softc *sc = hw->priv;
1158 struct ath_hw *ah = sc->sc_ah;
1159 struct ath_common *common = ath9k_hw_common(ah);
1160 struct ieee80211_conf *conf = &hw->conf;
1161 bool reset_channel = false;
1162
1163 ath9k_ps_wakeup(sc);
1164 mutex_lock(&sc->mutex);
1165
1166 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1167 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1168 if (sc->ps_idle) {
1169 ath_cancel_work(sc);
1170 ath9k_stop_btcoex(sc);
1171 } else {
1172 ath9k_start_btcoex(sc);
1173 /*
1174 * The chip needs a reset to properly wake up from
1175 * full sleep
1176 */
1177 reset_channel = ah->chip_fullsleep;
1178 }
1179 }
1180
1181 /*
1182 * We just prepare to enable PS. We have to wait until our AP has
1183 * ACK'd our null data frame to disable RX otherwise we'll ignore
1184 * those ACKs and end up retransmitting the same null data frames.
1185 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1186 */
1187 if (changed & IEEE80211_CONF_CHANGE_PS) {
1188 unsigned long flags;
1189 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1190 if (conf->flags & IEEE80211_CONF_PS)
1191 ath9k_enable_ps(sc);
1192 else
1193 ath9k_disable_ps(sc);
1194 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1195 }
1196
1197 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1198 if (conf->flags & IEEE80211_CONF_MONITOR) {
1199 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1200 sc->sc_ah->is_monitoring = true;
1201 } else {
1202 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1203 sc->sc_ah->is_monitoring = false;
1204 }
1205 }
1206
1207 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
1208 struct ieee80211_channel *curchan = hw->conf.channel;
1209 int pos = curchan->hw_value;
1210 int old_pos = -1;
1211 unsigned long flags;
1212
1213 if (ah->curchan)
1214 old_pos = ah->curchan - &ah->channels[0];
1215
1216 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
1217 curchan->center_freq, conf->channel_type);
1218
1219 /* update survey stats for the old channel before switching */
1220 spin_lock_irqsave(&common->cc_lock, flags);
1221 ath_update_survey_stats(sc);
1222 spin_unlock_irqrestore(&common->cc_lock, flags);
1223
1224 /*
1225 * Preserve the current channel values, before updating
1226 * the same channel
1227 */
1228 if (ah->curchan && (old_pos == pos))
1229 ath9k_hw_getnf(ah, ah->curchan);
1230
1231 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1232 curchan, conf->channel_type);
1233
1234 /*
1235 * If the operating channel changes, change the survey in-use flags
1236 * along with it.
1237 * Reset the survey data for the new channel, unless we're switching
1238 * back to the operating channel from an off-channel operation.
1239 */
1240 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1241 sc->cur_survey != &sc->survey[pos]) {
1242
1243 if (sc->cur_survey)
1244 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1245
1246 sc->cur_survey = &sc->survey[pos];
1247
1248 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1249 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1250 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1251 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1252 }
1253
1254 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1255 ath_err(common, "Unable to set channel\n");
1256 mutex_unlock(&sc->mutex);
1257 ath9k_ps_restore(sc);
1258 return -EINVAL;
1259 }
1260
1261 /*
1262 * The most recent snapshot of channel->noisefloor for the old
1263 * channel is only available after the hardware reset. Copy it to
1264 * the survey stats now.
1265 */
1266 if (old_pos >= 0)
1267 ath_update_survey_nf(sc, old_pos);
1268
1269 /* perform spectral scan if requested. */
1270 if (sc->scanning && sc->spectral_mode == SPECTRAL_CHANSCAN)
1271 ath9k_spectral_scan_trigger(hw);
1272
1273 }
1274
1275 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1276 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1277 sc->config.txpowlimit = 2 * conf->power_level;
1278 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1279 sc->config.txpowlimit, &sc->curtxpow);
1280 }
1281
1282 mutex_unlock(&sc->mutex);
1283 ath9k_ps_restore(sc);
1284
1285 return 0;
1286 }
1287
1288 #define SUPPORTED_FILTERS \
1289 (FIF_PROMISC_IN_BSS | \
1290 FIF_ALLMULTI | \
1291 FIF_CONTROL | \
1292 FIF_PSPOLL | \
1293 FIF_OTHER_BSS | \
1294 FIF_BCN_PRBRESP_PROMISC | \
1295 FIF_PROBE_REQ | \
1296 FIF_FCSFAIL)
1297
1298 /* FIXME: sc->sc_full_reset ? */
1299 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1300 unsigned int changed_flags,
1301 unsigned int *total_flags,
1302 u64 multicast)
1303 {
1304 struct ath_softc *sc = hw->priv;
1305 u32 rfilt;
1306
1307 changed_flags &= SUPPORTED_FILTERS;
1308 *total_flags &= SUPPORTED_FILTERS;
1309
1310 sc->rx.rxfilter = *total_flags;
1311 ath9k_ps_wakeup(sc);
1312 rfilt = ath_calcrxfilter(sc);
1313 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1314 ath9k_ps_restore(sc);
1315
1316 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1317 rfilt);
1318 }
1319
1320 static int ath9k_sta_add(struct ieee80211_hw *hw,
1321 struct ieee80211_vif *vif,
1322 struct ieee80211_sta *sta)
1323 {
1324 struct ath_softc *sc = hw->priv;
1325 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1326 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1327 struct ieee80211_key_conf ps_key = { };
1328
1329 ath_node_attach(sc, sta, vif);
1330
1331 if (vif->type != NL80211_IFTYPE_AP &&
1332 vif->type != NL80211_IFTYPE_AP_VLAN)
1333 return 0;
1334
1335 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
1336
1337 return 0;
1338 }
1339
1340 static void ath9k_del_ps_key(struct ath_softc *sc,
1341 struct ieee80211_vif *vif,
1342 struct ieee80211_sta *sta)
1343 {
1344 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1345 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1346 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1347
1348 if (!an->ps_key)
1349 return;
1350
1351 ath_key_delete(common, &ps_key);
1352 }
1353
1354 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1355 struct ieee80211_vif *vif,
1356 struct ieee80211_sta *sta)
1357 {
1358 struct ath_softc *sc = hw->priv;
1359
1360 ath9k_del_ps_key(sc, vif, sta);
1361 ath_node_detach(sc, sta);
1362
1363 return 0;
1364 }
1365
1366 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1367 struct ieee80211_vif *vif,
1368 enum sta_notify_cmd cmd,
1369 struct ieee80211_sta *sta)
1370 {
1371 struct ath_softc *sc = hw->priv;
1372 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1373
1374 if (!sta->ht_cap.ht_supported)
1375 return;
1376
1377 switch (cmd) {
1378 case STA_NOTIFY_SLEEP:
1379 an->sleeping = true;
1380 ath_tx_aggr_sleep(sta, sc, an);
1381 break;
1382 case STA_NOTIFY_AWAKE:
1383 an->sleeping = false;
1384 ath_tx_aggr_wakeup(sc, an);
1385 break;
1386 }
1387 }
1388
1389 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1390 struct ieee80211_vif *vif, u16 queue,
1391 const struct ieee80211_tx_queue_params *params)
1392 {
1393 struct ath_softc *sc = hw->priv;
1394 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1395 struct ath_txq *txq;
1396 struct ath9k_tx_queue_info qi;
1397 int ret = 0;
1398
1399 if (queue >= IEEE80211_NUM_ACS)
1400 return 0;
1401
1402 txq = sc->tx.txq_map[queue];
1403
1404 ath9k_ps_wakeup(sc);
1405 mutex_lock(&sc->mutex);
1406
1407 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1408
1409 qi.tqi_aifs = params->aifs;
1410 qi.tqi_cwmin = params->cw_min;
1411 qi.tqi_cwmax = params->cw_max;
1412 qi.tqi_burstTime = params->txop * 32;
1413
1414 ath_dbg(common, CONFIG,
1415 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1416 queue, txq->axq_qnum, params->aifs, params->cw_min,
1417 params->cw_max, params->txop);
1418
1419 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1420 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1421 if (ret)
1422 ath_err(common, "TXQ Update failed\n");
1423
1424 mutex_unlock(&sc->mutex);
1425 ath9k_ps_restore(sc);
1426
1427 return ret;
1428 }
1429
1430 static int ath9k_set_key(struct ieee80211_hw *hw,
1431 enum set_key_cmd cmd,
1432 struct ieee80211_vif *vif,
1433 struct ieee80211_sta *sta,
1434 struct ieee80211_key_conf *key)
1435 {
1436 struct ath_softc *sc = hw->priv;
1437 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1438 int ret = 0;
1439
1440 if (ath9k_modparam_nohwcrypt)
1441 return -ENOSPC;
1442
1443 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1444 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1445 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1446 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1447 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1448 /*
1449 * For now, disable hw crypto for the RSN IBSS group keys. This
1450 * could be optimized in the future to use a modified key cache
1451 * design to support per-STA RX GTK, but until that gets
1452 * implemented, use of software crypto for group addressed
1453 * frames is a acceptable to allow RSN IBSS to be used.
1454 */
1455 return -EOPNOTSUPP;
1456 }
1457
1458 mutex_lock(&sc->mutex);
1459 ath9k_ps_wakeup(sc);
1460 ath_dbg(common, CONFIG, "Set HW Key\n");
1461
1462 switch (cmd) {
1463 case SET_KEY:
1464 if (sta)
1465 ath9k_del_ps_key(sc, vif, sta);
1466
1467 ret = ath_key_config(common, vif, sta, key);
1468 if (ret >= 0) {
1469 key->hw_key_idx = ret;
1470 /* push IV and Michael MIC generation to stack */
1471 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1472 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1473 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1474 if (sc->sc_ah->sw_mgmt_crypto &&
1475 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1476 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1477 ret = 0;
1478 }
1479 break;
1480 case DISABLE_KEY:
1481 ath_key_delete(common, key);
1482 break;
1483 default:
1484 ret = -EINVAL;
1485 }
1486
1487 ath9k_ps_restore(sc);
1488 mutex_unlock(&sc->mutex);
1489
1490 return ret;
1491 }
1492
1493 static void ath9k_set_assoc_state(struct ath_softc *sc,
1494 struct ieee80211_vif *vif)
1495 {
1496 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1497 struct ath_vif *avp = (void *)vif->drv_priv;
1498 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1499 unsigned long flags;
1500
1501 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1502 avp->primary_sta_vif = true;
1503
1504 /*
1505 * Set the AID, BSSID and do beacon-sync only when
1506 * the HW opmode is STATION.
1507 *
1508 * But the primary bit is set above in any case.
1509 */
1510 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1511 return;
1512
1513 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1514 common->curaid = bss_conf->aid;
1515 ath9k_hw_write_associd(sc->sc_ah);
1516
1517 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1518 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1519
1520 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1521 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1522 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1523
1524 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1525 ath9k_mci_update_wlan_channels(sc, false);
1526
1527 ath_dbg(common, CONFIG,
1528 "Primary Station interface: %pM, BSSID: %pM\n",
1529 vif->addr, common->curbssid);
1530 }
1531
1532 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1533 {
1534 struct ath_softc *sc = data;
1535 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1536
1537 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
1538 return;
1539
1540 if (bss_conf->assoc)
1541 ath9k_set_assoc_state(sc, vif);
1542 }
1543
1544 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1545 struct ieee80211_vif *vif,
1546 struct ieee80211_bss_conf *bss_conf,
1547 u32 changed)
1548 {
1549 #define CHECK_ANI \
1550 (BSS_CHANGED_ASSOC | \
1551 BSS_CHANGED_IBSS | \
1552 BSS_CHANGED_BEACON_ENABLED)
1553
1554 struct ath_softc *sc = hw->priv;
1555 struct ath_hw *ah = sc->sc_ah;
1556 struct ath_common *common = ath9k_hw_common(ah);
1557 struct ath_vif *avp = (void *)vif->drv_priv;
1558 int slottime;
1559
1560 ath9k_ps_wakeup(sc);
1561 mutex_lock(&sc->mutex);
1562
1563 if (changed & BSS_CHANGED_ASSOC) {
1564 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1565 bss_conf->bssid, bss_conf->assoc);
1566
1567 if (avp->primary_sta_vif && !bss_conf->assoc) {
1568 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1569 avp->primary_sta_vif = false;
1570
1571 if (ah->opmode == NL80211_IFTYPE_STATION)
1572 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1573 }
1574
1575 ieee80211_iterate_active_interfaces_atomic(
1576 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1577 ath9k_bss_assoc_iter, sc);
1578
1579 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1580 ah->opmode == NL80211_IFTYPE_STATION) {
1581 memset(common->curbssid, 0, ETH_ALEN);
1582 common->curaid = 0;
1583 ath9k_hw_write_associd(sc->sc_ah);
1584 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1585 ath9k_mci_update_wlan_channels(sc, true);
1586 }
1587 }
1588
1589 if (changed & BSS_CHANGED_IBSS) {
1590 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1591 common->curaid = bss_conf->aid;
1592 ath9k_hw_write_associd(sc->sc_ah);
1593 }
1594
1595 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1596 (changed & BSS_CHANGED_BEACON_INT)) {
1597 if (ah->opmode == NL80211_IFTYPE_AP &&
1598 bss_conf->enable_beacon)
1599 ath9k_set_tsfadjust(sc, vif);
1600 if (ath9k_allow_beacon_config(sc, vif))
1601 ath9k_beacon_config(sc, vif, changed);
1602 }
1603
1604 if (changed & BSS_CHANGED_ERP_SLOT) {
1605 if (bss_conf->use_short_slot)
1606 slottime = 9;
1607 else
1608 slottime = 20;
1609 if (vif->type == NL80211_IFTYPE_AP) {
1610 /*
1611 * Defer update, so that connected stations can adjust
1612 * their settings at the same time.
1613 * See beacon.c for more details
1614 */
1615 sc->beacon.slottime = slottime;
1616 sc->beacon.updateslot = UPDATE;
1617 } else {
1618 ah->slottime = slottime;
1619 ath9k_hw_init_global_settings(ah);
1620 }
1621 }
1622
1623 if (changed & CHECK_ANI)
1624 ath_check_ani(sc);
1625
1626 mutex_unlock(&sc->mutex);
1627 ath9k_ps_restore(sc);
1628
1629 #undef CHECK_ANI
1630 }
1631
1632 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1633 {
1634 struct ath_softc *sc = hw->priv;
1635 u64 tsf;
1636
1637 mutex_lock(&sc->mutex);
1638 ath9k_ps_wakeup(sc);
1639 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1640 ath9k_ps_restore(sc);
1641 mutex_unlock(&sc->mutex);
1642
1643 return tsf;
1644 }
1645
1646 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1647 struct ieee80211_vif *vif,
1648 u64 tsf)
1649 {
1650 struct ath_softc *sc = hw->priv;
1651
1652 mutex_lock(&sc->mutex);
1653 ath9k_ps_wakeup(sc);
1654 ath9k_hw_settsf64(sc->sc_ah, tsf);
1655 ath9k_ps_restore(sc);
1656 mutex_unlock(&sc->mutex);
1657 }
1658
1659 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1660 {
1661 struct ath_softc *sc = hw->priv;
1662
1663 mutex_lock(&sc->mutex);
1664
1665 ath9k_ps_wakeup(sc);
1666 ath9k_hw_reset_tsf(sc->sc_ah);
1667 ath9k_ps_restore(sc);
1668
1669 mutex_unlock(&sc->mutex);
1670 }
1671
1672 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1673 struct ieee80211_vif *vif,
1674 enum ieee80211_ampdu_mlme_action action,
1675 struct ieee80211_sta *sta,
1676 u16 tid, u16 *ssn, u8 buf_size)
1677 {
1678 struct ath_softc *sc = hw->priv;
1679 int ret = 0;
1680
1681 local_bh_disable();
1682
1683 switch (action) {
1684 case IEEE80211_AMPDU_RX_START:
1685 break;
1686 case IEEE80211_AMPDU_RX_STOP:
1687 break;
1688 case IEEE80211_AMPDU_TX_START:
1689 ath9k_ps_wakeup(sc);
1690 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1691 if (!ret)
1692 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1693 ath9k_ps_restore(sc);
1694 break;
1695 case IEEE80211_AMPDU_TX_STOP_CONT:
1696 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1697 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1698 ath9k_ps_wakeup(sc);
1699 ath_tx_aggr_stop(sc, sta, tid);
1700 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1701 ath9k_ps_restore(sc);
1702 break;
1703 case IEEE80211_AMPDU_TX_OPERATIONAL:
1704 ath9k_ps_wakeup(sc);
1705 ath_tx_aggr_resume(sc, sta, tid);
1706 ath9k_ps_restore(sc);
1707 break;
1708 default:
1709 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1710 }
1711
1712 local_bh_enable();
1713
1714 return ret;
1715 }
1716
1717 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1718 struct survey_info *survey)
1719 {
1720 struct ath_softc *sc = hw->priv;
1721 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1722 struct ieee80211_supported_band *sband;
1723 struct ieee80211_channel *chan;
1724 unsigned long flags;
1725 int pos;
1726
1727 spin_lock_irqsave(&common->cc_lock, flags);
1728 if (idx == 0)
1729 ath_update_survey_stats(sc);
1730
1731 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1732 if (sband && idx >= sband->n_channels) {
1733 idx -= sband->n_channels;
1734 sband = NULL;
1735 }
1736
1737 if (!sband)
1738 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1739
1740 if (!sband || idx >= sband->n_channels) {
1741 spin_unlock_irqrestore(&common->cc_lock, flags);
1742 return -ENOENT;
1743 }
1744
1745 chan = &sband->channels[idx];
1746 pos = chan->hw_value;
1747 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1748 survey->channel = chan;
1749 spin_unlock_irqrestore(&common->cc_lock, flags);
1750
1751 return 0;
1752 }
1753
1754 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1755 {
1756 struct ath_softc *sc = hw->priv;
1757 struct ath_hw *ah = sc->sc_ah;
1758
1759 mutex_lock(&sc->mutex);
1760 ah->coverage_class = coverage_class;
1761
1762 ath9k_ps_wakeup(sc);
1763 ath9k_hw_init_global_settings(ah);
1764 ath9k_ps_restore(sc);
1765
1766 mutex_unlock(&sc->mutex);
1767 }
1768
1769 static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1770 {
1771 struct ath_softc *sc = hw->priv;
1772 struct ath_hw *ah = sc->sc_ah;
1773 struct ath_common *common = ath9k_hw_common(ah);
1774 int timeout = 200; /* ms */
1775 int i, j;
1776 bool drain_txq;
1777
1778 mutex_lock(&sc->mutex);
1779 cancel_delayed_work_sync(&sc->tx_complete_work);
1780
1781 if (ah->ah_flags & AH_UNPLUGGED) {
1782 ath_dbg(common, ANY, "Device has been unplugged!\n");
1783 mutex_unlock(&sc->mutex);
1784 return;
1785 }
1786
1787 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
1788 ath_dbg(common, ANY, "Device not present\n");
1789 mutex_unlock(&sc->mutex);
1790 return;
1791 }
1792
1793 for (j = 0; j < timeout; j++) {
1794 bool npend = false;
1795
1796 if (j)
1797 usleep_range(1000, 2000);
1798
1799 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1800 if (!ATH_TXQ_SETUP(sc, i))
1801 continue;
1802
1803 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1804
1805 if (npend)
1806 break;
1807 }
1808
1809 if (!npend)
1810 break;
1811 }
1812
1813 if (drop) {
1814 ath9k_ps_wakeup(sc);
1815 spin_lock_bh(&sc->sc_pcu_lock);
1816 drain_txq = ath_drain_all_txq(sc);
1817 spin_unlock_bh(&sc->sc_pcu_lock);
1818
1819 if (!drain_txq)
1820 ath_reset(sc);
1821
1822 ath9k_ps_restore(sc);
1823 ieee80211_wake_queues(hw);
1824 }
1825
1826 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1827 mutex_unlock(&sc->mutex);
1828 }
1829
1830 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1831 {
1832 struct ath_softc *sc = hw->priv;
1833 int i;
1834
1835 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1836 if (!ATH_TXQ_SETUP(sc, i))
1837 continue;
1838
1839 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1840 return true;
1841 }
1842 return false;
1843 }
1844
1845 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
1846 {
1847 struct ath_softc *sc = hw->priv;
1848 struct ath_hw *ah = sc->sc_ah;
1849 struct ieee80211_vif *vif;
1850 struct ath_vif *avp;
1851 struct ath_buf *bf;
1852 struct ath_tx_status ts;
1853 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1854 int status;
1855
1856 vif = sc->beacon.bslot[0];
1857 if (!vif)
1858 return 0;
1859
1860 if (!vif->bss_conf.enable_beacon)
1861 return 0;
1862
1863 avp = (void *)vif->drv_priv;
1864
1865 if (!sc->beacon.tx_processed && !edma) {
1866 tasklet_disable(&sc->bcon_tasklet);
1867
1868 bf = avp->av_bcbuf;
1869 if (!bf || !bf->bf_mpdu)
1870 goto skip;
1871
1872 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1873 if (status == -EINPROGRESS)
1874 goto skip;
1875
1876 sc->beacon.tx_processed = true;
1877 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1878
1879 skip:
1880 tasklet_enable(&sc->bcon_tasklet);
1881 }
1882
1883 return sc->beacon.tx_last;
1884 }
1885
1886 static int ath9k_get_stats(struct ieee80211_hw *hw,
1887 struct ieee80211_low_level_stats *stats)
1888 {
1889 struct ath_softc *sc = hw->priv;
1890 struct ath_hw *ah = sc->sc_ah;
1891 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1892
1893 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1894 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1895 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1896 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1897 return 0;
1898 }
1899
1900 static u32 fill_chainmask(u32 cap, u32 new)
1901 {
1902 u32 filled = 0;
1903 int i;
1904
1905 for (i = 0; cap && new; i++, cap >>= 1) {
1906 if (!(cap & BIT(0)))
1907 continue;
1908
1909 if (new & BIT(0))
1910 filled |= BIT(i);
1911
1912 new >>= 1;
1913 }
1914
1915 return filled;
1916 }
1917
1918 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
1919 {
1920 switch (val & 0x7) {
1921 case 0x1:
1922 case 0x3:
1923 case 0x7:
1924 return true;
1925 case 0x2:
1926 return (ah->caps.rx_chainmask == 1);
1927 default:
1928 return false;
1929 }
1930 }
1931
1932 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1933 {
1934 struct ath_softc *sc = hw->priv;
1935 struct ath_hw *ah = sc->sc_ah;
1936
1937 if (ah->caps.rx_chainmask != 1)
1938 rx_ant |= tx_ant;
1939
1940 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
1941 return -EINVAL;
1942
1943 sc->ant_rx = rx_ant;
1944 sc->ant_tx = tx_ant;
1945
1946 if (ah->caps.rx_chainmask == 1)
1947 return 0;
1948
1949 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1950 if (AR_SREV_9100(ah))
1951 ah->rxchainmask = 0x7;
1952 else
1953 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1954
1955 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1956 ath9k_reload_chainmask_settings(sc);
1957
1958 return 0;
1959 }
1960
1961 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1962 {
1963 struct ath_softc *sc = hw->priv;
1964
1965 *tx_ant = sc->ant_tx;
1966 *rx_ant = sc->ant_rx;
1967 return 0;
1968 }
1969
1970 #ifdef CONFIG_PM_SLEEP
1971
1972 static void ath9k_wow_map_triggers(struct ath_softc *sc,
1973 struct cfg80211_wowlan *wowlan,
1974 u32 *wow_triggers)
1975 {
1976 if (wowlan->disconnect)
1977 *wow_triggers |= AH_WOW_LINK_CHANGE |
1978 AH_WOW_BEACON_MISS;
1979 if (wowlan->magic_pkt)
1980 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
1981
1982 if (wowlan->n_patterns)
1983 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
1984
1985 sc->wow_enabled = *wow_triggers;
1986
1987 }
1988
1989 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
1990 {
1991 struct ath_hw *ah = sc->sc_ah;
1992 struct ath_common *common = ath9k_hw_common(ah);
1993 struct ath9k_hw_capabilities *pcaps = &ah->caps;
1994 int pattern_count = 0;
1995 int i, byte_cnt;
1996 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
1997 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
1998
1999 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2000 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2001
2002 /*
2003 * Create Dissassociate / Deauthenticate packet filter
2004 *
2005 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
2006 * +--------------+----------+---------+--------+--------+----
2007 * + Frame Control+ Duration + DA + SA + BSSID +
2008 * +--------------+----------+---------+--------+--------+----
2009 *
2010 * The above is the management frame format for disassociate/
2011 * deauthenticate pattern, from this we need to match the first byte
2012 * of 'Frame Control' and DA, SA, and BSSID fields
2013 * (skipping 2nd byte of FC and Duration feild.
2014 *
2015 * Disassociate pattern
2016 * --------------------
2017 * Frame control = 00 00 1010
2018 * DA, SA, BSSID = x:x:x:x:x:x
2019 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2020 * | x:x:x:x:x:x -- 22 bytes
2021 *
2022 * Deauthenticate pattern
2023 * ----------------------
2024 * Frame control = 00 00 1100
2025 * DA, SA, BSSID = x:x:x:x:x:x
2026 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2027 * | x:x:x:x:x:x -- 22 bytes
2028 */
2029
2030 /* Create Disassociate Pattern first */
2031
2032 byte_cnt = 0;
2033
2034 /* Fill out the mask with all FF's */
2035
2036 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2037 dis_deauth_mask[i] = 0xff;
2038
2039 /* copy the first byte of frame control field */
2040 dis_deauth_pattern[byte_cnt] = 0xa0;
2041 byte_cnt++;
2042
2043 /* skip 2nd byte of frame control and Duration field */
2044 byte_cnt += 3;
2045
2046 /*
2047 * need not match the destination mac address, it can be a broadcast
2048 * mac address or an unicast to this station
2049 */
2050 byte_cnt += 6;
2051
2052 /* copy the source mac address */
2053 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2054
2055 byte_cnt += 6;
2056
2057 /* copy the bssid, its same as the source mac address */
2058
2059 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2060
2061 /* Create Disassociate pattern mask */
2062
2063 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
2064
2065 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
2066 /*
2067 * for AR9280, because of hardware limitation, the
2068 * first 4 bytes have to be matched for all patterns.
2069 * the mask for disassociation and de-auth pattern
2070 * matching need to enable the first 4 bytes.
2071 * also the duration field needs to be filled.
2072 */
2073 dis_deauth_mask[0] = 0xf0;
2074
2075 /*
2076 * fill in duration field
2077 FIXME: what is the exact value ?
2078 */
2079 dis_deauth_pattern[2] = 0xff;
2080 dis_deauth_pattern[3] = 0xff;
2081 } else {
2082 dis_deauth_mask[0] = 0xfe;
2083 }
2084
2085 dis_deauth_mask[1] = 0x03;
2086 dis_deauth_mask[2] = 0xc0;
2087 } else {
2088 dis_deauth_mask[0] = 0xef;
2089 dis_deauth_mask[1] = 0x3f;
2090 dis_deauth_mask[2] = 0x00;
2091 dis_deauth_mask[3] = 0xfc;
2092 }
2093
2094 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2095
2096 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2097 pattern_count, byte_cnt);
2098
2099 pattern_count++;
2100 /*
2101 * for de-authenticate pattern, only the first byte of the frame
2102 * control field gets changed from 0xA0 to 0xC0
2103 */
2104 dis_deauth_pattern[0] = 0xC0;
2105
2106 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2107 pattern_count, byte_cnt);
2108
2109 }
2110
2111 static void ath9k_wow_add_pattern(struct ath_softc *sc,
2112 struct cfg80211_wowlan *wowlan)
2113 {
2114 struct ath_hw *ah = sc->sc_ah;
2115 struct ath9k_wow_pattern *wow_pattern = NULL;
2116 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2117 int mask_len;
2118 s8 i = 0;
2119
2120 if (!wowlan->n_patterns)
2121 return;
2122
2123 /*
2124 * Add the new user configured patterns
2125 */
2126 for (i = 0; i < wowlan->n_patterns; i++) {
2127
2128 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2129
2130 if (!wow_pattern)
2131 return;
2132
2133 /*
2134 * TODO: convert the generic user space pattern to
2135 * appropriate chip specific/802.11 pattern.
2136 */
2137
2138 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2139 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2140 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2141 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2142 patterns[i].pattern_len);
2143 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2144 wow_pattern->pattern_len = patterns[i].pattern_len;
2145
2146 /*
2147 * just need to take care of deauth and disssoc pattern,
2148 * make sure we don't overwrite them.
2149 */
2150
2151 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2152 wow_pattern->mask_bytes,
2153 i + 2,
2154 wow_pattern->pattern_len);
2155 kfree(wow_pattern);
2156
2157 }
2158
2159 }
2160
2161 static int ath9k_suspend(struct ieee80211_hw *hw,
2162 struct cfg80211_wowlan *wowlan)
2163 {
2164 struct ath_softc *sc = hw->priv;
2165 struct ath_hw *ah = sc->sc_ah;
2166 struct ath_common *common = ath9k_hw_common(ah);
2167 u32 wow_triggers_enabled = 0;
2168 int ret = 0;
2169
2170 mutex_lock(&sc->mutex);
2171
2172 ath_cancel_work(sc);
2173 ath_stop_ani(sc);
2174 del_timer_sync(&sc->rx_poll_timer);
2175
2176 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2177 ath_dbg(common, ANY, "Device not present\n");
2178 ret = -EINVAL;
2179 goto fail_wow;
2180 }
2181
2182 if (WARN_ON(!wowlan)) {
2183 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2184 ret = -EINVAL;
2185 goto fail_wow;
2186 }
2187
2188 if (!device_can_wakeup(sc->dev)) {
2189 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2190 ret = 1;
2191 goto fail_wow;
2192 }
2193
2194 /*
2195 * none of the sta vifs are associated
2196 * and we are not currently handling multivif
2197 * cases, for instance we have to seperately
2198 * configure 'keep alive frame' for each
2199 * STA.
2200 */
2201
2202 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2203 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2204 ret = 1;
2205 goto fail_wow;
2206 }
2207
2208 if (sc->nvifs > 1) {
2209 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2210 ret = 1;
2211 goto fail_wow;
2212 }
2213
2214 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2215
2216 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2217 wow_triggers_enabled);
2218
2219 ath9k_ps_wakeup(sc);
2220
2221 ath9k_stop_btcoex(sc);
2222
2223 /*
2224 * Enable wake up on recieving disassoc/deauth
2225 * frame by default.
2226 */
2227 ath9k_wow_add_disassoc_deauth_pattern(sc);
2228
2229 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2230 ath9k_wow_add_pattern(sc, wowlan);
2231
2232 spin_lock_bh(&sc->sc_pcu_lock);
2233 /*
2234 * To avoid false wake, we enable beacon miss interrupt only
2235 * when we go to sleep. We save the current interrupt mask
2236 * so we can restore it after the system wakes up
2237 */
2238 sc->wow_intr_before_sleep = ah->imask;
2239 ah->imask &= ~ATH9K_INT_GLOBAL;
2240 ath9k_hw_disable_interrupts(ah);
2241 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2242 ath9k_hw_set_interrupts(ah);
2243 ath9k_hw_enable_interrupts(ah);
2244
2245 spin_unlock_bh(&sc->sc_pcu_lock);
2246
2247 /*
2248 * we can now sync irq and kill any running tasklets, since we already
2249 * disabled interrupts and not holding a spin lock
2250 */
2251 synchronize_irq(sc->irq);
2252 tasklet_kill(&sc->intr_tq);
2253
2254 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2255
2256 ath9k_ps_restore(sc);
2257 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2258 atomic_inc(&sc->wow_sleep_proc_intr);
2259
2260 fail_wow:
2261 mutex_unlock(&sc->mutex);
2262 return ret;
2263 }
2264
2265 static int ath9k_resume(struct ieee80211_hw *hw)
2266 {
2267 struct ath_softc *sc = hw->priv;
2268 struct ath_hw *ah = sc->sc_ah;
2269 struct ath_common *common = ath9k_hw_common(ah);
2270 u32 wow_status;
2271
2272 mutex_lock(&sc->mutex);
2273
2274 ath9k_ps_wakeup(sc);
2275
2276 spin_lock_bh(&sc->sc_pcu_lock);
2277
2278 ath9k_hw_disable_interrupts(ah);
2279 ah->imask = sc->wow_intr_before_sleep;
2280 ath9k_hw_set_interrupts(ah);
2281 ath9k_hw_enable_interrupts(ah);
2282
2283 spin_unlock_bh(&sc->sc_pcu_lock);
2284
2285 wow_status = ath9k_hw_wow_wakeup(ah);
2286
2287 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2288 /*
2289 * some devices may not pick beacon miss
2290 * as the reason they woke up so we add
2291 * that here for that shortcoming.
2292 */
2293 wow_status |= AH_WOW_BEACON_MISS;
2294 atomic_dec(&sc->wow_got_bmiss_intr);
2295 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2296 }
2297
2298 atomic_dec(&sc->wow_sleep_proc_intr);
2299
2300 if (wow_status) {
2301 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2302 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2303 }
2304
2305 ath_restart_work(sc);
2306 ath9k_start_btcoex(sc);
2307
2308 ath9k_ps_restore(sc);
2309 mutex_unlock(&sc->mutex);
2310
2311 return 0;
2312 }
2313
2314 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2315 {
2316 struct ath_softc *sc = hw->priv;
2317
2318 mutex_lock(&sc->mutex);
2319 device_init_wakeup(sc->dev, 1);
2320 device_set_wakeup_enable(sc->dev, enabled);
2321 mutex_unlock(&sc->mutex);
2322 }
2323
2324 #endif
2325 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2326 {
2327 struct ath_softc *sc = hw->priv;
2328
2329 sc->scanning = 1;
2330 }
2331
2332 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2333 {
2334 struct ath_softc *sc = hw->priv;
2335
2336 sc->scanning = 0;
2337 }
2338
2339 struct ieee80211_ops ath9k_ops = {
2340 .tx = ath9k_tx,
2341 .start = ath9k_start,
2342 .stop = ath9k_stop,
2343 .add_interface = ath9k_add_interface,
2344 .change_interface = ath9k_change_interface,
2345 .remove_interface = ath9k_remove_interface,
2346 .config = ath9k_config,
2347 .configure_filter = ath9k_configure_filter,
2348 .sta_add = ath9k_sta_add,
2349 .sta_remove = ath9k_sta_remove,
2350 .sta_notify = ath9k_sta_notify,
2351 .conf_tx = ath9k_conf_tx,
2352 .bss_info_changed = ath9k_bss_info_changed,
2353 .set_key = ath9k_set_key,
2354 .get_tsf = ath9k_get_tsf,
2355 .set_tsf = ath9k_set_tsf,
2356 .reset_tsf = ath9k_reset_tsf,
2357 .ampdu_action = ath9k_ampdu_action,
2358 .get_survey = ath9k_get_survey,
2359 .rfkill_poll = ath9k_rfkill_poll_state,
2360 .set_coverage_class = ath9k_set_coverage_class,
2361 .flush = ath9k_flush,
2362 .tx_frames_pending = ath9k_tx_frames_pending,
2363 .tx_last_beacon = ath9k_tx_last_beacon,
2364 .get_stats = ath9k_get_stats,
2365 .set_antenna = ath9k_set_antenna,
2366 .get_antenna = ath9k_get_antenna,
2367
2368 #ifdef CONFIG_PM_SLEEP
2369 .suspend = ath9k_suspend,
2370 .resume = ath9k_resume,
2371 .set_wakeup = ath9k_set_wakeup,
2372 #endif
2373
2374 #ifdef CONFIG_ATH9K_DEBUGFS
2375 .get_et_sset_count = ath9k_get_et_sset_count,
2376 .get_et_stats = ath9k_get_et_stats,
2377 .get_et_strings = ath9k_get_et_strings,
2378 #endif
2379
2380 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
2381 .sta_add_debugfs = ath9k_sta_add_debugfs,
2382 .sta_remove_debugfs = ath9k_sta_remove_debugfs,
2383 #endif
2384 .sw_scan_start = ath9k_sw_scan_start,
2385 .sw_scan_complete = ath9k_sw_scan_complete,
2386 };
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