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cfg80211: remove enum ieee80211_band
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23 {
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55 }
56
57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
58 bool sw_pending)
59 {
60 bool pending = false;
61
62 spin_lock_bh(&txq->axq_lock);
63
64 if (txq->axq_depth) {
65 pending = true;
66 goto out;
67 }
68
69 if (!sw_pending)
70 goto out;
71
72 if (txq->mac80211_qnum >= 0) {
73 struct list_head *list;
74
75 list = &sc->cur_chan->acq[txq->mac80211_qnum];
76 if (!list_empty(list))
77 pending = true;
78 }
79 out:
80 spin_unlock_bh(&txq->axq_lock);
81 return pending;
82 }
83
84 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
85 {
86 unsigned long flags;
87 bool ret;
88
89 spin_lock_irqsave(&sc->sc_pm_lock, flags);
90 ret = ath9k_hw_setpower(sc->sc_ah, mode);
91 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
92
93 return ret;
94 }
95
96 void ath_ps_full_sleep(unsigned long data)
97 {
98 struct ath_softc *sc = (struct ath_softc *) data;
99 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
100 bool reset;
101
102 spin_lock(&common->cc_lock);
103 ath_hw_cycle_counters_update(common);
104 spin_unlock(&common->cc_lock);
105
106 ath9k_hw_setrxabort(sc->sc_ah, 1);
107 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
108
109 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
110 }
111
112 void ath9k_ps_wakeup(struct ath_softc *sc)
113 {
114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
115 unsigned long flags;
116 enum ath9k_power_mode power_mode;
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (++sc->ps_usecount != 1)
120 goto unlock;
121
122 del_timer_sync(&sc->sleep_timer);
123 power_mode = sc->sc_ah->power_mode;
124 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
125
126 /*
127 * While the hardware is asleep, the cycle counters contain no
128 * useful data. Better clear them now so that they don't mess up
129 * survey data results.
130 */
131 if (power_mode != ATH9K_PM_AWAKE) {
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
135 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
136 spin_unlock(&common->cc_lock);
137 }
138
139 unlock:
140 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
141 }
142
143 void ath9k_ps_restore(struct ath_softc *sc)
144 {
145 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
146 enum ath9k_power_mode mode;
147 unsigned long flags;
148
149 spin_lock_irqsave(&sc->sc_pm_lock, flags);
150 if (--sc->ps_usecount != 0)
151 goto unlock;
152
153 if (sc->ps_idle) {
154 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
155 goto unlock;
156 }
157
158 if (sc->ps_enabled &&
159 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
160 PS_WAIT_FOR_CAB |
161 PS_WAIT_FOR_PSPOLL_DATA |
162 PS_WAIT_FOR_TX_ACK |
163 PS_WAIT_FOR_ANI))) {
164 mode = ATH9K_PM_NETWORK_SLEEP;
165 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
166 ath9k_btcoex_stop_gen_timer(sc);
167 } else {
168 goto unlock;
169 }
170
171 spin_lock(&common->cc_lock);
172 ath_hw_cycle_counters_update(common);
173 spin_unlock(&common->cc_lock);
174
175 ath9k_hw_setpower(sc->sc_ah, mode);
176
177 unlock:
178 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
179 }
180
181 static void __ath_cancel_work(struct ath_softc *sc)
182 {
183 cancel_work_sync(&sc->paprd_work);
184 cancel_delayed_work_sync(&sc->tx_complete_work);
185 cancel_delayed_work_sync(&sc->hw_pll_work);
186
187 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
188 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
189 cancel_work_sync(&sc->mci_work);
190 #endif
191 }
192
193 void ath_cancel_work(struct ath_softc *sc)
194 {
195 __ath_cancel_work(sc);
196 cancel_work_sync(&sc->hw_reset_work);
197 }
198
199 void ath_restart_work(struct ath_softc *sc)
200 {
201 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
202
203 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
204 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
205 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
206
207 ath_start_ani(sc);
208 }
209
210 static bool ath_prepare_reset(struct ath_softc *sc)
211 {
212 struct ath_hw *ah = sc->sc_ah;
213 bool ret = true;
214
215 ieee80211_stop_queues(sc->hw);
216 ath_stop_ani(sc);
217 ath9k_hw_disable_interrupts(ah);
218
219 if (AR_SREV_9300_20_OR_LATER(ah)) {
220 ret &= ath_stoprecv(sc);
221 ret &= ath_drain_all_txq(sc);
222 } else {
223 ret &= ath_drain_all_txq(sc);
224 ret &= ath_stoprecv(sc);
225 }
226
227 return ret;
228 }
229
230 static bool ath_complete_reset(struct ath_softc *sc, bool start)
231 {
232 struct ath_hw *ah = sc->sc_ah;
233 struct ath_common *common = ath9k_hw_common(ah);
234 unsigned long flags;
235
236 ath9k_calculate_summary_state(sc, sc->cur_chan);
237 ath_startrecv(sc);
238 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
239 sc->cur_chan->txpower,
240 &sc->cur_chan->cur_txpower);
241 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
242
243 if (!sc->cur_chan->offchannel && start) {
244 /* restore per chanctx TSF timer */
245 if (sc->cur_chan->tsf_val) {
246 u32 offset;
247
248 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
249 NULL);
250 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
251 }
252
253
254 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
255 goto work;
256
257 if (ah->opmode == NL80211_IFTYPE_STATION &&
258 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
259 spin_lock_irqsave(&sc->sc_pm_lock, flags);
260 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
261 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
262 } else {
263 ath9k_set_beacon(sc);
264 }
265 work:
266 ath_restart_work(sc);
267 ath_txq_schedule_all(sc);
268 }
269
270 sc->gtt_cnt = 0;
271
272 ath9k_hw_set_interrupts(ah);
273 ath9k_hw_enable_interrupts(ah);
274 ieee80211_wake_queues(sc->hw);
275 ath9k_p2p_ps_timer(sc);
276
277 return true;
278 }
279
280 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
281 {
282 struct ath_hw *ah = sc->sc_ah;
283 struct ath_common *common = ath9k_hw_common(ah);
284 struct ath9k_hw_cal_data *caldata = NULL;
285 bool fastcc = true;
286 int r;
287
288 __ath_cancel_work(sc);
289
290 disable_irq(sc->irq);
291 tasklet_disable(&sc->intr_tq);
292 tasklet_disable(&sc->bcon_tasklet);
293 spin_lock_bh(&sc->sc_pcu_lock);
294
295 if (!sc->cur_chan->offchannel) {
296 fastcc = false;
297 caldata = &sc->cur_chan->caldata;
298 }
299
300 if (!hchan) {
301 fastcc = false;
302 hchan = ah->curchan;
303 }
304
305 if (!ath_prepare_reset(sc))
306 fastcc = false;
307
308 if (ath9k_is_chanctx_enabled())
309 fastcc = false;
310
311 spin_lock_bh(&sc->chan_lock);
312 sc->cur_chandef = sc->cur_chan->chandef;
313 spin_unlock_bh(&sc->chan_lock);
314
315 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
316 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
317
318 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
319 if (r) {
320 ath_err(common,
321 "Unable to reset channel, reset status %d\n", r);
322
323 ath9k_hw_enable_interrupts(ah);
324 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
325
326 goto out;
327 }
328
329 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
330 sc->cur_chan->offchannel)
331 ath9k_mci_set_txpower(sc, true, false);
332
333 if (!ath_complete_reset(sc, true))
334 r = -EIO;
335
336 out:
337 enable_irq(sc->irq);
338 spin_unlock_bh(&sc->sc_pcu_lock);
339 tasklet_enable(&sc->bcon_tasklet);
340 tasklet_enable(&sc->intr_tq);
341
342 return r;
343 }
344
345 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
346 struct ieee80211_vif *vif)
347 {
348 struct ath_node *an;
349 an = (struct ath_node *)sta->drv_priv;
350
351 an->sc = sc;
352 an->sta = sta;
353 an->vif = vif;
354 memset(&an->key_idx, 0, sizeof(an->key_idx));
355
356 ath_tx_node_init(sc, an);
357
358 ath_dynack_node_init(sc->sc_ah, an);
359 }
360
361 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
362 {
363 struct ath_node *an = (struct ath_node *)sta->drv_priv;
364 ath_tx_node_cleanup(sc, an);
365
366 ath_dynack_node_deinit(sc->sc_ah, an);
367 }
368
369 void ath9k_tasklet(unsigned long data)
370 {
371 struct ath_softc *sc = (struct ath_softc *)data;
372 struct ath_hw *ah = sc->sc_ah;
373 struct ath_common *common = ath9k_hw_common(ah);
374 enum ath_reset_type type;
375 unsigned long flags;
376 u32 status = sc->intrstatus;
377 u32 rxmask;
378
379 ath9k_ps_wakeup(sc);
380 spin_lock(&sc->sc_pcu_lock);
381
382 if (status & ATH9K_INT_FATAL) {
383 type = RESET_TYPE_FATAL_INT;
384 ath9k_queue_reset(sc, type);
385
386 /*
387 * Increment the ref. counter here so that
388 * interrupts are enabled in the reset routine.
389 */
390 atomic_inc(&ah->intr_ref_cnt);
391 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
392 goto out;
393 }
394
395 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
396 (status & ATH9K_INT_BB_WATCHDOG)) {
397 spin_lock(&common->cc_lock);
398 ath_hw_cycle_counters_update(common);
399 ar9003_hw_bb_watchdog_dbg_info(ah);
400 spin_unlock(&common->cc_lock);
401
402 if (ar9003_hw_bb_watchdog_check(ah)) {
403 type = RESET_TYPE_BB_WATCHDOG;
404 ath9k_queue_reset(sc, type);
405
406 /*
407 * Increment the ref. counter here so that
408 * interrupts are enabled in the reset routine.
409 */
410 atomic_inc(&ah->intr_ref_cnt);
411 ath_dbg(common, RESET,
412 "BB_WATCHDOG: Skipping interrupts\n");
413 goto out;
414 }
415 }
416
417 if (status & ATH9K_INT_GTT) {
418 sc->gtt_cnt++;
419
420 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
421 type = RESET_TYPE_TX_GTT;
422 ath9k_queue_reset(sc, type);
423 atomic_inc(&ah->intr_ref_cnt);
424 ath_dbg(common, RESET,
425 "GTT: Skipping interrupts\n");
426 goto out;
427 }
428 }
429
430 spin_lock_irqsave(&sc->sc_pm_lock, flags);
431 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
432 /*
433 * TSF sync does not look correct; remain awake to sync with
434 * the next Beacon.
435 */
436 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
437 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
438 }
439 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
440
441 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
442 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
443 ATH9K_INT_RXORN);
444 else
445 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
446
447 if (status & rxmask) {
448 /* Check for high priority Rx first */
449 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
450 (status & ATH9K_INT_RXHP))
451 ath_rx_tasklet(sc, 0, true);
452
453 ath_rx_tasklet(sc, 0, false);
454 }
455
456 if (status & ATH9K_INT_TX) {
457 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
458 /*
459 * For EDMA chips, TX completion is enabled for the
460 * beacon queue, so if a beacon has been transmitted
461 * successfully after a GTT interrupt, the GTT counter
462 * gets reset to zero here.
463 */
464 sc->gtt_cnt = 0;
465
466 ath_tx_edma_tasklet(sc);
467 } else {
468 ath_tx_tasklet(sc);
469 }
470
471 wake_up(&sc->tx_wait);
472 }
473
474 if (status & ATH9K_INT_GENTIMER)
475 ath_gen_timer_isr(sc->sc_ah);
476
477 ath9k_btcoex_handle_interrupt(sc, status);
478
479 /* re-enable hardware interrupt */
480 ath9k_hw_enable_interrupts(ah);
481 out:
482 spin_unlock(&sc->sc_pcu_lock);
483 ath9k_ps_restore(sc);
484 }
485
486 irqreturn_t ath_isr(int irq, void *dev)
487 {
488 #define SCHED_INTR ( \
489 ATH9K_INT_FATAL | \
490 ATH9K_INT_BB_WATCHDOG | \
491 ATH9K_INT_RXORN | \
492 ATH9K_INT_RXEOL | \
493 ATH9K_INT_RX | \
494 ATH9K_INT_RXLP | \
495 ATH9K_INT_RXHP | \
496 ATH9K_INT_TX | \
497 ATH9K_INT_BMISS | \
498 ATH9K_INT_CST | \
499 ATH9K_INT_GTT | \
500 ATH9K_INT_TSFOOR | \
501 ATH9K_INT_GENTIMER | \
502 ATH9K_INT_MCI)
503
504 struct ath_softc *sc = dev;
505 struct ath_hw *ah = sc->sc_ah;
506 struct ath_common *common = ath9k_hw_common(ah);
507 enum ath9k_int status;
508 u32 sync_cause = 0;
509 bool sched = false;
510
511 /*
512 * The hardware is not ready/present, don't
513 * touch anything. Note this can happen early
514 * on if the IRQ is shared.
515 */
516 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
517 return IRQ_NONE;
518
519 /* shared irq, not for us */
520 if (!ath9k_hw_intrpend(ah))
521 return IRQ_NONE;
522
523 /*
524 * Figure out the reason(s) for the interrupt. Note
525 * that the hal returns a pseudo-ISR that may include
526 * bits we haven't explicitly enabled so we mask the
527 * value to insure we only process bits we requested.
528 */
529 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
530 ath9k_debug_sync_cause(sc, sync_cause);
531 status &= ah->imask; /* discard unasked-for bits */
532
533 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
534 return IRQ_HANDLED;
535
536 /*
537 * If there are no status bits set, then this interrupt was not
538 * for me (should have been caught above).
539 */
540 if (!status)
541 return IRQ_NONE;
542
543 /* Cache the status */
544 sc->intrstatus = status;
545
546 if (status & SCHED_INTR)
547 sched = true;
548
549 /*
550 * If a FATAL interrupt is received, we have to reset the chip
551 * immediately.
552 */
553 if (status & ATH9K_INT_FATAL)
554 goto chip_reset;
555
556 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
557 (status & ATH9K_INT_BB_WATCHDOG))
558 goto chip_reset;
559
560 if (status & ATH9K_INT_SWBA)
561 tasklet_schedule(&sc->bcon_tasklet);
562
563 if (status & ATH9K_INT_TXURN)
564 ath9k_hw_updatetxtriglevel(ah, true);
565
566 if (status & ATH9K_INT_RXEOL) {
567 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
568 ath9k_hw_set_interrupts(ah);
569 }
570
571 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
572 if (status & ATH9K_INT_TIM_TIMER) {
573 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
574 goto chip_reset;
575 /* Clear RxAbort bit so that we can
576 * receive frames */
577 ath9k_setpower(sc, ATH9K_PM_AWAKE);
578 spin_lock(&sc->sc_pm_lock);
579 ath9k_hw_setrxabort(sc->sc_ah, 0);
580 sc->ps_flags |= PS_WAIT_FOR_BEACON;
581 spin_unlock(&sc->sc_pm_lock);
582 }
583
584 chip_reset:
585
586 ath_debug_stat_interrupt(sc, status);
587
588 if (sched) {
589 /* turn off every interrupt */
590 ath9k_hw_disable_interrupts(ah);
591 tasklet_schedule(&sc->intr_tq);
592 }
593
594 return IRQ_HANDLED;
595
596 #undef SCHED_INTR
597 }
598
599 /*
600 * This function is called when a HW reset cannot be deferred
601 * and has to be immediate.
602 */
603 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
604 {
605 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
606 int r;
607
608 ath9k_hw_kill_interrupts(sc->sc_ah);
609 set_bit(ATH_OP_HW_RESET, &common->op_flags);
610
611 ath9k_ps_wakeup(sc);
612 r = ath_reset_internal(sc, hchan);
613 ath9k_ps_restore(sc);
614
615 return r;
616 }
617
618 /*
619 * When a HW reset can be deferred, it is added to the
620 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
621 * queueing.
622 */
623 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
624 {
625 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
626 #ifdef CONFIG_ATH9K_DEBUGFS
627 RESET_STAT_INC(sc, type);
628 #endif
629 ath9k_hw_kill_interrupts(sc->sc_ah);
630 set_bit(ATH_OP_HW_RESET, &common->op_flags);
631 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
632 }
633
634 void ath_reset_work(struct work_struct *work)
635 {
636 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
637
638 ath9k_ps_wakeup(sc);
639 ath_reset_internal(sc, NULL);
640 ath9k_ps_restore(sc);
641 }
642
643 /**********************/
644 /* mac80211 callbacks */
645 /**********************/
646
647 static int ath9k_start(struct ieee80211_hw *hw)
648 {
649 struct ath_softc *sc = hw->priv;
650 struct ath_hw *ah = sc->sc_ah;
651 struct ath_common *common = ath9k_hw_common(ah);
652 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
653 struct ath_chanctx *ctx = sc->cur_chan;
654 struct ath9k_channel *init_channel;
655 int r;
656
657 ath_dbg(common, CONFIG,
658 "Starting driver with initial channel: %d MHz\n",
659 curchan->center_freq);
660
661 ath9k_ps_wakeup(sc);
662 mutex_lock(&sc->mutex);
663
664 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
665 sc->cur_chandef = hw->conf.chandef;
666
667 /* Reset SERDES registers */
668 ath9k_hw_configpcipowersave(ah, false);
669
670 /*
671 * The basic interface to setting the hardware in a good
672 * state is ``reset''. On return the hardware is known to
673 * be powered up and with interrupts disabled. This must
674 * be followed by initialization of the appropriate bits
675 * and then setup of the interrupt mask.
676 */
677 spin_lock_bh(&sc->sc_pcu_lock);
678
679 atomic_set(&ah->intr_ref_cnt, -1);
680
681 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
682 if (r) {
683 ath_err(common,
684 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
685 r, curchan->center_freq);
686 ah->reset_power_on = false;
687 }
688
689 /* Setup our intr mask. */
690 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
691 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
692 ATH9K_INT_GLOBAL;
693
694 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
695 ah->imask |= ATH9K_INT_RXHP |
696 ATH9K_INT_RXLP;
697 else
698 ah->imask |= ATH9K_INT_RX;
699
700 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
701 ah->imask |= ATH9K_INT_BB_WATCHDOG;
702
703 /*
704 * Enable GTT interrupts only for AR9003/AR9004 chips
705 * for now.
706 */
707 if (AR_SREV_9300_20_OR_LATER(ah))
708 ah->imask |= ATH9K_INT_GTT;
709
710 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
711 ah->imask |= ATH9K_INT_CST;
712
713 ath_mci_enable(sc);
714
715 clear_bit(ATH_OP_INVALID, &common->op_flags);
716 sc->sc_ah->is_monitoring = false;
717
718 if (!ath_complete_reset(sc, false))
719 ah->reset_power_on = false;
720
721 if (ah->led_pin >= 0)
722 ath9k_hw_set_gpio(ah, ah->led_pin,
723 (ah->config.led_active_high) ? 1 : 0);
724
725 /*
726 * Reset key cache to sane defaults (all entries cleared) instead of
727 * semi-random values after suspend/resume.
728 */
729 ath9k_cmn_init_crypto(sc->sc_ah);
730
731 ath9k_hw_reset_tsf(ah);
732
733 spin_unlock_bh(&sc->sc_pcu_lock);
734
735 mutex_unlock(&sc->mutex);
736
737 ath9k_ps_restore(sc);
738
739 ath9k_rng_start(sc);
740
741 return 0;
742 }
743
744 static void ath9k_tx(struct ieee80211_hw *hw,
745 struct ieee80211_tx_control *control,
746 struct sk_buff *skb)
747 {
748 struct ath_softc *sc = hw->priv;
749 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
750 struct ath_tx_control txctl;
751 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
752 unsigned long flags;
753
754 if (sc->ps_enabled) {
755 /*
756 * mac80211 does not set PM field for normal data frames, so we
757 * need to update that based on the current PS mode.
758 */
759 if (ieee80211_is_data(hdr->frame_control) &&
760 !ieee80211_is_nullfunc(hdr->frame_control) &&
761 !ieee80211_has_pm(hdr->frame_control)) {
762 ath_dbg(common, PS,
763 "Add PM=1 for a TX frame while in PS mode\n");
764 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
765 }
766 }
767
768 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
769 /*
770 * We are using PS-Poll and mac80211 can request TX while in
771 * power save mode. Need to wake up hardware for the TX to be
772 * completed and if needed, also for RX of buffered frames.
773 */
774 ath9k_ps_wakeup(sc);
775 spin_lock_irqsave(&sc->sc_pm_lock, flags);
776 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
777 ath9k_hw_setrxabort(sc->sc_ah, 0);
778 if (ieee80211_is_pspoll(hdr->frame_control)) {
779 ath_dbg(common, PS,
780 "Sending PS-Poll to pick a buffered frame\n");
781 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
782 } else {
783 ath_dbg(common, PS, "Wake up to complete TX\n");
784 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
785 }
786 /*
787 * The actual restore operation will happen only after
788 * the ps_flags bit is cleared. We are just dropping
789 * the ps_usecount here.
790 */
791 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
792 ath9k_ps_restore(sc);
793 }
794
795 /*
796 * Cannot tx while the hardware is in full sleep, it first needs a full
797 * chip reset to recover from that
798 */
799 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
800 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
801 goto exit;
802 }
803
804 memset(&txctl, 0, sizeof(struct ath_tx_control));
805 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
806 txctl.sta = control->sta;
807
808 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
809
810 if (ath_tx_start(hw, skb, &txctl) != 0) {
811 ath_dbg(common, XMIT, "TX failed\n");
812 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
813 goto exit;
814 }
815
816 return;
817 exit:
818 ieee80211_free_txskb(hw, skb);
819 }
820
821 static void ath9k_stop(struct ieee80211_hw *hw)
822 {
823 struct ath_softc *sc = hw->priv;
824 struct ath_hw *ah = sc->sc_ah;
825 struct ath_common *common = ath9k_hw_common(ah);
826 bool prev_idle;
827
828 ath9k_deinit_channel_context(sc);
829
830 ath9k_rng_stop(sc);
831
832 mutex_lock(&sc->mutex);
833
834 ath_cancel_work(sc);
835
836 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
837 ath_dbg(common, ANY, "Device not present\n");
838 mutex_unlock(&sc->mutex);
839 return;
840 }
841
842 /* Ensure HW is awake when we try to shut it down. */
843 ath9k_ps_wakeup(sc);
844
845 spin_lock_bh(&sc->sc_pcu_lock);
846
847 /* prevent tasklets to enable interrupts once we disable them */
848 ah->imask &= ~ATH9K_INT_GLOBAL;
849
850 /* make sure h/w will not generate any interrupt
851 * before setting the invalid flag. */
852 ath9k_hw_disable_interrupts(ah);
853
854 spin_unlock_bh(&sc->sc_pcu_lock);
855
856 /* we can now sync irq and kill any running tasklets, since we already
857 * disabled interrupts and not holding a spin lock */
858 synchronize_irq(sc->irq);
859 tasklet_kill(&sc->intr_tq);
860 tasklet_kill(&sc->bcon_tasklet);
861
862 prev_idle = sc->ps_idle;
863 sc->ps_idle = true;
864
865 spin_lock_bh(&sc->sc_pcu_lock);
866
867 if (ah->led_pin >= 0)
868 ath9k_hw_set_gpio(ah, ah->led_pin,
869 (ah->config.led_active_high) ? 0 : 1);
870
871 ath_prepare_reset(sc);
872
873 if (sc->rx.frag) {
874 dev_kfree_skb_any(sc->rx.frag);
875 sc->rx.frag = NULL;
876 }
877
878 if (!ah->curchan)
879 ah->curchan = ath9k_cmn_get_channel(hw, ah,
880 &sc->cur_chan->chandef);
881
882 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
883
884 set_bit(ATH_OP_INVALID, &common->op_flags);
885
886 ath9k_hw_phy_disable(ah);
887
888 ath9k_hw_configpcipowersave(ah, true);
889
890 spin_unlock_bh(&sc->sc_pcu_lock);
891
892 ath9k_ps_restore(sc);
893
894 sc->ps_idle = prev_idle;
895
896 mutex_unlock(&sc->mutex);
897
898 ath_dbg(common, CONFIG, "Driver halt\n");
899 }
900
901 static bool ath9k_uses_beacons(int type)
902 {
903 switch (type) {
904 case NL80211_IFTYPE_AP:
905 case NL80211_IFTYPE_ADHOC:
906 case NL80211_IFTYPE_MESH_POINT:
907 return true;
908 default:
909 return false;
910 }
911 }
912
913 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
914 u8 *mac, struct ieee80211_vif *vif)
915 {
916 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
917 int i;
918
919 if (iter_data->has_hw_macaddr) {
920 for (i = 0; i < ETH_ALEN; i++)
921 iter_data->mask[i] &=
922 ~(iter_data->hw_macaddr[i] ^ mac[i]);
923 } else {
924 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
925 iter_data->has_hw_macaddr = true;
926 }
927
928 if (!vif->bss_conf.use_short_slot)
929 iter_data->slottime = ATH9K_SLOT_TIME_20;
930
931 switch (vif->type) {
932 case NL80211_IFTYPE_AP:
933 iter_data->naps++;
934 break;
935 case NL80211_IFTYPE_STATION:
936 iter_data->nstations++;
937 if (avp->assoc && !iter_data->primary_sta)
938 iter_data->primary_sta = vif;
939 break;
940 case NL80211_IFTYPE_OCB:
941 iter_data->nocbs++;
942 break;
943 case NL80211_IFTYPE_ADHOC:
944 iter_data->nadhocs++;
945 if (vif->bss_conf.enable_beacon)
946 iter_data->beacons = true;
947 break;
948 case NL80211_IFTYPE_MESH_POINT:
949 iter_data->nmeshes++;
950 if (vif->bss_conf.enable_beacon)
951 iter_data->beacons = true;
952 break;
953 case NL80211_IFTYPE_WDS:
954 iter_data->nwds++;
955 break;
956 default:
957 break;
958 }
959 }
960
961 static void ath9k_update_bssid_mask(struct ath_softc *sc,
962 struct ath_chanctx *ctx,
963 struct ath9k_vif_iter_data *iter_data)
964 {
965 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
966 struct ath_vif *avp;
967 int i;
968
969 if (!ath9k_is_chanctx_enabled())
970 return;
971
972 list_for_each_entry(avp, &ctx->vifs, list) {
973 if (ctx->nvifs_assigned != 1)
974 continue;
975
976 if (!iter_data->has_hw_macaddr)
977 continue;
978
979 ether_addr_copy(common->curbssid, avp->bssid);
980
981 /* perm_addr will be used as the p2p device address. */
982 for (i = 0; i < ETH_ALEN; i++)
983 iter_data->mask[i] &=
984 ~(iter_data->hw_macaddr[i] ^
985 sc->hw->wiphy->perm_addr[i]);
986 }
987 }
988
989 /* Called with sc->mutex held. */
990 void ath9k_calculate_iter_data(struct ath_softc *sc,
991 struct ath_chanctx *ctx,
992 struct ath9k_vif_iter_data *iter_data)
993 {
994 struct ath_vif *avp;
995
996 /*
997 * The hardware will use primary station addr together with the
998 * BSSID mask when matching addresses.
999 */
1000 memset(iter_data, 0, sizeof(*iter_data));
1001 eth_broadcast_addr(iter_data->mask);
1002 iter_data->slottime = ATH9K_SLOT_TIME_9;
1003
1004 list_for_each_entry(avp, &ctx->vifs, list)
1005 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1006
1007 ath9k_update_bssid_mask(sc, ctx, iter_data);
1008 }
1009
1010 static void ath9k_set_assoc_state(struct ath_softc *sc,
1011 struct ieee80211_vif *vif, bool changed)
1012 {
1013 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1014 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1015 unsigned long flags;
1016
1017 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1018
1019 ether_addr_copy(common->curbssid, avp->bssid);
1020 common->curaid = avp->aid;
1021 ath9k_hw_write_associd(sc->sc_ah);
1022
1023 if (changed) {
1024 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1025 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1026
1027 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1028 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1029 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1030 }
1031
1032 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1033 ath9k_mci_update_wlan_channels(sc, false);
1034
1035 ath_dbg(common, CONFIG,
1036 "Primary Station interface: %pM, BSSID: %pM\n",
1037 vif->addr, common->curbssid);
1038 }
1039
1040 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1041 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1042 {
1043 struct ath_hw *ah = sc->sc_ah;
1044 struct ath_common *common = ath9k_hw_common(ah);
1045 struct ieee80211_vif *vif = NULL;
1046
1047 ath9k_ps_wakeup(sc);
1048
1049 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1050 vif = sc->offchannel.scan_vif;
1051 else
1052 vif = sc->offchannel.roc_vif;
1053
1054 if (WARN_ON(!vif))
1055 goto exit;
1056
1057 eth_zero_addr(common->curbssid);
1058 eth_broadcast_addr(common->bssidmask);
1059 memcpy(common->macaddr, vif->addr, ETH_ALEN);
1060 common->curaid = 0;
1061 ah->opmode = vif->type;
1062 ah->imask &= ~ATH9K_INT_SWBA;
1063 ah->imask &= ~ATH9K_INT_TSFOOR;
1064 ah->slottime = ATH9K_SLOT_TIME_9;
1065
1066 ath_hw_setbssidmask(common);
1067 ath9k_hw_setopmode(ah);
1068 ath9k_hw_write_associd(sc->sc_ah);
1069 ath9k_hw_set_interrupts(ah);
1070 ath9k_hw_init_global_settings(ah);
1071
1072 exit:
1073 ath9k_ps_restore(sc);
1074 }
1075 #endif
1076
1077 /* Called with sc->mutex held. */
1078 void ath9k_calculate_summary_state(struct ath_softc *sc,
1079 struct ath_chanctx *ctx)
1080 {
1081 struct ath_hw *ah = sc->sc_ah;
1082 struct ath_common *common = ath9k_hw_common(ah);
1083 struct ath9k_vif_iter_data iter_data;
1084 struct ath_beacon_config *cur_conf;
1085
1086 ath_chanctx_check_active(sc, ctx);
1087
1088 if (ctx != sc->cur_chan)
1089 return;
1090
1091 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1092 if (ctx == &sc->offchannel.chan)
1093 return ath9k_set_offchannel_state(sc);
1094 #endif
1095
1096 ath9k_ps_wakeup(sc);
1097 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1098
1099 if (iter_data.has_hw_macaddr)
1100 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1101
1102 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1103 ath_hw_setbssidmask(common);
1104
1105 if (iter_data.naps > 0) {
1106 cur_conf = &ctx->beacon;
1107 ath9k_hw_set_tsfadjust(ah, true);
1108 ah->opmode = NL80211_IFTYPE_AP;
1109 if (cur_conf->enable_beacon)
1110 iter_data.beacons = true;
1111 } else {
1112 ath9k_hw_set_tsfadjust(ah, false);
1113
1114 if (iter_data.nmeshes)
1115 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1116 else if (iter_data.nocbs)
1117 ah->opmode = NL80211_IFTYPE_OCB;
1118 else if (iter_data.nwds)
1119 ah->opmode = NL80211_IFTYPE_AP;
1120 else if (iter_data.nadhocs)
1121 ah->opmode = NL80211_IFTYPE_ADHOC;
1122 else
1123 ah->opmode = NL80211_IFTYPE_STATION;
1124 }
1125
1126 ath9k_hw_setopmode(ah);
1127
1128 ctx->switch_after_beacon = false;
1129 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1130 ah->imask |= ATH9K_INT_TSFOOR;
1131 else {
1132 ah->imask &= ~ATH9K_INT_TSFOOR;
1133 if (iter_data.naps == 1 && iter_data.beacons)
1134 ctx->switch_after_beacon = true;
1135 }
1136
1137 ah->imask &= ~ATH9K_INT_SWBA;
1138 if (ah->opmode == NL80211_IFTYPE_STATION) {
1139 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1140
1141 if (iter_data.primary_sta) {
1142 iter_data.beacons = true;
1143 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1144 changed);
1145 ctx->primary_sta = iter_data.primary_sta;
1146 } else {
1147 ctx->primary_sta = NULL;
1148 eth_zero_addr(common->curbssid);
1149 common->curaid = 0;
1150 ath9k_hw_write_associd(sc->sc_ah);
1151 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1152 ath9k_mci_update_wlan_channels(sc, true);
1153 }
1154 } else if (iter_data.beacons) {
1155 ah->imask |= ATH9K_INT_SWBA;
1156 }
1157 ath9k_hw_set_interrupts(ah);
1158
1159 if (iter_data.beacons)
1160 set_bit(ATH_OP_BEACONS, &common->op_flags);
1161 else
1162 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1163
1164 if (ah->slottime != iter_data.slottime) {
1165 ah->slottime = iter_data.slottime;
1166 ath9k_hw_init_global_settings(ah);
1167 }
1168
1169 if (iter_data.primary_sta)
1170 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1171 else
1172 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1173
1174 ath_dbg(common, CONFIG,
1175 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1176 common->macaddr, common->curbssid, common->bssidmask);
1177
1178 ath9k_ps_restore(sc);
1179 }
1180
1181 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1182 {
1183 int *power = (int *)data;
1184
1185 if (*power < vif->bss_conf.txpower)
1186 *power = vif->bss_conf.txpower;
1187 }
1188
1189 /* Called with sc->mutex held. */
1190 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1191 {
1192 int power;
1193 struct ath_hw *ah = sc->sc_ah;
1194 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1195
1196 ath9k_ps_wakeup(sc);
1197 if (ah->tpc_enabled) {
1198 power = (vif) ? vif->bss_conf.txpower : -1;
1199 ieee80211_iterate_active_interfaces_atomic(
1200 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1201 ath9k_tpc_vif_iter, &power);
1202 if (power == -1)
1203 power = sc->hw->conf.power_level;
1204 } else {
1205 power = sc->hw->conf.power_level;
1206 }
1207 sc->cur_chan->txpower = 2 * power;
1208 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1209 sc->cur_chan->cur_txpower = reg->max_power_level;
1210 ath9k_ps_restore(sc);
1211 }
1212
1213 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1214 struct ieee80211_vif *vif)
1215 {
1216 int i;
1217
1218 if (!ath9k_is_chanctx_enabled())
1219 return;
1220
1221 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1222 vif->hw_queue[i] = i;
1223
1224 if (vif->type == NL80211_IFTYPE_AP ||
1225 vif->type == NL80211_IFTYPE_MESH_POINT)
1226 vif->cab_queue = hw->queues - 2;
1227 else
1228 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1229 }
1230
1231 static int ath9k_add_interface(struct ieee80211_hw *hw,
1232 struct ieee80211_vif *vif)
1233 {
1234 struct ath_softc *sc = hw->priv;
1235 struct ath_hw *ah = sc->sc_ah;
1236 struct ath_common *common = ath9k_hw_common(ah);
1237 struct ath_vif *avp = (void *)vif->drv_priv;
1238 struct ath_node *an = &avp->mcast_node;
1239
1240 mutex_lock(&sc->mutex);
1241
1242 if (config_enabled(CONFIG_ATH9K_TX99)) {
1243 if (sc->cur_chan->nvifs >= 1) {
1244 mutex_unlock(&sc->mutex);
1245 return -EOPNOTSUPP;
1246 }
1247 sc->tx99_vif = vif;
1248 }
1249
1250 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1251 sc->cur_chan->nvifs++;
1252
1253 if (vif->type == NL80211_IFTYPE_STATION && ath9k_is_chanctx_enabled())
1254 vif->driver_flags |= IEEE80211_VIF_GET_NOA_UPDATE;
1255
1256 if (ath9k_uses_beacons(vif->type))
1257 ath9k_beacon_assign_slot(sc, vif);
1258
1259 avp->vif = vif;
1260 if (!ath9k_is_chanctx_enabled()) {
1261 avp->chanctx = sc->cur_chan;
1262 list_add_tail(&avp->list, &avp->chanctx->vifs);
1263 }
1264
1265 ath9k_calculate_summary_state(sc, avp->chanctx);
1266
1267 ath9k_assign_hw_queues(hw, vif);
1268
1269 ath9k_set_txpower(sc, vif);
1270
1271 an->sc = sc;
1272 an->sta = NULL;
1273 an->vif = vif;
1274 an->no_ps_filter = true;
1275 ath_tx_node_init(sc, an);
1276
1277 mutex_unlock(&sc->mutex);
1278 return 0;
1279 }
1280
1281 static int ath9k_change_interface(struct ieee80211_hw *hw,
1282 struct ieee80211_vif *vif,
1283 enum nl80211_iftype new_type,
1284 bool p2p)
1285 {
1286 struct ath_softc *sc = hw->priv;
1287 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1288 struct ath_vif *avp = (void *)vif->drv_priv;
1289
1290 mutex_lock(&sc->mutex);
1291
1292 if (config_enabled(CONFIG_ATH9K_TX99)) {
1293 mutex_unlock(&sc->mutex);
1294 return -EOPNOTSUPP;
1295 }
1296
1297 ath_dbg(common, CONFIG, "Change Interface\n");
1298
1299 if (ath9k_uses_beacons(vif->type))
1300 ath9k_beacon_remove_slot(sc, vif);
1301
1302 vif->type = new_type;
1303 vif->p2p = p2p;
1304
1305 if (ath9k_uses_beacons(vif->type))
1306 ath9k_beacon_assign_slot(sc, vif);
1307
1308 ath9k_assign_hw_queues(hw, vif);
1309 ath9k_calculate_summary_state(sc, avp->chanctx);
1310
1311 ath9k_set_txpower(sc, vif);
1312
1313 mutex_unlock(&sc->mutex);
1314 return 0;
1315 }
1316
1317 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1318 struct ieee80211_vif *vif)
1319 {
1320 struct ath_softc *sc = hw->priv;
1321 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1322 struct ath_vif *avp = (void *)vif->drv_priv;
1323
1324 ath_dbg(common, CONFIG, "Detach Interface\n");
1325
1326 mutex_lock(&sc->mutex);
1327
1328 ath9k_p2p_remove_vif(sc, vif);
1329
1330 sc->cur_chan->nvifs--;
1331 sc->tx99_vif = NULL;
1332 if (!ath9k_is_chanctx_enabled())
1333 list_del(&avp->list);
1334
1335 if (ath9k_uses_beacons(vif->type))
1336 ath9k_beacon_remove_slot(sc, vif);
1337
1338 ath_tx_node_cleanup(sc, &avp->mcast_node);
1339
1340 ath9k_calculate_summary_state(sc, avp->chanctx);
1341
1342 ath9k_set_txpower(sc, NULL);
1343
1344 mutex_unlock(&sc->mutex);
1345 }
1346
1347 static void ath9k_enable_ps(struct ath_softc *sc)
1348 {
1349 struct ath_hw *ah = sc->sc_ah;
1350 struct ath_common *common = ath9k_hw_common(ah);
1351
1352 if (config_enabled(CONFIG_ATH9K_TX99))
1353 return;
1354
1355 sc->ps_enabled = true;
1356 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1357 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1358 ah->imask |= ATH9K_INT_TIM_TIMER;
1359 ath9k_hw_set_interrupts(ah);
1360 }
1361 ath9k_hw_setrxabort(ah, 1);
1362 }
1363 ath_dbg(common, PS, "PowerSave enabled\n");
1364 }
1365
1366 static void ath9k_disable_ps(struct ath_softc *sc)
1367 {
1368 struct ath_hw *ah = sc->sc_ah;
1369 struct ath_common *common = ath9k_hw_common(ah);
1370
1371 if (config_enabled(CONFIG_ATH9K_TX99))
1372 return;
1373
1374 sc->ps_enabled = false;
1375 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1376 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1377 ath9k_hw_setrxabort(ah, 0);
1378 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1379 PS_WAIT_FOR_CAB |
1380 PS_WAIT_FOR_PSPOLL_DATA |
1381 PS_WAIT_FOR_TX_ACK);
1382 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1383 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1384 ath9k_hw_set_interrupts(ah);
1385 }
1386 }
1387 ath_dbg(common, PS, "PowerSave disabled\n");
1388 }
1389
1390 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1391 {
1392 struct ath_softc *sc = hw->priv;
1393 struct ath_hw *ah = sc->sc_ah;
1394 struct ath_common *common = ath9k_hw_common(ah);
1395 struct ieee80211_conf *conf = &hw->conf;
1396 struct ath_chanctx *ctx = sc->cur_chan;
1397
1398 ath9k_ps_wakeup(sc);
1399 mutex_lock(&sc->mutex);
1400
1401 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1402 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1403 if (sc->ps_idle) {
1404 ath_cancel_work(sc);
1405 ath9k_stop_btcoex(sc);
1406 } else {
1407 ath9k_start_btcoex(sc);
1408 /*
1409 * The chip needs a reset to properly wake up from
1410 * full sleep
1411 */
1412 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1413 }
1414 }
1415
1416 /*
1417 * We just prepare to enable PS. We have to wait until our AP has
1418 * ACK'd our null data frame to disable RX otherwise we'll ignore
1419 * those ACKs and end up retransmitting the same null data frames.
1420 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1421 */
1422 if (changed & IEEE80211_CONF_CHANGE_PS) {
1423 unsigned long flags;
1424 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1425 if (conf->flags & IEEE80211_CONF_PS)
1426 ath9k_enable_ps(sc);
1427 else
1428 ath9k_disable_ps(sc);
1429 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1430 }
1431
1432 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1433 if (conf->flags & IEEE80211_CONF_MONITOR) {
1434 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1435 sc->sc_ah->is_monitoring = true;
1436 } else {
1437 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1438 sc->sc_ah->is_monitoring = false;
1439 }
1440 }
1441
1442 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1443 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1444 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1445 }
1446
1447 mutex_unlock(&sc->mutex);
1448 ath9k_ps_restore(sc);
1449
1450 return 0;
1451 }
1452
1453 #define SUPPORTED_FILTERS \
1454 (FIF_ALLMULTI | \
1455 FIF_CONTROL | \
1456 FIF_PSPOLL | \
1457 FIF_OTHER_BSS | \
1458 FIF_BCN_PRBRESP_PROMISC | \
1459 FIF_PROBE_REQ | \
1460 FIF_FCSFAIL)
1461
1462 /* FIXME: sc->sc_full_reset ? */
1463 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1464 unsigned int changed_flags,
1465 unsigned int *total_flags,
1466 u64 multicast)
1467 {
1468 struct ath_softc *sc = hw->priv;
1469 struct ath_chanctx *ctx;
1470 u32 rfilt;
1471
1472 changed_flags &= SUPPORTED_FILTERS;
1473 *total_flags &= SUPPORTED_FILTERS;
1474
1475 spin_lock_bh(&sc->chan_lock);
1476 ath_for_each_chanctx(sc, ctx)
1477 ctx->rxfilter = *total_flags;
1478 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1479 sc->offchannel.chan.rxfilter = *total_flags;
1480 #endif
1481 spin_unlock_bh(&sc->chan_lock);
1482
1483 ath9k_ps_wakeup(sc);
1484 rfilt = ath_calcrxfilter(sc);
1485 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1486 ath9k_ps_restore(sc);
1487
1488 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1489 rfilt);
1490 }
1491
1492 static int ath9k_sta_add(struct ieee80211_hw *hw,
1493 struct ieee80211_vif *vif,
1494 struct ieee80211_sta *sta)
1495 {
1496 struct ath_softc *sc = hw->priv;
1497 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1498 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1499 struct ieee80211_key_conf ps_key = { };
1500 int key;
1501
1502 ath_node_attach(sc, sta, vif);
1503
1504 if (vif->type != NL80211_IFTYPE_AP &&
1505 vif->type != NL80211_IFTYPE_AP_VLAN)
1506 return 0;
1507
1508 key = ath_key_config(common, vif, sta, &ps_key);
1509 if (key > 0) {
1510 an->ps_key = key;
1511 an->key_idx[0] = key;
1512 }
1513
1514 return 0;
1515 }
1516
1517 static void ath9k_del_ps_key(struct ath_softc *sc,
1518 struct ieee80211_vif *vif,
1519 struct ieee80211_sta *sta)
1520 {
1521 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1522 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1523 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1524
1525 if (!an->ps_key)
1526 return;
1527
1528 ath_key_delete(common, &ps_key);
1529 an->ps_key = 0;
1530 an->key_idx[0] = 0;
1531 }
1532
1533 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1534 struct ieee80211_vif *vif,
1535 struct ieee80211_sta *sta)
1536 {
1537 struct ath_softc *sc = hw->priv;
1538
1539 ath9k_del_ps_key(sc, vif, sta);
1540 ath_node_detach(sc, sta);
1541
1542 return 0;
1543 }
1544
1545 static int ath9k_sta_state(struct ieee80211_hw *hw,
1546 struct ieee80211_vif *vif,
1547 struct ieee80211_sta *sta,
1548 enum ieee80211_sta_state old_state,
1549 enum ieee80211_sta_state new_state)
1550 {
1551 struct ath_softc *sc = hw->priv;
1552 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1553 int ret = 0;
1554
1555 if (old_state == IEEE80211_STA_AUTH &&
1556 new_state == IEEE80211_STA_ASSOC) {
1557 ret = ath9k_sta_add(hw, vif, sta);
1558 ath_dbg(common, CONFIG,
1559 "Add station: %pM\n", sta->addr);
1560 } else if (old_state == IEEE80211_STA_ASSOC &&
1561 new_state == IEEE80211_STA_AUTH) {
1562 ret = ath9k_sta_remove(hw, vif, sta);
1563 ath_dbg(common, CONFIG,
1564 "Remove station: %pM\n", sta->addr);
1565 }
1566
1567 if (ath9k_is_chanctx_enabled()) {
1568 if (vif->type == NL80211_IFTYPE_STATION) {
1569 if (old_state == IEEE80211_STA_ASSOC &&
1570 new_state == IEEE80211_STA_AUTHORIZED)
1571 ath_chanctx_event(sc, vif,
1572 ATH_CHANCTX_EVENT_AUTHORIZED);
1573 }
1574 }
1575
1576 return ret;
1577 }
1578
1579 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1580 struct ath_node *an,
1581 bool set)
1582 {
1583 int i;
1584
1585 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1586 if (!an->key_idx[i])
1587 continue;
1588 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1589 }
1590 }
1591
1592 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1593 struct ieee80211_vif *vif,
1594 enum sta_notify_cmd cmd,
1595 struct ieee80211_sta *sta)
1596 {
1597 struct ath_softc *sc = hw->priv;
1598 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1599
1600 switch (cmd) {
1601 case STA_NOTIFY_SLEEP:
1602 an->sleeping = true;
1603 ath_tx_aggr_sleep(sta, sc, an);
1604 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1605 break;
1606 case STA_NOTIFY_AWAKE:
1607 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1608 an->sleeping = false;
1609 ath_tx_aggr_wakeup(sc, an);
1610 break;
1611 }
1612 }
1613
1614 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1615 struct ieee80211_vif *vif, u16 queue,
1616 const struct ieee80211_tx_queue_params *params)
1617 {
1618 struct ath_softc *sc = hw->priv;
1619 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1620 struct ath_txq *txq;
1621 struct ath9k_tx_queue_info qi;
1622 int ret = 0;
1623
1624 if (queue >= IEEE80211_NUM_ACS)
1625 return 0;
1626
1627 txq = sc->tx.txq_map[queue];
1628
1629 ath9k_ps_wakeup(sc);
1630 mutex_lock(&sc->mutex);
1631
1632 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1633
1634 qi.tqi_aifs = params->aifs;
1635 qi.tqi_cwmin = params->cw_min;
1636 qi.tqi_cwmax = params->cw_max;
1637 qi.tqi_burstTime = params->txop * 32;
1638
1639 ath_dbg(common, CONFIG,
1640 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1641 queue, txq->axq_qnum, params->aifs, params->cw_min,
1642 params->cw_max, params->txop);
1643
1644 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1645 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1646 if (ret)
1647 ath_err(common, "TXQ Update failed\n");
1648
1649 mutex_unlock(&sc->mutex);
1650 ath9k_ps_restore(sc);
1651
1652 return ret;
1653 }
1654
1655 static int ath9k_set_key(struct ieee80211_hw *hw,
1656 enum set_key_cmd cmd,
1657 struct ieee80211_vif *vif,
1658 struct ieee80211_sta *sta,
1659 struct ieee80211_key_conf *key)
1660 {
1661 struct ath_softc *sc = hw->priv;
1662 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1663 struct ath_node *an = NULL;
1664 int ret = 0, i;
1665
1666 if (ath9k_modparam_nohwcrypt)
1667 return -ENOSPC;
1668
1669 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1670 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1671 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1672 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1673 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1674 /*
1675 * For now, disable hw crypto for the RSN IBSS group keys. This
1676 * could be optimized in the future to use a modified key cache
1677 * design to support per-STA RX GTK, but until that gets
1678 * implemented, use of software crypto for group addressed
1679 * frames is a acceptable to allow RSN IBSS to be used.
1680 */
1681 return -EOPNOTSUPP;
1682 }
1683
1684 mutex_lock(&sc->mutex);
1685 ath9k_ps_wakeup(sc);
1686 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1687 if (sta)
1688 an = (struct ath_node *)sta->drv_priv;
1689
1690 switch (cmd) {
1691 case SET_KEY:
1692 if (sta)
1693 ath9k_del_ps_key(sc, vif, sta);
1694
1695 key->hw_key_idx = 0;
1696 ret = ath_key_config(common, vif, sta, key);
1697 if (ret >= 0) {
1698 key->hw_key_idx = ret;
1699 /* push IV and Michael MIC generation to stack */
1700 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1701 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1702 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1703 if (sc->sc_ah->sw_mgmt_crypto_tx &&
1704 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1705 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1706 ret = 0;
1707 }
1708 if (an && key->hw_key_idx) {
1709 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1710 if (an->key_idx[i])
1711 continue;
1712 an->key_idx[i] = key->hw_key_idx;
1713 break;
1714 }
1715 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1716 }
1717 break;
1718 case DISABLE_KEY:
1719 ath_key_delete(common, key);
1720 if (an) {
1721 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1722 if (an->key_idx[i] != key->hw_key_idx)
1723 continue;
1724 an->key_idx[i] = 0;
1725 break;
1726 }
1727 }
1728 key->hw_key_idx = 0;
1729 break;
1730 default:
1731 ret = -EINVAL;
1732 }
1733
1734 ath9k_ps_restore(sc);
1735 mutex_unlock(&sc->mutex);
1736
1737 return ret;
1738 }
1739
1740 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1741 struct ieee80211_vif *vif,
1742 struct ieee80211_bss_conf *bss_conf,
1743 u32 changed)
1744 {
1745 #define CHECK_ANI \
1746 (BSS_CHANGED_ASSOC | \
1747 BSS_CHANGED_IBSS | \
1748 BSS_CHANGED_BEACON_ENABLED)
1749
1750 struct ath_softc *sc = hw->priv;
1751 struct ath_hw *ah = sc->sc_ah;
1752 struct ath_common *common = ath9k_hw_common(ah);
1753 struct ath_vif *avp = (void *)vif->drv_priv;
1754 int slottime;
1755
1756 ath9k_ps_wakeup(sc);
1757 mutex_lock(&sc->mutex);
1758
1759 if (changed & BSS_CHANGED_ASSOC) {
1760 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1761 bss_conf->bssid, bss_conf->assoc);
1762
1763 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1764 avp->aid = bss_conf->aid;
1765 avp->assoc = bss_conf->assoc;
1766
1767 ath9k_calculate_summary_state(sc, avp->chanctx);
1768 }
1769
1770 if ((changed & BSS_CHANGED_IBSS) ||
1771 (changed & BSS_CHANGED_OCB)) {
1772 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1773 common->curaid = bss_conf->aid;
1774 ath9k_hw_write_associd(sc->sc_ah);
1775 }
1776
1777 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1778 (changed & BSS_CHANGED_BEACON_INT) ||
1779 (changed & BSS_CHANGED_BEACON_INFO)) {
1780 ath9k_beacon_config(sc, vif, changed);
1781 if (changed & BSS_CHANGED_BEACON_ENABLED)
1782 ath9k_calculate_summary_state(sc, avp->chanctx);
1783 }
1784
1785 if ((avp->chanctx == sc->cur_chan) &&
1786 (changed & BSS_CHANGED_ERP_SLOT)) {
1787 if (bss_conf->use_short_slot)
1788 slottime = 9;
1789 else
1790 slottime = 20;
1791 if (vif->type == NL80211_IFTYPE_AP) {
1792 /*
1793 * Defer update, so that connected stations can adjust
1794 * their settings at the same time.
1795 * See beacon.c for more details
1796 */
1797 sc->beacon.slottime = slottime;
1798 sc->beacon.updateslot = UPDATE;
1799 } else {
1800 ah->slottime = slottime;
1801 ath9k_hw_init_global_settings(ah);
1802 }
1803 }
1804
1805 if (changed & BSS_CHANGED_P2P_PS)
1806 ath9k_p2p_bss_info_changed(sc, vif);
1807
1808 if (changed & CHECK_ANI)
1809 ath_check_ani(sc);
1810
1811 if (changed & BSS_CHANGED_TXPOWER) {
1812 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1813 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1814 ath9k_set_txpower(sc, vif);
1815 }
1816
1817 mutex_unlock(&sc->mutex);
1818 ath9k_ps_restore(sc);
1819
1820 #undef CHECK_ANI
1821 }
1822
1823 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1824 {
1825 struct ath_softc *sc = hw->priv;
1826 u64 tsf;
1827
1828 mutex_lock(&sc->mutex);
1829 ath9k_ps_wakeup(sc);
1830 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1831 ath9k_ps_restore(sc);
1832 mutex_unlock(&sc->mutex);
1833
1834 return tsf;
1835 }
1836
1837 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1838 struct ieee80211_vif *vif,
1839 u64 tsf)
1840 {
1841 struct ath_softc *sc = hw->priv;
1842
1843 mutex_lock(&sc->mutex);
1844 ath9k_ps_wakeup(sc);
1845 ath9k_hw_settsf64(sc->sc_ah, tsf);
1846 ath9k_ps_restore(sc);
1847 mutex_unlock(&sc->mutex);
1848 }
1849
1850 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1851 {
1852 struct ath_softc *sc = hw->priv;
1853
1854 mutex_lock(&sc->mutex);
1855
1856 ath9k_ps_wakeup(sc);
1857 ath9k_hw_reset_tsf(sc->sc_ah);
1858 ath9k_ps_restore(sc);
1859
1860 mutex_unlock(&sc->mutex);
1861 }
1862
1863 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1864 struct ieee80211_vif *vif,
1865 struct ieee80211_ampdu_params *params)
1866 {
1867 struct ath_softc *sc = hw->priv;
1868 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1869 bool flush = false;
1870 int ret = 0;
1871 struct ieee80211_sta *sta = params->sta;
1872 enum ieee80211_ampdu_mlme_action action = params->action;
1873 u16 tid = params->tid;
1874 u16 *ssn = &params->ssn;
1875
1876 mutex_lock(&sc->mutex);
1877
1878 switch (action) {
1879 case IEEE80211_AMPDU_RX_START:
1880 break;
1881 case IEEE80211_AMPDU_RX_STOP:
1882 break;
1883 case IEEE80211_AMPDU_TX_START:
1884 if (ath9k_is_chanctx_enabled()) {
1885 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
1886 ret = -EBUSY;
1887 break;
1888 }
1889 }
1890 ath9k_ps_wakeup(sc);
1891 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1892 if (!ret)
1893 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1894 ath9k_ps_restore(sc);
1895 break;
1896 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1897 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1898 flush = true;
1899 case IEEE80211_AMPDU_TX_STOP_CONT:
1900 ath9k_ps_wakeup(sc);
1901 ath_tx_aggr_stop(sc, sta, tid);
1902 if (!flush)
1903 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1904 ath9k_ps_restore(sc);
1905 break;
1906 case IEEE80211_AMPDU_TX_OPERATIONAL:
1907 ath9k_ps_wakeup(sc);
1908 ath_tx_aggr_resume(sc, sta, tid);
1909 ath9k_ps_restore(sc);
1910 break;
1911 default:
1912 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1913 }
1914
1915 mutex_unlock(&sc->mutex);
1916
1917 return ret;
1918 }
1919
1920 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1921 struct survey_info *survey)
1922 {
1923 struct ath_softc *sc = hw->priv;
1924 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1925 struct ieee80211_supported_band *sband;
1926 struct ieee80211_channel *chan;
1927 int pos;
1928
1929 if (config_enabled(CONFIG_ATH9K_TX99))
1930 return -EOPNOTSUPP;
1931
1932 spin_lock_bh(&common->cc_lock);
1933 if (idx == 0)
1934 ath_update_survey_stats(sc);
1935
1936 sband = hw->wiphy->bands[NL80211_BAND_2GHZ];
1937 if (sband && idx >= sband->n_channels) {
1938 idx -= sband->n_channels;
1939 sband = NULL;
1940 }
1941
1942 if (!sband)
1943 sband = hw->wiphy->bands[NL80211_BAND_5GHZ];
1944
1945 if (!sband || idx >= sband->n_channels) {
1946 spin_unlock_bh(&common->cc_lock);
1947 return -ENOENT;
1948 }
1949
1950 chan = &sband->channels[idx];
1951 pos = chan->hw_value;
1952 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1953 survey->channel = chan;
1954 spin_unlock_bh(&common->cc_lock);
1955
1956 return 0;
1957 }
1958
1959 static void ath9k_enable_dynack(struct ath_softc *sc)
1960 {
1961 #ifdef CONFIG_ATH9K_DYNACK
1962 u32 rfilt;
1963 struct ath_hw *ah = sc->sc_ah;
1964
1965 ath_dynack_reset(ah);
1966
1967 ah->dynack.enabled = true;
1968 rfilt = ath_calcrxfilter(sc);
1969 ath9k_hw_setrxfilter(ah, rfilt);
1970 #endif
1971 }
1972
1973 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
1974 s16 coverage_class)
1975 {
1976 struct ath_softc *sc = hw->priv;
1977 struct ath_hw *ah = sc->sc_ah;
1978
1979 if (config_enabled(CONFIG_ATH9K_TX99))
1980 return;
1981
1982 mutex_lock(&sc->mutex);
1983
1984 if (coverage_class >= 0) {
1985 ah->coverage_class = coverage_class;
1986 if (ah->dynack.enabled) {
1987 u32 rfilt;
1988
1989 ah->dynack.enabled = false;
1990 rfilt = ath_calcrxfilter(sc);
1991 ath9k_hw_setrxfilter(ah, rfilt);
1992 }
1993 ath9k_ps_wakeup(sc);
1994 ath9k_hw_init_global_settings(ah);
1995 ath9k_ps_restore(sc);
1996 } else if (!ah->dynack.enabled) {
1997 ath9k_enable_dynack(sc);
1998 }
1999
2000 mutex_unlock(&sc->mutex);
2001 }
2002
2003 static bool ath9k_has_tx_pending(struct ath_softc *sc,
2004 bool sw_pending)
2005 {
2006 int i, npend = 0;
2007
2008 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2009 if (!ATH_TXQ_SETUP(sc, i))
2010 continue;
2011
2012 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2013 sw_pending);
2014 if (npend)
2015 break;
2016 }
2017
2018 return !!npend;
2019 }
2020
2021 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2022 u32 queues, bool drop)
2023 {
2024 struct ath_softc *sc = hw->priv;
2025 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2026
2027 if (ath9k_is_chanctx_enabled()) {
2028 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2029 goto flush;
2030
2031 /*
2032 * If MCC is active, extend the flush timeout
2033 * and wait for the HW/SW queues to become
2034 * empty. This needs to be done outside the
2035 * sc->mutex lock to allow the channel scheduler
2036 * to switch channel contexts.
2037 *
2038 * The vif queues have been stopped in mac80211,
2039 * so there won't be any incoming frames.
2040 */
2041 __ath9k_flush(hw, queues, drop, true, true);
2042 return;
2043 }
2044 flush:
2045 mutex_lock(&sc->mutex);
2046 __ath9k_flush(hw, queues, drop, true, false);
2047 mutex_unlock(&sc->mutex);
2048 }
2049
2050 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2051 bool sw_pending, bool timeout_override)
2052 {
2053 struct ath_softc *sc = hw->priv;
2054 struct ath_hw *ah = sc->sc_ah;
2055 struct ath_common *common = ath9k_hw_common(ah);
2056 int timeout;
2057 bool drain_txq;
2058
2059 cancel_delayed_work_sync(&sc->tx_complete_work);
2060
2061 if (ah->ah_flags & AH_UNPLUGGED) {
2062 ath_dbg(common, ANY, "Device has been unplugged!\n");
2063 return;
2064 }
2065
2066 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2067 ath_dbg(common, ANY, "Device not present\n");
2068 return;
2069 }
2070
2071 spin_lock_bh(&sc->chan_lock);
2072 if (timeout_override)
2073 timeout = HZ / 5;
2074 else
2075 timeout = sc->cur_chan->flush_timeout;
2076 spin_unlock_bh(&sc->chan_lock);
2077
2078 ath_dbg(common, CHAN_CTX,
2079 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2080
2081 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2082 timeout) > 0)
2083 drop = false;
2084
2085 if (drop) {
2086 ath9k_ps_wakeup(sc);
2087 spin_lock_bh(&sc->sc_pcu_lock);
2088 drain_txq = ath_drain_all_txq(sc);
2089 spin_unlock_bh(&sc->sc_pcu_lock);
2090
2091 if (!drain_txq)
2092 ath_reset(sc, NULL);
2093
2094 ath9k_ps_restore(sc);
2095 }
2096
2097 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2098 }
2099
2100 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2101 {
2102 struct ath_softc *sc = hw->priv;
2103
2104 return ath9k_has_tx_pending(sc, true);
2105 }
2106
2107 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2108 {
2109 struct ath_softc *sc = hw->priv;
2110 struct ath_hw *ah = sc->sc_ah;
2111 struct ieee80211_vif *vif;
2112 struct ath_vif *avp;
2113 struct ath_buf *bf;
2114 struct ath_tx_status ts;
2115 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2116 int status;
2117
2118 vif = sc->beacon.bslot[0];
2119 if (!vif)
2120 return 0;
2121
2122 if (!vif->bss_conf.enable_beacon)
2123 return 0;
2124
2125 avp = (void *)vif->drv_priv;
2126
2127 if (!sc->beacon.tx_processed && !edma) {
2128 tasklet_disable(&sc->bcon_tasklet);
2129
2130 bf = avp->av_bcbuf;
2131 if (!bf || !bf->bf_mpdu)
2132 goto skip;
2133
2134 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2135 if (status == -EINPROGRESS)
2136 goto skip;
2137
2138 sc->beacon.tx_processed = true;
2139 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2140
2141 skip:
2142 tasklet_enable(&sc->bcon_tasklet);
2143 }
2144
2145 return sc->beacon.tx_last;
2146 }
2147
2148 static int ath9k_get_stats(struct ieee80211_hw *hw,
2149 struct ieee80211_low_level_stats *stats)
2150 {
2151 struct ath_softc *sc = hw->priv;
2152 struct ath_hw *ah = sc->sc_ah;
2153 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2154
2155 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2156 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2157 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2158 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2159 return 0;
2160 }
2161
2162 static u32 fill_chainmask(u32 cap, u32 new)
2163 {
2164 u32 filled = 0;
2165 int i;
2166
2167 for (i = 0; cap && new; i++, cap >>= 1) {
2168 if (!(cap & BIT(0)))
2169 continue;
2170
2171 if (new & BIT(0))
2172 filled |= BIT(i);
2173
2174 new >>= 1;
2175 }
2176
2177 return filled;
2178 }
2179
2180 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2181 {
2182 if (AR_SREV_9300_20_OR_LATER(ah))
2183 return true;
2184
2185 switch (val & 0x7) {
2186 case 0x1:
2187 case 0x3:
2188 case 0x7:
2189 return true;
2190 case 0x2:
2191 return (ah->caps.rx_chainmask == 1);
2192 default:
2193 return false;
2194 }
2195 }
2196
2197 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2198 {
2199 struct ath_softc *sc = hw->priv;
2200 struct ath_hw *ah = sc->sc_ah;
2201
2202 if (ah->caps.rx_chainmask != 1)
2203 rx_ant |= tx_ant;
2204
2205 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2206 return -EINVAL;
2207
2208 sc->ant_rx = rx_ant;
2209 sc->ant_tx = tx_ant;
2210
2211 if (ah->caps.rx_chainmask == 1)
2212 return 0;
2213
2214 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2215 if (AR_SREV_9100(ah))
2216 ah->rxchainmask = 0x7;
2217 else
2218 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2219
2220 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2221 ath9k_cmn_reload_chainmask(ah);
2222
2223 return 0;
2224 }
2225
2226 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2227 {
2228 struct ath_softc *sc = hw->priv;
2229
2230 *tx_ant = sc->ant_tx;
2231 *rx_ant = sc->ant_rx;
2232 return 0;
2233 }
2234
2235 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2236 struct ieee80211_vif *vif,
2237 const u8 *mac_addr)
2238 {
2239 struct ath_softc *sc = hw->priv;
2240 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2241 set_bit(ATH_OP_SCANNING, &common->op_flags);
2242 }
2243
2244 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2245 struct ieee80211_vif *vif)
2246 {
2247 struct ath_softc *sc = hw->priv;
2248 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2249 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2250 }
2251
2252 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2253
2254 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2255 {
2256 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2257
2258 if (sc->offchannel.roc_vif) {
2259 ath_dbg(common, CHAN_CTX,
2260 "%s: Aborting RoC\n", __func__);
2261
2262 del_timer_sync(&sc->offchannel.timer);
2263 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2264 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2265 }
2266
2267 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2268 ath_dbg(common, CHAN_CTX,
2269 "%s: Aborting HW scan\n", __func__);
2270
2271 del_timer_sync(&sc->offchannel.timer);
2272 ath_scan_complete(sc, true);
2273 }
2274 }
2275
2276 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2277 struct ieee80211_scan_request *hw_req)
2278 {
2279 struct cfg80211_scan_request *req = &hw_req->req;
2280 struct ath_softc *sc = hw->priv;
2281 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2282 int ret = 0;
2283
2284 mutex_lock(&sc->mutex);
2285
2286 if (WARN_ON(sc->offchannel.scan_req)) {
2287 ret = -EBUSY;
2288 goto out;
2289 }
2290
2291 ath9k_ps_wakeup(sc);
2292 set_bit(ATH_OP_SCANNING, &common->op_flags);
2293 sc->offchannel.scan_vif = vif;
2294 sc->offchannel.scan_req = req;
2295 sc->offchannel.scan_idx = 0;
2296
2297 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2298 vif->addr);
2299
2300 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2301 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2302 ath_offchannel_next(sc);
2303 }
2304
2305 out:
2306 mutex_unlock(&sc->mutex);
2307
2308 return ret;
2309 }
2310
2311 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2312 struct ieee80211_vif *vif)
2313 {
2314 struct ath_softc *sc = hw->priv;
2315 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2316
2317 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2318
2319 mutex_lock(&sc->mutex);
2320 del_timer_sync(&sc->offchannel.timer);
2321 ath_scan_complete(sc, true);
2322 mutex_unlock(&sc->mutex);
2323 }
2324
2325 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2326 struct ieee80211_vif *vif,
2327 struct ieee80211_channel *chan, int duration,
2328 enum ieee80211_roc_type type)
2329 {
2330 struct ath_softc *sc = hw->priv;
2331 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2332 int ret = 0;
2333
2334 mutex_lock(&sc->mutex);
2335
2336 if (WARN_ON(sc->offchannel.roc_vif)) {
2337 ret = -EBUSY;
2338 goto out;
2339 }
2340
2341 ath9k_ps_wakeup(sc);
2342 sc->offchannel.roc_vif = vif;
2343 sc->offchannel.roc_chan = chan;
2344 sc->offchannel.roc_duration = duration;
2345
2346 ath_dbg(common, CHAN_CTX,
2347 "RoC request on vif: %pM, type: %d duration: %d\n",
2348 vif->addr, type, duration);
2349
2350 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2351 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2352 ath_offchannel_next(sc);
2353 }
2354
2355 out:
2356 mutex_unlock(&sc->mutex);
2357
2358 return ret;
2359 }
2360
2361 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2362 {
2363 struct ath_softc *sc = hw->priv;
2364 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2365
2366 mutex_lock(&sc->mutex);
2367
2368 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2369 del_timer_sync(&sc->offchannel.timer);
2370
2371 if (sc->offchannel.roc_vif) {
2372 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2373 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2374 }
2375
2376 mutex_unlock(&sc->mutex);
2377
2378 return 0;
2379 }
2380
2381 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2382 struct ieee80211_chanctx_conf *conf)
2383 {
2384 struct ath_softc *sc = hw->priv;
2385 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2386 struct ath_chanctx *ctx, **ptr;
2387 int pos;
2388
2389 mutex_lock(&sc->mutex);
2390
2391 ath_for_each_chanctx(sc, ctx) {
2392 if (ctx->assigned)
2393 continue;
2394
2395 ptr = (void *) conf->drv_priv;
2396 *ptr = ctx;
2397 ctx->assigned = true;
2398 pos = ctx - &sc->chanctx[0];
2399 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2400
2401 ath_dbg(common, CHAN_CTX,
2402 "Add channel context: %d MHz\n",
2403 conf->def.chan->center_freq);
2404
2405 ath_chanctx_set_channel(sc, ctx, &conf->def);
2406
2407 mutex_unlock(&sc->mutex);
2408 return 0;
2409 }
2410
2411 mutex_unlock(&sc->mutex);
2412 return -ENOSPC;
2413 }
2414
2415
2416 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2417 struct ieee80211_chanctx_conf *conf)
2418 {
2419 struct ath_softc *sc = hw->priv;
2420 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2421 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2422
2423 mutex_lock(&sc->mutex);
2424
2425 ath_dbg(common, CHAN_CTX,
2426 "Remove channel context: %d MHz\n",
2427 conf->def.chan->center_freq);
2428
2429 ctx->assigned = false;
2430 ctx->hw_queue_base = 0;
2431 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2432
2433 mutex_unlock(&sc->mutex);
2434 }
2435
2436 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2437 struct ieee80211_chanctx_conf *conf,
2438 u32 changed)
2439 {
2440 struct ath_softc *sc = hw->priv;
2441 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2442 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2443
2444 mutex_lock(&sc->mutex);
2445 ath_dbg(common, CHAN_CTX,
2446 "Change channel context: %d MHz\n",
2447 conf->def.chan->center_freq);
2448 ath_chanctx_set_channel(sc, ctx, &conf->def);
2449 mutex_unlock(&sc->mutex);
2450 }
2451
2452 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2453 struct ieee80211_vif *vif,
2454 struct ieee80211_chanctx_conf *conf)
2455 {
2456 struct ath_softc *sc = hw->priv;
2457 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2458 struct ath_vif *avp = (void *)vif->drv_priv;
2459 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2460 int i;
2461
2462 ath9k_cancel_pending_offchannel(sc);
2463
2464 mutex_lock(&sc->mutex);
2465
2466 ath_dbg(common, CHAN_CTX,
2467 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2468 vif->addr, vif->type, vif->p2p,
2469 conf->def.chan->center_freq);
2470
2471 avp->chanctx = ctx;
2472 ctx->nvifs_assigned++;
2473 list_add_tail(&avp->list, &ctx->vifs);
2474 ath9k_calculate_summary_state(sc, ctx);
2475 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2476 vif->hw_queue[i] = ctx->hw_queue_base + i;
2477
2478 mutex_unlock(&sc->mutex);
2479
2480 return 0;
2481 }
2482
2483 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2484 struct ieee80211_vif *vif,
2485 struct ieee80211_chanctx_conf *conf)
2486 {
2487 struct ath_softc *sc = hw->priv;
2488 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2489 struct ath_vif *avp = (void *)vif->drv_priv;
2490 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2491 int ac;
2492
2493 ath9k_cancel_pending_offchannel(sc);
2494
2495 mutex_lock(&sc->mutex);
2496
2497 ath_dbg(common, CHAN_CTX,
2498 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2499 vif->addr, vif->type, vif->p2p,
2500 conf->def.chan->center_freq);
2501
2502 avp->chanctx = NULL;
2503 ctx->nvifs_assigned--;
2504 list_del(&avp->list);
2505 ath9k_calculate_summary_state(sc, ctx);
2506 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2507 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2508
2509 mutex_unlock(&sc->mutex);
2510 }
2511
2512 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2513 struct ieee80211_vif *vif)
2514 {
2515 struct ath_softc *sc = hw->priv;
2516 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2517 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2518 struct ath_beacon_config *cur_conf;
2519 struct ath_chanctx *go_ctx;
2520 unsigned long timeout;
2521 bool changed = false;
2522 u32 beacon_int;
2523
2524 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2525 return;
2526
2527 if (!avp->chanctx)
2528 return;
2529
2530 mutex_lock(&sc->mutex);
2531
2532 spin_lock_bh(&sc->chan_lock);
2533 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2534 changed = true;
2535 spin_unlock_bh(&sc->chan_lock);
2536
2537 if (!changed)
2538 goto out;
2539
2540 ath9k_cancel_pending_offchannel(sc);
2541
2542 go_ctx = ath_is_go_chanctx_present(sc);
2543
2544 if (go_ctx) {
2545 /*
2546 * Wait till the GO interface gets a chance
2547 * to send out an NoA.
2548 */
2549 spin_lock_bh(&sc->chan_lock);
2550 sc->sched.mgd_prepare_tx = true;
2551 cur_conf = &go_ctx->beacon;
2552 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2553 spin_unlock_bh(&sc->chan_lock);
2554
2555 timeout = usecs_to_jiffies(beacon_int * 2);
2556 init_completion(&sc->go_beacon);
2557
2558 mutex_unlock(&sc->mutex);
2559
2560 if (wait_for_completion_timeout(&sc->go_beacon,
2561 timeout) == 0) {
2562 ath_dbg(common, CHAN_CTX,
2563 "Failed to send new NoA\n");
2564
2565 spin_lock_bh(&sc->chan_lock);
2566 sc->sched.mgd_prepare_tx = false;
2567 spin_unlock_bh(&sc->chan_lock);
2568 }
2569
2570 mutex_lock(&sc->mutex);
2571 }
2572
2573 ath_dbg(common, CHAN_CTX,
2574 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2575 __func__, vif->addr);
2576
2577 spin_lock_bh(&sc->chan_lock);
2578 sc->next_chan = avp->chanctx;
2579 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2580 spin_unlock_bh(&sc->chan_lock);
2581
2582 ath_chanctx_set_next(sc, true);
2583 out:
2584 mutex_unlock(&sc->mutex);
2585 }
2586
2587 void ath9k_fill_chanctx_ops(void)
2588 {
2589 if (!ath9k_is_chanctx_enabled())
2590 return;
2591
2592 ath9k_ops.hw_scan = ath9k_hw_scan;
2593 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2594 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2595 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2596 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2597 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2598 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2599 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2600 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2601 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2602 }
2603
2604 #endif
2605
2606 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2607 int *dbm)
2608 {
2609 struct ath_softc *sc = hw->priv;
2610 struct ath_vif *avp = (void *)vif->drv_priv;
2611
2612 mutex_lock(&sc->mutex);
2613 if (avp->chanctx)
2614 *dbm = avp->chanctx->cur_txpower;
2615 else
2616 *dbm = sc->cur_chan->cur_txpower;
2617 mutex_unlock(&sc->mutex);
2618
2619 *dbm /= 2;
2620
2621 return 0;
2622 }
2623
2624 struct ieee80211_ops ath9k_ops = {
2625 .tx = ath9k_tx,
2626 .start = ath9k_start,
2627 .stop = ath9k_stop,
2628 .add_interface = ath9k_add_interface,
2629 .change_interface = ath9k_change_interface,
2630 .remove_interface = ath9k_remove_interface,
2631 .config = ath9k_config,
2632 .configure_filter = ath9k_configure_filter,
2633 .sta_state = ath9k_sta_state,
2634 .sta_notify = ath9k_sta_notify,
2635 .conf_tx = ath9k_conf_tx,
2636 .bss_info_changed = ath9k_bss_info_changed,
2637 .set_key = ath9k_set_key,
2638 .get_tsf = ath9k_get_tsf,
2639 .set_tsf = ath9k_set_tsf,
2640 .reset_tsf = ath9k_reset_tsf,
2641 .ampdu_action = ath9k_ampdu_action,
2642 .get_survey = ath9k_get_survey,
2643 .rfkill_poll = ath9k_rfkill_poll_state,
2644 .set_coverage_class = ath9k_set_coverage_class,
2645 .flush = ath9k_flush,
2646 .tx_frames_pending = ath9k_tx_frames_pending,
2647 .tx_last_beacon = ath9k_tx_last_beacon,
2648 .release_buffered_frames = ath9k_release_buffered_frames,
2649 .get_stats = ath9k_get_stats,
2650 .set_antenna = ath9k_set_antenna,
2651 .get_antenna = ath9k_get_antenna,
2652
2653 #ifdef CONFIG_ATH9K_WOW
2654 .suspend = ath9k_suspend,
2655 .resume = ath9k_resume,
2656 .set_wakeup = ath9k_set_wakeup,
2657 #endif
2658
2659 #ifdef CONFIG_ATH9K_DEBUGFS
2660 .get_et_sset_count = ath9k_get_et_sset_count,
2661 .get_et_stats = ath9k_get_et_stats,
2662 .get_et_strings = ath9k_get_et_strings,
2663 #endif
2664
2665 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2666 .sta_add_debugfs = ath9k_sta_add_debugfs,
2667 #endif
2668 .sw_scan_start = ath9k_sw_scan_start,
2669 .sw_scan_complete = ath9k_sw_scan_complete,
2670 .get_txpower = ath9k_get_txpower,
2671 };
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