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Merge branch 'l3mdev_saddr_op'
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23 {
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55 }
56
57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
58 bool sw_pending)
59 {
60 bool pending = false;
61
62 spin_lock_bh(&txq->axq_lock);
63
64 if (txq->axq_depth) {
65 pending = true;
66 goto out;
67 }
68
69 if (!sw_pending)
70 goto out;
71
72 if (txq->mac80211_qnum >= 0) {
73 struct list_head *list;
74
75 list = &sc->cur_chan->acq[txq->mac80211_qnum];
76 if (!list_empty(list))
77 pending = true;
78 }
79 out:
80 spin_unlock_bh(&txq->axq_lock);
81 return pending;
82 }
83
84 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
85 {
86 unsigned long flags;
87 bool ret;
88
89 spin_lock_irqsave(&sc->sc_pm_lock, flags);
90 ret = ath9k_hw_setpower(sc->sc_ah, mode);
91 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
92
93 return ret;
94 }
95
96 void ath_ps_full_sleep(unsigned long data)
97 {
98 struct ath_softc *sc = (struct ath_softc *) data;
99 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
100 bool reset;
101
102 spin_lock(&common->cc_lock);
103 ath_hw_cycle_counters_update(common);
104 spin_unlock(&common->cc_lock);
105
106 ath9k_hw_setrxabort(sc->sc_ah, 1);
107 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
108
109 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
110 }
111
112 void ath9k_ps_wakeup(struct ath_softc *sc)
113 {
114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
115 unsigned long flags;
116 enum ath9k_power_mode power_mode;
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (++sc->ps_usecount != 1)
120 goto unlock;
121
122 del_timer_sync(&sc->sleep_timer);
123 power_mode = sc->sc_ah->power_mode;
124 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
125
126 /*
127 * While the hardware is asleep, the cycle counters contain no
128 * useful data. Better clear them now so that they don't mess up
129 * survey data results.
130 */
131 if (power_mode != ATH9K_PM_AWAKE) {
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
135 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
136 spin_unlock(&common->cc_lock);
137 }
138
139 unlock:
140 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
141 }
142
143 void ath9k_ps_restore(struct ath_softc *sc)
144 {
145 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
146 enum ath9k_power_mode mode;
147 unsigned long flags;
148
149 spin_lock_irqsave(&sc->sc_pm_lock, flags);
150 if (--sc->ps_usecount != 0)
151 goto unlock;
152
153 if (sc->ps_idle) {
154 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
155 goto unlock;
156 }
157
158 if (sc->ps_enabled &&
159 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
160 PS_WAIT_FOR_CAB |
161 PS_WAIT_FOR_PSPOLL_DATA |
162 PS_WAIT_FOR_TX_ACK |
163 PS_WAIT_FOR_ANI))) {
164 mode = ATH9K_PM_NETWORK_SLEEP;
165 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
166 ath9k_btcoex_stop_gen_timer(sc);
167 } else {
168 goto unlock;
169 }
170
171 spin_lock(&common->cc_lock);
172 ath_hw_cycle_counters_update(common);
173 spin_unlock(&common->cc_lock);
174
175 ath9k_hw_setpower(sc->sc_ah, mode);
176
177 unlock:
178 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
179 }
180
181 static void __ath_cancel_work(struct ath_softc *sc)
182 {
183 cancel_work_sync(&sc->paprd_work);
184 cancel_delayed_work_sync(&sc->tx_complete_work);
185 cancel_delayed_work_sync(&sc->hw_pll_work);
186
187 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
188 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
189 cancel_work_sync(&sc->mci_work);
190 #endif
191 }
192
193 void ath_cancel_work(struct ath_softc *sc)
194 {
195 __ath_cancel_work(sc);
196 cancel_work_sync(&sc->hw_reset_work);
197 }
198
199 void ath_restart_work(struct ath_softc *sc)
200 {
201 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
202
203 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
204 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
205 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
206
207 ath_start_ani(sc);
208 }
209
210 static bool ath_prepare_reset(struct ath_softc *sc)
211 {
212 struct ath_hw *ah = sc->sc_ah;
213 bool ret = true;
214
215 ieee80211_stop_queues(sc->hw);
216 ath_stop_ani(sc);
217 ath9k_hw_disable_interrupts(ah);
218
219 if (AR_SREV_9300_20_OR_LATER(ah)) {
220 ret &= ath_stoprecv(sc);
221 ret &= ath_drain_all_txq(sc);
222 } else {
223 ret &= ath_drain_all_txq(sc);
224 ret &= ath_stoprecv(sc);
225 }
226
227 return ret;
228 }
229
230 static bool ath_complete_reset(struct ath_softc *sc, bool start)
231 {
232 struct ath_hw *ah = sc->sc_ah;
233 struct ath_common *common = ath9k_hw_common(ah);
234 unsigned long flags;
235
236 ath9k_calculate_summary_state(sc, sc->cur_chan);
237 ath_startrecv(sc);
238 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
239 sc->cur_chan->txpower,
240 &sc->cur_chan->cur_txpower);
241 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
242
243 if (!sc->cur_chan->offchannel && start) {
244 /* restore per chanctx TSF timer */
245 if (sc->cur_chan->tsf_val) {
246 u32 offset;
247
248 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
249 NULL);
250 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
251 }
252
253
254 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
255 goto work;
256
257 if (ah->opmode == NL80211_IFTYPE_STATION &&
258 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
259 spin_lock_irqsave(&sc->sc_pm_lock, flags);
260 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
261 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
262 } else {
263 ath9k_set_beacon(sc);
264 }
265 work:
266 ath_restart_work(sc);
267 ath_txq_schedule_all(sc);
268 }
269
270 sc->gtt_cnt = 0;
271
272 ath9k_hw_set_interrupts(ah);
273 ath9k_hw_enable_interrupts(ah);
274 ieee80211_wake_queues(sc->hw);
275 ath9k_p2p_ps_timer(sc);
276
277 return true;
278 }
279
280 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
281 {
282 struct ath_hw *ah = sc->sc_ah;
283 struct ath_common *common = ath9k_hw_common(ah);
284 struct ath9k_hw_cal_data *caldata = NULL;
285 bool fastcc = true;
286 int r;
287
288 __ath_cancel_work(sc);
289
290 disable_irq(sc->irq);
291 tasklet_disable(&sc->intr_tq);
292 tasklet_disable(&sc->bcon_tasklet);
293 spin_lock_bh(&sc->sc_pcu_lock);
294
295 if (!sc->cur_chan->offchannel) {
296 fastcc = false;
297 caldata = &sc->cur_chan->caldata;
298 }
299
300 if (!hchan) {
301 fastcc = false;
302 hchan = ah->curchan;
303 }
304
305 if (!ath_prepare_reset(sc))
306 fastcc = false;
307
308 if (ath9k_is_chanctx_enabled())
309 fastcc = false;
310
311 spin_lock_bh(&sc->chan_lock);
312 sc->cur_chandef = sc->cur_chan->chandef;
313 spin_unlock_bh(&sc->chan_lock);
314
315 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
316 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
317
318 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
319 if (r) {
320 ath_err(common,
321 "Unable to reset channel, reset status %d\n", r);
322
323 ath9k_hw_enable_interrupts(ah);
324 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
325
326 goto out;
327 }
328
329 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
330 sc->cur_chan->offchannel)
331 ath9k_mci_set_txpower(sc, true, false);
332
333 if (!ath_complete_reset(sc, true))
334 r = -EIO;
335
336 out:
337 enable_irq(sc->irq);
338 spin_unlock_bh(&sc->sc_pcu_lock);
339 tasklet_enable(&sc->bcon_tasklet);
340 tasklet_enable(&sc->intr_tq);
341
342 return r;
343 }
344
345 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
346 struct ieee80211_vif *vif)
347 {
348 struct ath_node *an;
349 an = (struct ath_node *)sta->drv_priv;
350
351 an->sc = sc;
352 an->sta = sta;
353 an->vif = vif;
354 memset(&an->key_idx, 0, sizeof(an->key_idx));
355
356 ath_tx_node_init(sc, an);
357
358 ath_dynack_node_init(sc->sc_ah, an);
359 }
360
361 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
362 {
363 struct ath_node *an = (struct ath_node *)sta->drv_priv;
364 ath_tx_node_cleanup(sc, an);
365
366 ath_dynack_node_deinit(sc->sc_ah, an);
367 }
368
369 void ath9k_tasklet(unsigned long data)
370 {
371 struct ath_softc *sc = (struct ath_softc *)data;
372 struct ath_hw *ah = sc->sc_ah;
373 struct ath_common *common = ath9k_hw_common(ah);
374 enum ath_reset_type type;
375 unsigned long flags;
376 u32 status = sc->intrstatus;
377 u32 rxmask;
378
379 ath9k_ps_wakeup(sc);
380 spin_lock(&sc->sc_pcu_lock);
381
382 if (status & ATH9K_INT_FATAL) {
383 type = RESET_TYPE_FATAL_INT;
384 ath9k_queue_reset(sc, type);
385
386 /*
387 * Increment the ref. counter here so that
388 * interrupts are enabled in the reset routine.
389 */
390 atomic_inc(&ah->intr_ref_cnt);
391 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
392 goto out;
393 }
394
395 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
396 (status & ATH9K_INT_BB_WATCHDOG)) {
397 spin_lock(&common->cc_lock);
398 ath_hw_cycle_counters_update(common);
399 ar9003_hw_bb_watchdog_dbg_info(ah);
400 spin_unlock(&common->cc_lock);
401
402 if (ar9003_hw_bb_watchdog_check(ah)) {
403 type = RESET_TYPE_BB_WATCHDOG;
404 ath9k_queue_reset(sc, type);
405
406 /*
407 * Increment the ref. counter here so that
408 * interrupts are enabled in the reset routine.
409 */
410 atomic_inc(&ah->intr_ref_cnt);
411 ath_dbg(common, RESET,
412 "BB_WATCHDOG: Skipping interrupts\n");
413 goto out;
414 }
415 }
416
417 if (status & ATH9K_INT_GTT) {
418 sc->gtt_cnt++;
419
420 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
421 type = RESET_TYPE_TX_GTT;
422 ath9k_queue_reset(sc, type);
423 atomic_inc(&ah->intr_ref_cnt);
424 ath_dbg(common, RESET,
425 "GTT: Skipping interrupts\n");
426 goto out;
427 }
428 }
429
430 spin_lock_irqsave(&sc->sc_pm_lock, flags);
431 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
432 /*
433 * TSF sync does not look correct; remain awake to sync with
434 * the next Beacon.
435 */
436 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
437 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
438 }
439 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
440
441 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
442 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
443 ATH9K_INT_RXORN);
444 else
445 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
446
447 if (status & rxmask) {
448 /* Check for high priority Rx first */
449 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
450 (status & ATH9K_INT_RXHP))
451 ath_rx_tasklet(sc, 0, true);
452
453 ath_rx_tasklet(sc, 0, false);
454 }
455
456 if (status & ATH9K_INT_TX) {
457 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
458 /*
459 * For EDMA chips, TX completion is enabled for the
460 * beacon queue, so if a beacon has been transmitted
461 * successfully after a GTT interrupt, the GTT counter
462 * gets reset to zero here.
463 */
464 sc->gtt_cnt = 0;
465
466 ath_tx_edma_tasklet(sc);
467 } else {
468 ath_tx_tasklet(sc);
469 }
470
471 wake_up(&sc->tx_wait);
472 }
473
474 if (status & ATH9K_INT_GENTIMER)
475 ath_gen_timer_isr(sc->sc_ah);
476
477 ath9k_btcoex_handle_interrupt(sc, status);
478
479 /* re-enable hardware interrupt */
480 ath9k_hw_enable_interrupts(ah);
481 out:
482 spin_unlock(&sc->sc_pcu_lock);
483 ath9k_ps_restore(sc);
484 }
485
486 irqreturn_t ath_isr(int irq, void *dev)
487 {
488 #define SCHED_INTR ( \
489 ATH9K_INT_FATAL | \
490 ATH9K_INT_BB_WATCHDOG | \
491 ATH9K_INT_RXORN | \
492 ATH9K_INT_RXEOL | \
493 ATH9K_INT_RX | \
494 ATH9K_INT_RXLP | \
495 ATH9K_INT_RXHP | \
496 ATH9K_INT_TX | \
497 ATH9K_INT_BMISS | \
498 ATH9K_INT_CST | \
499 ATH9K_INT_GTT | \
500 ATH9K_INT_TSFOOR | \
501 ATH9K_INT_GENTIMER | \
502 ATH9K_INT_MCI)
503
504 struct ath_softc *sc = dev;
505 struct ath_hw *ah = sc->sc_ah;
506 struct ath_common *common = ath9k_hw_common(ah);
507 enum ath9k_int status;
508 u32 sync_cause = 0;
509 bool sched = false;
510
511 /*
512 * The hardware is not ready/present, don't
513 * touch anything. Note this can happen early
514 * on if the IRQ is shared.
515 */
516 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
517 return IRQ_NONE;
518
519 /* shared irq, not for us */
520 if (!ath9k_hw_intrpend(ah))
521 return IRQ_NONE;
522
523 /*
524 * Figure out the reason(s) for the interrupt. Note
525 * that the hal returns a pseudo-ISR that may include
526 * bits we haven't explicitly enabled so we mask the
527 * value to insure we only process bits we requested.
528 */
529 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
530 ath9k_debug_sync_cause(sc, sync_cause);
531 status &= ah->imask; /* discard unasked-for bits */
532
533 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
534 return IRQ_HANDLED;
535
536 /*
537 * If there are no status bits set, then this interrupt was not
538 * for me (should have been caught above).
539 */
540 if (!status)
541 return IRQ_NONE;
542
543 /* Cache the status */
544 sc->intrstatus = status;
545
546 if (status & SCHED_INTR)
547 sched = true;
548
549 /*
550 * If a FATAL interrupt is received, we have to reset the chip
551 * immediately.
552 */
553 if (status & ATH9K_INT_FATAL)
554 goto chip_reset;
555
556 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
557 (status & ATH9K_INT_BB_WATCHDOG))
558 goto chip_reset;
559
560 if (status & ATH9K_INT_SWBA)
561 tasklet_schedule(&sc->bcon_tasklet);
562
563 if (status & ATH9K_INT_TXURN)
564 ath9k_hw_updatetxtriglevel(ah, true);
565
566 if (status & ATH9K_INT_RXEOL) {
567 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
568 ath9k_hw_set_interrupts(ah);
569 }
570
571 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
572 if (status & ATH9K_INT_TIM_TIMER) {
573 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
574 goto chip_reset;
575 /* Clear RxAbort bit so that we can
576 * receive frames */
577 ath9k_setpower(sc, ATH9K_PM_AWAKE);
578 spin_lock(&sc->sc_pm_lock);
579 ath9k_hw_setrxabort(sc->sc_ah, 0);
580 sc->ps_flags |= PS_WAIT_FOR_BEACON;
581 spin_unlock(&sc->sc_pm_lock);
582 }
583
584 chip_reset:
585
586 ath_debug_stat_interrupt(sc, status);
587
588 if (sched) {
589 /* turn off every interrupt */
590 ath9k_hw_disable_interrupts(ah);
591 tasklet_schedule(&sc->intr_tq);
592 }
593
594 return IRQ_HANDLED;
595
596 #undef SCHED_INTR
597 }
598
599 /*
600 * This function is called when a HW reset cannot be deferred
601 * and has to be immediate.
602 */
603 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
604 {
605 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
606 int r;
607
608 ath9k_hw_kill_interrupts(sc->sc_ah);
609 set_bit(ATH_OP_HW_RESET, &common->op_flags);
610
611 ath9k_ps_wakeup(sc);
612 r = ath_reset_internal(sc, hchan);
613 ath9k_ps_restore(sc);
614
615 return r;
616 }
617
618 /*
619 * When a HW reset can be deferred, it is added to the
620 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
621 * queueing.
622 */
623 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
624 {
625 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
626 #ifdef CONFIG_ATH9K_DEBUGFS
627 RESET_STAT_INC(sc, type);
628 #endif
629 ath9k_hw_kill_interrupts(sc->sc_ah);
630 set_bit(ATH_OP_HW_RESET, &common->op_flags);
631 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
632 }
633
634 void ath_reset_work(struct work_struct *work)
635 {
636 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
637
638 ath9k_ps_wakeup(sc);
639 ath_reset_internal(sc, NULL);
640 ath9k_ps_restore(sc);
641 }
642
643 /**********************/
644 /* mac80211 callbacks */
645 /**********************/
646
647 static int ath9k_start(struct ieee80211_hw *hw)
648 {
649 struct ath_softc *sc = hw->priv;
650 struct ath_hw *ah = sc->sc_ah;
651 struct ath_common *common = ath9k_hw_common(ah);
652 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
653 struct ath_chanctx *ctx = sc->cur_chan;
654 struct ath9k_channel *init_channel;
655 int r;
656
657 ath_dbg(common, CONFIG,
658 "Starting driver with initial channel: %d MHz\n",
659 curchan->center_freq);
660
661 ath9k_ps_wakeup(sc);
662 mutex_lock(&sc->mutex);
663
664 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
665 sc->cur_chandef = hw->conf.chandef;
666
667 /* Reset SERDES registers */
668 ath9k_hw_configpcipowersave(ah, false);
669
670 /*
671 * The basic interface to setting the hardware in a good
672 * state is ``reset''. On return the hardware is known to
673 * be powered up and with interrupts disabled. This must
674 * be followed by initialization of the appropriate bits
675 * and then setup of the interrupt mask.
676 */
677 spin_lock_bh(&sc->sc_pcu_lock);
678
679 atomic_set(&ah->intr_ref_cnt, -1);
680
681 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
682 if (r) {
683 ath_err(common,
684 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
685 r, curchan->center_freq);
686 ah->reset_power_on = false;
687 }
688
689 /* Setup our intr mask. */
690 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
691 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
692 ATH9K_INT_GLOBAL;
693
694 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
695 ah->imask |= ATH9K_INT_RXHP |
696 ATH9K_INT_RXLP;
697 else
698 ah->imask |= ATH9K_INT_RX;
699
700 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
701 ah->imask |= ATH9K_INT_BB_WATCHDOG;
702
703 /*
704 * Enable GTT interrupts only for AR9003/AR9004 chips
705 * for now.
706 */
707 if (AR_SREV_9300_20_OR_LATER(ah))
708 ah->imask |= ATH9K_INT_GTT;
709
710 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
711 ah->imask |= ATH9K_INT_CST;
712
713 ath_mci_enable(sc);
714
715 clear_bit(ATH_OP_INVALID, &common->op_flags);
716 sc->sc_ah->is_monitoring = false;
717
718 if (!ath_complete_reset(sc, false))
719 ah->reset_power_on = false;
720
721 if (ah->led_pin >= 0) {
722 ath9k_hw_cfg_output(ah, ah->led_pin,
723 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
724 ath9k_hw_set_gpio(ah, ah->led_pin,
725 (ah->config.led_active_high) ? 1 : 0);
726 }
727
728 /*
729 * Reset key cache to sane defaults (all entries cleared) instead of
730 * semi-random values after suspend/resume.
731 */
732 ath9k_cmn_init_crypto(sc->sc_ah);
733
734 ath9k_hw_reset_tsf(ah);
735
736 spin_unlock_bh(&sc->sc_pcu_lock);
737
738 mutex_unlock(&sc->mutex);
739
740 ath9k_ps_restore(sc);
741
742 return 0;
743 }
744
745 static void ath9k_tx(struct ieee80211_hw *hw,
746 struct ieee80211_tx_control *control,
747 struct sk_buff *skb)
748 {
749 struct ath_softc *sc = hw->priv;
750 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
751 struct ath_tx_control txctl;
752 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
753 unsigned long flags;
754
755 if (sc->ps_enabled) {
756 /*
757 * mac80211 does not set PM field for normal data frames, so we
758 * need to update that based on the current PS mode.
759 */
760 if (ieee80211_is_data(hdr->frame_control) &&
761 !ieee80211_is_nullfunc(hdr->frame_control) &&
762 !ieee80211_has_pm(hdr->frame_control)) {
763 ath_dbg(common, PS,
764 "Add PM=1 for a TX frame while in PS mode\n");
765 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
766 }
767 }
768
769 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
770 /*
771 * We are using PS-Poll and mac80211 can request TX while in
772 * power save mode. Need to wake up hardware for the TX to be
773 * completed and if needed, also for RX of buffered frames.
774 */
775 ath9k_ps_wakeup(sc);
776 spin_lock_irqsave(&sc->sc_pm_lock, flags);
777 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
778 ath9k_hw_setrxabort(sc->sc_ah, 0);
779 if (ieee80211_is_pspoll(hdr->frame_control)) {
780 ath_dbg(common, PS,
781 "Sending PS-Poll to pick a buffered frame\n");
782 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
783 } else {
784 ath_dbg(common, PS, "Wake up to complete TX\n");
785 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
786 }
787 /*
788 * The actual restore operation will happen only after
789 * the ps_flags bit is cleared. We are just dropping
790 * the ps_usecount here.
791 */
792 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
793 ath9k_ps_restore(sc);
794 }
795
796 /*
797 * Cannot tx while the hardware is in full sleep, it first needs a full
798 * chip reset to recover from that
799 */
800 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
801 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
802 goto exit;
803 }
804
805 memset(&txctl, 0, sizeof(struct ath_tx_control));
806 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
807 txctl.sta = control->sta;
808
809 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
810
811 if (ath_tx_start(hw, skb, &txctl) != 0) {
812 ath_dbg(common, XMIT, "TX failed\n");
813 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
814 goto exit;
815 }
816
817 return;
818 exit:
819 ieee80211_free_txskb(hw, skb);
820 }
821
822 static void ath9k_stop(struct ieee80211_hw *hw)
823 {
824 struct ath_softc *sc = hw->priv;
825 struct ath_hw *ah = sc->sc_ah;
826 struct ath_common *common = ath9k_hw_common(ah);
827 bool prev_idle;
828
829 ath9k_deinit_channel_context(sc);
830
831 mutex_lock(&sc->mutex);
832
833 ath_cancel_work(sc);
834
835 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
836 ath_dbg(common, ANY, "Device not present\n");
837 mutex_unlock(&sc->mutex);
838 return;
839 }
840
841 /* Ensure HW is awake when we try to shut it down. */
842 ath9k_ps_wakeup(sc);
843
844 spin_lock_bh(&sc->sc_pcu_lock);
845
846 /* prevent tasklets to enable interrupts once we disable them */
847 ah->imask &= ~ATH9K_INT_GLOBAL;
848
849 /* make sure h/w will not generate any interrupt
850 * before setting the invalid flag. */
851 ath9k_hw_disable_interrupts(ah);
852
853 spin_unlock_bh(&sc->sc_pcu_lock);
854
855 /* we can now sync irq and kill any running tasklets, since we already
856 * disabled interrupts and not holding a spin lock */
857 synchronize_irq(sc->irq);
858 tasklet_kill(&sc->intr_tq);
859 tasklet_kill(&sc->bcon_tasklet);
860
861 prev_idle = sc->ps_idle;
862 sc->ps_idle = true;
863
864 spin_lock_bh(&sc->sc_pcu_lock);
865
866 if (ah->led_pin >= 0) {
867 ath9k_hw_set_gpio(ah, ah->led_pin,
868 (ah->config.led_active_high) ? 0 : 1);
869 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
870 }
871
872 ath_prepare_reset(sc);
873
874 if (sc->rx.frag) {
875 dev_kfree_skb_any(sc->rx.frag);
876 sc->rx.frag = NULL;
877 }
878
879 if (!ah->curchan)
880 ah->curchan = ath9k_cmn_get_channel(hw, ah,
881 &sc->cur_chan->chandef);
882
883 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
884
885 set_bit(ATH_OP_INVALID, &common->op_flags);
886
887 ath9k_hw_phy_disable(ah);
888
889 ath9k_hw_configpcipowersave(ah, true);
890
891 spin_unlock_bh(&sc->sc_pcu_lock);
892
893 ath9k_ps_restore(sc);
894
895 sc->ps_idle = prev_idle;
896
897 mutex_unlock(&sc->mutex);
898
899 ath_dbg(common, CONFIG, "Driver halt\n");
900 }
901
902 static bool ath9k_uses_beacons(int type)
903 {
904 switch (type) {
905 case NL80211_IFTYPE_AP:
906 case NL80211_IFTYPE_ADHOC:
907 case NL80211_IFTYPE_MESH_POINT:
908 return true;
909 default:
910 return false;
911 }
912 }
913
914 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
915 u8 *mac, struct ieee80211_vif *vif)
916 {
917 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
918 int i;
919
920 if (iter_data->has_hw_macaddr) {
921 for (i = 0; i < ETH_ALEN; i++)
922 iter_data->mask[i] &=
923 ~(iter_data->hw_macaddr[i] ^ mac[i]);
924 } else {
925 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
926 iter_data->has_hw_macaddr = true;
927 }
928
929 if (!vif->bss_conf.use_short_slot)
930 iter_data->slottime = ATH9K_SLOT_TIME_20;
931
932 switch (vif->type) {
933 case NL80211_IFTYPE_AP:
934 iter_data->naps++;
935 break;
936 case NL80211_IFTYPE_STATION:
937 iter_data->nstations++;
938 if (avp->assoc && !iter_data->primary_sta)
939 iter_data->primary_sta = vif;
940 break;
941 case NL80211_IFTYPE_ADHOC:
942 iter_data->nadhocs++;
943 if (vif->bss_conf.enable_beacon)
944 iter_data->beacons = true;
945 break;
946 case NL80211_IFTYPE_MESH_POINT:
947 iter_data->nmeshes++;
948 if (vif->bss_conf.enable_beacon)
949 iter_data->beacons = true;
950 break;
951 case NL80211_IFTYPE_WDS:
952 iter_data->nwds++;
953 break;
954 default:
955 break;
956 }
957 }
958
959 static void ath9k_update_bssid_mask(struct ath_softc *sc,
960 struct ath_chanctx *ctx,
961 struct ath9k_vif_iter_data *iter_data)
962 {
963 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
964 struct ath_vif *avp;
965 int i;
966
967 if (!ath9k_is_chanctx_enabled())
968 return;
969
970 list_for_each_entry(avp, &ctx->vifs, list) {
971 if (ctx->nvifs_assigned != 1)
972 continue;
973
974 if (!avp->vif->p2p || !iter_data->has_hw_macaddr)
975 continue;
976
977 ether_addr_copy(common->curbssid, avp->bssid);
978
979 /* perm_addr will be used as the p2p device address. */
980 for (i = 0; i < ETH_ALEN; i++)
981 iter_data->mask[i] &=
982 ~(iter_data->hw_macaddr[i] ^
983 sc->hw->wiphy->perm_addr[i]);
984 }
985 }
986
987 /* Called with sc->mutex held. */
988 void ath9k_calculate_iter_data(struct ath_softc *sc,
989 struct ath_chanctx *ctx,
990 struct ath9k_vif_iter_data *iter_data)
991 {
992 struct ath_vif *avp;
993
994 /*
995 * The hardware will use primary station addr together with the
996 * BSSID mask when matching addresses.
997 */
998 memset(iter_data, 0, sizeof(*iter_data));
999 eth_broadcast_addr(iter_data->mask);
1000 iter_data->slottime = ATH9K_SLOT_TIME_9;
1001
1002 list_for_each_entry(avp, &ctx->vifs, list)
1003 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1004
1005 ath9k_update_bssid_mask(sc, ctx, iter_data);
1006 }
1007
1008 static void ath9k_set_assoc_state(struct ath_softc *sc,
1009 struct ieee80211_vif *vif, bool changed)
1010 {
1011 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1012 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1013 unsigned long flags;
1014
1015 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1016
1017 ether_addr_copy(common->curbssid, avp->bssid);
1018 common->curaid = avp->aid;
1019 ath9k_hw_write_associd(sc->sc_ah);
1020
1021 if (changed) {
1022 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1023 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1024
1025 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1026 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1027 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1028 }
1029
1030 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1031 ath9k_mci_update_wlan_channels(sc, false);
1032
1033 ath_dbg(common, CONFIG,
1034 "Primary Station interface: %pM, BSSID: %pM\n",
1035 vif->addr, common->curbssid);
1036 }
1037
1038 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1039 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1040 {
1041 struct ath_hw *ah = sc->sc_ah;
1042 struct ath_common *common = ath9k_hw_common(ah);
1043 struct ieee80211_vif *vif = NULL;
1044
1045 ath9k_ps_wakeup(sc);
1046
1047 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1048 vif = sc->offchannel.scan_vif;
1049 else
1050 vif = sc->offchannel.roc_vif;
1051
1052 if (WARN_ON(!vif))
1053 goto exit;
1054
1055 eth_zero_addr(common->curbssid);
1056 eth_broadcast_addr(common->bssidmask);
1057 memcpy(common->macaddr, vif->addr, ETH_ALEN);
1058 common->curaid = 0;
1059 ah->opmode = vif->type;
1060 ah->imask &= ~ATH9K_INT_SWBA;
1061 ah->imask &= ~ATH9K_INT_TSFOOR;
1062 ah->slottime = ATH9K_SLOT_TIME_9;
1063
1064 ath_hw_setbssidmask(common);
1065 ath9k_hw_setopmode(ah);
1066 ath9k_hw_write_associd(sc->sc_ah);
1067 ath9k_hw_set_interrupts(ah);
1068 ath9k_hw_init_global_settings(ah);
1069
1070 exit:
1071 ath9k_ps_restore(sc);
1072 }
1073 #endif
1074
1075 /* Called with sc->mutex held. */
1076 void ath9k_calculate_summary_state(struct ath_softc *sc,
1077 struct ath_chanctx *ctx)
1078 {
1079 struct ath_hw *ah = sc->sc_ah;
1080 struct ath_common *common = ath9k_hw_common(ah);
1081 struct ath9k_vif_iter_data iter_data;
1082 struct ath_beacon_config *cur_conf;
1083
1084 ath_chanctx_check_active(sc, ctx);
1085
1086 if (ctx != sc->cur_chan)
1087 return;
1088
1089 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1090 if (ctx == &sc->offchannel.chan)
1091 return ath9k_set_offchannel_state(sc);
1092 #endif
1093
1094 ath9k_ps_wakeup(sc);
1095 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1096
1097 if (iter_data.has_hw_macaddr)
1098 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1099
1100 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1101 ath_hw_setbssidmask(common);
1102
1103 if (iter_data.naps > 0) {
1104 cur_conf = &ctx->beacon;
1105 ath9k_hw_set_tsfadjust(ah, true);
1106 ah->opmode = NL80211_IFTYPE_AP;
1107 if (cur_conf->enable_beacon)
1108 iter_data.beacons = true;
1109 } else {
1110 ath9k_hw_set_tsfadjust(ah, false);
1111
1112 if (iter_data.nmeshes)
1113 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1114 else if (iter_data.nwds)
1115 ah->opmode = NL80211_IFTYPE_AP;
1116 else if (iter_data.nadhocs)
1117 ah->opmode = NL80211_IFTYPE_ADHOC;
1118 else
1119 ah->opmode = NL80211_IFTYPE_STATION;
1120 }
1121
1122 ath9k_hw_setopmode(ah);
1123
1124 ctx->switch_after_beacon = false;
1125 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1126 ah->imask |= ATH9K_INT_TSFOOR;
1127 else {
1128 ah->imask &= ~ATH9K_INT_TSFOOR;
1129 if (iter_data.naps == 1 && iter_data.beacons)
1130 ctx->switch_after_beacon = true;
1131 }
1132
1133 ah->imask &= ~ATH9K_INT_SWBA;
1134 if (ah->opmode == NL80211_IFTYPE_STATION) {
1135 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1136
1137 if (iter_data.primary_sta) {
1138 iter_data.beacons = true;
1139 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1140 changed);
1141 ctx->primary_sta = iter_data.primary_sta;
1142 } else {
1143 ctx->primary_sta = NULL;
1144 eth_zero_addr(common->curbssid);
1145 common->curaid = 0;
1146 ath9k_hw_write_associd(sc->sc_ah);
1147 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1148 ath9k_mci_update_wlan_channels(sc, true);
1149 }
1150 } else if (iter_data.beacons) {
1151 ah->imask |= ATH9K_INT_SWBA;
1152 }
1153 ath9k_hw_set_interrupts(ah);
1154
1155 if (iter_data.beacons)
1156 set_bit(ATH_OP_BEACONS, &common->op_flags);
1157 else
1158 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1159
1160 if (ah->slottime != iter_data.slottime) {
1161 ah->slottime = iter_data.slottime;
1162 ath9k_hw_init_global_settings(ah);
1163 }
1164
1165 if (iter_data.primary_sta)
1166 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1167 else
1168 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1169
1170 ath_dbg(common, CONFIG,
1171 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1172 common->macaddr, common->curbssid, common->bssidmask);
1173
1174 ath9k_ps_restore(sc);
1175 }
1176
1177 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1178 {
1179 int *power = (int *)data;
1180
1181 if (*power < vif->bss_conf.txpower)
1182 *power = vif->bss_conf.txpower;
1183 }
1184
1185 /* Called with sc->mutex held. */
1186 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1187 {
1188 int power;
1189 struct ath_hw *ah = sc->sc_ah;
1190 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1191
1192 ath9k_ps_wakeup(sc);
1193 if (ah->tpc_enabled) {
1194 power = (vif) ? vif->bss_conf.txpower : -1;
1195 ieee80211_iterate_active_interfaces_atomic(
1196 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1197 ath9k_tpc_vif_iter, &power);
1198 if (power == -1)
1199 power = sc->hw->conf.power_level;
1200 } else {
1201 power = sc->hw->conf.power_level;
1202 }
1203 sc->cur_chan->txpower = 2 * power;
1204 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1205 sc->cur_chan->cur_txpower = reg->max_power_level;
1206 ath9k_ps_restore(sc);
1207 }
1208
1209 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1210 struct ieee80211_vif *vif)
1211 {
1212 int i;
1213
1214 if (!ath9k_is_chanctx_enabled())
1215 return;
1216
1217 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1218 vif->hw_queue[i] = i;
1219
1220 if (vif->type == NL80211_IFTYPE_AP ||
1221 vif->type == NL80211_IFTYPE_MESH_POINT)
1222 vif->cab_queue = hw->queues - 2;
1223 else
1224 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1225 }
1226
1227 static int ath9k_add_interface(struct ieee80211_hw *hw,
1228 struct ieee80211_vif *vif)
1229 {
1230 struct ath_softc *sc = hw->priv;
1231 struct ath_hw *ah = sc->sc_ah;
1232 struct ath_common *common = ath9k_hw_common(ah);
1233 struct ath_vif *avp = (void *)vif->drv_priv;
1234 struct ath_node *an = &avp->mcast_node;
1235
1236 mutex_lock(&sc->mutex);
1237
1238 if (config_enabled(CONFIG_ATH9K_TX99)) {
1239 if (sc->cur_chan->nvifs >= 1) {
1240 mutex_unlock(&sc->mutex);
1241 return -EOPNOTSUPP;
1242 }
1243 sc->tx99_vif = vif;
1244 }
1245
1246 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1247 sc->cur_chan->nvifs++;
1248
1249 if (ath9k_uses_beacons(vif->type))
1250 ath9k_beacon_assign_slot(sc, vif);
1251
1252 avp->vif = vif;
1253 if (!ath9k_is_chanctx_enabled()) {
1254 avp->chanctx = sc->cur_chan;
1255 list_add_tail(&avp->list, &avp->chanctx->vifs);
1256 }
1257
1258 ath9k_calculate_summary_state(sc, avp->chanctx);
1259
1260 ath9k_assign_hw_queues(hw, vif);
1261
1262 ath9k_set_txpower(sc, vif);
1263
1264 an->sc = sc;
1265 an->sta = NULL;
1266 an->vif = vif;
1267 an->no_ps_filter = true;
1268 ath_tx_node_init(sc, an);
1269
1270 mutex_unlock(&sc->mutex);
1271 return 0;
1272 }
1273
1274 static int ath9k_change_interface(struct ieee80211_hw *hw,
1275 struct ieee80211_vif *vif,
1276 enum nl80211_iftype new_type,
1277 bool p2p)
1278 {
1279 struct ath_softc *sc = hw->priv;
1280 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1281 struct ath_vif *avp = (void *)vif->drv_priv;
1282
1283 mutex_lock(&sc->mutex);
1284
1285 if (config_enabled(CONFIG_ATH9K_TX99)) {
1286 mutex_unlock(&sc->mutex);
1287 return -EOPNOTSUPP;
1288 }
1289
1290 ath_dbg(common, CONFIG, "Change Interface\n");
1291
1292 if (ath9k_uses_beacons(vif->type))
1293 ath9k_beacon_remove_slot(sc, vif);
1294
1295 vif->type = new_type;
1296 vif->p2p = p2p;
1297
1298 if (ath9k_uses_beacons(vif->type))
1299 ath9k_beacon_assign_slot(sc, vif);
1300
1301 ath9k_assign_hw_queues(hw, vif);
1302 ath9k_calculate_summary_state(sc, avp->chanctx);
1303
1304 ath9k_set_txpower(sc, vif);
1305
1306 mutex_unlock(&sc->mutex);
1307 return 0;
1308 }
1309
1310 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1311 struct ieee80211_vif *vif)
1312 {
1313 struct ath_softc *sc = hw->priv;
1314 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1315 struct ath_vif *avp = (void *)vif->drv_priv;
1316
1317 ath_dbg(common, CONFIG, "Detach Interface\n");
1318
1319 mutex_lock(&sc->mutex);
1320
1321 ath9k_p2p_remove_vif(sc, vif);
1322
1323 sc->cur_chan->nvifs--;
1324 sc->tx99_vif = NULL;
1325 if (!ath9k_is_chanctx_enabled())
1326 list_del(&avp->list);
1327
1328 if (ath9k_uses_beacons(vif->type))
1329 ath9k_beacon_remove_slot(sc, vif);
1330
1331 ath_tx_node_cleanup(sc, &avp->mcast_node);
1332
1333 ath9k_calculate_summary_state(sc, avp->chanctx);
1334
1335 ath9k_set_txpower(sc, NULL);
1336
1337 mutex_unlock(&sc->mutex);
1338 }
1339
1340 static void ath9k_enable_ps(struct ath_softc *sc)
1341 {
1342 struct ath_hw *ah = sc->sc_ah;
1343 struct ath_common *common = ath9k_hw_common(ah);
1344
1345 if (config_enabled(CONFIG_ATH9K_TX99))
1346 return;
1347
1348 sc->ps_enabled = true;
1349 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1350 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1351 ah->imask |= ATH9K_INT_TIM_TIMER;
1352 ath9k_hw_set_interrupts(ah);
1353 }
1354 ath9k_hw_setrxabort(ah, 1);
1355 }
1356 ath_dbg(common, PS, "PowerSave enabled\n");
1357 }
1358
1359 static void ath9k_disable_ps(struct ath_softc *sc)
1360 {
1361 struct ath_hw *ah = sc->sc_ah;
1362 struct ath_common *common = ath9k_hw_common(ah);
1363
1364 if (config_enabled(CONFIG_ATH9K_TX99))
1365 return;
1366
1367 sc->ps_enabled = false;
1368 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1369 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1370 ath9k_hw_setrxabort(ah, 0);
1371 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1372 PS_WAIT_FOR_CAB |
1373 PS_WAIT_FOR_PSPOLL_DATA |
1374 PS_WAIT_FOR_TX_ACK);
1375 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1376 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1377 ath9k_hw_set_interrupts(ah);
1378 }
1379 }
1380 ath_dbg(common, PS, "PowerSave disabled\n");
1381 }
1382
1383 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1384 {
1385 struct ath_softc *sc = hw->priv;
1386 struct ath_hw *ah = sc->sc_ah;
1387 struct ath_common *common = ath9k_hw_common(ah);
1388 struct ieee80211_conf *conf = &hw->conf;
1389 struct ath_chanctx *ctx = sc->cur_chan;
1390
1391 ath9k_ps_wakeup(sc);
1392 mutex_lock(&sc->mutex);
1393
1394 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1395 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1396 if (sc->ps_idle) {
1397 ath_cancel_work(sc);
1398 ath9k_stop_btcoex(sc);
1399 } else {
1400 ath9k_start_btcoex(sc);
1401 /*
1402 * The chip needs a reset to properly wake up from
1403 * full sleep
1404 */
1405 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1406 }
1407 }
1408
1409 /*
1410 * We just prepare to enable PS. We have to wait until our AP has
1411 * ACK'd our null data frame to disable RX otherwise we'll ignore
1412 * those ACKs and end up retransmitting the same null data frames.
1413 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1414 */
1415 if (changed & IEEE80211_CONF_CHANGE_PS) {
1416 unsigned long flags;
1417 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1418 if (conf->flags & IEEE80211_CONF_PS)
1419 ath9k_enable_ps(sc);
1420 else
1421 ath9k_disable_ps(sc);
1422 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1423 }
1424
1425 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1426 if (conf->flags & IEEE80211_CONF_MONITOR) {
1427 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1428 sc->sc_ah->is_monitoring = true;
1429 } else {
1430 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1431 sc->sc_ah->is_monitoring = false;
1432 }
1433 }
1434
1435 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1436 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1437 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1438 }
1439
1440 mutex_unlock(&sc->mutex);
1441 ath9k_ps_restore(sc);
1442
1443 return 0;
1444 }
1445
1446 #define SUPPORTED_FILTERS \
1447 (FIF_ALLMULTI | \
1448 FIF_CONTROL | \
1449 FIF_PSPOLL | \
1450 FIF_OTHER_BSS | \
1451 FIF_BCN_PRBRESP_PROMISC | \
1452 FIF_PROBE_REQ | \
1453 FIF_FCSFAIL)
1454
1455 /* FIXME: sc->sc_full_reset ? */
1456 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1457 unsigned int changed_flags,
1458 unsigned int *total_flags,
1459 u64 multicast)
1460 {
1461 struct ath_softc *sc = hw->priv;
1462 struct ath_chanctx *ctx;
1463 u32 rfilt;
1464
1465 changed_flags &= SUPPORTED_FILTERS;
1466 *total_flags &= SUPPORTED_FILTERS;
1467
1468 spin_lock_bh(&sc->chan_lock);
1469 ath_for_each_chanctx(sc, ctx)
1470 ctx->rxfilter = *total_flags;
1471 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1472 sc->offchannel.chan.rxfilter = *total_flags;
1473 #endif
1474 spin_unlock_bh(&sc->chan_lock);
1475
1476 ath9k_ps_wakeup(sc);
1477 rfilt = ath_calcrxfilter(sc);
1478 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1479 ath9k_ps_restore(sc);
1480
1481 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1482 rfilt);
1483 }
1484
1485 static int ath9k_sta_add(struct ieee80211_hw *hw,
1486 struct ieee80211_vif *vif,
1487 struct ieee80211_sta *sta)
1488 {
1489 struct ath_softc *sc = hw->priv;
1490 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1491 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1492 struct ieee80211_key_conf ps_key = { };
1493 int key;
1494
1495 ath_node_attach(sc, sta, vif);
1496
1497 if (vif->type != NL80211_IFTYPE_AP &&
1498 vif->type != NL80211_IFTYPE_AP_VLAN)
1499 return 0;
1500
1501 key = ath_key_config(common, vif, sta, &ps_key);
1502 if (key > 0) {
1503 an->ps_key = key;
1504 an->key_idx[0] = key;
1505 }
1506
1507 return 0;
1508 }
1509
1510 static void ath9k_del_ps_key(struct ath_softc *sc,
1511 struct ieee80211_vif *vif,
1512 struct ieee80211_sta *sta)
1513 {
1514 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1515 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1516 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1517
1518 if (!an->ps_key)
1519 return;
1520
1521 ath_key_delete(common, &ps_key);
1522 an->ps_key = 0;
1523 an->key_idx[0] = 0;
1524 }
1525
1526 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1527 struct ieee80211_vif *vif,
1528 struct ieee80211_sta *sta)
1529 {
1530 struct ath_softc *sc = hw->priv;
1531
1532 ath9k_del_ps_key(sc, vif, sta);
1533 ath_node_detach(sc, sta);
1534
1535 return 0;
1536 }
1537
1538 static int ath9k_sta_state(struct ieee80211_hw *hw,
1539 struct ieee80211_vif *vif,
1540 struct ieee80211_sta *sta,
1541 enum ieee80211_sta_state old_state,
1542 enum ieee80211_sta_state new_state)
1543 {
1544 struct ath_softc *sc = hw->priv;
1545 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1546 int ret = 0;
1547
1548 if (old_state == IEEE80211_STA_AUTH &&
1549 new_state == IEEE80211_STA_ASSOC) {
1550 ret = ath9k_sta_add(hw, vif, sta);
1551 ath_dbg(common, CONFIG,
1552 "Add station: %pM\n", sta->addr);
1553 } else if (old_state == IEEE80211_STA_ASSOC &&
1554 new_state == IEEE80211_STA_AUTH) {
1555 ret = ath9k_sta_remove(hw, vif, sta);
1556 ath_dbg(common, CONFIG,
1557 "Remove station: %pM\n", sta->addr);
1558 }
1559
1560 if (ath9k_is_chanctx_enabled()) {
1561 if (vif->type == NL80211_IFTYPE_STATION) {
1562 if (old_state == IEEE80211_STA_ASSOC &&
1563 new_state == IEEE80211_STA_AUTHORIZED)
1564 ath_chanctx_event(sc, vif,
1565 ATH_CHANCTX_EVENT_AUTHORIZED);
1566 }
1567 }
1568
1569 return ret;
1570 }
1571
1572 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1573 struct ath_node *an,
1574 bool set)
1575 {
1576 int i;
1577
1578 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1579 if (!an->key_idx[i])
1580 continue;
1581 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1582 }
1583 }
1584
1585 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1586 struct ieee80211_vif *vif,
1587 enum sta_notify_cmd cmd,
1588 struct ieee80211_sta *sta)
1589 {
1590 struct ath_softc *sc = hw->priv;
1591 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1592
1593 switch (cmd) {
1594 case STA_NOTIFY_SLEEP:
1595 an->sleeping = true;
1596 ath_tx_aggr_sleep(sta, sc, an);
1597 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1598 break;
1599 case STA_NOTIFY_AWAKE:
1600 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1601 an->sleeping = false;
1602 ath_tx_aggr_wakeup(sc, an);
1603 break;
1604 }
1605 }
1606
1607 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1608 struct ieee80211_vif *vif, u16 queue,
1609 const struct ieee80211_tx_queue_params *params)
1610 {
1611 struct ath_softc *sc = hw->priv;
1612 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1613 struct ath_txq *txq;
1614 struct ath9k_tx_queue_info qi;
1615 int ret = 0;
1616
1617 if (queue >= IEEE80211_NUM_ACS)
1618 return 0;
1619
1620 txq = sc->tx.txq_map[queue];
1621
1622 ath9k_ps_wakeup(sc);
1623 mutex_lock(&sc->mutex);
1624
1625 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1626
1627 qi.tqi_aifs = params->aifs;
1628 qi.tqi_cwmin = params->cw_min;
1629 qi.tqi_cwmax = params->cw_max;
1630 qi.tqi_burstTime = params->txop * 32;
1631
1632 ath_dbg(common, CONFIG,
1633 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1634 queue, txq->axq_qnum, params->aifs, params->cw_min,
1635 params->cw_max, params->txop);
1636
1637 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1638 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1639 if (ret)
1640 ath_err(common, "TXQ Update failed\n");
1641
1642 mutex_unlock(&sc->mutex);
1643 ath9k_ps_restore(sc);
1644
1645 return ret;
1646 }
1647
1648 static int ath9k_set_key(struct ieee80211_hw *hw,
1649 enum set_key_cmd cmd,
1650 struct ieee80211_vif *vif,
1651 struct ieee80211_sta *sta,
1652 struct ieee80211_key_conf *key)
1653 {
1654 struct ath_softc *sc = hw->priv;
1655 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1656 struct ath_node *an = NULL;
1657 int ret = 0, i;
1658
1659 if (ath9k_modparam_nohwcrypt)
1660 return -ENOSPC;
1661
1662 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1663 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1664 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1665 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1666 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1667 /*
1668 * For now, disable hw crypto for the RSN IBSS group keys. This
1669 * could be optimized in the future to use a modified key cache
1670 * design to support per-STA RX GTK, but until that gets
1671 * implemented, use of software crypto for group addressed
1672 * frames is a acceptable to allow RSN IBSS to be used.
1673 */
1674 return -EOPNOTSUPP;
1675 }
1676
1677 mutex_lock(&sc->mutex);
1678 ath9k_ps_wakeup(sc);
1679 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1680 if (sta)
1681 an = (struct ath_node *)sta->drv_priv;
1682
1683 switch (cmd) {
1684 case SET_KEY:
1685 if (sta)
1686 ath9k_del_ps_key(sc, vif, sta);
1687
1688 key->hw_key_idx = 0;
1689 ret = ath_key_config(common, vif, sta, key);
1690 if (ret >= 0) {
1691 key->hw_key_idx = ret;
1692 /* push IV and Michael MIC generation to stack */
1693 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1694 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1695 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1696 if (sc->sc_ah->sw_mgmt_crypto_tx &&
1697 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1698 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1699 ret = 0;
1700 }
1701 if (an && key->hw_key_idx) {
1702 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1703 if (an->key_idx[i])
1704 continue;
1705 an->key_idx[i] = key->hw_key_idx;
1706 break;
1707 }
1708 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1709 }
1710 break;
1711 case DISABLE_KEY:
1712 ath_key_delete(common, key);
1713 if (an) {
1714 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1715 if (an->key_idx[i] != key->hw_key_idx)
1716 continue;
1717 an->key_idx[i] = 0;
1718 break;
1719 }
1720 }
1721 key->hw_key_idx = 0;
1722 break;
1723 default:
1724 ret = -EINVAL;
1725 }
1726
1727 ath9k_ps_restore(sc);
1728 mutex_unlock(&sc->mutex);
1729
1730 return ret;
1731 }
1732
1733 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1734 struct ieee80211_vif *vif,
1735 struct ieee80211_bss_conf *bss_conf,
1736 u32 changed)
1737 {
1738 #define CHECK_ANI \
1739 (BSS_CHANGED_ASSOC | \
1740 BSS_CHANGED_IBSS | \
1741 BSS_CHANGED_BEACON_ENABLED)
1742
1743 struct ath_softc *sc = hw->priv;
1744 struct ath_hw *ah = sc->sc_ah;
1745 struct ath_common *common = ath9k_hw_common(ah);
1746 struct ath_vif *avp = (void *)vif->drv_priv;
1747 int slottime;
1748
1749 ath9k_ps_wakeup(sc);
1750 mutex_lock(&sc->mutex);
1751
1752 if (changed & BSS_CHANGED_ASSOC) {
1753 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1754 bss_conf->bssid, bss_conf->assoc);
1755
1756 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1757 avp->aid = bss_conf->aid;
1758 avp->assoc = bss_conf->assoc;
1759
1760 ath9k_calculate_summary_state(sc, avp->chanctx);
1761 }
1762
1763 if (changed & BSS_CHANGED_IBSS) {
1764 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1765 common->curaid = bss_conf->aid;
1766 ath9k_hw_write_associd(sc->sc_ah);
1767 }
1768
1769 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1770 (changed & BSS_CHANGED_BEACON_INT) ||
1771 (changed & BSS_CHANGED_BEACON_INFO)) {
1772 ath9k_beacon_config(sc, vif, changed);
1773 if (changed & BSS_CHANGED_BEACON_ENABLED)
1774 ath9k_calculate_summary_state(sc, avp->chanctx);
1775 }
1776
1777 if ((avp->chanctx == sc->cur_chan) &&
1778 (changed & BSS_CHANGED_ERP_SLOT)) {
1779 if (bss_conf->use_short_slot)
1780 slottime = 9;
1781 else
1782 slottime = 20;
1783 if (vif->type == NL80211_IFTYPE_AP) {
1784 /*
1785 * Defer update, so that connected stations can adjust
1786 * their settings at the same time.
1787 * See beacon.c for more details
1788 */
1789 sc->beacon.slottime = slottime;
1790 sc->beacon.updateslot = UPDATE;
1791 } else {
1792 ah->slottime = slottime;
1793 ath9k_hw_init_global_settings(ah);
1794 }
1795 }
1796
1797 if (changed & BSS_CHANGED_P2P_PS)
1798 ath9k_p2p_bss_info_changed(sc, vif);
1799
1800 if (changed & CHECK_ANI)
1801 ath_check_ani(sc);
1802
1803 if (changed & BSS_CHANGED_TXPOWER) {
1804 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1805 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1806 ath9k_set_txpower(sc, vif);
1807 }
1808
1809 mutex_unlock(&sc->mutex);
1810 ath9k_ps_restore(sc);
1811
1812 #undef CHECK_ANI
1813 }
1814
1815 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1816 {
1817 struct ath_softc *sc = hw->priv;
1818 u64 tsf;
1819
1820 mutex_lock(&sc->mutex);
1821 ath9k_ps_wakeup(sc);
1822 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1823 ath9k_ps_restore(sc);
1824 mutex_unlock(&sc->mutex);
1825
1826 return tsf;
1827 }
1828
1829 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1830 struct ieee80211_vif *vif,
1831 u64 tsf)
1832 {
1833 struct ath_softc *sc = hw->priv;
1834
1835 mutex_lock(&sc->mutex);
1836 ath9k_ps_wakeup(sc);
1837 ath9k_hw_settsf64(sc->sc_ah, tsf);
1838 ath9k_ps_restore(sc);
1839 mutex_unlock(&sc->mutex);
1840 }
1841
1842 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1843 {
1844 struct ath_softc *sc = hw->priv;
1845
1846 mutex_lock(&sc->mutex);
1847
1848 ath9k_ps_wakeup(sc);
1849 ath9k_hw_reset_tsf(sc->sc_ah);
1850 ath9k_ps_restore(sc);
1851
1852 mutex_unlock(&sc->mutex);
1853 }
1854
1855 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1856 struct ieee80211_vif *vif,
1857 enum ieee80211_ampdu_mlme_action action,
1858 struct ieee80211_sta *sta,
1859 u16 tid, u16 *ssn, u8 buf_size)
1860 {
1861 struct ath_softc *sc = hw->priv;
1862 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1863 bool flush = false;
1864 int ret = 0;
1865
1866 mutex_lock(&sc->mutex);
1867
1868 switch (action) {
1869 case IEEE80211_AMPDU_RX_START:
1870 break;
1871 case IEEE80211_AMPDU_RX_STOP:
1872 break;
1873 case IEEE80211_AMPDU_TX_START:
1874 if (ath9k_is_chanctx_enabled()) {
1875 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
1876 ret = -EBUSY;
1877 break;
1878 }
1879 }
1880 ath9k_ps_wakeup(sc);
1881 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1882 if (!ret)
1883 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1884 ath9k_ps_restore(sc);
1885 break;
1886 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1887 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1888 flush = true;
1889 case IEEE80211_AMPDU_TX_STOP_CONT:
1890 ath9k_ps_wakeup(sc);
1891 ath_tx_aggr_stop(sc, sta, tid);
1892 if (!flush)
1893 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1894 ath9k_ps_restore(sc);
1895 break;
1896 case IEEE80211_AMPDU_TX_OPERATIONAL:
1897 ath9k_ps_wakeup(sc);
1898 ath_tx_aggr_resume(sc, sta, tid);
1899 ath9k_ps_restore(sc);
1900 break;
1901 default:
1902 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1903 }
1904
1905 mutex_unlock(&sc->mutex);
1906
1907 return ret;
1908 }
1909
1910 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1911 struct survey_info *survey)
1912 {
1913 struct ath_softc *sc = hw->priv;
1914 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1915 struct ieee80211_supported_band *sband;
1916 struct ieee80211_channel *chan;
1917 int pos;
1918
1919 if (config_enabled(CONFIG_ATH9K_TX99))
1920 return -EOPNOTSUPP;
1921
1922 spin_lock_bh(&common->cc_lock);
1923 if (idx == 0)
1924 ath_update_survey_stats(sc);
1925
1926 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1927 if (sband && idx >= sband->n_channels) {
1928 idx -= sband->n_channels;
1929 sband = NULL;
1930 }
1931
1932 if (!sband)
1933 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1934
1935 if (!sband || idx >= sband->n_channels) {
1936 spin_unlock_bh(&common->cc_lock);
1937 return -ENOENT;
1938 }
1939
1940 chan = &sband->channels[idx];
1941 pos = chan->hw_value;
1942 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1943 survey->channel = chan;
1944 spin_unlock_bh(&common->cc_lock);
1945
1946 return 0;
1947 }
1948
1949 static void ath9k_enable_dynack(struct ath_softc *sc)
1950 {
1951 #ifdef CONFIG_ATH9K_DYNACK
1952 u32 rfilt;
1953 struct ath_hw *ah = sc->sc_ah;
1954
1955 ath_dynack_reset(ah);
1956
1957 ah->dynack.enabled = true;
1958 rfilt = ath_calcrxfilter(sc);
1959 ath9k_hw_setrxfilter(ah, rfilt);
1960 #endif
1961 }
1962
1963 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
1964 s16 coverage_class)
1965 {
1966 struct ath_softc *sc = hw->priv;
1967 struct ath_hw *ah = sc->sc_ah;
1968
1969 if (config_enabled(CONFIG_ATH9K_TX99))
1970 return;
1971
1972 mutex_lock(&sc->mutex);
1973
1974 if (coverage_class >= 0) {
1975 ah->coverage_class = coverage_class;
1976 if (ah->dynack.enabled) {
1977 u32 rfilt;
1978
1979 ah->dynack.enabled = false;
1980 rfilt = ath_calcrxfilter(sc);
1981 ath9k_hw_setrxfilter(ah, rfilt);
1982 }
1983 ath9k_ps_wakeup(sc);
1984 ath9k_hw_init_global_settings(ah);
1985 ath9k_ps_restore(sc);
1986 } else if (!ah->dynack.enabled) {
1987 ath9k_enable_dynack(sc);
1988 }
1989
1990 mutex_unlock(&sc->mutex);
1991 }
1992
1993 static bool ath9k_has_tx_pending(struct ath_softc *sc,
1994 bool sw_pending)
1995 {
1996 int i, npend = 0;
1997
1998 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1999 if (!ATH_TXQ_SETUP(sc, i))
2000 continue;
2001
2002 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2003 sw_pending);
2004 if (npend)
2005 break;
2006 }
2007
2008 return !!npend;
2009 }
2010
2011 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2012 u32 queues, bool drop)
2013 {
2014 struct ath_softc *sc = hw->priv;
2015 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2016
2017 if (ath9k_is_chanctx_enabled()) {
2018 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2019 goto flush;
2020
2021 /*
2022 * If MCC is active, extend the flush timeout
2023 * and wait for the HW/SW queues to become
2024 * empty. This needs to be done outside the
2025 * sc->mutex lock to allow the channel scheduler
2026 * to switch channel contexts.
2027 *
2028 * The vif queues have been stopped in mac80211,
2029 * so there won't be any incoming frames.
2030 */
2031 __ath9k_flush(hw, queues, drop, true, true);
2032 return;
2033 }
2034 flush:
2035 mutex_lock(&sc->mutex);
2036 __ath9k_flush(hw, queues, drop, true, false);
2037 mutex_unlock(&sc->mutex);
2038 }
2039
2040 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2041 bool sw_pending, bool timeout_override)
2042 {
2043 struct ath_softc *sc = hw->priv;
2044 struct ath_hw *ah = sc->sc_ah;
2045 struct ath_common *common = ath9k_hw_common(ah);
2046 int timeout;
2047 bool drain_txq;
2048
2049 cancel_delayed_work_sync(&sc->tx_complete_work);
2050
2051 if (ah->ah_flags & AH_UNPLUGGED) {
2052 ath_dbg(common, ANY, "Device has been unplugged!\n");
2053 return;
2054 }
2055
2056 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2057 ath_dbg(common, ANY, "Device not present\n");
2058 return;
2059 }
2060
2061 spin_lock_bh(&sc->chan_lock);
2062 if (timeout_override)
2063 timeout = HZ / 5;
2064 else
2065 timeout = sc->cur_chan->flush_timeout;
2066 spin_unlock_bh(&sc->chan_lock);
2067
2068 ath_dbg(common, CHAN_CTX,
2069 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2070
2071 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2072 timeout) > 0)
2073 drop = false;
2074
2075 if (drop) {
2076 ath9k_ps_wakeup(sc);
2077 spin_lock_bh(&sc->sc_pcu_lock);
2078 drain_txq = ath_drain_all_txq(sc);
2079 spin_unlock_bh(&sc->sc_pcu_lock);
2080
2081 if (!drain_txq)
2082 ath_reset(sc, NULL);
2083
2084 ath9k_ps_restore(sc);
2085 }
2086
2087 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2088 }
2089
2090 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2091 {
2092 struct ath_softc *sc = hw->priv;
2093
2094 return ath9k_has_tx_pending(sc, true);
2095 }
2096
2097 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2098 {
2099 struct ath_softc *sc = hw->priv;
2100 struct ath_hw *ah = sc->sc_ah;
2101 struct ieee80211_vif *vif;
2102 struct ath_vif *avp;
2103 struct ath_buf *bf;
2104 struct ath_tx_status ts;
2105 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2106 int status;
2107
2108 vif = sc->beacon.bslot[0];
2109 if (!vif)
2110 return 0;
2111
2112 if (!vif->bss_conf.enable_beacon)
2113 return 0;
2114
2115 avp = (void *)vif->drv_priv;
2116
2117 if (!sc->beacon.tx_processed && !edma) {
2118 tasklet_disable(&sc->bcon_tasklet);
2119
2120 bf = avp->av_bcbuf;
2121 if (!bf || !bf->bf_mpdu)
2122 goto skip;
2123
2124 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2125 if (status == -EINPROGRESS)
2126 goto skip;
2127
2128 sc->beacon.tx_processed = true;
2129 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2130
2131 skip:
2132 tasklet_enable(&sc->bcon_tasklet);
2133 }
2134
2135 return sc->beacon.tx_last;
2136 }
2137
2138 static int ath9k_get_stats(struct ieee80211_hw *hw,
2139 struct ieee80211_low_level_stats *stats)
2140 {
2141 struct ath_softc *sc = hw->priv;
2142 struct ath_hw *ah = sc->sc_ah;
2143 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2144
2145 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2146 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2147 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2148 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2149 return 0;
2150 }
2151
2152 static u32 fill_chainmask(u32 cap, u32 new)
2153 {
2154 u32 filled = 0;
2155 int i;
2156
2157 for (i = 0; cap && new; i++, cap >>= 1) {
2158 if (!(cap & BIT(0)))
2159 continue;
2160
2161 if (new & BIT(0))
2162 filled |= BIT(i);
2163
2164 new >>= 1;
2165 }
2166
2167 return filled;
2168 }
2169
2170 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2171 {
2172 if (AR_SREV_9300_20_OR_LATER(ah))
2173 return true;
2174
2175 switch (val & 0x7) {
2176 case 0x1:
2177 case 0x3:
2178 case 0x7:
2179 return true;
2180 case 0x2:
2181 return (ah->caps.rx_chainmask == 1);
2182 default:
2183 return false;
2184 }
2185 }
2186
2187 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2188 {
2189 struct ath_softc *sc = hw->priv;
2190 struct ath_hw *ah = sc->sc_ah;
2191
2192 if (ah->caps.rx_chainmask != 1)
2193 rx_ant |= tx_ant;
2194
2195 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2196 return -EINVAL;
2197
2198 sc->ant_rx = rx_ant;
2199 sc->ant_tx = tx_ant;
2200
2201 if (ah->caps.rx_chainmask == 1)
2202 return 0;
2203
2204 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2205 if (AR_SREV_9100(ah))
2206 ah->rxchainmask = 0x7;
2207 else
2208 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2209
2210 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2211 ath9k_cmn_reload_chainmask(ah);
2212
2213 return 0;
2214 }
2215
2216 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2217 {
2218 struct ath_softc *sc = hw->priv;
2219
2220 *tx_ant = sc->ant_tx;
2221 *rx_ant = sc->ant_rx;
2222 return 0;
2223 }
2224
2225 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2226 struct ieee80211_vif *vif,
2227 const u8 *mac_addr)
2228 {
2229 struct ath_softc *sc = hw->priv;
2230 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2231 set_bit(ATH_OP_SCANNING, &common->op_flags);
2232 }
2233
2234 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2235 struct ieee80211_vif *vif)
2236 {
2237 struct ath_softc *sc = hw->priv;
2238 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2239 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2240 }
2241
2242 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2243
2244 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2245 {
2246 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2247
2248 if (sc->offchannel.roc_vif) {
2249 ath_dbg(common, CHAN_CTX,
2250 "%s: Aborting RoC\n", __func__);
2251
2252 del_timer_sync(&sc->offchannel.timer);
2253 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2254 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2255 }
2256
2257 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2258 ath_dbg(common, CHAN_CTX,
2259 "%s: Aborting HW scan\n", __func__);
2260
2261 del_timer_sync(&sc->offchannel.timer);
2262 ath_scan_complete(sc, true);
2263 }
2264 }
2265
2266 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2267 struct ieee80211_scan_request *hw_req)
2268 {
2269 struct cfg80211_scan_request *req = &hw_req->req;
2270 struct ath_softc *sc = hw->priv;
2271 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2272 int ret = 0;
2273
2274 mutex_lock(&sc->mutex);
2275
2276 if (WARN_ON(sc->offchannel.scan_req)) {
2277 ret = -EBUSY;
2278 goto out;
2279 }
2280
2281 ath9k_ps_wakeup(sc);
2282 set_bit(ATH_OP_SCANNING, &common->op_flags);
2283 sc->offchannel.scan_vif = vif;
2284 sc->offchannel.scan_req = req;
2285 sc->offchannel.scan_idx = 0;
2286
2287 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2288 vif->addr);
2289
2290 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2291 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2292 ath_offchannel_next(sc);
2293 }
2294
2295 out:
2296 mutex_unlock(&sc->mutex);
2297
2298 return ret;
2299 }
2300
2301 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2302 struct ieee80211_vif *vif)
2303 {
2304 struct ath_softc *sc = hw->priv;
2305 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2306
2307 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2308
2309 mutex_lock(&sc->mutex);
2310 del_timer_sync(&sc->offchannel.timer);
2311 ath_scan_complete(sc, true);
2312 mutex_unlock(&sc->mutex);
2313 }
2314
2315 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2316 struct ieee80211_vif *vif,
2317 struct ieee80211_channel *chan, int duration,
2318 enum ieee80211_roc_type type)
2319 {
2320 struct ath_softc *sc = hw->priv;
2321 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2322 int ret = 0;
2323
2324 mutex_lock(&sc->mutex);
2325
2326 if (WARN_ON(sc->offchannel.roc_vif)) {
2327 ret = -EBUSY;
2328 goto out;
2329 }
2330
2331 ath9k_ps_wakeup(sc);
2332 sc->offchannel.roc_vif = vif;
2333 sc->offchannel.roc_chan = chan;
2334 sc->offchannel.roc_duration = duration;
2335
2336 ath_dbg(common, CHAN_CTX,
2337 "RoC request on vif: %pM, type: %d duration: %d\n",
2338 vif->addr, type, duration);
2339
2340 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2341 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2342 ath_offchannel_next(sc);
2343 }
2344
2345 out:
2346 mutex_unlock(&sc->mutex);
2347
2348 return ret;
2349 }
2350
2351 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2352 {
2353 struct ath_softc *sc = hw->priv;
2354 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2355
2356 mutex_lock(&sc->mutex);
2357
2358 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2359 del_timer_sync(&sc->offchannel.timer);
2360
2361 if (sc->offchannel.roc_vif) {
2362 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2363 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2364 }
2365
2366 mutex_unlock(&sc->mutex);
2367
2368 return 0;
2369 }
2370
2371 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2372 struct ieee80211_chanctx_conf *conf)
2373 {
2374 struct ath_softc *sc = hw->priv;
2375 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2376 struct ath_chanctx *ctx, **ptr;
2377 int pos;
2378
2379 mutex_lock(&sc->mutex);
2380
2381 ath_for_each_chanctx(sc, ctx) {
2382 if (ctx->assigned)
2383 continue;
2384
2385 ptr = (void *) conf->drv_priv;
2386 *ptr = ctx;
2387 ctx->assigned = true;
2388 pos = ctx - &sc->chanctx[0];
2389 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2390
2391 ath_dbg(common, CHAN_CTX,
2392 "Add channel context: %d MHz\n",
2393 conf->def.chan->center_freq);
2394
2395 ath_chanctx_set_channel(sc, ctx, &conf->def);
2396
2397 mutex_unlock(&sc->mutex);
2398 return 0;
2399 }
2400
2401 mutex_unlock(&sc->mutex);
2402 return -ENOSPC;
2403 }
2404
2405
2406 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2407 struct ieee80211_chanctx_conf *conf)
2408 {
2409 struct ath_softc *sc = hw->priv;
2410 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2411 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2412
2413 mutex_lock(&sc->mutex);
2414
2415 ath_dbg(common, CHAN_CTX,
2416 "Remove channel context: %d MHz\n",
2417 conf->def.chan->center_freq);
2418
2419 ctx->assigned = false;
2420 ctx->hw_queue_base = 0;
2421 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2422
2423 mutex_unlock(&sc->mutex);
2424 }
2425
2426 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2427 struct ieee80211_chanctx_conf *conf,
2428 u32 changed)
2429 {
2430 struct ath_softc *sc = hw->priv;
2431 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2432 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2433
2434 mutex_lock(&sc->mutex);
2435 ath_dbg(common, CHAN_CTX,
2436 "Change channel context: %d MHz\n",
2437 conf->def.chan->center_freq);
2438 ath_chanctx_set_channel(sc, ctx, &conf->def);
2439 mutex_unlock(&sc->mutex);
2440 }
2441
2442 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2443 struct ieee80211_vif *vif,
2444 struct ieee80211_chanctx_conf *conf)
2445 {
2446 struct ath_softc *sc = hw->priv;
2447 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2448 struct ath_vif *avp = (void *)vif->drv_priv;
2449 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2450 int i;
2451
2452 ath9k_cancel_pending_offchannel(sc);
2453
2454 mutex_lock(&sc->mutex);
2455
2456 ath_dbg(common, CHAN_CTX,
2457 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2458 vif->addr, vif->type, vif->p2p,
2459 conf->def.chan->center_freq);
2460
2461 avp->chanctx = ctx;
2462 ctx->nvifs_assigned++;
2463 list_add_tail(&avp->list, &ctx->vifs);
2464 ath9k_calculate_summary_state(sc, ctx);
2465 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2466 vif->hw_queue[i] = ctx->hw_queue_base + i;
2467
2468 mutex_unlock(&sc->mutex);
2469
2470 return 0;
2471 }
2472
2473 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2474 struct ieee80211_vif *vif,
2475 struct ieee80211_chanctx_conf *conf)
2476 {
2477 struct ath_softc *sc = hw->priv;
2478 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2479 struct ath_vif *avp = (void *)vif->drv_priv;
2480 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2481 int ac;
2482
2483 ath9k_cancel_pending_offchannel(sc);
2484
2485 mutex_lock(&sc->mutex);
2486
2487 ath_dbg(common, CHAN_CTX,
2488 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2489 vif->addr, vif->type, vif->p2p,
2490 conf->def.chan->center_freq);
2491
2492 avp->chanctx = NULL;
2493 ctx->nvifs_assigned--;
2494 list_del(&avp->list);
2495 ath9k_calculate_summary_state(sc, ctx);
2496 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2497 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2498
2499 mutex_unlock(&sc->mutex);
2500 }
2501
2502 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2503 struct ieee80211_vif *vif)
2504 {
2505 struct ath_softc *sc = hw->priv;
2506 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2507 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2508 struct ath_beacon_config *cur_conf;
2509 struct ath_chanctx *go_ctx;
2510 unsigned long timeout;
2511 bool changed = false;
2512 u32 beacon_int;
2513
2514 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2515 return;
2516
2517 if (!avp->chanctx)
2518 return;
2519
2520 mutex_lock(&sc->mutex);
2521
2522 spin_lock_bh(&sc->chan_lock);
2523 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2524 changed = true;
2525 spin_unlock_bh(&sc->chan_lock);
2526
2527 if (!changed)
2528 goto out;
2529
2530 ath9k_cancel_pending_offchannel(sc);
2531
2532 go_ctx = ath_is_go_chanctx_present(sc);
2533
2534 if (go_ctx) {
2535 /*
2536 * Wait till the GO interface gets a chance
2537 * to send out an NoA.
2538 */
2539 spin_lock_bh(&sc->chan_lock);
2540 sc->sched.mgd_prepare_tx = true;
2541 cur_conf = &go_ctx->beacon;
2542 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2543 spin_unlock_bh(&sc->chan_lock);
2544
2545 timeout = usecs_to_jiffies(beacon_int * 2);
2546 init_completion(&sc->go_beacon);
2547
2548 mutex_unlock(&sc->mutex);
2549
2550 if (wait_for_completion_timeout(&sc->go_beacon,
2551 timeout) == 0) {
2552 ath_dbg(common, CHAN_CTX,
2553 "Failed to send new NoA\n");
2554
2555 spin_lock_bh(&sc->chan_lock);
2556 sc->sched.mgd_prepare_tx = false;
2557 spin_unlock_bh(&sc->chan_lock);
2558 }
2559
2560 mutex_lock(&sc->mutex);
2561 }
2562
2563 ath_dbg(common, CHAN_CTX,
2564 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2565 __func__, vif->addr);
2566
2567 spin_lock_bh(&sc->chan_lock);
2568 sc->next_chan = avp->chanctx;
2569 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2570 spin_unlock_bh(&sc->chan_lock);
2571
2572 ath_chanctx_set_next(sc, true);
2573 out:
2574 mutex_unlock(&sc->mutex);
2575 }
2576
2577 void ath9k_fill_chanctx_ops(void)
2578 {
2579 if (!ath9k_is_chanctx_enabled())
2580 return;
2581
2582 ath9k_ops.hw_scan = ath9k_hw_scan;
2583 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2584 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2585 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2586 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2587 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2588 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2589 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2590 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2591 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2592 }
2593
2594 #endif
2595
2596 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2597 int *dbm)
2598 {
2599 struct ath_softc *sc = hw->priv;
2600 struct ath_vif *avp = (void *)vif->drv_priv;
2601
2602 mutex_lock(&sc->mutex);
2603 if (avp->chanctx)
2604 *dbm = avp->chanctx->cur_txpower;
2605 else
2606 *dbm = sc->cur_chan->cur_txpower;
2607 mutex_unlock(&sc->mutex);
2608
2609 *dbm /= 2;
2610
2611 return 0;
2612 }
2613
2614 struct ieee80211_ops ath9k_ops = {
2615 .tx = ath9k_tx,
2616 .start = ath9k_start,
2617 .stop = ath9k_stop,
2618 .add_interface = ath9k_add_interface,
2619 .change_interface = ath9k_change_interface,
2620 .remove_interface = ath9k_remove_interface,
2621 .config = ath9k_config,
2622 .configure_filter = ath9k_configure_filter,
2623 .sta_state = ath9k_sta_state,
2624 .sta_notify = ath9k_sta_notify,
2625 .conf_tx = ath9k_conf_tx,
2626 .bss_info_changed = ath9k_bss_info_changed,
2627 .set_key = ath9k_set_key,
2628 .get_tsf = ath9k_get_tsf,
2629 .set_tsf = ath9k_set_tsf,
2630 .reset_tsf = ath9k_reset_tsf,
2631 .ampdu_action = ath9k_ampdu_action,
2632 .get_survey = ath9k_get_survey,
2633 .rfkill_poll = ath9k_rfkill_poll_state,
2634 .set_coverage_class = ath9k_set_coverage_class,
2635 .flush = ath9k_flush,
2636 .tx_frames_pending = ath9k_tx_frames_pending,
2637 .tx_last_beacon = ath9k_tx_last_beacon,
2638 .release_buffered_frames = ath9k_release_buffered_frames,
2639 .get_stats = ath9k_get_stats,
2640 .set_antenna = ath9k_set_antenna,
2641 .get_antenna = ath9k_get_antenna,
2642
2643 #ifdef CONFIG_ATH9K_WOW
2644 .suspend = ath9k_suspend,
2645 .resume = ath9k_resume,
2646 .set_wakeup = ath9k_set_wakeup,
2647 #endif
2648
2649 #ifdef CONFIG_ATH9K_DEBUGFS
2650 .get_et_sset_count = ath9k_get_et_sset_count,
2651 .get_et_stats = ath9k_get_et_stats,
2652 .get_et_strings = ath9k_get_et_strings,
2653 #endif
2654
2655 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2656 .sta_add_debugfs = ath9k_sta_add_debugfs,
2657 #endif
2658 .sw_scan_start = ath9k_sw_scan_start,
2659 .sw_scan_complete = ath9k_sw_scan_complete,
2660 .get_txpower = ath9k_get_txpower,
2661 };
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