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Merge branch 'for-john' of git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac802...
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58 }
59
60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61 {
62 bool pending = false;
63
64 spin_lock_bh(&txq->axq_lock);
65
66 if (txq->axq_depth || !list_empty(&txq->axq_acq))
67 pending = true;
68
69 spin_unlock_bh(&txq->axq_lock);
70 return pending;
71 }
72
73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
74 {
75 unsigned long flags;
76 bool ret;
77
78 spin_lock_irqsave(&sc->sc_pm_lock, flags);
79 ret = ath9k_hw_setpower(sc->sc_ah, mode);
80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
81
82 return ret;
83 }
84
85 void ath9k_ps_wakeup(struct ath_softc *sc)
86 {
87 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
88 unsigned long flags;
89 enum ath9k_power_mode power_mode;
90
91 spin_lock_irqsave(&sc->sc_pm_lock, flags);
92 if (++sc->ps_usecount != 1)
93 goto unlock;
94
95 power_mode = sc->sc_ah->power_mode;
96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
97
98 /*
99 * While the hardware is asleep, the cycle counters contain no
100 * useful data. Better clear them now so that they don't mess up
101 * survey data results.
102 */
103 if (power_mode != ATH9K_PM_AWAKE) {
104 spin_lock(&common->cc_lock);
105 ath_hw_cycle_counters_update(common);
106 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
107 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
108 spin_unlock(&common->cc_lock);
109 }
110
111 unlock:
112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
113 }
114
115 void ath9k_ps_restore(struct ath_softc *sc)
116 {
117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
118 enum ath9k_power_mode mode;
119 unsigned long flags;
120 bool reset;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (--sc->ps_usecount != 0)
124 goto unlock;
125
126 if (sc->ps_idle) {
127 ath9k_hw_setrxabort(sc->sc_ah, 1);
128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
129 mode = ATH9K_PM_FULL_SLEEP;
130 } else if (sc->ps_enabled &&
131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
132 PS_WAIT_FOR_CAB |
133 PS_WAIT_FOR_PSPOLL_DATA |
134 PS_WAIT_FOR_TX_ACK |
135 PS_WAIT_FOR_ANI))) {
136 mode = ATH9K_PM_NETWORK_SLEEP;
137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
138 ath9k_btcoex_stop_gen_timer(sc);
139 } else {
140 goto unlock;
141 }
142
143 spin_lock(&common->cc_lock);
144 ath_hw_cycle_counters_update(common);
145 spin_unlock(&common->cc_lock);
146
147 ath9k_hw_setpower(sc->sc_ah, mode);
148
149 unlock:
150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
151 }
152
153 static void __ath_cancel_work(struct ath_softc *sc)
154 {
155 cancel_work_sync(&sc->paprd_work);
156 cancel_work_sync(&sc->hw_check_work);
157 cancel_delayed_work_sync(&sc->tx_complete_work);
158 cancel_delayed_work_sync(&sc->hw_pll_work);
159
160 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
161 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
162 cancel_work_sync(&sc->mci_work);
163 #endif
164 }
165
166 static void ath_cancel_work(struct ath_softc *sc)
167 {
168 __ath_cancel_work(sc);
169 cancel_work_sync(&sc->hw_reset_work);
170 }
171
172 static void ath_restart_work(struct ath_softc *sc)
173 {
174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
175
176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
177 AR_SREV_9550(sc->sc_ah))
178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
180
181 ath_start_rx_poll(sc, 3);
182 ath_start_ani(sc);
183 }
184
185 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
186 {
187 struct ath_hw *ah = sc->sc_ah;
188 bool ret = true;
189
190 ieee80211_stop_queues(sc->hw);
191
192 sc->hw_busy_count = 0;
193 ath_stop_ani(sc);
194 del_timer_sync(&sc->rx_poll_timer);
195
196 ath9k_debug_samp_bb_mac(sc);
197 ath9k_hw_disable_interrupts(ah);
198
199 if (!ath_stoprecv(sc))
200 ret = false;
201
202 if (!ath_drain_all_txq(sc, retry_tx))
203 ret = false;
204
205 if (!flush) {
206 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
207 ath_rx_tasklet(sc, 1, true);
208 ath_rx_tasklet(sc, 1, false);
209 } else {
210 ath_flushrecv(sc);
211 }
212
213 return ret;
214 }
215
216 static bool ath_complete_reset(struct ath_softc *sc, bool start)
217 {
218 struct ath_hw *ah = sc->sc_ah;
219 struct ath_common *common = ath9k_hw_common(ah);
220 unsigned long flags;
221
222 if (ath_startrecv(sc) != 0) {
223 ath_err(common, "Unable to restart recv logic\n");
224 return false;
225 }
226
227 ath9k_cmn_update_txpow(ah, sc->curtxpow,
228 sc->config.txpowlimit, &sc->curtxpow);
229
230 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
231 ath9k_hw_set_interrupts(ah);
232 ath9k_hw_enable_interrupts(ah);
233
234 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
235 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
236 goto work;
237
238 ath9k_set_beacon(sc);
239
240 if (ah->opmode == NL80211_IFTYPE_STATION &&
241 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
242 spin_lock_irqsave(&sc->sc_pm_lock, flags);
243 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
244 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
245 }
246 work:
247 ath_restart_work(sc);
248 }
249
250 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
251 ath_ant_comb_update(sc);
252
253 ieee80211_wake_queues(sc->hw);
254
255 return true;
256 }
257
258 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
259 bool retry_tx)
260 {
261 struct ath_hw *ah = sc->sc_ah;
262 struct ath_common *common = ath9k_hw_common(ah);
263 struct ath9k_hw_cal_data *caldata = NULL;
264 bool fastcc = true;
265 bool flush = false;
266 int r;
267
268 __ath_cancel_work(sc);
269
270 spin_lock_bh(&sc->sc_pcu_lock);
271
272 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
273 fastcc = false;
274 caldata = &sc->caldata;
275 }
276
277 if (!hchan) {
278 fastcc = false;
279 flush = true;
280 hchan = ah->curchan;
281 }
282
283 if (!ath_prepare_reset(sc, retry_tx, flush))
284 fastcc = false;
285
286 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
287 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
288
289 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
290 if (r) {
291 ath_err(common,
292 "Unable to reset channel, reset status %d\n", r);
293 goto out;
294 }
295
296 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
297 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
298 ath9k_mci_set_txpower(sc, true, false);
299
300 if (!ath_complete_reset(sc, true))
301 r = -EIO;
302
303 out:
304 spin_unlock_bh(&sc->sc_pcu_lock);
305 return r;
306 }
307
308
309 /*
310 * Set/change channels. If the channel is really being changed, it's done
311 * by reseting the chip. To accomplish this we must first cleanup any pending
312 * DMA, then restart stuff.
313 */
314 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
315 struct ath9k_channel *hchan)
316 {
317 int r;
318
319 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
320 return -EIO;
321
322 r = ath_reset_internal(sc, hchan, false);
323
324 return r;
325 }
326
327 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
328 struct ieee80211_vif *vif)
329 {
330 struct ath_node *an;
331 u8 density;
332 an = (struct ath_node *)sta->drv_priv;
333
334 #ifdef CONFIG_ATH9K_DEBUGFS
335 spin_lock(&sc->nodes_lock);
336 list_add(&an->list, &sc->nodes);
337 spin_unlock(&sc->nodes_lock);
338 #endif
339 an->sta = sta;
340 an->vif = vif;
341
342 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
343 ath_tx_node_init(sc, an);
344 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
345 sta->ht_cap.ampdu_factor);
346 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
347 an->mpdudensity = density;
348 }
349 }
350
351 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
352 {
353 struct ath_node *an = (struct ath_node *)sta->drv_priv;
354
355 #ifdef CONFIG_ATH9K_DEBUGFS
356 spin_lock(&sc->nodes_lock);
357 list_del(&an->list);
358 spin_unlock(&sc->nodes_lock);
359 an->sta = NULL;
360 #endif
361
362 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
363 ath_tx_node_cleanup(sc, an);
364 }
365
366 void ath9k_tasklet(unsigned long data)
367 {
368 struct ath_softc *sc = (struct ath_softc *)data;
369 struct ath_hw *ah = sc->sc_ah;
370 struct ath_common *common = ath9k_hw_common(ah);
371 enum ath_reset_type type;
372 unsigned long flags;
373 u32 status = sc->intrstatus;
374 u32 rxmask;
375
376 ath9k_ps_wakeup(sc);
377 spin_lock(&sc->sc_pcu_lock);
378
379 if ((status & ATH9K_INT_FATAL) ||
380 (status & ATH9K_INT_BB_WATCHDOG)) {
381
382 if (status & ATH9K_INT_FATAL)
383 type = RESET_TYPE_FATAL_INT;
384 else
385 type = RESET_TYPE_BB_WATCHDOG;
386
387 ath9k_queue_reset(sc, type);
388 goto out;
389 }
390
391 spin_lock_irqsave(&sc->sc_pm_lock, flags);
392 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
393 /*
394 * TSF sync does not look correct; remain awake to sync with
395 * the next Beacon.
396 */
397 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
398 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
399 }
400 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
401
402 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
403 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
404 ATH9K_INT_RXORN);
405 else
406 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
407
408 if (status & rxmask) {
409 /* Check for high priority Rx first */
410 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
411 (status & ATH9K_INT_RXHP))
412 ath_rx_tasklet(sc, 0, true);
413
414 ath_rx_tasklet(sc, 0, false);
415 }
416
417 if (status & ATH9K_INT_TX) {
418 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
419 ath_tx_edma_tasklet(sc);
420 else
421 ath_tx_tasklet(sc);
422 }
423
424 ath9k_btcoex_handle_interrupt(sc, status);
425
426 out:
427 /* re-enable hardware interrupt */
428 ath9k_hw_enable_interrupts(ah);
429
430 spin_unlock(&sc->sc_pcu_lock);
431 ath9k_ps_restore(sc);
432 }
433
434 irqreturn_t ath_isr(int irq, void *dev)
435 {
436 #define SCHED_INTR ( \
437 ATH9K_INT_FATAL | \
438 ATH9K_INT_BB_WATCHDOG | \
439 ATH9K_INT_RXORN | \
440 ATH9K_INT_RXEOL | \
441 ATH9K_INT_RX | \
442 ATH9K_INT_RXLP | \
443 ATH9K_INT_RXHP | \
444 ATH9K_INT_TX | \
445 ATH9K_INT_BMISS | \
446 ATH9K_INT_CST | \
447 ATH9K_INT_TSFOOR | \
448 ATH9K_INT_GENTIMER | \
449 ATH9K_INT_MCI)
450
451 struct ath_softc *sc = dev;
452 struct ath_hw *ah = sc->sc_ah;
453 struct ath_common *common = ath9k_hw_common(ah);
454 enum ath9k_int status;
455 bool sched = false;
456
457 /*
458 * The hardware is not ready/present, don't
459 * touch anything. Note this can happen early
460 * on if the IRQ is shared.
461 */
462 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
463 return IRQ_NONE;
464
465 /* shared irq, not for us */
466
467 if (!ath9k_hw_intrpend(ah))
468 return IRQ_NONE;
469
470 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
471 ath9k_hw_kill_interrupts(ah);
472 return IRQ_HANDLED;
473 }
474
475 /*
476 * Figure out the reason(s) for the interrupt. Note
477 * that the hal returns a pseudo-ISR that may include
478 * bits we haven't explicitly enabled so we mask the
479 * value to insure we only process bits we requested.
480 */
481 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
482 status &= ah->imask; /* discard unasked-for bits */
483
484 /*
485 * If there are no status bits set, then this interrupt was not
486 * for me (should have been caught above).
487 */
488 if (!status)
489 return IRQ_NONE;
490
491 /* Cache the status */
492 sc->intrstatus = status;
493
494 if (status & SCHED_INTR)
495 sched = true;
496
497 #ifdef CONFIG_PM_SLEEP
498 if (status & ATH9K_INT_BMISS) {
499 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
500 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
501 atomic_inc(&sc->wow_got_bmiss_intr);
502 atomic_dec(&sc->wow_sleep_proc_intr);
503 }
504 ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
505 }
506 #endif
507
508 /*
509 * If a FATAL or RXORN interrupt is received, we have to reset the
510 * chip immediately.
511 */
512 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
513 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
514 goto chip_reset;
515
516 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
517 (status & ATH9K_INT_BB_WATCHDOG)) {
518
519 spin_lock(&common->cc_lock);
520 ath_hw_cycle_counters_update(common);
521 ar9003_hw_bb_watchdog_dbg_info(ah);
522 spin_unlock(&common->cc_lock);
523
524 goto chip_reset;
525 }
526
527 if (status & ATH9K_INT_SWBA)
528 tasklet_schedule(&sc->bcon_tasklet);
529
530 if (status & ATH9K_INT_TXURN)
531 ath9k_hw_updatetxtriglevel(ah, true);
532
533 if (status & ATH9K_INT_RXEOL) {
534 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
535 ath9k_hw_set_interrupts(ah);
536 }
537
538 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
539 if (status & ATH9K_INT_TIM_TIMER) {
540 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
541 goto chip_reset;
542 /* Clear RxAbort bit so that we can
543 * receive frames */
544 ath9k_setpower(sc, ATH9K_PM_AWAKE);
545 spin_lock(&sc->sc_pm_lock);
546 ath9k_hw_setrxabort(sc->sc_ah, 0);
547 sc->ps_flags |= PS_WAIT_FOR_BEACON;
548 spin_unlock(&sc->sc_pm_lock);
549 }
550
551 chip_reset:
552
553 ath_debug_stat_interrupt(sc, status);
554
555 if (sched) {
556 /* turn off every interrupt */
557 ath9k_hw_disable_interrupts(ah);
558 tasklet_schedule(&sc->intr_tq);
559 }
560
561 return IRQ_HANDLED;
562
563 #undef SCHED_INTR
564 }
565
566 static int ath_reset(struct ath_softc *sc, bool retry_tx)
567 {
568 int r;
569
570 ath9k_ps_wakeup(sc);
571
572 r = ath_reset_internal(sc, NULL, retry_tx);
573
574 if (retry_tx) {
575 int i;
576 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
577 if (ATH_TXQ_SETUP(sc, i)) {
578 spin_lock_bh(&sc->tx.txq[i].axq_lock);
579 ath_txq_schedule(sc, &sc->tx.txq[i]);
580 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
581 }
582 }
583 }
584
585 ath9k_ps_restore(sc);
586
587 return r;
588 }
589
590 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
591 {
592 #ifdef CONFIG_ATH9K_DEBUGFS
593 RESET_STAT_INC(sc, type);
594 #endif
595 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
596 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
597 }
598
599 void ath_reset_work(struct work_struct *work)
600 {
601 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
602
603 ath_reset(sc, true);
604 }
605
606 /**********************/
607 /* mac80211 callbacks */
608 /**********************/
609
610 static int ath9k_start(struct ieee80211_hw *hw)
611 {
612 struct ath_softc *sc = hw->priv;
613 struct ath_hw *ah = sc->sc_ah;
614 struct ath_common *common = ath9k_hw_common(ah);
615 struct ieee80211_channel *curchan = hw->conf.channel;
616 struct ath9k_channel *init_channel;
617 int r;
618
619 ath_dbg(common, CONFIG,
620 "Starting driver with initial channel: %d MHz\n",
621 curchan->center_freq);
622
623 ath9k_ps_wakeup(sc);
624 mutex_lock(&sc->mutex);
625
626 init_channel = ath9k_cmn_get_curchannel(hw, ah);
627
628 /* Reset SERDES registers */
629 ath9k_hw_configpcipowersave(ah, false);
630
631 /*
632 * The basic interface to setting the hardware in a good
633 * state is ``reset''. On return the hardware is known to
634 * be powered up and with interrupts disabled. This must
635 * be followed by initialization of the appropriate bits
636 * and then setup of the interrupt mask.
637 */
638 spin_lock_bh(&sc->sc_pcu_lock);
639
640 atomic_set(&ah->intr_ref_cnt, -1);
641
642 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
643 if (r) {
644 ath_err(common,
645 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
646 r, curchan->center_freq);
647 ah->reset_power_on = false;
648 }
649
650 /* Setup our intr mask. */
651 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
652 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
653 ATH9K_INT_GLOBAL;
654
655 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
656 ah->imask |= ATH9K_INT_RXHP |
657 ATH9K_INT_RXLP |
658 ATH9K_INT_BB_WATCHDOG;
659 else
660 ah->imask |= ATH9K_INT_RX;
661
662 ah->imask |= ATH9K_INT_GTT;
663
664 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
665 ah->imask |= ATH9K_INT_CST;
666
667 ath_mci_enable(sc);
668
669 clear_bit(SC_OP_INVALID, &sc->sc_flags);
670 sc->sc_ah->is_monitoring = false;
671
672 if (!ath_complete_reset(sc, false))
673 ah->reset_power_on = false;
674
675 if (ah->led_pin >= 0) {
676 ath9k_hw_cfg_output(ah, ah->led_pin,
677 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
678 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
679 }
680
681 /*
682 * Reset key cache to sane defaults (all entries cleared) instead of
683 * semi-random values after suspend/resume.
684 */
685 ath9k_cmn_init_crypto(sc->sc_ah);
686
687 spin_unlock_bh(&sc->sc_pcu_lock);
688
689 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
690 common->bus_ops->extn_synch_en(common);
691
692 mutex_unlock(&sc->mutex);
693
694 ath9k_ps_restore(sc);
695
696 return 0;
697 }
698
699 static void ath9k_tx(struct ieee80211_hw *hw,
700 struct ieee80211_tx_control *control,
701 struct sk_buff *skb)
702 {
703 struct ath_softc *sc = hw->priv;
704 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
705 struct ath_tx_control txctl;
706 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
707 unsigned long flags;
708
709 if (sc->ps_enabled) {
710 /*
711 * mac80211 does not set PM field for normal data frames, so we
712 * need to update that based on the current PS mode.
713 */
714 if (ieee80211_is_data(hdr->frame_control) &&
715 !ieee80211_is_nullfunc(hdr->frame_control) &&
716 !ieee80211_has_pm(hdr->frame_control)) {
717 ath_dbg(common, PS,
718 "Add PM=1 for a TX frame while in PS mode\n");
719 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
720 }
721 }
722
723 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
724 /*
725 * We are using PS-Poll and mac80211 can request TX while in
726 * power save mode. Need to wake up hardware for the TX to be
727 * completed and if needed, also for RX of buffered frames.
728 */
729 ath9k_ps_wakeup(sc);
730 spin_lock_irqsave(&sc->sc_pm_lock, flags);
731 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
732 ath9k_hw_setrxabort(sc->sc_ah, 0);
733 if (ieee80211_is_pspoll(hdr->frame_control)) {
734 ath_dbg(common, PS,
735 "Sending PS-Poll to pick a buffered frame\n");
736 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
737 } else {
738 ath_dbg(common, PS, "Wake up to complete TX\n");
739 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
740 }
741 /*
742 * The actual restore operation will happen only after
743 * the ps_flags bit is cleared. We are just dropping
744 * the ps_usecount here.
745 */
746 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
747 ath9k_ps_restore(sc);
748 }
749
750 /*
751 * Cannot tx while the hardware is in full sleep, it first needs a full
752 * chip reset to recover from that
753 */
754 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
755 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
756 goto exit;
757 }
758
759 memset(&txctl, 0, sizeof(struct ath_tx_control));
760 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
761 txctl.sta = control->sta;
762
763 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
764
765 if (ath_tx_start(hw, skb, &txctl) != 0) {
766 ath_dbg(common, XMIT, "TX failed\n");
767 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
768 goto exit;
769 }
770
771 return;
772 exit:
773 ieee80211_free_txskb(hw, skb);
774 }
775
776 static void ath9k_stop(struct ieee80211_hw *hw)
777 {
778 struct ath_softc *sc = hw->priv;
779 struct ath_hw *ah = sc->sc_ah;
780 struct ath_common *common = ath9k_hw_common(ah);
781 bool prev_idle;
782
783 mutex_lock(&sc->mutex);
784
785 ath_cancel_work(sc);
786 del_timer_sync(&sc->rx_poll_timer);
787
788 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
789 ath_dbg(common, ANY, "Device not present\n");
790 mutex_unlock(&sc->mutex);
791 return;
792 }
793
794 /* Ensure HW is awake when we try to shut it down. */
795 ath9k_ps_wakeup(sc);
796
797 spin_lock_bh(&sc->sc_pcu_lock);
798
799 /* prevent tasklets to enable interrupts once we disable them */
800 ah->imask &= ~ATH9K_INT_GLOBAL;
801
802 /* make sure h/w will not generate any interrupt
803 * before setting the invalid flag. */
804 ath9k_hw_disable_interrupts(ah);
805
806 spin_unlock_bh(&sc->sc_pcu_lock);
807
808 /* we can now sync irq and kill any running tasklets, since we already
809 * disabled interrupts and not holding a spin lock */
810 synchronize_irq(sc->irq);
811 tasklet_kill(&sc->intr_tq);
812 tasklet_kill(&sc->bcon_tasklet);
813
814 prev_idle = sc->ps_idle;
815 sc->ps_idle = true;
816
817 spin_lock_bh(&sc->sc_pcu_lock);
818
819 if (ah->led_pin >= 0) {
820 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
821 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
822 }
823
824 ath_prepare_reset(sc, false, true);
825
826 if (sc->rx.frag) {
827 dev_kfree_skb_any(sc->rx.frag);
828 sc->rx.frag = NULL;
829 }
830
831 if (!ah->curchan)
832 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
833
834 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
835 ath9k_hw_phy_disable(ah);
836
837 ath9k_hw_configpcipowersave(ah, true);
838
839 spin_unlock_bh(&sc->sc_pcu_lock);
840
841 ath9k_ps_restore(sc);
842
843 set_bit(SC_OP_INVALID, &sc->sc_flags);
844 sc->ps_idle = prev_idle;
845
846 mutex_unlock(&sc->mutex);
847
848 ath_dbg(common, CONFIG, "Driver halt\n");
849 }
850
851 bool ath9k_uses_beacons(int type)
852 {
853 switch (type) {
854 case NL80211_IFTYPE_AP:
855 case NL80211_IFTYPE_ADHOC:
856 case NL80211_IFTYPE_MESH_POINT:
857 return true;
858 default:
859 return false;
860 }
861 }
862
863 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
864 {
865 struct ath9k_vif_iter_data *iter_data = data;
866 int i;
867
868 if (iter_data->hw_macaddr)
869 for (i = 0; i < ETH_ALEN; i++)
870 iter_data->mask[i] &=
871 ~(iter_data->hw_macaddr[i] ^ mac[i]);
872
873 switch (vif->type) {
874 case NL80211_IFTYPE_AP:
875 iter_data->naps++;
876 break;
877 case NL80211_IFTYPE_STATION:
878 iter_data->nstations++;
879 break;
880 case NL80211_IFTYPE_ADHOC:
881 iter_data->nadhocs++;
882 break;
883 case NL80211_IFTYPE_MESH_POINT:
884 iter_data->nmeshes++;
885 break;
886 case NL80211_IFTYPE_WDS:
887 iter_data->nwds++;
888 break;
889 default:
890 break;
891 }
892 }
893
894 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
895 {
896 struct ath_softc *sc = data;
897 struct ath_vif *avp = (void *)vif->drv_priv;
898
899 if (vif->type != NL80211_IFTYPE_STATION)
900 return;
901
902 if (avp->primary_sta_vif)
903 ath9k_set_assoc_state(sc, vif);
904 }
905
906 /* Called with sc->mutex held. */
907 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
908 struct ieee80211_vif *vif,
909 struct ath9k_vif_iter_data *iter_data)
910 {
911 struct ath_softc *sc = hw->priv;
912 struct ath_hw *ah = sc->sc_ah;
913 struct ath_common *common = ath9k_hw_common(ah);
914
915 /*
916 * Use the hardware MAC address as reference, the hardware uses it
917 * together with the BSSID mask when matching addresses.
918 */
919 memset(iter_data, 0, sizeof(*iter_data));
920 iter_data->hw_macaddr = common->macaddr;
921 memset(&iter_data->mask, 0xff, ETH_ALEN);
922
923 if (vif)
924 ath9k_vif_iter(iter_data, vif->addr, vif);
925
926 /* Get list of all active MAC addresses */
927 ieee80211_iterate_active_interfaces_atomic(
928 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
929 ath9k_vif_iter, iter_data);
930 }
931
932 /* Called with sc->mutex held. */
933 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
934 struct ieee80211_vif *vif)
935 {
936 struct ath_softc *sc = hw->priv;
937 struct ath_hw *ah = sc->sc_ah;
938 struct ath_common *common = ath9k_hw_common(ah);
939 struct ath9k_vif_iter_data iter_data;
940 enum nl80211_iftype old_opmode = ah->opmode;
941
942 ath9k_calculate_iter_data(hw, vif, &iter_data);
943
944 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
945 ath_hw_setbssidmask(common);
946
947 if (iter_data.naps > 0) {
948 ath9k_hw_set_tsfadjust(ah, true);
949 ah->opmode = NL80211_IFTYPE_AP;
950 } else {
951 ath9k_hw_set_tsfadjust(ah, false);
952
953 if (iter_data.nmeshes)
954 ah->opmode = NL80211_IFTYPE_MESH_POINT;
955 else if (iter_data.nwds)
956 ah->opmode = NL80211_IFTYPE_AP;
957 else if (iter_data.nadhocs)
958 ah->opmode = NL80211_IFTYPE_ADHOC;
959 else
960 ah->opmode = NL80211_IFTYPE_STATION;
961 }
962
963 ath9k_hw_setopmode(ah);
964
965 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
966 ah->imask |= ATH9K_INT_TSFOOR;
967 else
968 ah->imask &= ~ATH9K_INT_TSFOOR;
969
970 ath9k_hw_set_interrupts(ah);
971
972 /*
973 * If we are changing the opmode to STATION,
974 * a beacon sync needs to be done.
975 */
976 if (ah->opmode == NL80211_IFTYPE_STATION &&
977 old_opmode == NL80211_IFTYPE_AP &&
978 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
979 ieee80211_iterate_active_interfaces_atomic(
980 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
981 ath9k_sta_vif_iter, sc);
982 }
983 }
984
985 static int ath9k_add_interface(struct ieee80211_hw *hw,
986 struct ieee80211_vif *vif)
987 {
988 struct ath_softc *sc = hw->priv;
989 struct ath_hw *ah = sc->sc_ah;
990 struct ath_common *common = ath9k_hw_common(ah);
991
992 mutex_lock(&sc->mutex);
993
994 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
995 sc->nvifs++;
996
997 ath9k_ps_wakeup(sc);
998 ath9k_calculate_summary_state(hw, vif);
999 ath9k_ps_restore(sc);
1000
1001 if (ath9k_uses_beacons(vif->type))
1002 ath9k_beacon_assign_slot(sc, vif);
1003
1004 mutex_unlock(&sc->mutex);
1005 return 0;
1006 }
1007
1008 static int ath9k_change_interface(struct ieee80211_hw *hw,
1009 struct ieee80211_vif *vif,
1010 enum nl80211_iftype new_type,
1011 bool p2p)
1012 {
1013 struct ath_softc *sc = hw->priv;
1014 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1015
1016 ath_dbg(common, CONFIG, "Change Interface\n");
1017 mutex_lock(&sc->mutex);
1018
1019 if (ath9k_uses_beacons(vif->type))
1020 ath9k_beacon_remove_slot(sc, vif);
1021
1022 vif->type = new_type;
1023 vif->p2p = p2p;
1024
1025 ath9k_ps_wakeup(sc);
1026 ath9k_calculate_summary_state(hw, vif);
1027 ath9k_ps_restore(sc);
1028
1029 if (ath9k_uses_beacons(vif->type))
1030 ath9k_beacon_assign_slot(sc, vif);
1031
1032 mutex_unlock(&sc->mutex);
1033 return 0;
1034 }
1035
1036 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1037 struct ieee80211_vif *vif)
1038 {
1039 struct ath_softc *sc = hw->priv;
1040 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1041
1042 ath_dbg(common, CONFIG, "Detach Interface\n");
1043
1044 mutex_lock(&sc->mutex);
1045
1046 sc->nvifs--;
1047
1048 if (ath9k_uses_beacons(vif->type))
1049 ath9k_beacon_remove_slot(sc, vif);
1050
1051 ath9k_ps_wakeup(sc);
1052 ath9k_calculate_summary_state(hw, NULL);
1053 ath9k_ps_restore(sc);
1054
1055 mutex_unlock(&sc->mutex);
1056 }
1057
1058 static void ath9k_enable_ps(struct ath_softc *sc)
1059 {
1060 struct ath_hw *ah = sc->sc_ah;
1061 struct ath_common *common = ath9k_hw_common(ah);
1062
1063 sc->ps_enabled = true;
1064 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1065 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1066 ah->imask |= ATH9K_INT_TIM_TIMER;
1067 ath9k_hw_set_interrupts(ah);
1068 }
1069 ath9k_hw_setrxabort(ah, 1);
1070 }
1071 ath_dbg(common, PS, "PowerSave enabled\n");
1072 }
1073
1074 static void ath9k_disable_ps(struct ath_softc *sc)
1075 {
1076 struct ath_hw *ah = sc->sc_ah;
1077 struct ath_common *common = ath9k_hw_common(ah);
1078
1079 sc->ps_enabled = false;
1080 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1081 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1082 ath9k_hw_setrxabort(ah, 0);
1083 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1084 PS_WAIT_FOR_CAB |
1085 PS_WAIT_FOR_PSPOLL_DATA |
1086 PS_WAIT_FOR_TX_ACK);
1087 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1088 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1089 ath9k_hw_set_interrupts(ah);
1090 }
1091 }
1092 ath_dbg(common, PS, "PowerSave disabled\n");
1093 }
1094
1095 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1096 {
1097 struct ath_softc *sc = hw->priv;
1098 struct ath_hw *ah = sc->sc_ah;
1099 struct ath_common *common = ath9k_hw_common(ah);
1100 struct ieee80211_conf *conf = &hw->conf;
1101 bool reset_channel = false;
1102
1103 ath9k_ps_wakeup(sc);
1104 mutex_lock(&sc->mutex);
1105
1106 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1107 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1108 if (sc->ps_idle) {
1109 ath_cancel_work(sc);
1110 ath9k_stop_btcoex(sc);
1111 } else {
1112 ath9k_start_btcoex(sc);
1113 /*
1114 * The chip needs a reset to properly wake up from
1115 * full sleep
1116 */
1117 reset_channel = ah->chip_fullsleep;
1118 }
1119 }
1120
1121 /*
1122 * We just prepare to enable PS. We have to wait until our AP has
1123 * ACK'd our null data frame to disable RX otherwise we'll ignore
1124 * those ACKs and end up retransmitting the same null data frames.
1125 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1126 */
1127 if (changed & IEEE80211_CONF_CHANGE_PS) {
1128 unsigned long flags;
1129 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1130 if (conf->flags & IEEE80211_CONF_PS)
1131 ath9k_enable_ps(sc);
1132 else
1133 ath9k_disable_ps(sc);
1134 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1135 }
1136
1137 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1138 if (conf->flags & IEEE80211_CONF_MONITOR) {
1139 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1140 sc->sc_ah->is_monitoring = true;
1141 } else {
1142 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1143 sc->sc_ah->is_monitoring = false;
1144 }
1145 }
1146
1147 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
1148 struct ieee80211_channel *curchan = hw->conf.channel;
1149 int pos = curchan->hw_value;
1150 int old_pos = -1;
1151 unsigned long flags;
1152
1153 if (ah->curchan)
1154 old_pos = ah->curchan - &ah->channels[0];
1155
1156 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
1157 curchan->center_freq, conf->channel_type);
1158
1159 /* update survey stats for the old channel before switching */
1160 spin_lock_irqsave(&common->cc_lock, flags);
1161 ath_update_survey_stats(sc);
1162 spin_unlock_irqrestore(&common->cc_lock, flags);
1163
1164 /*
1165 * Preserve the current channel values, before updating
1166 * the same channel
1167 */
1168 if (ah->curchan && (old_pos == pos))
1169 ath9k_hw_getnf(ah, ah->curchan);
1170
1171 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1172 curchan, conf->channel_type);
1173
1174 /*
1175 * If the operating channel changes, change the survey in-use flags
1176 * along with it.
1177 * Reset the survey data for the new channel, unless we're switching
1178 * back to the operating channel from an off-channel operation.
1179 */
1180 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1181 sc->cur_survey != &sc->survey[pos]) {
1182
1183 if (sc->cur_survey)
1184 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1185
1186 sc->cur_survey = &sc->survey[pos];
1187
1188 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1189 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1190 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1191 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1192 }
1193
1194 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1195 ath_err(common, "Unable to set channel\n");
1196 mutex_unlock(&sc->mutex);
1197 ath9k_ps_restore(sc);
1198 return -EINVAL;
1199 }
1200
1201 /*
1202 * The most recent snapshot of channel->noisefloor for the old
1203 * channel is only available after the hardware reset. Copy it to
1204 * the survey stats now.
1205 */
1206 if (old_pos >= 0)
1207 ath_update_survey_nf(sc, old_pos);
1208 }
1209
1210 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1211 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1212 sc->config.txpowlimit = 2 * conf->power_level;
1213 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1214 sc->config.txpowlimit, &sc->curtxpow);
1215 }
1216
1217 mutex_unlock(&sc->mutex);
1218 ath9k_ps_restore(sc);
1219
1220 return 0;
1221 }
1222
1223 #define SUPPORTED_FILTERS \
1224 (FIF_PROMISC_IN_BSS | \
1225 FIF_ALLMULTI | \
1226 FIF_CONTROL | \
1227 FIF_PSPOLL | \
1228 FIF_OTHER_BSS | \
1229 FIF_BCN_PRBRESP_PROMISC | \
1230 FIF_PROBE_REQ | \
1231 FIF_FCSFAIL)
1232
1233 /* FIXME: sc->sc_full_reset ? */
1234 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1235 unsigned int changed_flags,
1236 unsigned int *total_flags,
1237 u64 multicast)
1238 {
1239 struct ath_softc *sc = hw->priv;
1240 u32 rfilt;
1241
1242 changed_flags &= SUPPORTED_FILTERS;
1243 *total_flags &= SUPPORTED_FILTERS;
1244
1245 sc->rx.rxfilter = *total_flags;
1246 ath9k_ps_wakeup(sc);
1247 rfilt = ath_calcrxfilter(sc);
1248 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1249 ath9k_ps_restore(sc);
1250
1251 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1252 rfilt);
1253 }
1254
1255 static int ath9k_sta_add(struct ieee80211_hw *hw,
1256 struct ieee80211_vif *vif,
1257 struct ieee80211_sta *sta)
1258 {
1259 struct ath_softc *sc = hw->priv;
1260 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1261 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1262 struct ieee80211_key_conf ps_key = { };
1263
1264 ath_node_attach(sc, sta, vif);
1265
1266 if (vif->type != NL80211_IFTYPE_AP &&
1267 vif->type != NL80211_IFTYPE_AP_VLAN)
1268 return 0;
1269
1270 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
1271
1272 return 0;
1273 }
1274
1275 static void ath9k_del_ps_key(struct ath_softc *sc,
1276 struct ieee80211_vif *vif,
1277 struct ieee80211_sta *sta)
1278 {
1279 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1280 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1281 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1282
1283 if (!an->ps_key)
1284 return;
1285
1286 ath_key_delete(common, &ps_key);
1287 }
1288
1289 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1290 struct ieee80211_vif *vif,
1291 struct ieee80211_sta *sta)
1292 {
1293 struct ath_softc *sc = hw->priv;
1294
1295 ath9k_del_ps_key(sc, vif, sta);
1296 ath_node_detach(sc, sta);
1297
1298 return 0;
1299 }
1300
1301 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1302 struct ieee80211_vif *vif,
1303 enum sta_notify_cmd cmd,
1304 struct ieee80211_sta *sta)
1305 {
1306 struct ath_softc *sc = hw->priv;
1307 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1308
1309 if (!sta->ht_cap.ht_supported)
1310 return;
1311
1312 switch (cmd) {
1313 case STA_NOTIFY_SLEEP:
1314 an->sleeping = true;
1315 ath_tx_aggr_sleep(sta, sc, an);
1316 break;
1317 case STA_NOTIFY_AWAKE:
1318 an->sleeping = false;
1319 ath_tx_aggr_wakeup(sc, an);
1320 break;
1321 }
1322 }
1323
1324 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1325 struct ieee80211_vif *vif, u16 queue,
1326 const struct ieee80211_tx_queue_params *params)
1327 {
1328 struct ath_softc *sc = hw->priv;
1329 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1330 struct ath_txq *txq;
1331 struct ath9k_tx_queue_info qi;
1332 int ret = 0;
1333
1334 if (queue >= WME_NUM_AC)
1335 return 0;
1336
1337 txq = sc->tx.txq_map[queue];
1338
1339 ath9k_ps_wakeup(sc);
1340 mutex_lock(&sc->mutex);
1341
1342 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1343
1344 qi.tqi_aifs = params->aifs;
1345 qi.tqi_cwmin = params->cw_min;
1346 qi.tqi_cwmax = params->cw_max;
1347 qi.tqi_burstTime = params->txop * 32;
1348
1349 ath_dbg(common, CONFIG,
1350 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1351 queue, txq->axq_qnum, params->aifs, params->cw_min,
1352 params->cw_max, params->txop);
1353
1354 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1355 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1356 if (ret)
1357 ath_err(common, "TXQ Update failed\n");
1358
1359 mutex_unlock(&sc->mutex);
1360 ath9k_ps_restore(sc);
1361
1362 return ret;
1363 }
1364
1365 static int ath9k_set_key(struct ieee80211_hw *hw,
1366 enum set_key_cmd cmd,
1367 struct ieee80211_vif *vif,
1368 struct ieee80211_sta *sta,
1369 struct ieee80211_key_conf *key)
1370 {
1371 struct ath_softc *sc = hw->priv;
1372 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1373 int ret = 0;
1374
1375 if (ath9k_modparam_nohwcrypt)
1376 return -ENOSPC;
1377
1378 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1379 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1380 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1381 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1382 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1383 /*
1384 * For now, disable hw crypto for the RSN IBSS group keys. This
1385 * could be optimized in the future to use a modified key cache
1386 * design to support per-STA RX GTK, but until that gets
1387 * implemented, use of software crypto for group addressed
1388 * frames is a acceptable to allow RSN IBSS to be used.
1389 */
1390 return -EOPNOTSUPP;
1391 }
1392
1393 mutex_lock(&sc->mutex);
1394 ath9k_ps_wakeup(sc);
1395 ath_dbg(common, CONFIG, "Set HW Key\n");
1396
1397 switch (cmd) {
1398 case SET_KEY:
1399 if (sta)
1400 ath9k_del_ps_key(sc, vif, sta);
1401
1402 ret = ath_key_config(common, vif, sta, key);
1403 if (ret >= 0) {
1404 key->hw_key_idx = ret;
1405 /* push IV and Michael MIC generation to stack */
1406 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1407 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1408 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1409 if (sc->sc_ah->sw_mgmt_crypto &&
1410 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1411 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1412 ret = 0;
1413 }
1414 break;
1415 case DISABLE_KEY:
1416 ath_key_delete(common, key);
1417 break;
1418 default:
1419 ret = -EINVAL;
1420 }
1421
1422 ath9k_ps_restore(sc);
1423 mutex_unlock(&sc->mutex);
1424
1425 return ret;
1426 }
1427
1428 static void ath9k_set_assoc_state(struct ath_softc *sc,
1429 struct ieee80211_vif *vif)
1430 {
1431 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1432 struct ath_vif *avp = (void *)vif->drv_priv;
1433 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1434 unsigned long flags;
1435
1436 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1437 avp->primary_sta_vif = true;
1438
1439 /*
1440 * Set the AID, BSSID and do beacon-sync only when
1441 * the HW opmode is STATION.
1442 *
1443 * But the primary bit is set above in any case.
1444 */
1445 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1446 return;
1447
1448 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1449 common->curaid = bss_conf->aid;
1450 ath9k_hw_write_associd(sc->sc_ah);
1451
1452 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1453 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1454
1455 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1456 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1457 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1458
1459 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1460 ath9k_mci_update_wlan_channels(sc, false);
1461
1462 ath_dbg(common, CONFIG,
1463 "Primary Station interface: %pM, BSSID: %pM\n",
1464 vif->addr, common->curbssid);
1465 }
1466
1467 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1468 {
1469 struct ath_softc *sc = data;
1470 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1471
1472 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
1473 return;
1474
1475 if (bss_conf->assoc)
1476 ath9k_set_assoc_state(sc, vif);
1477 }
1478
1479 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1480 struct ieee80211_vif *vif,
1481 struct ieee80211_bss_conf *bss_conf,
1482 u32 changed)
1483 {
1484 #define CHECK_ANI \
1485 (BSS_CHANGED_ASSOC | \
1486 BSS_CHANGED_IBSS | \
1487 BSS_CHANGED_BEACON_ENABLED)
1488
1489 struct ath_softc *sc = hw->priv;
1490 struct ath_hw *ah = sc->sc_ah;
1491 struct ath_common *common = ath9k_hw_common(ah);
1492 struct ath_vif *avp = (void *)vif->drv_priv;
1493 int slottime;
1494
1495 ath9k_ps_wakeup(sc);
1496 mutex_lock(&sc->mutex);
1497
1498 if (changed & BSS_CHANGED_ASSOC) {
1499 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1500 bss_conf->bssid, bss_conf->assoc);
1501
1502 if (avp->primary_sta_vif && !bss_conf->assoc) {
1503 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1504 avp->primary_sta_vif = false;
1505
1506 if (ah->opmode == NL80211_IFTYPE_STATION)
1507 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1508 }
1509
1510 ieee80211_iterate_active_interfaces_atomic(
1511 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1512 ath9k_bss_assoc_iter, sc);
1513
1514 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1515 ah->opmode == NL80211_IFTYPE_STATION) {
1516 memset(common->curbssid, 0, ETH_ALEN);
1517 common->curaid = 0;
1518 ath9k_hw_write_associd(sc->sc_ah);
1519 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1520 ath9k_mci_update_wlan_channels(sc, true);
1521 }
1522 }
1523
1524 if (changed & BSS_CHANGED_IBSS) {
1525 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1526 common->curaid = bss_conf->aid;
1527 ath9k_hw_write_associd(sc->sc_ah);
1528 }
1529
1530 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1531 (changed & BSS_CHANGED_BEACON_INT)) {
1532 if (ah->opmode == NL80211_IFTYPE_AP &&
1533 bss_conf->enable_beacon)
1534 ath9k_set_tsfadjust(sc, vif);
1535 if (ath9k_allow_beacon_config(sc, vif))
1536 ath9k_beacon_config(sc, vif, changed);
1537 }
1538
1539 if (changed & BSS_CHANGED_ERP_SLOT) {
1540 if (bss_conf->use_short_slot)
1541 slottime = 9;
1542 else
1543 slottime = 20;
1544 if (vif->type == NL80211_IFTYPE_AP) {
1545 /*
1546 * Defer update, so that connected stations can adjust
1547 * their settings at the same time.
1548 * See beacon.c for more details
1549 */
1550 sc->beacon.slottime = slottime;
1551 sc->beacon.updateslot = UPDATE;
1552 } else {
1553 ah->slottime = slottime;
1554 ath9k_hw_init_global_settings(ah);
1555 }
1556 }
1557
1558 if (changed & CHECK_ANI)
1559 ath_check_ani(sc);
1560
1561 mutex_unlock(&sc->mutex);
1562 ath9k_ps_restore(sc);
1563
1564 #undef CHECK_ANI
1565 }
1566
1567 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1568 {
1569 struct ath_softc *sc = hw->priv;
1570 u64 tsf;
1571
1572 mutex_lock(&sc->mutex);
1573 ath9k_ps_wakeup(sc);
1574 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1575 ath9k_ps_restore(sc);
1576 mutex_unlock(&sc->mutex);
1577
1578 return tsf;
1579 }
1580
1581 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1582 struct ieee80211_vif *vif,
1583 u64 tsf)
1584 {
1585 struct ath_softc *sc = hw->priv;
1586
1587 mutex_lock(&sc->mutex);
1588 ath9k_ps_wakeup(sc);
1589 ath9k_hw_settsf64(sc->sc_ah, tsf);
1590 ath9k_ps_restore(sc);
1591 mutex_unlock(&sc->mutex);
1592 }
1593
1594 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1595 {
1596 struct ath_softc *sc = hw->priv;
1597
1598 mutex_lock(&sc->mutex);
1599
1600 ath9k_ps_wakeup(sc);
1601 ath9k_hw_reset_tsf(sc->sc_ah);
1602 ath9k_ps_restore(sc);
1603
1604 mutex_unlock(&sc->mutex);
1605 }
1606
1607 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1608 struct ieee80211_vif *vif,
1609 enum ieee80211_ampdu_mlme_action action,
1610 struct ieee80211_sta *sta,
1611 u16 tid, u16 *ssn, u8 buf_size)
1612 {
1613 struct ath_softc *sc = hw->priv;
1614 int ret = 0;
1615
1616 local_bh_disable();
1617
1618 switch (action) {
1619 case IEEE80211_AMPDU_RX_START:
1620 break;
1621 case IEEE80211_AMPDU_RX_STOP:
1622 break;
1623 case IEEE80211_AMPDU_TX_START:
1624 ath9k_ps_wakeup(sc);
1625 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1626 if (!ret)
1627 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1628 ath9k_ps_restore(sc);
1629 break;
1630 case IEEE80211_AMPDU_TX_STOP:
1631 ath9k_ps_wakeup(sc);
1632 ath_tx_aggr_stop(sc, sta, tid);
1633 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1634 ath9k_ps_restore(sc);
1635 break;
1636 case IEEE80211_AMPDU_TX_OPERATIONAL:
1637 ath9k_ps_wakeup(sc);
1638 ath_tx_aggr_resume(sc, sta, tid);
1639 ath9k_ps_restore(sc);
1640 break;
1641 default:
1642 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1643 }
1644
1645 local_bh_enable();
1646
1647 return ret;
1648 }
1649
1650 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1651 struct survey_info *survey)
1652 {
1653 struct ath_softc *sc = hw->priv;
1654 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1655 struct ieee80211_supported_band *sband;
1656 struct ieee80211_channel *chan;
1657 unsigned long flags;
1658 int pos;
1659
1660 spin_lock_irqsave(&common->cc_lock, flags);
1661 if (idx == 0)
1662 ath_update_survey_stats(sc);
1663
1664 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1665 if (sband && idx >= sband->n_channels) {
1666 idx -= sband->n_channels;
1667 sband = NULL;
1668 }
1669
1670 if (!sband)
1671 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1672
1673 if (!sband || idx >= sband->n_channels) {
1674 spin_unlock_irqrestore(&common->cc_lock, flags);
1675 return -ENOENT;
1676 }
1677
1678 chan = &sband->channels[idx];
1679 pos = chan->hw_value;
1680 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1681 survey->channel = chan;
1682 spin_unlock_irqrestore(&common->cc_lock, flags);
1683
1684 return 0;
1685 }
1686
1687 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1688 {
1689 struct ath_softc *sc = hw->priv;
1690 struct ath_hw *ah = sc->sc_ah;
1691
1692 mutex_lock(&sc->mutex);
1693 ah->coverage_class = coverage_class;
1694
1695 ath9k_ps_wakeup(sc);
1696 ath9k_hw_init_global_settings(ah);
1697 ath9k_ps_restore(sc);
1698
1699 mutex_unlock(&sc->mutex);
1700 }
1701
1702 static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1703 {
1704 struct ath_softc *sc = hw->priv;
1705 struct ath_hw *ah = sc->sc_ah;
1706 struct ath_common *common = ath9k_hw_common(ah);
1707 int timeout = 200; /* ms */
1708 int i, j;
1709 bool drain_txq;
1710
1711 mutex_lock(&sc->mutex);
1712 cancel_delayed_work_sync(&sc->tx_complete_work);
1713
1714 if (ah->ah_flags & AH_UNPLUGGED) {
1715 ath_dbg(common, ANY, "Device has been unplugged!\n");
1716 mutex_unlock(&sc->mutex);
1717 return;
1718 }
1719
1720 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
1721 ath_dbg(common, ANY, "Device not present\n");
1722 mutex_unlock(&sc->mutex);
1723 return;
1724 }
1725
1726 for (j = 0; j < timeout; j++) {
1727 bool npend = false;
1728
1729 if (j)
1730 usleep_range(1000, 2000);
1731
1732 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1733 if (!ATH_TXQ_SETUP(sc, i))
1734 continue;
1735
1736 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1737
1738 if (npend)
1739 break;
1740 }
1741
1742 if (!npend)
1743 break;
1744 }
1745
1746 if (drop) {
1747 ath9k_ps_wakeup(sc);
1748 spin_lock_bh(&sc->sc_pcu_lock);
1749 drain_txq = ath_drain_all_txq(sc, false);
1750 spin_unlock_bh(&sc->sc_pcu_lock);
1751
1752 if (!drain_txq)
1753 ath_reset(sc, false);
1754
1755 ath9k_ps_restore(sc);
1756 ieee80211_wake_queues(hw);
1757 }
1758
1759 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1760 mutex_unlock(&sc->mutex);
1761 }
1762
1763 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1764 {
1765 struct ath_softc *sc = hw->priv;
1766 int i;
1767
1768 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1769 if (!ATH_TXQ_SETUP(sc, i))
1770 continue;
1771
1772 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1773 return true;
1774 }
1775 return false;
1776 }
1777
1778 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
1779 {
1780 struct ath_softc *sc = hw->priv;
1781 struct ath_hw *ah = sc->sc_ah;
1782 struct ieee80211_vif *vif;
1783 struct ath_vif *avp;
1784 struct ath_buf *bf;
1785 struct ath_tx_status ts;
1786 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1787 int status;
1788
1789 vif = sc->beacon.bslot[0];
1790 if (!vif)
1791 return 0;
1792
1793 if (!vif->bss_conf.enable_beacon)
1794 return 0;
1795
1796 avp = (void *)vif->drv_priv;
1797
1798 if (!sc->beacon.tx_processed && !edma) {
1799 tasklet_disable(&sc->bcon_tasklet);
1800
1801 bf = avp->av_bcbuf;
1802 if (!bf || !bf->bf_mpdu)
1803 goto skip;
1804
1805 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1806 if (status == -EINPROGRESS)
1807 goto skip;
1808
1809 sc->beacon.tx_processed = true;
1810 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1811
1812 skip:
1813 tasklet_enable(&sc->bcon_tasklet);
1814 }
1815
1816 return sc->beacon.tx_last;
1817 }
1818
1819 static int ath9k_get_stats(struct ieee80211_hw *hw,
1820 struct ieee80211_low_level_stats *stats)
1821 {
1822 struct ath_softc *sc = hw->priv;
1823 struct ath_hw *ah = sc->sc_ah;
1824 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1825
1826 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1827 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1828 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1829 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1830 return 0;
1831 }
1832
1833 static u32 fill_chainmask(u32 cap, u32 new)
1834 {
1835 u32 filled = 0;
1836 int i;
1837
1838 for (i = 0; cap && new; i++, cap >>= 1) {
1839 if (!(cap & BIT(0)))
1840 continue;
1841
1842 if (new & BIT(0))
1843 filled |= BIT(i);
1844
1845 new >>= 1;
1846 }
1847
1848 return filled;
1849 }
1850
1851 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
1852 {
1853 switch (val & 0x7) {
1854 case 0x1:
1855 case 0x3:
1856 case 0x7:
1857 return true;
1858 case 0x2:
1859 return (ah->caps.rx_chainmask == 1);
1860 default:
1861 return false;
1862 }
1863 }
1864
1865 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1866 {
1867 struct ath_softc *sc = hw->priv;
1868 struct ath_hw *ah = sc->sc_ah;
1869
1870 if (ah->caps.rx_chainmask != 1)
1871 rx_ant |= tx_ant;
1872
1873 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
1874 return -EINVAL;
1875
1876 sc->ant_rx = rx_ant;
1877 sc->ant_tx = tx_ant;
1878
1879 if (ah->caps.rx_chainmask == 1)
1880 return 0;
1881
1882 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1883 if (AR_SREV_9100(ah))
1884 ah->rxchainmask = 0x7;
1885 else
1886 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1887
1888 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1889 ath9k_reload_chainmask_settings(sc);
1890
1891 return 0;
1892 }
1893
1894 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1895 {
1896 struct ath_softc *sc = hw->priv;
1897
1898 *tx_ant = sc->ant_tx;
1899 *rx_ant = sc->ant_rx;
1900 return 0;
1901 }
1902
1903 #ifdef CONFIG_ATH9K_DEBUGFS
1904
1905 /* Ethtool support for get-stats */
1906
1907 #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
1908 static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
1909 "tx_pkts_nic",
1910 "tx_bytes_nic",
1911 "rx_pkts_nic",
1912 "rx_bytes_nic",
1913 AMKSTR(d_tx_pkts),
1914 AMKSTR(d_tx_bytes),
1915 AMKSTR(d_tx_mpdus_queued),
1916 AMKSTR(d_tx_mpdus_completed),
1917 AMKSTR(d_tx_mpdu_xretries),
1918 AMKSTR(d_tx_aggregates),
1919 AMKSTR(d_tx_ampdus_queued_hw),
1920 AMKSTR(d_tx_ampdus_queued_sw),
1921 AMKSTR(d_tx_ampdus_completed),
1922 AMKSTR(d_tx_ampdu_retries),
1923 AMKSTR(d_tx_ampdu_xretries),
1924 AMKSTR(d_tx_fifo_underrun),
1925 AMKSTR(d_tx_op_exceeded),
1926 AMKSTR(d_tx_timer_expiry),
1927 AMKSTR(d_tx_desc_cfg_err),
1928 AMKSTR(d_tx_data_underrun),
1929 AMKSTR(d_tx_delim_underrun),
1930
1931 "d_rx_decrypt_crc_err",
1932 "d_rx_phy_err",
1933 "d_rx_mic_err",
1934 "d_rx_pre_delim_crc_err",
1935 "d_rx_post_delim_crc_err",
1936 "d_rx_decrypt_busy_err",
1937
1938 "d_rx_phyerr_radar",
1939 "d_rx_phyerr_ofdm_timing",
1940 "d_rx_phyerr_cck_timing",
1941
1942 };
1943 #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
1944
1945 static void ath9k_get_et_strings(struct ieee80211_hw *hw,
1946 struct ieee80211_vif *vif,
1947 u32 sset, u8 *data)
1948 {
1949 if (sset == ETH_SS_STATS)
1950 memcpy(data, *ath9k_gstrings_stats,
1951 sizeof(ath9k_gstrings_stats));
1952 }
1953
1954 static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
1955 struct ieee80211_vif *vif, int sset)
1956 {
1957 if (sset == ETH_SS_STATS)
1958 return ATH9K_SSTATS_LEN;
1959 return 0;
1960 }
1961
1962 #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
1963 #define AWDATA(elem) \
1964 do { \
1965 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
1966 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
1967 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
1968 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
1969 } while (0)
1970
1971 #define AWDATA_RX(elem) \
1972 do { \
1973 data[i++] = sc->debug.stats.rxstats.elem; \
1974 } while (0)
1975
1976 static void ath9k_get_et_stats(struct ieee80211_hw *hw,
1977 struct ieee80211_vif *vif,
1978 struct ethtool_stats *stats, u64 *data)
1979 {
1980 struct ath_softc *sc = hw->priv;
1981 int i = 0;
1982
1983 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
1984 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
1985 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
1986 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
1987 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
1988 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
1989 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
1990 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
1991 AWDATA_RX(rx_pkts_all);
1992 AWDATA_RX(rx_bytes_all);
1993
1994 AWDATA(tx_pkts_all);
1995 AWDATA(tx_bytes_all);
1996 AWDATA(queued);
1997 AWDATA(completed);
1998 AWDATA(xretries);
1999 AWDATA(a_aggr);
2000 AWDATA(a_queued_hw);
2001 AWDATA(a_queued_sw);
2002 AWDATA(a_completed);
2003 AWDATA(a_retries);
2004 AWDATA(a_xretries);
2005 AWDATA(fifo_underrun);
2006 AWDATA(xtxop);
2007 AWDATA(timer_exp);
2008 AWDATA(desc_cfg_err);
2009 AWDATA(data_underrun);
2010 AWDATA(delim_underrun);
2011
2012 AWDATA_RX(decrypt_crc_err);
2013 AWDATA_RX(phy_err);
2014 AWDATA_RX(mic_err);
2015 AWDATA_RX(pre_delim_crc_err);
2016 AWDATA_RX(post_delim_crc_err);
2017 AWDATA_RX(decrypt_busy_err);
2018
2019 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
2020 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
2021 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
2022
2023 WARN_ON(i != ATH9K_SSTATS_LEN);
2024 }
2025
2026 /* End of ethtool get-stats functions */
2027
2028 #endif
2029
2030
2031 #ifdef CONFIG_PM_SLEEP
2032
2033 static void ath9k_wow_map_triggers(struct ath_softc *sc,
2034 struct cfg80211_wowlan *wowlan,
2035 u32 *wow_triggers)
2036 {
2037 if (wowlan->disconnect)
2038 *wow_triggers |= AH_WOW_LINK_CHANGE |
2039 AH_WOW_BEACON_MISS;
2040 if (wowlan->magic_pkt)
2041 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
2042
2043 if (wowlan->n_patterns)
2044 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
2045
2046 sc->wow_enabled = *wow_triggers;
2047
2048 }
2049
2050 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
2051 {
2052 struct ath_hw *ah = sc->sc_ah;
2053 struct ath_common *common = ath9k_hw_common(ah);
2054 struct ath9k_hw_capabilities *pcaps = &ah->caps;
2055 int pattern_count = 0;
2056 int i, byte_cnt;
2057 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
2058 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
2059
2060 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2061 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2062
2063 /*
2064 * Create Dissassociate / Deauthenticate packet filter
2065 *
2066 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
2067 * +--------------+----------+---------+--------+--------+----
2068 * + Frame Control+ Duration + DA + SA + BSSID +
2069 * +--------------+----------+---------+--------+--------+----
2070 *
2071 * The above is the management frame format for disassociate/
2072 * deauthenticate pattern, from this we need to match the first byte
2073 * of 'Frame Control' and DA, SA, and BSSID fields
2074 * (skipping 2nd byte of FC and Duration feild.
2075 *
2076 * Disassociate pattern
2077 * --------------------
2078 * Frame control = 00 00 1010
2079 * DA, SA, BSSID = x:x:x:x:x:x
2080 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2081 * | x:x:x:x:x:x -- 22 bytes
2082 *
2083 * Deauthenticate pattern
2084 * ----------------------
2085 * Frame control = 00 00 1100
2086 * DA, SA, BSSID = x:x:x:x:x:x
2087 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2088 * | x:x:x:x:x:x -- 22 bytes
2089 */
2090
2091 /* Create Disassociate Pattern first */
2092
2093 byte_cnt = 0;
2094
2095 /* Fill out the mask with all FF's */
2096
2097 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2098 dis_deauth_mask[i] = 0xff;
2099
2100 /* copy the first byte of frame control field */
2101 dis_deauth_pattern[byte_cnt] = 0xa0;
2102 byte_cnt++;
2103
2104 /* skip 2nd byte of frame control and Duration field */
2105 byte_cnt += 3;
2106
2107 /*
2108 * need not match the destination mac address, it can be a broadcast
2109 * mac address or an unicast to this station
2110 */
2111 byte_cnt += 6;
2112
2113 /* copy the source mac address */
2114 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2115
2116 byte_cnt += 6;
2117
2118 /* copy the bssid, its same as the source mac address */
2119
2120 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2121
2122 /* Create Disassociate pattern mask */
2123
2124 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
2125
2126 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
2127 /*
2128 * for AR9280, because of hardware limitation, the
2129 * first 4 bytes have to be matched for all patterns.
2130 * the mask for disassociation and de-auth pattern
2131 * matching need to enable the first 4 bytes.
2132 * also the duration field needs to be filled.
2133 */
2134 dis_deauth_mask[0] = 0xf0;
2135
2136 /*
2137 * fill in duration field
2138 FIXME: what is the exact value ?
2139 */
2140 dis_deauth_pattern[2] = 0xff;
2141 dis_deauth_pattern[3] = 0xff;
2142 } else {
2143 dis_deauth_mask[0] = 0xfe;
2144 }
2145
2146 dis_deauth_mask[1] = 0x03;
2147 dis_deauth_mask[2] = 0xc0;
2148 } else {
2149 dis_deauth_mask[0] = 0xef;
2150 dis_deauth_mask[1] = 0x3f;
2151 dis_deauth_mask[2] = 0x00;
2152 dis_deauth_mask[3] = 0xfc;
2153 }
2154
2155 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2156
2157 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2158 pattern_count, byte_cnt);
2159
2160 pattern_count++;
2161 /*
2162 * for de-authenticate pattern, only the first byte of the frame
2163 * control field gets changed from 0xA0 to 0xC0
2164 */
2165 dis_deauth_pattern[0] = 0xC0;
2166
2167 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2168 pattern_count, byte_cnt);
2169
2170 }
2171
2172 static void ath9k_wow_add_pattern(struct ath_softc *sc,
2173 struct cfg80211_wowlan *wowlan)
2174 {
2175 struct ath_hw *ah = sc->sc_ah;
2176 struct ath9k_wow_pattern *wow_pattern = NULL;
2177 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2178 int mask_len;
2179 s8 i = 0;
2180
2181 if (!wowlan->n_patterns)
2182 return;
2183
2184 /*
2185 * Add the new user configured patterns
2186 */
2187 for (i = 0; i < wowlan->n_patterns; i++) {
2188
2189 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2190
2191 if (!wow_pattern)
2192 return;
2193
2194 /*
2195 * TODO: convert the generic user space pattern to
2196 * appropriate chip specific/802.11 pattern.
2197 */
2198
2199 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2200 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2201 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2202 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2203 patterns[i].pattern_len);
2204 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2205 wow_pattern->pattern_len = patterns[i].pattern_len;
2206
2207 /*
2208 * just need to take care of deauth and disssoc pattern,
2209 * make sure we don't overwrite them.
2210 */
2211
2212 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2213 wow_pattern->mask_bytes,
2214 i + 2,
2215 wow_pattern->pattern_len);
2216 kfree(wow_pattern);
2217
2218 }
2219
2220 }
2221
2222 static int ath9k_suspend(struct ieee80211_hw *hw,
2223 struct cfg80211_wowlan *wowlan)
2224 {
2225 struct ath_softc *sc = hw->priv;
2226 struct ath_hw *ah = sc->sc_ah;
2227 struct ath_common *common = ath9k_hw_common(ah);
2228 u32 wow_triggers_enabled = 0;
2229 int ret = 0;
2230
2231 mutex_lock(&sc->mutex);
2232
2233 ath_cancel_work(sc);
2234 ath_stop_ani(sc);
2235 del_timer_sync(&sc->rx_poll_timer);
2236
2237 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2238 ath_dbg(common, ANY, "Device not present\n");
2239 ret = -EINVAL;
2240 goto fail_wow;
2241 }
2242
2243 if (WARN_ON(!wowlan)) {
2244 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2245 ret = -EINVAL;
2246 goto fail_wow;
2247 }
2248
2249 if (!device_can_wakeup(sc->dev)) {
2250 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2251 ret = 1;
2252 goto fail_wow;
2253 }
2254
2255 /*
2256 * none of the sta vifs are associated
2257 * and we are not currently handling multivif
2258 * cases, for instance we have to seperately
2259 * configure 'keep alive frame' for each
2260 * STA.
2261 */
2262
2263 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2264 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2265 ret = 1;
2266 goto fail_wow;
2267 }
2268
2269 if (sc->nvifs > 1) {
2270 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2271 ret = 1;
2272 goto fail_wow;
2273 }
2274
2275 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2276
2277 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2278 wow_triggers_enabled);
2279
2280 ath9k_ps_wakeup(sc);
2281
2282 ath9k_stop_btcoex(sc);
2283
2284 /*
2285 * Enable wake up on recieving disassoc/deauth
2286 * frame by default.
2287 */
2288 ath9k_wow_add_disassoc_deauth_pattern(sc);
2289
2290 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2291 ath9k_wow_add_pattern(sc, wowlan);
2292
2293 spin_lock_bh(&sc->sc_pcu_lock);
2294 /*
2295 * To avoid false wake, we enable beacon miss interrupt only
2296 * when we go to sleep. We save the current interrupt mask
2297 * so we can restore it after the system wakes up
2298 */
2299 sc->wow_intr_before_sleep = ah->imask;
2300 ah->imask &= ~ATH9K_INT_GLOBAL;
2301 ath9k_hw_disable_interrupts(ah);
2302 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2303 ath9k_hw_set_interrupts(ah);
2304 ath9k_hw_enable_interrupts(ah);
2305
2306 spin_unlock_bh(&sc->sc_pcu_lock);
2307
2308 /*
2309 * we can now sync irq and kill any running tasklets, since we already
2310 * disabled interrupts and not holding a spin lock
2311 */
2312 synchronize_irq(sc->irq);
2313 tasklet_kill(&sc->intr_tq);
2314
2315 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2316
2317 ath9k_ps_restore(sc);
2318 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2319 atomic_inc(&sc->wow_sleep_proc_intr);
2320
2321 fail_wow:
2322 mutex_unlock(&sc->mutex);
2323 return ret;
2324 }
2325
2326 static int ath9k_resume(struct ieee80211_hw *hw)
2327 {
2328 struct ath_softc *sc = hw->priv;
2329 struct ath_hw *ah = sc->sc_ah;
2330 struct ath_common *common = ath9k_hw_common(ah);
2331 u32 wow_status;
2332
2333 mutex_lock(&sc->mutex);
2334
2335 ath9k_ps_wakeup(sc);
2336
2337 spin_lock_bh(&sc->sc_pcu_lock);
2338
2339 ath9k_hw_disable_interrupts(ah);
2340 ah->imask = sc->wow_intr_before_sleep;
2341 ath9k_hw_set_interrupts(ah);
2342 ath9k_hw_enable_interrupts(ah);
2343
2344 spin_unlock_bh(&sc->sc_pcu_lock);
2345
2346 wow_status = ath9k_hw_wow_wakeup(ah);
2347
2348 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2349 /*
2350 * some devices may not pick beacon miss
2351 * as the reason they woke up so we add
2352 * that here for that shortcoming.
2353 */
2354 wow_status |= AH_WOW_BEACON_MISS;
2355 atomic_dec(&sc->wow_got_bmiss_intr);
2356 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2357 }
2358
2359 atomic_dec(&sc->wow_sleep_proc_intr);
2360
2361 if (wow_status) {
2362 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2363 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2364 }
2365
2366 ath_restart_work(sc);
2367 ath9k_start_btcoex(sc);
2368
2369 ath9k_ps_restore(sc);
2370 mutex_unlock(&sc->mutex);
2371
2372 return 0;
2373 }
2374
2375 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2376 {
2377 struct ath_softc *sc = hw->priv;
2378
2379 mutex_lock(&sc->mutex);
2380 device_init_wakeup(sc->dev, 1);
2381 device_set_wakeup_enable(sc->dev, enabled);
2382 mutex_unlock(&sc->mutex);
2383 }
2384
2385 #endif
2386
2387 struct ieee80211_ops ath9k_ops = {
2388 .tx = ath9k_tx,
2389 .start = ath9k_start,
2390 .stop = ath9k_stop,
2391 .add_interface = ath9k_add_interface,
2392 .change_interface = ath9k_change_interface,
2393 .remove_interface = ath9k_remove_interface,
2394 .config = ath9k_config,
2395 .configure_filter = ath9k_configure_filter,
2396 .sta_add = ath9k_sta_add,
2397 .sta_remove = ath9k_sta_remove,
2398 .sta_notify = ath9k_sta_notify,
2399 .conf_tx = ath9k_conf_tx,
2400 .bss_info_changed = ath9k_bss_info_changed,
2401 .set_key = ath9k_set_key,
2402 .get_tsf = ath9k_get_tsf,
2403 .set_tsf = ath9k_set_tsf,
2404 .reset_tsf = ath9k_reset_tsf,
2405 .ampdu_action = ath9k_ampdu_action,
2406 .get_survey = ath9k_get_survey,
2407 .rfkill_poll = ath9k_rfkill_poll_state,
2408 .set_coverage_class = ath9k_set_coverage_class,
2409 .flush = ath9k_flush,
2410 .tx_frames_pending = ath9k_tx_frames_pending,
2411 .tx_last_beacon = ath9k_tx_last_beacon,
2412 .get_stats = ath9k_get_stats,
2413 .set_antenna = ath9k_set_antenna,
2414 .get_antenna = ath9k_get_antenna,
2415
2416 #ifdef CONFIG_PM_SLEEP
2417 .suspend = ath9k_suspend,
2418 .resume = ath9k_resume,
2419 .set_wakeup = ath9k_set_wakeup,
2420 #endif
2421
2422 #ifdef CONFIG_ATH9K_DEBUGFS
2423 .get_et_sset_count = ath9k_get_et_sset_count,
2424 .get_et_stats = ath9k_get_et_stats,
2425 .get_et_strings = ath9k_get_et_strings,
2426 #endif
2427 };
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