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ath9k: perform ANI cycle in idle state
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58 }
59
60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61 {
62 bool pending = false;
63
64 spin_lock_bh(&txq->axq_lock);
65
66 if (txq->axq_depth || !list_empty(&txq->axq_acq))
67 pending = true;
68
69 spin_unlock_bh(&txq->axq_lock);
70 return pending;
71 }
72
73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
74 {
75 unsigned long flags;
76 bool ret;
77
78 spin_lock_irqsave(&sc->sc_pm_lock, flags);
79 ret = ath9k_hw_setpower(sc->sc_ah, mode);
80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
81
82 return ret;
83 }
84
85 void ath9k_ps_wakeup(struct ath_softc *sc)
86 {
87 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
88 unsigned long flags;
89 enum ath9k_power_mode power_mode;
90
91 spin_lock_irqsave(&sc->sc_pm_lock, flags);
92 if (++sc->ps_usecount != 1)
93 goto unlock;
94
95 power_mode = sc->sc_ah->power_mode;
96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
97
98 /*
99 * While the hardware is asleep, the cycle counters contain no
100 * useful data. Better clear them now so that they don't mess up
101 * survey data results.
102 */
103 if (power_mode != ATH9K_PM_AWAKE) {
104 spin_lock(&common->cc_lock);
105 ath_hw_cycle_counters_update(common);
106 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
107 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
108 spin_unlock(&common->cc_lock);
109 }
110
111 unlock:
112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
113 }
114
115 void ath9k_ps_restore(struct ath_softc *sc)
116 {
117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
118 enum ath9k_power_mode mode;
119 unsigned long flags;
120 bool reset;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (--sc->ps_usecount != 0)
124 goto unlock;
125
126 if (sc->ps_idle) {
127 ath9k_hw_setrxabort(sc->sc_ah, 1);
128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
129 mode = ATH9K_PM_FULL_SLEEP;
130 } else if (sc->ps_enabled &&
131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
132 PS_WAIT_FOR_CAB |
133 PS_WAIT_FOR_PSPOLL_DATA |
134 PS_WAIT_FOR_TX_ACK |
135 PS_WAIT_FOR_ANI))) {
136 mode = ATH9K_PM_NETWORK_SLEEP;
137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
138 ath9k_btcoex_stop_gen_timer(sc);
139 } else {
140 goto unlock;
141 }
142
143 spin_lock(&common->cc_lock);
144 ath_hw_cycle_counters_update(common);
145 spin_unlock(&common->cc_lock);
146
147 ath9k_hw_setpower(sc->sc_ah, mode);
148
149 unlock:
150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
151 }
152
153 static void __ath_cancel_work(struct ath_softc *sc)
154 {
155 cancel_work_sync(&sc->paprd_work);
156 cancel_work_sync(&sc->hw_check_work);
157 cancel_delayed_work_sync(&sc->tx_complete_work);
158 cancel_delayed_work_sync(&sc->hw_pll_work);
159
160 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
161 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
162 cancel_work_sync(&sc->mci_work);
163 #endif
164 }
165
166 static void ath_cancel_work(struct ath_softc *sc)
167 {
168 __ath_cancel_work(sc);
169 cancel_work_sync(&sc->hw_reset_work);
170 }
171
172 static void ath_restart_work(struct ath_softc *sc)
173 {
174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
175
176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
177 AR_SREV_9550(sc->sc_ah))
178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
180
181 ath_start_rx_poll(sc, 3);
182 ath_start_ani(sc);
183 }
184
185 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
186 {
187 struct ath_hw *ah = sc->sc_ah;
188 bool ret = true;
189
190 ieee80211_stop_queues(sc->hw);
191
192 sc->hw_busy_count = 0;
193 ath_stop_ani(sc);
194 del_timer_sync(&sc->rx_poll_timer);
195
196 ath9k_debug_samp_bb_mac(sc);
197 ath9k_hw_disable_interrupts(ah);
198
199 if (!ath_stoprecv(sc))
200 ret = false;
201
202 if (!ath_drain_all_txq(sc, retry_tx))
203 ret = false;
204
205 if (!flush) {
206 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
207 ath_rx_tasklet(sc, 1, true);
208 ath_rx_tasklet(sc, 1, false);
209 } else {
210 ath_flushrecv(sc);
211 }
212
213 return ret;
214 }
215
216 static bool ath_complete_reset(struct ath_softc *sc, bool start)
217 {
218 struct ath_hw *ah = sc->sc_ah;
219 struct ath_common *common = ath9k_hw_common(ah);
220 unsigned long flags;
221
222 if (ath_startrecv(sc) != 0) {
223 ath_err(common, "Unable to restart recv logic\n");
224 return false;
225 }
226
227 ath9k_cmn_update_txpow(ah, sc->curtxpow,
228 sc->config.txpowlimit, &sc->curtxpow);
229
230 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
231 ath9k_hw_set_interrupts(ah);
232 ath9k_hw_enable_interrupts(ah);
233
234 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
235 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
236 goto work;
237
238 ath9k_set_beacon(sc);
239
240 if (ah->opmode == NL80211_IFTYPE_STATION &&
241 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
242 spin_lock_irqsave(&sc->sc_pm_lock, flags);
243 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
244 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
245 }
246 work:
247 ath_restart_work(sc);
248 }
249
250 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
251 ath_ant_comb_update(sc);
252
253 ieee80211_wake_queues(sc->hw);
254
255 return true;
256 }
257
258 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
259 bool retry_tx)
260 {
261 struct ath_hw *ah = sc->sc_ah;
262 struct ath_common *common = ath9k_hw_common(ah);
263 struct ath9k_hw_cal_data *caldata = NULL;
264 bool fastcc = true;
265 bool flush = false;
266 int r;
267
268 __ath_cancel_work(sc);
269
270 spin_lock_bh(&sc->sc_pcu_lock);
271
272 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
273 fastcc = false;
274 caldata = &sc->caldata;
275 }
276
277 if (!hchan) {
278 fastcc = false;
279 flush = true;
280 hchan = ah->curchan;
281 }
282
283 if (!ath_prepare_reset(sc, retry_tx, flush))
284 fastcc = false;
285
286 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
287 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
288
289 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
290 if (r) {
291 ath_err(common,
292 "Unable to reset channel, reset status %d\n", r);
293 goto out;
294 }
295
296 if (!ath_complete_reset(sc, true))
297 r = -EIO;
298
299 out:
300 spin_unlock_bh(&sc->sc_pcu_lock);
301 return r;
302 }
303
304
305 /*
306 * Set/change channels. If the channel is really being changed, it's done
307 * by reseting the chip. To accomplish this we must first cleanup any pending
308 * DMA, then restart stuff.
309 */
310 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
311 struct ath9k_channel *hchan)
312 {
313 int r;
314
315 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
316 return -EIO;
317
318 r = ath_reset_internal(sc, hchan, false);
319
320 return r;
321 }
322
323 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
324 struct ieee80211_vif *vif)
325 {
326 struct ath_node *an;
327 u8 density;
328 an = (struct ath_node *)sta->drv_priv;
329
330 #ifdef CONFIG_ATH9K_DEBUGFS
331 spin_lock(&sc->nodes_lock);
332 list_add(&an->list, &sc->nodes);
333 spin_unlock(&sc->nodes_lock);
334 #endif
335 an->sta = sta;
336 an->vif = vif;
337
338 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
339 ath_tx_node_init(sc, an);
340 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
341 sta->ht_cap.ampdu_factor);
342 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
343 an->mpdudensity = density;
344 }
345 }
346
347 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
348 {
349 struct ath_node *an = (struct ath_node *)sta->drv_priv;
350
351 #ifdef CONFIG_ATH9K_DEBUGFS
352 spin_lock(&sc->nodes_lock);
353 list_del(&an->list);
354 spin_unlock(&sc->nodes_lock);
355 an->sta = NULL;
356 #endif
357
358 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
359 ath_tx_node_cleanup(sc, an);
360 }
361
362 void ath9k_tasklet(unsigned long data)
363 {
364 struct ath_softc *sc = (struct ath_softc *)data;
365 struct ath_hw *ah = sc->sc_ah;
366 struct ath_common *common = ath9k_hw_common(ah);
367 enum ath_reset_type type;
368 unsigned long flags;
369 u32 status = sc->intrstatus;
370 u32 rxmask;
371
372 ath9k_ps_wakeup(sc);
373 spin_lock(&sc->sc_pcu_lock);
374
375 if ((status & ATH9K_INT_FATAL) ||
376 (status & ATH9K_INT_BB_WATCHDOG)) {
377
378 if (status & ATH9K_INT_FATAL)
379 type = RESET_TYPE_FATAL_INT;
380 else
381 type = RESET_TYPE_BB_WATCHDOG;
382
383 ath9k_queue_reset(sc, type);
384 goto out;
385 }
386
387 spin_lock_irqsave(&sc->sc_pm_lock, flags);
388 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
389 /*
390 * TSF sync does not look correct; remain awake to sync with
391 * the next Beacon.
392 */
393 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
394 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
395 }
396 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
397
398 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
399 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
400 ATH9K_INT_RXORN);
401 else
402 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
403
404 if (status & rxmask) {
405 /* Check for high priority Rx first */
406 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
407 (status & ATH9K_INT_RXHP))
408 ath_rx_tasklet(sc, 0, true);
409
410 ath_rx_tasklet(sc, 0, false);
411 }
412
413 if (status & ATH9K_INT_TX) {
414 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
415 ath_tx_edma_tasklet(sc);
416 else
417 ath_tx_tasklet(sc);
418 }
419
420 ath9k_btcoex_handle_interrupt(sc, status);
421
422 out:
423 /* re-enable hardware interrupt */
424 ath9k_hw_enable_interrupts(ah);
425
426 spin_unlock(&sc->sc_pcu_lock);
427 ath9k_ps_restore(sc);
428 }
429
430 irqreturn_t ath_isr(int irq, void *dev)
431 {
432 #define SCHED_INTR ( \
433 ATH9K_INT_FATAL | \
434 ATH9K_INT_BB_WATCHDOG | \
435 ATH9K_INT_RXORN | \
436 ATH9K_INT_RXEOL | \
437 ATH9K_INT_RX | \
438 ATH9K_INT_RXLP | \
439 ATH9K_INT_RXHP | \
440 ATH9K_INT_TX | \
441 ATH9K_INT_BMISS | \
442 ATH9K_INT_CST | \
443 ATH9K_INT_TSFOOR | \
444 ATH9K_INT_GENTIMER | \
445 ATH9K_INT_MCI)
446
447 struct ath_softc *sc = dev;
448 struct ath_hw *ah = sc->sc_ah;
449 struct ath_common *common = ath9k_hw_common(ah);
450 enum ath9k_int status;
451 bool sched = false;
452
453 /*
454 * The hardware is not ready/present, don't
455 * touch anything. Note this can happen early
456 * on if the IRQ is shared.
457 */
458 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
459 return IRQ_NONE;
460
461 /* shared irq, not for us */
462
463 if (!ath9k_hw_intrpend(ah))
464 return IRQ_NONE;
465
466 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
467 ath9k_hw_kill_interrupts(ah);
468 return IRQ_HANDLED;
469 }
470
471 /*
472 * Figure out the reason(s) for the interrupt. Note
473 * that the hal returns a pseudo-ISR that may include
474 * bits we haven't explicitly enabled so we mask the
475 * value to insure we only process bits we requested.
476 */
477 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
478 status &= ah->imask; /* discard unasked-for bits */
479
480 /*
481 * If there are no status bits set, then this interrupt was not
482 * for me (should have been caught above).
483 */
484 if (!status)
485 return IRQ_NONE;
486
487 /* Cache the status */
488 sc->intrstatus = status;
489
490 if (status & SCHED_INTR)
491 sched = true;
492
493 #ifdef CONFIG_PM_SLEEP
494 if (status & ATH9K_INT_BMISS) {
495 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
496 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
497 atomic_inc(&sc->wow_got_bmiss_intr);
498 atomic_dec(&sc->wow_sleep_proc_intr);
499 }
500 ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
501 }
502 #endif
503
504 /*
505 * If a FATAL or RXORN interrupt is received, we have to reset the
506 * chip immediately.
507 */
508 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
509 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
510 goto chip_reset;
511
512 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
513 (status & ATH9K_INT_BB_WATCHDOG)) {
514
515 spin_lock(&common->cc_lock);
516 ath_hw_cycle_counters_update(common);
517 ar9003_hw_bb_watchdog_dbg_info(ah);
518 spin_unlock(&common->cc_lock);
519
520 goto chip_reset;
521 }
522
523 if (status & ATH9K_INT_SWBA)
524 tasklet_schedule(&sc->bcon_tasklet);
525
526 if (status & ATH9K_INT_TXURN)
527 ath9k_hw_updatetxtriglevel(ah, true);
528
529 if (status & ATH9K_INT_RXEOL) {
530 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
531 ath9k_hw_set_interrupts(ah);
532 }
533
534 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
535 if (status & ATH9K_INT_TIM_TIMER) {
536 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
537 goto chip_reset;
538 /* Clear RxAbort bit so that we can
539 * receive frames */
540 ath9k_setpower(sc, ATH9K_PM_AWAKE);
541 spin_lock(&sc->sc_pm_lock);
542 ath9k_hw_setrxabort(sc->sc_ah, 0);
543 sc->ps_flags |= PS_WAIT_FOR_BEACON;
544 spin_unlock(&sc->sc_pm_lock);
545 }
546
547 chip_reset:
548
549 ath_debug_stat_interrupt(sc, status);
550
551 if (sched) {
552 /* turn off every interrupt */
553 ath9k_hw_disable_interrupts(ah);
554 tasklet_schedule(&sc->intr_tq);
555 }
556
557 return IRQ_HANDLED;
558
559 #undef SCHED_INTR
560 }
561
562 static int ath_reset(struct ath_softc *sc, bool retry_tx)
563 {
564 int r;
565
566 ath9k_ps_wakeup(sc);
567
568 r = ath_reset_internal(sc, NULL, retry_tx);
569
570 if (retry_tx) {
571 int i;
572 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
573 if (ATH_TXQ_SETUP(sc, i)) {
574 spin_lock_bh(&sc->tx.txq[i].axq_lock);
575 ath_txq_schedule(sc, &sc->tx.txq[i]);
576 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
577 }
578 }
579 }
580
581 ath9k_ps_restore(sc);
582
583 return r;
584 }
585
586 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
587 {
588 #ifdef CONFIG_ATH9K_DEBUGFS
589 RESET_STAT_INC(sc, type);
590 #endif
591 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
592 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
593 }
594
595 void ath_reset_work(struct work_struct *work)
596 {
597 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
598
599 ath_reset(sc, true);
600 }
601
602 /**********************/
603 /* mac80211 callbacks */
604 /**********************/
605
606 static int ath9k_start(struct ieee80211_hw *hw)
607 {
608 struct ath_softc *sc = hw->priv;
609 struct ath_hw *ah = sc->sc_ah;
610 struct ath_common *common = ath9k_hw_common(ah);
611 struct ieee80211_channel *curchan = hw->conf.channel;
612 struct ath9k_channel *init_channel;
613 int r;
614
615 ath_dbg(common, CONFIG,
616 "Starting driver with initial channel: %d MHz\n",
617 curchan->center_freq);
618
619 ath9k_ps_wakeup(sc);
620 mutex_lock(&sc->mutex);
621
622 init_channel = ath9k_cmn_get_curchannel(hw, ah);
623
624 /* Reset SERDES registers */
625 ath9k_hw_configpcipowersave(ah, false);
626
627 /*
628 * The basic interface to setting the hardware in a good
629 * state is ``reset''. On return the hardware is known to
630 * be powered up and with interrupts disabled. This must
631 * be followed by initialization of the appropriate bits
632 * and then setup of the interrupt mask.
633 */
634 spin_lock_bh(&sc->sc_pcu_lock);
635
636 atomic_set(&ah->intr_ref_cnt, -1);
637
638 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
639 if (r) {
640 ath_err(common,
641 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
642 r, curchan->center_freq);
643 ah->reset_power_on = false;
644 }
645
646 /* Setup our intr mask. */
647 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
648 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
649 ATH9K_INT_GLOBAL;
650
651 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
652 ah->imask |= ATH9K_INT_RXHP |
653 ATH9K_INT_RXLP |
654 ATH9K_INT_BB_WATCHDOG;
655 else
656 ah->imask |= ATH9K_INT_RX;
657
658 ah->imask |= ATH9K_INT_GTT;
659
660 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
661 ah->imask |= ATH9K_INT_CST;
662
663 ath_mci_enable(sc);
664
665 clear_bit(SC_OP_INVALID, &sc->sc_flags);
666 sc->sc_ah->is_monitoring = false;
667
668 if (!ath_complete_reset(sc, false))
669 ah->reset_power_on = false;
670
671 if (ah->led_pin >= 0) {
672 ath9k_hw_cfg_output(ah, ah->led_pin,
673 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
674 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
675 }
676
677 /*
678 * Reset key cache to sane defaults (all entries cleared) instead of
679 * semi-random values after suspend/resume.
680 */
681 ath9k_cmn_init_crypto(sc->sc_ah);
682
683 spin_unlock_bh(&sc->sc_pcu_lock);
684
685 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
686 common->bus_ops->extn_synch_en(common);
687
688 mutex_unlock(&sc->mutex);
689
690 ath9k_ps_restore(sc);
691
692 return 0;
693 }
694
695 static void ath9k_tx(struct ieee80211_hw *hw,
696 struct ieee80211_tx_control *control,
697 struct sk_buff *skb)
698 {
699 struct ath_softc *sc = hw->priv;
700 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
701 struct ath_tx_control txctl;
702 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
703 unsigned long flags;
704
705 if (sc->ps_enabled) {
706 /*
707 * mac80211 does not set PM field for normal data frames, so we
708 * need to update that based on the current PS mode.
709 */
710 if (ieee80211_is_data(hdr->frame_control) &&
711 !ieee80211_is_nullfunc(hdr->frame_control) &&
712 !ieee80211_has_pm(hdr->frame_control)) {
713 ath_dbg(common, PS,
714 "Add PM=1 for a TX frame while in PS mode\n");
715 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
716 }
717 }
718
719 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
720 /*
721 * We are using PS-Poll and mac80211 can request TX while in
722 * power save mode. Need to wake up hardware for the TX to be
723 * completed and if needed, also for RX of buffered frames.
724 */
725 ath9k_ps_wakeup(sc);
726 spin_lock_irqsave(&sc->sc_pm_lock, flags);
727 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
728 ath9k_hw_setrxabort(sc->sc_ah, 0);
729 if (ieee80211_is_pspoll(hdr->frame_control)) {
730 ath_dbg(common, PS,
731 "Sending PS-Poll to pick a buffered frame\n");
732 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
733 } else {
734 ath_dbg(common, PS, "Wake up to complete TX\n");
735 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
736 }
737 /*
738 * The actual restore operation will happen only after
739 * the ps_flags bit is cleared. We are just dropping
740 * the ps_usecount here.
741 */
742 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
743 ath9k_ps_restore(sc);
744 }
745
746 /*
747 * Cannot tx while the hardware is in full sleep, it first needs a full
748 * chip reset to recover from that
749 */
750 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
751 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
752 goto exit;
753 }
754
755 memset(&txctl, 0, sizeof(struct ath_tx_control));
756 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
757 txctl.sta = control->sta;
758
759 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
760
761 if (ath_tx_start(hw, skb, &txctl) != 0) {
762 ath_dbg(common, XMIT, "TX failed\n");
763 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
764 goto exit;
765 }
766
767 return;
768 exit:
769 ieee80211_free_txskb(hw, skb);
770 }
771
772 static void ath9k_stop(struct ieee80211_hw *hw)
773 {
774 struct ath_softc *sc = hw->priv;
775 struct ath_hw *ah = sc->sc_ah;
776 struct ath_common *common = ath9k_hw_common(ah);
777 bool prev_idle;
778
779 mutex_lock(&sc->mutex);
780
781 ath_cancel_work(sc);
782 del_timer_sync(&sc->rx_poll_timer);
783
784 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
785 ath_dbg(common, ANY, "Device not present\n");
786 mutex_unlock(&sc->mutex);
787 return;
788 }
789
790 /* Ensure HW is awake when we try to shut it down. */
791 ath9k_ps_wakeup(sc);
792
793 spin_lock_bh(&sc->sc_pcu_lock);
794
795 /* prevent tasklets to enable interrupts once we disable them */
796 ah->imask &= ~ATH9K_INT_GLOBAL;
797
798 /* make sure h/w will not generate any interrupt
799 * before setting the invalid flag. */
800 ath9k_hw_disable_interrupts(ah);
801
802 spin_unlock_bh(&sc->sc_pcu_lock);
803
804 /* we can now sync irq and kill any running tasklets, since we already
805 * disabled interrupts and not holding a spin lock */
806 synchronize_irq(sc->irq);
807 tasklet_kill(&sc->intr_tq);
808 tasklet_kill(&sc->bcon_tasklet);
809
810 prev_idle = sc->ps_idle;
811 sc->ps_idle = true;
812
813 spin_lock_bh(&sc->sc_pcu_lock);
814
815 if (ah->led_pin >= 0) {
816 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
817 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
818 }
819
820 ath_prepare_reset(sc, false, true);
821
822 if (sc->rx.frag) {
823 dev_kfree_skb_any(sc->rx.frag);
824 sc->rx.frag = NULL;
825 }
826
827 if (!ah->curchan)
828 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
829
830 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
831 ath9k_hw_phy_disable(ah);
832
833 ath9k_hw_configpcipowersave(ah, true);
834
835 spin_unlock_bh(&sc->sc_pcu_lock);
836
837 ath9k_ps_restore(sc);
838
839 set_bit(SC_OP_INVALID, &sc->sc_flags);
840 sc->ps_idle = prev_idle;
841
842 mutex_unlock(&sc->mutex);
843
844 ath_dbg(common, CONFIG, "Driver halt\n");
845 }
846
847 bool ath9k_uses_beacons(int type)
848 {
849 switch (type) {
850 case NL80211_IFTYPE_AP:
851 case NL80211_IFTYPE_ADHOC:
852 case NL80211_IFTYPE_MESH_POINT:
853 return true;
854 default:
855 return false;
856 }
857 }
858
859 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
860 {
861 struct ath9k_vif_iter_data *iter_data = data;
862 int i;
863
864 if (iter_data->hw_macaddr)
865 for (i = 0; i < ETH_ALEN; i++)
866 iter_data->mask[i] &=
867 ~(iter_data->hw_macaddr[i] ^ mac[i]);
868
869 switch (vif->type) {
870 case NL80211_IFTYPE_AP:
871 iter_data->naps++;
872 break;
873 case NL80211_IFTYPE_STATION:
874 iter_data->nstations++;
875 break;
876 case NL80211_IFTYPE_ADHOC:
877 iter_data->nadhocs++;
878 break;
879 case NL80211_IFTYPE_MESH_POINT:
880 iter_data->nmeshes++;
881 break;
882 case NL80211_IFTYPE_WDS:
883 iter_data->nwds++;
884 break;
885 default:
886 break;
887 }
888 }
889
890 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
891 {
892 struct ath_softc *sc = data;
893 struct ath_vif *avp = (void *)vif->drv_priv;
894
895 if (vif->type != NL80211_IFTYPE_STATION)
896 return;
897
898 if (avp->primary_sta_vif)
899 ath9k_set_assoc_state(sc, vif);
900 }
901
902 /* Called with sc->mutex held. */
903 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
904 struct ieee80211_vif *vif,
905 struct ath9k_vif_iter_data *iter_data)
906 {
907 struct ath_softc *sc = hw->priv;
908 struct ath_hw *ah = sc->sc_ah;
909 struct ath_common *common = ath9k_hw_common(ah);
910
911 /*
912 * Use the hardware MAC address as reference, the hardware uses it
913 * together with the BSSID mask when matching addresses.
914 */
915 memset(iter_data, 0, sizeof(*iter_data));
916 iter_data->hw_macaddr = common->macaddr;
917 memset(&iter_data->mask, 0xff, ETH_ALEN);
918
919 if (vif)
920 ath9k_vif_iter(iter_data, vif->addr, vif);
921
922 /* Get list of all active MAC addresses */
923 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
924 iter_data);
925 }
926
927 /* Called with sc->mutex held. */
928 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
929 struct ieee80211_vif *vif)
930 {
931 struct ath_softc *sc = hw->priv;
932 struct ath_hw *ah = sc->sc_ah;
933 struct ath_common *common = ath9k_hw_common(ah);
934 struct ath9k_vif_iter_data iter_data;
935 enum nl80211_iftype old_opmode = ah->opmode;
936
937 ath9k_calculate_iter_data(hw, vif, &iter_data);
938
939 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
940 ath_hw_setbssidmask(common);
941
942 if (iter_data.naps > 0) {
943 ath9k_hw_set_tsfadjust(ah, true);
944 ah->opmode = NL80211_IFTYPE_AP;
945 } else {
946 ath9k_hw_set_tsfadjust(ah, false);
947
948 if (iter_data.nmeshes)
949 ah->opmode = NL80211_IFTYPE_MESH_POINT;
950 else if (iter_data.nwds)
951 ah->opmode = NL80211_IFTYPE_AP;
952 else if (iter_data.nadhocs)
953 ah->opmode = NL80211_IFTYPE_ADHOC;
954 else
955 ah->opmode = NL80211_IFTYPE_STATION;
956 }
957
958 ath9k_hw_setopmode(ah);
959
960 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
961 ah->imask |= ATH9K_INT_TSFOOR;
962 else
963 ah->imask &= ~ATH9K_INT_TSFOOR;
964
965 ath9k_hw_set_interrupts(ah);
966
967 /*
968 * If we are changing the opmode to STATION,
969 * a beacon sync needs to be done.
970 */
971 if (ah->opmode == NL80211_IFTYPE_STATION &&
972 old_opmode == NL80211_IFTYPE_AP &&
973 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
974 ieee80211_iterate_active_interfaces_atomic(sc->hw,
975 ath9k_sta_vif_iter, sc);
976 }
977 }
978
979 static int ath9k_add_interface(struct ieee80211_hw *hw,
980 struct ieee80211_vif *vif)
981 {
982 struct ath_softc *sc = hw->priv;
983 struct ath_hw *ah = sc->sc_ah;
984 struct ath_common *common = ath9k_hw_common(ah);
985
986 mutex_lock(&sc->mutex);
987
988 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
989 sc->nvifs++;
990
991 ath9k_ps_wakeup(sc);
992 ath9k_calculate_summary_state(hw, vif);
993 ath9k_ps_restore(sc);
994
995 if (ath9k_uses_beacons(vif->type))
996 ath9k_beacon_assign_slot(sc, vif);
997
998 mutex_unlock(&sc->mutex);
999 return 0;
1000 }
1001
1002 static int ath9k_change_interface(struct ieee80211_hw *hw,
1003 struct ieee80211_vif *vif,
1004 enum nl80211_iftype new_type,
1005 bool p2p)
1006 {
1007 struct ath_softc *sc = hw->priv;
1008 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1009
1010 ath_dbg(common, CONFIG, "Change Interface\n");
1011 mutex_lock(&sc->mutex);
1012
1013 if (ath9k_uses_beacons(vif->type))
1014 ath9k_beacon_remove_slot(sc, vif);
1015
1016 vif->type = new_type;
1017 vif->p2p = p2p;
1018
1019 ath9k_ps_wakeup(sc);
1020 ath9k_calculate_summary_state(hw, vif);
1021 ath9k_ps_restore(sc);
1022
1023 if (ath9k_uses_beacons(vif->type))
1024 ath9k_beacon_assign_slot(sc, vif);
1025
1026 mutex_unlock(&sc->mutex);
1027 return 0;
1028 }
1029
1030 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1031 struct ieee80211_vif *vif)
1032 {
1033 struct ath_softc *sc = hw->priv;
1034 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1035
1036 ath_dbg(common, CONFIG, "Detach Interface\n");
1037
1038 mutex_lock(&sc->mutex);
1039
1040 sc->nvifs--;
1041
1042 if (ath9k_uses_beacons(vif->type))
1043 ath9k_beacon_remove_slot(sc, vif);
1044
1045 ath9k_ps_wakeup(sc);
1046 ath9k_calculate_summary_state(hw, NULL);
1047 ath9k_ps_restore(sc);
1048
1049 mutex_unlock(&sc->mutex);
1050 }
1051
1052 static void ath9k_enable_ps(struct ath_softc *sc)
1053 {
1054 struct ath_hw *ah = sc->sc_ah;
1055 struct ath_common *common = ath9k_hw_common(ah);
1056
1057 sc->ps_enabled = true;
1058 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1059 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1060 ah->imask |= ATH9K_INT_TIM_TIMER;
1061 ath9k_hw_set_interrupts(ah);
1062 }
1063 ath9k_hw_setrxabort(ah, 1);
1064 }
1065 ath_dbg(common, PS, "PowerSave enabled\n");
1066 }
1067
1068 static void ath9k_disable_ps(struct ath_softc *sc)
1069 {
1070 struct ath_hw *ah = sc->sc_ah;
1071 struct ath_common *common = ath9k_hw_common(ah);
1072
1073 sc->ps_enabled = false;
1074 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1075 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1076 ath9k_hw_setrxabort(ah, 0);
1077 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1078 PS_WAIT_FOR_CAB |
1079 PS_WAIT_FOR_PSPOLL_DATA |
1080 PS_WAIT_FOR_TX_ACK);
1081 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1082 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1083 ath9k_hw_set_interrupts(ah);
1084 }
1085 }
1086 ath_dbg(common, PS, "PowerSave disabled\n");
1087 }
1088
1089 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1090 {
1091 struct ath_softc *sc = hw->priv;
1092 struct ath_hw *ah = sc->sc_ah;
1093 struct ath_common *common = ath9k_hw_common(ah);
1094 struct ieee80211_conf *conf = &hw->conf;
1095 bool reset_channel = false;
1096
1097 ath9k_ps_wakeup(sc);
1098 mutex_lock(&sc->mutex);
1099
1100 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1101 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1102 if (sc->ps_idle) {
1103 ath_cancel_work(sc);
1104 ath9k_stop_btcoex(sc);
1105 } else {
1106 ath9k_start_btcoex(sc);
1107 /*
1108 * The chip needs a reset to properly wake up from
1109 * full sleep
1110 */
1111 reset_channel = ah->chip_fullsleep;
1112 }
1113 }
1114
1115 /*
1116 * We just prepare to enable PS. We have to wait until our AP has
1117 * ACK'd our null data frame to disable RX otherwise we'll ignore
1118 * those ACKs and end up retransmitting the same null data frames.
1119 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1120 */
1121 if (changed & IEEE80211_CONF_CHANGE_PS) {
1122 unsigned long flags;
1123 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1124 if (conf->flags & IEEE80211_CONF_PS)
1125 ath9k_enable_ps(sc);
1126 else
1127 ath9k_disable_ps(sc);
1128 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1129 }
1130
1131 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1132 if (conf->flags & IEEE80211_CONF_MONITOR) {
1133 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1134 sc->sc_ah->is_monitoring = true;
1135 } else {
1136 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1137 sc->sc_ah->is_monitoring = false;
1138 }
1139 }
1140
1141 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
1142 struct ieee80211_channel *curchan = hw->conf.channel;
1143 int pos = curchan->hw_value;
1144 int old_pos = -1;
1145 unsigned long flags;
1146
1147 if (ah->curchan)
1148 old_pos = ah->curchan - &ah->channels[0];
1149
1150 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
1151 curchan->center_freq, conf->channel_type);
1152
1153 /* update survey stats for the old channel before switching */
1154 spin_lock_irqsave(&common->cc_lock, flags);
1155 ath_update_survey_stats(sc);
1156 spin_unlock_irqrestore(&common->cc_lock, flags);
1157
1158 /*
1159 * Preserve the current channel values, before updating
1160 * the same channel
1161 */
1162 if (ah->curchan && (old_pos == pos))
1163 ath9k_hw_getnf(ah, ah->curchan);
1164
1165 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1166 curchan, conf->channel_type);
1167
1168 /*
1169 * If the operating channel changes, change the survey in-use flags
1170 * along with it.
1171 * Reset the survey data for the new channel, unless we're switching
1172 * back to the operating channel from an off-channel operation.
1173 */
1174 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1175 sc->cur_survey != &sc->survey[pos]) {
1176
1177 if (sc->cur_survey)
1178 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1179
1180 sc->cur_survey = &sc->survey[pos];
1181
1182 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1183 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1184 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1185 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1186 }
1187
1188 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1189 ath_err(common, "Unable to set channel\n");
1190 mutex_unlock(&sc->mutex);
1191 ath9k_ps_restore(sc);
1192 return -EINVAL;
1193 }
1194
1195 /*
1196 * The most recent snapshot of channel->noisefloor for the old
1197 * channel is only available after the hardware reset. Copy it to
1198 * the survey stats now.
1199 */
1200 if (old_pos >= 0)
1201 ath_update_survey_nf(sc, old_pos);
1202 }
1203
1204 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1205 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1206 sc->config.txpowlimit = 2 * conf->power_level;
1207 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1208 sc->config.txpowlimit, &sc->curtxpow);
1209 }
1210
1211 mutex_unlock(&sc->mutex);
1212 ath9k_ps_restore(sc);
1213
1214 return 0;
1215 }
1216
1217 #define SUPPORTED_FILTERS \
1218 (FIF_PROMISC_IN_BSS | \
1219 FIF_ALLMULTI | \
1220 FIF_CONTROL | \
1221 FIF_PSPOLL | \
1222 FIF_OTHER_BSS | \
1223 FIF_BCN_PRBRESP_PROMISC | \
1224 FIF_PROBE_REQ | \
1225 FIF_FCSFAIL)
1226
1227 /* FIXME: sc->sc_full_reset ? */
1228 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1229 unsigned int changed_flags,
1230 unsigned int *total_flags,
1231 u64 multicast)
1232 {
1233 struct ath_softc *sc = hw->priv;
1234 u32 rfilt;
1235
1236 changed_flags &= SUPPORTED_FILTERS;
1237 *total_flags &= SUPPORTED_FILTERS;
1238
1239 sc->rx.rxfilter = *total_flags;
1240 ath9k_ps_wakeup(sc);
1241 rfilt = ath_calcrxfilter(sc);
1242 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1243 ath9k_ps_restore(sc);
1244
1245 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1246 rfilt);
1247 }
1248
1249 static int ath9k_sta_add(struct ieee80211_hw *hw,
1250 struct ieee80211_vif *vif,
1251 struct ieee80211_sta *sta)
1252 {
1253 struct ath_softc *sc = hw->priv;
1254 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1255 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1256 struct ieee80211_key_conf ps_key = { };
1257
1258 ath_node_attach(sc, sta, vif);
1259
1260 if (vif->type != NL80211_IFTYPE_AP &&
1261 vif->type != NL80211_IFTYPE_AP_VLAN)
1262 return 0;
1263
1264 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
1265
1266 return 0;
1267 }
1268
1269 static void ath9k_del_ps_key(struct ath_softc *sc,
1270 struct ieee80211_vif *vif,
1271 struct ieee80211_sta *sta)
1272 {
1273 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1274 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1275 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1276
1277 if (!an->ps_key)
1278 return;
1279
1280 ath_key_delete(common, &ps_key);
1281 }
1282
1283 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1284 struct ieee80211_vif *vif,
1285 struct ieee80211_sta *sta)
1286 {
1287 struct ath_softc *sc = hw->priv;
1288
1289 ath9k_del_ps_key(sc, vif, sta);
1290 ath_node_detach(sc, sta);
1291
1292 return 0;
1293 }
1294
1295 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1296 struct ieee80211_vif *vif,
1297 enum sta_notify_cmd cmd,
1298 struct ieee80211_sta *sta)
1299 {
1300 struct ath_softc *sc = hw->priv;
1301 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1302
1303 if (!sta->ht_cap.ht_supported)
1304 return;
1305
1306 switch (cmd) {
1307 case STA_NOTIFY_SLEEP:
1308 an->sleeping = true;
1309 ath_tx_aggr_sleep(sta, sc, an);
1310 break;
1311 case STA_NOTIFY_AWAKE:
1312 an->sleeping = false;
1313 ath_tx_aggr_wakeup(sc, an);
1314 break;
1315 }
1316 }
1317
1318 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1319 struct ieee80211_vif *vif, u16 queue,
1320 const struct ieee80211_tx_queue_params *params)
1321 {
1322 struct ath_softc *sc = hw->priv;
1323 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1324 struct ath_txq *txq;
1325 struct ath9k_tx_queue_info qi;
1326 int ret = 0;
1327
1328 if (queue >= WME_NUM_AC)
1329 return 0;
1330
1331 txq = sc->tx.txq_map[queue];
1332
1333 ath9k_ps_wakeup(sc);
1334 mutex_lock(&sc->mutex);
1335
1336 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1337
1338 qi.tqi_aifs = params->aifs;
1339 qi.tqi_cwmin = params->cw_min;
1340 qi.tqi_cwmax = params->cw_max;
1341 qi.tqi_burstTime = params->txop * 32;
1342
1343 ath_dbg(common, CONFIG,
1344 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1345 queue, txq->axq_qnum, params->aifs, params->cw_min,
1346 params->cw_max, params->txop);
1347
1348 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1349 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1350 if (ret)
1351 ath_err(common, "TXQ Update failed\n");
1352
1353 mutex_unlock(&sc->mutex);
1354 ath9k_ps_restore(sc);
1355
1356 return ret;
1357 }
1358
1359 static int ath9k_set_key(struct ieee80211_hw *hw,
1360 enum set_key_cmd cmd,
1361 struct ieee80211_vif *vif,
1362 struct ieee80211_sta *sta,
1363 struct ieee80211_key_conf *key)
1364 {
1365 struct ath_softc *sc = hw->priv;
1366 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1367 int ret = 0;
1368
1369 if (ath9k_modparam_nohwcrypt)
1370 return -ENOSPC;
1371
1372 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1373 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1374 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1375 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1376 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1377 /*
1378 * For now, disable hw crypto for the RSN IBSS group keys. This
1379 * could be optimized in the future to use a modified key cache
1380 * design to support per-STA RX GTK, but until that gets
1381 * implemented, use of software crypto for group addressed
1382 * frames is a acceptable to allow RSN IBSS to be used.
1383 */
1384 return -EOPNOTSUPP;
1385 }
1386
1387 mutex_lock(&sc->mutex);
1388 ath9k_ps_wakeup(sc);
1389 ath_dbg(common, CONFIG, "Set HW Key\n");
1390
1391 switch (cmd) {
1392 case SET_KEY:
1393 if (sta)
1394 ath9k_del_ps_key(sc, vif, sta);
1395
1396 ret = ath_key_config(common, vif, sta, key);
1397 if (ret >= 0) {
1398 key->hw_key_idx = ret;
1399 /* push IV and Michael MIC generation to stack */
1400 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1401 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1402 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1403 if (sc->sc_ah->sw_mgmt_crypto &&
1404 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1405 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1406 ret = 0;
1407 }
1408 break;
1409 case DISABLE_KEY:
1410 ath_key_delete(common, key);
1411 break;
1412 default:
1413 ret = -EINVAL;
1414 }
1415
1416 ath9k_ps_restore(sc);
1417 mutex_unlock(&sc->mutex);
1418
1419 return ret;
1420 }
1421
1422 static void ath9k_set_assoc_state(struct ath_softc *sc,
1423 struct ieee80211_vif *vif)
1424 {
1425 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1426 struct ath_vif *avp = (void *)vif->drv_priv;
1427 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1428 unsigned long flags;
1429
1430 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1431 avp->primary_sta_vif = true;
1432
1433 /*
1434 * Set the AID, BSSID and do beacon-sync only when
1435 * the HW opmode is STATION.
1436 *
1437 * But the primary bit is set above in any case.
1438 */
1439 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1440 return;
1441
1442 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1443 common->curaid = bss_conf->aid;
1444 ath9k_hw_write_associd(sc->sc_ah);
1445
1446 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1447 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1448
1449 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1450 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1451 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1452
1453 ath_dbg(common, CONFIG,
1454 "Primary Station interface: %pM, BSSID: %pM\n",
1455 vif->addr, common->curbssid);
1456 }
1457
1458 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1459 {
1460 struct ath_softc *sc = data;
1461 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1462
1463 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
1464 return;
1465
1466 if (bss_conf->assoc)
1467 ath9k_set_assoc_state(sc, vif);
1468 }
1469
1470 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1471 struct ieee80211_vif *vif,
1472 struct ieee80211_bss_conf *bss_conf,
1473 u32 changed)
1474 {
1475 #define CHECK_ANI \
1476 (BSS_CHANGED_ASSOC | \
1477 BSS_CHANGED_IBSS | \
1478 BSS_CHANGED_BEACON_ENABLED)
1479
1480 struct ath_softc *sc = hw->priv;
1481 struct ath_hw *ah = sc->sc_ah;
1482 struct ath_common *common = ath9k_hw_common(ah);
1483 struct ath_vif *avp = (void *)vif->drv_priv;
1484 int slottime;
1485
1486 ath9k_ps_wakeup(sc);
1487 mutex_lock(&sc->mutex);
1488
1489 if (changed & BSS_CHANGED_ASSOC) {
1490 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1491 bss_conf->bssid, bss_conf->assoc);
1492
1493 if (avp->primary_sta_vif && !bss_conf->assoc) {
1494 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1495 avp->primary_sta_vif = false;
1496
1497 if (ah->opmode == NL80211_IFTYPE_STATION)
1498 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1499 }
1500
1501 ieee80211_iterate_active_interfaces_atomic(sc->hw,
1502 ath9k_bss_assoc_iter, sc);
1503
1504 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1505 ah->opmode == NL80211_IFTYPE_STATION) {
1506 memset(common->curbssid, 0, ETH_ALEN);
1507 common->curaid = 0;
1508 ath9k_hw_write_associd(sc->sc_ah);
1509 }
1510 }
1511
1512 if (changed & BSS_CHANGED_IBSS) {
1513 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1514 common->curaid = bss_conf->aid;
1515 ath9k_hw_write_associd(sc->sc_ah);
1516 }
1517
1518 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1519 (changed & BSS_CHANGED_BEACON_INT)) {
1520 if (ah->opmode == NL80211_IFTYPE_AP &&
1521 bss_conf->enable_beacon)
1522 ath9k_set_tsfadjust(sc, vif);
1523 if (ath9k_allow_beacon_config(sc, vif))
1524 ath9k_beacon_config(sc, vif, changed);
1525 }
1526
1527 if (changed & BSS_CHANGED_ERP_SLOT) {
1528 if (bss_conf->use_short_slot)
1529 slottime = 9;
1530 else
1531 slottime = 20;
1532 if (vif->type == NL80211_IFTYPE_AP) {
1533 /*
1534 * Defer update, so that connected stations can adjust
1535 * their settings at the same time.
1536 * See beacon.c for more details
1537 */
1538 sc->beacon.slottime = slottime;
1539 sc->beacon.updateslot = UPDATE;
1540 } else {
1541 ah->slottime = slottime;
1542 ath9k_hw_init_global_settings(ah);
1543 }
1544 }
1545
1546 if (changed & CHECK_ANI)
1547 ath_check_ani(sc);
1548
1549 mutex_unlock(&sc->mutex);
1550 ath9k_ps_restore(sc);
1551
1552 #undef CHECK_ANI
1553 }
1554
1555 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1556 {
1557 struct ath_softc *sc = hw->priv;
1558 u64 tsf;
1559
1560 mutex_lock(&sc->mutex);
1561 ath9k_ps_wakeup(sc);
1562 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1563 ath9k_ps_restore(sc);
1564 mutex_unlock(&sc->mutex);
1565
1566 return tsf;
1567 }
1568
1569 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1570 struct ieee80211_vif *vif,
1571 u64 tsf)
1572 {
1573 struct ath_softc *sc = hw->priv;
1574
1575 mutex_lock(&sc->mutex);
1576 ath9k_ps_wakeup(sc);
1577 ath9k_hw_settsf64(sc->sc_ah, tsf);
1578 ath9k_ps_restore(sc);
1579 mutex_unlock(&sc->mutex);
1580 }
1581
1582 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1583 {
1584 struct ath_softc *sc = hw->priv;
1585
1586 mutex_lock(&sc->mutex);
1587
1588 ath9k_ps_wakeup(sc);
1589 ath9k_hw_reset_tsf(sc->sc_ah);
1590 ath9k_ps_restore(sc);
1591
1592 mutex_unlock(&sc->mutex);
1593 }
1594
1595 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1596 struct ieee80211_vif *vif,
1597 enum ieee80211_ampdu_mlme_action action,
1598 struct ieee80211_sta *sta,
1599 u16 tid, u16 *ssn, u8 buf_size)
1600 {
1601 struct ath_softc *sc = hw->priv;
1602 int ret = 0;
1603
1604 local_bh_disable();
1605
1606 switch (action) {
1607 case IEEE80211_AMPDU_RX_START:
1608 break;
1609 case IEEE80211_AMPDU_RX_STOP:
1610 break;
1611 case IEEE80211_AMPDU_TX_START:
1612 ath9k_ps_wakeup(sc);
1613 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1614 if (!ret)
1615 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1616 ath9k_ps_restore(sc);
1617 break;
1618 case IEEE80211_AMPDU_TX_STOP:
1619 ath9k_ps_wakeup(sc);
1620 ath_tx_aggr_stop(sc, sta, tid);
1621 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1622 ath9k_ps_restore(sc);
1623 break;
1624 case IEEE80211_AMPDU_TX_OPERATIONAL:
1625 ath9k_ps_wakeup(sc);
1626 ath_tx_aggr_resume(sc, sta, tid);
1627 ath9k_ps_restore(sc);
1628 break;
1629 default:
1630 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1631 }
1632
1633 local_bh_enable();
1634
1635 return ret;
1636 }
1637
1638 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1639 struct survey_info *survey)
1640 {
1641 struct ath_softc *sc = hw->priv;
1642 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1643 struct ieee80211_supported_band *sband;
1644 struct ieee80211_channel *chan;
1645 unsigned long flags;
1646 int pos;
1647
1648 spin_lock_irqsave(&common->cc_lock, flags);
1649 if (idx == 0)
1650 ath_update_survey_stats(sc);
1651
1652 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1653 if (sband && idx >= sband->n_channels) {
1654 idx -= sband->n_channels;
1655 sband = NULL;
1656 }
1657
1658 if (!sband)
1659 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1660
1661 if (!sband || idx >= sband->n_channels) {
1662 spin_unlock_irqrestore(&common->cc_lock, flags);
1663 return -ENOENT;
1664 }
1665
1666 chan = &sband->channels[idx];
1667 pos = chan->hw_value;
1668 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1669 survey->channel = chan;
1670 spin_unlock_irqrestore(&common->cc_lock, flags);
1671
1672 return 0;
1673 }
1674
1675 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1676 {
1677 struct ath_softc *sc = hw->priv;
1678 struct ath_hw *ah = sc->sc_ah;
1679
1680 mutex_lock(&sc->mutex);
1681 ah->coverage_class = coverage_class;
1682
1683 ath9k_ps_wakeup(sc);
1684 ath9k_hw_init_global_settings(ah);
1685 ath9k_ps_restore(sc);
1686
1687 mutex_unlock(&sc->mutex);
1688 }
1689
1690 static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1691 {
1692 struct ath_softc *sc = hw->priv;
1693 struct ath_hw *ah = sc->sc_ah;
1694 struct ath_common *common = ath9k_hw_common(ah);
1695 int timeout = 200; /* ms */
1696 int i, j;
1697 bool drain_txq;
1698
1699 mutex_lock(&sc->mutex);
1700 cancel_delayed_work_sync(&sc->tx_complete_work);
1701
1702 if (ah->ah_flags & AH_UNPLUGGED) {
1703 ath_dbg(common, ANY, "Device has been unplugged!\n");
1704 mutex_unlock(&sc->mutex);
1705 return;
1706 }
1707
1708 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
1709 ath_dbg(common, ANY, "Device not present\n");
1710 mutex_unlock(&sc->mutex);
1711 return;
1712 }
1713
1714 for (j = 0; j < timeout; j++) {
1715 bool npend = false;
1716
1717 if (j)
1718 usleep_range(1000, 2000);
1719
1720 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1721 if (!ATH_TXQ_SETUP(sc, i))
1722 continue;
1723
1724 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1725
1726 if (npend)
1727 break;
1728 }
1729
1730 if (!npend)
1731 break;
1732 }
1733
1734 if (drop) {
1735 ath9k_ps_wakeup(sc);
1736 spin_lock_bh(&sc->sc_pcu_lock);
1737 drain_txq = ath_drain_all_txq(sc, false);
1738 spin_unlock_bh(&sc->sc_pcu_lock);
1739
1740 if (!drain_txq)
1741 ath_reset(sc, false);
1742
1743 ath9k_ps_restore(sc);
1744 ieee80211_wake_queues(hw);
1745 }
1746
1747 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1748 mutex_unlock(&sc->mutex);
1749 }
1750
1751 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1752 {
1753 struct ath_softc *sc = hw->priv;
1754 int i;
1755
1756 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1757 if (!ATH_TXQ_SETUP(sc, i))
1758 continue;
1759
1760 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1761 return true;
1762 }
1763 return false;
1764 }
1765
1766 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
1767 {
1768 struct ath_softc *sc = hw->priv;
1769 struct ath_hw *ah = sc->sc_ah;
1770 struct ieee80211_vif *vif;
1771 struct ath_vif *avp;
1772 struct ath_buf *bf;
1773 struct ath_tx_status ts;
1774 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1775 int status;
1776
1777 vif = sc->beacon.bslot[0];
1778 if (!vif)
1779 return 0;
1780
1781 if (!vif->bss_conf.enable_beacon)
1782 return 0;
1783
1784 avp = (void *)vif->drv_priv;
1785
1786 if (!sc->beacon.tx_processed && !edma) {
1787 tasklet_disable(&sc->bcon_tasklet);
1788
1789 bf = avp->av_bcbuf;
1790 if (!bf || !bf->bf_mpdu)
1791 goto skip;
1792
1793 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1794 if (status == -EINPROGRESS)
1795 goto skip;
1796
1797 sc->beacon.tx_processed = true;
1798 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1799
1800 skip:
1801 tasklet_enable(&sc->bcon_tasklet);
1802 }
1803
1804 return sc->beacon.tx_last;
1805 }
1806
1807 static int ath9k_get_stats(struct ieee80211_hw *hw,
1808 struct ieee80211_low_level_stats *stats)
1809 {
1810 struct ath_softc *sc = hw->priv;
1811 struct ath_hw *ah = sc->sc_ah;
1812 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1813
1814 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1815 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1816 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1817 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1818 return 0;
1819 }
1820
1821 static u32 fill_chainmask(u32 cap, u32 new)
1822 {
1823 u32 filled = 0;
1824 int i;
1825
1826 for (i = 0; cap && new; i++, cap >>= 1) {
1827 if (!(cap & BIT(0)))
1828 continue;
1829
1830 if (new & BIT(0))
1831 filled |= BIT(i);
1832
1833 new >>= 1;
1834 }
1835
1836 return filled;
1837 }
1838
1839 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
1840 {
1841 switch (val & 0x7) {
1842 case 0x1:
1843 case 0x3:
1844 case 0x7:
1845 return true;
1846 case 0x2:
1847 return (ah->caps.rx_chainmask == 1);
1848 default:
1849 return false;
1850 }
1851 }
1852
1853 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1854 {
1855 struct ath_softc *sc = hw->priv;
1856 struct ath_hw *ah = sc->sc_ah;
1857
1858 if (ah->caps.rx_chainmask != 1)
1859 rx_ant |= tx_ant;
1860
1861 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
1862 return -EINVAL;
1863
1864 sc->ant_rx = rx_ant;
1865 sc->ant_tx = tx_ant;
1866
1867 if (ah->caps.rx_chainmask == 1)
1868 return 0;
1869
1870 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1871 if (AR_SREV_9100(ah))
1872 ah->rxchainmask = 0x7;
1873 else
1874 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1875
1876 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1877 ath9k_reload_chainmask_settings(sc);
1878
1879 return 0;
1880 }
1881
1882 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1883 {
1884 struct ath_softc *sc = hw->priv;
1885
1886 *tx_ant = sc->ant_tx;
1887 *rx_ant = sc->ant_rx;
1888 return 0;
1889 }
1890
1891 #ifdef CONFIG_ATH9K_DEBUGFS
1892
1893 /* Ethtool support for get-stats */
1894
1895 #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
1896 static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
1897 "tx_pkts_nic",
1898 "tx_bytes_nic",
1899 "rx_pkts_nic",
1900 "rx_bytes_nic",
1901 AMKSTR(d_tx_pkts),
1902 AMKSTR(d_tx_bytes),
1903 AMKSTR(d_tx_mpdus_queued),
1904 AMKSTR(d_tx_mpdus_completed),
1905 AMKSTR(d_tx_mpdu_xretries),
1906 AMKSTR(d_tx_aggregates),
1907 AMKSTR(d_tx_ampdus_queued_hw),
1908 AMKSTR(d_tx_ampdus_queued_sw),
1909 AMKSTR(d_tx_ampdus_completed),
1910 AMKSTR(d_tx_ampdu_retries),
1911 AMKSTR(d_tx_ampdu_xretries),
1912 AMKSTR(d_tx_fifo_underrun),
1913 AMKSTR(d_tx_op_exceeded),
1914 AMKSTR(d_tx_timer_expiry),
1915 AMKSTR(d_tx_desc_cfg_err),
1916 AMKSTR(d_tx_data_underrun),
1917 AMKSTR(d_tx_delim_underrun),
1918
1919 "d_rx_decrypt_crc_err",
1920 "d_rx_phy_err",
1921 "d_rx_mic_err",
1922 "d_rx_pre_delim_crc_err",
1923 "d_rx_post_delim_crc_err",
1924 "d_rx_decrypt_busy_err",
1925
1926 "d_rx_phyerr_radar",
1927 "d_rx_phyerr_ofdm_timing",
1928 "d_rx_phyerr_cck_timing",
1929
1930 };
1931 #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
1932
1933 static void ath9k_get_et_strings(struct ieee80211_hw *hw,
1934 struct ieee80211_vif *vif,
1935 u32 sset, u8 *data)
1936 {
1937 if (sset == ETH_SS_STATS)
1938 memcpy(data, *ath9k_gstrings_stats,
1939 sizeof(ath9k_gstrings_stats));
1940 }
1941
1942 static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
1943 struct ieee80211_vif *vif, int sset)
1944 {
1945 if (sset == ETH_SS_STATS)
1946 return ATH9K_SSTATS_LEN;
1947 return 0;
1948 }
1949
1950 #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
1951 #define AWDATA(elem) \
1952 do { \
1953 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
1954 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
1955 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
1956 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
1957 } while (0)
1958
1959 #define AWDATA_RX(elem) \
1960 do { \
1961 data[i++] = sc->debug.stats.rxstats.elem; \
1962 } while (0)
1963
1964 static void ath9k_get_et_stats(struct ieee80211_hw *hw,
1965 struct ieee80211_vif *vif,
1966 struct ethtool_stats *stats, u64 *data)
1967 {
1968 struct ath_softc *sc = hw->priv;
1969 int i = 0;
1970
1971 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
1972 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
1973 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
1974 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
1975 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
1976 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
1977 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
1978 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
1979 AWDATA_RX(rx_pkts_all);
1980 AWDATA_RX(rx_bytes_all);
1981
1982 AWDATA(tx_pkts_all);
1983 AWDATA(tx_bytes_all);
1984 AWDATA(queued);
1985 AWDATA(completed);
1986 AWDATA(xretries);
1987 AWDATA(a_aggr);
1988 AWDATA(a_queued_hw);
1989 AWDATA(a_queued_sw);
1990 AWDATA(a_completed);
1991 AWDATA(a_retries);
1992 AWDATA(a_xretries);
1993 AWDATA(fifo_underrun);
1994 AWDATA(xtxop);
1995 AWDATA(timer_exp);
1996 AWDATA(desc_cfg_err);
1997 AWDATA(data_underrun);
1998 AWDATA(delim_underrun);
1999
2000 AWDATA_RX(decrypt_crc_err);
2001 AWDATA_RX(phy_err);
2002 AWDATA_RX(mic_err);
2003 AWDATA_RX(pre_delim_crc_err);
2004 AWDATA_RX(post_delim_crc_err);
2005 AWDATA_RX(decrypt_busy_err);
2006
2007 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
2008 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
2009 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
2010
2011 WARN_ON(i != ATH9K_SSTATS_LEN);
2012 }
2013
2014 /* End of ethtool get-stats functions */
2015
2016 #endif
2017
2018
2019 #ifdef CONFIG_PM_SLEEP
2020
2021 static void ath9k_wow_map_triggers(struct ath_softc *sc,
2022 struct cfg80211_wowlan *wowlan,
2023 u32 *wow_triggers)
2024 {
2025 if (wowlan->disconnect)
2026 *wow_triggers |= AH_WOW_LINK_CHANGE |
2027 AH_WOW_BEACON_MISS;
2028 if (wowlan->magic_pkt)
2029 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
2030
2031 if (wowlan->n_patterns)
2032 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
2033
2034 sc->wow_enabled = *wow_triggers;
2035
2036 }
2037
2038 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
2039 {
2040 struct ath_hw *ah = sc->sc_ah;
2041 struct ath_common *common = ath9k_hw_common(ah);
2042 struct ath9k_hw_capabilities *pcaps = &ah->caps;
2043 int pattern_count = 0;
2044 int i, byte_cnt;
2045 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
2046 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
2047
2048 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2049 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2050
2051 /*
2052 * Create Dissassociate / Deauthenticate packet filter
2053 *
2054 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
2055 * +--------------+----------+---------+--------+--------+----
2056 * + Frame Control+ Duration + DA + SA + BSSID +
2057 * +--------------+----------+---------+--------+--------+----
2058 *
2059 * The above is the management frame format for disassociate/
2060 * deauthenticate pattern, from this we need to match the first byte
2061 * of 'Frame Control' and DA, SA, and BSSID fields
2062 * (skipping 2nd byte of FC and Duration feild.
2063 *
2064 * Disassociate pattern
2065 * --------------------
2066 * Frame control = 00 00 1010
2067 * DA, SA, BSSID = x:x:x:x:x:x
2068 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2069 * | x:x:x:x:x:x -- 22 bytes
2070 *
2071 * Deauthenticate pattern
2072 * ----------------------
2073 * Frame control = 00 00 1100
2074 * DA, SA, BSSID = x:x:x:x:x:x
2075 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2076 * | x:x:x:x:x:x -- 22 bytes
2077 */
2078
2079 /* Create Disassociate Pattern first */
2080
2081 byte_cnt = 0;
2082
2083 /* Fill out the mask with all FF's */
2084
2085 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2086 dis_deauth_mask[i] = 0xff;
2087
2088 /* copy the first byte of frame control field */
2089 dis_deauth_pattern[byte_cnt] = 0xa0;
2090 byte_cnt++;
2091
2092 /* skip 2nd byte of frame control and Duration field */
2093 byte_cnt += 3;
2094
2095 /*
2096 * need not match the destination mac address, it can be a broadcast
2097 * mac address or an unicast to this station
2098 */
2099 byte_cnt += 6;
2100
2101 /* copy the source mac address */
2102 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2103
2104 byte_cnt += 6;
2105
2106 /* copy the bssid, its same as the source mac address */
2107
2108 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2109
2110 /* Create Disassociate pattern mask */
2111
2112 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
2113
2114 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
2115 /*
2116 * for AR9280, because of hardware limitation, the
2117 * first 4 bytes have to be matched for all patterns.
2118 * the mask for disassociation and de-auth pattern
2119 * matching need to enable the first 4 bytes.
2120 * also the duration field needs to be filled.
2121 */
2122 dis_deauth_mask[0] = 0xf0;
2123
2124 /*
2125 * fill in duration field
2126 FIXME: what is the exact value ?
2127 */
2128 dis_deauth_pattern[2] = 0xff;
2129 dis_deauth_pattern[3] = 0xff;
2130 } else {
2131 dis_deauth_mask[0] = 0xfe;
2132 }
2133
2134 dis_deauth_mask[1] = 0x03;
2135 dis_deauth_mask[2] = 0xc0;
2136 } else {
2137 dis_deauth_mask[0] = 0xef;
2138 dis_deauth_mask[1] = 0x3f;
2139 dis_deauth_mask[2] = 0x00;
2140 dis_deauth_mask[3] = 0xfc;
2141 }
2142
2143 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2144
2145 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2146 pattern_count, byte_cnt);
2147
2148 pattern_count++;
2149 /*
2150 * for de-authenticate pattern, only the first byte of the frame
2151 * control field gets changed from 0xA0 to 0xC0
2152 */
2153 dis_deauth_pattern[0] = 0xC0;
2154
2155 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2156 pattern_count, byte_cnt);
2157
2158 }
2159
2160 static void ath9k_wow_add_pattern(struct ath_softc *sc,
2161 struct cfg80211_wowlan *wowlan)
2162 {
2163 struct ath_hw *ah = sc->sc_ah;
2164 struct ath9k_wow_pattern *wow_pattern = NULL;
2165 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2166 int mask_len;
2167 s8 i = 0;
2168
2169 if (!wowlan->n_patterns)
2170 return;
2171
2172 /*
2173 * Add the new user configured patterns
2174 */
2175 for (i = 0; i < wowlan->n_patterns; i++) {
2176
2177 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2178
2179 if (!wow_pattern)
2180 return;
2181
2182 /*
2183 * TODO: convert the generic user space pattern to
2184 * appropriate chip specific/802.11 pattern.
2185 */
2186
2187 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2188 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2189 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2190 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2191 patterns[i].pattern_len);
2192 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2193 wow_pattern->pattern_len = patterns[i].pattern_len;
2194
2195 /*
2196 * just need to take care of deauth and disssoc pattern,
2197 * make sure we don't overwrite them.
2198 */
2199
2200 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2201 wow_pattern->mask_bytes,
2202 i + 2,
2203 wow_pattern->pattern_len);
2204 kfree(wow_pattern);
2205
2206 }
2207
2208 }
2209
2210 static int ath9k_suspend(struct ieee80211_hw *hw,
2211 struct cfg80211_wowlan *wowlan)
2212 {
2213 struct ath_softc *sc = hw->priv;
2214 struct ath_hw *ah = sc->sc_ah;
2215 struct ath_common *common = ath9k_hw_common(ah);
2216 u32 wow_triggers_enabled = 0;
2217 int ret = 0;
2218
2219 mutex_lock(&sc->mutex);
2220
2221 ath_cancel_work(sc);
2222 ath_stop_ani(sc);
2223 del_timer_sync(&sc->rx_poll_timer);
2224
2225 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2226 ath_dbg(common, ANY, "Device not present\n");
2227 ret = -EINVAL;
2228 goto fail_wow;
2229 }
2230
2231 if (WARN_ON(!wowlan)) {
2232 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2233 ret = -EINVAL;
2234 goto fail_wow;
2235 }
2236
2237 if (!device_can_wakeup(sc->dev)) {
2238 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2239 ret = 1;
2240 goto fail_wow;
2241 }
2242
2243 /*
2244 * none of the sta vifs are associated
2245 * and we are not currently handling multivif
2246 * cases, for instance we have to seperately
2247 * configure 'keep alive frame' for each
2248 * STA.
2249 */
2250
2251 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2252 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2253 ret = 1;
2254 goto fail_wow;
2255 }
2256
2257 if (sc->nvifs > 1) {
2258 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2259 ret = 1;
2260 goto fail_wow;
2261 }
2262
2263 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2264
2265 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2266 wow_triggers_enabled);
2267
2268 ath9k_ps_wakeup(sc);
2269
2270 ath9k_stop_btcoex(sc);
2271
2272 /*
2273 * Enable wake up on recieving disassoc/deauth
2274 * frame by default.
2275 */
2276 ath9k_wow_add_disassoc_deauth_pattern(sc);
2277
2278 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2279 ath9k_wow_add_pattern(sc, wowlan);
2280
2281 spin_lock_bh(&sc->sc_pcu_lock);
2282 /*
2283 * To avoid false wake, we enable beacon miss interrupt only
2284 * when we go to sleep. We save the current interrupt mask
2285 * so we can restore it after the system wakes up
2286 */
2287 sc->wow_intr_before_sleep = ah->imask;
2288 ah->imask &= ~ATH9K_INT_GLOBAL;
2289 ath9k_hw_disable_interrupts(ah);
2290 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2291 ath9k_hw_set_interrupts(ah);
2292 ath9k_hw_enable_interrupts(ah);
2293
2294 spin_unlock_bh(&sc->sc_pcu_lock);
2295
2296 /*
2297 * we can now sync irq and kill any running tasklets, since we already
2298 * disabled interrupts and not holding a spin lock
2299 */
2300 synchronize_irq(sc->irq);
2301 tasklet_kill(&sc->intr_tq);
2302
2303 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2304
2305 ath9k_ps_restore(sc);
2306 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2307 atomic_inc(&sc->wow_sleep_proc_intr);
2308
2309 fail_wow:
2310 mutex_unlock(&sc->mutex);
2311 return ret;
2312 }
2313
2314 static int ath9k_resume(struct ieee80211_hw *hw)
2315 {
2316 struct ath_softc *sc = hw->priv;
2317 struct ath_hw *ah = sc->sc_ah;
2318 struct ath_common *common = ath9k_hw_common(ah);
2319 u32 wow_status;
2320
2321 mutex_lock(&sc->mutex);
2322
2323 ath9k_ps_wakeup(sc);
2324
2325 spin_lock_bh(&sc->sc_pcu_lock);
2326
2327 ath9k_hw_disable_interrupts(ah);
2328 ah->imask = sc->wow_intr_before_sleep;
2329 ath9k_hw_set_interrupts(ah);
2330 ath9k_hw_enable_interrupts(ah);
2331
2332 spin_unlock_bh(&sc->sc_pcu_lock);
2333
2334 wow_status = ath9k_hw_wow_wakeup(ah);
2335
2336 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2337 /*
2338 * some devices may not pick beacon miss
2339 * as the reason they woke up so we add
2340 * that here for that shortcoming.
2341 */
2342 wow_status |= AH_WOW_BEACON_MISS;
2343 atomic_dec(&sc->wow_got_bmiss_intr);
2344 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2345 }
2346
2347 atomic_dec(&sc->wow_sleep_proc_intr);
2348
2349 if (wow_status) {
2350 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2351 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2352 }
2353
2354 ath_restart_work(sc);
2355 ath9k_start_btcoex(sc);
2356
2357 ath9k_ps_restore(sc);
2358 mutex_unlock(&sc->mutex);
2359
2360 return 0;
2361 }
2362
2363 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2364 {
2365 struct ath_softc *sc = hw->priv;
2366
2367 mutex_lock(&sc->mutex);
2368 device_init_wakeup(sc->dev, 1);
2369 device_set_wakeup_enable(sc->dev, enabled);
2370 mutex_unlock(&sc->mutex);
2371 }
2372
2373 #endif
2374
2375 struct ieee80211_ops ath9k_ops = {
2376 .tx = ath9k_tx,
2377 .start = ath9k_start,
2378 .stop = ath9k_stop,
2379 .add_interface = ath9k_add_interface,
2380 .change_interface = ath9k_change_interface,
2381 .remove_interface = ath9k_remove_interface,
2382 .config = ath9k_config,
2383 .configure_filter = ath9k_configure_filter,
2384 .sta_add = ath9k_sta_add,
2385 .sta_remove = ath9k_sta_remove,
2386 .sta_notify = ath9k_sta_notify,
2387 .conf_tx = ath9k_conf_tx,
2388 .bss_info_changed = ath9k_bss_info_changed,
2389 .set_key = ath9k_set_key,
2390 .get_tsf = ath9k_get_tsf,
2391 .set_tsf = ath9k_set_tsf,
2392 .reset_tsf = ath9k_reset_tsf,
2393 .ampdu_action = ath9k_ampdu_action,
2394 .get_survey = ath9k_get_survey,
2395 .rfkill_poll = ath9k_rfkill_poll_state,
2396 .set_coverage_class = ath9k_set_coverage_class,
2397 .flush = ath9k_flush,
2398 .tx_frames_pending = ath9k_tx_frames_pending,
2399 .tx_last_beacon = ath9k_tx_last_beacon,
2400 .get_stats = ath9k_get_stats,
2401 .set_antenna = ath9k_set_antenna,
2402 .get_antenna = ath9k_get_antenna,
2403
2404 #ifdef CONFIG_PM_SLEEP
2405 .suspend = ath9k_suspend,
2406 .resume = ath9k_resume,
2407 .set_wakeup = ath9k_set_wakeup,
2408 #endif
2409
2410 #ifdef CONFIG_ATH9K_DEBUGFS
2411 .get_et_sset_count = ath9k_get_et_sset_count,
2412 .get_et_stats = ath9k_get_et_stats,
2413 .get_et_strings = ath9k_get_et_strings,
2414 #endif
2415 };
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