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ath9k/ath9k_htc: Remove WME macros
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58 }
59
60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61 {
62 bool pending = false;
63
64 spin_lock_bh(&txq->axq_lock);
65
66 if (txq->axq_depth || !list_empty(&txq->axq_acq))
67 pending = true;
68
69 spin_unlock_bh(&txq->axq_lock);
70 return pending;
71 }
72
73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
74 {
75 unsigned long flags;
76 bool ret;
77
78 spin_lock_irqsave(&sc->sc_pm_lock, flags);
79 ret = ath9k_hw_setpower(sc->sc_ah, mode);
80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
81
82 return ret;
83 }
84
85 void ath9k_ps_wakeup(struct ath_softc *sc)
86 {
87 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
88 unsigned long flags;
89 enum ath9k_power_mode power_mode;
90
91 spin_lock_irqsave(&sc->sc_pm_lock, flags);
92 if (++sc->ps_usecount != 1)
93 goto unlock;
94
95 power_mode = sc->sc_ah->power_mode;
96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
97
98 /*
99 * While the hardware is asleep, the cycle counters contain no
100 * useful data. Better clear them now so that they don't mess up
101 * survey data results.
102 */
103 if (power_mode != ATH9K_PM_AWAKE) {
104 spin_lock(&common->cc_lock);
105 ath_hw_cycle_counters_update(common);
106 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
107 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
108 spin_unlock(&common->cc_lock);
109 }
110
111 unlock:
112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
113 }
114
115 void ath9k_ps_restore(struct ath_softc *sc)
116 {
117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
118 enum ath9k_power_mode mode;
119 unsigned long flags;
120 bool reset;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (--sc->ps_usecount != 0)
124 goto unlock;
125
126 if (sc->ps_idle) {
127 ath9k_hw_setrxabort(sc->sc_ah, 1);
128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
129 mode = ATH9K_PM_FULL_SLEEP;
130 } else if (sc->ps_enabled &&
131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
132 PS_WAIT_FOR_CAB |
133 PS_WAIT_FOR_PSPOLL_DATA |
134 PS_WAIT_FOR_TX_ACK |
135 PS_WAIT_FOR_ANI))) {
136 mode = ATH9K_PM_NETWORK_SLEEP;
137 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
138 ath9k_btcoex_stop_gen_timer(sc);
139 } else {
140 goto unlock;
141 }
142
143 spin_lock(&common->cc_lock);
144 ath_hw_cycle_counters_update(common);
145 spin_unlock(&common->cc_lock);
146
147 ath9k_hw_setpower(sc->sc_ah, mode);
148
149 unlock:
150 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
151 }
152
153 static void __ath_cancel_work(struct ath_softc *sc)
154 {
155 cancel_work_sync(&sc->paprd_work);
156 cancel_work_sync(&sc->hw_check_work);
157 cancel_delayed_work_sync(&sc->tx_complete_work);
158 cancel_delayed_work_sync(&sc->hw_pll_work);
159
160 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
161 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
162 cancel_work_sync(&sc->mci_work);
163 #endif
164 }
165
166 static void ath_cancel_work(struct ath_softc *sc)
167 {
168 __ath_cancel_work(sc);
169 cancel_work_sync(&sc->hw_reset_work);
170 }
171
172 static void ath_restart_work(struct ath_softc *sc)
173 {
174 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
175
176 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
177 AR_SREV_9550(sc->sc_ah))
178 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
179 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
180
181 ath_start_rx_poll(sc, 3);
182 ath_start_ani(sc);
183 }
184
185 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
186 {
187 struct ath_hw *ah = sc->sc_ah;
188 bool ret = true;
189
190 ieee80211_stop_queues(sc->hw);
191
192 sc->hw_busy_count = 0;
193 ath_stop_ani(sc);
194 del_timer_sync(&sc->rx_poll_timer);
195
196 ath9k_debug_samp_bb_mac(sc);
197 ath9k_hw_disable_interrupts(ah);
198
199 if (!ath_stoprecv(sc))
200 ret = false;
201
202 if (!ath_drain_all_txq(sc, retry_tx))
203 ret = false;
204
205 if (!flush) {
206 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
207 ath_rx_tasklet(sc, 1, true);
208 ath_rx_tasklet(sc, 1, false);
209 } else {
210 ath_flushrecv(sc);
211 }
212
213 return ret;
214 }
215
216 static bool ath_complete_reset(struct ath_softc *sc, bool start)
217 {
218 struct ath_hw *ah = sc->sc_ah;
219 struct ath_common *common = ath9k_hw_common(ah);
220 unsigned long flags;
221
222 if (ath_startrecv(sc) != 0) {
223 ath_err(common, "Unable to restart recv logic\n");
224 return false;
225 }
226
227 ath9k_cmn_update_txpow(ah, sc->curtxpow,
228 sc->config.txpowlimit, &sc->curtxpow);
229
230 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
231 ath9k_hw_set_interrupts(ah);
232 ath9k_hw_enable_interrupts(ah);
233
234 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
235 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
236 goto work;
237
238 ath9k_set_beacon(sc);
239
240 if (ah->opmode == NL80211_IFTYPE_STATION &&
241 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
242 spin_lock_irqsave(&sc->sc_pm_lock, flags);
243 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
244 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
245 }
246 work:
247 ath_restart_work(sc);
248 }
249
250 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
251 ath_ant_comb_update(sc);
252
253 ieee80211_wake_queues(sc->hw);
254
255 return true;
256 }
257
258 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
259 bool retry_tx)
260 {
261 struct ath_hw *ah = sc->sc_ah;
262 struct ath_common *common = ath9k_hw_common(ah);
263 struct ath9k_hw_cal_data *caldata = NULL;
264 bool fastcc = true;
265 bool flush = false;
266 int r;
267
268 __ath_cancel_work(sc);
269
270 spin_lock_bh(&sc->sc_pcu_lock);
271
272 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
273 fastcc = false;
274 caldata = &sc->caldata;
275 }
276
277 if (!hchan) {
278 fastcc = false;
279 flush = true;
280 hchan = ah->curchan;
281 }
282
283 if (!ath_prepare_reset(sc, retry_tx, flush))
284 fastcc = false;
285
286 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
287 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
288
289 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
290 if (r) {
291 ath_err(common,
292 "Unable to reset channel, reset status %d\n", r);
293 goto out;
294 }
295
296 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
297 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
298 ath9k_mci_set_txpower(sc, true, false);
299
300 if (!ath_complete_reset(sc, true))
301 r = -EIO;
302
303 out:
304 spin_unlock_bh(&sc->sc_pcu_lock);
305 return r;
306 }
307
308
309 /*
310 * Set/change channels. If the channel is really being changed, it's done
311 * by reseting the chip. To accomplish this we must first cleanup any pending
312 * DMA, then restart stuff.
313 */
314 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
315 struct ath9k_channel *hchan)
316 {
317 int r;
318
319 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
320 return -EIO;
321
322 r = ath_reset_internal(sc, hchan, false);
323
324 return r;
325 }
326
327 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
328 struct ieee80211_vif *vif)
329 {
330 struct ath_node *an;
331 u8 density;
332 an = (struct ath_node *)sta->drv_priv;
333
334 #ifdef CONFIG_ATH9K_DEBUGFS
335 spin_lock(&sc->nodes_lock);
336 list_add(&an->list, &sc->nodes);
337 spin_unlock(&sc->nodes_lock);
338 #endif
339 an->sta = sta;
340 an->vif = vif;
341
342 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
343 ath_tx_node_init(sc, an);
344 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
345 sta->ht_cap.ampdu_factor);
346 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
347 an->mpdudensity = density;
348 }
349 }
350
351 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
352 {
353 struct ath_node *an = (struct ath_node *)sta->drv_priv;
354
355 #ifdef CONFIG_ATH9K_DEBUGFS
356 spin_lock(&sc->nodes_lock);
357 list_del(&an->list);
358 spin_unlock(&sc->nodes_lock);
359 an->sta = NULL;
360 #endif
361
362 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
363 ath_tx_node_cleanup(sc, an);
364 }
365
366 void ath9k_tasklet(unsigned long data)
367 {
368 struct ath_softc *sc = (struct ath_softc *)data;
369 struct ath_hw *ah = sc->sc_ah;
370 struct ath_common *common = ath9k_hw_common(ah);
371 enum ath_reset_type type;
372 unsigned long flags;
373 u32 status = sc->intrstatus;
374 u32 rxmask;
375
376 ath9k_ps_wakeup(sc);
377 spin_lock(&sc->sc_pcu_lock);
378
379 if ((status & ATH9K_INT_FATAL) ||
380 (status & ATH9K_INT_BB_WATCHDOG)) {
381
382 if (status & ATH9K_INT_FATAL)
383 type = RESET_TYPE_FATAL_INT;
384 else
385 type = RESET_TYPE_BB_WATCHDOG;
386
387 ath9k_queue_reset(sc, type);
388 goto out;
389 }
390
391 spin_lock_irqsave(&sc->sc_pm_lock, flags);
392 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
393 /*
394 * TSF sync does not look correct; remain awake to sync with
395 * the next Beacon.
396 */
397 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
398 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
399 }
400 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
401
402 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
403 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
404 ATH9K_INT_RXORN);
405 else
406 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
407
408 if (status & rxmask) {
409 /* Check for high priority Rx first */
410 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
411 (status & ATH9K_INT_RXHP))
412 ath_rx_tasklet(sc, 0, true);
413
414 ath_rx_tasklet(sc, 0, false);
415 }
416
417 if (status & ATH9K_INT_TX) {
418 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
419 ath_tx_edma_tasklet(sc);
420 else
421 ath_tx_tasklet(sc);
422 }
423
424 ath9k_btcoex_handle_interrupt(sc, status);
425
426 out:
427 /* re-enable hardware interrupt */
428 ath9k_hw_enable_interrupts(ah);
429
430 spin_unlock(&sc->sc_pcu_lock);
431 ath9k_ps_restore(sc);
432 }
433
434 irqreturn_t ath_isr(int irq, void *dev)
435 {
436 #define SCHED_INTR ( \
437 ATH9K_INT_FATAL | \
438 ATH9K_INT_BB_WATCHDOG | \
439 ATH9K_INT_RXORN | \
440 ATH9K_INT_RXEOL | \
441 ATH9K_INT_RX | \
442 ATH9K_INT_RXLP | \
443 ATH9K_INT_RXHP | \
444 ATH9K_INT_TX | \
445 ATH9K_INT_BMISS | \
446 ATH9K_INT_CST | \
447 ATH9K_INT_TSFOOR | \
448 ATH9K_INT_GENTIMER | \
449 ATH9K_INT_MCI)
450
451 struct ath_softc *sc = dev;
452 struct ath_hw *ah = sc->sc_ah;
453 struct ath_common *common = ath9k_hw_common(ah);
454 enum ath9k_int status;
455 bool sched = false;
456
457 /*
458 * The hardware is not ready/present, don't
459 * touch anything. Note this can happen early
460 * on if the IRQ is shared.
461 */
462 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
463 return IRQ_NONE;
464
465 /* shared irq, not for us */
466
467 if (!ath9k_hw_intrpend(ah))
468 return IRQ_NONE;
469
470 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
471 ath9k_hw_kill_interrupts(ah);
472 return IRQ_HANDLED;
473 }
474
475 /*
476 * Figure out the reason(s) for the interrupt. Note
477 * that the hal returns a pseudo-ISR that may include
478 * bits we haven't explicitly enabled so we mask the
479 * value to insure we only process bits we requested.
480 */
481 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
482 status &= ah->imask; /* discard unasked-for bits */
483
484 /*
485 * If there are no status bits set, then this interrupt was not
486 * for me (should have been caught above).
487 */
488 if (!status)
489 return IRQ_NONE;
490
491 /* Cache the status */
492 sc->intrstatus = status;
493
494 if (status & SCHED_INTR)
495 sched = true;
496
497 /*
498 * If a FATAL or RXORN interrupt is received, we have to reset the
499 * chip immediately.
500 */
501 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
502 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
503 goto chip_reset;
504
505 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
506 (status & ATH9K_INT_BB_WATCHDOG)) {
507
508 spin_lock(&common->cc_lock);
509 ath_hw_cycle_counters_update(common);
510 ar9003_hw_bb_watchdog_dbg_info(ah);
511 spin_unlock(&common->cc_lock);
512
513 goto chip_reset;
514 }
515 #ifdef CONFIG_PM_SLEEP
516 if (status & ATH9K_INT_BMISS) {
517 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
518 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
519 atomic_inc(&sc->wow_got_bmiss_intr);
520 atomic_dec(&sc->wow_sleep_proc_intr);
521 }
522 }
523 #endif
524 if (status & ATH9K_INT_SWBA)
525 tasklet_schedule(&sc->bcon_tasklet);
526
527 if (status & ATH9K_INT_TXURN)
528 ath9k_hw_updatetxtriglevel(ah, true);
529
530 if (status & ATH9K_INT_RXEOL) {
531 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
532 ath9k_hw_set_interrupts(ah);
533 }
534
535 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
536 if (status & ATH9K_INT_TIM_TIMER) {
537 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
538 goto chip_reset;
539 /* Clear RxAbort bit so that we can
540 * receive frames */
541 ath9k_setpower(sc, ATH9K_PM_AWAKE);
542 spin_lock(&sc->sc_pm_lock);
543 ath9k_hw_setrxabort(sc->sc_ah, 0);
544 sc->ps_flags |= PS_WAIT_FOR_BEACON;
545 spin_unlock(&sc->sc_pm_lock);
546 }
547
548 chip_reset:
549
550 ath_debug_stat_interrupt(sc, status);
551
552 if (sched) {
553 /* turn off every interrupt */
554 ath9k_hw_disable_interrupts(ah);
555 tasklet_schedule(&sc->intr_tq);
556 }
557
558 return IRQ_HANDLED;
559
560 #undef SCHED_INTR
561 }
562
563 static int ath_reset(struct ath_softc *sc, bool retry_tx)
564 {
565 int r;
566
567 ath9k_ps_wakeup(sc);
568
569 r = ath_reset_internal(sc, NULL, retry_tx);
570
571 if (retry_tx) {
572 int i;
573 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
574 if (ATH_TXQ_SETUP(sc, i)) {
575 spin_lock_bh(&sc->tx.txq[i].axq_lock);
576 ath_txq_schedule(sc, &sc->tx.txq[i]);
577 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
578 }
579 }
580 }
581
582 ath9k_ps_restore(sc);
583
584 return r;
585 }
586
587 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
588 {
589 #ifdef CONFIG_ATH9K_DEBUGFS
590 RESET_STAT_INC(sc, type);
591 #endif
592 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
593 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
594 }
595
596 void ath_reset_work(struct work_struct *work)
597 {
598 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
599
600 ath_reset(sc, true);
601 }
602
603 /**********************/
604 /* mac80211 callbacks */
605 /**********************/
606
607 static int ath9k_start(struct ieee80211_hw *hw)
608 {
609 struct ath_softc *sc = hw->priv;
610 struct ath_hw *ah = sc->sc_ah;
611 struct ath_common *common = ath9k_hw_common(ah);
612 struct ieee80211_channel *curchan = hw->conf.channel;
613 struct ath9k_channel *init_channel;
614 int r;
615
616 ath_dbg(common, CONFIG,
617 "Starting driver with initial channel: %d MHz\n",
618 curchan->center_freq);
619
620 ath9k_ps_wakeup(sc);
621 mutex_lock(&sc->mutex);
622
623 init_channel = ath9k_cmn_get_curchannel(hw, ah);
624
625 /* Reset SERDES registers */
626 ath9k_hw_configpcipowersave(ah, false);
627
628 /*
629 * The basic interface to setting the hardware in a good
630 * state is ``reset''. On return the hardware is known to
631 * be powered up and with interrupts disabled. This must
632 * be followed by initialization of the appropriate bits
633 * and then setup of the interrupt mask.
634 */
635 spin_lock_bh(&sc->sc_pcu_lock);
636
637 atomic_set(&ah->intr_ref_cnt, -1);
638
639 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
640 if (r) {
641 ath_err(common,
642 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
643 r, curchan->center_freq);
644 ah->reset_power_on = false;
645 }
646
647 /* Setup our intr mask. */
648 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
649 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
650 ATH9K_INT_GLOBAL;
651
652 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
653 ah->imask |= ATH9K_INT_RXHP |
654 ATH9K_INT_RXLP |
655 ATH9K_INT_BB_WATCHDOG;
656 else
657 ah->imask |= ATH9K_INT_RX;
658
659 ah->imask |= ATH9K_INT_GTT;
660
661 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
662 ah->imask |= ATH9K_INT_CST;
663
664 ath_mci_enable(sc);
665
666 clear_bit(SC_OP_INVALID, &sc->sc_flags);
667 sc->sc_ah->is_monitoring = false;
668
669 if (!ath_complete_reset(sc, false))
670 ah->reset_power_on = false;
671
672 if (ah->led_pin >= 0) {
673 ath9k_hw_cfg_output(ah, ah->led_pin,
674 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
675 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
676 }
677
678 /*
679 * Reset key cache to sane defaults (all entries cleared) instead of
680 * semi-random values after suspend/resume.
681 */
682 ath9k_cmn_init_crypto(sc->sc_ah);
683
684 spin_unlock_bh(&sc->sc_pcu_lock);
685
686 mutex_unlock(&sc->mutex);
687
688 ath9k_ps_restore(sc);
689
690 return 0;
691 }
692
693 static void ath9k_tx(struct ieee80211_hw *hw,
694 struct ieee80211_tx_control *control,
695 struct sk_buff *skb)
696 {
697 struct ath_softc *sc = hw->priv;
698 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
699 struct ath_tx_control txctl;
700 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
701 unsigned long flags;
702
703 if (sc->ps_enabled) {
704 /*
705 * mac80211 does not set PM field for normal data frames, so we
706 * need to update that based on the current PS mode.
707 */
708 if (ieee80211_is_data(hdr->frame_control) &&
709 !ieee80211_is_nullfunc(hdr->frame_control) &&
710 !ieee80211_has_pm(hdr->frame_control)) {
711 ath_dbg(common, PS,
712 "Add PM=1 for a TX frame while in PS mode\n");
713 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
714 }
715 }
716
717 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
718 /*
719 * We are using PS-Poll and mac80211 can request TX while in
720 * power save mode. Need to wake up hardware for the TX to be
721 * completed and if needed, also for RX of buffered frames.
722 */
723 ath9k_ps_wakeup(sc);
724 spin_lock_irqsave(&sc->sc_pm_lock, flags);
725 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
726 ath9k_hw_setrxabort(sc->sc_ah, 0);
727 if (ieee80211_is_pspoll(hdr->frame_control)) {
728 ath_dbg(common, PS,
729 "Sending PS-Poll to pick a buffered frame\n");
730 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
731 } else {
732 ath_dbg(common, PS, "Wake up to complete TX\n");
733 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
734 }
735 /*
736 * The actual restore operation will happen only after
737 * the ps_flags bit is cleared. We are just dropping
738 * the ps_usecount here.
739 */
740 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
741 ath9k_ps_restore(sc);
742 }
743
744 /*
745 * Cannot tx while the hardware is in full sleep, it first needs a full
746 * chip reset to recover from that
747 */
748 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
749 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
750 goto exit;
751 }
752
753 memset(&txctl, 0, sizeof(struct ath_tx_control));
754 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
755 txctl.sta = control->sta;
756
757 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
758
759 if (ath_tx_start(hw, skb, &txctl) != 0) {
760 ath_dbg(common, XMIT, "TX failed\n");
761 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
762 goto exit;
763 }
764
765 return;
766 exit:
767 ieee80211_free_txskb(hw, skb);
768 }
769
770 static void ath9k_stop(struct ieee80211_hw *hw)
771 {
772 struct ath_softc *sc = hw->priv;
773 struct ath_hw *ah = sc->sc_ah;
774 struct ath_common *common = ath9k_hw_common(ah);
775 bool prev_idle;
776
777 mutex_lock(&sc->mutex);
778
779 ath_cancel_work(sc);
780 del_timer_sync(&sc->rx_poll_timer);
781
782 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
783 ath_dbg(common, ANY, "Device not present\n");
784 mutex_unlock(&sc->mutex);
785 return;
786 }
787
788 /* Ensure HW is awake when we try to shut it down. */
789 ath9k_ps_wakeup(sc);
790
791 spin_lock_bh(&sc->sc_pcu_lock);
792
793 /* prevent tasklets to enable interrupts once we disable them */
794 ah->imask &= ~ATH9K_INT_GLOBAL;
795
796 /* make sure h/w will not generate any interrupt
797 * before setting the invalid flag. */
798 ath9k_hw_disable_interrupts(ah);
799
800 spin_unlock_bh(&sc->sc_pcu_lock);
801
802 /* we can now sync irq and kill any running tasklets, since we already
803 * disabled interrupts and not holding a spin lock */
804 synchronize_irq(sc->irq);
805 tasklet_kill(&sc->intr_tq);
806 tasklet_kill(&sc->bcon_tasklet);
807
808 prev_idle = sc->ps_idle;
809 sc->ps_idle = true;
810
811 spin_lock_bh(&sc->sc_pcu_lock);
812
813 if (ah->led_pin >= 0) {
814 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
815 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
816 }
817
818 ath_prepare_reset(sc, false, true);
819
820 if (sc->rx.frag) {
821 dev_kfree_skb_any(sc->rx.frag);
822 sc->rx.frag = NULL;
823 }
824
825 if (!ah->curchan)
826 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
827
828 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
829 ath9k_hw_phy_disable(ah);
830
831 ath9k_hw_configpcipowersave(ah, true);
832
833 spin_unlock_bh(&sc->sc_pcu_lock);
834
835 ath9k_ps_restore(sc);
836
837 set_bit(SC_OP_INVALID, &sc->sc_flags);
838 sc->ps_idle = prev_idle;
839
840 mutex_unlock(&sc->mutex);
841
842 ath_dbg(common, CONFIG, "Driver halt\n");
843 }
844
845 bool ath9k_uses_beacons(int type)
846 {
847 switch (type) {
848 case NL80211_IFTYPE_AP:
849 case NL80211_IFTYPE_ADHOC:
850 case NL80211_IFTYPE_MESH_POINT:
851 return true;
852 default:
853 return false;
854 }
855 }
856
857 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
858 {
859 struct ath9k_vif_iter_data *iter_data = data;
860 int i;
861
862 if (iter_data->hw_macaddr)
863 for (i = 0; i < ETH_ALEN; i++)
864 iter_data->mask[i] &=
865 ~(iter_data->hw_macaddr[i] ^ mac[i]);
866
867 switch (vif->type) {
868 case NL80211_IFTYPE_AP:
869 iter_data->naps++;
870 break;
871 case NL80211_IFTYPE_STATION:
872 iter_data->nstations++;
873 break;
874 case NL80211_IFTYPE_ADHOC:
875 iter_data->nadhocs++;
876 break;
877 case NL80211_IFTYPE_MESH_POINT:
878 iter_data->nmeshes++;
879 break;
880 case NL80211_IFTYPE_WDS:
881 iter_data->nwds++;
882 break;
883 default:
884 break;
885 }
886 }
887
888 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
889 {
890 struct ath_softc *sc = data;
891 struct ath_vif *avp = (void *)vif->drv_priv;
892
893 if (vif->type != NL80211_IFTYPE_STATION)
894 return;
895
896 if (avp->primary_sta_vif)
897 ath9k_set_assoc_state(sc, vif);
898 }
899
900 /* Called with sc->mutex held. */
901 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
902 struct ieee80211_vif *vif,
903 struct ath9k_vif_iter_data *iter_data)
904 {
905 struct ath_softc *sc = hw->priv;
906 struct ath_hw *ah = sc->sc_ah;
907 struct ath_common *common = ath9k_hw_common(ah);
908
909 /*
910 * Use the hardware MAC address as reference, the hardware uses it
911 * together with the BSSID mask when matching addresses.
912 */
913 memset(iter_data, 0, sizeof(*iter_data));
914 iter_data->hw_macaddr = common->macaddr;
915 memset(&iter_data->mask, 0xff, ETH_ALEN);
916
917 if (vif)
918 ath9k_vif_iter(iter_data, vif->addr, vif);
919
920 /* Get list of all active MAC addresses */
921 ieee80211_iterate_active_interfaces_atomic(
922 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
923 ath9k_vif_iter, iter_data);
924 }
925
926 /* Called with sc->mutex held. */
927 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
928 struct ieee80211_vif *vif)
929 {
930 struct ath_softc *sc = hw->priv;
931 struct ath_hw *ah = sc->sc_ah;
932 struct ath_common *common = ath9k_hw_common(ah);
933 struct ath9k_vif_iter_data iter_data;
934 enum nl80211_iftype old_opmode = ah->opmode;
935
936 ath9k_calculate_iter_data(hw, vif, &iter_data);
937
938 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
939 ath_hw_setbssidmask(common);
940
941 if (iter_data.naps > 0) {
942 ath9k_hw_set_tsfadjust(ah, true);
943 ah->opmode = NL80211_IFTYPE_AP;
944 } else {
945 ath9k_hw_set_tsfadjust(ah, false);
946
947 if (iter_data.nmeshes)
948 ah->opmode = NL80211_IFTYPE_MESH_POINT;
949 else if (iter_data.nwds)
950 ah->opmode = NL80211_IFTYPE_AP;
951 else if (iter_data.nadhocs)
952 ah->opmode = NL80211_IFTYPE_ADHOC;
953 else
954 ah->opmode = NL80211_IFTYPE_STATION;
955 }
956
957 ath9k_hw_setopmode(ah);
958
959 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
960 ah->imask |= ATH9K_INT_TSFOOR;
961 else
962 ah->imask &= ~ATH9K_INT_TSFOOR;
963
964 ath9k_hw_set_interrupts(ah);
965
966 /*
967 * If we are changing the opmode to STATION,
968 * a beacon sync needs to be done.
969 */
970 if (ah->opmode == NL80211_IFTYPE_STATION &&
971 old_opmode == NL80211_IFTYPE_AP &&
972 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
973 ieee80211_iterate_active_interfaces_atomic(
974 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
975 ath9k_sta_vif_iter, sc);
976 }
977 }
978
979 static int ath9k_add_interface(struct ieee80211_hw *hw,
980 struct ieee80211_vif *vif)
981 {
982 struct ath_softc *sc = hw->priv;
983 struct ath_hw *ah = sc->sc_ah;
984 struct ath_common *common = ath9k_hw_common(ah);
985
986 mutex_lock(&sc->mutex);
987
988 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
989 sc->nvifs++;
990
991 ath9k_ps_wakeup(sc);
992 ath9k_calculate_summary_state(hw, vif);
993 ath9k_ps_restore(sc);
994
995 if (ath9k_uses_beacons(vif->type))
996 ath9k_beacon_assign_slot(sc, vif);
997
998 mutex_unlock(&sc->mutex);
999 return 0;
1000 }
1001
1002 static int ath9k_change_interface(struct ieee80211_hw *hw,
1003 struct ieee80211_vif *vif,
1004 enum nl80211_iftype new_type,
1005 bool p2p)
1006 {
1007 struct ath_softc *sc = hw->priv;
1008 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1009
1010 ath_dbg(common, CONFIG, "Change Interface\n");
1011 mutex_lock(&sc->mutex);
1012
1013 if (ath9k_uses_beacons(vif->type))
1014 ath9k_beacon_remove_slot(sc, vif);
1015
1016 vif->type = new_type;
1017 vif->p2p = p2p;
1018
1019 ath9k_ps_wakeup(sc);
1020 ath9k_calculate_summary_state(hw, vif);
1021 ath9k_ps_restore(sc);
1022
1023 if (ath9k_uses_beacons(vif->type))
1024 ath9k_beacon_assign_slot(sc, vif);
1025
1026 mutex_unlock(&sc->mutex);
1027 return 0;
1028 }
1029
1030 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1031 struct ieee80211_vif *vif)
1032 {
1033 struct ath_softc *sc = hw->priv;
1034 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1035
1036 ath_dbg(common, CONFIG, "Detach Interface\n");
1037
1038 mutex_lock(&sc->mutex);
1039
1040 sc->nvifs--;
1041
1042 if (ath9k_uses_beacons(vif->type))
1043 ath9k_beacon_remove_slot(sc, vif);
1044
1045 ath9k_ps_wakeup(sc);
1046 ath9k_calculate_summary_state(hw, NULL);
1047 ath9k_ps_restore(sc);
1048
1049 mutex_unlock(&sc->mutex);
1050 }
1051
1052 static void ath9k_enable_ps(struct ath_softc *sc)
1053 {
1054 struct ath_hw *ah = sc->sc_ah;
1055 struct ath_common *common = ath9k_hw_common(ah);
1056
1057 sc->ps_enabled = true;
1058 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1059 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1060 ah->imask |= ATH9K_INT_TIM_TIMER;
1061 ath9k_hw_set_interrupts(ah);
1062 }
1063 ath9k_hw_setrxabort(ah, 1);
1064 }
1065 ath_dbg(common, PS, "PowerSave enabled\n");
1066 }
1067
1068 static void ath9k_disable_ps(struct ath_softc *sc)
1069 {
1070 struct ath_hw *ah = sc->sc_ah;
1071 struct ath_common *common = ath9k_hw_common(ah);
1072
1073 sc->ps_enabled = false;
1074 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1075 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1076 ath9k_hw_setrxabort(ah, 0);
1077 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1078 PS_WAIT_FOR_CAB |
1079 PS_WAIT_FOR_PSPOLL_DATA |
1080 PS_WAIT_FOR_TX_ACK);
1081 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1082 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1083 ath9k_hw_set_interrupts(ah);
1084 }
1085 }
1086 ath_dbg(common, PS, "PowerSave disabled\n");
1087 }
1088
1089 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1090 {
1091 struct ath_softc *sc = hw->priv;
1092 struct ath_hw *ah = sc->sc_ah;
1093 struct ath_common *common = ath9k_hw_common(ah);
1094 struct ieee80211_conf *conf = &hw->conf;
1095 bool reset_channel = false;
1096
1097 ath9k_ps_wakeup(sc);
1098 mutex_lock(&sc->mutex);
1099
1100 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1101 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1102 if (sc->ps_idle) {
1103 ath_cancel_work(sc);
1104 ath9k_stop_btcoex(sc);
1105 } else {
1106 ath9k_start_btcoex(sc);
1107 /*
1108 * The chip needs a reset to properly wake up from
1109 * full sleep
1110 */
1111 reset_channel = ah->chip_fullsleep;
1112 }
1113 }
1114
1115 /*
1116 * We just prepare to enable PS. We have to wait until our AP has
1117 * ACK'd our null data frame to disable RX otherwise we'll ignore
1118 * those ACKs and end up retransmitting the same null data frames.
1119 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1120 */
1121 if (changed & IEEE80211_CONF_CHANGE_PS) {
1122 unsigned long flags;
1123 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1124 if (conf->flags & IEEE80211_CONF_PS)
1125 ath9k_enable_ps(sc);
1126 else
1127 ath9k_disable_ps(sc);
1128 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1129 }
1130
1131 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1132 if (conf->flags & IEEE80211_CONF_MONITOR) {
1133 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1134 sc->sc_ah->is_monitoring = true;
1135 } else {
1136 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1137 sc->sc_ah->is_monitoring = false;
1138 }
1139 }
1140
1141 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
1142 struct ieee80211_channel *curchan = hw->conf.channel;
1143 int pos = curchan->hw_value;
1144 int old_pos = -1;
1145 unsigned long flags;
1146
1147 if (ah->curchan)
1148 old_pos = ah->curchan - &ah->channels[0];
1149
1150 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
1151 curchan->center_freq, conf->channel_type);
1152
1153 /* update survey stats for the old channel before switching */
1154 spin_lock_irqsave(&common->cc_lock, flags);
1155 ath_update_survey_stats(sc);
1156 spin_unlock_irqrestore(&common->cc_lock, flags);
1157
1158 /*
1159 * Preserve the current channel values, before updating
1160 * the same channel
1161 */
1162 if (ah->curchan && (old_pos == pos))
1163 ath9k_hw_getnf(ah, ah->curchan);
1164
1165 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1166 curchan, conf->channel_type);
1167
1168 /*
1169 * If the operating channel changes, change the survey in-use flags
1170 * along with it.
1171 * Reset the survey data for the new channel, unless we're switching
1172 * back to the operating channel from an off-channel operation.
1173 */
1174 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1175 sc->cur_survey != &sc->survey[pos]) {
1176
1177 if (sc->cur_survey)
1178 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1179
1180 sc->cur_survey = &sc->survey[pos];
1181
1182 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1183 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1184 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1185 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1186 }
1187
1188 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1189 ath_err(common, "Unable to set channel\n");
1190 mutex_unlock(&sc->mutex);
1191 ath9k_ps_restore(sc);
1192 return -EINVAL;
1193 }
1194
1195 /*
1196 * The most recent snapshot of channel->noisefloor for the old
1197 * channel is only available after the hardware reset. Copy it to
1198 * the survey stats now.
1199 */
1200 if (old_pos >= 0)
1201 ath_update_survey_nf(sc, old_pos);
1202 }
1203
1204 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1205 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1206 sc->config.txpowlimit = 2 * conf->power_level;
1207 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1208 sc->config.txpowlimit, &sc->curtxpow);
1209 }
1210
1211 mutex_unlock(&sc->mutex);
1212 ath9k_ps_restore(sc);
1213
1214 return 0;
1215 }
1216
1217 #define SUPPORTED_FILTERS \
1218 (FIF_PROMISC_IN_BSS | \
1219 FIF_ALLMULTI | \
1220 FIF_CONTROL | \
1221 FIF_PSPOLL | \
1222 FIF_OTHER_BSS | \
1223 FIF_BCN_PRBRESP_PROMISC | \
1224 FIF_PROBE_REQ | \
1225 FIF_FCSFAIL)
1226
1227 /* FIXME: sc->sc_full_reset ? */
1228 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1229 unsigned int changed_flags,
1230 unsigned int *total_flags,
1231 u64 multicast)
1232 {
1233 struct ath_softc *sc = hw->priv;
1234 u32 rfilt;
1235
1236 changed_flags &= SUPPORTED_FILTERS;
1237 *total_flags &= SUPPORTED_FILTERS;
1238
1239 sc->rx.rxfilter = *total_flags;
1240 ath9k_ps_wakeup(sc);
1241 rfilt = ath_calcrxfilter(sc);
1242 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1243 ath9k_ps_restore(sc);
1244
1245 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1246 rfilt);
1247 }
1248
1249 static int ath9k_sta_add(struct ieee80211_hw *hw,
1250 struct ieee80211_vif *vif,
1251 struct ieee80211_sta *sta)
1252 {
1253 struct ath_softc *sc = hw->priv;
1254 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1255 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1256 struct ieee80211_key_conf ps_key = { };
1257
1258 ath_node_attach(sc, sta, vif);
1259
1260 if (vif->type != NL80211_IFTYPE_AP &&
1261 vif->type != NL80211_IFTYPE_AP_VLAN)
1262 return 0;
1263
1264 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
1265
1266 return 0;
1267 }
1268
1269 static void ath9k_del_ps_key(struct ath_softc *sc,
1270 struct ieee80211_vif *vif,
1271 struct ieee80211_sta *sta)
1272 {
1273 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1274 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1275 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1276
1277 if (!an->ps_key)
1278 return;
1279
1280 ath_key_delete(common, &ps_key);
1281 }
1282
1283 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1284 struct ieee80211_vif *vif,
1285 struct ieee80211_sta *sta)
1286 {
1287 struct ath_softc *sc = hw->priv;
1288
1289 ath9k_del_ps_key(sc, vif, sta);
1290 ath_node_detach(sc, sta);
1291
1292 return 0;
1293 }
1294
1295 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1296 struct ieee80211_vif *vif,
1297 enum sta_notify_cmd cmd,
1298 struct ieee80211_sta *sta)
1299 {
1300 struct ath_softc *sc = hw->priv;
1301 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1302
1303 if (!sta->ht_cap.ht_supported)
1304 return;
1305
1306 switch (cmd) {
1307 case STA_NOTIFY_SLEEP:
1308 an->sleeping = true;
1309 ath_tx_aggr_sleep(sta, sc, an);
1310 break;
1311 case STA_NOTIFY_AWAKE:
1312 an->sleeping = false;
1313 ath_tx_aggr_wakeup(sc, an);
1314 break;
1315 }
1316 }
1317
1318 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1319 struct ieee80211_vif *vif, u16 queue,
1320 const struct ieee80211_tx_queue_params *params)
1321 {
1322 struct ath_softc *sc = hw->priv;
1323 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1324 struct ath_txq *txq;
1325 struct ath9k_tx_queue_info qi;
1326 int ret = 0;
1327
1328 if (queue >= IEEE80211_NUM_ACS)
1329 return 0;
1330
1331 txq = sc->tx.txq_map[queue];
1332
1333 ath9k_ps_wakeup(sc);
1334 mutex_lock(&sc->mutex);
1335
1336 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1337
1338 qi.tqi_aifs = params->aifs;
1339 qi.tqi_cwmin = params->cw_min;
1340 qi.tqi_cwmax = params->cw_max;
1341 qi.tqi_burstTime = params->txop * 32;
1342
1343 ath_dbg(common, CONFIG,
1344 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1345 queue, txq->axq_qnum, params->aifs, params->cw_min,
1346 params->cw_max, params->txop);
1347
1348 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1349 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1350 if (ret)
1351 ath_err(common, "TXQ Update failed\n");
1352
1353 mutex_unlock(&sc->mutex);
1354 ath9k_ps_restore(sc);
1355
1356 return ret;
1357 }
1358
1359 static int ath9k_set_key(struct ieee80211_hw *hw,
1360 enum set_key_cmd cmd,
1361 struct ieee80211_vif *vif,
1362 struct ieee80211_sta *sta,
1363 struct ieee80211_key_conf *key)
1364 {
1365 struct ath_softc *sc = hw->priv;
1366 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1367 int ret = 0;
1368
1369 if (ath9k_modparam_nohwcrypt)
1370 return -ENOSPC;
1371
1372 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1373 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1374 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1375 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1376 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1377 /*
1378 * For now, disable hw crypto for the RSN IBSS group keys. This
1379 * could be optimized in the future to use a modified key cache
1380 * design to support per-STA RX GTK, but until that gets
1381 * implemented, use of software crypto for group addressed
1382 * frames is a acceptable to allow RSN IBSS to be used.
1383 */
1384 return -EOPNOTSUPP;
1385 }
1386
1387 mutex_lock(&sc->mutex);
1388 ath9k_ps_wakeup(sc);
1389 ath_dbg(common, CONFIG, "Set HW Key\n");
1390
1391 switch (cmd) {
1392 case SET_KEY:
1393 if (sta)
1394 ath9k_del_ps_key(sc, vif, sta);
1395
1396 ret = ath_key_config(common, vif, sta, key);
1397 if (ret >= 0) {
1398 key->hw_key_idx = ret;
1399 /* push IV and Michael MIC generation to stack */
1400 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1401 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1402 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1403 if (sc->sc_ah->sw_mgmt_crypto &&
1404 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1405 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1406 ret = 0;
1407 }
1408 break;
1409 case DISABLE_KEY:
1410 ath_key_delete(common, key);
1411 break;
1412 default:
1413 ret = -EINVAL;
1414 }
1415
1416 ath9k_ps_restore(sc);
1417 mutex_unlock(&sc->mutex);
1418
1419 return ret;
1420 }
1421
1422 static void ath9k_set_assoc_state(struct ath_softc *sc,
1423 struct ieee80211_vif *vif)
1424 {
1425 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1426 struct ath_vif *avp = (void *)vif->drv_priv;
1427 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1428 unsigned long flags;
1429
1430 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1431 avp->primary_sta_vif = true;
1432
1433 /*
1434 * Set the AID, BSSID and do beacon-sync only when
1435 * the HW opmode is STATION.
1436 *
1437 * But the primary bit is set above in any case.
1438 */
1439 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1440 return;
1441
1442 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1443 common->curaid = bss_conf->aid;
1444 ath9k_hw_write_associd(sc->sc_ah);
1445
1446 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1447 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1448
1449 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1450 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1451 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1452
1453 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1454 ath9k_mci_update_wlan_channels(sc, false);
1455
1456 ath_dbg(common, CONFIG,
1457 "Primary Station interface: %pM, BSSID: %pM\n",
1458 vif->addr, common->curbssid);
1459 }
1460
1461 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1462 {
1463 struct ath_softc *sc = data;
1464 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1465
1466 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
1467 return;
1468
1469 if (bss_conf->assoc)
1470 ath9k_set_assoc_state(sc, vif);
1471 }
1472
1473 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1474 struct ieee80211_vif *vif,
1475 struct ieee80211_bss_conf *bss_conf,
1476 u32 changed)
1477 {
1478 #define CHECK_ANI \
1479 (BSS_CHANGED_ASSOC | \
1480 BSS_CHANGED_IBSS | \
1481 BSS_CHANGED_BEACON_ENABLED)
1482
1483 struct ath_softc *sc = hw->priv;
1484 struct ath_hw *ah = sc->sc_ah;
1485 struct ath_common *common = ath9k_hw_common(ah);
1486 struct ath_vif *avp = (void *)vif->drv_priv;
1487 int slottime;
1488
1489 ath9k_ps_wakeup(sc);
1490 mutex_lock(&sc->mutex);
1491
1492 if (changed & BSS_CHANGED_ASSOC) {
1493 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1494 bss_conf->bssid, bss_conf->assoc);
1495
1496 if (avp->primary_sta_vif && !bss_conf->assoc) {
1497 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1498 avp->primary_sta_vif = false;
1499
1500 if (ah->opmode == NL80211_IFTYPE_STATION)
1501 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1502 }
1503
1504 ieee80211_iterate_active_interfaces_atomic(
1505 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1506 ath9k_bss_assoc_iter, sc);
1507
1508 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1509 ah->opmode == NL80211_IFTYPE_STATION) {
1510 memset(common->curbssid, 0, ETH_ALEN);
1511 common->curaid = 0;
1512 ath9k_hw_write_associd(sc->sc_ah);
1513 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1514 ath9k_mci_update_wlan_channels(sc, true);
1515 }
1516 }
1517
1518 if (changed & BSS_CHANGED_IBSS) {
1519 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1520 common->curaid = bss_conf->aid;
1521 ath9k_hw_write_associd(sc->sc_ah);
1522 }
1523
1524 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1525 (changed & BSS_CHANGED_BEACON_INT)) {
1526 if (ah->opmode == NL80211_IFTYPE_AP &&
1527 bss_conf->enable_beacon)
1528 ath9k_set_tsfadjust(sc, vif);
1529 if (ath9k_allow_beacon_config(sc, vif))
1530 ath9k_beacon_config(sc, vif, changed);
1531 }
1532
1533 if (changed & BSS_CHANGED_ERP_SLOT) {
1534 if (bss_conf->use_short_slot)
1535 slottime = 9;
1536 else
1537 slottime = 20;
1538 if (vif->type == NL80211_IFTYPE_AP) {
1539 /*
1540 * Defer update, so that connected stations can adjust
1541 * their settings at the same time.
1542 * See beacon.c for more details
1543 */
1544 sc->beacon.slottime = slottime;
1545 sc->beacon.updateslot = UPDATE;
1546 } else {
1547 ah->slottime = slottime;
1548 ath9k_hw_init_global_settings(ah);
1549 }
1550 }
1551
1552 if (changed & CHECK_ANI)
1553 ath_check_ani(sc);
1554
1555 mutex_unlock(&sc->mutex);
1556 ath9k_ps_restore(sc);
1557
1558 #undef CHECK_ANI
1559 }
1560
1561 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1562 {
1563 struct ath_softc *sc = hw->priv;
1564 u64 tsf;
1565
1566 mutex_lock(&sc->mutex);
1567 ath9k_ps_wakeup(sc);
1568 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1569 ath9k_ps_restore(sc);
1570 mutex_unlock(&sc->mutex);
1571
1572 return tsf;
1573 }
1574
1575 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1576 struct ieee80211_vif *vif,
1577 u64 tsf)
1578 {
1579 struct ath_softc *sc = hw->priv;
1580
1581 mutex_lock(&sc->mutex);
1582 ath9k_ps_wakeup(sc);
1583 ath9k_hw_settsf64(sc->sc_ah, tsf);
1584 ath9k_ps_restore(sc);
1585 mutex_unlock(&sc->mutex);
1586 }
1587
1588 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1589 {
1590 struct ath_softc *sc = hw->priv;
1591
1592 mutex_lock(&sc->mutex);
1593
1594 ath9k_ps_wakeup(sc);
1595 ath9k_hw_reset_tsf(sc->sc_ah);
1596 ath9k_ps_restore(sc);
1597
1598 mutex_unlock(&sc->mutex);
1599 }
1600
1601 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1602 struct ieee80211_vif *vif,
1603 enum ieee80211_ampdu_mlme_action action,
1604 struct ieee80211_sta *sta,
1605 u16 tid, u16 *ssn, u8 buf_size)
1606 {
1607 struct ath_softc *sc = hw->priv;
1608 int ret = 0;
1609
1610 local_bh_disable();
1611
1612 switch (action) {
1613 case IEEE80211_AMPDU_RX_START:
1614 break;
1615 case IEEE80211_AMPDU_RX_STOP:
1616 break;
1617 case IEEE80211_AMPDU_TX_START:
1618 ath9k_ps_wakeup(sc);
1619 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1620 if (!ret)
1621 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1622 ath9k_ps_restore(sc);
1623 break;
1624 case IEEE80211_AMPDU_TX_STOP:
1625 ath9k_ps_wakeup(sc);
1626 ath_tx_aggr_stop(sc, sta, tid);
1627 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1628 ath9k_ps_restore(sc);
1629 break;
1630 case IEEE80211_AMPDU_TX_OPERATIONAL:
1631 ath9k_ps_wakeup(sc);
1632 ath_tx_aggr_resume(sc, sta, tid);
1633 ath9k_ps_restore(sc);
1634 break;
1635 default:
1636 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1637 }
1638
1639 local_bh_enable();
1640
1641 return ret;
1642 }
1643
1644 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1645 struct survey_info *survey)
1646 {
1647 struct ath_softc *sc = hw->priv;
1648 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1649 struct ieee80211_supported_band *sband;
1650 struct ieee80211_channel *chan;
1651 unsigned long flags;
1652 int pos;
1653
1654 spin_lock_irqsave(&common->cc_lock, flags);
1655 if (idx == 0)
1656 ath_update_survey_stats(sc);
1657
1658 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1659 if (sband && idx >= sband->n_channels) {
1660 idx -= sband->n_channels;
1661 sband = NULL;
1662 }
1663
1664 if (!sband)
1665 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1666
1667 if (!sband || idx >= sband->n_channels) {
1668 spin_unlock_irqrestore(&common->cc_lock, flags);
1669 return -ENOENT;
1670 }
1671
1672 chan = &sband->channels[idx];
1673 pos = chan->hw_value;
1674 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1675 survey->channel = chan;
1676 spin_unlock_irqrestore(&common->cc_lock, flags);
1677
1678 return 0;
1679 }
1680
1681 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1682 {
1683 struct ath_softc *sc = hw->priv;
1684 struct ath_hw *ah = sc->sc_ah;
1685
1686 mutex_lock(&sc->mutex);
1687 ah->coverage_class = coverage_class;
1688
1689 ath9k_ps_wakeup(sc);
1690 ath9k_hw_init_global_settings(ah);
1691 ath9k_ps_restore(sc);
1692
1693 mutex_unlock(&sc->mutex);
1694 }
1695
1696 static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1697 {
1698 struct ath_softc *sc = hw->priv;
1699 struct ath_hw *ah = sc->sc_ah;
1700 struct ath_common *common = ath9k_hw_common(ah);
1701 int timeout = 200; /* ms */
1702 int i, j;
1703 bool drain_txq;
1704
1705 mutex_lock(&sc->mutex);
1706 cancel_delayed_work_sync(&sc->tx_complete_work);
1707
1708 if (ah->ah_flags & AH_UNPLUGGED) {
1709 ath_dbg(common, ANY, "Device has been unplugged!\n");
1710 mutex_unlock(&sc->mutex);
1711 return;
1712 }
1713
1714 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
1715 ath_dbg(common, ANY, "Device not present\n");
1716 mutex_unlock(&sc->mutex);
1717 return;
1718 }
1719
1720 for (j = 0; j < timeout; j++) {
1721 bool npend = false;
1722
1723 if (j)
1724 usleep_range(1000, 2000);
1725
1726 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1727 if (!ATH_TXQ_SETUP(sc, i))
1728 continue;
1729
1730 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1731
1732 if (npend)
1733 break;
1734 }
1735
1736 if (!npend)
1737 break;
1738 }
1739
1740 if (drop) {
1741 ath9k_ps_wakeup(sc);
1742 spin_lock_bh(&sc->sc_pcu_lock);
1743 drain_txq = ath_drain_all_txq(sc, false);
1744 spin_unlock_bh(&sc->sc_pcu_lock);
1745
1746 if (!drain_txq)
1747 ath_reset(sc, false);
1748
1749 ath9k_ps_restore(sc);
1750 ieee80211_wake_queues(hw);
1751 }
1752
1753 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1754 mutex_unlock(&sc->mutex);
1755 }
1756
1757 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1758 {
1759 struct ath_softc *sc = hw->priv;
1760 int i;
1761
1762 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1763 if (!ATH_TXQ_SETUP(sc, i))
1764 continue;
1765
1766 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1767 return true;
1768 }
1769 return false;
1770 }
1771
1772 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
1773 {
1774 struct ath_softc *sc = hw->priv;
1775 struct ath_hw *ah = sc->sc_ah;
1776 struct ieee80211_vif *vif;
1777 struct ath_vif *avp;
1778 struct ath_buf *bf;
1779 struct ath_tx_status ts;
1780 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1781 int status;
1782
1783 vif = sc->beacon.bslot[0];
1784 if (!vif)
1785 return 0;
1786
1787 if (!vif->bss_conf.enable_beacon)
1788 return 0;
1789
1790 avp = (void *)vif->drv_priv;
1791
1792 if (!sc->beacon.tx_processed && !edma) {
1793 tasklet_disable(&sc->bcon_tasklet);
1794
1795 bf = avp->av_bcbuf;
1796 if (!bf || !bf->bf_mpdu)
1797 goto skip;
1798
1799 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1800 if (status == -EINPROGRESS)
1801 goto skip;
1802
1803 sc->beacon.tx_processed = true;
1804 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1805
1806 skip:
1807 tasklet_enable(&sc->bcon_tasklet);
1808 }
1809
1810 return sc->beacon.tx_last;
1811 }
1812
1813 static int ath9k_get_stats(struct ieee80211_hw *hw,
1814 struct ieee80211_low_level_stats *stats)
1815 {
1816 struct ath_softc *sc = hw->priv;
1817 struct ath_hw *ah = sc->sc_ah;
1818 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1819
1820 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1821 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1822 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1823 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1824 return 0;
1825 }
1826
1827 static u32 fill_chainmask(u32 cap, u32 new)
1828 {
1829 u32 filled = 0;
1830 int i;
1831
1832 for (i = 0; cap && new; i++, cap >>= 1) {
1833 if (!(cap & BIT(0)))
1834 continue;
1835
1836 if (new & BIT(0))
1837 filled |= BIT(i);
1838
1839 new >>= 1;
1840 }
1841
1842 return filled;
1843 }
1844
1845 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
1846 {
1847 switch (val & 0x7) {
1848 case 0x1:
1849 case 0x3:
1850 case 0x7:
1851 return true;
1852 case 0x2:
1853 return (ah->caps.rx_chainmask == 1);
1854 default:
1855 return false;
1856 }
1857 }
1858
1859 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1860 {
1861 struct ath_softc *sc = hw->priv;
1862 struct ath_hw *ah = sc->sc_ah;
1863
1864 if (ah->caps.rx_chainmask != 1)
1865 rx_ant |= tx_ant;
1866
1867 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
1868 return -EINVAL;
1869
1870 sc->ant_rx = rx_ant;
1871 sc->ant_tx = tx_ant;
1872
1873 if (ah->caps.rx_chainmask == 1)
1874 return 0;
1875
1876 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1877 if (AR_SREV_9100(ah))
1878 ah->rxchainmask = 0x7;
1879 else
1880 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1881
1882 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1883 ath9k_reload_chainmask_settings(sc);
1884
1885 return 0;
1886 }
1887
1888 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1889 {
1890 struct ath_softc *sc = hw->priv;
1891
1892 *tx_ant = sc->ant_tx;
1893 *rx_ant = sc->ant_rx;
1894 return 0;
1895 }
1896
1897 #ifdef CONFIG_ATH9K_DEBUGFS
1898
1899 /* Ethtool support for get-stats */
1900
1901 #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
1902 static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
1903 "tx_pkts_nic",
1904 "tx_bytes_nic",
1905 "rx_pkts_nic",
1906 "rx_bytes_nic",
1907 AMKSTR(d_tx_pkts),
1908 AMKSTR(d_tx_bytes),
1909 AMKSTR(d_tx_mpdus_queued),
1910 AMKSTR(d_tx_mpdus_completed),
1911 AMKSTR(d_tx_mpdu_xretries),
1912 AMKSTR(d_tx_aggregates),
1913 AMKSTR(d_tx_ampdus_queued_hw),
1914 AMKSTR(d_tx_ampdus_queued_sw),
1915 AMKSTR(d_tx_ampdus_completed),
1916 AMKSTR(d_tx_ampdu_retries),
1917 AMKSTR(d_tx_ampdu_xretries),
1918 AMKSTR(d_tx_fifo_underrun),
1919 AMKSTR(d_tx_op_exceeded),
1920 AMKSTR(d_tx_timer_expiry),
1921 AMKSTR(d_tx_desc_cfg_err),
1922 AMKSTR(d_tx_data_underrun),
1923 AMKSTR(d_tx_delim_underrun),
1924
1925 "d_rx_decrypt_crc_err",
1926 "d_rx_phy_err",
1927 "d_rx_mic_err",
1928 "d_rx_pre_delim_crc_err",
1929 "d_rx_post_delim_crc_err",
1930 "d_rx_decrypt_busy_err",
1931
1932 "d_rx_phyerr_radar",
1933 "d_rx_phyerr_ofdm_timing",
1934 "d_rx_phyerr_cck_timing",
1935
1936 };
1937 #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
1938
1939 static void ath9k_get_et_strings(struct ieee80211_hw *hw,
1940 struct ieee80211_vif *vif,
1941 u32 sset, u8 *data)
1942 {
1943 if (sset == ETH_SS_STATS)
1944 memcpy(data, *ath9k_gstrings_stats,
1945 sizeof(ath9k_gstrings_stats));
1946 }
1947
1948 static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
1949 struct ieee80211_vif *vif, int sset)
1950 {
1951 if (sset == ETH_SS_STATS)
1952 return ATH9K_SSTATS_LEN;
1953 return 0;
1954 }
1955
1956 #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
1957 #define AWDATA(elem) \
1958 do { \
1959 data[i++] = sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BE)].elem; \
1960 data[i++] = sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BK)].elem; \
1961 data[i++] = sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VI)].elem; \
1962 data[i++] = sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VO)].elem; \
1963 } while (0)
1964
1965 #define AWDATA_RX(elem) \
1966 do { \
1967 data[i++] = sc->debug.stats.rxstats.elem; \
1968 } while (0)
1969
1970 static void ath9k_get_et_stats(struct ieee80211_hw *hw,
1971 struct ieee80211_vif *vif,
1972 struct ethtool_stats *stats, u64 *data)
1973 {
1974 struct ath_softc *sc = hw->priv;
1975 int i = 0;
1976
1977 data[i++] = (sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BE)].tx_pkts_all +
1978 sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BK)].tx_pkts_all +
1979 sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VI)].tx_pkts_all +
1980 sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VO)].tx_pkts_all);
1981 data[i++] = (sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BE)].tx_bytes_all +
1982 sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_BK)].tx_bytes_all +
1983 sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VI)].tx_bytes_all +
1984 sc->debug.stats.txstats[PR_QNUM(IEEE80211_AC_VO)].tx_bytes_all);
1985 AWDATA_RX(rx_pkts_all);
1986 AWDATA_RX(rx_bytes_all);
1987
1988 AWDATA(tx_pkts_all);
1989 AWDATA(tx_bytes_all);
1990 AWDATA(queued);
1991 AWDATA(completed);
1992 AWDATA(xretries);
1993 AWDATA(a_aggr);
1994 AWDATA(a_queued_hw);
1995 AWDATA(a_queued_sw);
1996 AWDATA(a_completed);
1997 AWDATA(a_retries);
1998 AWDATA(a_xretries);
1999 AWDATA(fifo_underrun);
2000 AWDATA(xtxop);
2001 AWDATA(timer_exp);
2002 AWDATA(desc_cfg_err);
2003 AWDATA(data_underrun);
2004 AWDATA(delim_underrun);
2005
2006 AWDATA_RX(decrypt_crc_err);
2007 AWDATA_RX(phy_err);
2008 AWDATA_RX(mic_err);
2009 AWDATA_RX(pre_delim_crc_err);
2010 AWDATA_RX(post_delim_crc_err);
2011 AWDATA_RX(decrypt_busy_err);
2012
2013 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
2014 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
2015 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
2016
2017 WARN_ON(i != ATH9K_SSTATS_LEN);
2018 }
2019
2020 /* End of ethtool get-stats functions */
2021
2022 #endif
2023
2024
2025 #ifdef CONFIG_PM_SLEEP
2026
2027 static void ath9k_wow_map_triggers(struct ath_softc *sc,
2028 struct cfg80211_wowlan *wowlan,
2029 u32 *wow_triggers)
2030 {
2031 if (wowlan->disconnect)
2032 *wow_triggers |= AH_WOW_LINK_CHANGE |
2033 AH_WOW_BEACON_MISS;
2034 if (wowlan->magic_pkt)
2035 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
2036
2037 if (wowlan->n_patterns)
2038 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
2039
2040 sc->wow_enabled = *wow_triggers;
2041
2042 }
2043
2044 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
2045 {
2046 struct ath_hw *ah = sc->sc_ah;
2047 struct ath_common *common = ath9k_hw_common(ah);
2048 struct ath9k_hw_capabilities *pcaps = &ah->caps;
2049 int pattern_count = 0;
2050 int i, byte_cnt;
2051 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
2052 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
2053
2054 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2055 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2056
2057 /*
2058 * Create Dissassociate / Deauthenticate packet filter
2059 *
2060 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
2061 * +--------------+----------+---------+--------+--------+----
2062 * + Frame Control+ Duration + DA + SA + BSSID +
2063 * +--------------+----------+---------+--------+--------+----
2064 *
2065 * The above is the management frame format for disassociate/
2066 * deauthenticate pattern, from this we need to match the first byte
2067 * of 'Frame Control' and DA, SA, and BSSID fields
2068 * (skipping 2nd byte of FC and Duration feild.
2069 *
2070 * Disassociate pattern
2071 * --------------------
2072 * Frame control = 00 00 1010
2073 * DA, SA, BSSID = x:x:x:x:x:x
2074 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2075 * | x:x:x:x:x:x -- 22 bytes
2076 *
2077 * Deauthenticate pattern
2078 * ----------------------
2079 * Frame control = 00 00 1100
2080 * DA, SA, BSSID = x:x:x:x:x:x
2081 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2082 * | x:x:x:x:x:x -- 22 bytes
2083 */
2084
2085 /* Create Disassociate Pattern first */
2086
2087 byte_cnt = 0;
2088
2089 /* Fill out the mask with all FF's */
2090
2091 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2092 dis_deauth_mask[i] = 0xff;
2093
2094 /* copy the first byte of frame control field */
2095 dis_deauth_pattern[byte_cnt] = 0xa0;
2096 byte_cnt++;
2097
2098 /* skip 2nd byte of frame control and Duration field */
2099 byte_cnt += 3;
2100
2101 /*
2102 * need not match the destination mac address, it can be a broadcast
2103 * mac address or an unicast to this station
2104 */
2105 byte_cnt += 6;
2106
2107 /* copy the source mac address */
2108 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2109
2110 byte_cnt += 6;
2111
2112 /* copy the bssid, its same as the source mac address */
2113
2114 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2115
2116 /* Create Disassociate pattern mask */
2117
2118 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
2119
2120 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
2121 /*
2122 * for AR9280, because of hardware limitation, the
2123 * first 4 bytes have to be matched for all patterns.
2124 * the mask for disassociation and de-auth pattern
2125 * matching need to enable the first 4 bytes.
2126 * also the duration field needs to be filled.
2127 */
2128 dis_deauth_mask[0] = 0xf0;
2129
2130 /*
2131 * fill in duration field
2132 FIXME: what is the exact value ?
2133 */
2134 dis_deauth_pattern[2] = 0xff;
2135 dis_deauth_pattern[3] = 0xff;
2136 } else {
2137 dis_deauth_mask[0] = 0xfe;
2138 }
2139
2140 dis_deauth_mask[1] = 0x03;
2141 dis_deauth_mask[2] = 0xc0;
2142 } else {
2143 dis_deauth_mask[0] = 0xef;
2144 dis_deauth_mask[1] = 0x3f;
2145 dis_deauth_mask[2] = 0x00;
2146 dis_deauth_mask[3] = 0xfc;
2147 }
2148
2149 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2150
2151 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2152 pattern_count, byte_cnt);
2153
2154 pattern_count++;
2155 /*
2156 * for de-authenticate pattern, only the first byte of the frame
2157 * control field gets changed from 0xA0 to 0xC0
2158 */
2159 dis_deauth_pattern[0] = 0xC0;
2160
2161 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2162 pattern_count, byte_cnt);
2163
2164 }
2165
2166 static void ath9k_wow_add_pattern(struct ath_softc *sc,
2167 struct cfg80211_wowlan *wowlan)
2168 {
2169 struct ath_hw *ah = sc->sc_ah;
2170 struct ath9k_wow_pattern *wow_pattern = NULL;
2171 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2172 int mask_len;
2173 s8 i = 0;
2174
2175 if (!wowlan->n_patterns)
2176 return;
2177
2178 /*
2179 * Add the new user configured patterns
2180 */
2181 for (i = 0; i < wowlan->n_patterns; i++) {
2182
2183 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2184
2185 if (!wow_pattern)
2186 return;
2187
2188 /*
2189 * TODO: convert the generic user space pattern to
2190 * appropriate chip specific/802.11 pattern.
2191 */
2192
2193 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2194 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2195 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2196 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2197 patterns[i].pattern_len);
2198 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2199 wow_pattern->pattern_len = patterns[i].pattern_len;
2200
2201 /*
2202 * just need to take care of deauth and disssoc pattern,
2203 * make sure we don't overwrite them.
2204 */
2205
2206 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2207 wow_pattern->mask_bytes,
2208 i + 2,
2209 wow_pattern->pattern_len);
2210 kfree(wow_pattern);
2211
2212 }
2213
2214 }
2215
2216 static int ath9k_suspend(struct ieee80211_hw *hw,
2217 struct cfg80211_wowlan *wowlan)
2218 {
2219 struct ath_softc *sc = hw->priv;
2220 struct ath_hw *ah = sc->sc_ah;
2221 struct ath_common *common = ath9k_hw_common(ah);
2222 u32 wow_triggers_enabled = 0;
2223 int ret = 0;
2224
2225 mutex_lock(&sc->mutex);
2226
2227 ath_cancel_work(sc);
2228 ath_stop_ani(sc);
2229 del_timer_sync(&sc->rx_poll_timer);
2230
2231 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2232 ath_dbg(common, ANY, "Device not present\n");
2233 ret = -EINVAL;
2234 goto fail_wow;
2235 }
2236
2237 if (WARN_ON(!wowlan)) {
2238 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2239 ret = -EINVAL;
2240 goto fail_wow;
2241 }
2242
2243 if (!device_can_wakeup(sc->dev)) {
2244 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2245 ret = 1;
2246 goto fail_wow;
2247 }
2248
2249 /*
2250 * none of the sta vifs are associated
2251 * and we are not currently handling multivif
2252 * cases, for instance we have to seperately
2253 * configure 'keep alive frame' for each
2254 * STA.
2255 */
2256
2257 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2258 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2259 ret = 1;
2260 goto fail_wow;
2261 }
2262
2263 if (sc->nvifs > 1) {
2264 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2265 ret = 1;
2266 goto fail_wow;
2267 }
2268
2269 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2270
2271 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2272 wow_triggers_enabled);
2273
2274 ath9k_ps_wakeup(sc);
2275
2276 ath9k_stop_btcoex(sc);
2277
2278 /*
2279 * Enable wake up on recieving disassoc/deauth
2280 * frame by default.
2281 */
2282 ath9k_wow_add_disassoc_deauth_pattern(sc);
2283
2284 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2285 ath9k_wow_add_pattern(sc, wowlan);
2286
2287 spin_lock_bh(&sc->sc_pcu_lock);
2288 /*
2289 * To avoid false wake, we enable beacon miss interrupt only
2290 * when we go to sleep. We save the current interrupt mask
2291 * so we can restore it after the system wakes up
2292 */
2293 sc->wow_intr_before_sleep = ah->imask;
2294 ah->imask &= ~ATH9K_INT_GLOBAL;
2295 ath9k_hw_disable_interrupts(ah);
2296 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2297 ath9k_hw_set_interrupts(ah);
2298 ath9k_hw_enable_interrupts(ah);
2299
2300 spin_unlock_bh(&sc->sc_pcu_lock);
2301
2302 /*
2303 * we can now sync irq and kill any running tasklets, since we already
2304 * disabled interrupts and not holding a spin lock
2305 */
2306 synchronize_irq(sc->irq);
2307 tasklet_kill(&sc->intr_tq);
2308
2309 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2310
2311 ath9k_ps_restore(sc);
2312 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2313 atomic_inc(&sc->wow_sleep_proc_intr);
2314
2315 fail_wow:
2316 mutex_unlock(&sc->mutex);
2317 return ret;
2318 }
2319
2320 static int ath9k_resume(struct ieee80211_hw *hw)
2321 {
2322 struct ath_softc *sc = hw->priv;
2323 struct ath_hw *ah = sc->sc_ah;
2324 struct ath_common *common = ath9k_hw_common(ah);
2325 u32 wow_status;
2326
2327 mutex_lock(&sc->mutex);
2328
2329 ath9k_ps_wakeup(sc);
2330
2331 spin_lock_bh(&sc->sc_pcu_lock);
2332
2333 ath9k_hw_disable_interrupts(ah);
2334 ah->imask = sc->wow_intr_before_sleep;
2335 ath9k_hw_set_interrupts(ah);
2336 ath9k_hw_enable_interrupts(ah);
2337
2338 spin_unlock_bh(&sc->sc_pcu_lock);
2339
2340 wow_status = ath9k_hw_wow_wakeup(ah);
2341
2342 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2343 /*
2344 * some devices may not pick beacon miss
2345 * as the reason they woke up so we add
2346 * that here for that shortcoming.
2347 */
2348 wow_status |= AH_WOW_BEACON_MISS;
2349 atomic_dec(&sc->wow_got_bmiss_intr);
2350 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2351 }
2352
2353 atomic_dec(&sc->wow_sleep_proc_intr);
2354
2355 if (wow_status) {
2356 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2357 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2358 }
2359
2360 ath_restart_work(sc);
2361 ath9k_start_btcoex(sc);
2362
2363 ath9k_ps_restore(sc);
2364 mutex_unlock(&sc->mutex);
2365
2366 return 0;
2367 }
2368
2369 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2370 {
2371 struct ath_softc *sc = hw->priv;
2372
2373 mutex_lock(&sc->mutex);
2374 device_init_wakeup(sc->dev, 1);
2375 device_set_wakeup_enable(sc->dev, enabled);
2376 mutex_unlock(&sc->mutex);
2377 }
2378
2379 #endif
2380
2381 struct ieee80211_ops ath9k_ops = {
2382 .tx = ath9k_tx,
2383 .start = ath9k_start,
2384 .stop = ath9k_stop,
2385 .add_interface = ath9k_add_interface,
2386 .change_interface = ath9k_change_interface,
2387 .remove_interface = ath9k_remove_interface,
2388 .config = ath9k_config,
2389 .configure_filter = ath9k_configure_filter,
2390 .sta_add = ath9k_sta_add,
2391 .sta_remove = ath9k_sta_remove,
2392 .sta_notify = ath9k_sta_notify,
2393 .conf_tx = ath9k_conf_tx,
2394 .bss_info_changed = ath9k_bss_info_changed,
2395 .set_key = ath9k_set_key,
2396 .get_tsf = ath9k_get_tsf,
2397 .set_tsf = ath9k_set_tsf,
2398 .reset_tsf = ath9k_reset_tsf,
2399 .ampdu_action = ath9k_ampdu_action,
2400 .get_survey = ath9k_get_survey,
2401 .rfkill_poll = ath9k_rfkill_poll_state,
2402 .set_coverage_class = ath9k_set_coverage_class,
2403 .flush = ath9k_flush,
2404 .tx_frames_pending = ath9k_tx_frames_pending,
2405 .tx_last_beacon = ath9k_tx_last_beacon,
2406 .get_stats = ath9k_get_stats,
2407 .set_antenna = ath9k_set_antenna,
2408 .get_antenna = ath9k_get_antenna,
2409
2410 #ifdef CONFIG_PM_SLEEP
2411 .suspend = ath9k_suspend,
2412 .resume = ath9k_resume,
2413 .set_wakeup = ath9k_set_wakeup,
2414 #endif
2415
2416 #ifdef CONFIG_ATH9K_DEBUGFS
2417 .get_et_sset_count = ath9k_get_et_sset_count,
2418 .get_et_stats = ath9k_get_et_stats,
2419 .get_et_strings = ath9k_get_et_strings,
2420 #endif
2421 };
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