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Merge branch 'for-linus-37rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rw/uml
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / main.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58 }
59
60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61 {
62 bool pending = false;
63
64 spin_lock_bh(&txq->axq_lock);
65
66 if (txq->axq_depth || !list_empty(&txq->axq_acq))
67 pending = true;
68
69 spin_unlock_bh(&txq->axq_lock);
70 return pending;
71 }
72
73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
74 {
75 unsigned long flags;
76 bool ret;
77
78 spin_lock_irqsave(&sc->sc_pm_lock, flags);
79 ret = ath9k_hw_setpower(sc->sc_ah, mode);
80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
81
82 return ret;
83 }
84
85 void ath9k_ps_wakeup(struct ath_softc *sc)
86 {
87 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
88 unsigned long flags;
89 enum ath9k_power_mode power_mode;
90
91 spin_lock_irqsave(&sc->sc_pm_lock, flags);
92 if (++sc->ps_usecount != 1)
93 goto unlock;
94
95 power_mode = sc->sc_ah->power_mode;
96 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
97
98 /*
99 * While the hardware is asleep, the cycle counters contain no
100 * useful data. Better clear them now so that they don't mess up
101 * survey data results.
102 */
103 if (power_mode != ATH9K_PM_AWAKE) {
104 spin_lock(&common->cc_lock);
105 ath_hw_cycle_counters_update(common);
106 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
107 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
108 spin_unlock(&common->cc_lock);
109 }
110
111 unlock:
112 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
113 }
114
115 void ath9k_ps_restore(struct ath_softc *sc)
116 {
117 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
118 enum ath9k_power_mode mode;
119 unsigned long flags;
120 bool reset;
121
122 spin_lock_irqsave(&sc->sc_pm_lock, flags);
123 if (--sc->ps_usecount != 0)
124 goto unlock;
125
126 if (sc->ps_idle) {
127 ath9k_hw_setrxabort(sc->sc_ah, 1);
128 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
129 mode = ATH9K_PM_FULL_SLEEP;
130 } else if (sc->ps_enabled &&
131 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
132 PS_WAIT_FOR_CAB |
133 PS_WAIT_FOR_PSPOLL_DATA |
134 PS_WAIT_FOR_TX_ACK))) {
135 mode = ATH9K_PM_NETWORK_SLEEP;
136 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
137 ath9k_btcoex_stop_gen_timer(sc);
138 } else {
139 goto unlock;
140 }
141
142 spin_lock(&common->cc_lock);
143 ath_hw_cycle_counters_update(common);
144 spin_unlock(&common->cc_lock);
145
146 ath9k_hw_setpower(sc->sc_ah, mode);
147
148 unlock:
149 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
150 }
151
152 static void __ath_cancel_work(struct ath_softc *sc)
153 {
154 cancel_work_sync(&sc->paprd_work);
155 cancel_work_sync(&sc->hw_check_work);
156 cancel_delayed_work_sync(&sc->tx_complete_work);
157 cancel_delayed_work_sync(&sc->hw_pll_work);
158
159 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
160 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
161 cancel_work_sync(&sc->mci_work);
162 #endif
163 }
164
165 static void ath_cancel_work(struct ath_softc *sc)
166 {
167 __ath_cancel_work(sc);
168 cancel_work_sync(&sc->hw_reset_work);
169 }
170
171 static void ath_restart_work(struct ath_softc *sc)
172 {
173 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
174
175 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
176 AR_SREV_9550(sc->sc_ah))
177 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
178 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
179
180 ath_start_rx_poll(sc, 3);
181 ath_start_ani(sc);
182 }
183
184 static bool ath_prepare_reset(struct ath_softc *sc, bool retry_tx, bool flush)
185 {
186 struct ath_hw *ah = sc->sc_ah;
187 bool ret = true;
188
189 ieee80211_stop_queues(sc->hw);
190
191 sc->hw_busy_count = 0;
192 ath_stop_ani(sc);
193 del_timer_sync(&sc->rx_poll_timer);
194
195 ath9k_debug_samp_bb_mac(sc);
196 ath9k_hw_disable_interrupts(ah);
197
198 if (!ath_stoprecv(sc))
199 ret = false;
200
201 if (!ath_drain_all_txq(sc, retry_tx))
202 ret = false;
203
204 if (!flush) {
205 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
206 ath_rx_tasklet(sc, 1, true);
207 ath_rx_tasklet(sc, 1, false);
208 } else {
209 ath_flushrecv(sc);
210 }
211
212 return ret;
213 }
214
215 static bool ath_complete_reset(struct ath_softc *sc, bool start)
216 {
217 struct ath_hw *ah = sc->sc_ah;
218 struct ath_common *common = ath9k_hw_common(ah);
219 unsigned long flags;
220
221 if (ath_startrecv(sc) != 0) {
222 ath_err(common, "Unable to restart recv logic\n");
223 return false;
224 }
225
226 ath9k_cmn_update_txpow(ah, sc->curtxpow,
227 sc->config.txpowlimit, &sc->curtxpow);
228
229 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
230 ath9k_hw_set_interrupts(ah);
231 ath9k_hw_enable_interrupts(ah);
232
233 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
234 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
235 goto work;
236
237 ath9k_set_beacon(sc);
238
239 if (ah->opmode == NL80211_IFTYPE_STATION &&
240 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
241 spin_lock_irqsave(&sc->sc_pm_lock, flags);
242 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
243 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
244 }
245 work:
246 ath_restart_work(sc);
247 }
248
249 if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
250 ath_ant_comb_update(sc);
251
252 ieee80211_wake_queues(sc->hw);
253
254 return true;
255 }
256
257 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan,
258 bool retry_tx)
259 {
260 struct ath_hw *ah = sc->sc_ah;
261 struct ath_common *common = ath9k_hw_common(ah);
262 struct ath9k_hw_cal_data *caldata = NULL;
263 bool fastcc = true;
264 bool flush = false;
265 int r;
266
267 __ath_cancel_work(sc);
268
269 spin_lock_bh(&sc->sc_pcu_lock);
270
271 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
272 fastcc = false;
273 caldata = &sc->caldata;
274 }
275
276 if (!hchan) {
277 fastcc = false;
278 flush = true;
279 hchan = ah->curchan;
280 }
281
282 if (!ath_prepare_reset(sc, retry_tx, flush))
283 fastcc = false;
284
285 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
286 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
287
288 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
289 if (r) {
290 ath_err(common,
291 "Unable to reset channel, reset status %d\n", r);
292 goto out;
293 }
294
295 if (!ath_complete_reset(sc, true))
296 r = -EIO;
297
298 out:
299 spin_unlock_bh(&sc->sc_pcu_lock);
300 return r;
301 }
302
303
304 /*
305 * Set/change channels. If the channel is really being changed, it's done
306 * by reseting the chip. To accomplish this we must first cleanup any pending
307 * DMA, then restart stuff.
308 */
309 static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
310 struct ath9k_channel *hchan)
311 {
312 int r;
313
314 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
315 return -EIO;
316
317 r = ath_reset_internal(sc, hchan, false);
318
319 return r;
320 }
321
322 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
323 struct ieee80211_vif *vif)
324 {
325 struct ath_node *an;
326 u8 density;
327 an = (struct ath_node *)sta->drv_priv;
328
329 #ifdef CONFIG_ATH9K_DEBUGFS
330 spin_lock(&sc->nodes_lock);
331 list_add(&an->list, &sc->nodes);
332 spin_unlock(&sc->nodes_lock);
333 #endif
334 an->sta = sta;
335 an->vif = vif;
336
337 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
338 ath_tx_node_init(sc, an);
339 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
340 sta->ht_cap.ampdu_factor);
341 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
342 an->mpdudensity = density;
343 }
344 }
345
346 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
347 {
348 struct ath_node *an = (struct ath_node *)sta->drv_priv;
349
350 #ifdef CONFIG_ATH9K_DEBUGFS
351 spin_lock(&sc->nodes_lock);
352 list_del(&an->list);
353 spin_unlock(&sc->nodes_lock);
354 an->sta = NULL;
355 #endif
356
357 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
358 ath_tx_node_cleanup(sc, an);
359 }
360
361 void ath9k_tasklet(unsigned long data)
362 {
363 struct ath_softc *sc = (struct ath_softc *)data;
364 struct ath_hw *ah = sc->sc_ah;
365 struct ath_common *common = ath9k_hw_common(ah);
366 enum ath_reset_type type;
367 unsigned long flags;
368 u32 status = sc->intrstatus;
369 u32 rxmask;
370
371 ath9k_ps_wakeup(sc);
372 spin_lock(&sc->sc_pcu_lock);
373
374 if ((status & ATH9K_INT_FATAL) ||
375 (status & ATH9K_INT_BB_WATCHDOG)) {
376
377 if (status & ATH9K_INT_FATAL)
378 type = RESET_TYPE_FATAL_INT;
379 else
380 type = RESET_TYPE_BB_WATCHDOG;
381
382 ath9k_queue_reset(sc, type);
383 goto out;
384 }
385
386 spin_lock_irqsave(&sc->sc_pm_lock, flags);
387 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
388 /*
389 * TSF sync does not look correct; remain awake to sync with
390 * the next Beacon.
391 */
392 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
393 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
394 }
395 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
396
397 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
398 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
399 ATH9K_INT_RXORN);
400 else
401 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
402
403 if (status & rxmask) {
404 /* Check for high priority Rx first */
405 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
406 (status & ATH9K_INT_RXHP))
407 ath_rx_tasklet(sc, 0, true);
408
409 ath_rx_tasklet(sc, 0, false);
410 }
411
412 if (status & ATH9K_INT_TX) {
413 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
414 ath_tx_edma_tasklet(sc);
415 else
416 ath_tx_tasklet(sc);
417 }
418
419 ath9k_btcoex_handle_interrupt(sc, status);
420
421 out:
422 /* re-enable hardware interrupt */
423 ath9k_hw_enable_interrupts(ah);
424
425 spin_unlock(&sc->sc_pcu_lock);
426 ath9k_ps_restore(sc);
427 }
428
429 irqreturn_t ath_isr(int irq, void *dev)
430 {
431 #define SCHED_INTR ( \
432 ATH9K_INT_FATAL | \
433 ATH9K_INT_BB_WATCHDOG | \
434 ATH9K_INT_RXORN | \
435 ATH9K_INT_RXEOL | \
436 ATH9K_INT_RX | \
437 ATH9K_INT_RXLP | \
438 ATH9K_INT_RXHP | \
439 ATH9K_INT_TX | \
440 ATH9K_INT_BMISS | \
441 ATH9K_INT_CST | \
442 ATH9K_INT_TSFOOR | \
443 ATH9K_INT_GENTIMER | \
444 ATH9K_INT_MCI)
445
446 struct ath_softc *sc = dev;
447 struct ath_hw *ah = sc->sc_ah;
448 struct ath_common *common = ath9k_hw_common(ah);
449 enum ath9k_int status;
450 bool sched = false;
451
452 /*
453 * The hardware is not ready/present, don't
454 * touch anything. Note this can happen early
455 * on if the IRQ is shared.
456 */
457 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
458 return IRQ_NONE;
459
460 /* shared irq, not for us */
461
462 if (!ath9k_hw_intrpend(ah))
463 return IRQ_NONE;
464
465 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
466 ath9k_hw_kill_interrupts(ah);
467 return IRQ_HANDLED;
468 }
469
470 /*
471 * Figure out the reason(s) for the interrupt. Note
472 * that the hal returns a pseudo-ISR that may include
473 * bits we haven't explicitly enabled so we mask the
474 * value to insure we only process bits we requested.
475 */
476 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
477 status &= ah->imask; /* discard unasked-for bits */
478
479 /*
480 * If there are no status bits set, then this interrupt was not
481 * for me (should have been caught above).
482 */
483 if (!status)
484 return IRQ_NONE;
485
486 /* Cache the status */
487 sc->intrstatus = status;
488
489 if (status & SCHED_INTR)
490 sched = true;
491
492 #ifdef CONFIG_PM_SLEEP
493 if (status & ATH9K_INT_BMISS) {
494 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
495 ath_dbg(common, ANY, "during WoW we got a BMISS\n");
496 atomic_inc(&sc->wow_got_bmiss_intr);
497 atomic_dec(&sc->wow_sleep_proc_intr);
498 }
499 ath_dbg(common, INTERRUPT, "beacon miss interrupt\n");
500 }
501 #endif
502
503 /*
504 * If a FATAL or RXORN interrupt is received, we have to reset the
505 * chip immediately.
506 */
507 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
508 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
509 goto chip_reset;
510
511 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
512 (status & ATH9K_INT_BB_WATCHDOG)) {
513
514 spin_lock(&common->cc_lock);
515 ath_hw_cycle_counters_update(common);
516 ar9003_hw_bb_watchdog_dbg_info(ah);
517 spin_unlock(&common->cc_lock);
518
519 goto chip_reset;
520 }
521
522 if (status & ATH9K_INT_SWBA)
523 tasklet_schedule(&sc->bcon_tasklet);
524
525 if (status & ATH9K_INT_TXURN)
526 ath9k_hw_updatetxtriglevel(ah, true);
527
528 if (status & ATH9K_INT_RXEOL) {
529 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
530 ath9k_hw_set_interrupts(ah);
531 }
532
533 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
534 if (status & ATH9K_INT_TIM_TIMER) {
535 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
536 goto chip_reset;
537 /* Clear RxAbort bit so that we can
538 * receive frames */
539 ath9k_setpower(sc, ATH9K_PM_AWAKE);
540 spin_lock(&sc->sc_pm_lock);
541 ath9k_hw_setrxabort(sc->sc_ah, 0);
542 sc->ps_flags |= PS_WAIT_FOR_BEACON;
543 spin_unlock(&sc->sc_pm_lock);
544 }
545
546 chip_reset:
547
548 ath_debug_stat_interrupt(sc, status);
549
550 if (sched) {
551 /* turn off every interrupt */
552 ath9k_hw_disable_interrupts(ah);
553 tasklet_schedule(&sc->intr_tq);
554 }
555
556 return IRQ_HANDLED;
557
558 #undef SCHED_INTR
559 }
560
561 static int ath_reset(struct ath_softc *sc, bool retry_tx)
562 {
563 int r;
564
565 ath9k_ps_wakeup(sc);
566
567 r = ath_reset_internal(sc, NULL, retry_tx);
568
569 if (retry_tx) {
570 int i;
571 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
572 if (ATH_TXQ_SETUP(sc, i)) {
573 spin_lock_bh(&sc->tx.txq[i].axq_lock);
574 ath_txq_schedule(sc, &sc->tx.txq[i]);
575 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
576 }
577 }
578 }
579
580 ath9k_ps_restore(sc);
581
582 return r;
583 }
584
585 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
586 {
587 #ifdef CONFIG_ATH9K_DEBUGFS
588 RESET_STAT_INC(sc, type);
589 #endif
590 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
591 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
592 }
593
594 void ath_reset_work(struct work_struct *work)
595 {
596 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
597
598 ath_reset(sc, true);
599 }
600
601 /**********************/
602 /* mac80211 callbacks */
603 /**********************/
604
605 static int ath9k_start(struct ieee80211_hw *hw)
606 {
607 struct ath_softc *sc = hw->priv;
608 struct ath_hw *ah = sc->sc_ah;
609 struct ath_common *common = ath9k_hw_common(ah);
610 struct ieee80211_channel *curchan = hw->conf.channel;
611 struct ath9k_channel *init_channel;
612 int r;
613
614 ath_dbg(common, CONFIG,
615 "Starting driver with initial channel: %d MHz\n",
616 curchan->center_freq);
617
618 ath9k_ps_wakeup(sc);
619 mutex_lock(&sc->mutex);
620
621 init_channel = ath9k_cmn_get_curchannel(hw, ah);
622
623 /* Reset SERDES registers */
624 ath9k_hw_configpcipowersave(ah, false);
625
626 /*
627 * The basic interface to setting the hardware in a good
628 * state is ``reset''. On return the hardware is known to
629 * be powered up and with interrupts disabled. This must
630 * be followed by initialization of the appropriate bits
631 * and then setup of the interrupt mask.
632 */
633 spin_lock_bh(&sc->sc_pcu_lock);
634
635 atomic_set(&ah->intr_ref_cnt, -1);
636
637 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
638 if (r) {
639 ath_err(common,
640 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
641 r, curchan->center_freq);
642 spin_unlock_bh(&sc->sc_pcu_lock);
643 goto mutex_unlock;
644 }
645
646 /* Setup our intr mask. */
647 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
648 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
649 ATH9K_INT_GLOBAL;
650
651 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
652 ah->imask |= ATH9K_INT_RXHP |
653 ATH9K_INT_RXLP |
654 ATH9K_INT_BB_WATCHDOG;
655 else
656 ah->imask |= ATH9K_INT_RX;
657
658 ah->imask |= ATH9K_INT_GTT;
659
660 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
661 ah->imask |= ATH9K_INT_CST;
662
663 ath_mci_enable(sc);
664
665 clear_bit(SC_OP_INVALID, &sc->sc_flags);
666 sc->sc_ah->is_monitoring = false;
667
668 if (!ath_complete_reset(sc, false)) {
669 r = -EIO;
670 spin_unlock_bh(&sc->sc_pcu_lock);
671 goto mutex_unlock;
672 }
673
674 if (ah->led_pin >= 0) {
675 ath9k_hw_cfg_output(ah, ah->led_pin,
676 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
677 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
678 }
679
680 /*
681 * Reset key cache to sane defaults (all entries cleared) instead of
682 * semi-random values after suspend/resume.
683 */
684 ath9k_cmn_init_crypto(sc->sc_ah);
685
686 spin_unlock_bh(&sc->sc_pcu_lock);
687
688 if (ah->caps.pcie_lcr_extsync_en && common->bus_ops->extn_synch_en)
689 common->bus_ops->extn_synch_en(common);
690
691 mutex_unlock:
692 mutex_unlock(&sc->mutex);
693
694 ath9k_ps_restore(sc);
695
696 return r;
697 }
698
699 static void ath9k_tx(struct ieee80211_hw *hw,
700 struct ieee80211_tx_control *control,
701 struct sk_buff *skb)
702 {
703 struct ath_softc *sc = hw->priv;
704 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
705 struct ath_tx_control txctl;
706 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
707 unsigned long flags;
708
709 if (sc->ps_enabled) {
710 /*
711 * mac80211 does not set PM field for normal data frames, so we
712 * need to update that based on the current PS mode.
713 */
714 if (ieee80211_is_data(hdr->frame_control) &&
715 !ieee80211_is_nullfunc(hdr->frame_control) &&
716 !ieee80211_has_pm(hdr->frame_control)) {
717 ath_dbg(common, PS,
718 "Add PM=1 for a TX frame while in PS mode\n");
719 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
720 }
721 }
722
723 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
724 /*
725 * We are using PS-Poll and mac80211 can request TX while in
726 * power save mode. Need to wake up hardware for the TX to be
727 * completed and if needed, also for RX of buffered frames.
728 */
729 ath9k_ps_wakeup(sc);
730 spin_lock_irqsave(&sc->sc_pm_lock, flags);
731 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
732 ath9k_hw_setrxabort(sc->sc_ah, 0);
733 if (ieee80211_is_pspoll(hdr->frame_control)) {
734 ath_dbg(common, PS,
735 "Sending PS-Poll to pick a buffered frame\n");
736 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
737 } else {
738 ath_dbg(common, PS, "Wake up to complete TX\n");
739 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
740 }
741 /*
742 * The actual restore operation will happen only after
743 * the ps_flags bit is cleared. We are just dropping
744 * the ps_usecount here.
745 */
746 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
747 ath9k_ps_restore(sc);
748 }
749
750 /*
751 * Cannot tx while the hardware is in full sleep, it first needs a full
752 * chip reset to recover from that
753 */
754 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
755 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
756 goto exit;
757 }
758
759 memset(&txctl, 0, sizeof(struct ath_tx_control));
760 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
761 txctl.sta = control->sta;
762
763 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
764
765 if (ath_tx_start(hw, skb, &txctl) != 0) {
766 ath_dbg(common, XMIT, "TX failed\n");
767 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
768 goto exit;
769 }
770
771 return;
772 exit:
773 dev_kfree_skb_any(skb);
774 }
775
776 static void ath9k_stop(struct ieee80211_hw *hw)
777 {
778 struct ath_softc *sc = hw->priv;
779 struct ath_hw *ah = sc->sc_ah;
780 struct ath_common *common = ath9k_hw_common(ah);
781 bool prev_idle;
782
783 mutex_lock(&sc->mutex);
784
785 ath_cancel_work(sc);
786 del_timer_sync(&sc->rx_poll_timer);
787
788 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
789 ath_dbg(common, ANY, "Device not present\n");
790 mutex_unlock(&sc->mutex);
791 return;
792 }
793
794 /* Ensure HW is awake when we try to shut it down. */
795 ath9k_ps_wakeup(sc);
796
797 spin_lock_bh(&sc->sc_pcu_lock);
798
799 /* prevent tasklets to enable interrupts once we disable them */
800 ah->imask &= ~ATH9K_INT_GLOBAL;
801
802 /* make sure h/w will not generate any interrupt
803 * before setting the invalid flag. */
804 ath9k_hw_disable_interrupts(ah);
805
806 spin_unlock_bh(&sc->sc_pcu_lock);
807
808 /* we can now sync irq and kill any running tasklets, since we already
809 * disabled interrupts and not holding a spin lock */
810 synchronize_irq(sc->irq);
811 tasklet_kill(&sc->intr_tq);
812 tasklet_kill(&sc->bcon_tasklet);
813
814 prev_idle = sc->ps_idle;
815 sc->ps_idle = true;
816
817 spin_lock_bh(&sc->sc_pcu_lock);
818
819 if (ah->led_pin >= 0) {
820 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
821 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
822 }
823
824 ath_prepare_reset(sc, false, true);
825
826 if (sc->rx.frag) {
827 dev_kfree_skb_any(sc->rx.frag);
828 sc->rx.frag = NULL;
829 }
830
831 if (!ah->curchan)
832 ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
833
834 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
835 ath9k_hw_phy_disable(ah);
836
837 ath9k_hw_configpcipowersave(ah, true);
838
839 spin_unlock_bh(&sc->sc_pcu_lock);
840
841 ath9k_ps_restore(sc);
842
843 set_bit(SC_OP_INVALID, &sc->sc_flags);
844 sc->ps_idle = prev_idle;
845
846 mutex_unlock(&sc->mutex);
847
848 ath_dbg(common, CONFIG, "Driver halt\n");
849 }
850
851 bool ath9k_uses_beacons(int type)
852 {
853 switch (type) {
854 case NL80211_IFTYPE_AP:
855 case NL80211_IFTYPE_ADHOC:
856 case NL80211_IFTYPE_MESH_POINT:
857 return true;
858 default:
859 return false;
860 }
861 }
862
863 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
864 {
865 struct ath9k_vif_iter_data *iter_data = data;
866 int i;
867
868 if (iter_data->hw_macaddr)
869 for (i = 0; i < ETH_ALEN; i++)
870 iter_data->mask[i] &=
871 ~(iter_data->hw_macaddr[i] ^ mac[i]);
872
873 switch (vif->type) {
874 case NL80211_IFTYPE_AP:
875 iter_data->naps++;
876 break;
877 case NL80211_IFTYPE_STATION:
878 iter_data->nstations++;
879 break;
880 case NL80211_IFTYPE_ADHOC:
881 iter_data->nadhocs++;
882 break;
883 case NL80211_IFTYPE_MESH_POINT:
884 iter_data->nmeshes++;
885 break;
886 case NL80211_IFTYPE_WDS:
887 iter_data->nwds++;
888 break;
889 default:
890 break;
891 }
892 }
893
894 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
895 {
896 struct ath_softc *sc = data;
897 struct ath_vif *avp = (void *)vif->drv_priv;
898
899 if (vif->type != NL80211_IFTYPE_STATION)
900 return;
901
902 if (avp->primary_sta_vif)
903 ath9k_set_assoc_state(sc, vif);
904 }
905
906 /* Called with sc->mutex held. */
907 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
908 struct ieee80211_vif *vif,
909 struct ath9k_vif_iter_data *iter_data)
910 {
911 struct ath_softc *sc = hw->priv;
912 struct ath_hw *ah = sc->sc_ah;
913 struct ath_common *common = ath9k_hw_common(ah);
914
915 /*
916 * Use the hardware MAC address as reference, the hardware uses it
917 * together with the BSSID mask when matching addresses.
918 */
919 memset(iter_data, 0, sizeof(*iter_data));
920 iter_data->hw_macaddr = common->macaddr;
921 memset(&iter_data->mask, 0xff, ETH_ALEN);
922
923 if (vif)
924 ath9k_vif_iter(iter_data, vif->addr, vif);
925
926 /* Get list of all active MAC addresses */
927 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath9k_vif_iter,
928 iter_data);
929 }
930
931 /* Called with sc->mutex held. */
932 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
933 struct ieee80211_vif *vif)
934 {
935 struct ath_softc *sc = hw->priv;
936 struct ath_hw *ah = sc->sc_ah;
937 struct ath_common *common = ath9k_hw_common(ah);
938 struct ath9k_vif_iter_data iter_data;
939 enum nl80211_iftype old_opmode = ah->opmode;
940
941 ath9k_calculate_iter_data(hw, vif, &iter_data);
942
943 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
944 ath_hw_setbssidmask(common);
945
946 if (iter_data.naps > 0) {
947 ath9k_hw_set_tsfadjust(ah, true);
948 ah->opmode = NL80211_IFTYPE_AP;
949 } else {
950 ath9k_hw_set_tsfadjust(ah, false);
951
952 if (iter_data.nmeshes)
953 ah->opmode = NL80211_IFTYPE_MESH_POINT;
954 else if (iter_data.nwds)
955 ah->opmode = NL80211_IFTYPE_AP;
956 else if (iter_data.nadhocs)
957 ah->opmode = NL80211_IFTYPE_ADHOC;
958 else
959 ah->opmode = NL80211_IFTYPE_STATION;
960 }
961
962 ath9k_hw_setopmode(ah);
963
964 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
965 ah->imask |= ATH9K_INT_TSFOOR;
966 else
967 ah->imask &= ~ATH9K_INT_TSFOOR;
968
969 ath9k_hw_set_interrupts(ah);
970
971 /*
972 * If we are changing the opmode to STATION,
973 * a beacon sync needs to be done.
974 */
975 if (ah->opmode == NL80211_IFTYPE_STATION &&
976 old_opmode == NL80211_IFTYPE_AP &&
977 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
978 ieee80211_iterate_active_interfaces_atomic(sc->hw,
979 ath9k_sta_vif_iter, sc);
980 }
981 }
982
983 static int ath9k_add_interface(struct ieee80211_hw *hw,
984 struct ieee80211_vif *vif)
985 {
986 struct ath_softc *sc = hw->priv;
987 struct ath_hw *ah = sc->sc_ah;
988 struct ath_common *common = ath9k_hw_common(ah);
989
990 mutex_lock(&sc->mutex);
991
992 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
993 sc->nvifs++;
994
995 ath9k_ps_wakeup(sc);
996 ath9k_calculate_summary_state(hw, vif);
997 ath9k_ps_restore(sc);
998
999 if (ath9k_uses_beacons(vif->type))
1000 ath9k_beacon_assign_slot(sc, vif);
1001
1002 mutex_unlock(&sc->mutex);
1003 return 0;
1004 }
1005
1006 static int ath9k_change_interface(struct ieee80211_hw *hw,
1007 struct ieee80211_vif *vif,
1008 enum nl80211_iftype new_type,
1009 bool p2p)
1010 {
1011 struct ath_softc *sc = hw->priv;
1012 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1013
1014 ath_dbg(common, CONFIG, "Change Interface\n");
1015 mutex_lock(&sc->mutex);
1016
1017 if (ath9k_uses_beacons(vif->type))
1018 ath9k_beacon_remove_slot(sc, vif);
1019
1020 vif->type = new_type;
1021 vif->p2p = p2p;
1022
1023 ath9k_ps_wakeup(sc);
1024 ath9k_calculate_summary_state(hw, vif);
1025 ath9k_ps_restore(sc);
1026
1027 if (ath9k_uses_beacons(vif->type))
1028 ath9k_beacon_assign_slot(sc, vif);
1029
1030 mutex_unlock(&sc->mutex);
1031 return 0;
1032 }
1033
1034 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1035 struct ieee80211_vif *vif)
1036 {
1037 struct ath_softc *sc = hw->priv;
1038 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1039
1040 ath_dbg(common, CONFIG, "Detach Interface\n");
1041
1042 mutex_lock(&sc->mutex);
1043
1044 sc->nvifs--;
1045
1046 if (ath9k_uses_beacons(vif->type))
1047 ath9k_beacon_remove_slot(sc, vif);
1048
1049 ath9k_ps_wakeup(sc);
1050 ath9k_calculate_summary_state(hw, NULL);
1051 ath9k_ps_restore(sc);
1052
1053 mutex_unlock(&sc->mutex);
1054 }
1055
1056 static void ath9k_enable_ps(struct ath_softc *sc)
1057 {
1058 struct ath_hw *ah = sc->sc_ah;
1059 struct ath_common *common = ath9k_hw_common(ah);
1060
1061 sc->ps_enabled = true;
1062 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1063 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1064 ah->imask |= ATH9K_INT_TIM_TIMER;
1065 ath9k_hw_set_interrupts(ah);
1066 }
1067 ath9k_hw_setrxabort(ah, 1);
1068 }
1069 ath_dbg(common, PS, "PowerSave enabled\n");
1070 }
1071
1072 static void ath9k_disable_ps(struct ath_softc *sc)
1073 {
1074 struct ath_hw *ah = sc->sc_ah;
1075 struct ath_common *common = ath9k_hw_common(ah);
1076
1077 sc->ps_enabled = false;
1078 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1079 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1080 ath9k_hw_setrxabort(ah, 0);
1081 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1082 PS_WAIT_FOR_CAB |
1083 PS_WAIT_FOR_PSPOLL_DATA |
1084 PS_WAIT_FOR_TX_ACK);
1085 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1086 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1087 ath9k_hw_set_interrupts(ah);
1088 }
1089 }
1090 ath_dbg(common, PS, "PowerSave disabled\n");
1091 }
1092
1093 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1094 {
1095 struct ath_softc *sc = hw->priv;
1096 struct ath_hw *ah = sc->sc_ah;
1097 struct ath_common *common = ath9k_hw_common(ah);
1098 struct ieee80211_conf *conf = &hw->conf;
1099 bool reset_channel = false;
1100
1101 ath9k_ps_wakeup(sc);
1102 mutex_lock(&sc->mutex);
1103
1104 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1105 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1106 if (sc->ps_idle) {
1107 ath_cancel_work(sc);
1108 ath9k_stop_btcoex(sc);
1109 } else {
1110 ath9k_start_btcoex(sc);
1111 /*
1112 * The chip needs a reset to properly wake up from
1113 * full sleep
1114 */
1115 reset_channel = ah->chip_fullsleep;
1116 }
1117 }
1118
1119 /*
1120 * We just prepare to enable PS. We have to wait until our AP has
1121 * ACK'd our null data frame to disable RX otherwise we'll ignore
1122 * those ACKs and end up retransmitting the same null data frames.
1123 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1124 */
1125 if (changed & IEEE80211_CONF_CHANGE_PS) {
1126 unsigned long flags;
1127 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1128 if (conf->flags & IEEE80211_CONF_PS)
1129 ath9k_enable_ps(sc);
1130 else
1131 ath9k_disable_ps(sc);
1132 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1133 }
1134
1135 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1136 if (conf->flags & IEEE80211_CONF_MONITOR) {
1137 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1138 sc->sc_ah->is_monitoring = true;
1139 } else {
1140 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1141 sc->sc_ah->is_monitoring = false;
1142 }
1143 }
1144
1145 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
1146 struct ieee80211_channel *curchan = hw->conf.channel;
1147 int pos = curchan->hw_value;
1148 int old_pos = -1;
1149 unsigned long flags;
1150
1151 if (ah->curchan)
1152 old_pos = ah->curchan - &ah->channels[0];
1153
1154 ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
1155 curchan->center_freq, conf->channel_type);
1156
1157 /* update survey stats for the old channel before switching */
1158 spin_lock_irqsave(&common->cc_lock, flags);
1159 ath_update_survey_stats(sc);
1160 spin_unlock_irqrestore(&common->cc_lock, flags);
1161
1162 /*
1163 * Preserve the current channel values, before updating
1164 * the same channel
1165 */
1166 if (ah->curchan && (old_pos == pos))
1167 ath9k_hw_getnf(ah, ah->curchan);
1168
1169 ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
1170 curchan, conf->channel_type);
1171
1172 /*
1173 * If the operating channel changes, change the survey in-use flags
1174 * along with it.
1175 * Reset the survey data for the new channel, unless we're switching
1176 * back to the operating channel from an off-channel operation.
1177 */
1178 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
1179 sc->cur_survey != &sc->survey[pos]) {
1180
1181 if (sc->cur_survey)
1182 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
1183
1184 sc->cur_survey = &sc->survey[pos];
1185
1186 memset(sc->cur_survey, 0, sizeof(struct survey_info));
1187 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
1188 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
1189 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
1190 }
1191
1192 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
1193 ath_err(common, "Unable to set channel\n");
1194 mutex_unlock(&sc->mutex);
1195 ath9k_ps_restore(sc);
1196 return -EINVAL;
1197 }
1198
1199 /*
1200 * The most recent snapshot of channel->noisefloor for the old
1201 * channel is only available after the hardware reset. Copy it to
1202 * the survey stats now.
1203 */
1204 if (old_pos >= 0)
1205 ath_update_survey_nf(sc, old_pos);
1206 }
1207
1208 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1209 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1210 sc->config.txpowlimit = 2 * conf->power_level;
1211 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1212 sc->config.txpowlimit, &sc->curtxpow);
1213 }
1214
1215 mutex_unlock(&sc->mutex);
1216 ath9k_ps_restore(sc);
1217
1218 return 0;
1219 }
1220
1221 #define SUPPORTED_FILTERS \
1222 (FIF_PROMISC_IN_BSS | \
1223 FIF_ALLMULTI | \
1224 FIF_CONTROL | \
1225 FIF_PSPOLL | \
1226 FIF_OTHER_BSS | \
1227 FIF_BCN_PRBRESP_PROMISC | \
1228 FIF_PROBE_REQ | \
1229 FIF_FCSFAIL)
1230
1231 /* FIXME: sc->sc_full_reset ? */
1232 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1233 unsigned int changed_flags,
1234 unsigned int *total_flags,
1235 u64 multicast)
1236 {
1237 struct ath_softc *sc = hw->priv;
1238 u32 rfilt;
1239
1240 changed_flags &= SUPPORTED_FILTERS;
1241 *total_flags &= SUPPORTED_FILTERS;
1242
1243 sc->rx.rxfilter = *total_flags;
1244 ath9k_ps_wakeup(sc);
1245 rfilt = ath_calcrxfilter(sc);
1246 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1247 ath9k_ps_restore(sc);
1248
1249 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1250 rfilt);
1251 }
1252
1253 static int ath9k_sta_add(struct ieee80211_hw *hw,
1254 struct ieee80211_vif *vif,
1255 struct ieee80211_sta *sta)
1256 {
1257 struct ath_softc *sc = hw->priv;
1258 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1259 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1260 struct ieee80211_key_conf ps_key = { };
1261
1262 ath_node_attach(sc, sta, vif);
1263
1264 if (vif->type != NL80211_IFTYPE_AP &&
1265 vif->type != NL80211_IFTYPE_AP_VLAN)
1266 return 0;
1267
1268 an->ps_key = ath_key_config(common, vif, sta, &ps_key);
1269
1270 return 0;
1271 }
1272
1273 static void ath9k_del_ps_key(struct ath_softc *sc,
1274 struct ieee80211_vif *vif,
1275 struct ieee80211_sta *sta)
1276 {
1277 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1278 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1279 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1280
1281 if (!an->ps_key)
1282 return;
1283
1284 ath_key_delete(common, &ps_key);
1285 }
1286
1287 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1288 struct ieee80211_vif *vif,
1289 struct ieee80211_sta *sta)
1290 {
1291 struct ath_softc *sc = hw->priv;
1292
1293 ath9k_del_ps_key(sc, vif, sta);
1294 ath_node_detach(sc, sta);
1295
1296 return 0;
1297 }
1298
1299 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1300 struct ieee80211_vif *vif,
1301 enum sta_notify_cmd cmd,
1302 struct ieee80211_sta *sta)
1303 {
1304 struct ath_softc *sc = hw->priv;
1305 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1306
1307 if (!sta->ht_cap.ht_supported)
1308 return;
1309
1310 switch (cmd) {
1311 case STA_NOTIFY_SLEEP:
1312 an->sleeping = true;
1313 ath_tx_aggr_sleep(sta, sc, an);
1314 break;
1315 case STA_NOTIFY_AWAKE:
1316 an->sleeping = false;
1317 ath_tx_aggr_wakeup(sc, an);
1318 break;
1319 }
1320 }
1321
1322 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1323 struct ieee80211_vif *vif, u16 queue,
1324 const struct ieee80211_tx_queue_params *params)
1325 {
1326 struct ath_softc *sc = hw->priv;
1327 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1328 struct ath_txq *txq;
1329 struct ath9k_tx_queue_info qi;
1330 int ret = 0;
1331
1332 if (queue >= WME_NUM_AC)
1333 return 0;
1334
1335 txq = sc->tx.txq_map[queue];
1336
1337 ath9k_ps_wakeup(sc);
1338 mutex_lock(&sc->mutex);
1339
1340 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1341
1342 qi.tqi_aifs = params->aifs;
1343 qi.tqi_cwmin = params->cw_min;
1344 qi.tqi_cwmax = params->cw_max;
1345 qi.tqi_burstTime = params->txop * 32;
1346
1347 ath_dbg(common, CONFIG,
1348 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1349 queue, txq->axq_qnum, params->aifs, params->cw_min,
1350 params->cw_max, params->txop);
1351
1352 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1353 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1354 if (ret)
1355 ath_err(common, "TXQ Update failed\n");
1356
1357 mutex_unlock(&sc->mutex);
1358 ath9k_ps_restore(sc);
1359
1360 return ret;
1361 }
1362
1363 static int ath9k_set_key(struct ieee80211_hw *hw,
1364 enum set_key_cmd cmd,
1365 struct ieee80211_vif *vif,
1366 struct ieee80211_sta *sta,
1367 struct ieee80211_key_conf *key)
1368 {
1369 struct ath_softc *sc = hw->priv;
1370 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1371 int ret = 0;
1372
1373 if (ath9k_modparam_nohwcrypt)
1374 return -ENOSPC;
1375
1376 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1377 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1378 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1379 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1380 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1381 /*
1382 * For now, disable hw crypto for the RSN IBSS group keys. This
1383 * could be optimized in the future to use a modified key cache
1384 * design to support per-STA RX GTK, but until that gets
1385 * implemented, use of software crypto for group addressed
1386 * frames is a acceptable to allow RSN IBSS to be used.
1387 */
1388 return -EOPNOTSUPP;
1389 }
1390
1391 mutex_lock(&sc->mutex);
1392 ath9k_ps_wakeup(sc);
1393 ath_dbg(common, CONFIG, "Set HW Key\n");
1394
1395 switch (cmd) {
1396 case SET_KEY:
1397 if (sta)
1398 ath9k_del_ps_key(sc, vif, sta);
1399
1400 ret = ath_key_config(common, vif, sta, key);
1401 if (ret >= 0) {
1402 key->hw_key_idx = ret;
1403 /* push IV and Michael MIC generation to stack */
1404 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1405 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1406 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1407 if (sc->sc_ah->sw_mgmt_crypto &&
1408 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1409 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1410 ret = 0;
1411 }
1412 break;
1413 case DISABLE_KEY:
1414 ath_key_delete(common, key);
1415 break;
1416 default:
1417 ret = -EINVAL;
1418 }
1419
1420 ath9k_ps_restore(sc);
1421 mutex_unlock(&sc->mutex);
1422
1423 return ret;
1424 }
1425
1426 static void ath9k_set_assoc_state(struct ath_softc *sc,
1427 struct ieee80211_vif *vif)
1428 {
1429 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1430 struct ath_vif *avp = (void *)vif->drv_priv;
1431 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1432 unsigned long flags;
1433
1434 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1435 avp->primary_sta_vif = true;
1436
1437 /*
1438 * Set the AID, BSSID and do beacon-sync only when
1439 * the HW opmode is STATION.
1440 *
1441 * But the primary bit is set above in any case.
1442 */
1443 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1444 return;
1445
1446 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1447 common->curaid = bss_conf->aid;
1448 ath9k_hw_write_associd(sc->sc_ah);
1449
1450 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1451 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1452
1453 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1454 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1455 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1456
1457 ath_dbg(common, CONFIG,
1458 "Primary Station interface: %pM, BSSID: %pM\n",
1459 vif->addr, common->curbssid);
1460 }
1461
1462 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1463 {
1464 struct ath_softc *sc = data;
1465 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1466
1467 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
1468 return;
1469
1470 if (bss_conf->assoc)
1471 ath9k_set_assoc_state(sc, vif);
1472 }
1473
1474 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1475 struct ieee80211_vif *vif,
1476 struct ieee80211_bss_conf *bss_conf,
1477 u32 changed)
1478 {
1479 #define CHECK_ANI \
1480 (BSS_CHANGED_ASSOC | \
1481 BSS_CHANGED_IBSS | \
1482 BSS_CHANGED_BEACON_ENABLED)
1483
1484 struct ath_softc *sc = hw->priv;
1485 struct ath_hw *ah = sc->sc_ah;
1486 struct ath_common *common = ath9k_hw_common(ah);
1487 struct ath_vif *avp = (void *)vif->drv_priv;
1488 int slottime;
1489
1490 ath9k_ps_wakeup(sc);
1491 mutex_lock(&sc->mutex);
1492
1493 if (changed & BSS_CHANGED_ASSOC) {
1494 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1495 bss_conf->bssid, bss_conf->assoc);
1496
1497 if (avp->primary_sta_vif && !bss_conf->assoc) {
1498 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1499 avp->primary_sta_vif = false;
1500
1501 if (ah->opmode == NL80211_IFTYPE_STATION)
1502 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1503 }
1504
1505 ieee80211_iterate_active_interfaces_atomic(sc->hw,
1506 ath9k_bss_assoc_iter, sc);
1507
1508 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1509 ah->opmode == NL80211_IFTYPE_STATION) {
1510 memset(common->curbssid, 0, ETH_ALEN);
1511 common->curaid = 0;
1512 ath9k_hw_write_associd(sc->sc_ah);
1513 }
1514 }
1515
1516 if (changed & BSS_CHANGED_IBSS) {
1517 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1518 common->curaid = bss_conf->aid;
1519 ath9k_hw_write_associd(sc->sc_ah);
1520 }
1521
1522 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1523 (changed & BSS_CHANGED_BEACON_INT)) {
1524 if (ah->opmode == NL80211_IFTYPE_AP &&
1525 bss_conf->enable_beacon)
1526 ath9k_set_tsfadjust(sc, vif);
1527 if (ath9k_allow_beacon_config(sc, vif))
1528 ath9k_beacon_config(sc, vif, changed);
1529 }
1530
1531 if (changed & BSS_CHANGED_ERP_SLOT) {
1532 if (bss_conf->use_short_slot)
1533 slottime = 9;
1534 else
1535 slottime = 20;
1536 if (vif->type == NL80211_IFTYPE_AP) {
1537 /*
1538 * Defer update, so that connected stations can adjust
1539 * their settings at the same time.
1540 * See beacon.c for more details
1541 */
1542 sc->beacon.slottime = slottime;
1543 sc->beacon.updateslot = UPDATE;
1544 } else {
1545 ah->slottime = slottime;
1546 ath9k_hw_init_global_settings(ah);
1547 }
1548 }
1549
1550 if (changed & CHECK_ANI)
1551 ath_check_ani(sc);
1552
1553 mutex_unlock(&sc->mutex);
1554 ath9k_ps_restore(sc);
1555
1556 #undef CHECK_ANI
1557 }
1558
1559 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1560 {
1561 struct ath_softc *sc = hw->priv;
1562 u64 tsf;
1563
1564 mutex_lock(&sc->mutex);
1565 ath9k_ps_wakeup(sc);
1566 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1567 ath9k_ps_restore(sc);
1568 mutex_unlock(&sc->mutex);
1569
1570 return tsf;
1571 }
1572
1573 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1574 struct ieee80211_vif *vif,
1575 u64 tsf)
1576 {
1577 struct ath_softc *sc = hw->priv;
1578
1579 mutex_lock(&sc->mutex);
1580 ath9k_ps_wakeup(sc);
1581 ath9k_hw_settsf64(sc->sc_ah, tsf);
1582 ath9k_ps_restore(sc);
1583 mutex_unlock(&sc->mutex);
1584 }
1585
1586 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1587 {
1588 struct ath_softc *sc = hw->priv;
1589
1590 mutex_lock(&sc->mutex);
1591
1592 ath9k_ps_wakeup(sc);
1593 ath9k_hw_reset_tsf(sc->sc_ah);
1594 ath9k_ps_restore(sc);
1595
1596 mutex_unlock(&sc->mutex);
1597 }
1598
1599 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1600 struct ieee80211_vif *vif,
1601 enum ieee80211_ampdu_mlme_action action,
1602 struct ieee80211_sta *sta,
1603 u16 tid, u16 *ssn, u8 buf_size)
1604 {
1605 struct ath_softc *sc = hw->priv;
1606 int ret = 0;
1607
1608 local_bh_disable();
1609
1610 switch (action) {
1611 case IEEE80211_AMPDU_RX_START:
1612 break;
1613 case IEEE80211_AMPDU_RX_STOP:
1614 break;
1615 case IEEE80211_AMPDU_TX_START:
1616 ath9k_ps_wakeup(sc);
1617 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1618 if (!ret)
1619 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1620 ath9k_ps_restore(sc);
1621 break;
1622 case IEEE80211_AMPDU_TX_STOP:
1623 ath9k_ps_wakeup(sc);
1624 ath_tx_aggr_stop(sc, sta, tid);
1625 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1626 ath9k_ps_restore(sc);
1627 break;
1628 case IEEE80211_AMPDU_TX_OPERATIONAL:
1629 ath9k_ps_wakeup(sc);
1630 ath_tx_aggr_resume(sc, sta, tid);
1631 ath9k_ps_restore(sc);
1632 break;
1633 default:
1634 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1635 }
1636
1637 local_bh_enable();
1638
1639 return ret;
1640 }
1641
1642 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1643 struct survey_info *survey)
1644 {
1645 struct ath_softc *sc = hw->priv;
1646 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1647 struct ieee80211_supported_band *sband;
1648 struct ieee80211_channel *chan;
1649 unsigned long flags;
1650 int pos;
1651
1652 spin_lock_irqsave(&common->cc_lock, flags);
1653 if (idx == 0)
1654 ath_update_survey_stats(sc);
1655
1656 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1657 if (sband && idx >= sband->n_channels) {
1658 idx -= sband->n_channels;
1659 sband = NULL;
1660 }
1661
1662 if (!sband)
1663 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1664
1665 if (!sband || idx >= sband->n_channels) {
1666 spin_unlock_irqrestore(&common->cc_lock, flags);
1667 return -ENOENT;
1668 }
1669
1670 chan = &sband->channels[idx];
1671 pos = chan->hw_value;
1672 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1673 survey->channel = chan;
1674 spin_unlock_irqrestore(&common->cc_lock, flags);
1675
1676 return 0;
1677 }
1678
1679 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1680 {
1681 struct ath_softc *sc = hw->priv;
1682 struct ath_hw *ah = sc->sc_ah;
1683
1684 mutex_lock(&sc->mutex);
1685 ah->coverage_class = coverage_class;
1686
1687 ath9k_ps_wakeup(sc);
1688 ath9k_hw_init_global_settings(ah);
1689 ath9k_ps_restore(sc);
1690
1691 mutex_unlock(&sc->mutex);
1692 }
1693
1694 static void ath9k_flush(struct ieee80211_hw *hw, bool drop)
1695 {
1696 struct ath_softc *sc = hw->priv;
1697 struct ath_hw *ah = sc->sc_ah;
1698 struct ath_common *common = ath9k_hw_common(ah);
1699 int timeout = 200; /* ms */
1700 int i, j;
1701 bool drain_txq;
1702
1703 mutex_lock(&sc->mutex);
1704 cancel_delayed_work_sync(&sc->tx_complete_work);
1705
1706 if (ah->ah_flags & AH_UNPLUGGED) {
1707 ath_dbg(common, ANY, "Device has been unplugged!\n");
1708 mutex_unlock(&sc->mutex);
1709 return;
1710 }
1711
1712 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
1713 ath_dbg(common, ANY, "Device not present\n");
1714 mutex_unlock(&sc->mutex);
1715 return;
1716 }
1717
1718 for (j = 0; j < timeout; j++) {
1719 bool npend = false;
1720
1721 if (j)
1722 usleep_range(1000, 2000);
1723
1724 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1725 if (!ATH_TXQ_SETUP(sc, i))
1726 continue;
1727
1728 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1729
1730 if (npend)
1731 break;
1732 }
1733
1734 if (!npend)
1735 break;
1736 }
1737
1738 if (drop) {
1739 ath9k_ps_wakeup(sc);
1740 spin_lock_bh(&sc->sc_pcu_lock);
1741 drain_txq = ath_drain_all_txq(sc, false);
1742 spin_unlock_bh(&sc->sc_pcu_lock);
1743
1744 if (!drain_txq)
1745 ath_reset(sc, false);
1746
1747 ath9k_ps_restore(sc);
1748 ieee80211_wake_queues(hw);
1749 }
1750
1751 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1752 mutex_unlock(&sc->mutex);
1753 }
1754
1755 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1756 {
1757 struct ath_softc *sc = hw->priv;
1758 int i;
1759
1760 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1761 if (!ATH_TXQ_SETUP(sc, i))
1762 continue;
1763
1764 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1765 return true;
1766 }
1767 return false;
1768 }
1769
1770 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
1771 {
1772 struct ath_softc *sc = hw->priv;
1773 struct ath_hw *ah = sc->sc_ah;
1774 struct ieee80211_vif *vif;
1775 struct ath_vif *avp;
1776 struct ath_buf *bf;
1777 struct ath_tx_status ts;
1778 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1779 int status;
1780
1781 vif = sc->beacon.bslot[0];
1782 if (!vif)
1783 return 0;
1784
1785 if (!vif->bss_conf.enable_beacon)
1786 return 0;
1787
1788 avp = (void *)vif->drv_priv;
1789
1790 if (!sc->beacon.tx_processed && !edma) {
1791 tasklet_disable(&sc->bcon_tasklet);
1792
1793 bf = avp->av_bcbuf;
1794 if (!bf || !bf->bf_mpdu)
1795 goto skip;
1796
1797 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1798 if (status == -EINPROGRESS)
1799 goto skip;
1800
1801 sc->beacon.tx_processed = true;
1802 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1803
1804 skip:
1805 tasklet_enable(&sc->bcon_tasklet);
1806 }
1807
1808 return sc->beacon.tx_last;
1809 }
1810
1811 static int ath9k_get_stats(struct ieee80211_hw *hw,
1812 struct ieee80211_low_level_stats *stats)
1813 {
1814 struct ath_softc *sc = hw->priv;
1815 struct ath_hw *ah = sc->sc_ah;
1816 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1817
1818 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1819 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1820 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1821 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1822 return 0;
1823 }
1824
1825 static u32 fill_chainmask(u32 cap, u32 new)
1826 {
1827 u32 filled = 0;
1828 int i;
1829
1830 for (i = 0; cap && new; i++, cap >>= 1) {
1831 if (!(cap & BIT(0)))
1832 continue;
1833
1834 if (new & BIT(0))
1835 filled |= BIT(i);
1836
1837 new >>= 1;
1838 }
1839
1840 return filled;
1841 }
1842
1843 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
1844 {
1845 switch (val & 0x7) {
1846 case 0x1:
1847 case 0x3:
1848 case 0x7:
1849 return true;
1850 case 0x2:
1851 return (ah->caps.rx_chainmask == 1);
1852 default:
1853 return false;
1854 }
1855 }
1856
1857 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
1858 {
1859 struct ath_softc *sc = hw->priv;
1860 struct ath_hw *ah = sc->sc_ah;
1861
1862 if (ah->caps.rx_chainmask != 1)
1863 rx_ant |= tx_ant;
1864
1865 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
1866 return -EINVAL;
1867
1868 sc->ant_rx = rx_ant;
1869 sc->ant_tx = tx_ant;
1870
1871 if (ah->caps.rx_chainmask == 1)
1872 return 0;
1873
1874 /* AR9100 runs into calibration issues if not all rx chains are enabled */
1875 if (AR_SREV_9100(ah))
1876 ah->rxchainmask = 0x7;
1877 else
1878 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
1879
1880 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
1881 ath9k_reload_chainmask_settings(sc);
1882
1883 return 0;
1884 }
1885
1886 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
1887 {
1888 struct ath_softc *sc = hw->priv;
1889
1890 *tx_ant = sc->ant_tx;
1891 *rx_ant = sc->ant_rx;
1892 return 0;
1893 }
1894
1895 #ifdef CONFIG_ATH9K_DEBUGFS
1896
1897 /* Ethtool support for get-stats */
1898
1899 #define AMKSTR(nm) #nm "_BE", #nm "_BK", #nm "_VI", #nm "_VO"
1900 static const char ath9k_gstrings_stats[][ETH_GSTRING_LEN] = {
1901 "tx_pkts_nic",
1902 "tx_bytes_nic",
1903 "rx_pkts_nic",
1904 "rx_bytes_nic",
1905 AMKSTR(d_tx_pkts),
1906 AMKSTR(d_tx_bytes),
1907 AMKSTR(d_tx_mpdus_queued),
1908 AMKSTR(d_tx_mpdus_completed),
1909 AMKSTR(d_tx_mpdu_xretries),
1910 AMKSTR(d_tx_aggregates),
1911 AMKSTR(d_tx_ampdus_queued_hw),
1912 AMKSTR(d_tx_ampdus_queued_sw),
1913 AMKSTR(d_tx_ampdus_completed),
1914 AMKSTR(d_tx_ampdu_retries),
1915 AMKSTR(d_tx_ampdu_xretries),
1916 AMKSTR(d_tx_fifo_underrun),
1917 AMKSTR(d_tx_op_exceeded),
1918 AMKSTR(d_tx_timer_expiry),
1919 AMKSTR(d_tx_desc_cfg_err),
1920 AMKSTR(d_tx_data_underrun),
1921 AMKSTR(d_tx_delim_underrun),
1922
1923 "d_rx_decrypt_crc_err",
1924 "d_rx_phy_err",
1925 "d_rx_mic_err",
1926 "d_rx_pre_delim_crc_err",
1927 "d_rx_post_delim_crc_err",
1928 "d_rx_decrypt_busy_err",
1929
1930 "d_rx_phyerr_radar",
1931 "d_rx_phyerr_ofdm_timing",
1932 "d_rx_phyerr_cck_timing",
1933
1934 };
1935 #define ATH9K_SSTATS_LEN ARRAY_SIZE(ath9k_gstrings_stats)
1936
1937 static void ath9k_get_et_strings(struct ieee80211_hw *hw,
1938 struct ieee80211_vif *vif,
1939 u32 sset, u8 *data)
1940 {
1941 if (sset == ETH_SS_STATS)
1942 memcpy(data, *ath9k_gstrings_stats,
1943 sizeof(ath9k_gstrings_stats));
1944 }
1945
1946 static int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
1947 struct ieee80211_vif *vif, int sset)
1948 {
1949 if (sset == ETH_SS_STATS)
1950 return ATH9K_SSTATS_LEN;
1951 return 0;
1952 }
1953
1954 #define PR_QNUM(_n) (sc->tx.txq_map[_n]->axq_qnum)
1955 #define AWDATA(elem) \
1956 do { \
1957 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].elem; \
1958 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].elem; \
1959 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].elem; \
1960 data[i++] = sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].elem; \
1961 } while (0)
1962
1963 #define AWDATA_RX(elem) \
1964 do { \
1965 data[i++] = sc->debug.stats.rxstats.elem; \
1966 } while (0)
1967
1968 static void ath9k_get_et_stats(struct ieee80211_hw *hw,
1969 struct ieee80211_vif *vif,
1970 struct ethtool_stats *stats, u64 *data)
1971 {
1972 struct ath_softc *sc = hw->priv;
1973 int i = 0;
1974
1975 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_pkts_all +
1976 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_pkts_all +
1977 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_pkts_all +
1978 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_pkts_all);
1979 data[i++] = (sc->debug.stats.txstats[PR_QNUM(WME_AC_BE)].tx_bytes_all +
1980 sc->debug.stats.txstats[PR_QNUM(WME_AC_BK)].tx_bytes_all +
1981 sc->debug.stats.txstats[PR_QNUM(WME_AC_VI)].tx_bytes_all +
1982 sc->debug.stats.txstats[PR_QNUM(WME_AC_VO)].tx_bytes_all);
1983 AWDATA_RX(rx_pkts_all);
1984 AWDATA_RX(rx_bytes_all);
1985
1986 AWDATA(tx_pkts_all);
1987 AWDATA(tx_bytes_all);
1988 AWDATA(queued);
1989 AWDATA(completed);
1990 AWDATA(xretries);
1991 AWDATA(a_aggr);
1992 AWDATA(a_queued_hw);
1993 AWDATA(a_queued_sw);
1994 AWDATA(a_completed);
1995 AWDATA(a_retries);
1996 AWDATA(a_xretries);
1997 AWDATA(fifo_underrun);
1998 AWDATA(xtxop);
1999 AWDATA(timer_exp);
2000 AWDATA(desc_cfg_err);
2001 AWDATA(data_underrun);
2002 AWDATA(delim_underrun);
2003
2004 AWDATA_RX(decrypt_crc_err);
2005 AWDATA_RX(phy_err);
2006 AWDATA_RX(mic_err);
2007 AWDATA_RX(pre_delim_crc_err);
2008 AWDATA_RX(post_delim_crc_err);
2009 AWDATA_RX(decrypt_busy_err);
2010
2011 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_RADAR]);
2012 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_OFDM_TIMING]);
2013 AWDATA_RX(phy_err_stats[ATH9K_PHYERR_CCK_TIMING]);
2014
2015 WARN_ON(i != ATH9K_SSTATS_LEN);
2016 }
2017
2018 /* End of ethtool get-stats functions */
2019
2020 #endif
2021
2022
2023 #ifdef CONFIG_PM_SLEEP
2024
2025 static void ath9k_wow_map_triggers(struct ath_softc *sc,
2026 struct cfg80211_wowlan *wowlan,
2027 u32 *wow_triggers)
2028 {
2029 if (wowlan->disconnect)
2030 *wow_triggers |= AH_WOW_LINK_CHANGE |
2031 AH_WOW_BEACON_MISS;
2032 if (wowlan->magic_pkt)
2033 *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
2034
2035 if (wowlan->n_patterns)
2036 *wow_triggers |= AH_WOW_USER_PATTERN_EN;
2037
2038 sc->wow_enabled = *wow_triggers;
2039
2040 }
2041
2042 static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
2043 {
2044 struct ath_hw *ah = sc->sc_ah;
2045 struct ath_common *common = ath9k_hw_common(ah);
2046 struct ath9k_hw_capabilities *pcaps = &ah->caps;
2047 int pattern_count = 0;
2048 int i, byte_cnt;
2049 u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
2050 u8 dis_deauth_mask[MAX_PATTERN_SIZE];
2051
2052 memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
2053 memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
2054
2055 /*
2056 * Create Dissassociate / Deauthenticate packet filter
2057 *
2058 * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
2059 * +--------------+----------+---------+--------+--------+----
2060 * + Frame Control+ Duration + DA + SA + BSSID +
2061 * +--------------+----------+---------+--------+--------+----
2062 *
2063 * The above is the management frame format for disassociate/
2064 * deauthenticate pattern, from this we need to match the first byte
2065 * of 'Frame Control' and DA, SA, and BSSID fields
2066 * (skipping 2nd byte of FC and Duration feild.
2067 *
2068 * Disassociate pattern
2069 * --------------------
2070 * Frame control = 00 00 1010
2071 * DA, SA, BSSID = x:x:x:x:x:x
2072 * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2073 * | x:x:x:x:x:x -- 22 bytes
2074 *
2075 * Deauthenticate pattern
2076 * ----------------------
2077 * Frame control = 00 00 1100
2078 * DA, SA, BSSID = x:x:x:x:x:x
2079 * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
2080 * | x:x:x:x:x:x -- 22 bytes
2081 */
2082
2083 /* Create Disassociate Pattern first */
2084
2085 byte_cnt = 0;
2086
2087 /* Fill out the mask with all FF's */
2088
2089 for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
2090 dis_deauth_mask[i] = 0xff;
2091
2092 /* copy the first byte of frame control field */
2093 dis_deauth_pattern[byte_cnt] = 0xa0;
2094 byte_cnt++;
2095
2096 /* skip 2nd byte of frame control and Duration field */
2097 byte_cnt += 3;
2098
2099 /*
2100 * need not match the destination mac address, it can be a broadcast
2101 * mac address or an unicast to this station
2102 */
2103 byte_cnt += 6;
2104
2105 /* copy the source mac address */
2106 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2107
2108 byte_cnt += 6;
2109
2110 /* copy the bssid, its same as the source mac address */
2111
2112 memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
2113
2114 /* Create Disassociate pattern mask */
2115
2116 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
2117
2118 if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
2119 /*
2120 * for AR9280, because of hardware limitation, the
2121 * first 4 bytes have to be matched for all patterns.
2122 * the mask for disassociation and de-auth pattern
2123 * matching need to enable the first 4 bytes.
2124 * also the duration field needs to be filled.
2125 */
2126 dis_deauth_mask[0] = 0xf0;
2127
2128 /*
2129 * fill in duration field
2130 FIXME: what is the exact value ?
2131 */
2132 dis_deauth_pattern[2] = 0xff;
2133 dis_deauth_pattern[3] = 0xff;
2134 } else {
2135 dis_deauth_mask[0] = 0xfe;
2136 }
2137
2138 dis_deauth_mask[1] = 0x03;
2139 dis_deauth_mask[2] = 0xc0;
2140 } else {
2141 dis_deauth_mask[0] = 0xef;
2142 dis_deauth_mask[1] = 0x3f;
2143 dis_deauth_mask[2] = 0x00;
2144 dis_deauth_mask[3] = 0xfc;
2145 }
2146
2147 ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
2148
2149 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2150 pattern_count, byte_cnt);
2151
2152 pattern_count++;
2153 /*
2154 * for de-authenticate pattern, only the first byte of the frame
2155 * control field gets changed from 0xA0 to 0xC0
2156 */
2157 dis_deauth_pattern[0] = 0xC0;
2158
2159 ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
2160 pattern_count, byte_cnt);
2161
2162 }
2163
2164 static void ath9k_wow_add_pattern(struct ath_softc *sc,
2165 struct cfg80211_wowlan *wowlan)
2166 {
2167 struct ath_hw *ah = sc->sc_ah;
2168 struct ath9k_wow_pattern *wow_pattern = NULL;
2169 struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
2170 int mask_len;
2171 s8 i = 0;
2172
2173 if (!wowlan->n_patterns)
2174 return;
2175
2176 /*
2177 * Add the new user configured patterns
2178 */
2179 for (i = 0; i < wowlan->n_patterns; i++) {
2180
2181 wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
2182
2183 if (!wow_pattern)
2184 return;
2185
2186 /*
2187 * TODO: convert the generic user space pattern to
2188 * appropriate chip specific/802.11 pattern.
2189 */
2190
2191 mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
2192 memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
2193 memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
2194 memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
2195 patterns[i].pattern_len);
2196 memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
2197 wow_pattern->pattern_len = patterns[i].pattern_len;
2198
2199 /*
2200 * just need to take care of deauth and disssoc pattern,
2201 * make sure we don't overwrite them.
2202 */
2203
2204 ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
2205 wow_pattern->mask_bytes,
2206 i + 2,
2207 wow_pattern->pattern_len);
2208 kfree(wow_pattern);
2209
2210 }
2211
2212 }
2213
2214 static int ath9k_suspend(struct ieee80211_hw *hw,
2215 struct cfg80211_wowlan *wowlan)
2216 {
2217 struct ath_softc *sc = hw->priv;
2218 struct ath_hw *ah = sc->sc_ah;
2219 struct ath_common *common = ath9k_hw_common(ah);
2220 u32 wow_triggers_enabled = 0;
2221 int ret = 0;
2222
2223 mutex_lock(&sc->mutex);
2224
2225 ath_cancel_work(sc);
2226 ath_stop_ani(sc);
2227 del_timer_sync(&sc->rx_poll_timer);
2228
2229 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
2230 ath_dbg(common, ANY, "Device not present\n");
2231 ret = -EINVAL;
2232 goto fail_wow;
2233 }
2234
2235 if (WARN_ON(!wowlan)) {
2236 ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
2237 ret = -EINVAL;
2238 goto fail_wow;
2239 }
2240
2241 if (!device_can_wakeup(sc->dev)) {
2242 ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
2243 ret = 1;
2244 goto fail_wow;
2245 }
2246
2247 /*
2248 * none of the sta vifs are associated
2249 * and we are not currently handling multivif
2250 * cases, for instance we have to seperately
2251 * configure 'keep alive frame' for each
2252 * STA.
2253 */
2254
2255 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
2256 ath_dbg(common, WOW, "None of the STA vifs are associated\n");
2257 ret = 1;
2258 goto fail_wow;
2259 }
2260
2261 if (sc->nvifs > 1) {
2262 ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
2263 ret = 1;
2264 goto fail_wow;
2265 }
2266
2267 ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
2268
2269 ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
2270 wow_triggers_enabled);
2271
2272 ath9k_ps_wakeup(sc);
2273
2274 ath9k_stop_btcoex(sc);
2275
2276 /*
2277 * Enable wake up on recieving disassoc/deauth
2278 * frame by default.
2279 */
2280 ath9k_wow_add_disassoc_deauth_pattern(sc);
2281
2282 if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
2283 ath9k_wow_add_pattern(sc, wowlan);
2284
2285 spin_lock_bh(&sc->sc_pcu_lock);
2286 /*
2287 * To avoid false wake, we enable beacon miss interrupt only
2288 * when we go to sleep. We save the current interrupt mask
2289 * so we can restore it after the system wakes up
2290 */
2291 sc->wow_intr_before_sleep = ah->imask;
2292 ah->imask &= ~ATH9K_INT_GLOBAL;
2293 ath9k_hw_disable_interrupts(ah);
2294 ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
2295 ath9k_hw_set_interrupts(ah);
2296 ath9k_hw_enable_interrupts(ah);
2297
2298 spin_unlock_bh(&sc->sc_pcu_lock);
2299
2300 /*
2301 * we can now sync irq and kill any running tasklets, since we already
2302 * disabled interrupts and not holding a spin lock
2303 */
2304 synchronize_irq(sc->irq);
2305 tasklet_kill(&sc->intr_tq);
2306
2307 ath9k_hw_wow_enable(ah, wow_triggers_enabled);
2308
2309 ath9k_ps_restore(sc);
2310 ath_dbg(common, ANY, "WoW enabled in ath9k\n");
2311 atomic_inc(&sc->wow_sleep_proc_intr);
2312
2313 fail_wow:
2314 mutex_unlock(&sc->mutex);
2315 return ret;
2316 }
2317
2318 static int ath9k_resume(struct ieee80211_hw *hw)
2319 {
2320 struct ath_softc *sc = hw->priv;
2321 struct ath_hw *ah = sc->sc_ah;
2322 struct ath_common *common = ath9k_hw_common(ah);
2323 u32 wow_status;
2324
2325 mutex_lock(&sc->mutex);
2326
2327 ath9k_ps_wakeup(sc);
2328
2329 spin_lock_bh(&sc->sc_pcu_lock);
2330
2331 ath9k_hw_disable_interrupts(ah);
2332 ah->imask = sc->wow_intr_before_sleep;
2333 ath9k_hw_set_interrupts(ah);
2334 ath9k_hw_enable_interrupts(ah);
2335
2336 spin_unlock_bh(&sc->sc_pcu_lock);
2337
2338 wow_status = ath9k_hw_wow_wakeup(ah);
2339
2340 if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
2341 /*
2342 * some devices may not pick beacon miss
2343 * as the reason they woke up so we add
2344 * that here for that shortcoming.
2345 */
2346 wow_status |= AH_WOW_BEACON_MISS;
2347 atomic_dec(&sc->wow_got_bmiss_intr);
2348 ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
2349 }
2350
2351 atomic_dec(&sc->wow_sleep_proc_intr);
2352
2353 if (wow_status) {
2354 ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
2355 ath9k_hw_wow_event_to_string(wow_status), wow_status);
2356 }
2357
2358 ath_restart_work(sc);
2359 ath9k_start_btcoex(sc);
2360
2361 ath9k_ps_restore(sc);
2362 mutex_unlock(&sc->mutex);
2363
2364 return 0;
2365 }
2366
2367 static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
2368 {
2369 struct ath_softc *sc = hw->priv;
2370
2371 mutex_lock(&sc->mutex);
2372 device_init_wakeup(sc->dev, 1);
2373 device_set_wakeup_enable(sc->dev, enabled);
2374 mutex_unlock(&sc->mutex);
2375 }
2376
2377 #endif
2378
2379 struct ieee80211_ops ath9k_ops = {
2380 .tx = ath9k_tx,
2381 .start = ath9k_start,
2382 .stop = ath9k_stop,
2383 .add_interface = ath9k_add_interface,
2384 .change_interface = ath9k_change_interface,
2385 .remove_interface = ath9k_remove_interface,
2386 .config = ath9k_config,
2387 .configure_filter = ath9k_configure_filter,
2388 .sta_add = ath9k_sta_add,
2389 .sta_remove = ath9k_sta_remove,
2390 .sta_notify = ath9k_sta_notify,
2391 .conf_tx = ath9k_conf_tx,
2392 .bss_info_changed = ath9k_bss_info_changed,
2393 .set_key = ath9k_set_key,
2394 .get_tsf = ath9k_get_tsf,
2395 .set_tsf = ath9k_set_tsf,
2396 .reset_tsf = ath9k_reset_tsf,
2397 .ampdu_action = ath9k_ampdu_action,
2398 .get_survey = ath9k_get_survey,
2399 .rfkill_poll = ath9k_rfkill_poll_state,
2400 .set_coverage_class = ath9k_set_coverage_class,
2401 .flush = ath9k_flush,
2402 .tx_frames_pending = ath9k_tx_frames_pending,
2403 .tx_last_beacon = ath9k_tx_last_beacon,
2404 .get_stats = ath9k_get_stats,
2405 .set_antenna = ath9k_set_antenna,
2406 .get_antenna = ath9k_get_antenna,
2407
2408 #ifdef CONFIG_PM_SLEEP
2409 .suspend = ath9k_suspend,
2410 .resume = ath9k_resume,
2411 .set_wakeup = ath9k_set_wakeup,
2412 #endif
2413
2414 #ifdef CONFIG_ATH9K_DEBUGFS
2415 .get_et_sset_count = ath9k_get_et_sset_count,
2416 .get_et_stats = ath9k_get_et_stats,
2417 .get_et_strings = ath9k_get_et_strings,
2418 #endif
2419 };
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