2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 static struct ieee80211_hw
* ath_get_virt_hw(struct ath_softc
*sc
,
20 struct ieee80211_hdr
*hdr
)
22 struct ieee80211_hw
*hw
= sc
->pri_wiphy
->hw
;
25 spin_lock_bh(&sc
->wiphy_lock
);
26 for (i
= 0; i
< sc
->num_sec_wiphy
; i
++) {
27 struct ath_wiphy
*aphy
= sc
->sec_wiphy
[i
];
30 if (compare_ether_addr(hdr
->addr1
, aphy
->hw
->wiphy
->perm_addr
)
36 spin_unlock_bh(&sc
->wiphy_lock
);
41 * Setup and link descriptors.
43 * 11N: we can no longer afford to self link the last descriptor.
44 * MAC acknowledges BA status as long as it copies frames to host
45 * buffer (or rx fifo). This can incorrectly acknowledge packets
46 * to a sender if last desc is self-linked.
48 static void ath_rx_buf_link(struct ath_softc
*sc
, struct ath_buf
*bf
)
50 struct ath_hw
*ah
= sc
->sc_ah
;
57 ds
->ds_link
= 0; /* link to null */
58 ds
->ds_data
= bf
->bf_buf_addr
;
60 /* virtual addr of the beginning of the buffer. */
63 ds
->ds_vdata
= skb
->data
;
65 /* setup rx descriptors. The rx.bufsize here tells the harware
66 * how much data it can DMA to us and that we are prepared
68 ath9k_hw_setuprxdesc(ah
, ds
,
72 if (sc
->rx
.rxlink
== NULL
)
73 ath9k_hw_putrxbuf(ah
, bf
->bf_daddr
);
75 *sc
->rx
.rxlink
= bf
->bf_daddr
;
77 sc
->rx
.rxlink
= &ds
->ds_link
;
81 static void ath_setdefantenna(struct ath_softc
*sc
, u32 antenna
)
83 /* XXX block beacon interrupts */
84 ath9k_hw_setantenna(sc
->sc_ah
, antenna
);
85 sc
->rx
.defant
= antenna
;
86 sc
->rx
.rxotherant
= 0;
90 * Extend 15-bit time stamp from rx descriptor to
91 * a full 64-bit TSF using the current h/w TSF.
93 static u64
ath_extend_tsf(struct ath_softc
*sc
, u32 rstamp
)
97 tsf
= ath9k_hw_gettsf64(sc
->sc_ah
);
98 if ((tsf
& 0x7fff) < rstamp
)
100 return (tsf
& ~0x7fff) | rstamp
;
103 static struct sk_buff
*ath_rxbuf_alloc(struct ath_softc
*sc
, u32 len
, gfp_t gfp_mask
)
109 * Cache-line-align. This is important (for the
110 * 5210 at least) as not doing so causes bogus data
114 /* Note: the kernel can allocate a value greater than
115 * what we ask it to give us. We really only need 4 KB as that
116 * is this hardware supports and in fact we need at least 3849
117 * as that is the MAX AMSDU size this hardware supports.
118 * Unfortunately this means we may get 8 KB here from the
119 * kernel... and that is actually what is observed on some
121 skb
= __dev_alloc_skb(len
+ sc
->cachelsz
- 1, gfp_mask
);
123 off
= ((unsigned long) skb
->data
) % sc
->cachelsz
;
125 skb_reserve(skb
, sc
->cachelsz
- off
);
127 DPRINTF(sc
, ATH_DBG_FATAL
,
128 "skbuff alloc of size %u failed\n", len
);
136 * For Decrypt or Demic errors, we only mark packet status here and always push
137 * up the frame up to let mac80211 handle the actual error case, be it no
138 * decryption key or real decryption error. This let us keep statistics there.
140 static int ath_rx_prepare(struct sk_buff
*skb
, struct ath_desc
*ds
,
141 struct ieee80211_rx_status
*rx_status
, bool *decrypt_error
,
142 struct ath_softc
*sc
)
144 struct ieee80211_hdr
*hdr
;
147 struct ieee80211_hw
*hw
;
149 hdr
= (struct ieee80211_hdr
*)skb
->data
;
150 fc
= hdr
->frame_control
;
151 memset(rx_status
, 0, sizeof(struct ieee80211_rx_status
));
152 hw
= ath_get_virt_hw(sc
, hdr
);
154 if (ds
->ds_rxstat
.rs_more
) {
156 * Frame spans multiple descriptors; this cannot happen yet
157 * as we don't support jumbograms. If not in monitor mode,
158 * discard the frame. Enable this if you want to see
159 * error frames in Monitor mode.
161 if (sc
->sc_ah
->opmode
!= NL80211_IFTYPE_MONITOR
)
163 } else if (ds
->ds_rxstat
.rs_status
!= 0) {
164 if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_CRC
)
165 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
166 if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_PHY
)
169 if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_DECRYPT
) {
170 *decrypt_error
= true;
171 } else if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_MIC
) {
172 if (ieee80211_is_ctl(fc
))
174 * Sometimes, we get invalid
175 * MIC failures on valid control frames.
176 * Remove these mic errors.
178 ds
->ds_rxstat
.rs_status
&= ~ATH9K_RXERR_MIC
;
180 rx_status
->flag
|= RX_FLAG_MMIC_ERROR
;
183 * Reject error frames with the exception of
184 * decryption and MIC failures. For monitor mode,
185 * we also ignore the CRC error.
187 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_MONITOR
) {
188 if (ds
->ds_rxstat
.rs_status
&
189 ~(ATH9K_RXERR_DECRYPT
| ATH9K_RXERR_MIC
|
193 if (ds
->ds_rxstat
.rs_status
&
194 ~(ATH9K_RXERR_DECRYPT
| ATH9K_RXERR_MIC
)) {
200 ratecode
= ds
->ds_rxstat
.rs_rate
;
202 if (ratecode
& 0x80) {
204 rx_status
->flag
|= RX_FLAG_HT
;
205 if (ds
->ds_rxstat
.rs_flags
& ATH9K_RX_2040
)
206 rx_status
->flag
|= RX_FLAG_40MHZ
;
207 if (ds
->ds_rxstat
.rs_flags
& ATH9K_RX_GI
)
208 rx_status
->flag
|= RX_FLAG_SHORT_GI
;
209 rx_status
->rate_idx
= ratecode
& 0x7f;
211 int i
= 0, cur_band
, n_rates
;
213 cur_band
= hw
->conf
.channel
->band
;
214 n_rates
= sc
->sbands
[cur_band
].n_bitrates
;
216 for (i
= 0; i
< n_rates
; i
++) {
217 if (sc
->sbands
[cur_band
].bitrates
[i
].hw_value
==
219 rx_status
->rate_idx
= i
;
223 if (sc
->sbands
[cur_band
].bitrates
[i
].hw_value_short
==
225 rx_status
->rate_idx
= i
;
226 rx_status
->flag
|= RX_FLAG_SHORTPRE
;
232 rx_status
->mactime
= ath_extend_tsf(sc
, ds
->ds_rxstat
.rs_tstamp
);
233 rx_status
->band
= hw
->conf
.channel
->band
;
234 rx_status
->freq
= hw
->conf
.channel
->center_freq
;
235 rx_status
->noise
= sc
->ani
.noise_floor
;
236 rx_status
->signal
= rx_status
->noise
+ ds
->ds_rxstat
.rs_rssi
;
237 rx_status
->antenna
= ds
->ds_rxstat
.rs_antenna
;
239 /* at 45 you will be able to use MCS 15 reliably. A more elaborate
240 * scheme can be used here but it requires tables of SNR/throughput for
241 * each possible mode used. */
242 rx_status
->qual
= ds
->ds_rxstat
.rs_rssi
* 100 / 45;
244 /* rssi can be more than 45 though, anything above that
245 * should be considered at 100% */
246 if (rx_status
->qual
> 100)
247 rx_status
->qual
= 100;
249 rx_status
->flag
|= RX_FLAG_TSFT
;
256 static void ath_opmode_init(struct ath_softc
*sc
)
258 struct ath_hw
*ah
= sc
->sc_ah
;
261 /* configure rx filter */
262 rfilt
= ath_calcrxfilter(sc
);
263 ath9k_hw_setrxfilter(ah
, rfilt
);
265 /* configure bssid mask */
266 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
)
267 ath9k_hw_setbssidmask(sc
);
269 /* configure operational mode */
270 ath9k_hw_setopmode(ah
);
272 /* Handle any link-level address change. */
273 ath9k_hw_setmac(ah
, sc
->sc_ah
->macaddr
);
275 /* calculate and install multicast filter */
276 mfilt
[0] = mfilt
[1] = ~0;
277 ath9k_hw_setmcastfilter(ah
, mfilt
[0], mfilt
[1]);
280 int ath_rx_init(struct ath_softc
*sc
, int nbufs
)
286 spin_lock_init(&sc
->rx
.rxflushlock
);
287 sc
->sc_flags
&= ~SC_OP_RXFLUSH
;
288 spin_lock_init(&sc
->rx
.rxbuflock
);
290 sc
->rx
.bufsize
= roundup(IEEE80211_MAX_MPDU_LEN
,
291 min(sc
->cachelsz
, (u16
)64));
293 DPRINTF(sc
, ATH_DBG_CONFIG
, "cachelsz %u rxbufsize %u\n",
294 sc
->cachelsz
, sc
->rx
.bufsize
);
296 /* Initialize rx descriptors */
298 error
= ath_descdma_setup(sc
, &sc
->rx
.rxdma
, &sc
->rx
.rxbuf
,
301 DPRINTF(sc
, ATH_DBG_FATAL
,
302 "failed to allocate rx descriptors: %d\n", error
);
306 list_for_each_entry(bf
, &sc
->rx
.rxbuf
, list
) {
307 skb
= ath_rxbuf_alloc(sc
, sc
->rx
.bufsize
, GFP_KERNEL
);
314 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
317 if (unlikely(dma_mapping_error(sc
->dev
,
319 dev_kfree_skb_any(skb
);
321 DPRINTF(sc
, ATH_DBG_FATAL
,
322 "dma_mapping_error() on RX init\n");
326 bf
->bf_dmacontext
= bf
->bf_buf_addr
;
328 sc
->rx
.rxlink
= NULL
;
337 void ath_rx_cleanup(struct ath_softc
*sc
)
342 list_for_each_entry(bf
, &sc
->rx
.rxbuf
, list
) {
345 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
,
346 sc
->rx
.bufsize
, DMA_FROM_DEVICE
);
351 if (sc
->rx
.rxdma
.dd_desc_len
!= 0)
352 ath_descdma_cleanup(sc
, &sc
->rx
.rxdma
, &sc
->rx
.rxbuf
);
356 * Calculate the receive filter according to the
357 * operating mode and state:
359 * o always accept unicast, broadcast, and multicast traffic
360 * o maintain current state of phy error reception (the hal
361 * may enable phy error frames for noise immunity work)
362 * o probe request frames are accepted only when operating in
363 * hostap, adhoc, or monitor modes
364 * o enable promiscuous mode according to the interface state
366 * - when operating in adhoc mode so the 802.11 layer creates
367 * node table entries for peers,
368 * - when operating in station mode for collecting rssi data when
369 * the station is otherwise quiet, or
370 * - when operating as a repeater so we see repeater-sta beacons
374 u32
ath_calcrxfilter(struct ath_softc
*sc
)
376 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
380 rfilt
= (ath9k_hw_getrxfilter(sc
->sc_ah
) & RX_FILTER_PRESERVE
)
381 | ATH9K_RX_FILTER_UCAST
| ATH9K_RX_FILTER_BCAST
382 | ATH9K_RX_FILTER_MCAST
;
384 /* If not a STA, enable processing of Probe Requests */
385 if (sc
->sc_ah
->opmode
!= NL80211_IFTYPE_STATION
)
386 rfilt
|= ATH9K_RX_FILTER_PROBEREQ
;
389 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
390 * mode interface or when in monitor mode. AP mode does not need this
391 * since it receives all in-BSS frames anyway.
393 if (((sc
->sc_ah
->opmode
!= NL80211_IFTYPE_AP
) &&
394 (sc
->rx
.rxfilter
& FIF_PROMISC_IN_BSS
)) ||
395 (sc
->sc_ah
->opmode
== NL80211_IFTYPE_MONITOR
))
396 rfilt
|= ATH9K_RX_FILTER_PROM
;
398 if (sc
->rx
.rxfilter
& FIF_CONTROL
)
399 rfilt
|= ATH9K_RX_FILTER_CONTROL
;
401 if ((sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
) &&
402 !(sc
->rx
.rxfilter
& FIF_BCN_PRBRESP_PROMISC
))
403 rfilt
|= ATH9K_RX_FILTER_MYBEACON
;
405 rfilt
|= ATH9K_RX_FILTER_BEACON
;
407 /* If in HOSTAP mode, want to enable reception of PSPOLL frames */
408 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_AP
)
409 rfilt
|= ATH9K_RX_FILTER_PSPOLL
;
412 /* TODO: only needed if more than one BSSID is in use in
413 * station/adhoc mode */
414 /* TODO: for older chips, may need to add ATH9K_RX_FILTER_PROM
416 rfilt
|= ATH9K_RX_FILTER_MCAST_BCAST_ALL
;
421 #undef RX_FILTER_PRESERVE
424 int ath_startrecv(struct ath_softc
*sc
)
426 struct ath_hw
*ah
= sc
->sc_ah
;
427 struct ath_buf
*bf
, *tbf
;
429 spin_lock_bh(&sc
->rx
.rxbuflock
);
430 if (list_empty(&sc
->rx
.rxbuf
))
433 sc
->rx
.rxlink
= NULL
;
434 list_for_each_entry_safe(bf
, tbf
, &sc
->rx
.rxbuf
, list
) {
435 ath_rx_buf_link(sc
, bf
);
438 /* We could have deleted elements so the list may be empty now */
439 if (list_empty(&sc
->rx
.rxbuf
))
442 bf
= list_first_entry(&sc
->rx
.rxbuf
, struct ath_buf
, list
);
443 ath9k_hw_putrxbuf(ah
, bf
->bf_daddr
);
447 spin_unlock_bh(&sc
->rx
.rxbuflock
);
449 ath9k_hw_startpcureceive(ah
);
454 bool ath_stoprecv(struct ath_softc
*sc
)
456 struct ath_hw
*ah
= sc
->sc_ah
;
459 ath9k_hw_stoppcurecv(ah
);
460 ath9k_hw_setrxfilter(ah
, 0);
461 stopped
= ath9k_hw_stopdmarecv(ah
);
462 sc
->rx
.rxlink
= NULL
;
467 void ath_flushrecv(struct ath_softc
*sc
)
469 spin_lock_bh(&sc
->rx
.rxflushlock
);
470 sc
->sc_flags
|= SC_OP_RXFLUSH
;
471 ath_rx_tasklet(sc
, 1);
472 sc
->sc_flags
&= ~SC_OP_RXFLUSH
;
473 spin_unlock_bh(&sc
->rx
.rxflushlock
);
476 static bool ath_beacon_dtim_pending_cab(struct sk_buff
*skb
)
478 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
479 struct ieee80211_mgmt
*mgmt
;
480 u8
*pos
, *end
, id
, elen
;
481 struct ieee80211_tim_ie
*tim
;
483 mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
484 pos
= mgmt
->u
.beacon
.variable
;
485 end
= skb
->data
+ skb
->len
;
487 while (pos
+ 2 < end
) {
490 if (pos
+ elen
> end
)
493 if (id
== WLAN_EID_TIM
) {
494 if (elen
< sizeof(*tim
))
496 tim
= (struct ieee80211_tim_ie
*) pos
;
497 if (tim
->dtim_count
!= 0)
499 return tim
->bitmap_ctrl
& 0x01;
508 static void ath_rx_ps_back_to_sleep(struct ath_softc
*sc
)
510 sc
->sc_flags
&= ~(SC_OP_WAIT_FOR_BEACON
| SC_OP_WAIT_FOR_CAB
);
513 static void ath_rx_ps_beacon(struct ath_softc
*sc
, struct sk_buff
*skb
)
515 struct ieee80211_mgmt
*mgmt
;
517 if (skb
->len
< 24 + 8 + 2 + 2)
520 mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
521 if (memcmp(sc
->curbssid
, mgmt
->bssid
, ETH_ALEN
) != 0)
522 return; /* not from our current AP */
524 if (sc
->sc_flags
& SC_OP_BEACON_SYNC
) {
525 sc
->sc_flags
&= ~SC_OP_BEACON_SYNC
;
526 DPRINTF(sc
, ATH_DBG_PS
, "Reconfigure Beacon timers based on "
527 "timestamp from the AP\n");
528 ath_beacon_config(sc
, NULL
);
531 if (!(sc
->hw
->conf
.flags
& IEEE80211_CONF_PS
)) {
532 /* We are not in PS mode anymore; remain awake */
533 DPRINTF(sc
, ATH_DBG_PS
, "Not in PS mode anymore, remain "
535 sc
->sc_flags
&= ~(SC_OP_WAIT_FOR_BEACON
| SC_OP_WAIT_FOR_CAB
);
539 if (ath_beacon_dtim_pending_cab(skb
)) {
541 * Remain awake waiting for buffered broadcast/multicast
542 * frames. If the last broadcast/multicast frame is not
543 * received properly, the next beacon frame will work as
544 * a backup trigger for returning into NETWORK SLEEP state,
545 * so we are waiting for it as well.
547 DPRINTF(sc
, ATH_DBG_PS
, "Received DTIM beacon indicating "
548 "buffered broadcast/multicast frame(s)\n");
549 sc
->sc_flags
|= SC_OP_WAIT_FOR_CAB
| SC_OP_WAIT_FOR_BEACON
;
553 if (sc
->sc_flags
& SC_OP_WAIT_FOR_CAB
) {
555 * This can happen if a broadcast frame is dropped or the AP
556 * fails to send a frame indicating that all CAB frames have
559 DPRINTF(sc
, ATH_DBG_PS
, "PS wait for CAB frames timed out\n");
562 /* No more broadcast/multicast frames to be received at this point. */
563 ath_rx_ps_back_to_sleep(sc
);
566 static void ath_rx_ps(struct ath_softc
*sc
, struct sk_buff
*skb
)
568 struct ieee80211_hdr
*hdr
;
570 hdr
= (struct ieee80211_hdr
*)skb
->data
;
572 /* Process Beacon and CAB receive in PS state */
573 if ((sc
->sc_flags
& SC_OP_WAIT_FOR_BEACON
) &&
574 ieee80211_is_beacon(hdr
->frame_control
))
575 ath_rx_ps_beacon(sc
, skb
);
576 else if ((sc
->sc_flags
& SC_OP_WAIT_FOR_CAB
) &&
577 (ieee80211_is_data(hdr
->frame_control
) ||
578 ieee80211_is_action(hdr
->frame_control
)) &&
579 is_multicast_ether_addr(hdr
->addr1
) &&
580 !ieee80211_has_moredata(hdr
->frame_control
)) {
581 DPRINTF(sc
, ATH_DBG_PS
, "All PS CAB frames received, back to "
584 * No more broadcast/multicast frames to be received at this
587 ath_rx_ps_back_to_sleep(sc
);
588 } else if ((sc
->sc_flags
& SC_OP_WAIT_FOR_PSPOLL_DATA
) &&
589 !is_multicast_ether_addr(hdr
->addr1
) &&
590 !ieee80211_has_morefrags(hdr
->frame_control
)) {
591 sc
->sc_flags
&= ~SC_OP_WAIT_FOR_PSPOLL_DATA
;
592 DPRINTF(sc
, ATH_DBG_PS
, "Going back to sleep after having "
593 "received PS-Poll data (0x%x)\n",
594 sc
->sc_flags
& (SC_OP_WAIT_FOR_BEACON
|
596 SC_OP_WAIT_FOR_PSPOLL_DATA
|
597 SC_OP_WAIT_FOR_TX_ACK
));
601 static void ath_rx_send_to_mac80211(struct ath_softc
*sc
, struct sk_buff
*skb
,
602 struct ieee80211_rx_status
*rx_status
)
604 struct ieee80211_hdr
*hdr
;
606 hdr
= (struct ieee80211_hdr
*)skb
->data
;
608 /* Send the frame to mac80211 */
609 if (is_multicast_ether_addr(hdr
->addr1
)) {
612 * Deliver broadcast/multicast frames to all suitable
615 /* TODO: filter based on channel configuration */
616 for (i
= 0; i
< sc
->num_sec_wiphy
; i
++) {
617 struct ath_wiphy
*aphy
= sc
->sec_wiphy
[i
];
618 struct sk_buff
*nskb
;
621 nskb
= skb_copy(skb
, GFP_ATOMIC
);
623 memcpy(IEEE80211_SKB_RXCB(nskb
), rx_status
,
625 ieee80211_rx(aphy
->hw
, nskb
);
628 memcpy(IEEE80211_SKB_RXCB(skb
), rx_status
, sizeof(*rx_status
));
629 ieee80211_rx(sc
->hw
, skb
);
631 /* Deliver unicast frames based on receiver address */
632 memcpy(IEEE80211_SKB_RXCB(skb
), rx_status
, sizeof(*rx_status
));
633 ieee80211_rx(ath_get_virt_hw(sc
, hdr
), skb
);
637 int ath_rx_tasklet(struct ath_softc
*sc
, int flush
)
639 #define PA2DESC(_sc, _pa) \
640 ((struct ath_desc *)((caddr_t)(_sc)->rx.rxdma.dd_desc + \
641 ((_pa) - (_sc)->rx.rxdma.dd_desc_paddr)))
645 struct sk_buff
*skb
= NULL
, *requeue_skb
;
646 struct ieee80211_rx_status rx_status
;
647 struct ath_hw
*ah
= sc
->sc_ah
;
648 struct ieee80211_hdr
*hdr
;
649 int hdrlen
, padsize
, retval
;
650 bool decrypt_error
= false;
654 spin_lock_bh(&sc
->rx
.rxbuflock
);
657 /* If handling rx interrupt and flush is in progress => exit */
658 if ((sc
->sc_flags
& SC_OP_RXFLUSH
) && (flush
== 0))
661 if (list_empty(&sc
->rx
.rxbuf
)) {
662 sc
->rx
.rxlink
= NULL
;
666 bf
= list_first_entry(&sc
->rx
.rxbuf
, struct ath_buf
, list
);
670 * Must provide the virtual address of the current
671 * descriptor, the physical address, and the virtual
672 * address of the next descriptor in the h/w chain.
673 * This allows the HAL to look ahead to see if the
674 * hardware is done with a descriptor by checking the
675 * done bit in the following descriptor and the address
676 * of the current descriptor the DMA engine is working
677 * on. All this is necessary because of our use of
678 * a self-linked list to avoid rx overruns.
680 retval
= ath9k_hw_rxprocdesc(ah
, ds
,
682 PA2DESC(sc
, ds
->ds_link
),
684 if (retval
== -EINPROGRESS
) {
686 struct ath_desc
*tds
;
688 if (list_is_last(&bf
->list
, &sc
->rx
.rxbuf
)) {
689 sc
->rx
.rxlink
= NULL
;
693 tbf
= list_entry(bf
->list
.next
, struct ath_buf
, list
);
696 * On some hardware the descriptor status words could
697 * get corrupted, including the done bit. Because of
698 * this, check if the next descriptor's done bit is
701 * If the next descriptor's done bit is set, the current
702 * descriptor has been corrupted. Force s/w to discard
703 * this descriptor and continue...
707 retval
= ath9k_hw_rxprocdesc(ah
, tds
, tbf
->bf_daddr
,
708 PA2DESC(sc
, tds
->ds_link
), 0);
709 if (retval
== -EINPROGRESS
) {
719 * Synchronize the DMA transfer with CPU before
720 * 1. accessing the frame
721 * 2. requeueing the same buffer to h/w
723 dma_sync_single_for_cpu(sc
->dev
, bf
->bf_buf_addr
,
728 * If we're asked to flush receive queue, directly
729 * chain it back at the queue without processing it.
734 if (!ds
->ds_rxstat
.rs_datalen
)
737 /* The status portion of the descriptor could get corrupted. */
738 if (sc
->rx
.bufsize
< ds
->ds_rxstat
.rs_datalen
)
741 if (!ath_rx_prepare(skb
, ds
, &rx_status
, &decrypt_error
, sc
))
744 /* Ensure we always have an skb to requeue once we are done
745 * processing the current buffer's skb */
746 requeue_skb
= ath_rxbuf_alloc(sc
, sc
->rx
.bufsize
, GFP_ATOMIC
);
748 /* If there is no memory we ignore the current RX'd frame,
749 * tell hardware it can give us a new frame using the old
750 * skb and put it at the tail of the sc->rx.rxbuf list for
755 /* Unmap the frame */
756 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
,
760 skb_put(skb
, ds
->ds_rxstat
.rs_datalen
);
761 skb
->protocol
= cpu_to_be16(ETH_P_CONTROL
);
763 /* see if any padding is done by the hw and remove it */
764 hdr
= (struct ieee80211_hdr
*)skb
->data
;
765 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
766 fc
= hdr
->frame_control
;
768 /* The MAC header is padded to have 32-bit boundary if the
769 * packet payload is non-zero. The general calculation for
770 * padsize would take into account odd header lengths:
771 * padsize = (4 - hdrlen % 4) % 4; However, since only
772 * even-length headers are used, padding can only be 0 or 2
773 * bytes and we can optimize this a bit. In addition, we must
774 * not try to remove padding from short control frames that do
775 * not have payload. */
776 padsize
= hdrlen
& 3;
777 if (padsize
&& hdrlen
>= 24) {
778 memmove(skb
->data
+ padsize
, skb
->data
, hdrlen
);
779 skb_pull(skb
, padsize
);
782 keyix
= ds
->ds_rxstat
.rs_keyix
;
784 if (!(keyix
== ATH9K_RXKEYIX_INVALID
) && !decrypt_error
) {
785 rx_status
.flag
|= RX_FLAG_DECRYPTED
;
786 } else if (ieee80211_has_protected(fc
)
787 && !decrypt_error
&& skb
->len
>= hdrlen
+ 4) {
788 keyix
= skb
->data
[hdrlen
+ 3] >> 6;
790 if (test_bit(keyix
, sc
->keymap
))
791 rx_status
.flag
|= RX_FLAG_DECRYPTED
;
793 if (ah
->sw_mgmt_crypto
&&
794 (rx_status
.flag
& RX_FLAG_DECRYPTED
) &&
795 ieee80211_is_mgmt(fc
)) {
796 /* Use software decrypt for management frames. */
797 rx_status
.flag
&= ~RX_FLAG_DECRYPTED
;
800 /* We will now give hardware our shiny new allocated skb */
801 bf
->bf_mpdu
= requeue_skb
;
802 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, requeue_skb
->data
,
805 if (unlikely(dma_mapping_error(sc
->dev
,
807 dev_kfree_skb_any(requeue_skb
);
809 DPRINTF(sc
, ATH_DBG_FATAL
,
810 "dma_mapping_error() on RX\n");
811 ath_rx_send_to_mac80211(sc
, skb
, &rx_status
);
814 bf
->bf_dmacontext
= bf
->bf_buf_addr
;
817 * change the default rx antenna if rx diversity chooses the
818 * other antenna 3 times in a row.
820 if (sc
->rx
.defant
!= ds
->ds_rxstat
.rs_antenna
) {
821 if (++sc
->rx
.rxotherant
>= 3)
822 ath_setdefantenna(sc
, ds
->ds_rxstat
.rs_antenna
);
824 sc
->rx
.rxotherant
= 0;
827 if (unlikely(sc
->sc_flags
& (SC_OP_WAIT_FOR_BEACON
|
829 SC_OP_WAIT_FOR_PSPOLL_DATA
)))
832 ath_rx_send_to_mac80211(sc
, skb
, &rx_status
);
835 list_move_tail(&bf
->list
, &sc
->rx
.rxbuf
);
836 ath_rx_buf_link(sc
, bf
);
839 spin_unlock_bh(&sc
->rx
.rxbuflock
);