2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol
[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
53 struct ath_atx_tid
*tid
, struct sk_buff
*skb
);
54 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
55 int tx_flags
, struct ath_txq
*txq
);
56 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
57 struct ath_txq
*txq
, struct list_head
*bf_q
,
58 struct ath_tx_status
*ts
, int txok
);
59 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
60 struct list_head
*head
, bool internal
);
61 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
62 struct ath_tx_status
*ts
, int nframes
, int nbad
,
64 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
66 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
68 struct ath_atx_tid
*tid
,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc
*sc
, struct ath_txq
*txq
)
83 __acquires(&txq
->axq_lock
)
85 spin_lock_bh(&txq
->axq_lock
);
88 void ath_txq_unlock(struct ath_softc
*sc
, struct ath_txq
*txq
)
89 __releases(&txq
->axq_lock
)
91 spin_unlock_bh(&txq
->axq_lock
);
94 void ath_txq_unlock_complete(struct ath_softc
*sc
, struct ath_txq
*txq
)
95 __releases(&txq
->axq_lock
)
97 struct sk_buff_head q
;
100 __skb_queue_head_init(&q
);
101 skb_queue_splice_init(&txq
->complete_q
, &q
);
102 spin_unlock_bh(&txq
->axq_lock
);
104 while ((skb
= __skb_dequeue(&q
)))
105 ieee80211_tx_status(sc
->hw
, skb
);
108 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
110 struct ath_atx_ac
*ac
= tid
->ac
;
119 list_add_tail(&tid
->list
, &ac
->tid_q
);
125 list_add_tail(&ac
->list
, &txq
->axq_acq
);
128 static void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
130 struct ath_txq
*txq
= tid
->ac
->txq
;
132 WARN_ON(!tid
->paused
);
134 ath_txq_lock(sc
, txq
);
137 if (skb_queue_empty(&tid
->buf_q
))
140 ath_tx_queue_tid(txq
, tid
);
141 ath_txq_schedule(sc
, txq
);
143 ath_txq_unlock_complete(sc
, txq
);
146 static struct ath_frame_info
*get_frame_info(struct sk_buff
*skb
)
148 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
149 BUILD_BUG_ON(sizeof(struct ath_frame_info
) >
150 sizeof(tx_info
->rate_driver_data
));
151 return (struct ath_frame_info
*) &tx_info
->rate_driver_data
[0];
154 static void ath_send_bar(struct ath_atx_tid
*tid
, u16 seqno
)
156 ieee80211_send_bar(tid
->an
->vif
, tid
->an
->sta
->addr
, tid
->tidno
,
157 seqno
<< IEEE80211_SEQ_SEQ_SHIFT
);
160 static void ath_set_rates(struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
163 ieee80211_get_tx_rates(vif
, sta
, bf
->bf_mpdu
, bf
->rates
,
164 ARRAY_SIZE(bf
->rates
));
167 static void ath_tx_clear_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
169 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
170 tid
->state
&= ~AGGR_CLEANUP
;
174 ieee80211_start_tx_ba_cb_irqsafe(tid
->an
->vif
, tid
->an
->sta
->addr
,
176 tid
->stop_cb
= false;
179 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
182 struct ath_txq
*txq
= tid
->ac
->txq
;
185 struct list_head bf_head
;
186 struct ath_tx_status ts
;
187 struct ath_frame_info
*fi
;
188 bool sendbar
= false;
190 INIT_LIST_HEAD(&bf_head
);
192 memset(&ts
, 0, sizeof(ts
));
194 while ((skb
= __skb_dequeue(&tid
->buf_q
))) {
195 fi
= get_frame_info(skb
);
197 if (!bf
&& !flush_packets
)
198 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
201 ieee80211_free_txskb(sc
->hw
, skb
);
205 if (fi
->retries
|| flush_packets
) {
206 list_add_tail(&bf
->list
, &bf_head
);
207 ath_tx_update_baw(sc
, tid
, bf
->bf_state
.seqno
);
208 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
211 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
212 ath_tx_send_normal(sc
, txq
, NULL
, skb
);
216 if (tid
->baw_head
== tid
->baw_tail
)
217 ath_tx_clear_tid(sc
, tid
);
219 if (sendbar
&& !flush_packets
) {
220 ath_txq_unlock(sc
, txq
);
221 ath_send_bar(tid
, tid
->seq_start
);
222 ath_txq_lock(sc
, txq
);
226 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
231 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
232 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
234 __clear_bit(cindex
, tid
->tx_buf
);
236 while (tid
->baw_head
!= tid
->baw_tail
&& !test_bit(tid
->baw_head
, tid
->tx_buf
)) {
237 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
238 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
239 if (tid
->bar_index
>= 0)
244 static void ath_tx_addto_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
249 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
250 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
251 __set_bit(cindex
, tid
->tx_buf
);
253 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
254 (ATH_TID_MAX_BUFS
- 1))) {
255 tid
->baw_tail
= cindex
;
256 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
261 * TODO: For frame(s) that are in the retry state, we will reuse the
262 * sequence number(s) without setting the retry bit. The
263 * alternative is to give up on these and BAR the receiver's window
266 static void ath_tid_drain(struct ath_softc
*sc
, struct ath_txq
*txq
,
267 struct ath_atx_tid
*tid
)
272 struct list_head bf_head
;
273 struct ath_tx_status ts
;
274 struct ath_frame_info
*fi
;
276 memset(&ts
, 0, sizeof(ts
));
277 INIT_LIST_HEAD(&bf_head
);
279 while ((skb
= __skb_dequeue(&tid
->buf_q
))) {
280 fi
= get_frame_info(skb
);
284 ath_tx_complete(sc
, skb
, ATH_TX_ERROR
, txq
);
288 list_add_tail(&bf
->list
, &bf_head
);
290 ath_tx_update_baw(sc
, tid
, bf
->bf_state
.seqno
);
291 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
294 tid
->seq_next
= tid
->seq_start
;
295 tid
->baw_tail
= tid
->baw_head
;
299 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_txq
*txq
,
300 struct sk_buff
*skb
, int count
)
302 struct ath_frame_info
*fi
= get_frame_info(skb
);
303 struct ath_buf
*bf
= fi
->bf
;
304 struct ieee80211_hdr
*hdr
;
305 int prev
= fi
->retries
;
307 TX_STAT_INC(txq
->axq_qnum
, a_retries
);
308 fi
->retries
+= count
;
313 hdr
= (struct ieee80211_hdr
*)skb
->data
;
314 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
315 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
316 sizeof(*hdr
), DMA_TO_DEVICE
);
319 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
321 struct ath_buf
*bf
= NULL
;
323 spin_lock_bh(&sc
->tx
.txbuflock
);
325 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
326 spin_unlock_bh(&sc
->tx
.txbuflock
);
330 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
333 spin_unlock_bh(&sc
->tx
.txbuflock
);
338 static void ath_tx_return_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
)
340 spin_lock_bh(&sc
->tx
.txbuflock
);
341 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
342 spin_unlock_bh(&sc
->tx
.txbuflock
);
345 static struct ath_buf
* ath_clone_txbuf(struct ath_softc
*sc
, struct ath_buf
*bf
)
349 tbf
= ath_tx_get_buffer(sc
);
353 ATH_TXBUF_RESET(tbf
);
355 tbf
->bf_mpdu
= bf
->bf_mpdu
;
356 tbf
->bf_buf_addr
= bf
->bf_buf_addr
;
357 memcpy(tbf
->bf_desc
, bf
->bf_desc
, sc
->sc_ah
->caps
.tx_desc_len
);
358 tbf
->bf_state
= bf
->bf_state
;
363 static void ath_tx_count_frames(struct ath_softc
*sc
, struct ath_buf
*bf
,
364 struct ath_tx_status
*ts
, int txok
,
365 int *nframes
, int *nbad
)
367 struct ath_frame_info
*fi
;
369 u32 ba
[WME_BA_BMP_SIZE
>> 5];
376 isaggr
= bf_isaggr(bf
);
378 seq_st
= ts
->ts_seqnum
;
379 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
383 fi
= get_frame_info(bf
->bf_mpdu
);
384 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_state
.seqno
);
387 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
395 static void ath_tx_complete_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
396 struct ath_buf
*bf
, struct list_head
*bf_q
,
397 struct ath_tx_status
*ts
, int txok
)
399 struct ath_node
*an
= NULL
;
401 struct ieee80211_sta
*sta
;
402 struct ieee80211_hw
*hw
= sc
->hw
;
403 struct ieee80211_hdr
*hdr
;
404 struct ieee80211_tx_info
*tx_info
;
405 struct ath_atx_tid
*tid
= NULL
;
406 struct ath_buf
*bf_next
, *bf_last
= bf
->bf_lastbf
;
407 struct list_head bf_head
;
408 struct sk_buff_head bf_pending
;
409 u16 seq_st
= 0, acked_cnt
= 0, txfail_cnt
= 0, seq_first
;
410 u32 ba
[WME_BA_BMP_SIZE
>> 5];
411 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0, nbad
= 0;
412 bool rc_update
= true, isba
;
413 struct ieee80211_tx_rate rates
[4];
414 struct ath_frame_info
*fi
;
417 bool flush
= !!(ts
->ts_status
& ATH9K_TX_FLUSH
);
422 hdr
= (struct ieee80211_hdr
*)skb
->data
;
424 tx_info
= IEEE80211_SKB_CB(skb
);
426 memcpy(rates
, bf
->rates
, sizeof(rates
));
428 retries
= ts
->ts_longretry
+ 1;
429 for (i
= 0; i
< ts
->ts_rateindex
; i
++)
430 retries
+= rates
[i
].count
;
434 sta
= ieee80211_find_sta_by_ifaddr(hw
, hdr
->addr1
, hdr
->addr2
);
438 INIT_LIST_HEAD(&bf_head
);
440 bf_next
= bf
->bf_next
;
442 if (!bf
->bf_stale
|| bf_next
!= NULL
)
443 list_move_tail(&bf
->list
, &bf_head
);
445 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
, 0);
452 an
= (struct ath_node
*)sta
->drv_priv
;
453 tidno
= ieee80211_get_qos_ctl(hdr
)[0] & IEEE80211_QOS_CTL_TID_MASK
;
454 tid
= ATH_AN_2_TID(an
, tidno
);
455 seq_first
= tid
->seq_start
;
456 isba
= ts
->ts_flags
& ATH9K_TX_BA
;
459 * The hardware occasionally sends a tx status for the wrong TID.
460 * In this case, the BA status cannot be considered valid and all
461 * subframes need to be retransmitted
463 * Only BlockAcks have a TID and therefore normal Acks cannot be
466 if (isba
&& tidno
!= ts
->tid
)
469 isaggr
= bf_isaggr(bf
);
470 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
472 if (isaggr
&& txok
) {
473 if (ts
->ts_flags
& ATH9K_TX_BA
) {
474 seq_st
= ts
->ts_seqnum
;
475 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
478 * AR5416 can become deaf/mute when BA
479 * issue happens. Chip needs to be reset.
480 * But AP code may have sychronization issues
481 * when perform internal reset in this routine.
482 * Only enable reset in STA mode for now.
484 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
)
489 __skb_queue_head_init(&bf_pending
);
491 ath_tx_count_frames(sc
, bf
, ts
, txok
, &nframes
, &nbad
);
493 u16 seqno
= bf
->bf_state
.seqno
;
495 txfail
= txpending
= sendbar
= 0;
496 bf_next
= bf
->bf_next
;
499 tx_info
= IEEE80211_SKB_CB(skb
);
500 fi
= get_frame_info(skb
);
502 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, seqno
))) {
503 /* transmit completion, subframe is
504 * acked by block ack */
506 } else if (!isaggr
&& txok
) {
507 /* transmit completion */
509 } else if (tid
->state
& AGGR_CLEANUP
) {
511 * cleanup in progress, just fail
512 * the un-acked sub-frames
517 } else if (fi
->retries
< ATH_MAX_SW_RETRIES
) {
518 if (txok
|| !an
->sleeping
)
519 ath_tx_set_retry(sc
, txq
, bf
->bf_mpdu
,
526 bar_index
= max_t(int, bar_index
,
527 ATH_BA_INDEX(seq_first
, seqno
));
531 * Make sure the last desc is reclaimed if it
532 * not a holding desc.
534 INIT_LIST_HEAD(&bf_head
);
535 if (bf_next
!= NULL
|| !bf_last
->bf_stale
)
536 list_move_tail(&bf
->list
, &bf_head
);
538 if (!txpending
|| (tid
->state
& AGGR_CLEANUP
)) {
540 * complete the acked-ones/xretried ones; update
543 ath_tx_update_baw(sc
, tid
, seqno
);
545 if (rc_update
&& (acked_cnt
== 1 || txfail_cnt
== 1)) {
546 memcpy(tx_info
->control
.rates
, rates
, sizeof(rates
));
547 ath_tx_rc_status(sc
, bf
, ts
, nframes
, nbad
, txok
);
551 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
,
554 /* retry the un-acked ones */
555 if (bf
->bf_next
== NULL
&& bf_last
->bf_stale
) {
558 tbf
= ath_clone_txbuf(sc
, bf_last
);
560 * Update tx baw and complete the
561 * frame with failed status if we
565 ath_tx_update_baw(sc
, tid
, seqno
);
567 ath_tx_complete_buf(sc
, bf
, txq
,
569 bar_index
= max_t(int, bar_index
,
570 ATH_BA_INDEX(seq_first
, seqno
));
578 * Put this buffer to the temporary pending
579 * queue to retain ordering
581 __skb_queue_tail(&bf_pending
, skb
);
587 /* prepend un-acked frames to the beginning of the pending frame queue */
588 if (!skb_queue_empty(&bf_pending
)) {
590 ieee80211_sta_set_buffered(sta
, tid
->tidno
, true);
592 skb_queue_splice(&bf_pending
, &tid
->buf_q
);
594 ath_tx_queue_tid(txq
, tid
);
596 if (ts
->ts_status
& (ATH9K_TXERR_FILT
| ATH9K_TXERR_XRETRY
))
597 tid
->ac
->clear_ps_filter
= true;
601 if (bar_index
>= 0) {
602 u16 bar_seq
= ATH_BA_INDEX2SEQ(seq_first
, bar_index
);
604 if (BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bar_seq
))
605 tid
->bar_index
= ATH_BA_INDEX(tid
->seq_start
, bar_seq
);
607 ath_txq_unlock(sc
, txq
);
608 ath_send_bar(tid
, ATH_BA_INDEX2SEQ(seq_first
, bar_index
+ 1));
609 ath_txq_lock(sc
, txq
);
612 if (tid
->state
& AGGR_CLEANUP
)
613 ath_tx_flush_tid(sc
, tid
, false);
618 ath9k_queue_reset(sc
, RESET_TYPE_TX_ERROR
);
621 static bool bf_is_ampdu_not_probing(struct ath_buf
*bf
)
623 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
624 return bf_isampdu(bf
) && !(info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
);
627 static void ath_tx_process_buffer(struct ath_softc
*sc
, struct ath_txq
*txq
,
628 struct ath_tx_status
*ts
, struct ath_buf
*bf
,
629 struct list_head
*bf_head
)
631 struct ieee80211_tx_info
*info
;
634 txok
= !(ts
->ts_status
& ATH9K_TXERR_MASK
);
635 flush
= !!(ts
->ts_status
& ATH9K_TX_FLUSH
);
636 txq
->axq_tx_inprogress
= false;
639 if (bf_is_ampdu_not_probing(bf
))
640 txq
->axq_ampdu_depth
--;
642 if (!bf_isampdu(bf
)) {
644 info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
645 memcpy(info
->control
.rates
, bf
->rates
,
646 sizeof(info
->control
.rates
));
647 ath_tx_rc_status(sc
, bf
, ts
, 1, txok
? 0 : 1, txok
);
649 ath_tx_complete_buf(sc
, bf
, txq
, bf_head
, ts
, txok
);
651 ath_tx_complete_aggr(sc
, txq
, bf
, bf_head
, ts
, txok
);
653 if ((sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
) && !flush
)
654 ath_txq_schedule(sc
, txq
);
657 static bool ath_lookup_legacy(struct ath_buf
*bf
)
660 struct ieee80211_tx_info
*tx_info
;
661 struct ieee80211_tx_rate
*rates
;
665 tx_info
= IEEE80211_SKB_CB(skb
);
666 rates
= tx_info
->control
.rates
;
668 for (i
= 0; i
< 4; i
++) {
669 if (!rates
[i
].count
|| rates
[i
].idx
< 0)
672 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
))
679 static u32
ath_lookup_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
680 struct ath_atx_tid
*tid
)
683 struct ieee80211_tx_info
*tx_info
;
684 struct ieee80211_tx_rate
*rates
;
685 u32 max_4ms_framelen
, frmlen
;
686 u16 aggr_limit
, bt_aggr_limit
, legacy
= 0;
687 int q
= tid
->ac
->txq
->mac80211_qnum
;
691 tx_info
= IEEE80211_SKB_CB(skb
);
695 * Find the lowest frame length among the rate series that will have a
696 * 4ms (or TXOP limited) transmit duration.
698 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
700 for (i
= 0; i
< 4; i
++) {
706 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
)) {
711 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
716 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
719 frmlen
= sc
->tx
.max_aggr_framelen
[q
][modeidx
][rates
[i
].idx
];
720 max_4ms_framelen
= min(max_4ms_framelen
, frmlen
);
724 * limit aggregate size by the minimum rate if rate selected is
725 * not a probe rate, if rate selected is a probe rate then
726 * avoid aggregation of this packet.
728 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
731 aggr_limit
= min(max_4ms_framelen
, (u32
)ATH_AMPDU_LIMIT_MAX
);
734 * Override the default aggregation limit for BTCOEX.
736 bt_aggr_limit
= ath9k_btcoex_aggr_limit(sc
, max_4ms_framelen
);
738 aggr_limit
= bt_aggr_limit
;
741 * h/w can accept aggregates up to 16 bit lengths (65535).
742 * The IE, however can hold up to 65536, which shows up here
743 * as zero. Ignore 65536 since we are constrained by hw.
745 if (tid
->an
->maxampdu
)
746 aggr_limit
= min(aggr_limit
, tid
->an
->maxampdu
);
752 * Returns the number of delimiters to be added to
753 * meet the minimum required mpdudensity.
755 static int ath_compute_num_delims(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
756 struct ath_buf
*bf
, u16 frmlen
,
759 #define FIRST_DESC_NDELIMS 60
760 u32 nsymbits
, nsymbols
;
763 int width
, streams
, half_gi
, ndelim
, mindelim
;
764 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
766 /* Select standard number of delimiters based on frame length alone */
767 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
770 * If encryption enabled, hardware requires some more padding between
772 * TODO - this could be improved to be dependent on the rate.
773 * The hardware can keep up at lower rates, but not higher rates
775 if ((fi
->keyix
!= ATH9K_TXKEYIX_INVALID
) &&
776 !(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
))
777 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
780 * Add delimiter when using RTS/CTS with aggregation
781 * and non enterprise AR9003 card
783 if (first_subfrm
&& !AR_SREV_9580_10_OR_LATER(sc
->sc_ah
) &&
784 (sc
->sc_ah
->ent_mode
& AR_ENT_OTP_MIN_PKT_SIZE_DISABLE
))
785 ndelim
= max(ndelim
, FIRST_DESC_NDELIMS
);
788 * Convert desired mpdu density from microeconds to bytes based
789 * on highest rate in rate series (i.e. first rate) to determine
790 * required minimum length for subframe. Take into account
791 * whether high rate is 20 or 40Mhz and half or full GI.
793 * If there is no mpdu density restriction, no further calculation
797 if (tid
->an
->mpdudensity
== 0)
800 rix
= bf
->rates
[0].idx
;
801 flags
= bf
->rates
[0].flags
;
802 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
803 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
806 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(tid
->an
->mpdudensity
);
808 nsymbols
= NUM_SYMBOLS_PER_USEC(tid
->an
->mpdudensity
);
813 streams
= HT_RC_2_STREAMS(rix
);
814 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
815 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
817 if (frmlen
< minlen
) {
818 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
819 ndelim
= max(mindelim
, ndelim
);
825 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
827 struct ath_atx_tid
*tid
,
828 struct list_head
*bf_q
,
831 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
832 struct ath_buf
*bf
, *bf_first
= NULL
, *bf_prev
= NULL
;
833 int rl
= 0, nframes
= 0, ndelim
, prev_al
= 0;
834 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
835 al_delta
, h_baw
= tid
->baw_size
/ 2;
836 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
837 struct ieee80211_tx_info
*tx_info
;
838 struct ath_frame_info
*fi
;
843 skb
= skb_peek(&tid
->buf_q
);
844 fi
= get_frame_info(skb
);
847 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
850 __skb_unlink(skb
, &tid
->buf_q
);
851 ieee80211_free_txskb(sc
->hw
, skb
);
855 bf
->bf_state
.bf_type
= BUF_AMPDU
| BUF_AGGR
;
856 seqno
= bf
->bf_state
.seqno
;
858 /* do not step over block-ack window */
859 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, seqno
)) {
860 status
= ATH_AGGR_BAW_CLOSED
;
864 if (tid
->bar_index
> ATH_BA_INDEX(tid
->seq_start
, seqno
)) {
865 struct ath_tx_status ts
= {};
866 struct list_head bf_head
;
868 INIT_LIST_HEAD(&bf_head
);
869 list_add(&bf
->list
, &bf_head
);
870 __skb_unlink(skb
, &tid
->buf_q
);
871 ath_tx_update_baw(sc
, tid
, seqno
);
872 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
880 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
881 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
885 /* do not exceed aggregation limit */
886 al_delta
= ATH_AGGR_DELIM_SZ
+ fi
->framelen
;
889 ((aggr_limit
< (al
+ bpad
+ al_delta
+ prev_al
)) ||
890 ath_lookup_legacy(bf
))) {
891 status
= ATH_AGGR_LIMITED
;
895 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
896 if (nframes
&& (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
))
899 /* do not exceed subframe limit */
900 if (nframes
>= min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
901 status
= ATH_AGGR_LIMITED
;
905 /* add padding for previous frame to aggregation length */
906 al
+= bpad
+ al_delta
;
909 * Get the delimiters needed to meet the MPDU
910 * density for this node.
912 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, fi
->framelen
,
914 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
919 /* link buffers of this frame to the aggregate */
921 ath_tx_addto_baw(sc
, tid
, seqno
);
922 bf
->bf_state
.ndelim
= ndelim
;
924 __skb_unlink(skb
, &tid
->buf_q
);
925 list_add_tail(&bf
->list
, bf_q
);
927 bf_prev
->bf_next
= bf
;
931 } while (!skb_queue_empty(&tid
->buf_q
));
941 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
942 * width - 0 for 20 MHz, 1 for 40 MHz
943 * half_gi - to use 4us v/s 3.6 us for symbol time
945 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, int pktlen
,
946 int width
, int half_gi
, bool shortPreamble
)
948 u32 nbits
, nsymbits
, duration
, nsymbols
;
951 /* find number of symbols: PLCP + data */
952 streams
= HT_RC_2_STREAMS(rix
);
953 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
954 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
955 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
958 duration
= SYMBOL_TIME(nsymbols
);
960 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
962 /* addup duration for legacy/ht training and signal fields */
963 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
968 static int ath_max_framelen(int usec
, int mcs
, bool ht40
, bool sgi
)
970 int streams
= HT_RC_2_STREAMS(mcs
);
974 symbols
= sgi
? TIME_SYMBOLS_HALFGI(usec
) : TIME_SYMBOLS(usec
);
975 bits
= symbols
* bits_per_symbol
[mcs
% 8][ht40
] * streams
;
976 bits
-= OFDM_PLCP_BITS
;
978 bytes
-= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
985 void ath_update_max_aggr_framelen(struct ath_softc
*sc
, int queue
, int txop
)
987 u16
*cur_ht20
, *cur_ht20_sgi
, *cur_ht40
, *cur_ht40_sgi
;
990 /* 4ms is the default (and maximum) duration */
991 if (!txop
|| txop
> 4096)
994 cur_ht20
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT20
];
995 cur_ht20_sgi
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT20_SGI
];
996 cur_ht40
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT40
];
997 cur_ht40_sgi
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT40_SGI
];
998 for (mcs
= 0; mcs
< 32; mcs
++) {
999 cur_ht20
[mcs
] = ath_max_framelen(txop
, mcs
, false, false);
1000 cur_ht20_sgi
[mcs
] = ath_max_framelen(txop
, mcs
, false, true);
1001 cur_ht40
[mcs
] = ath_max_framelen(txop
, mcs
, true, false);
1002 cur_ht40_sgi
[mcs
] = ath_max_framelen(txop
, mcs
, true, true);
1006 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
1007 struct ath_tx_info
*info
, int len
)
1009 struct ath_hw
*ah
= sc
->sc_ah
;
1010 struct sk_buff
*skb
;
1011 struct ieee80211_tx_info
*tx_info
;
1012 struct ieee80211_tx_rate
*rates
;
1013 const struct ieee80211_rate
*rate
;
1014 struct ieee80211_hdr
*hdr
;
1015 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
1020 tx_info
= IEEE80211_SKB_CB(skb
);
1022 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1024 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1025 info
->dur_update
= !ieee80211_is_pspoll(hdr
->frame_control
);
1026 info
->rtscts_rate
= fi
->rtscts_rate
;
1028 for (i
= 0; i
< ARRAY_SIZE(bf
->rates
); i
++) {
1029 bool is_40
, is_sgi
, is_sp
;
1032 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
1036 info
->rates
[i
].Tries
= rates
[i
].count
;
1038 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
1039 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1040 info
->flags
|= ATH9K_TXDESC_RTSENA
;
1041 } else if (rates
[i
].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1042 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1043 info
->flags
|= ATH9K_TXDESC_CTSENA
;
1046 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
1047 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_2040
;
1048 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
1049 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_HALFGI
;
1051 is_sgi
= !!(rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
);
1052 is_40
= !!(rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
);
1053 is_sp
= !!(rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
);
1055 if (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) {
1057 info
->rates
[i
].Rate
= rix
| 0x80;
1058 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
1059 ah
->txchainmask
, info
->rates
[i
].Rate
);
1060 info
->rates
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, len
,
1061 is_40
, is_sgi
, is_sp
);
1062 if (rix
< 8 && (tx_info
->flags
& IEEE80211_TX_CTL_STBC
))
1063 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_STBC
;
1068 rate
= &sc
->sbands
[tx_info
->band
].bitrates
[rates
[i
].idx
];
1069 if ((tx_info
->band
== IEEE80211_BAND_2GHZ
) &&
1070 !(rate
->flags
& IEEE80211_RATE_ERP_G
))
1071 phy
= WLAN_RC_PHY_CCK
;
1073 phy
= WLAN_RC_PHY_OFDM
;
1075 info
->rates
[i
].Rate
= rate
->hw_value
;
1076 if (rate
->hw_value_short
) {
1077 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
1078 info
->rates
[i
].Rate
|= rate
->hw_value_short
;
1083 if (bf
->bf_state
.bfs_paprd
)
1084 info
->rates
[i
].ChSel
= ah
->txchainmask
;
1086 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
1087 ah
->txchainmask
, info
->rates
[i
].Rate
);
1089 info
->rates
[i
].PktDuration
= ath9k_hw_computetxtime(sc
->sc_ah
,
1090 phy
, rate
->bitrate
* 100, len
, rix
, is_sp
);
1093 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1094 if (bf_isaggr(bf
) && (len
> sc
->sc_ah
->caps
.rts_aggr_limit
))
1095 info
->flags
&= ~ATH9K_TXDESC_RTSENA
;
1097 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1098 if (info
->flags
& ATH9K_TXDESC_RTSENA
)
1099 info
->flags
&= ~ATH9K_TXDESC_CTSENA
;
1102 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1104 struct ieee80211_hdr
*hdr
;
1105 enum ath9k_pkt_type htype
;
1108 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1109 fc
= hdr
->frame_control
;
1111 if (ieee80211_is_beacon(fc
))
1112 htype
= ATH9K_PKT_TYPE_BEACON
;
1113 else if (ieee80211_is_probe_resp(fc
))
1114 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
1115 else if (ieee80211_is_atim(fc
))
1116 htype
= ATH9K_PKT_TYPE_ATIM
;
1117 else if (ieee80211_is_pspoll(fc
))
1118 htype
= ATH9K_PKT_TYPE_PSPOLL
;
1120 htype
= ATH9K_PKT_TYPE_NORMAL
;
1125 static void ath_tx_fill_desc(struct ath_softc
*sc
, struct ath_buf
*bf
,
1126 struct ath_txq
*txq
, int len
)
1128 struct ath_hw
*ah
= sc
->sc_ah
;
1129 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1130 struct ath_buf
*bf_first
= bf
;
1131 struct ath_tx_info info
;
1132 bool aggr
= !!(bf
->bf_state
.bf_type
& BUF_AGGR
);
1134 memset(&info
, 0, sizeof(info
));
1135 info
.is_first
= true;
1136 info
.is_last
= true;
1137 info
.txpower
= MAX_RATE_POWER
;
1138 info
.qcu
= txq
->axq_qnum
;
1140 info
.flags
= ATH9K_TXDESC_INTREQ
;
1141 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1142 info
.flags
|= ATH9K_TXDESC_NOACK
;
1143 if (tx_info
->flags
& IEEE80211_TX_CTL_LDPC
)
1144 info
.flags
|= ATH9K_TXDESC_LDPC
;
1146 ath_buf_set_rate(sc
, bf
, &info
, len
);
1148 if (tx_info
->flags
& IEEE80211_TX_CTL_CLEAR_PS_FILT
)
1149 info
.flags
|= ATH9K_TXDESC_CLRDMASK
;
1151 if (bf
->bf_state
.bfs_paprd
)
1152 info
.flags
|= (u32
) bf
->bf_state
.bfs_paprd
<< ATH9K_TXDESC_PAPRD_S
;
1156 struct sk_buff
*skb
= bf
->bf_mpdu
;
1157 struct ath_frame_info
*fi
= get_frame_info(skb
);
1159 info
.type
= get_hw_packet_type(skb
);
1161 info
.link
= bf
->bf_next
->bf_daddr
;
1165 info
.buf_addr
[0] = bf
->bf_buf_addr
;
1166 info
.buf_len
[0] = skb
->len
;
1167 info
.pkt_len
= fi
->framelen
;
1168 info
.keyix
= fi
->keyix
;
1169 info
.keytype
= fi
->keytype
;
1173 info
.aggr
= AGGR_BUF_FIRST
;
1174 else if (!bf
->bf_next
)
1175 info
.aggr
= AGGR_BUF_LAST
;
1177 info
.aggr
= AGGR_BUF_MIDDLE
;
1179 info
.ndelim
= bf
->bf_state
.ndelim
;
1180 info
.aggr_len
= len
;
1183 ath9k_hw_set_txdesc(ah
, bf
->bf_desc
, &info
);
1188 static void ath_tx_sched_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
1189 struct ath_atx_tid
*tid
)
1192 enum ATH_AGGR_STATUS status
;
1193 struct ieee80211_tx_info
*tx_info
;
1194 struct list_head bf_q
;
1198 if (skb_queue_empty(&tid
->buf_q
))
1201 INIT_LIST_HEAD(&bf_q
);
1203 status
= ath_tx_form_aggr(sc
, txq
, tid
, &bf_q
, &aggr_len
);
1206 * no frames picked up to be aggregated;
1207 * block-ack window is not open.
1209 if (list_empty(&bf_q
))
1212 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1213 bf
->bf_lastbf
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1214 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1216 if (tid
->ac
->clear_ps_filter
) {
1217 tid
->ac
->clear_ps_filter
= false;
1218 tx_info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1220 tx_info
->flags
&= ~IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1223 /* if only one frame, send as non-aggregate */
1224 if (bf
== bf
->bf_lastbf
) {
1225 aggr_len
= get_frame_info(bf
->bf_mpdu
)->framelen
;
1226 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1228 TX_STAT_INC(txq
->axq_qnum
, a_aggr
);
1231 ath_tx_fill_desc(sc
, bf
, txq
, aggr_len
);
1232 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, false);
1233 } while (txq
->axq_ampdu_depth
< ATH_AGGR_MIN_QDEPTH
&&
1234 status
!= ATH_AGGR_BAW_CLOSED
);
1237 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
1240 struct ath_atx_tid
*txtid
;
1241 struct ath_node
*an
;
1244 an
= (struct ath_node
*)sta
->drv_priv
;
1245 txtid
= ATH_AN_2_TID(an
, tid
);
1247 if (txtid
->state
& (AGGR_CLEANUP
| AGGR_ADDBA_COMPLETE
))
1250 /* update ampdu factor/density, they may have changed. This may happen
1251 * in HT IBSS when a beacon with HT-info is received after the station
1252 * has already been added.
1254 if (sta
->ht_cap
.ht_supported
) {
1255 an
->maxampdu
= 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR
+
1256 sta
->ht_cap
.ampdu_factor
);
1257 density
= ath9k_parse_mpdudensity(sta
->ht_cap
.ampdu_density
);
1258 an
->mpdudensity
= density
;
1261 txtid
->state
|= AGGR_ADDBA_PROGRESS
;
1262 txtid
->paused
= true;
1263 *ssn
= txtid
->seq_start
= txtid
->seq_next
;
1264 txtid
->bar_index
= -1;
1266 memset(txtid
->tx_buf
, 0, sizeof(txtid
->tx_buf
));
1267 txtid
->baw_head
= txtid
->baw_tail
= 0;
1272 bool ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
,
1275 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
1276 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
1277 struct ath_txq
*txq
= txtid
->ac
->txq
;
1281 txtid
->stop_cb
= false;
1283 if (txtid
->state
& AGGR_CLEANUP
)
1286 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
1287 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
1291 ath_txq_lock(sc
, txq
);
1292 txtid
->paused
= true;
1295 * If frames are still being transmitted for this TID, they will be
1296 * cleaned up during tx completion. To prevent race conditions, this
1297 * TID can only be reused after all in-progress subframes have been
1300 if (txtid
->baw_head
!= txtid
->baw_tail
) {
1301 txtid
->state
|= AGGR_CLEANUP
;
1303 txtid
->stop_cb
= !flush
;
1305 txtid
->state
&= ~AGGR_ADDBA_COMPLETE
;
1308 ath_tx_flush_tid(sc
, txtid
, flush
);
1309 ath_txq_unlock_complete(sc
, txq
);
1313 void ath_tx_aggr_sleep(struct ieee80211_sta
*sta
, struct ath_softc
*sc
,
1314 struct ath_node
*an
)
1316 struct ath_atx_tid
*tid
;
1317 struct ath_atx_ac
*ac
;
1318 struct ath_txq
*txq
;
1322 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1323 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
1331 ath_txq_lock(sc
, txq
);
1333 buffered
= !skb_queue_empty(&tid
->buf_q
);
1336 list_del(&tid
->list
);
1340 list_del(&ac
->list
);
1343 ath_txq_unlock(sc
, txq
);
1345 ieee80211_sta_set_buffered(sta
, tidno
, buffered
);
1349 void ath_tx_aggr_wakeup(struct ath_softc
*sc
, struct ath_node
*an
)
1351 struct ath_atx_tid
*tid
;
1352 struct ath_atx_ac
*ac
;
1353 struct ath_txq
*txq
;
1356 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1357 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
1362 ath_txq_lock(sc
, txq
);
1363 ac
->clear_ps_filter
= true;
1365 if (!skb_queue_empty(&tid
->buf_q
) && !tid
->paused
) {
1366 ath_tx_queue_tid(txq
, tid
);
1367 ath_txq_schedule(sc
, txq
);
1370 ath_txq_unlock_complete(sc
, txq
);
1374 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
1376 struct ath_atx_tid
*txtid
;
1377 struct ath_node
*an
;
1379 an
= (struct ath_node
*)sta
->drv_priv
;
1381 txtid
= ATH_AN_2_TID(an
, tid
);
1382 txtid
->baw_size
= IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
1383 txtid
->state
|= AGGR_ADDBA_COMPLETE
;
1384 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
1385 ath_tx_resume_tid(sc
, txtid
);
1388 /********************/
1389 /* Queue Management */
1390 /********************/
1392 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
1394 struct ath_hw
*ah
= sc
->sc_ah
;
1395 struct ath9k_tx_queue_info qi
;
1396 static const int subtype_txq_to_hwq
[] = {
1397 [IEEE80211_AC_BE
] = ATH_TXQ_AC_BE
,
1398 [IEEE80211_AC_BK
] = ATH_TXQ_AC_BK
,
1399 [IEEE80211_AC_VI
] = ATH_TXQ_AC_VI
,
1400 [IEEE80211_AC_VO
] = ATH_TXQ_AC_VO
,
1404 memset(&qi
, 0, sizeof(qi
));
1405 qi
.tqi_subtype
= subtype_txq_to_hwq
[subtype
];
1406 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
1407 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
1408 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
1409 qi
.tqi_physCompBuf
= 0;
1412 * Enable interrupts only for EOL and DESC conditions.
1413 * We mark tx descriptors to receive a DESC interrupt
1414 * when a tx queue gets deep; otherwise waiting for the
1415 * EOL to reap descriptors. Note that this is done to
1416 * reduce interrupt load and this only defers reaping
1417 * descriptors, never transmitting frames. Aside from
1418 * reducing interrupts this also permits more concurrency.
1419 * The only potential downside is if the tx queue backs
1420 * up in which case the top half of the kernel may backup
1421 * due to a lack of tx descriptors.
1423 * The UAPSD queue is an exception, since we take a desc-
1424 * based intr on the EOSP frames.
1426 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1427 qi
.tqi_qflags
= TXQ_FLAG_TXINT_ENABLE
;
1429 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
1430 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
1432 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
1433 TXQ_FLAG_TXDESCINT_ENABLE
;
1435 axq_qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
1436 if (axq_qnum
== -1) {
1438 * NB: don't print a message, this happens
1439 * normally on parts with too few tx queues
1443 if (!ATH_TXQ_SETUP(sc
, axq_qnum
)) {
1444 struct ath_txq
*txq
= &sc
->tx
.txq
[axq_qnum
];
1446 txq
->axq_qnum
= axq_qnum
;
1447 txq
->mac80211_qnum
= -1;
1448 txq
->axq_link
= NULL
;
1449 __skb_queue_head_init(&txq
->complete_q
);
1450 INIT_LIST_HEAD(&txq
->axq_q
);
1451 INIT_LIST_HEAD(&txq
->axq_acq
);
1452 spin_lock_init(&txq
->axq_lock
);
1454 txq
->axq_ampdu_depth
= 0;
1455 txq
->axq_tx_inprogress
= false;
1456 sc
->tx
.txqsetup
|= 1<<axq_qnum
;
1458 txq
->txq_headidx
= txq
->txq_tailidx
= 0;
1459 for (i
= 0; i
< ATH_TXFIFO_DEPTH
; i
++)
1460 INIT_LIST_HEAD(&txq
->txq_fifo
[i
]);
1462 return &sc
->tx
.txq
[axq_qnum
];
1465 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
1466 struct ath9k_tx_queue_info
*qinfo
)
1468 struct ath_hw
*ah
= sc
->sc_ah
;
1470 struct ath9k_tx_queue_info qi
;
1472 BUG_ON(sc
->tx
.txq
[qnum
].axq_qnum
!= qnum
);
1474 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
1475 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
1476 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
1477 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
1478 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
1479 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
1481 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
1482 ath_err(ath9k_hw_common(sc
->sc_ah
),
1483 "Unable to update hardware queue %u!\n", qnum
);
1486 ath9k_hw_resettxqueue(ah
, qnum
);
1492 int ath_cabq_update(struct ath_softc
*sc
)
1494 struct ath9k_tx_queue_info qi
;
1495 struct ath_beacon_config
*cur_conf
= &sc
->cur_beacon_conf
;
1496 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
1498 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
1500 * Ensure the readytime % is within the bounds.
1502 if (sc
->config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
1503 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
1504 else if (sc
->config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
1505 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
1507 qi
.tqi_readyTime
= (cur_conf
->beacon_interval
*
1508 sc
->config
.cabqReadytime
) / 100;
1509 ath_txq_update(sc
, qnum
, &qi
);
1514 static void ath_drain_txq_list(struct ath_softc
*sc
, struct ath_txq
*txq
,
1515 struct list_head
*list
)
1517 struct ath_buf
*bf
, *lastbf
;
1518 struct list_head bf_head
;
1519 struct ath_tx_status ts
;
1521 memset(&ts
, 0, sizeof(ts
));
1522 ts
.ts_status
= ATH9K_TX_FLUSH
;
1523 INIT_LIST_HEAD(&bf_head
);
1525 while (!list_empty(list
)) {
1526 bf
= list_first_entry(list
, struct ath_buf
, list
);
1529 list_del(&bf
->list
);
1531 ath_tx_return_buffer(sc
, bf
);
1535 lastbf
= bf
->bf_lastbf
;
1536 list_cut_position(&bf_head
, list
, &lastbf
->list
);
1537 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
1542 * Drain a given TX queue (could be Beacon or Data)
1544 * This assumes output has been stopped and
1545 * we do not need to block ath_tx_tasklet.
1547 void ath_draintxq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1549 ath_txq_lock(sc
, txq
);
1551 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1552 int idx
= txq
->txq_tailidx
;
1554 while (!list_empty(&txq
->txq_fifo
[idx
])) {
1555 ath_drain_txq_list(sc
, txq
, &txq
->txq_fifo
[idx
]);
1557 INCR(idx
, ATH_TXFIFO_DEPTH
);
1559 txq
->txq_tailidx
= idx
;
1562 txq
->axq_link
= NULL
;
1563 txq
->axq_tx_inprogress
= false;
1564 ath_drain_txq_list(sc
, txq
, &txq
->axq_q
);
1566 ath_txq_unlock_complete(sc
, txq
);
1569 bool ath_drain_all_txq(struct ath_softc
*sc
)
1571 struct ath_hw
*ah
= sc
->sc_ah
;
1572 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1573 struct ath_txq
*txq
;
1577 if (test_bit(SC_OP_INVALID
, &sc
->sc_flags
))
1580 ath9k_hw_abort_tx_dma(ah
);
1582 /* Check if any queue remains active */
1583 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1584 if (!ATH_TXQ_SETUP(sc
, i
))
1587 if (ath9k_hw_numtxpending(ah
, sc
->tx
.txq
[i
].axq_qnum
))
1592 ath_err(common
, "Failed to stop TX DMA, queues=0x%03x!\n", npend
);
1594 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1595 if (!ATH_TXQ_SETUP(sc
, i
))
1599 * The caller will resume queues with ieee80211_wake_queues.
1600 * Mark the queue as not stopped to prevent ath_tx_complete
1601 * from waking the queue too early.
1603 txq
= &sc
->tx
.txq
[i
];
1604 txq
->stopped
= false;
1605 ath_draintxq(sc
, txq
);
1611 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1613 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1614 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1617 /* For each axq_acq entry, for each tid, try to schedule packets
1618 * for transmit until ampdu_depth has reached min Q depth.
1620 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
1622 struct ath_atx_ac
*ac
, *ac_tmp
, *last_ac
;
1623 struct ath_atx_tid
*tid
, *last_tid
;
1625 if (test_bit(SC_OP_HW_RESET
, &sc
->sc_flags
) ||
1626 list_empty(&txq
->axq_acq
) ||
1627 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1630 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
1631 last_ac
= list_entry(txq
->axq_acq
.prev
, struct ath_atx_ac
, list
);
1633 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1634 last_tid
= list_entry(ac
->tid_q
.prev
, struct ath_atx_tid
, list
);
1635 list_del(&ac
->list
);
1638 while (!list_empty(&ac
->tid_q
)) {
1639 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
,
1641 list_del(&tid
->list
);
1647 ath_tx_sched_aggr(sc
, txq
, tid
);
1650 * add tid to round-robin queue if more frames
1651 * are pending for the tid
1653 if (!skb_queue_empty(&tid
->buf_q
))
1654 ath_tx_queue_tid(txq
, tid
);
1656 if (tid
== last_tid
||
1657 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1661 if (!list_empty(&ac
->tid_q
) && !ac
->sched
) {
1663 list_add_tail(&ac
->list
, &txq
->axq_acq
);
1666 if (ac
== last_ac
||
1667 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1677 * Insert a chain of ath_buf (descriptors) on a txq and
1678 * assume the descriptors are already chained together by caller.
1680 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
1681 struct list_head
*head
, bool internal
)
1683 struct ath_hw
*ah
= sc
->sc_ah
;
1684 struct ath_common
*common
= ath9k_hw_common(ah
);
1685 struct ath_buf
*bf
, *bf_last
;
1686 bool puttxbuf
= false;
1690 * Insert the frame on the outbound list and
1691 * pass it on to the hardware.
1694 if (list_empty(head
))
1697 edma
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
);
1698 bf
= list_first_entry(head
, struct ath_buf
, list
);
1699 bf_last
= list_entry(head
->prev
, struct ath_buf
, list
);
1701 ath_dbg(common
, QUEUE
, "qnum: %d, txq depth: %d\n",
1702 txq
->axq_qnum
, txq
->axq_depth
);
1704 if (edma
&& list_empty(&txq
->txq_fifo
[txq
->txq_headidx
])) {
1705 list_splice_tail_init(head
, &txq
->txq_fifo
[txq
->txq_headidx
]);
1706 INCR(txq
->txq_headidx
, ATH_TXFIFO_DEPTH
);
1709 list_splice_tail_init(head
, &txq
->axq_q
);
1711 if (txq
->axq_link
) {
1712 ath9k_hw_set_desc_link(ah
, txq
->axq_link
, bf
->bf_daddr
);
1713 ath_dbg(common
, XMIT
, "link[%u] (%p)=%llx (%p)\n",
1714 txq
->axq_qnum
, txq
->axq_link
,
1715 ito64(bf
->bf_daddr
), bf
->bf_desc
);
1719 txq
->axq_link
= bf_last
->bf_desc
;
1723 TX_STAT_INC(txq
->axq_qnum
, puttxbuf
);
1724 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
1725 ath_dbg(common
, XMIT
, "TXDP[%u] = %llx (%p)\n",
1726 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
1730 TX_STAT_INC(txq
->axq_qnum
, txstart
);
1731 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
1736 if (bf_is_ampdu_not_probing(bf
))
1737 txq
->axq_ampdu_depth
++;
1741 static void ath_tx_send_ampdu(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
1742 struct sk_buff
*skb
, struct ath_tx_control
*txctl
)
1744 struct ath_frame_info
*fi
= get_frame_info(skb
);
1745 struct list_head bf_head
;
1749 * Do not queue to h/w when any of the following conditions is true:
1750 * - there are pending frames in software queue
1751 * - the TID is currently paused for ADDBA/BAR request
1752 * - seqno is not within block-ack window
1753 * - h/w queue depth exceeds low water mark
1755 if (!skb_queue_empty(&tid
->buf_q
) || tid
->paused
||
1756 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, tid
->seq_next
) ||
1757 txctl
->txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1759 * Add this frame to software queue for scheduling later
1762 TX_STAT_INC(txctl
->txq
->axq_qnum
, a_queued_sw
);
1763 __skb_queue_tail(&tid
->buf_q
, skb
);
1764 if (!txctl
->an
|| !txctl
->an
->sleeping
)
1765 ath_tx_queue_tid(txctl
->txq
, tid
);
1769 bf
= ath_tx_setup_buffer(sc
, txctl
->txq
, tid
, skb
);
1771 ieee80211_free_txskb(sc
->hw
, skb
);
1775 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1776 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1777 INIT_LIST_HEAD(&bf_head
);
1778 list_add(&bf
->list
, &bf_head
);
1780 /* Add sub-frame to BAW */
1781 ath_tx_addto_baw(sc
, tid
, bf
->bf_state
.seqno
);
1783 /* Queue to h/w without aggregation */
1784 TX_STAT_INC(txctl
->txq
->axq_qnum
, a_queued_hw
);
1786 ath_tx_fill_desc(sc
, bf
, txctl
->txq
, fi
->framelen
);
1787 ath_tx_txqaddbuf(sc
, txctl
->txq
, &bf_head
, false);
1790 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1791 struct ath_atx_tid
*tid
, struct sk_buff
*skb
)
1793 struct ath_frame_info
*fi
= get_frame_info(skb
);
1794 struct list_head bf_head
;
1799 INIT_LIST_HEAD(&bf_head
);
1800 list_add_tail(&bf
->list
, &bf_head
);
1801 bf
->bf_state
.bf_type
= 0;
1805 ath_tx_fill_desc(sc
, bf
, txq
, fi
->framelen
);
1806 ath_tx_txqaddbuf(sc
, txq
, &bf_head
, false);
1807 TX_STAT_INC(txq
->axq_qnum
, queued
);
1810 static void setup_frame_info(struct ieee80211_hw
*hw
,
1811 struct ieee80211_sta
*sta
,
1812 struct sk_buff
*skb
,
1815 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1816 struct ieee80211_key_conf
*hw_key
= tx_info
->control
.hw_key
;
1817 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1818 const struct ieee80211_rate
*rate
;
1819 struct ath_frame_info
*fi
= get_frame_info(skb
);
1820 struct ath_node
*an
= NULL
;
1821 enum ath9k_key_type keytype
;
1822 bool short_preamble
= false;
1825 * We check if Short Preamble is needed for the CTS rate by
1826 * checking the BSS's global flag.
1827 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1829 if (tx_info
->control
.vif
&&
1830 tx_info
->control
.vif
->bss_conf
.use_short_preamble
)
1831 short_preamble
= true;
1833 rate
= ieee80211_get_rts_cts_rate(hw
, tx_info
);
1834 keytype
= ath9k_cmn_get_hw_crypto_keytype(skb
);
1837 an
= (struct ath_node
*) sta
->drv_priv
;
1839 memset(fi
, 0, sizeof(*fi
));
1841 fi
->keyix
= hw_key
->hw_key_idx
;
1842 else if (an
&& ieee80211_is_data(hdr
->frame_control
) && an
->ps_key
> 0)
1843 fi
->keyix
= an
->ps_key
;
1845 fi
->keyix
= ATH9K_TXKEYIX_INVALID
;
1846 fi
->keytype
= keytype
;
1847 fi
->framelen
= framelen
;
1848 fi
->rtscts_rate
= rate
->hw_value
;
1850 fi
->rtscts_rate
|= rate
->hw_value_short
;
1853 u8
ath_txchainmask_reduction(struct ath_softc
*sc
, u8 chainmask
, u32 rate
)
1855 struct ath_hw
*ah
= sc
->sc_ah
;
1856 struct ath9k_channel
*curchan
= ah
->curchan
;
1858 if ((ah
->caps
.hw_caps
& ATH9K_HW_CAP_APM
) &&
1859 (curchan
->channelFlags
& CHANNEL_5GHZ
) &&
1860 (chainmask
== 0x7) && (rate
< 0x90))
1862 else if (AR_SREV_9462(ah
) && ath9k_hw_btcoex_is_enabled(ah
) &&
1870 * Assign a descriptor (and sequence number if necessary,
1871 * and map buffer for DMA. Frees skb on error
1873 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
1874 struct ath_txq
*txq
,
1875 struct ath_atx_tid
*tid
,
1876 struct sk_buff
*skb
)
1878 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1879 struct ath_frame_info
*fi
= get_frame_info(skb
);
1880 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1885 bf
= ath_tx_get_buffer(sc
);
1887 ath_dbg(common
, XMIT
, "TX buffers are full\n");
1891 ATH_TXBUF_RESET(bf
);
1894 fragno
= le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
;
1895 seqno
= tid
->seq_next
;
1896 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<< IEEE80211_SEQ_SEQ_SHIFT
);
1899 hdr
->seq_ctrl
|= cpu_to_le16(fragno
);
1901 if (!ieee80211_has_morefrags(hdr
->frame_control
))
1902 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
1904 bf
->bf_state
.seqno
= seqno
;
1909 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
1910 skb
->len
, DMA_TO_DEVICE
);
1911 if (unlikely(dma_mapping_error(sc
->dev
, bf
->bf_buf_addr
))) {
1913 bf
->bf_buf_addr
= 0;
1914 ath_err(ath9k_hw_common(sc
->sc_ah
),
1915 "dma_mapping_error() on TX\n");
1916 ath_tx_return_buffer(sc
, bf
);
1925 /* Upon failure caller should free skb */
1926 int ath_tx_start(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1927 struct ath_tx_control
*txctl
)
1929 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
1930 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1931 struct ieee80211_sta
*sta
= txctl
->sta
;
1932 struct ieee80211_vif
*vif
= info
->control
.vif
;
1933 struct ath_softc
*sc
= hw
->priv
;
1934 struct ath_txq
*txq
= txctl
->txq
;
1935 struct ath_atx_tid
*tid
= NULL
;
1937 int padpos
, padsize
;
1938 int frmlen
= skb
->len
+ FCS_LEN
;
1942 /* NOTE: sta can be NULL according to net/mac80211.h */
1944 txctl
->an
= (struct ath_node
*)sta
->drv_priv
;
1946 if (info
->control
.hw_key
)
1947 frmlen
+= info
->control
.hw_key
->icv_len
;
1950 * As a temporary workaround, assign seq# here; this will likely need
1951 * to be cleaned up to work better with Beacon transmission and virtual
1954 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
1955 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
1956 sc
->tx
.seq_no
+= 0x10;
1957 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
1958 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
1961 /* Add the padding after the header if this is not already done */
1962 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
1963 padsize
= padpos
& 3;
1964 if (padsize
&& skb
->len
> padpos
) {
1965 if (skb_headroom(skb
) < padsize
)
1968 skb_push(skb
, padsize
);
1969 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
1970 hdr
= (struct ieee80211_hdr
*) skb
->data
;
1973 if ((vif
&& vif
->type
!= NL80211_IFTYPE_AP
&&
1974 vif
->type
!= NL80211_IFTYPE_AP_VLAN
) ||
1975 !ieee80211_is_data(hdr
->frame_control
))
1976 info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1978 setup_frame_info(hw
, sta
, skb
, frmlen
);
1981 * At this point, the vif, hw_key and sta pointers in the tx control
1982 * info are no longer valid (overwritten by the ath_frame_info data.
1985 q
= skb_get_queue_mapping(skb
);
1987 ath_txq_lock(sc
, txq
);
1988 if (txq
== sc
->tx
.txq_map
[q
] &&
1989 ++txq
->pending_frames
> sc
->tx
.txq_max_pending
[q
] &&
1991 ieee80211_stop_queue(sc
->hw
, q
);
1992 txq
->stopped
= true;
1995 if (txctl
->an
&& ieee80211_is_data_qos(hdr
->frame_control
)) {
1996 tidno
= ieee80211_get_qos_ctl(hdr
)[0] &
1997 IEEE80211_QOS_CTL_TID_MASK
;
1998 tid
= ATH_AN_2_TID(txctl
->an
, tidno
);
2000 WARN_ON(tid
->ac
->txq
!= txctl
->txq
);
2003 if ((info
->flags
& IEEE80211_TX_CTL_AMPDU
) && tid
) {
2005 * Try aggregation if it's a unicast data frame
2006 * and the destination is HT capable.
2008 ath_tx_send_ampdu(sc
, tid
, skb
, txctl
);
2012 bf
= ath_tx_setup_buffer(sc
, txctl
->txq
, tid
, skb
);
2015 dev_kfree_skb_any(skb
);
2017 ieee80211_free_txskb(sc
->hw
, skb
);
2021 bf
->bf_state
.bfs_paprd
= txctl
->paprd
;
2024 bf
->bf_state
.bfs_paprd_timestamp
= jiffies
;
2026 ath_set_rates(vif
, sta
, bf
);
2027 ath_tx_send_normal(sc
, txctl
->txq
, tid
, skb
);
2030 ath_txq_unlock(sc
, txq
);
2039 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
2040 int tx_flags
, struct ath_txq
*txq
)
2042 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2043 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2044 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
2045 int q
, padpos
, padsize
;
2046 unsigned long flags
;
2048 ath_dbg(common
, XMIT
, "TX complete: skb: %p\n", skb
);
2050 if (sc
->sc_ah
->caldata
)
2051 sc
->sc_ah
->caldata
->paprd_packet_sent
= true;
2053 if (!(tx_flags
& ATH_TX_ERROR
))
2054 /* Frame was ACKed */
2055 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
2057 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2058 padsize
= padpos
& 3;
2059 if (padsize
&& skb
->len
>padpos
+padsize
) {
2061 * Remove MAC header padding before giving the frame back to
2064 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
2065 skb_pull(skb
, padsize
);
2068 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
2069 if ((sc
->ps_flags
& PS_WAIT_FOR_TX_ACK
) && !txq
->axq_depth
) {
2070 sc
->ps_flags
&= ~PS_WAIT_FOR_TX_ACK
;
2072 "Going back to sleep after having received TX status (0x%lx)\n",
2073 sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
2075 PS_WAIT_FOR_PSPOLL_DATA
|
2076 PS_WAIT_FOR_TX_ACK
));
2078 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
2080 q
= skb_get_queue_mapping(skb
);
2081 if (txq
== sc
->tx
.txq_map
[q
]) {
2082 if (WARN_ON(--txq
->pending_frames
< 0))
2083 txq
->pending_frames
= 0;
2086 txq
->pending_frames
< sc
->tx
.txq_max_pending
[q
]) {
2087 ieee80211_wake_queue(sc
->hw
, q
);
2088 txq
->stopped
= false;
2092 __skb_queue_tail(&txq
->complete_q
, skb
);
2095 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
2096 struct ath_txq
*txq
, struct list_head
*bf_q
,
2097 struct ath_tx_status
*ts
, int txok
)
2099 struct sk_buff
*skb
= bf
->bf_mpdu
;
2100 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2101 unsigned long flags
;
2105 tx_flags
|= ATH_TX_ERROR
;
2107 if (ts
->ts_status
& ATH9K_TXERR_FILT
)
2108 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
2110 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
, skb
->len
, DMA_TO_DEVICE
);
2111 bf
->bf_buf_addr
= 0;
2113 if (bf
->bf_state
.bfs_paprd
) {
2114 if (time_after(jiffies
,
2115 bf
->bf_state
.bfs_paprd_timestamp
+
2116 msecs_to_jiffies(ATH_PAPRD_TIMEOUT
)))
2117 dev_kfree_skb_any(skb
);
2119 complete(&sc
->paprd_complete
);
2121 ath_debug_stat_tx(sc
, bf
, ts
, txq
, tx_flags
);
2122 ath_tx_complete(sc
, skb
, tx_flags
, txq
);
2124 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2125 * accidentally reference it later.
2130 * Return the list of ath_buf of this mpdu to free queue
2132 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
2133 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
2134 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
2137 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
2138 struct ath_tx_status
*ts
, int nframes
, int nbad
,
2141 struct sk_buff
*skb
= bf
->bf_mpdu
;
2142 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2143 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2144 struct ieee80211_hw
*hw
= sc
->hw
;
2145 struct ath_hw
*ah
= sc
->sc_ah
;
2149 tx_info
->status
.ack_signal
= ts
->ts_rssi
;
2151 tx_rateindex
= ts
->ts_rateindex
;
2152 WARN_ON(tx_rateindex
>= hw
->max_rates
);
2154 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
2155 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
2157 BUG_ON(nbad
> nframes
);
2159 tx_info
->status
.ampdu_len
= nframes
;
2160 tx_info
->status
.ampdu_ack_len
= nframes
- nbad
;
2162 if ((ts
->ts_status
& ATH9K_TXERR_FILT
) == 0 &&
2163 (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
) == 0) {
2165 * If an underrun error is seen assume it as an excessive
2166 * retry only if max frame trigger level has been reached
2167 * (2 KB for single stream, and 4 KB for dual stream).
2168 * Adjust the long retry as if the frame was tried
2169 * hw->max_rate_tries times to affect how rate control updates
2170 * PER for the failed rate.
2171 * In case of congestion on the bus penalizing this type of
2172 * underruns should help hardware actually transmit new frames
2173 * successfully by eventually preferring slower rates.
2174 * This itself should also alleviate congestion on the bus.
2176 if (unlikely(ts
->ts_flags
& (ATH9K_TX_DATA_UNDERRUN
|
2177 ATH9K_TX_DELIM_UNDERRUN
)) &&
2178 ieee80211_is_data(hdr
->frame_control
) &&
2179 ah
->tx_trig_level
>= sc
->sc_ah
->config
.max_txtrig_level
)
2180 tx_info
->status
.rates
[tx_rateindex
].count
=
2184 for (i
= tx_rateindex
+ 1; i
< hw
->max_rates
; i
++) {
2185 tx_info
->status
.rates
[i
].count
= 0;
2186 tx_info
->status
.rates
[i
].idx
= -1;
2189 tx_info
->status
.rates
[tx_rateindex
].count
= ts
->ts_longretry
+ 1;
2192 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2194 struct ath_hw
*ah
= sc
->sc_ah
;
2195 struct ath_common
*common
= ath9k_hw_common(ah
);
2196 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
2197 struct list_head bf_head
;
2198 struct ath_desc
*ds
;
2199 struct ath_tx_status ts
;
2202 ath_dbg(common
, QUEUE
, "tx queue %d (%x), link %p\n",
2203 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
2206 ath_txq_lock(sc
, txq
);
2208 if (test_bit(SC_OP_HW_RESET
, &sc
->sc_flags
))
2211 if (list_empty(&txq
->axq_q
)) {
2212 txq
->axq_link
= NULL
;
2213 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_HT
)
2214 ath_txq_schedule(sc
, txq
);
2217 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2220 * There is a race condition that a BH gets scheduled
2221 * after sw writes TxE and before hw re-load the last
2222 * descriptor to get the newly chained one.
2223 * Software must keep the last DONE descriptor as a
2224 * holding descriptor - software does so by marking
2225 * it with the STALE flag.
2230 if (list_is_last(&bf_held
->list
, &txq
->axq_q
))
2233 bf
= list_entry(bf_held
->list
.next
, struct ath_buf
,
2237 lastbf
= bf
->bf_lastbf
;
2238 ds
= lastbf
->bf_desc
;
2240 memset(&ts
, 0, sizeof(ts
));
2241 status
= ath9k_hw_txprocdesc(ah
, ds
, &ts
);
2242 if (status
== -EINPROGRESS
)
2245 TX_STAT_INC(txq
->axq_qnum
, txprocdesc
);
2248 * Remove ath_buf's of the same transmit unit from txq,
2249 * however leave the last descriptor back as the holding
2250 * descriptor for hw.
2252 lastbf
->bf_stale
= true;
2253 INIT_LIST_HEAD(&bf_head
);
2254 if (!list_is_singular(&lastbf
->list
))
2255 list_cut_position(&bf_head
,
2256 &txq
->axq_q
, lastbf
->list
.prev
);
2259 list_del(&bf_held
->list
);
2260 ath_tx_return_buffer(sc
, bf_held
);
2263 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2265 ath_txq_unlock_complete(sc
, txq
);
2268 void ath_tx_tasklet(struct ath_softc
*sc
)
2270 struct ath_hw
*ah
= sc
->sc_ah
;
2271 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1) & ah
->intr_txqs
;
2274 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2275 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2276 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2280 void ath_tx_edma_tasklet(struct ath_softc
*sc
)
2282 struct ath_tx_status ts
;
2283 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2284 struct ath_hw
*ah
= sc
->sc_ah
;
2285 struct ath_txq
*txq
;
2286 struct ath_buf
*bf
, *lastbf
;
2287 struct list_head bf_head
;
2288 struct list_head
*fifo_list
;
2292 if (test_bit(SC_OP_HW_RESET
, &sc
->sc_flags
))
2295 status
= ath9k_hw_txprocdesc(ah
, NULL
, (void *)&ts
);
2296 if (status
== -EINPROGRESS
)
2298 if (status
== -EIO
) {
2299 ath_dbg(common
, XMIT
, "Error processing tx status\n");
2303 /* Process beacon completions separately */
2304 if (ts
.qid
== sc
->beacon
.beaconq
) {
2305 sc
->beacon
.tx_processed
= true;
2306 sc
->beacon
.tx_last
= !(ts
.ts_status
& ATH9K_TXERR_MASK
);
2310 txq
= &sc
->tx
.txq
[ts
.qid
];
2312 ath_txq_lock(sc
, txq
);
2314 TX_STAT_INC(txq
->axq_qnum
, txprocdesc
);
2316 fifo_list
= &txq
->txq_fifo
[txq
->txq_tailidx
];
2317 if (list_empty(fifo_list
)) {
2318 ath_txq_unlock(sc
, txq
);
2322 bf
= list_first_entry(fifo_list
, struct ath_buf
, list
);
2324 list_del(&bf
->list
);
2325 ath_tx_return_buffer(sc
, bf
);
2326 bf
= list_first_entry(fifo_list
, struct ath_buf
, list
);
2329 lastbf
= bf
->bf_lastbf
;
2331 INIT_LIST_HEAD(&bf_head
);
2332 if (list_is_last(&lastbf
->list
, fifo_list
)) {
2333 list_splice_tail_init(fifo_list
, &bf_head
);
2334 INCR(txq
->txq_tailidx
, ATH_TXFIFO_DEPTH
);
2336 if (!list_empty(&txq
->axq_q
)) {
2337 struct list_head bf_q
;
2339 INIT_LIST_HEAD(&bf_q
);
2340 txq
->axq_link
= NULL
;
2341 list_splice_tail_init(&txq
->axq_q
, &bf_q
);
2342 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, true);
2345 lastbf
->bf_stale
= true;
2347 list_cut_position(&bf_head
, fifo_list
,
2351 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2352 ath_txq_unlock_complete(sc
, txq
);
2360 static int ath_txstatus_setup(struct ath_softc
*sc
, int size
)
2362 struct ath_descdma
*dd
= &sc
->txsdma
;
2363 u8 txs_len
= sc
->sc_ah
->caps
.txs_len
;
2365 dd
->dd_desc_len
= size
* txs_len
;
2366 dd
->dd_desc
= dmam_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
2367 &dd
->dd_desc_paddr
, GFP_KERNEL
);
2374 static int ath_tx_edma_init(struct ath_softc
*sc
)
2378 err
= ath_txstatus_setup(sc
, ATH_TXSTATUS_RING_SIZE
);
2380 ath9k_hw_setup_statusring(sc
->sc_ah
, sc
->txsdma
.dd_desc
,
2381 sc
->txsdma
.dd_desc_paddr
,
2382 ATH_TXSTATUS_RING_SIZE
);
2387 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2389 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2392 spin_lock_init(&sc
->tx
.txbuflock
);
2394 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
2398 "Failed to allocate tx descriptors: %d\n", error
);
2402 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
2403 "beacon", ATH_BCBUF
, 1, 1);
2406 "Failed to allocate beacon descriptors: %d\n", error
);
2410 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath_tx_complete_poll_work
);
2412 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
2413 error
= ath_tx_edma_init(sc
);
2418 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2420 struct ath_atx_tid
*tid
;
2421 struct ath_atx_ac
*ac
;
2424 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2425 tidno
< IEEE80211_NUM_TIDS
;
2429 tid
->seq_start
= tid
->seq_next
= 0;
2430 tid
->baw_size
= WME_MAX_BA
;
2431 tid
->baw_head
= tid
->baw_tail
= 0;
2433 tid
->paused
= false;
2434 tid
->state
&= ~AGGR_CLEANUP
;
2435 __skb_queue_head_init(&tid
->buf_q
);
2436 acno
= TID_TO_WME_AC(tidno
);
2437 tid
->ac
= &an
->ac
[acno
];
2438 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2439 tid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2440 tid
->stop_cb
= false;
2443 for (acno
= 0, ac
= &an
->ac
[acno
];
2444 acno
< IEEE80211_NUM_ACS
; acno
++, ac
++) {
2446 ac
->txq
= sc
->tx
.txq_map
[acno
];
2447 INIT_LIST_HEAD(&ac
->tid_q
);
2451 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2453 struct ath_atx_ac
*ac
;
2454 struct ath_atx_tid
*tid
;
2455 struct ath_txq
*txq
;
2458 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2459 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
2464 ath_txq_lock(sc
, txq
);
2467 list_del(&tid
->list
);
2472 list_del(&ac
->list
);
2473 tid
->ac
->sched
= false;
2476 ath_tid_drain(sc
, txq
, tid
);
2477 ath_tx_clear_tid(sc
, tid
);
2479 ath_txq_unlock(sc
, txq
);