2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x1f)
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
35 #define OFDM_SIFS_TIME 16
37 static u16 bits_per_symbol
[][2] = {
39 { 26, 54 }, /* 0: BPSK */
40 { 52, 108 }, /* 1: QPSK 1/2 */
41 { 78, 162 }, /* 2: QPSK 3/4 */
42 { 104, 216 }, /* 3: 16-QAM 1/2 */
43 { 156, 324 }, /* 4: 16-QAM 3/4 */
44 { 208, 432 }, /* 5: 64-QAM 2/3 */
45 { 234, 486 }, /* 6: 64-QAM 3/4 */
46 { 260, 540 }, /* 7: 64-QAM 5/6 */
49 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
51 static void ath_tx_send_ht_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
52 struct ath_atx_tid
*tid
,
53 struct list_head
*bf_head
);
54 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
55 struct ath_txq
*txq
, struct list_head
*bf_q
,
56 struct ath_tx_status
*ts
, int txok
, int sendbar
);
57 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
58 struct list_head
*head
);
59 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
);
60 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
61 struct ath_tx_status
*ts
, int txok
);
62 static void ath_tx_rc_status(struct ath_buf
*bf
, struct ath_tx_status
*ts
,
63 int nbad
, int txok
, bool update_rc
);
72 static int ath_max_4ms_framelen
[4][32] = {
74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
99 /*********************/
100 /* Aggregation logic */
101 /*********************/
103 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
105 struct ath_atx_ac
*ac
= tid
->ac
;
114 list_add_tail(&tid
->list
, &ac
->tid_q
);
120 list_add_tail(&ac
->list
, &txq
->axq_acq
);
123 static void ath_tx_pause_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
125 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
127 spin_lock_bh(&txq
->axq_lock
);
129 spin_unlock_bh(&txq
->axq_lock
);
132 static void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
134 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
136 BUG_ON(tid
->paused
<= 0);
137 spin_lock_bh(&txq
->axq_lock
);
144 if (list_empty(&tid
->buf_q
))
147 ath_tx_queue_tid(txq
, tid
);
148 ath_txq_schedule(sc
, txq
);
150 spin_unlock_bh(&txq
->axq_lock
);
153 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
155 struct ath_txq
*txq
= &sc
->tx
.txq
[tid
->ac
->qnum
];
157 struct list_head bf_head
;
158 INIT_LIST_HEAD(&bf_head
);
160 BUG_ON(tid
->paused
<= 0);
161 spin_lock_bh(&txq
->axq_lock
);
165 if (tid
->paused
> 0) {
166 spin_unlock_bh(&txq
->axq_lock
);
170 while (!list_empty(&tid
->buf_q
)) {
171 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
172 BUG_ON(bf_isretried(bf
));
173 list_move_tail(&bf
->list
, &bf_head
);
174 ath_tx_send_ht_normal(sc
, txq
, tid
, &bf_head
);
177 spin_unlock_bh(&txq
->axq_lock
);
180 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
185 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
186 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
188 tid
->tx_buf
[cindex
] = NULL
;
190 while (tid
->baw_head
!= tid
->baw_tail
&& !tid
->tx_buf
[tid
->baw_head
]) {
191 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
192 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
196 static void ath_tx_addto_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
201 if (bf_isretried(bf
))
204 index
= ATH_BA_INDEX(tid
->seq_start
, bf
->bf_seqno
);
205 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
207 BUG_ON(tid
->tx_buf
[cindex
] != NULL
);
208 tid
->tx_buf
[cindex
] = bf
;
210 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
211 (ATH_TID_MAX_BUFS
- 1))) {
212 tid
->baw_tail
= cindex
;
213 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
218 * TODO: For frame(s) that are in the retry state, we will reuse the
219 * sequence number(s) without setting the retry bit. The
220 * alternative is to give up on these and BAR the receiver's window
223 static void ath_tid_drain(struct ath_softc
*sc
, struct ath_txq
*txq
,
224 struct ath_atx_tid
*tid
)
228 struct list_head bf_head
;
229 struct ath_tx_status ts
;
231 memset(&ts
, 0, sizeof(ts
));
232 INIT_LIST_HEAD(&bf_head
);
235 if (list_empty(&tid
->buf_q
))
238 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
239 list_move_tail(&bf
->list
, &bf_head
);
241 if (bf_isretried(bf
))
242 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
244 spin_unlock(&txq
->axq_lock
);
245 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0, 0);
246 spin_lock(&txq
->axq_lock
);
249 tid
->seq_next
= tid
->seq_start
;
250 tid
->baw_tail
= tid
->baw_head
;
253 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_txq
*txq
,
257 struct ieee80211_hdr
*hdr
;
259 bf
->bf_state
.bf_type
|= BUF_RETRY
;
261 TX_STAT_INC(txq
->axq_qnum
, a_retries
);
264 hdr
= (struct ieee80211_hdr
*)skb
->data
;
265 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
268 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
270 struct ath_buf
*bf
= NULL
;
272 spin_lock_bh(&sc
->tx
.txbuflock
);
274 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
275 spin_unlock_bh(&sc
->tx
.txbuflock
);
279 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
282 spin_unlock_bh(&sc
->tx
.txbuflock
);
287 static void ath_tx_return_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
)
289 spin_lock_bh(&sc
->tx
.txbuflock
);
290 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
291 spin_unlock_bh(&sc
->tx
.txbuflock
);
294 static struct ath_buf
* ath_clone_txbuf(struct ath_softc
*sc
, struct ath_buf
*bf
)
298 tbf
= ath_tx_get_buffer(sc
);
302 ATH_TXBUF_RESET(tbf
);
304 tbf
->aphy
= bf
->aphy
;
305 tbf
->bf_mpdu
= bf
->bf_mpdu
;
306 tbf
->bf_buf_addr
= bf
->bf_buf_addr
;
307 memcpy(tbf
->bf_desc
, bf
->bf_desc
, sc
->sc_ah
->caps
.tx_desc_len
);
308 tbf
->bf_state
= bf
->bf_state
;
309 tbf
->bf_dmacontext
= bf
->bf_dmacontext
;
314 static void ath_tx_complete_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
315 struct ath_buf
*bf
, struct list_head
*bf_q
,
316 struct ath_tx_status
*ts
, int txok
)
318 struct ath_node
*an
= NULL
;
320 struct ieee80211_sta
*sta
;
321 struct ieee80211_hw
*hw
;
322 struct ieee80211_hdr
*hdr
;
323 struct ieee80211_tx_info
*tx_info
;
324 struct ath_atx_tid
*tid
= NULL
;
325 struct ath_buf
*bf_next
, *bf_last
= bf
->bf_lastbf
;
326 struct list_head bf_head
, bf_pending
;
327 u16 seq_st
= 0, acked_cnt
= 0, txfail_cnt
= 0;
328 u32 ba
[WME_BA_BMP_SIZE
>> 5];
329 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0, nbad
= 0;
330 bool rc_update
= true;
333 hdr
= (struct ieee80211_hdr
*)skb
->data
;
335 tx_info
= IEEE80211_SKB_CB(skb
);
340 /* XXX: use ieee80211_find_sta! */
341 sta
= ieee80211_find_sta_by_hw(hw
, hdr
->addr1
);
347 an
= (struct ath_node
*)sta
->drv_priv
;
348 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
350 isaggr
= bf_isaggr(bf
);
351 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
353 if (isaggr
&& txok
) {
354 if (ts
->ts_flags
& ATH9K_TX_BA
) {
355 seq_st
= ts
->ts_seqnum
;
356 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
359 * AR5416 can become deaf/mute when BA
360 * issue happens. Chip needs to be reset.
361 * But AP code may have sychronization issues
362 * when perform internal reset in this routine.
363 * Only enable reset in STA mode for now.
365 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
)
370 INIT_LIST_HEAD(&bf_pending
);
371 INIT_LIST_HEAD(&bf_head
);
373 nbad
= ath_tx_num_badfrms(sc
, bf
, ts
, txok
);
375 txfail
= txpending
= 0;
376 bf_next
= bf
->bf_next
;
378 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, bf
->bf_seqno
))) {
379 /* transmit completion, subframe is
380 * acked by block ack */
382 } else if (!isaggr
&& txok
) {
383 /* transmit completion */
386 if (!(tid
->state
& AGGR_CLEANUP
) &&
387 !bf_last
->bf_tx_aborted
) {
388 if (bf
->bf_retries
< ATH_MAX_SW_RETRIES
) {
389 ath_tx_set_retry(sc
, txq
, bf
);
392 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
399 * cleanup in progress, just fail
400 * the un-acked sub-frames
406 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) &&
409 * Make sure the last desc is reclaimed if it
410 * not a holding desc.
412 if (!bf_last
->bf_stale
)
413 list_move_tail(&bf
->list
, &bf_head
);
415 INIT_LIST_HEAD(&bf_head
);
417 BUG_ON(list_empty(bf_q
));
418 list_move_tail(&bf
->list
, &bf_head
);
423 * complete the acked-ones/xretried ones; update
426 spin_lock_bh(&txq
->axq_lock
);
427 ath_tx_update_baw(sc
, tid
, bf
->bf_seqno
);
428 spin_unlock_bh(&txq
->axq_lock
);
430 if (rc_update
&& (acked_cnt
== 1 || txfail_cnt
== 1)) {
431 ath_tx_rc_status(bf
, ts
, nbad
, txok
, true);
434 ath_tx_rc_status(bf
, ts
, nbad
, txok
, false);
437 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
,
440 /* retry the un-acked ones */
441 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)) {
442 if (bf
->bf_next
== NULL
&& bf_last
->bf_stale
) {
445 tbf
= ath_clone_txbuf(sc
, bf_last
);
447 * Update tx baw and complete the
448 * frame with failed status if we
452 spin_lock_bh(&txq
->axq_lock
);
453 ath_tx_update_baw(sc
, tid
,
455 spin_unlock_bh(&txq
->axq_lock
);
457 bf
->bf_state
.bf_type
|=
459 ath_tx_rc_status(bf
, ts
, nbad
,
461 ath_tx_complete_buf(sc
, bf
, txq
,
467 ath9k_hw_cleartxdesc(sc
->sc_ah
,
469 list_add_tail(&tbf
->list
, &bf_head
);
472 * Clear descriptor status words for
475 ath9k_hw_cleartxdesc(sc
->sc_ah
,
481 * Put this buffer to the temporary pending
482 * queue to retain ordering
484 list_splice_tail_init(&bf_head
, &bf_pending
);
490 if (tid
->state
& AGGR_CLEANUP
) {
491 if (tid
->baw_head
== tid
->baw_tail
) {
492 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
493 tid
->state
&= ~AGGR_CLEANUP
;
495 /* send buffered frames as singles */
496 ath_tx_flush_tid(sc
, tid
);
502 /* prepend un-acked frames to the beginning of the pending frame queue */
503 if (!list_empty(&bf_pending
)) {
504 spin_lock_bh(&txq
->axq_lock
);
505 list_splice(&bf_pending
, &tid
->buf_q
);
506 ath_tx_queue_tid(txq
, tid
);
507 spin_unlock_bh(&txq
->axq_lock
);
513 ath_reset(sc
, false);
516 static u32
ath_lookup_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
517 struct ath_atx_tid
*tid
)
520 struct ieee80211_tx_info
*tx_info
;
521 struct ieee80211_tx_rate
*rates
;
522 u32 max_4ms_framelen
, frmlen
;
523 u16 aggr_limit
, legacy
= 0;
527 tx_info
= IEEE80211_SKB_CB(skb
);
528 rates
= tx_info
->control
.rates
;
531 * Find the lowest frame length among the rate series that will have a
532 * 4ms transmit duration.
533 * TODO - TXOP limit needs to be considered.
535 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
537 for (i
= 0; i
< 4; i
++) {
538 if (rates
[i
].count
) {
540 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
)) {
545 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
550 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
553 frmlen
= ath_max_4ms_framelen
[modeidx
][rates
[i
].idx
];
554 max_4ms_framelen
= min(max_4ms_framelen
, frmlen
);
559 * limit aggregate size by the minimum rate if rate selected is
560 * not a probe rate, if rate selected is a probe rate then
561 * avoid aggregation of this packet.
563 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
566 if (sc
->sc_flags
& SC_OP_BT_PRIORITY_DETECTED
)
567 aggr_limit
= min((max_4ms_framelen
* 3) / 8,
568 (u32
)ATH_AMPDU_LIMIT_MAX
);
570 aggr_limit
= min(max_4ms_framelen
,
571 (u32
)ATH_AMPDU_LIMIT_MAX
);
574 * h/w can accept aggregates upto 16 bit lengths (65535).
575 * The IE, however can hold upto 65536, which shows up here
576 * as zero. Ignore 65536 since we are constrained by hw.
578 if (tid
->an
->maxampdu
)
579 aggr_limit
= min(aggr_limit
, tid
->an
->maxampdu
);
585 * Returns the number of delimiters to be added to
586 * meet the minimum required mpdudensity.
588 static int ath_compute_num_delims(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
589 struct ath_buf
*bf
, u16 frmlen
)
591 struct sk_buff
*skb
= bf
->bf_mpdu
;
592 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
593 u32 nsymbits
, nsymbols
;
596 int width
, streams
, half_gi
, ndelim
, mindelim
;
598 /* Select standard number of delimiters based on frame length alone */
599 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
602 * If encryption enabled, hardware requires some more padding between
604 * TODO - this could be improved to be dependent on the rate.
605 * The hardware can keep up at lower rates, but not higher rates
607 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
)
608 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
611 * Convert desired mpdu density from microeconds to bytes based
612 * on highest rate in rate series (i.e. first rate) to determine
613 * required minimum length for subframe. Take into account
614 * whether high rate is 20 or 40Mhz and half or full GI.
616 * If there is no mpdu density restriction, no further calculation
620 if (tid
->an
->mpdudensity
== 0)
623 rix
= tx_info
->control
.rates
[0].idx
;
624 flags
= tx_info
->control
.rates
[0].flags
;
625 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
626 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
629 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(tid
->an
->mpdudensity
);
631 nsymbols
= NUM_SYMBOLS_PER_USEC(tid
->an
->mpdudensity
);
636 streams
= HT_RC_2_STREAMS(rix
);
637 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
638 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
640 if (frmlen
< minlen
) {
641 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
642 ndelim
= max(mindelim
, ndelim
);
648 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
650 struct ath_atx_tid
*tid
,
651 struct list_head
*bf_q
)
653 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
654 struct ath_buf
*bf
, *bf_first
, *bf_prev
= NULL
;
655 int rl
= 0, nframes
= 0, ndelim
, prev_al
= 0;
656 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
657 al_delta
, h_baw
= tid
->baw_size
/ 2;
658 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
660 bf_first
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
663 bf
= list_first_entry(&tid
->buf_q
, struct ath_buf
, list
);
665 /* do not step over block-ack window */
666 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
)) {
667 status
= ATH_AGGR_BAW_CLOSED
;
672 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
676 /* do not exceed aggregation limit */
677 al_delta
= ATH_AGGR_DELIM_SZ
+ bf
->bf_frmlen
;
680 (aggr_limit
< (al
+ bpad
+ al_delta
+ prev_al
))) {
681 status
= ATH_AGGR_LIMITED
;
685 /* do not exceed subframe limit */
686 if (nframes
>= min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
687 status
= ATH_AGGR_LIMITED
;
692 /* add padding for previous frame to aggregation length */
693 al
+= bpad
+ al_delta
;
696 * Get the delimiters needed to meet the MPDU
697 * density for this node.
699 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, bf
->bf_frmlen
);
700 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
703 ath9k_hw_set_desc_link(sc
->sc_ah
, bf
->bf_desc
, 0);
705 /* link buffers of this frame to the aggregate */
706 ath_tx_addto_baw(sc
, tid
, bf
);
707 ath9k_hw_set11n_aggr_middle(sc
->sc_ah
, bf
->bf_desc
, ndelim
);
708 list_move_tail(&bf
->list
, bf_q
);
710 bf_prev
->bf_next
= bf
;
711 ath9k_hw_set_desc_link(sc
->sc_ah
, bf_prev
->bf_desc
,
716 } while (!list_empty(&tid
->buf_q
));
718 bf_first
->bf_al
= al
;
719 bf_first
->bf_nframes
= nframes
;
725 static void ath_tx_sched_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
726 struct ath_atx_tid
*tid
)
729 enum ATH_AGGR_STATUS status
;
730 struct list_head bf_q
;
733 if (list_empty(&tid
->buf_q
))
736 INIT_LIST_HEAD(&bf_q
);
738 status
= ath_tx_form_aggr(sc
, txq
, tid
, &bf_q
);
741 * no frames picked up to be aggregated;
742 * block-ack window is not open.
744 if (list_empty(&bf_q
))
747 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
748 bf
->bf_lastbf
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
750 /* if only one frame, send as non-aggregate */
751 if (bf
->bf_nframes
== 1) {
752 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
753 ath9k_hw_clr11n_aggr(sc
->sc_ah
, bf
->bf_desc
);
754 ath_buf_set_rate(sc
, bf
);
755 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
759 /* setup first desc of aggregate */
760 bf
->bf_state
.bf_type
|= BUF_AGGR
;
761 ath_buf_set_rate(sc
, bf
);
762 ath9k_hw_set11n_aggr_first(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_al
);
764 /* anchor last desc of aggregate */
765 ath9k_hw_set11n_aggr_last(sc
->sc_ah
, bf
->bf_lastbf
->bf_desc
);
767 ath_tx_txqaddbuf(sc
, txq
, &bf_q
);
768 TX_STAT_INC(txq
->axq_qnum
, a_aggr
);
770 } while (txq
->axq_depth
< ATH_AGGR_MIN_QDEPTH
&&
771 status
!= ATH_AGGR_BAW_CLOSED
);
774 void ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
777 struct ath_atx_tid
*txtid
;
780 an
= (struct ath_node
*)sta
->drv_priv
;
781 txtid
= ATH_AN_2_TID(an
, tid
);
782 txtid
->state
|= AGGR_ADDBA_PROGRESS
;
783 ath_tx_pause_tid(sc
, txtid
);
784 *ssn
= txtid
->seq_start
;
787 void ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
789 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
790 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
791 struct ath_txq
*txq
= &sc
->tx
.txq
[txtid
->ac
->qnum
];
792 struct ath_tx_status ts
;
794 struct list_head bf_head
;
796 memset(&ts
, 0, sizeof(ts
));
797 INIT_LIST_HEAD(&bf_head
);
799 if (txtid
->state
& AGGR_CLEANUP
)
802 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
803 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
807 ath_tx_pause_tid(sc
, txtid
);
809 /* drop all software retried frames and mark this TID */
810 spin_lock_bh(&txq
->axq_lock
);
811 while (!list_empty(&txtid
->buf_q
)) {
812 bf
= list_first_entry(&txtid
->buf_q
, struct ath_buf
, list
);
813 if (!bf_isretried(bf
)) {
815 * NB: it's based on the assumption that
816 * software retried frame will always stay
817 * at the head of software queue.
821 list_move_tail(&bf
->list
, &bf_head
);
822 ath_tx_update_baw(sc
, txtid
, bf
->bf_seqno
);
823 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0, 0);
825 spin_unlock_bh(&txq
->axq_lock
);
827 if (txtid
->baw_head
!= txtid
->baw_tail
) {
828 txtid
->state
|= AGGR_CLEANUP
;
830 txtid
->state
&= ~AGGR_ADDBA_COMPLETE
;
831 ath_tx_flush_tid(sc
, txtid
);
835 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
837 struct ath_atx_tid
*txtid
;
840 an
= (struct ath_node
*)sta
->drv_priv
;
842 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
843 txtid
= ATH_AN_2_TID(an
, tid
);
845 IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
846 txtid
->state
|= AGGR_ADDBA_COMPLETE
;
847 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
848 ath_tx_resume_tid(sc
, txtid
);
852 bool ath_tx_aggr_check(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
)
854 struct ath_atx_tid
*txtid
;
856 if (!(sc
->sc_flags
& SC_OP_TXAGGR
))
859 txtid
= ATH_AN_2_TID(an
, tidno
);
861 if (!(txtid
->state
& (AGGR_ADDBA_COMPLETE
| AGGR_ADDBA_PROGRESS
)))
866 /********************/
867 /* Queue Management */
868 /********************/
870 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
873 struct ath_atx_ac
*ac
, *ac_tmp
;
874 struct ath_atx_tid
*tid
, *tid_tmp
;
876 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
879 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
880 list_del(&tid
->list
);
882 ath_tid_drain(sc
, txq
, tid
);
887 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
889 struct ath_hw
*ah
= sc
->sc_ah
;
890 struct ath_common
*common
= ath9k_hw_common(ah
);
891 struct ath9k_tx_queue_info qi
;
894 memset(&qi
, 0, sizeof(qi
));
895 qi
.tqi_subtype
= subtype
;
896 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
897 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
898 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
899 qi
.tqi_physCompBuf
= 0;
902 * Enable interrupts only for EOL and DESC conditions.
903 * We mark tx descriptors to receive a DESC interrupt
904 * when a tx queue gets deep; otherwise waiting for the
905 * EOL to reap descriptors. Note that this is done to
906 * reduce interrupt load and this only defers reaping
907 * descriptors, never transmitting frames. Aside from
908 * reducing interrupts this also permits more concurrency.
909 * The only potential downside is if the tx queue backs
910 * up in which case the top half of the kernel may backup
911 * due to a lack of tx descriptors.
913 * The UAPSD queue is an exception, since we take a desc-
914 * based intr on the EOSP frames.
916 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
917 qi
.tqi_qflags
= TXQ_FLAG_TXOKINT_ENABLE
|
918 TXQ_FLAG_TXERRINT_ENABLE
;
920 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
921 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
923 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
924 TXQ_FLAG_TXDESCINT_ENABLE
;
926 qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
929 * NB: don't print a message, this happens
930 * normally on parts with too few tx queues
934 if (qnum
>= ARRAY_SIZE(sc
->tx
.txq
)) {
935 ath_print(common
, ATH_DBG_FATAL
,
936 "qnum %u out of range, max %u!\n",
937 qnum
, (unsigned int)ARRAY_SIZE(sc
->tx
.txq
));
938 ath9k_hw_releasetxqueue(ah
, qnum
);
941 if (!ATH_TXQ_SETUP(sc
, qnum
)) {
942 struct ath_txq
*txq
= &sc
->tx
.txq
[qnum
];
944 txq
->axq_qnum
= qnum
;
945 txq
->axq_link
= NULL
;
946 INIT_LIST_HEAD(&txq
->axq_q
);
947 INIT_LIST_HEAD(&txq
->axq_acq
);
948 spin_lock_init(&txq
->axq_lock
);
950 txq
->axq_tx_inprogress
= false;
951 sc
->tx
.txqsetup
|= 1<<qnum
;
953 txq
->txq_headidx
= txq
->txq_tailidx
= 0;
954 for (i
= 0; i
< ATH_TXFIFO_DEPTH
; i
++)
955 INIT_LIST_HEAD(&txq
->txq_fifo
[i
]);
956 INIT_LIST_HEAD(&txq
->txq_fifo_pending
);
958 return &sc
->tx
.txq
[qnum
];
961 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
)
966 case ATH9K_TX_QUEUE_DATA
:
967 if (haltype
>= ARRAY_SIZE(sc
->tx
.hwq_map
)) {
968 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
969 "HAL AC %u out of range, max %zu!\n",
970 haltype
, ARRAY_SIZE(sc
->tx
.hwq_map
));
973 qnum
= sc
->tx
.hwq_map
[haltype
];
975 case ATH9K_TX_QUEUE_BEACON
:
976 qnum
= sc
->beacon
.beaconq
;
978 case ATH9K_TX_QUEUE_CAB
:
979 qnum
= sc
->beacon
.cabq
->axq_qnum
;
987 struct ath_txq
*ath_test_get_txq(struct ath_softc
*sc
, struct sk_buff
*skb
)
989 struct ath_txq
*txq
= NULL
;
990 u16 skb_queue
= skb_get_queue_mapping(skb
);
993 qnum
= ath_get_hal_qnum(skb_queue
, sc
);
994 txq
= &sc
->tx
.txq
[qnum
];
996 spin_lock_bh(&txq
->axq_lock
);
998 if (txq
->axq_depth
>= (ATH_TXBUF
- 20)) {
999 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_XMIT
,
1000 "TX queue: %d is full, depth: %d\n",
1001 qnum
, txq
->axq_depth
);
1002 ath_mac80211_stop_queue(sc
, skb_queue
);
1004 spin_unlock_bh(&txq
->axq_lock
);
1008 spin_unlock_bh(&txq
->axq_lock
);
1013 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
1014 struct ath9k_tx_queue_info
*qinfo
)
1016 struct ath_hw
*ah
= sc
->sc_ah
;
1018 struct ath9k_tx_queue_info qi
;
1020 if (qnum
== sc
->beacon
.beaconq
) {
1022 * XXX: for beacon queue, we just save the parameter.
1023 * It will be picked up by ath_beaconq_config when
1026 sc
->beacon
.beacon_qi
= *qinfo
;
1030 BUG_ON(sc
->tx
.txq
[qnum
].axq_qnum
!= qnum
);
1032 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
1033 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
1034 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
1035 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
1036 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
1037 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
1039 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
1040 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
1041 "Unable to update hardware queue %u!\n", qnum
);
1044 ath9k_hw_resettxqueue(ah
, qnum
);
1050 int ath_cabq_update(struct ath_softc
*sc
)
1052 struct ath9k_tx_queue_info qi
;
1053 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
1055 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
1057 * Ensure the readytime % is within the bounds.
1059 if (sc
->config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
1060 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
1061 else if (sc
->config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
1062 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
1064 qi
.tqi_readyTime
= (sc
->beacon_interval
*
1065 sc
->config
.cabqReadytime
) / 100;
1066 ath_txq_update(sc
, qnum
, &qi
);
1072 * Drain a given TX queue (could be Beacon or Data)
1074 * This assumes output has been stopped and
1075 * we do not need to block ath_tx_tasklet.
1077 void ath_draintxq(struct ath_softc
*sc
, struct ath_txq
*txq
, bool retry_tx
)
1079 struct ath_buf
*bf
, *lastbf
;
1080 struct list_head bf_head
;
1081 struct ath_tx_status ts
;
1083 memset(&ts
, 0, sizeof(ts
));
1084 INIT_LIST_HEAD(&bf_head
);
1087 spin_lock_bh(&txq
->axq_lock
);
1089 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1090 if (list_empty(&txq
->txq_fifo
[txq
->txq_tailidx
])) {
1091 txq
->txq_headidx
= txq
->txq_tailidx
= 0;
1092 spin_unlock_bh(&txq
->axq_lock
);
1095 bf
= list_first_entry(&txq
->txq_fifo
[txq
->txq_tailidx
],
1096 struct ath_buf
, list
);
1099 if (list_empty(&txq
->axq_q
)) {
1100 txq
->axq_link
= NULL
;
1101 spin_unlock_bh(&txq
->axq_lock
);
1104 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
,
1108 list_del(&bf
->list
);
1109 spin_unlock_bh(&txq
->axq_lock
);
1111 ath_tx_return_buffer(sc
, bf
);
1116 lastbf
= bf
->bf_lastbf
;
1118 lastbf
->bf_tx_aborted
= true;
1120 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1121 list_cut_position(&bf_head
,
1122 &txq
->txq_fifo
[txq
->txq_tailidx
],
1124 INCR(txq
->txq_tailidx
, ATH_TXFIFO_DEPTH
);
1126 /* remove ath_buf's of the same mpdu from txq */
1127 list_cut_position(&bf_head
, &txq
->axq_q
, &lastbf
->list
);
1132 spin_unlock_bh(&txq
->axq_lock
);
1135 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, &ts
, 0);
1137 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0, 0);
1140 spin_lock_bh(&txq
->axq_lock
);
1141 txq
->axq_tx_inprogress
= false;
1142 spin_unlock_bh(&txq
->axq_lock
);
1144 /* flush any pending frames if aggregation is enabled */
1145 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
1147 spin_lock_bh(&txq
->axq_lock
);
1148 ath_txq_drain_pending_buffers(sc
, txq
);
1149 spin_unlock_bh(&txq
->axq_lock
);
1153 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1154 spin_lock_bh(&txq
->axq_lock
);
1155 while (!list_empty(&txq
->txq_fifo_pending
)) {
1156 bf
= list_first_entry(&txq
->txq_fifo_pending
,
1157 struct ath_buf
, list
);
1158 list_cut_position(&bf_head
,
1159 &txq
->txq_fifo_pending
,
1160 &bf
->bf_lastbf
->list
);
1161 spin_unlock_bh(&txq
->axq_lock
);
1164 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
,
1167 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
,
1169 spin_lock_bh(&txq
->axq_lock
);
1171 spin_unlock_bh(&txq
->axq_lock
);
1175 void ath_drain_all_txq(struct ath_softc
*sc
, bool retry_tx
)
1177 struct ath_hw
*ah
= sc
->sc_ah
;
1178 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1179 struct ath_txq
*txq
;
1182 if (sc
->sc_flags
& SC_OP_INVALID
)
1185 /* Stop beacon queue */
1186 ath9k_hw_stoptxdma(sc
->sc_ah
, sc
->beacon
.beaconq
);
1188 /* Stop data queues */
1189 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1190 if (ATH_TXQ_SETUP(sc
, i
)) {
1191 txq
= &sc
->tx
.txq
[i
];
1192 ath9k_hw_stoptxdma(ah
, txq
->axq_qnum
);
1193 npend
+= ath9k_hw_numtxpending(ah
, txq
->axq_qnum
);
1200 ath_print(common
, ATH_DBG_FATAL
,
1201 "Unable to stop TxDMA. Reset HAL!\n");
1203 spin_lock_bh(&sc
->sc_resetlock
);
1204 r
= ath9k_hw_reset(ah
, sc
->sc_ah
->curchan
, false);
1206 ath_print(common
, ATH_DBG_FATAL
,
1207 "Unable to reset hardware; reset status %d\n",
1209 spin_unlock_bh(&sc
->sc_resetlock
);
1212 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1213 if (ATH_TXQ_SETUP(sc
, i
))
1214 ath_draintxq(sc
, &sc
->tx
.txq
[i
], retry_tx
);
1218 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1220 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1221 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1224 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
1226 struct ath_atx_ac
*ac
;
1227 struct ath_atx_tid
*tid
;
1229 if (list_empty(&txq
->axq_acq
))
1232 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
1233 list_del(&ac
->list
);
1237 if (list_empty(&ac
->tid_q
))
1240 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
, list
);
1241 list_del(&tid
->list
);
1247 ath_tx_sched_aggr(sc
, txq
, tid
);
1250 * add tid to round-robin queue if more frames
1251 * are pending for the tid
1253 if (!list_empty(&tid
->buf_q
))
1254 ath_tx_queue_tid(txq
, tid
);
1257 } while (!list_empty(&ac
->tid_q
));
1259 if (!list_empty(&ac
->tid_q
)) {
1262 list_add_tail(&ac
->list
, &txq
->axq_acq
);
1267 int ath_tx_setup(struct ath_softc
*sc
, int haltype
)
1269 struct ath_txq
*txq
;
1271 if (haltype
>= ARRAY_SIZE(sc
->tx
.hwq_map
)) {
1272 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
1273 "HAL AC %u out of range, max %zu!\n",
1274 haltype
, ARRAY_SIZE(sc
->tx
.hwq_map
));
1277 txq
= ath_txq_setup(sc
, ATH9K_TX_QUEUE_DATA
, haltype
);
1279 sc
->tx
.hwq_map
[haltype
] = txq
->axq_qnum
;
1290 * Insert a chain of ath_buf (descriptors) on a txq and
1291 * assume the descriptors are already chained together by caller.
1293 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
1294 struct list_head
*head
)
1296 struct ath_hw
*ah
= sc
->sc_ah
;
1297 struct ath_common
*common
= ath9k_hw_common(ah
);
1301 * Insert the frame on the outbound list and
1302 * pass it on to the hardware.
1305 if (list_empty(head
))
1308 bf
= list_first_entry(head
, struct ath_buf
, list
);
1310 ath_print(common
, ATH_DBG_QUEUE
,
1311 "qnum: %d, txq depth: %d\n", txq
->axq_qnum
, txq
->axq_depth
);
1313 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1314 if (txq
->axq_depth
>= ATH_TXFIFO_DEPTH
) {
1315 list_splice_tail_init(head
, &txq
->txq_fifo_pending
);
1318 if (!list_empty(&txq
->txq_fifo
[txq
->txq_headidx
]))
1319 ath_print(common
, ATH_DBG_XMIT
,
1320 "Initializing tx fifo %d which "
1323 INIT_LIST_HEAD(&txq
->txq_fifo
[txq
->txq_headidx
]);
1324 list_splice_init(head
, &txq
->txq_fifo
[txq
->txq_headidx
]);
1325 INCR(txq
->txq_headidx
, ATH_TXFIFO_DEPTH
);
1326 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
1327 ath_print(common
, ATH_DBG_XMIT
,
1328 "TXDP[%u] = %llx (%p)\n",
1329 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
1331 list_splice_tail_init(head
, &txq
->axq_q
);
1333 if (txq
->axq_link
== NULL
) {
1334 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
1335 ath_print(common
, ATH_DBG_XMIT
,
1336 "TXDP[%u] = %llx (%p)\n",
1337 txq
->axq_qnum
, ito64(bf
->bf_daddr
),
1340 *txq
->axq_link
= bf
->bf_daddr
;
1341 ath_print(common
, ATH_DBG_XMIT
,
1342 "link[%u] (%p)=%llx (%p)\n",
1343 txq
->axq_qnum
, txq
->axq_link
,
1344 ito64(bf
->bf_daddr
), bf
->bf_desc
);
1346 ath9k_hw_get_desc_link(ah
, bf
->bf_lastbf
->bf_desc
,
1348 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
1353 static void ath_tx_send_ampdu(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
1354 struct list_head
*bf_head
,
1355 struct ath_tx_control
*txctl
)
1359 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1360 bf
->bf_state
.bf_type
|= BUF_AMPDU
;
1361 TX_STAT_INC(txctl
->txq
->axq_qnum
, a_queued
);
1364 * Do not queue to h/w when any of the following conditions is true:
1365 * - there are pending frames in software queue
1366 * - the TID is currently paused for ADDBA/BAR request
1367 * - seqno is not within block-ack window
1368 * - h/w queue depth exceeds low water mark
1370 if (!list_empty(&tid
->buf_q
) || tid
->paused
||
1371 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bf
->bf_seqno
) ||
1372 txctl
->txq
->axq_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1374 * Add this frame to software queue for scheduling later
1377 list_move_tail(&bf
->list
, &tid
->buf_q
);
1378 ath_tx_queue_tid(txctl
->txq
, tid
);
1382 /* Add sub-frame to BAW */
1383 ath_tx_addto_baw(sc
, tid
, bf
);
1385 /* Queue to h/w without aggregation */
1388 ath_buf_set_rate(sc
, bf
);
1389 ath_tx_txqaddbuf(sc
, txctl
->txq
, bf_head
);
1392 static void ath_tx_send_ht_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1393 struct ath_atx_tid
*tid
,
1394 struct list_head
*bf_head
)
1398 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1399 bf
->bf_state
.bf_type
&= ~BUF_AMPDU
;
1401 /* update starting sequence number for subsequent ADDBA request */
1402 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
1406 ath_buf_set_rate(sc
, bf
);
1407 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
1408 TX_STAT_INC(txq
->axq_qnum
, queued
);
1411 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1412 struct list_head
*bf_head
)
1416 bf
= list_first_entry(bf_head
, struct ath_buf
, list
);
1420 ath_buf_set_rate(sc
, bf
);
1421 ath_tx_txqaddbuf(sc
, txq
, bf_head
);
1422 TX_STAT_INC(txq
->axq_qnum
, queued
);
1425 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1427 struct ieee80211_hdr
*hdr
;
1428 enum ath9k_pkt_type htype
;
1431 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1432 fc
= hdr
->frame_control
;
1434 if (ieee80211_is_beacon(fc
))
1435 htype
= ATH9K_PKT_TYPE_BEACON
;
1436 else if (ieee80211_is_probe_resp(fc
))
1437 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
1438 else if (ieee80211_is_atim(fc
))
1439 htype
= ATH9K_PKT_TYPE_ATIM
;
1440 else if (ieee80211_is_pspoll(fc
))
1441 htype
= ATH9K_PKT_TYPE_PSPOLL
;
1443 htype
= ATH9K_PKT_TYPE_NORMAL
;
1448 static int get_hw_crypto_keytype(struct sk_buff
*skb
)
1450 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1452 if (tx_info
->control
.hw_key
) {
1453 if (tx_info
->control
.hw_key
->alg
== ALG_WEP
)
1454 return ATH9K_KEY_TYPE_WEP
;
1455 else if (tx_info
->control
.hw_key
->alg
== ALG_TKIP
)
1456 return ATH9K_KEY_TYPE_TKIP
;
1457 else if (tx_info
->control
.hw_key
->alg
== ALG_CCMP
)
1458 return ATH9K_KEY_TYPE_AES
;
1461 return ATH9K_KEY_TYPE_CLEAR
;
1464 static void assign_aggr_tid_seqno(struct sk_buff
*skb
,
1467 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1468 struct ieee80211_hdr
*hdr
;
1469 struct ath_node
*an
;
1470 struct ath_atx_tid
*tid
;
1474 if (!tx_info
->control
.sta
)
1477 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1478 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1479 fc
= hdr
->frame_control
;
1481 if (ieee80211_is_data_qos(fc
)) {
1482 qc
= ieee80211_get_qos_ctl(hdr
);
1483 bf
->bf_tidno
= qc
[0] & 0xf;
1487 * For HT capable stations, we save tidno for later use.
1488 * We also override seqno set by upper layer with the one
1489 * in tx aggregation state.
1491 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1492 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<< IEEE80211_SEQ_SEQ_SHIFT
);
1493 bf
->bf_seqno
= tid
->seq_next
;
1494 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
1497 static int setup_tx_flags(struct sk_buff
*skb
, bool use_ldpc
)
1499 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1502 flags
|= ATH9K_TXDESC_CLRDMASK
; /* needed for crypto errors */
1503 flags
|= ATH9K_TXDESC_INTREQ
;
1505 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1506 flags
|= ATH9K_TXDESC_NOACK
;
1509 flags
|= ATH9K_TXDESC_LDPC
;
1516 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1517 * width - 0 for 20 MHz, 1 for 40 MHz
1518 * half_gi - to use 4us v/s 3.6 us for symbol time
1520 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, struct ath_buf
*bf
,
1521 int width
, int half_gi
, bool shortPreamble
)
1523 u32 nbits
, nsymbits
, duration
, nsymbols
;
1524 int streams
, pktlen
;
1526 pktlen
= bf_isaggr(bf
) ? bf
->bf_al
: bf
->bf_frmlen
;
1528 /* find number of symbols: PLCP + data */
1529 streams
= HT_RC_2_STREAMS(rix
);
1530 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
1531 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
1532 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
1535 duration
= SYMBOL_TIME(nsymbols
);
1537 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
1539 /* addup duration for legacy/ht training and signal fields */
1540 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
1545 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
)
1547 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1548 struct ath9k_11n_rate_series series
[4];
1549 struct sk_buff
*skb
;
1550 struct ieee80211_tx_info
*tx_info
;
1551 struct ieee80211_tx_rate
*rates
;
1552 const struct ieee80211_rate
*rate
;
1553 struct ieee80211_hdr
*hdr
;
1555 u8 rix
= 0, ctsrate
= 0;
1558 memset(series
, 0, sizeof(struct ath9k_11n_rate_series
) * 4);
1561 tx_info
= IEEE80211_SKB_CB(skb
);
1562 rates
= tx_info
->control
.rates
;
1563 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1564 is_pspoll
= ieee80211_is_pspoll(hdr
->frame_control
);
1567 * We check if Short Preamble is needed for the CTS rate by
1568 * checking the BSS's global flag.
1569 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1571 rate
= ieee80211_get_rts_cts_rate(sc
->hw
, tx_info
);
1572 ctsrate
= rate
->hw_value
;
1573 if (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
)
1574 ctsrate
|= rate
->hw_value_short
;
1576 for (i
= 0; i
< 4; i
++) {
1577 bool is_40
, is_sgi
, is_sp
;
1580 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
1584 series
[i
].Tries
= rates
[i
].count
;
1585 series
[i
].ChSel
= common
->tx_chainmask
;
1587 if ((sc
->config
.ath_aggr_prot
&& bf_isaggr(bf
)) ||
1588 (rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)) {
1589 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1590 flags
|= ATH9K_TXDESC_RTSENA
;
1591 } else if (rates
[i
].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1592 series
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1593 flags
|= ATH9K_TXDESC_CTSENA
;
1596 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
1597 series
[i
].RateFlags
|= ATH9K_RATESERIES_2040
;
1598 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
1599 series
[i
].RateFlags
|= ATH9K_RATESERIES_HALFGI
;
1601 is_sgi
= !!(rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
);
1602 is_40
= !!(rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
);
1603 is_sp
= !!(rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
);
1605 if (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) {
1607 series
[i
].Rate
= rix
| 0x80;
1608 series
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, bf
,
1609 is_40
, is_sgi
, is_sp
);
1610 if (rix
< 8 && (tx_info
->flags
& IEEE80211_TX_CTL_STBC
))
1611 series
[i
].RateFlags
|= ATH9K_RATESERIES_STBC
;
1616 if ((tx_info
->band
== IEEE80211_BAND_2GHZ
) &&
1617 !(rate
->flags
& IEEE80211_RATE_ERP_G
))
1618 phy
= WLAN_RC_PHY_CCK
;
1620 phy
= WLAN_RC_PHY_OFDM
;
1622 rate
= &sc
->sbands
[tx_info
->band
].bitrates
[rates
[i
].idx
];
1623 series
[i
].Rate
= rate
->hw_value
;
1624 if (rate
->hw_value_short
) {
1625 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
1626 series
[i
].Rate
|= rate
->hw_value_short
;
1631 series
[i
].PktDuration
= ath9k_hw_computetxtime(sc
->sc_ah
,
1632 phy
, rate
->bitrate
* 100, bf
->bf_frmlen
, rix
, is_sp
);
1635 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1636 if (bf_isaggr(bf
) && (bf
->bf_al
> sc
->sc_ah
->caps
.rts_aggr_limit
))
1637 flags
&= ~ATH9K_TXDESC_RTSENA
;
1639 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1640 if (flags
& ATH9K_TXDESC_RTSENA
)
1641 flags
&= ~ATH9K_TXDESC_CTSENA
;
1643 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1644 ath9k_hw_set11n_ratescenario(sc
->sc_ah
, bf
->bf_desc
,
1645 bf
->bf_lastbf
->bf_desc
,
1646 !is_pspoll
, ctsrate
,
1647 0, series
, 4, flags
);
1649 if (sc
->config
.ath_aggr_prot
&& flags
)
1650 ath9k_hw_set11n_burstduration(sc
->sc_ah
, bf
->bf_desc
, 8192);
1653 static int ath_tx_setup_buffer(struct ieee80211_hw
*hw
, struct ath_buf
*bf
,
1654 struct sk_buff
*skb
,
1655 struct ath_tx_control
*txctl
)
1657 struct ath_wiphy
*aphy
= hw
->priv
;
1658 struct ath_softc
*sc
= aphy
->sc
;
1659 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1660 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1663 int padpos
, padsize
;
1664 bool use_ldpc
= false;
1666 tx_info
->pad
[0] = 0;
1667 switch (txctl
->frame_type
) {
1668 case ATH9K_IFT_NOT_INTERNAL
:
1670 case ATH9K_IFT_PAUSE
:
1671 tx_info
->pad
[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE
;
1673 case ATH9K_IFT_UNPAUSE
:
1674 tx_info
->pad
[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL
;
1677 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1678 fc
= hdr
->frame_control
;
1680 ATH_TXBUF_RESET(bf
);
1683 bf
->bf_frmlen
= skb
->len
+ FCS_LEN
;
1684 /* Remove the padding size from bf_frmlen, if any */
1685 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1686 padsize
= padpos
& 3;
1687 if (padsize
&& skb
->len
>padpos
+padsize
) {
1688 bf
->bf_frmlen
-= padsize
;
1691 if (conf_is_ht(&hw
->conf
)) {
1692 bf
->bf_state
.bf_type
|= BUF_HT
;
1693 if (tx_info
->flags
& IEEE80211_TX_CTL_LDPC
)
1697 bf
->bf_flags
= setup_tx_flags(skb
, use_ldpc
);
1699 bf
->bf_keytype
= get_hw_crypto_keytype(skb
);
1700 if (bf
->bf_keytype
!= ATH9K_KEY_TYPE_CLEAR
) {
1701 bf
->bf_frmlen
+= tx_info
->control
.hw_key
->icv_len
;
1702 bf
->bf_keyix
= tx_info
->control
.hw_key
->hw_key_idx
;
1704 bf
->bf_keyix
= ATH9K_TXKEYIX_INVALID
;
1707 if (ieee80211_is_data_qos(fc
) && bf_isht(bf
) &&
1708 (sc
->sc_flags
& SC_OP_TXAGGR
))
1709 assign_aggr_tid_seqno(skb
, bf
);
1713 bf
->bf_dmacontext
= dma_map_single(sc
->dev
, skb
->data
,
1714 skb
->len
, DMA_TO_DEVICE
);
1715 if (unlikely(dma_mapping_error(sc
->dev
, bf
->bf_dmacontext
))) {
1717 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_FATAL
,
1718 "dma_mapping_error() on TX\n");
1722 bf
->bf_buf_addr
= bf
->bf_dmacontext
;
1724 /* tag if this is a nullfunc frame to enable PS when AP acks it */
1725 if (ieee80211_is_nullfunc(fc
) && ieee80211_has_pm(fc
)) {
1726 bf
->bf_isnullfunc
= true;
1727 sc
->ps_flags
&= ~PS_NULLFUNC_COMPLETED
;
1729 bf
->bf_isnullfunc
= false;
1734 /* FIXME: tx power */
1735 static void ath_tx_start_dma(struct ath_softc
*sc
, struct ath_buf
*bf
,
1736 struct ath_tx_control
*txctl
)
1738 struct sk_buff
*skb
= bf
->bf_mpdu
;
1739 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1740 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1741 struct ath_node
*an
= NULL
;
1742 struct list_head bf_head
;
1743 struct ath_desc
*ds
;
1744 struct ath_atx_tid
*tid
;
1745 struct ath_hw
*ah
= sc
->sc_ah
;
1749 frm_type
= get_hw_packet_type(skb
);
1750 fc
= hdr
->frame_control
;
1752 INIT_LIST_HEAD(&bf_head
);
1753 list_add_tail(&bf
->list
, &bf_head
);
1756 ath9k_hw_set_desc_link(ah
, ds
, 0);
1758 ath9k_hw_set11n_txdesc(ah
, ds
, bf
->bf_frmlen
, frm_type
, MAX_RATE_POWER
,
1759 bf
->bf_keyix
, bf
->bf_keytype
, bf
->bf_flags
);
1761 ath9k_hw_filltxdesc(ah
, ds
,
1762 skb
->len
, /* segment length */
1763 true, /* first segment */
1764 true, /* last segment */
1765 ds
, /* first descriptor */
1767 txctl
->txq
->axq_qnum
);
1769 spin_lock_bh(&txctl
->txq
->axq_lock
);
1771 if (bf_isht(bf
) && (sc
->sc_flags
& SC_OP_TXAGGR
) &&
1772 tx_info
->control
.sta
) {
1773 an
= (struct ath_node
*)tx_info
->control
.sta
->drv_priv
;
1774 tid
= ATH_AN_2_TID(an
, bf
->bf_tidno
);
1776 if (!ieee80211_is_data_qos(fc
)) {
1777 ath_tx_send_normal(sc
, txctl
->txq
, &bf_head
);
1781 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
1783 * Try aggregation if it's a unicast data frame
1784 * and the destination is HT capable.
1786 ath_tx_send_ampdu(sc
, tid
, &bf_head
, txctl
);
1789 * Send this frame as regular when ADDBA
1790 * exchange is neither complete nor pending.
1792 ath_tx_send_ht_normal(sc
, txctl
->txq
,
1796 ath_tx_send_normal(sc
, txctl
->txq
, &bf_head
);
1800 spin_unlock_bh(&txctl
->txq
->axq_lock
);
1803 /* Upon failure caller should free skb */
1804 int ath_tx_start(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1805 struct ath_tx_control
*txctl
)
1807 struct ath_wiphy
*aphy
= hw
->priv
;
1808 struct ath_softc
*sc
= aphy
->sc
;
1809 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1813 bf
= ath_tx_get_buffer(sc
);
1815 ath_print(common
, ATH_DBG_XMIT
, "TX buffers are full\n");
1819 r
= ath_tx_setup_buffer(hw
, bf
, skb
, txctl
);
1821 struct ath_txq
*txq
= txctl
->txq
;
1823 ath_print(common
, ATH_DBG_FATAL
, "TX mem alloc failure\n");
1825 /* upon ath_tx_processq() this TX queue will be resumed, we
1826 * guarantee this will happen by knowing beforehand that
1827 * we will at least have to run TX completionon one buffer
1829 spin_lock_bh(&txq
->axq_lock
);
1830 if (sc
->tx
.txq
[txq
->axq_qnum
].axq_depth
> 1) {
1831 ath_mac80211_stop_queue(sc
, skb_get_queue_mapping(skb
));
1834 spin_unlock_bh(&txq
->axq_lock
);
1836 ath_tx_return_buffer(sc
, bf
);
1841 ath_tx_start_dma(sc
, bf
, txctl
);
1846 void ath_tx_cabq(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
1848 struct ath_wiphy
*aphy
= hw
->priv
;
1849 struct ath_softc
*sc
= aphy
->sc
;
1850 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1851 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
1852 int padpos
, padsize
;
1853 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1854 struct ath_tx_control txctl
;
1856 memset(&txctl
, 0, sizeof(struct ath_tx_control
));
1859 * As a temporary workaround, assign seq# here; this will likely need
1860 * to be cleaned up to work better with Beacon transmission and virtual
1863 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
1864 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
1865 sc
->tx
.seq_no
+= 0x10;
1866 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
1867 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
1870 /* Add the padding after the header if this is not already done */
1871 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1872 padsize
= padpos
& 3;
1873 if (padsize
&& skb
->len
>padpos
) {
1874 if (skb_headroom(skb
) < padsize
) {
1875 ath_print(common
, ATH_DBG_XMIT
,
1876 "TX CABQ padding failed\n");
1877 dev_kfree_skb_any(skb
);
1880 skb_push(skb
, padsize
);
1881 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
1884 txctl
.txq
= sc
->beacon
.cabq
;
1886 ath_print(common
, ATH_DBG_XMIT
,
1887 "transmitting CABQ packet, skb: %p\n", skb
);
1889 if (ath_tx_start(hw
, skb
, &txctl
) != 0) {
1890 ath_print(common
, ATH_DBG_XMIT
, "CABQ TX failed\n");
1896 dev_kfree_skb_any(skb
);
1903 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
1904 struct ath_wiphy
*aphy
, int tx_flags
)
1906 struct ieee80211_hw
*hw
= sc
->hw
;
1907 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1908 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1909 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
1910 int padpos
, padsize
;
1912 ath_print(common
, ATH_DBG_XMIT
, "TX complete: skb: %p\n", skb
);
1917 if (tx_flags
& ATH_TX_BAR
)
1918 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
1920 if (!(tx_flags
& (ATH_TX_ERROR
| ATH_TX_XRETRY
))) {
1921 /* Frame was ACKed */
1922 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
1925 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1926 padsize
= padpos
& 3;
1927 if (padsize
&& skb
->len
>padpos
+padsize
) {
1929 * Remove MAC header padding before giving the frame back to
1932 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1933 skb_pull(skb
, padsize
);
1936 if (sc
->ps_flags
& PS_WAIT_FOR_TX_ACK
) {
1937 sc
->ps_flags
&= ~PS_WAIT_FOR_TX_ACK
;
1938 ath_print(common
, ATH_DBG_PS
,
1939 "Going back to sleep after having "
1940 "received TX status (0x%lx)\n",
1941 sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
1943 PS_WAIT_FOR_PSPOLL_DATA
|
1944 PS_WAIT_FOR_TX_ACK
));
1947 if (unlikely(tx_info
->pad
[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL
))
1948 ath9k_tx_status(hw
, skb
);
1950 ieee80211_tx_status(hw
, skb
);
1953 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
1954 struct ath_txq
*txq
, struct list_head
*bf_q
,
1955 struct ath_tx_status
*ts
, int txok
, int sendbar
)
1957 struct sk_buff
*skb
= bf
->bf_mpdu
;
1958 unsigned long flags
;
1962 tx_flags
= ATH_TX_BAR
;
1965 tx_flags
|= ATH_TX_ERROR
;
1967 if (bf_isxretried(bf
))
1968 tx_flags
|= ATH_TX_XRETRY
;
1971 dma_unmap_single(sc
->dev
, bf
->bf_dmacontext
, skb
->len
, DMA_TO_DEVICE
);
1972 ath_tx_complete(sc
, skb
, bf
->aphy
, tx_flags
);
1973 ath_debug_stat_tx(sc
, txq
, bf
, ts
);
1976 * Return the list of ath_buf of this mpdu to free queue
1978 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
1979 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
1980 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
1983 static int ath_tx_num_badfrms(struct ath_softc
*sc
, struct ath_buf
*bf
,
1984 struct ath_tx_status
*ts
, int txok
)
1987 u32 ba
[WME_BA_BMP_SIZE
>> 5];
1992 if (bf
->bf_tx_aborted
)
1995 isaggr
= bf_isaggr(bf
);
1997 seq_st
= ts
->ts_seqnum
;
1998 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
2002 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_seqno
);
2003 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
2012 static void ath_tx_rc_status(struct ath_buf
*bf
, struct ath_tx_status
*ts
,
2013 int nbad
, int txok
, bool update_rc
)
2015 struct sk_buff
*skb
= bf
->bf_mpdu
;
2016 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2017 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2018 struct ieee80211_hw
*hw
= bf
->aphy
->hw
;
2022 tx_info
->status
.ack_signal
= ts
->ts_rssi
;
2024 tx_rateindex
= ts
->ts_rateindex
;
2025 WARN_ON(tx_rateindex
>= hw
->max_rates
);
2027 if (ts
->ts_status
& ATH9K_TXERR_FILT
)
2028 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
2029 if ((tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) && update_rc
)
2030 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
2032 if ((ts
->ts_status
& ATH9K_TXERR_FILT
) == 0 &&
2033 (bf
->bf_flags
& ATH9K_TXDESC_NOACK
) == 0 && update_rc
) {
2034 if (ieee80211_is_data(hdr
->frame_control
)) {
2036 (ATH9K_TX_DATA_UNDERRUN
| ATH9K_TX_DELIM_UNDERRUN
))
2037 tx_info
->pad
[0] |= ATH_TX_INFO_UNDERRUN
;
2038 if ((ts
->ts_status
& ATH9K_TXERR_XRETRY
) ||
2039 (ts
->ts_status
& ATH9K_TXERR_FIFO
))
2040 tx_info
->pad
[0] |= ATH_TX_INFO_XRETRY
;
2041 tx_info
->status
.ampdu_len
= bf
->bf_nframes
;
2042 tx_info
->status
.ampdu_ack_len
= bf
->bf_nframes
- nbad
;
2046 for (i
= tx_rateindex
+ 1; i
< hw
->max_rates
; i
++) {
2047 tx_info
->status
.rates
[i
].count
= 0;
2048 tx_info
->status
.rates
[i
].idx
= -1;
2051 tx_info
->status
.rates
[tx_rateindex
].count
= bf
->bf_retries
+ 1;
2054 static void ath_wake_mac80211_queue(struct ath_softc
*sc
, struct ath_txq
*txq
)
2058 spin_lock_bh(&txq
->axq_lock
);
2060 sc
->tx
.txq
[txq
->axq_qnum
].axq_depth
<= (ATH_TXBUF
- 20)) {
2061 qnum
= ath_get_mac80211_qnum(txq
->axq_qnum
, sc
);
2063 ath_mac80211_start_queue(sc
, qnum
);
2067 spin_unlock_bh(&txq
->axq_lock
);
2070 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2072 struct ath_hw
*ah
= sc
->sc_ah
;
2073 struct ath_common
*common
= ath9k_hw_common(ah
);
2074 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
2075 struct list_head bf_head
;
2076 struct ath_desc
*ds
;
2077 struct ath_tx_status ts
;
2081 ath_print(common
, ATH_DBG_QUEUE
, "tx queue %d (%x), link %p\n",
2082 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
2086 spin_lock_bh(&txq
->axq_lock
);
2087 if (list_empty(&txq
->axq_q
)) {
2088 txq
->axq_link
= NULL
;
2089 spin_unlock_bh(&txq
->axq_lock
);
2092 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2095 * There is a race condition that a BH gets scheduled
2096 * after sw writes TxE and before hw re-load the last
2097 * descriptor to get the newly chained one.
2098 * Software must keep the last DONE descriptor as a
2099 * holding descriptor - software does so by marking
2100 * it with the STALE flag.
2105 if (list_is_last(&bf_held
->list
, &txq
->axq_q
)) {
2106 spin_unlock_bh(&txq
->axq_lock
);
2109 bf
= list_entry(bf_held
->list
.next
,
2110 struct ath_buf
, list
);
2114 lastbf
= bf
->bf_lastbf
;
2115 ds
= lastbf
->bf_desc
;
2117 memset(&ts
, 0, sizeof(ts
));
2118 status
= ath9k_hw_txprocdesc(ah
, ds
, &ts
);
2119 if (status
== -EINPROGRESS
) {
2120 spin_unlock_bh(&txq
->axq_lock
);
2125 * We now know the nullfunc frame has been ACKed so we
2128 if (bf
->bf_isnullfunc
&&
2129 (ts
.ts_status
& ATH9K_TX_ACKED
)) {
2130 if ((sc
->ps_flags
& PS_ENABLED
))
2131 ath9k_enable_ps(sc
);
2133 sc
->ps_flags
|= PS_NULLFUNC_COMPLETED
;
2137 * Remove ath_buf's of the same transmit unit from txq,
2138 * however leave the last descriptor back as the holding
2139 * descriptor for hw.
2141 lastbf
->bf_stale
= true;
2142 INIT_LIST_HEAD(&bf_head
);
2143 if (!list_is_singular(&lastbf
->list
))
2144 list_cut_position(&bf_head
,
2145 &txq
->axq_q
, lastbf
->list
.prev
);
2148 txok
= !(ts
.ts_status
& ATH9K_TXERR_MASK
);
2149 txq
->axq_tx_inprogress
= false;
2151 list_del(&bf_held
->list
);
2152 spin_unlock_bh(&txq
->axq_lock
);
2155 ath_tx_return_buffer(sc
, bf_held
);
2157 if (!bf_isampdu(bf
)) {
2159 * This frame is sent out as a single frame.
2160 * Use hardware retry status for this frame.
2162 bf
->bf_retries
= ts
.ts_longretry
;
2163 if (ts
.ts_status
& ATH9K_TXERR_XRETRY
)
2164 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
2165 ath_tx_rc_status(bf
, &ts
, 0, txok
, true);
2169 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, &ts
, txok
);
2171 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, txok
, 0);
2173 ath_wake_mac80211_queue(sc
, txq
);
2175 spin_lock_bh(&txq
->axq_lock
);
2176 if (sc
->sc_flags
& SC_OP_TXAGGR
)
2177 ath_txq_schedule(sc
, txq
);
2178 spin_unlock_bh(&txq
->axq_lock
);
2182 static void ath_tx_complete_poll_work(struct work_struct
*work
)
2184 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
2185 tx_complete_work
.work
);
2186 struct ath_txq
*txq
;
2188 bool needreset
= false;
2190 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
2191 if (ATH_TXQ_SETUP(sc
, i
)) {
2192 txq
= &sc
->tx
.txq
[i
];
2193 spin_lock_bh(&txq
->axq_lock
);
2194 if (txq
->axq_depth
) {
2195 if (txq
->axq_tx_inprogress
) {
2197 spin_unlock_bh(&txq
->axq_lock
);
2200 txq
->axq_tx_inprogress
= true;
2203 spin_unlock_bh(&txq
->axq_lock
);
2207 ath_print(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_RESET
,
2208 "tx hung, resetting the chip\n");
2209 ath9k_ps_wakeup(sc
);
2210 ath_reset(sc
, false);
2211 ath9k_ps_restore(sc
);
2214 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
,
2215 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT
));
2220 void ath_tx_tasklet(struct ath_softc
*sc
)
2223 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2225 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2227 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2228 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2229 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2233 void ath_tx_edma_tasklet(struct ath_softc
*sc
)
2235 struct ath_tx_status txs
;
2236 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2237 struct ath_hw
*ah
= sc
->sc_ah
;
2238 struct ath_txq
*txq
;
2239 struct ath_buf
*bf
, *lastbf
;
2240 struct list_head bf_head
;
2245 status
= ath9k_hw_txprocdesc(ah
, NULL
, (void *)&txs
);
2246 if (status
== -EINPROGRESS
)
2248 if (status
== -EIO
) {
2249 ath_print(common
, ATH_DBG_XMIT
,
2250 "Error processing tx status\n");
2254 /* Skip beacon completions */
2255 if (txs
.qid
== sc
->beacon
.beaconq
)
2258 txq
= &sc
->tx
.txq
[txs
.qid
];
2260 spin_lock_bh(&txq
->axq_lock
);
2261 if (list_empty(&txq
->txq_fifo
[txq
->txq_tailidx
])) {
2262 spin_unlock_bh(&txq
->axq_lock
);
2266 bf
= list_first_entry(&txq
->txq_fifo
[txq
->txq_tailidx
],
2267 struct ath_buf
, list
);
2268 lastbf
= bf
->bf_lastbf
;
2270 INIT_LIST_HEAD(&bf_head
);
2271 list_cut_position(&bf_head
, &txq
->txq_fifo
[txq
->txq_tailidx
],
2273 INCR(txq
->txq_tailidx
, ATH_TXFIFO_DEPTH
);
2275 txq
->axq_tx_inprogress
= false;
2276 spin_unlock_bh(&txq
->axq_lock
);
2278 txok
= !(txs
.ts_status
& ATH9K_TXERR_MASK
);
2280 if (!bf_isampdu(bf
)) {
2281 bf
->bf_retries
= txs
.ts_longretry
;
2282 if (txs
.ts_status
& ATH9K_TXERR_XRETRY
)
2283 bf
->bf_state
.bf_type
|= BUF_XRETRY
;
2284 ath_tx_rc_status(bf
, &txs
, 0, txok
, true);
2288 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, &txs
, txok
);
2290 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
,
2293 ath_wake_mac80211_queue(sc
, txq
);
2295 spin_lock_bh(&txq
->axq_lock
);
2296 if (!list_empty(&txq
->txq_fifo_pending
)) {
2297 INIT_LIST_HEAD(&bf_head
);
2298 bf
= list_first_entry(&txq
->txq_fifo_pending
,
2299 struct ath_buf
, list
);
2300 list_cut_position(&bf_head
, &txq
->txq_fifo_pending
,
2301 &bf
->bf_lastbf
->list
);
2302 ath_tx_txqaddbuf(sc
, txq
, &bf_head
);
2303 } else if (sc
->sc_flags
& SC_OP_TXAGGR
)
2304 ath_txq_schedule(sc
, txq
);
2305 spin_unlock_bh(&txq
->axq_lock
);
2313 static int ath_txstatus_setup(struct ath_softc
*sc
, int size
)
2315 struct ath_descdma
*dd
= &sc
->txsdma
;
2316 u8 txs_len
= sc
->sc_ah
->caps
.txs_len
;
2318 dd
->dd_desc_len
= size
* txs_len
;
2319 dd
->dd_desc
= dma_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
2320 &dd
->dd_desc_paddr
, GFP_KERNEL
);
2327 static int ath_tx_edma_init(struct ath_softc
*sc
)
2331 err
= ath_txstatus_setup(sc
, ATH_TXSTATUS_RING_SIZE
);
2333 ath9k_hw_setup_statusring(sc
->sc_ah
, sc
->txsdma
.dd_desc
,
2334 sc
->txsdma
.dd_desc_paddr
,
2335 ATH_TXSTATUS_RING_SIZE
);
2340 static void ath_tx_edma_cleanup(struct ath_softc
*sc
)
2342 struct ath_descdma
*dd
= &sc
->txsdma
;
2344 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
2348 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2350 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2353 spin_lock_init(&sc
->tx
.txbuflock
);
2355 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
2358 ath_print(common
, ATH_DBG_FATAL
,
2359 "Failed to allocate tx descriptors: %d\n", error
);
2363 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
2364 "beacon", ATH_BCBUF
, 1, 1);
2366 ath_print(common
, ATH_DBG_FATAL
,
2367 "Failed to allocate beacon descriptors: %d\n", error
);
2371 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath_tx_complete_poll_work
);
2373 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
2374 error
= ath_tx_edma_init(sc
);
2386 void ath_tx_cleanup(struct ath_softc
*sc
)
2388 if (sc
->beacon
.bdma
.dd_desc_len
!= 0)
2389 ath_descdma_cleanup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
);
2391 if (sc
->tx
.txdma
.dd_desc_len
!= 0)
2392 ath_descdma_cleanup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
);
2394 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
2395 ath_tx_edma_cleanup(sc
);
2398 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2400 struct ath_atx_tid
*tid
;
2401 struct ath_atx_ac
*ac
;
2404 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2405 tidno
< WME_NUM_TID
;
2409 tid
->seq_start
= tid
->seq_next
= 0;
2410 tid
->baw_size
= WME_MAX_BA
;
2411 tid
->baw_head
= tid
->baw_tail
= 0;
2413 tid
->paused
= false;
2414 tid
->state
&= ~AGGR_CLEANUP
;
2415 INIT_LIST_HEAD(&tid
->buf_q
);
2416 acno
= TID_TO_WME_AC(tidno
);
2417 tid
->ac
= &an
->ac
[acno
];
2418 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2419 tid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2422 for (acno
= 0, ac
= &an
->ac
[acno
];
2423 acno
< WME_NUM_AC
; acno
++, ac
++) {
2425 INIT_LIST_HEAD(&ac
->tid_q
);
2429 ac
->qnum
= ath_tx_get_qnum(sc
,
2430 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BE
);
2433 ac
->qnum
= ath_tx_get_qnum(sc
,
2434 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_BK
);
2437 ac
->qnum
= ath_tx_get_qnum(sc
,
2438 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VI
);
2441 ac
->qnum
= ath_tx_get_qnum(sc
,
2442 ATH9K_TX_QUEUE_DATA
, ATH9K_WME_AC_VO
);
2448 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2451 struct ath_atx_ac
*ac
, *ac_tmp
;
2452 struct ath_atx_tid
*tid
, *tid_tmp
;
2453 struct ath_txq
*txq
;
2455 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2456 if (ATH_TXQ_SETUP(sc
, i
)) {
2457 txq
= &sc
->tx
.txq
[i
];
2459 spin_lock_bh(&txq
->axq_lock
);
2461 list_for_each_entry_safe(ac
,
2462 ac_tmp
, &txq
->axq_acq
, list
) {
2463 tid
= list_first_entry(&ac
->tid_q
,
2464 struct ath_atx_tid
, list
);
2465 if (tid
&& tid
->an
!= an
)
2467 list_del(&ac
->list
);
2470 list_for_each_entry_safe(tid
,
2471 tid_tmp
, &ac
->tid_q
, list
) {
2472 list_del(&tid
->list
);
2474 ath_tid_drain(sc
, txq
, tid
);
2475 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2476 tid
->state
&= ~AGGR_CLEANUP
;
2480 spin_unlock_bh(&txq
->axq_lock
);