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[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34 #define OFDM_SIFS_TIME 16
35
36 static u32 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
54 };
55
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
57
58 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct list_head *bf_q,
63 int txok, int sendbar);
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head);
66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
67 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
68 int txok);
69 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
70 int nbad, int txok, bool update_rc);
71
72 /*********************/
73 /* Aggregation logic */
74 /*********************/
75
76 static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno)
77 {
78 struct ath_atx_tid *tid;
79 tid = ATH_AN_2_TID(an, tidno);
80
81 if (tid->state & AGGR_ADDBA_COMPLETE ||
82 tid->state & AGGR_ADDBA_PROGRESS)
83 return 1;
84 else
85 return 0;
86 }
87
88 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
89 {
90 struct ath_atx_ac *ac = tid->ac;
91
92 if (tid->paused)
93 return;
94
95 if (tid->sched)
96 return;
97
98 tid->sched = true;
99 list_add_tail(&tid->list, &ac->tid_q);
100
101 if (ac->sched)
102 return;
103
104 ac->sched = true;
105 list_add_tail(&ac->list, &txq->axq_acq);
106 }
107
108 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
109 {
110 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
111
112 spin_lock_bh(&txq->axq_lock);
113 tid->paused++;
114 spin_unlock_bh(&txq->axq_lock);
115 }
116
117 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
118 {
119 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
120
121 ASSERT(tid->paused > 0);
122 spin_lock_bh(&txq->axq_lock);
123
124 tid->paused--;
125
126 if (tid->paused > 0)
127 goto unlock;
128
129 if (list_empty(&tid->buf_q))
130 goto unlock;
131
132 ath_tx_queue_tid(txq, tid);
133 ath_txq_schedule(sc, txq);
134 unlock:
135 spin_unlock_bh(&txq->axq_lock);
136 }
137
138 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
139 {
140 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
141 struct ath_buf *bf;
142 struct list_head bf_head;
143 INIT_LIST_HEAD(&bf_head);
144
145 ASSERT(tid->paused > 0);
146 spin_lock_bh(&txq->axq_lock);
147
148 tid->paused--;
149
150 if (tid->paused > 0) {
151 spin_unlock_bh(&txq->axq_lock);
152 return;
153 }
154
155 while (!list_empty(&tid->buf_q)) {
156 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
157 ASSERT(!bf_isretried(bf));
158 list_move_tail(&bf->list, &bf_head);
159 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
160 }
161
162 spin_unlock_bh(&txq->axq_lock);
163 }
164
165 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
166 int seqno)
167 {
168 int index, cindex;
169
170 index = ATH_BA_INDEX(tid->seq_start, seqno);
171 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
172
173 tid->tx_buf[cindex] = NULL;
174
175 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
176 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
177 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
178 }
179 }
180
181 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
182 struct ath_buf *bf)
183 {
184 int index, cindex;
185
186 if (bf_isretried(bf))
187 return;
188
189 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
190 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
191
192 ASSERT(tid->tx_buf[cindex] == NULL);
193 tid->tx_buf[cindex] = bf;
194
195 if (index >= ((tid->baw_tail - tid->baw_head) &
196 (ATH_TID_MAX_BUFS - 1))) {
197 tid->baw_tail = cindex;
198 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
199 }
200 }
201
202 /*
203 * TODO: For frame(s) that are in the retry state, we will reuse the
204 * sequence number(s) without setting the retry bit. The
205 * alternative is to give up on these and BAR the receiver's window
206 * forward.
207 */
208 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
209 struct ath_atx_tid *tid)
210
211 {
212 struct ath_buf *bf;
213 struct list_head bf_head;
214 INIT_LIST_HEAD(&bf_head);
215
216 for (;;) {
217 if (list_empty(&tid->buf_q))
218 break;
219
220 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
221 list_move_tail(&bf->list, &bf_head);
222
223 if (bf_isretried(bf))
224 ath_tx_update_baw(sc, tid, bf->bf_seqno);
225
226 spin_unlock(&txq->axq_lock);
227 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
228 spin_lock(&txq->axq_lock);
229 }
230
231 tid->seq_next = tid->seq_start;
232 tid->baw_tail = tid->baw_head;
233 }
234
235 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
236 {
237 struct sk_buff *skb;
238 struct ieee80211_hdr *hdr;
239
240 bf->bf_state.bf_type |= BUF_RETRY;
241 bf->bf_retries++;
242
243 skb = bf->bf_mpdu;
244 hdr = (struct ieee80211_hdr *)skb->data;
245 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
246 }
247
248 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
249 {
250 struct ath_buf *tbf;
251
252 spin_lock_bh(&sc->tx.txbuflock);
253 ASSERT(!list_empty((&sc->tx.txbuf)));
254 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
255 list_del(&tbf->list);
256 spin_unlock_bh(&sc->tx.txbuflock);
257
258 ATH_TXBUF_RESET(tbf);
259
260 tbf->bf_mpdu = bf->bf_mpdu;
261 tbf->bf_buf_addr = bf->bf_buf_addr;
262 *(tbf->bf_desc) = *(bf->bf_desc);
263 tbf->bf_state = bf->bf_state;
264 tbf->bf_dmacontext = bf->bf_dmacontext;
265
266 return tbf;
267 }
268
269 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
270 struct ath_buf *bf, struct list_head *bf_q,
271 int txok)
272 {
273 struct ath_node *an = NULL;
274 struct sk_buff *skb;
275 struct ieee80211_sta *sta;
276 struct ieee80211_hdr *hdr;
277 struct ath_atx_tid *tid = NULL;
278 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
279 struct ath_desc *ds = bf_last->bf_desc;
280 struct list_head bf_head, bf_pending;
281 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
282 u32 ba[WME_BA_BMP_SIZE >> 5];
283 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
284 bool rc_update = true;
285
286 skb = bf->bf_mpdu;
287 hdr = (struct ieee80211_hdr *)skb->data;
288
289 rcu_read_lock();
290
291 sta = ieee80211_find_sta(sc->hw, hdr->addr1);
292 if (!sta) {
293 rcu_read_unlock();
294 return;
295 }
296
297 an = (struct ath_node *)sta->drv_priv;
298 tid = ATH_AN_2_TID(an, bf->bf_tidno);
299
300 isaggr = bf_isaggr(bf);
301 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
302
303 if (isaggr && txok) {
304 if (ATH_DS_TX_BA(ds)) {
305 seq_st = ATH_DS_BA_SEQ(ds);
306 memcpy(ba, ATH_DS_BA_BITMAP(ds),
307 WME_BA_BMP_SIZE >> 3);
308 } else {
309 /*
310 * AR5416 can become deaf/mute when BA
311 * issue happens. Chip needs to be reset.
312 * But AP code may have sychronization issues
313 * when perform internal reset in this routine.
314 * Only enable reset in STA mode for now.
315 */
316 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
317 needreset = 1;
318 }
319 }
320
321 INIT_LIST_HEAD(&bf_pending);
322 INIT_LIST_HEAD(&bf_head);
323
324 nbad = ath_tx_num_badfrms(sc, bf, txok);
325 while (bf) {
326 txfail = txpending = 0;
327 bf_next = bf->bf_next;
328
329 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
330 /* transmit completion, subframe is
331 * acked by block ack */
332 acked_cnt++;
333 } else if (!isaggr && txok) {
334 /* transmit completion */
335 acked_cnt++;
336 } else {
337 if (!(tid->state & AGGR_CLEANUP) &&
338 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
339 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
340 ath_tx_set_retry(sc, bf);
341 txpending = 1;
342 } else {
343 bf->bf_state.bf_type |= BUF_XRETRY;
344 txfail = 1;
345 sendbar = 1;
346 txfail_cnt++;
347 }
348 } else {
349 /*
350 * cleanup in progress, just fail
351 * the un-acked sub-frames
352 */
353 txfail = 1;
354 }
355 }
356
357 if (bf_next == NULL) {
358 INIT_LIST_HEAD(&bf_head);
359 } else {
360 ASSERT(!list_empty(bf_q));
361 list_move_tail(&bf->list, &bf_head);
362 }
363
364 if (!txpending) {
365 /*
366 * complete the acked-ones/xretried ones; update
367 * block-ack window
368 */
369 spin_lock_bh(&txq->axq_lock);
370 ath_tx_update_baw(sc, tid, bf->bf_seqno);
371 spin_unlock_bh(&txq->axq_lock);
372
373 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
374 ath_tx_rc_status(bf, ds, nbad, txok, true);
375 rc_update = false;
376 } else {
377 ath_tx_rc_status(bf, ds, nbad, txok, false);
378 }
379
380 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
381 } else {
382 /* retry the un-acked ones */
383 if (bf->bf_next == NULL && bf_last->bf_stale) {
384 struct ath_buf *tbf;
385
386 tbf = ath_clone_txbuf(sc, bf_last);
387 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
388 list_add_tail(&tbf->list, &bf_head);
389 } else {
390 /*
391 * Clear descriptor status words for
392 * software retry
393 */
394 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
395 }
396
397 /*
398 * Put this buffer to the temporary pending
399 * queue to retain ordering
400 */
401 list_splice_tail_init(&bf_head, &bf_pending);
402 }
403
404 bf = bf_next;
405 }
406
407 if (tid->state & AGGR_CLEANUP) {
408 if (tid->baw_head == tid->baw_tail) {
409 tid->state &= ~AGGR_ADDBA_COMPLETE;
410 tid->addba_exchangeattempts = 0;
411 tid->state &= ~AGGR_CLEANUP;
412
413 /* send buffered frames as singles */
414 ath_tx_flush_tid(sc, tid);
415 }
416 rcu_read_unlock();
417 return;
418 }
419
420 /* prepend un-acked frames to the beginning of the pending frame queue */
421 if (!list_empty(&bf_pending)) {
422 spin_lock_bh(&txq->axq_lock);
423 list_splice(&bf_pending, &tid->buf_q);
424 ath_tx_queue_tid(txq, tid);
425 spin_unlock_bh(&txq->axq_lock);
426 }
427
428 rcu_read_unlock();
429
430 if (needreset)
431 ath_reset(sc, false);
432 }
433
434 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
435 struct ath_atx_tid *tid)
436 {
437 struct ath_rate_table *rate_table = sc->cur_rate_table;
438 struct sk_buff *skb;
439 struct ieee80211_tx_info *tx_info;
440 struct ieee80211_tx_rate *rates;
441 struct ath_tx_info_priv *tx_info_priv;
442 u32 max_4ms_framelen, frmlen;
443 u16 aggr_limit, legacy = 0, maxampdu;
444 int i;
445
446 skb = bf->bf_mpdu;
447 tx_info = IEEE80211_SKB_CB(skb);
448 rates = tx_info->control.rates;
449 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
450
451 /*
452 * Find the lowest frame length among the rate series that will have a
453 * 4ms transmit duration.
454 * TODO - TXOP limit needs to be considered.
455 */
456 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
457
458 for (i = 0; i < 4; i++) {
459 if (rates[i].count) {
460 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
461 legacy = 1;
462 break;
463 }
464
465 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
466 max_4ms_framelen = min(max_4ms_framelen, frmlen);
467 }
468 }
469
470 /*
471 * limit aggregate size by the minimum rate if rate selected is
472 * not a probe rate, if rate selected is a probe rate then
473 * avoid aggregation of this packet.
474 */
475 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
476 return 0;
477
478 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT);
479
480 /*
481 * h/w can accept aggregates upto 16 bit lengths (65535).
482 * The IE, however can hold upto 65536, which shows up here
483 * as zero. Ignore 65536 since we are constrained by hw.
484 */
485 maxampdu = tid->an->maxampdu;
486 if (maxampdu)
487 aggr_limit = min(aggr_limit, maxampdu);
488
489 return aggr_limit;
490 }
491
492 /*
493 * Returns the number of delimiters to be added to
494 * meet the minimum required mpdudensity.
495 * caller should make sure that the rate is HT rate .
496 */
497 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
498 struct ath_buf *bf, u16 frmlen)
499 {
500 struct ath_rate_table *rt = sc->cur_rate_table;
501 struct sk_buff *skb = bf->bf_mpdu;
502 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
503 u32 nsymbits, nsymbols, mpdudensity;
504 u16 minlen;
505 u8 rc, flags, rix;
506 int width, half_gi, ndelim, mindelim;
507
508 /* Select standard number of delimiters based on frame length alone */
509 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
510
511 /*
512 * If encryption enabled, hardware requires some more padding between
513 * subframes.
514 * TODO - this could be improved to be dependent on the rate.
515 * The hardware can keep up at lower rates, but not higher rates
516 */
517 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
518 ndelim += ATH_AGGR_ENCRYPTDELIM;
519
520 /*
521 * Convert desired mpdu density from microeconds to bytes based
522 * on highest rate in rate series (i.e. first rate) to determine
523 * required minimum length for subframe. Take into account
524 * whether high rate is 20 or 40Mhz and half or full GI.
525 */
526 mpdudensity = tid->an->mpdudensity;
527
528 /*
529 * If there is no mpdu density restriction, no further calculation
530 * is needed.
531 */
532 if (mpdudensity == 0)
533 return ndelim;
534
535 rix = tx_info->control.rates[0].idx;
536 flags = tx_info->control.rates[0].flags;
537 rc = rt->info[rix].ratecode;
538 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
539 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
540
541 if (half_gi)
542 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
543 else
544 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
545
546 if (nsymbols == 0)
547 nsymbols = 1;
548
549 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
550 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
551
552 if (frmlen < minlen) {
553 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
554 ndelim = max(mindelim, ndelim);
555 }
556
557 return ndelim;
558 }
559
560 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
561 struct ath_atx_tid *tid,
562 struct list_head *bf_q)
563 {
564 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
565 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
566 int rl = 0, nframes = 0, ndelim, prev_al = 0;
567 u16 aggr_limit = 0, al = 0, bpad = 0,
568 al_delta, h_baw = tid->baw_size / 2;
569 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
570
571 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
572
573 do {
574 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
575
576 /* do not step over block-ack window */
577 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
578 status = ATH_AGGR_BAW_CLOSED;
579 break;
580 }
581
582 if (!rl) {
583 aggr_limit = ath_lookup_rate(sc, bf, tid);
584 rl = 1;
585 }
586
587 /* do not exceed aggregation limit */
588 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
589
590 if (nframes &&
591 (aggr_limit < (al + bpad + al_delta + prev_al))) {
592 status = ATH_AGGR_LIMITED;
593 break;
594 }
595
596 /* do not exceed subframe limit */
597 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
598 status = ATH_AGGR_LIMITED;
599 break;
600 }
601 nframes++;
602
603 /* add padding for previous frame to aggregation length */
604 al += bpad + al_delta;
605
606 /*
607 * Get the delimiters needed to meet the MPDU
608 * density for this node.
609 */
610 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
611 bpad = PADBYTES(al_delta) + (ndelim << 2);
612
613 bf->bf_next = NULL;
614 bf->bf_desc->ds_link = 0;
615
616 /* link buffers of this frame to the aggregate */
617 ath_tx_addto_baw(sc, tid, bf);
618 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
619 list_move_tail(&bf->list, bf_q);
620 if (bf_prev) {
621 bf_prev->bf_next = bf;
622 bf_prev->bf_desc->ds_link = bf->bf_daddr;
623 }
624 bf_prev = bf;
625 } while (!list_empty(&tid->buf_q));
626
627 bf_first->bf_al = al;
628 bf_first->bf_nframes = nframes;
629
630 return status;
631 #undef PADBYTES
632 }
633
634 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
635 struct ath_atx_tid *tid)
636 {
637 struct ath_buf *bf;
638 enum ATH_AGGR_STATUS status;
639 struct list_head bf_q;
640
641 do {
642 if (list_empty(&tid->buf_q))
643 return;
644
645 INIT_LIST_HEAD(&bf_q);
646
647 status = ath_tx_form_aggr(sc, tid, &bf_q);
648
649 /*
650 * no frames picked up to be aggregated;
651 * block-ack window is not open.
652 */
653 if (list_empty(&bf_q))
654 break;
655
656 bf = list_first_entry(&bf_q, struct ath_buf, list);
657 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
658
659 /* if only one frame, send as non-aggregate */
660 if (bf->bf_nframes == 1) {
661 bf->bf_state.bf_type &= ~BUF_AGGR;
662 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
663 ath_buf_set_rate(sc, bf);
664 ath_tx_txqaddbuf(sc, txq, &bf_q);
665 continue;
666 }
667
668 /* setup first desc of aggregate */
669 bf->bf_state.bf_type |= BUF_AGGR;
670 ath_buf_set_rate(sc, bf);
671 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
672
673 /* anchor last desc of aggregate */
674 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
675
676 txq->axq_aggr_depth++;
677 ath_tx_txqaddbuf(sc, txq, &bf_q);
678
679 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
680 status != ATH_AGGR_BAW_CLOSED);
681 }
682
683 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
684 u16 tid, u16 *ssn)
685 {
686 struct ath_atx_tid *txtid;
687 struct ath_node *an;
688
689 an = (struct ath_node *)sta->drv_priv;
690
691 if (sc->sc_flags & SC_OP_TXAGGR) {
692 txtid = ATH_AN_2_TID(an, tid);
693 txtid->state |= AGGR_ADDBA_PROGRESS;
694 ath_tx_pause_tid(sc, txtid);
695 *ssn = txtid->seq_start;
696 }
697
698 return 0;
699 }
700
701 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
702 {
703 struct ath_node *an = (struct ath_node *)sta->drv_priv;
704 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
705 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
706 struct ath_buf *bf;
707 struct list_head bf_head;
708 INIT_LIST_HEAD(&bf_head);
709
710 if (txtid->state & AGGR_CLEANUP)
711 return 0;
712
713 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
714 txtid->addba_exchangeattempts = 0;
715 return 0;
716 }
717
718 ath_tx_pause_tid(sc, txtid);
719
720 /* drop all software retried frames and mark this TID */
721 spin_lock_bh(&txq->axq_lock);
722 while (!list_empty(&txtid->buf_q)) {
723 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
724 if (!bf_isretried(bf)) {
725 /*
726 * NB: it's based on the assumption that
727 * software retried frame will always stay
728 * at the head of software queue.
729 */
730 break;
731 }
732 list_move_tail(&bf->list, &bf_head);
733 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
734 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
735 }
736 spin_unlock_bh(&txq->axq_lock);
737
738 if (txtid->baw_head != txtid->baw_tail) {
739 txtid->state |= AGGR_CLEANUP;
740 } else {
741 txtid->state &= ~AGGR_ADDBA_COMPLETE;
742 txtid->addba_exchangeattempts = 0;
743 ath_tx_flush_tid(sc, txtid);
744 }
745
746 return 0;
747 }
748
749 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
750 {
751 struct ath_atx_tid *txtid;
752 struct ath_node *an;
753
754 an = (struct ath_node *)sta->drv_priv;
755
756 if (sc->sc_flags & SC_OP_TXAGGR) {
757 txtid = ATH_AN_2_TID(an, tid);
758 txtid->baw_size =
759 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
760 txtid->state |= AGGR_ADDBA_COMPLETE;
761 txtid->state &= ~AGGR_ADDBA_PROGRESS;
762 ath_tx_resume_tid(sc, txtid);
763 }
764 }
765
766 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
767 {
768 struct ath_atx_tid *txtid;
769
770 if (!(sc->sc_flags & SC_OP_TXAGGR))
771 return false;
772
773 txtid = ATH_AN_2_TID(an, tidno);
774
775 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
776 if (!(txtid->state & AGGR_ADDBA_PROGRESS) &&
777 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
778 txtid->addba_exchangeattempts++;
779 return true;
780 }
781 }
782
783 return false;
784 }
785
786 /********************/
787 /* Queue Management */
788 /********************/
789
790 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
791 struct ath_txq *txq)
792 {
793 struct ath_atx_ac *ac, *ac_tmp;
794 struct ath_atx_tid *tid, *tid_tmp;
795
796 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
797 list_del(&ac->list);
798 ac->sched = false;
799 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
800 list_del(&tid->list);
801 tid->sched = false;
802 ath_tid_drain(sc, txq, tid);
803 }
804 }
805 }
806
807 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
808 {
809 struct ath_hw *ah = sc->sc_ah;
810 struct ath9k_tx_queue_info qi;
811 int qnum;
812
813 memset(&qi, 0, sizeof(qi));
814 qi.tqi_subtype = subtype;
815 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
816 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
817 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
818 qi.tqi_physCompBuf = 0;
819
820 /*
821 * Enable interrupts only for EOL and DESC conditions.
822 * We mark tx descriptors to receive a DESC interrupt
823 * when a tx queue gets deep; otherwise waiting for the
824 * EOL to reap descriptors. Note that this is done to
825 * reduce interrupt load and this only defers reaping
826 * descriptors, never transmitting frames. Aside from
827 * reducing interrupts this also permits more concurrency.
828 * The only potential downside is if the tx queue backs
829 * up in which case the top half of the kernel may backup
830 * due to a lack of tx descriptors.
831 *
832 * The UAPSD queue is an exception, since we take a desc-
833 * based intr on the EOSP frames.
834 */
835 if (qtype == ATH9K_TX_QUEUE_UAPSD)
836 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
837 else
838 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
839 TXQ_FLAG_TXDESCINT_ENABLE;
840 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
841 if (qnum == -1) {
842 /*
843 * NB: don't print a message, this happens
844 * normally on parts with too few tx queues
845 */
846 return NULL;
847 }
848 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
849 DPRINTF(sc, ATH_DBG_FATAL,
850 "qnum %u out of range, max %u!\n",
851 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
852 ath9k_hw_releasetxqueue(ah, qnum);
853 return NULL;
854 }
855 if (!ATH_TXQ_SETUP(sc, qnum)) {
856 struct ath_txq *txq = &sc->tx.txq[qnum];
857
858 txq->axq_qnum = qnum;
859 txq->axq_link = NULL;
860 INIT_LIST_HEAD(&txq->axq_q);
861 INIT_LIST_HEAD(&txq->axq_acq);
862 spin_lock_init(&txq->axq_lock);
863 txq->axq_depth = 0;
864 txq->axq_aggr_depth = 0;
865 txq->axq_totalqueued = 0;
866 txq->axq_linkbuf = NULL;
867 sc->tx.txqsetup |= 1<<qnum;
868 }
869 return &sc->tx.txq[qnum];
870 }
871
872 static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
873 {
874 int qnum;
875
876 switch (qtype) {
877 case ATH9K_TX_QUEUE_DATA:
878 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
879 DPRINTF(sc, ATH_DBG_FATAL,
880 "HAL AC %u out of range, max %zu!\n",
881 haltype, ARRAY_SIZE(sc->tx.hwq_map));
882 return -1;
883 }
884 qnum = sc->tx.hwq_map[haltype];
885 break;
886 case ATH9K_TX_QUEUE_BEACON:
887 qnum = sc->beacon.beaconq;
888 break;
889 case ATH9K_TX_QUEUE_CAB:
890 qnum = sc->beacon.cabq->axq_qnum;
891 break;
892 default:
893 qnum = -1;
894 }
895 return qnum;
896 }
897
898 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
899 {
900 struct ath_txq *txq = NULL;
901 int qnum;
902
903 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
904 txq = &sc->tx.txq[qnum];
905
906 spin_lock_bh(&txq->axq_lock);
907
908 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
909 DPRINTF(sc, ATH_DBG_XMIT,
910 "TX queue: %d is full, depth: %d\n",
911 qnum, txq->axq_depth);
912 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
913 txq->stopped = 1;
914 spin_unlock_bh(&txq->axq_lock);
915 return NULL;
916 }
917
918 spin_unlock_bh(&txq->axq_lock);
919
920 return txq;
921 }
922
923 int ath_txq_update(struct ath_softc *sc, int qnum,
924 struct ath9k_tx_queue_info *qinfo)
925 {
926 struct ath_hw *ah = sc->sc_ah;
927 int error = 0;
928 struct ath9k_tx_queue_info qi;
929
930 if (qnum == sc->beacon.beaconq) {
931 /*
932 * XXX: for beacon queue, we just save the parameter.
933 * It will be picked up by ath_beaconq_config when
934 * it's necessary.
935 */
936 sc->beacon.beacon_qi = *qinfo;
937 return 0;
938 }
939
940 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
941
942 ath9k_hw_get_txq_props(ah, qnum, &qi);
943 qi.tqi_aifs = qinfo->tqi_aifs;
944 qi.tqi_cwmin = qinfo->tqi_cwmin;
945 qi.tqi_cwmax = qinfo->tqi_cwmax;
946 qi.tqi_burstTime = qinfo->tqi_burstTime;
947 qi.tqi_readyTime = qinfo->tqi_readyTime;
948
949 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
950 DPRINTF(sc, ATH_DBG_FATAL,
951 "Unable to update hardware queue %u!\n", qnum);
952 error = -EIO;
953 } else {
954 ath9k_hw_resettxqueue(ah, qnum);
955 }
956
957 return error;
958 }
959
960 int ath_cabq_update(struct ath_softc *sc)
961 {
962 struct ath9k_tx_queue_info qi;
963 int qnum = sc->beacon.cabq->axq_qnum;
964
965 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
966 /*
967 * Ensure the readytime % is within the bounds.
968 */
969 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
970 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
971 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
972 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
973
974 qi.tqi_readyTime = (sc->hw->conf.beacon_int *
975 sc->config.cabqReadytime) / 100;
976 ath_txq_update(sc, qnum, &qi);
977
978 return 0;
979 }
980
981 /*
982 * Drain a given TX queue (could be Beacon or Data)
983 *
984 * This assumes output has been stopped and
985 * we do not need to block ath_tx_tasklet.
986 */
987 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
988 {
989 struct ath_buf *bf, *lastbf;
990 struct list_head bf_head;
991
992 INIT_LIST_HEAD(&bf_head);
993
994 for (;;) {
995 spin_lock_bh(&txq->axq_lock);
996
997 if (list_empty(&txq->axq_q)) {
998 txq->axq_link = NULL;
999 txq->axq_linkbuf = NULL;
1000 spin_unlock_bh(&txq->axq_lock);
1001 break;
1002 }
1003
1004 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1005
1006 if (bf->bf_stale) {
1007 list_del(&bf->list);
1008 spin_unlock_bh(&txq->axq_lock);
1009
1010 spin_lock_bh(&sc->tx.txbuflock);
1011 list_add_tail(&bf->list, &sc->tx.txbuf);
1012 spin_unlock_bh(&sc->tx.txbuflock);
1013 continue;
1014 }
1015
1016 lastbf = bf->bf_lastbf;
1017 if (!retry_tx)
1018 lastbf->bf_desc->ds_txstat.ts_flags =
1019 ATH9K_TX_SW_ABORTED;
1020
1021 /* remove ath_buf's of the same mpdu from txq */
1022 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1023 txq->axq_depth--;
1024
1025 spin_unlock_bh(&txq->axq_lock);
1026
1027 if (bf_isampdu(bf))
1028 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1029 else
1030 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1031 }
1032
1033 /* flush any pending frames if aggregation is enabled */
1034 if (sc->sc_flags & SC_OP_TXAGGR) {
1035 if (!retry_tx) {
1036 spin_lock_bh(&txq->axq_lock);
1037 ath_txq_drain_pending_buffers(sc, txq);
1038 spin_unlock_bh(&txq->axq_lock);
1039 }
1040 }
1041 }
1042
1043 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1044 {
1045 struct ath_hw *ah = sc->sc_ah;
1046 struct ath_txq *txq;
1047 int i, npend = 0;
1048
1049 if (sc->sc_flags & SC_OP_INVALID)
1050 return;
1051
1052 /* Stop beacon queue */
1053 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1054
1055 /* Stop data queues */
1056 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1057 if (ATH_TXQ_SETUP(sc, i)) {
1058 txq = &sc->tx.txq[i];
1059 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1060 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1061 }
1062 }
1063
1064 if (npend) {
1065 int r;
1066
1067 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1068
1069 spin_lock_bh(&sc->sc_resetlock);
1070 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1071 if (r)
1072 DPRINTF(sc, ATH_DBG_FATAL,
1073 "Unable to reset hardware; reset status %u\n",
1074 r);
1075 spin_unlock_bh(&sc->sc_resetlock);
1076 }
1077
1078 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1079 if (ATH_TXQ_SETUP(sc, i))
1080 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1081 }
1082 }
1083
1084 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1085 {
1086 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1087 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1088 }
1089
1090 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1091 {
1092 struct ath_atx_ac *ac;
1093 struct ath_atx_tid *tid;
1094
1095 if (list_empty(&txq->axq_acq))
1096 return;
1097
1098 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1099 list_del(&ac->list);
1100 ac->sched = false;
1101
1102 do {
1103 if (list_empty(&ac->tid_q))
1104 return;
1105
1106 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1107 list_del(&tid->list);
1108 tid->sched = false;
1109
1110 if (tid->paused)
1111 continue;
1112
1113 if ((txq->axq_depth % 2) == 0)
1114 ath_tx_sched_aggr(sc, txq, tid);
1115
1116 /*
1117 * add tid to round-robin queue if more frames
1118 * are pending for the tid
1119 */
1120 if (!list_empty(&tid->buf_q))
1121 ath_tx_queue_tid(txq, tid);
1122
1123 break;
1124 } while (!list_empty(&ac->tid_q));
1125
1126 if (!list_empty(&ac->tid_q)) {
1127 if (!ac->sched) {
1128 ac->sched = true;
1129 list_add_tail(&ac->list, &txq->axq_acq);
1130 }
1131 }
1132 }
1133
1134 int ath_tx_setup(struct ath_softc *sc, int haltype)
1135 {
1136 struct ath_txq *txq;
1137
1138 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1139 DPRINTF(sc, ATH_DBG_FATAL,
1140 "HAL AC %u out of range, max %zu!\n",
1141 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1142 return 0;
1143 }
1144 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1145 if (txq != NULL) {
1146 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1147 return 1;
1148 } else
1149 return 0;
1150 }
1151
1152 /***********/
1153 /* TX, DMA */
1154 /***********/
1155
1156 /*
1157 * Insert a chain of ath_buf (descriptors) on a txq and
1158 * assume the descriptors are already chained together by caller.
1159 */
1160 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1161 struct list_head *head)
1162 {
1163 struct ath_hw *ah = sc->sc_ah;
1164 struct ath_buf *bf;
1165
1166 /*
1167 * Insert the frame on the outbound list and
1168 * pass it on to the hardware.
1169 */
1170
1171 if (list_empty(head))
1172 return;
1173
1174 bf = list_first_entry(head, struct ath_buf, list);
1175
1176 list_splice_tail_init(head, &txq->axq_q);
1177 txq->axq_depth++;
1178 txq->axq_totalqueued++;
1179 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1180
1181 DPRINTF(sc, ATH_DBG_QUEUE,
1182 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1183
1184 if (txq->axq_link == NULL) {
1185 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1186 DPRINTF(sc, ATH_DBG_XMIT,
1187 "TXDP[%u] = %llx (%p)\n",
1188 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1189 } else {
1190 *txq->axq_link = bf->bf_daddr;
1191 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1192 txq->axq_qnum, txq->axq_link,
1193 ito64(bf->bf_daddr), bf->bf_desc);
1194 }
1195 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1196 ath9k_hw_txstart(ah, txq->axq_qnum);
1197 }
1198
1199 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1200 {
1201 struct ath_buf *bf = NULL;
1202
1203 spin_lock_bh(&sc->tx.txbuflock);
1204
1205 if (unlikely(list_empty(&sc->tx.txbuf))) {
1206 spin_unlock_bh(&sc->tx.txbuflock);
1207 return NULL;
1208 }
1209
1210 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1211 list_del(&bf->list);
1212
1213 spin_unlock_bh(&sc->tx.txbuflock);
1214
1215 return bf;
1216 }
1217
1218 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1219 struct list_head *bf_head,
1220 struct ath_tx_control *txctl)
1221 {
1222 struct ath_buf *bf;
1223
1224 bf = list_first_entry(bf_head, struct ath_buf, list);
1225 bf->bf_state.bf_type |= BUF_AMPDU;
1226
1227 /*
1228 * Do not queue to h/w when any of the following conditions is true:
1229 * - there are pending frames in software queue
1230 * - the TID is currently paused for ADDBA/BAR request
1231 * - seqno is not within block-ack window
1232 * - h/w queue depth exceeds low water mark
1233 */
1234 if (!list_empty(&tid->buf_q) || tid->paused ||
1235 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1236 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1237 /*
1238 * Add this frame to software queue for scheduling later
1239 * for aggregation.
1240 */
1241 list_move_tail(&bf->list, &tid->buf_q);
1242 ath_tx_queue_tid(txctl->txq, tid);
1243 return;
1244 }
1245
1246 /* Add sub-frame to BAW */
1247 ath_tx_addto_baw(sc, tid, bf);
1248
1249 /* Queue to h/w without aggregation */
1250 bf->bf_nframes = 1;
1251 bf->bf_lastbf = bf;
1252 ath_buf_set_rate(sc, bf);
1253 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1254 }
1255
1256 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1257 struct ath_atx_tid *tid,
1258 struct list_head *bf_head)
1259 {
1260 struct ath_buf *bf;
1261
1262 bf = list_first_entry(bf_head, struct ath_buf, list);
1263 bf->bf_state.bf_type &= ~BUF_AMPDU;
1264
1265 /* update starting sequence number for subsequent ADDBA request */
1266 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1267
1268 bf->bf_nframes = 1;
1269 bf->bf_lastbf = bf;
1270 ath_buf_set_rate(sc, bf);
1271 ath_tx_txqaddbuf(sc, txq, bf_head);
1272 }
1273
1274 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1275 struct list_head *bf_head)
1276 {
1277 struct ath_buf *bf;
1278
1279 bf = list_first_entry(bf_head, struct ath_buf, list);
1280
1281 bf->bf_lastbf = bf;
1282 bf->bf_nframes = 1;
1283 ath_buf_set_rate(sc, bf);
1284 ath_tx_txqaddbuf(sc, txq, bf_head);
1285 }
1286
1287 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1288 {
1289 struct ieee80211_hdr *hdr;
1290 enum ath9k_pkt_type htype;
1291 __le16 fc;
1292
1293 hdr = (struct ieee80211_hdr *)skb->data;
1294 fc = hdr->frame_control;
1295
1296 if (ieee80211_is_beacon(fc))
1297 htype = ATH9K_PKT_TYPE_BEACON;
1298 else if (ieee80211_is_probe_resp(fc))
1299 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1300 else if (ieee80211_is_atim(fc))
1301 htype = ATH9K_PKT_TYPE_ATIM;
1302 else if (ieee80211_is_pspoll(fc))
1303 htype = ATH9K_PKT_TYPE_PSPOLL;
1304 else
1305 htype = ATH9K_PKT_TYPE_NORMAL;
1306
1307 return htype;
1308 }
1309
1310 static bool is_pae(struct sk_buff *skb)
1311 {
1312 struct ieee80211_hdr *hdr;
1313 __le16 fc;
1314
1315 hdr = (struct ieee80211_hdr *)skb->data;
1316 fc = hdr->frame_control;
1317
1318 if (ieee80211_is_data(fc)) {
1319 if (ieee80211_is_nullfunc(fc) ||
1320 /* Port Access Entity (IEEE 802.1X) */
1321 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1322 return true;
1323 }
1324 }
1325
1326 return false;
1327 }
1328
1329 static int get_hw_crypto_keytype(struct sk_buff *skb)
1330 {
1331 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1332
1333 if (tx_info->control.hw_key) {
1334 if (tx_info->control.hw_key->alg == ALG_WEP)
1335 return ATH9K_KEY_TYPE_WEP;
1336 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1337 return ATH9K_KEY_TYPE_TKIP;
1338 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1339 return ATH9K_KEY_TYPE_AES;
1340 }
1341
1342 return ATH9K_KEY_TYPE_CLEAR;
1343 }
1344
1345 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1346 struct ath_buf *bf)
1347 {
1348 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1349 struct ieee80211_hdr *hdr;
1350 struct ath_node *an;
1351 struct ath_atx_tid *tid;
1352 __le16 fc;
1353 u8 *qc;
1354
1355 if (!tx_info->control.sta)
1356 return;
1357
1358 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1359 hdr = (struct ieee80211_hdr *)skb->data;
1360 fc = hdr->frame_control;
1361
1362 if (ieee80211_is_data_qos(fc)) {
1363 qc = ieee80211_get_qos_ctl(hdr);
1364 bf->bf_tidno = qc[0] & 0xf;
1365 }
1366
1367 /*
1368 * For HT capable stations, we save tidno for later use.
1369 * We also override seqno set by upper layer with the one
1370 * in tx aggregation state.
1371 *
1372 * If fragmentation is on, the sequence number is
1373 * not overridden, since it has been
1374 * incremented by the fragmentation routine.
1375 *
1376 * FIXME: check if the fragmentation threshold exceeds
1377 * IEEE80211 max.
1378 */
1379 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1380 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1381 IEEE80211_SEQ_SEQ_SHIFT);
1382 bf->bf_seqno = tid->seq_next;
1383 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1384 }
1385
1386 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1387 struct ath_txq *txq)
1388 {
1389 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1390 int flags = 0;
1391
1392 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1393 flags |= ATH9K_TXDESC_INTREQ;
1394
1395 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1396 flags |= ATH9K_TXDESC_NOACK;
1397
1398 return flags;
1399 }
1400
1401 /*
1402 * rix - rate index
1403 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1404 * width - 0 for 20 MHz, 1 for 40 MHz
1405 * half_gi - to use 4us v/s 3.6 us for symbol time
1406 */
1407 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1408 int width, int half_gi, bool shortPreamble)
1409 {
1410 struct ath_rate_table *rate_table = sc->cur_rate_table;
1411 u32 nbits, nsymbits, duration, nsymbols;
1412 u8 rc;
1413 int streams, pktlen;
1414
1415 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1416 rc = rate_table->info[rix].ratecode;
1417
1418 /* for legacy rates, use old function to compute packet duration */
1419 if (!IS_HT_RATE(rc))
1420 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1421 rix, shortPreamble);
1422
1423 /* find number of symbols: PLCP + data */
1424 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1425 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1426 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1427
1428 if (!half_gi)
1429 duration = SYMBOL_TIME(nsymbols);
1430 else
1431 duration = SYMBOL_TIME_HALFGI(nsymbols);
1432
1433 /* addup duration for legacy/ht training and signal fields */
1434 streams = HT_RC_2_STREAMS(rc);
1435 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1436
1437 return duration;
1438 }
1439
1440 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1441 {
1442 struct ath_rate_table *rt = sc->cur_rate_table;
1443 struct ath9k_11n_rate_series series[4];
1444 struct sk_buff *skb;
1445 struct ieee80211_tx_info *tx_info;
1446 struct ieee80211_tx_rate *rates;
1447 struct ieee80211_hdr *hdr;
1448 int i, flags = 0;
1449 u8 rix = 0, ctsrate = 0;
1450 bool is_pspoll;
1451
1452 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1453
1454 skb = bf->bf_mpdu;
1455 tx_info = IEEE80211_SKB_CB(skb);
1456 rates = tx_info->control.rates;
1457 hdr = (struct ieee80211_hdr *)skb->data;
1458 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1459
1460 /*
1461 * We check if Short Preamble is needed for the CTS rate by
1462 * checking the BSS's global flag.
1463 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1464 */
1465 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1466 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
1467 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1468 else
1469 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1470
1471 /*
1472 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1473 * Check the first rate in the series to decide whether RTS/CTS
1474 * or CTS-to-self has to be used.
1475 */
1476 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1477 flags = ATH9K_TXDESC_CTSENA;
1478 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1479 flags = ATH9K_TXDESC_RTSENA;
1480
1481 /* FIXME: Handle aggregation protection */
1482 if (sc->config.ath_aggr_prot &&
1483 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1484 flags = ATH9K_TXDESC_RTSENA;
1485 }
1486
1487 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1488 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1489 flags &= ~(ATH9K_TXDESC_RTSENA);
1490
1491 for (i = 0; i < 4; i++) {
1492 if (!rates[i].count || (rates[i].idx < 0))
1493 continue;
1494
1495 rix = rates[i].idx;
1496 series[i].Tries = rates[i].count;
1497 series[i].ChSel = sc->tx_chainmask;
1498
1499 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1500 series[i].Rate = rt->info[rix].ratecode |
1501 rt->info[rix].short_preamble;
1502 else
1503 series[i].Rate = rt->info[rix].ratecode;
1504
1505 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1506 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1507 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1508 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1509 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1510 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1511
1512 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1513 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1514 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1515 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
1516 }
1517
1518 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1519 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1520 bf->bf_lastbf->bf_desc,
1521 !is_pspoll, ctsrate,
1522 0, series, 4, flags);
1523
1524 if (sc->config.ath_aggr_prot && flags)
1525 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1526 }
1527
1528 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1529 struct sk_buff *skb,
1530 struct ath_tx_control *txctl)
1531 {
1532 struct ath_wiphy *aphy = hw->priv;
1533 struct ath_softc *sc = aphy->sc;
1534 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1535 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1536 struct ath_tx_info_priv *tx_info_priv;
1537 int hdrlen;
1538 __le16 fc;
1539
1540 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1541 if (unlikely(!tx_info_priv))
1542 return -ENOMEM;
1543 tx_info->rate_driver_data[0] = tx_info_priv;
1544 tx_info_priv->aphy = aphy;
1545 tx_info_priv->frame_type = txctl->frame_type;
1546 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1547 fc = hdr->frame_control;
1548
1549 ATH_TXBUF_RESET(bf);
1550
1551 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1552
1553 if (conf_is_ht(&sc->hw->conf) && !is_pae(skb))
1554 bf->bf_state.bf_type |= BUF_HT;
1555
1556 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1557
1558 bf->bf_keytype = get_hw_crypto_keytype(skb);
1559 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1560 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1561 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1562 } else {
1563 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1564 }
1565
1566 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1567 assign_aggr_tid_seqno(skb, bf);
1568
1569 bf->bf_mpdu = skb;
1570
1571 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1572 skb->len, DMA_TO_DEVICE);
1573 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1574 bf->bf_mpdu = NULL;
1575 DPRINTF(sc, ATH_DBG_CONFIG,
1576 "dma_mapping_error() on TX\n");
1577 return -ENOMEM;
1578 }
1579
1580 bf->bf_buf_addr = bf->bf_dmacontext;
1581 return 0;
1582 }
1583
1584 /* FIXME: tx power */
1585 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1586 struct ath_tx_control *txctl)
1587 {
1588 struct sk_buff *skb = bf->bf_mpdu;
1589 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1590 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1591 struct ath_node *an = NULL;
1592 struct list_head bf_head;
1593 struct ath_desc *ds;
1594 struct ath_atx_tid *tid;
1595 struct ath_hw *ah = sc->sc_ah;
1596 int frm_type;
1597 __le16 fc;
1598
1599 frm_type = get_hw_packet_type(skb);
1600 fc = hdr->frame_control;
1601
1602 INIT_LIST_HEAD(&bf_head);
1603 list_add_tail(&bf->list, &bf_head);
1604
1605 ds = bf->bf_desc;
1606 ds->ds_link = 0;
1607 ds->ds_data = bf->bf_buf_addr;
1608
1609 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1610 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1611
1612 ath9k_hw_filltxdesc(ah, ds,
1613 skb->len, /* segment length */
1614 true, /* first segment */
1615 true, /* last segment */
1616 ds); /* first descriptor */
1617
1618 spin_lock_bh(&txctl->txq->axq_lock);
1619
1620 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1621 tx_info->control.sta) {
1622 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1623 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1624
1625 if (!ieee80211_is_data_qos(fc)) {
1626 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1627 goto tx_done;
1628 }
1629
1630 if (ath_aggr_query(sc, an, bf->bf_tidno)) {
1631 /*
1632 * Try aggregation if it's a unicast data frame
1633 * and the destination is HT capable.
1634 */
1635 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1636 } else {
1637 /*
1638 * Send this frame as regular when ADDBA
1639 * exchange is neither complete nor pending.
1640 */
1641 ath_tx_send_ht_normal(sc, txctl->txq,
1642 tid, &bf_head);
1643 }
1644 } else {
1645 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1646 }
1647
1648 tx_done:
1649 spin_unlock_bh(&txctl->txq->axq_lock);
1650 }
1651
1652 /* Upon failure caller should free skb */
1653 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1654 struct ath_tx_control *txctl)
1655 {
1656 struct ath_wiphy *aphy = hw->priv;
1657 struct ath_softc *sc = aphy->sc;
1658 struct ath_buf *bf;
1659 int r;
1660
1661 bf = ath_tx_get_buffer(sc);
1662 if (!bf) {
1663 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1664 return -1;
1665 }
1666
1667 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1668 if (unlikely(r)) {
1669 struct ath_txq *txq = txctl->txq;
1670
1671 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
1672
1673 /* upon ath_tx_processq() this TX queue will be resumed, we
1674 * guarantee this will happen by knowing beforehand that
1675 * we will at least have to run TX completionon one buffer
1676 * on the queue */
1677 spin_lock_bh(&txq->axq_lock);
1678 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1679 ieee80211_stop_queue(sc->hw,
1680 skb_get_queue_mapping(skb));
1681 txq->stopped = 1;
1682 }
1683 spin_unlock_bh(&txq->axq_lock);
1684
1685 spin_lock_bh(&sc->tx.txbuflock);
1686 list_add_tail(&bf->list, &sc->tx.txbuf);
1687 spin_unlock_bh(&sc->tx.txbuflock);
1688
1689 return r;
1690 }
1691
1692 ath_tx_start_dma(sc, bf, txctl);
1693
1694 return 0;
1695 }
1696
1697 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1698 {
1699 struct ath_wiphy *aphy = hw->priv;
1700 struct ath_softc *sc = aphy->sc;
1701 int hdrlen, padsize;
1702 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1703 struct ath_tx_control txctl;
1704
1705 memset(&txctl, 0, sizeof(struct ath_tx_control));
1706
1707 /*
1708 * As a temporary workaround, assign seq# here; this will likely need
1709 * to be cleaned up to work better with Beacon transmission and virtual
1710 * BSSes.
1711 */
1712 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1713 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1714 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1715 sc->tx.seq_no += 0x10;
1716 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1717 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1718 }
1719
1720 /* Add the padding after the header if this is not already done */
1721 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1722 if (hdrlen & 3) {
1723 padsize = hdrlen % 4;
1724 if (skb_headroom(skb) < padsize) {
1725 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
1726 dev_kfree_skb_any(skb);
1727 return;
1728 }
1729 skb_push(skb, padsize);
1730 memmove(skb->data, skb->data + padsize, hdrlen);
1731 }
1732
1733 txctl.txq = sc->beacon.cabq;
1734
1735 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
1736
1737 if (ath_tx_start(hw, skb, &txctl) != 0) {
1738 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
1739 goto exit;
1740 }
1741
1742 return;
1743 exit:
1744 dev_kfree_skb_any(skb);
1745 }
1746
1747 /*****************/
1748 /* TX Completion */
1749 /*****************/
1750
1751 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1752 int tx_flags)
1753 {
1754 struct ieee80211_hw *hw = sc->hw;
1755 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1756 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1757 int hdrlen, padsize;
1758 int frame_type = ATH9K_NOT_INTERNAL;
1759
1760 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1761
1762 if (tx_info_priv) {
1763 hw = tx_info_priv->aphy->hw;
1764 frame_type = tx_info_priv->frame_type;
1765 }
1766
1767 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1768 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1769 kfree(tx_info_priv);
1770 tx_info->rate_driver_data[0] = NULL;
1771 }
1772
1773 if (tx_flags & ATH_TX_BAR)
1774 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1775
1776 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1777 /* Frame was ACKed */
1778 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1779 }
1780
1781 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1782 padsize = hdrlen & 3;
1783 if (padsize && hdrlen >= 24) {
1784 /*
1785 * Remove MAC header padding before giving the frame back to
1786 * mac80211.
1787 */
1788 memmove(skb->data + padsize, skb->data, hdrlen);
1789 skb_pull(skb, padsize);
1790 }
1791
1792 if (frame_type == ATH9K_NOT_INTERNAL)
1793 ieee80211_tx_status(hw, skb);
1794 else
1795 ath9k_tx_status(hw, skb);
1796 }
1797
1798 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1799 struct list_head *bf_q,
1800 int txok, int sendbar)
1801 {
1802 struct sk_buff *skb = bf->bf_mpdu;
1803 unsigned long flags;
1804 int tx_flags = 0;
1805
1806
1807 if (sendbar)
1808 tx_flags = ATH_TX_BAR;
1809
1810 if (!txok) {
1811 tx_flags |= ATH_TX_ERROR;
1812
1813 if (bf_isxretried(bf))
1814 tx_flags |= ATH_TX_XRETRY;
1815 }
1816
1817 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1818 ath_tx_complete(sc, skb, tx_flags);
1819
1820 /*
1821 * Return the list of ath_buf of this mpdu to free queue
1822 */
1823 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1824 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1825 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1826 }
1827
1828 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1829 int txok)
1830 {
1831 struct ath_buf *bf_last = bf->bf_lastbf;
1832 struct ath_desc *ds = bf_last->bf_desc;
1833 u16 seq_st = 0;
1834 u32 ba[WME_BA_BMP_SIZE >> 5];
1835 int ba_index;
1836 int nbad = 0;
1837 int isaggr = 0;
1838
1839 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1840 return 0;
1841
1842 isaggr = bf_isaggr(bf);
1843 if (isaggr) {
1844 seq_st = ATH_DS_BA_SEQ(ds);
1845 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1846 }
1847
1848 while (bf) {
1849 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1850 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1851 nbad++;
1852
1853 bf = bf->bf_next;
1854 }
1855
1856 return nbad;
1857 }
1858
1859 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds,
1860 int nbad, int txok, bool update_rc)
1861 {
1862 struct sk_buff *skb = bf->bf_mpdu;
1863 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1864 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1865 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1866 struct ieee80211_hw *hw = tx_info_priv->aphy->hw;
1867 u8 i, tx_rateindex;
1868
1869 if (txok)
1870 tx_info->status.ack_signal = ds->ds_txstat.ts_rssi;
1871
1872 tx_rateindex = ds->ds_txstat.ts_rateindex;
1873 WARN_ON(tx_rateindex >= hw->max_rates);
1874
1875 tx_info_priv->update_rc = update_rc;
1876 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1877 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1878
1879 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1880 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1881 if (ieee80211_is_data(hdr->frame_control)) {
1882 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1883 sizeof(tx_info_priv->tx));
1884 tx_info_priv->n_frames = bf->bf_nframes;
1885 tx_info_priv->n_bad_frames = nbad;
1886 }
1887 }
1888
1889 for (i = tx_rateindex + 1; i < hw->max_rates; i++)
1890 tx_info->status.rates[i].count = 0;
1891
1892 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
1893 }
1894
1895 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1896 {
1897 int qnum;
1898
1899 spin_lock_bh(&txq->axq_lock);
1900 if (txq->stopped &&
1901 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1902 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1903 if (qnum != -1) {
1904 ieee80211_wake_queue(sc->hw, qnum);
1905 txq->stopped = 0;
1906 }
1907 }
1908 spin_unlock_bh(&txq->axq_lock);
1909 }
1910
1911 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1912 {
1913 struct ath_hw *ah = sc->sc_ah;
1914 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1915 struct list_head bf_head;
1916 struct ath_desc *ds;
1917 int txok;
1918 int status;
1919
1920 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1921 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1922 txq->axq_link);
1923
1924 for (;;) {
1925 spin_lock_bh(&txq->axq_lock);
1926 if (list_empty(&txq->axq_q)) {
1927 txq->axq_link = NULL;
1928 txq->axq_linkbuf = NULL;
1929 spin_unlock_bh(&txq->axq_lock);
1930 break;
1931 }
1932 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1933
1934 /*
1935 * There is a race condition that a BH gets scheduled
1936 * after sw writes TxE and before hw re-load the last
1937 * descriptor to get the newly chained one.
1938 * Software must keep the last DONE descriptor as a
1939 * holding descriptor - software does so by marking
1940 * it with the STALE flag.
1941 */
1942 bf_held = NULL;
1943 if (bf->bf_stale) {
1944 bf_held = bf;
1945 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1946 txq->axq_link = NULL;
1947 txq->axq_linkbuf = NULL;
1948 spin_unlock_bh(&txq->axq_lock);
1949
1950 /*
1951 * The holding descriptor is the last
1952 * descriptor in queue. It's safe to remove
1953 * the last holding descriptor in BH context.
1954 */
1955 spin_lock_bh(&sc->tx.txbuflock);
1956 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1957 spin_unlock_bh(&sc->tx.txbuflock);
1958
1959 break;
1960 } else {
1961 bf = list_entry(bf_held->list.next,
1962 struct ath_buf, list);
1963 }
1964 }
1965
1966 lastbf = bf->bf_lastbf;
1967 ds = lastbf->bf_desc;
1968
1969 status = ath9k_hw_txprocdesc(ah, ds);
1970 if (status == -EINPROGRESS) {
1971 spin_unlock_bh(&txq->axq_lock);
1972 break;
1973 }
1974 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1975 txq->axq_lastdsWithCTS = NULL;
1976 if (ds == txq->axq_gatingds)
1977 txq->axq_gatingds = NULL;
1978
1979 /*
1980 * Remove ath_buf's of the same transmit unit from txq,
1981 * however leave the last descriptor back as the holding
1982 * descriptor for hw.
1983 */
1984 lastbf->bf_stale = true;
1985 INIT_LIST_HEAD(&bf_head);
1986 if (!list_is_singular(&lastbf->list))
1987 list_cut_position(&bf_head,
1988 &txq->axq_q, lastbf->list.prev);
1989
1990 txq->axq_depth--;
1991 if (bf_isaggr(bf))
1992 txq->axq_aggr_depth--;
1993
1994 txok = (ds->ds_txstat.ts_status == 0);
1995 spin_unlock_bh(&txq->axq_lock);
1996
1997 if (bf_held) {
1998 spin_lock_bh(&sc->tx.txbuflock);
1999 list_move_tail(&bf_held->list, &sc->tx.txbuf);
2000 spin_unlock_bh(&sc->tx.txbuflock);
2001 }
2002
2003 if (!bf_isampdu(bf)) {
2004 /*
2005 * This frame is sent out as a single frame.
2006 * Use hardware retry status for this frame.
2007 */
2008 bf->bf_retries = ds->ds_txstat.ts_longretry;
2009 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
2010 bf->bf_state.bf_type |= BUF_XRETRY;
2011 ath_tx_rc_status(bf, ds, 0, txok, true);
2012 }
2013
2014 if (bf_isampdu(bf))
2015 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
2016 else
2017 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
2018
2019 ath_wake_mac80211_queue(sc, txq);
2020
2021 spin_lock_bh(&txq->axq_lock);
2022 if (sc->sc_flags & SC_OP_TXAGGR)
2023 ath_txq_schedule(sc, txq);
2024 spin_unlock_bh(&txq->axq_lock);
2025 }
2026 }
2027
2028
2029 void ath_tx_tasklet(struct ath_softc *sc)
2030 {
2031 int i;
2032 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2033
2034 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2035
2036 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2037 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2038 ath_tx_processq(sc, &sc->tx.txq[i]);
2039 }
2040 }
2041
2042 /*****************/
2043 /* Init, Cleanup */
2044 /*****************/
2045
2046 int ath_tx_init(struct ath_softc *sc, int nbufs)
2047 {
2048 int error = 0;
2049
2050 spin_lock_init(&sc->tx.txbuflock);
2051
2052 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2053 "tx", nbufs, 1);
2054 if (error != 0) {
2055 DPRINTF(sc, ATH_DBG_FATAL,
2056 "Failed to allocate tx descriptors: %d\n", error);
2057 goto err;
2058 }
2059
2060 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2061 "beacon", ATH_BCBUF, 1);
2062 if (error != 0) {
2063 DPRINTF(sc, ATH_DBG_FATAL,
2064 "Failed to allocate beacon descriptors: %d\n", error);
2065 goto err;
2066 }
2067
2068 err:
2069 if (error != 0)
2070 ath_tx_cleanup(sc);
2071
2072 return error;
2073 }
2074
2075 void ath_tx_cleanup(struct ath_softc *sc)
2076 {
2077 if (sc->beacon.bdma.dd_desc_len != 0)
2078 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2079
2080 if (sc->tx.txdma.dd_desc_len != 0)
2081 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2082 }
2083
2084 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2085 {
2086 struct ath_atx_tid *tid;
2087 struct ath_atx_ac *ac;
2088 int tidno, acno;
2089
2090 for (tidno = 0, tid = &an->tid[tidno];
2091 tidno < WME_NUM_TID;
2092 tidno++, tid++) {
2093 tid->an = an;
2094 tid->tidno = tidno;
2095 tid->seq_start = tid->seq_next = 0;
2096 tid->baw_size = WME_MAX_BA;
2097 tid->baw_head = tid->baw_tail = 0;
2098 tid->sched = false;
2099 tid->paused = false;
2100 tid->state &= ~AGGR_CLEANUP;
2101 INIT_LIST_HEAD(&tid->buf_q);
2102 acno = TID_TO_WME_AC(tidno);
2103 tid->ac = &an->ac[acno];
2104 tid->state &= ~AGGR_ADDBA_COMPLETE;
2105 tid->state &= ~AGGR_ADDBA_PROGRESS;
2106 tid->addba_exchangeattempts = 0;
2107 }
2108
2109 for (acno = 0, ac = &an->ac[acno];
2110 acno < WME_NUM_AC; acno++, ac++) {
2111 ac->sched = false;
2112 INIT_LIST_HEAD(&ac->tid_q);
2113
2114 switch (acno) {
2115 case WME_AC_BE:
2116 ac->qnum = ath_tx_get_qnum(sc,
2117 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2118 break;
2119 case WME_AC_BK:
2120 ac->qnum = ath_tx_get_qnum(sc,
2121 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2122 break;
2123 case WME_AC_VI:
2124 ac->qnum = ath_tx_get_qnum(sc,
2125 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2126 break;
2127 case WME_AC_VO:
2128 ac->qnum = ath_tx_get_qnum(sc,
2129 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2130 break;
2131 }
2132 }
2133 }
2134
2135 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2136 {
2137 int i;
2138 struct ath_atx_ac *ac, *ac_tmp;
2139 struct ath_atx_tid *tid, *tid_tmp;
2140 struct ath_txq *txq;
2141
2142 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2143 if (ATH_TXQ_SETUP(sc, i)) {
2144 txq = &sc->tx.txq[i];
2145
2146 spin_lock(&txq->axq_lock);
2147
2148 list_for_each_entry_safe(ac,
2149 ac_tmp, &txq->axq_acq, list) {
2150 tid = list_first_entry(&ac->tid_q,
2151 struct ath_atx_tid, list);
2152 if (tid && tid->an != an)
2153 continue;
2154 list_del(&ac->list);
2155 ac->sched = false;
2156
2157 list_for_each_entry_safe(tid,
2158 tid_tmp, &ac->tid_q, list) {
2159 list_del(&tid->list);
2160 tid->sched = false;
2161 ath_tid_drain(sc, txq, tid);
2162 tid->state &= ~AGGR_ADDBA_COMPLETE;
2163 tid->addba_exchangeattempts = 0;
2164 tid->state &= ~AGGR_CLEANUP;
2165 }
2166 }
2167
2168 spin_unlock(&txq->axq_lock);
2169 }
2170 }
2171 }
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