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[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / ath / ath9k / xmit.c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/dma-mapping.h>
18 #include "ath9k.h"
19 #include "ar9003_mac.h"
20
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
24 #define L_STF 8
25 #define L_LTF 8
26 #define L_SIG 4
27 #define HT_SIG 8
28 #define HT_STF 4
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36
37
38 static u16 bits_per_symbol[][2] = {
39 /* 20MHz 40MHz */
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 };
49
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
61 int txok);
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
63 int seqno);
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
65 struct ath_txq *txq,
66 struct ath_atx_tid *tid,
67 struct sk_buff *skb);
68
69 enum {
70 MCS_HT20,
71 MCS_HT20_SGI,
72 MCS_HT40,
73 MCS_HT40_SGI,
74 };
75
76 /*********************/
77 /* Aggregation logic */
78 /*********************/
79
80 void ath_txq_lock(struct ath_softc *sc, struct ath_txq *txq)
81 __acquires(&txq->axq_lock)
82 {
83 spin_lock_bh(&txq->axq_lock);
84 }
85
86 void ath_txq_unlock(struct ath_softc *sc, struct ath_txq *txq)
87 __releases(&txq->axq_lock)
88 {
89 spin_unlock_bh(&txq->axq_lock);
90 }
91
92 void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
93 __releases(&txq->axq_lock)
94 {
95 struct sk_buff_head q;
96 struct sk_buff *skb;
97
98 __skb_queue_head_init(&q);
99 skb_queue_splice_init(&txq->complete_q, &q);
100 spin_unlock_bh(&txq->axq_lock);
101
102 while ((skb = __skb_dequeue(&q)))
103 ieee80211_tx_status(sc->hw, skb);
104 }
105
106 static void ath_tx_queue_tid(struct ath_softc *sc, struct ath_txq *txq,
107 struct ath_atx_tid *tid)
108 {
109 struct ath_atx_ac *ac = tid->ac;
110 struct list_head *list;
111 struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
112 struct ath_chanctx *ctx = avp->chanctx;
113
114 if (!ctx)
115 return;
116
117 if (tid->sched)
118 return;
119
120 tid->sched = true;
121 list_add_tail(&tid->list, &ac->tid_q);
122
123 if (ac->sched)
124 return;
125
126 ac->sched = true;
127
128 list = &ctx->acq[TID_TO_WME_AC(tid->tidno)];
129 list_add_tail(&ac->list, list);
130 }
131
132 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
133 {
134 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
135 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
136 sizeof(tx_info->rate_driver_data));
137 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
138 }
139
140 static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
141 {
142 if (!tid->an->sta)
143 return;
144
145 ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
146 seqno << IEEE80211_SEQ_SEQ_SHIFT);
147 }
148
149 static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
150 struct ath_buf *bf)
151 {
152 ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
153 ARRAY_SIZE(bf->rates));
154 }
155
156 static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
157 struct sk_buff *skb)
158 {
159 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
160 struct ath_frame_info *fi = get_frame_info(skb);
161 int q = fi->txq;
162
163 if (q < 0)
164 return;
165
166 txq = sc->tx.txq_map[q];
167 if (WARN_ON(--txq->pending_frames < 0))
168 txq->pending_frames = 0;
169
170 if (txq->stopped &&
171 txq->pending_frames < sc->tx.txq_max_pending[q]) {
172 if (ath9k_is_chanctx_enabled())
173 ieee80211_wake_queue(sc->hw, info->hw_queue);
174 else
175 ieee80211_wake_queue(sc->hw, q);
176 txq->stopped = false;
177 }
178 }
179
180 static struct ath_atx_tid *
181 ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
182 {
183 u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
184 return ATH_AN_2_TID(an, tidno);
185 }
186
187 static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
188 {
189 return !skb_queue_empty(&tid->buf_q) || !skb_queue_empty(&tid->retry_q);
190 }
191
192 static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
193 {
194 struct sk_buff *skb;
195
196 skb = __skb_dequeue(&tid->retry_q);
197 if (!skb)
198 skb = __skb_dequeue(&tid->buf_q);
199
200 return skb;
201 }
202
203 /*
204 * ath_tx_tid_change_state:
205 * - clears a-mpdu flag of previous session
206 * - force sequence number allocation to fix next BlockAck Window
207 */
208 static void
209 ath_tx_tid_change_state(struct ath_softc *sc, struct ath_atx_tid *tid)
210 {
211 struct ath_txq *txq = tid->ac->txq;
212 struct ieee80211_tx_info *tx_info;
213 struct sk_buff *skb, *tskb;
214 struct ath_buf *bf;
215 struct ath_frame_info *fi;
216
217 skb_queue_walk_safe(&tid->buf_q, skb, tskb) {
218 fi = get_frame_info(skb);
219 bf = fi->bf;
220
221 tx_info = IEEE80211_SKB_CB(skb);
222 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
223
224 if (bf)
225 continue;
226
227 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
228 if (!bf) {
229 __skb_unlink(skb, &tid->buf_q);
230 ath_txq_skb_done(sc, txq, skb);
231 ieee80211_free_txskb(sc->hw, skb);
232 continue;
233 }
234 }
235
236 }
237
238 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
239 {
240 struct ath_txq *txq = tid->ac->txq;
241 struct sk_buff *skb;
242 struct ath_buf *bf;
243 struct list_head bf_head;
244 struct ath_tx_status ts;
245 struct ath_frame_info *fi;
246 bool sendbar = false;
247
248 INIT_LIST_HEAD(&bf_head);
249
250 memset(&ts, 0, sizeof(ts));
251
252 while ((skb = __skb_dequeue(&tid->retry_q))) {
253 fi = get_frame_info(skb);
254 bf = fi->bf;
255 if (!bf) {
256 ath_txq_skb_done(sc, txq, skb);
257 ieee80211_free_txskb(sc->hw, skb);
258 continue;
259 }
260
261 if (fi->baw_tracked) {
262 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
263 sendbar = true;
264 }
265
266 list_add_tail(&bf->list, &bf_head);
267 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
268 }
269
270 if (sendbar) {
271 ath_txq_unlock(sc, txq);
272 ath_send_bar(tid, tid->seq_start);
273 ath_txq_lock(sc, txq);
274 }
275 }
276
277 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
278 int seqno)
279 {
280 int index, cindex;
281
282 index = ATH_BA_INDEX(tid->seq_start, seqno);
283 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
284
285 __clear_bit(cindex, tid->tx_buf);
286
287 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
288 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
289 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
290 if (tid->bar_index >= 0)
291 tid->bar_index--;
292 }
293 }
294
295 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
296 struct ath_buf *bf)
297 {
298 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
299 u16 seqno = bf->bf_state.seqno;
300 int index, cindex;
301
302 index = ATH_BA_INDEX(tid->seq_start, seqno);
303 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
304 __set_bit(cindex, tid->tx_buf);
305 fi->baw_tracked = 1;
306
307 if (index >= ((tid->baw_tail - tid->baw_head) &
308 (ATH_TID_MAX_BUFS - 1))) {
309 tid->baw_tail = cindex;
310 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
311 }
312 }
313
314 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
315 struct ath_atx_tid *tid)
316
317 {
318 struct sk_buff *skb;
319 struct ath_buf *bf;
320 struct list_head bf_head;
321 struct ath_tx_status ts;
322 struct ath_frame_info *fi;
323
324 memset(&ts, 0, sizeof(ts));
325 INIT_LIST_HEAD(&bf_head);
326
327 while ((skb = ath_tid_dequeue(tid))) {
328 fi = get_frame_info(skb);
329 bf = fi->bf;
330
331 if (!bf) {
332 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
333 continue;
334 }
335
336 list_add_tail(&bf->list, &bf_head);
337 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
338 }
339 }
340
341 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
342 struct sk_buff *skb, int count)
343 {
344 struct ath_frame_info *fi = get_frame_info(skb);
345 struct ath_buf *bf = fi->bf;
346 struct ieee80211_hdr *hdr;
347 int prev = fi->retries;
348
349 TX_STAT_INC(txq->axq_qnum, a_retries);
350 fi->retries += count;
351
352 if (prev > 0)
353 return;
354
355 hdr = (struct ieee80211_hdr *)skb->data;
356 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
357 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
358 sizeof(*hdr), DMA_TO_DEVICE);
359 }
360
361 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
362 {
363 struct ath_buf *bf = NULL;
364
365 spin_lock_bh(&sc->tx.txbuflock);
366
367 if (unlikely(list_empty(&sc->tx.txbuf))) {
368 spin_unlock_bh(&sc->tx.txbuflock);
369 return NULL;
370 }
371
372 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
373 list_del(&bf->list);
374
375 spin_unlock_bh(&sc->tx.txbuflock);
376
377 return bf;
378 }
379
380 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
381 {
382 spin_lock_bh(&sc->tx.txbuflock);
383 list_add_tail(&bf->list, &sc->tx.txbuf);
384 spin_unlock_bh(&sc->tx.txbuflock);
385 }
386
387 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
388 {
389 struct ath_buf *tbf;
390
391 tbf = ath_tx_get_buffer(sc);
392 if (WARN_ON(!tbf))
393 return NULL;
394
395 ATH_TXBUF_RESET(tbf);
396
397 tbf->bf_mpdu = bf->bf_mpdu;
398 tbf->bf_buf_addr = bf->bf_buf_addr;
399 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
400 tbf->bf_state = bf->bf_state;
401 tbf->bf_state.stale = false;
402
403 return tbf;
404 }
405
406 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
407 struct ath_tx_status *ts, int txok,
408 int *nframes, int *nbad)
409 {
410 struct ath_frame_info *fi;
411 u16 seq_st = 0;
412 u32 ba[WME_BA_BMP_SIZE >> 5];
413 int ba_index;
414 int isaggr = 0;
415
416 *nbad = 0;
417 *nframes = 0;
418
419 isaggr = bf_isaggr(bf);
420 if (isaggr) {
421 seq_st = ts->ts_seqnum;
422 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
423 }
424
425 while (bf) {
426 fi = get_frame_info(bf->bf_mpdu);
427 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
428
429 (*nframes)++;
430 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
431 (*nbad)++;
432
433 bf = bf->bf_next;
434 }
435 }
436
437
438 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
439 struct ath_buf *bf, struct list_head *bf_q,
440 struct ath_tx_status *ts, int txok)
441 {
442 struct ath_node *an = NULL;
443 struct sk_buff *skb;
444 struct ieee80211_sta *sta;
445 struct ieee80211_hw *hw = sc->hw;
446 struct ieee80211_hdr *hdr;
447 struct ieee80211_tx_info *tx_info;
448 struct ath_atx_tid *tid = NULL;
449 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
450 struct list_head bf_head;
451 struct sk_buff_head bf_pending;
452 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
453 u32 ba[WME_BA_BMP_SIZE >> 5];
454 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
455 bool rc_update = true, isba;
456 struct ieee80211_tx_rate rates[4];
457 struct ath_frame_info *fi;
458 int nframes;
459 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
460 int i, retries;
461 int bar_index = -1;
462
463 skb = bf->bf_mpdu;
464 hdr = (struct ieee80211_hdr *)skb->data;
465
466 tx_info = IEEE80211_SKB_CB(skb);
467
468 memcpy(rates, bf->rates, sizeof(rates));
469
470 retries = ts->ts_longretry + 1;
471 for (i = 0; i < ts->ts_rateindex; i++)
472 retries += rates[i].count;
473
474 rcu_read_lock();
475
476 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
477 if (!sta) {
478 rcu_read_unlock();
479
480 INIT_LIST_HEAD(&bf_head);
481 while (bf) {
482 bf_next = bf->bf_next;
483
484 if (!bf->bf_state.stale || bf_next != NULL)
485 list_move_tail(&bf->list, &bf_head);
486
487 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts, 0);
488
489 bf = bf_next;
490 }
491 return;
492 }
493
494 an = (struct ath_node *)sta->drv_priv;
495 tid = ath_get_skb_tid(sc, an, skb);
496 seq_first = tid->seq_start;
497 isba = ts->ts_flags & ATH9K_TX_BA;
498
499 /*
500 * The hardware occasionally sends a tx status for the wrong TID.
501 * In this case, the BA status cannot be considered valid and all
502 * subframes need to be retransmitted
503 *
504 * Only BlockAcks have a TID and therefore normal Acks cannot be
505 * checked
506 */
507 if (isba && tid->tidno != ts->tid)
508 txok = false;
509
510 isaggr = bf_isaggr(bf);
511 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
512
513 if (isaggr && txok) {
514 if (ts->ts_flags & ATH9K_TX_BA) {
515 seq_st = ts->ts_seqnum;
516 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
517 } else {
518 /*
519 * AR5416 can become deaf/mute when BA
520 * issue happens. Chip needs to be reset.
521 * But AP code may have sychronization issues
522 * when perform internal reset in this routine.
523 * Only enable reset in STA mode for now.
524 */
525 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
526 needreset = 1;
527 }
528 }
529
530 __skb_queue_head_init(&bf_pending);
531
532 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
533 while (bf) {
534 u16 seqno = bf->bf_state.seqno;
535
536 txfail = txpending = sendbar = 0;
537 bf_next = bf->bf_next;
538
539 skb = bf->bf_mpdu;
540 tx_info = IEEE80211_SKB_CB(skb);
541 fi = get_frame_info(skb);
542
543 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
544 !tid->active) {
545 /*
546 * Outside of the current BlockAck window,
547 * maybe part of a previous session
548 */
549 txfail = 1;
550 } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
551 /* transmit completion, subframe is
552 * acked by block ack */
553 acked_cnt++;
554 } else if (!isaggr && txok) {
555 /* transmit completion */
556 acked_cnt++;
557 } else if (flush) {
558 txpending = 1;
559 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
560 if (txok || !an->sleeping)
561 ath_tx_set_retry(sc, txq, bf->bf_mpdu,
562 retries);
563
564 txpending = 1;
565 } else {
566 txfail = 1;
567 txfail_cnt++;
568 bar_index = max_t(int, bar_index,
569 ATH_BA_INDEX(seq_first, seqno));
570 }
571
572 /*
573 * Make sure the last desc is reclaimed if it
574 * not a holding desc.
575 */
576 INIT_LIST_HEAD(&bf_head);
577 if (bf_next != NULL || !bf_last->bf_state.stale)
578 list_move_tail(&bf->list, &bf_head);
579
580 if (!txpending) {
581 /*
582 * complete the acked-ones/xretried ones; update
583 * block-ack window
584 */
585 ath_tx_update_baw(sc, tid, seqno);
586
587 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
588 memcpy(tx_info->control.rates, rates, sizeof(rates));
589 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
590 rc_update = false;
591 if (bf == bf->bf_lastbf)
592 ath_dynack_sample_tx_ts(sc->sc_ah,
593 bf->bf_mpdu,
594 ts);
595 }
596
597 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
598 !txfail);
599 } else {
600 if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
601 tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
602 ieee80211_sta_eosp(sta);
603 }
604 /* retry the un-acked ones */
605 if (bf->bf_next == NULL && bf_last->bf_state.stale) {
606 struct ath_buf *tbf;
607
608 tbf = ath_clone_txbuf(sc, bf_last);
609 /*
610 * Update tx baw and complete the
611 * frame with failed status if we
612 * run out of tx buf.
613 */
614 if (!tbf) {
615 ath_tx_update_baw(sc, tid, seqno);
616
617 ath_tx_complete_buf(sc, bf, txq,
618 &bf_head, ts, 0);
619 bar_index = max_t(int, bar_index,
620 ATH_BA_INDEX(seq_first, seqno));
621 break;
622 }
623
624 fi->bf = tbf;
625 }
626
627 /*
628 * Put this buffer to the temporary pending
629 * queue to retain ordering
630 */
631 __skb_queue_tail(&bf_pending, skb);
632 }
633
634 bf = bf_next;
635 }
636
637 /* prepend un-acked frames to the beginning of the pending frame queue */
638 if (!skb_queue_empty(&bf_pending)) {
639 if (an->sleeping)
640 ieee80211_sta_set_buffered(sta, tid->tidno, true);
641
642 skb_queue_splice_tail(&bf_pending, &tid->retry_q);
643 if (!an->sleeping) {
644 ath_tx_queue_tid(sc, txq, tid);
645
646 if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
647 tid->ac->clear_ps_filter = true;
648 }
649 }
650
651 if (bar_index >= 0) {
652 u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
653
654 if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
655 tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
656
657 ath_txq_unlock(sc, txq);
658 ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
659 ath_txq_lock(sc, txq);
660 }
661
662 rcu_read_unlock();
663
664 if (needreset)
665 ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
666 }
667
668 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
669 {
670 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
671 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
672 }
673
674 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
675 struct ath_tx_status *ts, struct ath_buf *bf,
676 struct list_head *bf_head)
677 {
678 struct ieee80211_tx_info *info;
679 bool txok, flush;
680
681 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
682 flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
683 txq->axq_tx_inprogress = false;
684
685 txq->axq_depth--;
686 if (bf_is_ampdu_not_probing(bf))
687 txq->axq_ampdu_depth--;
688
689 ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
690 ts->ts_rateindex);
691 if (!bf_isampdu(bf)) {
692 if (!flush) {
693 info = IEEE80211_SKB_CB(bf->bf_mpdu);
694 memcpy(info->control.rates, bf->rates,
695 sizeof(info->control.rates));
696 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
697 ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts);
698 }
699 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok);
700 } else
701 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok);
702
703 if (!flush)
704 ath_txq_schedule(sc, txq);
705 }
706
707 static bool ath_lookup_legacy(struct ath_buf *bf)
708 {
709 struct sk_buff *skb;
710 struct ieee80211_tx_info *tx_info;
711 struct ieee80211_tx_rate *rates;
712 int i;
713
714 skb = bf->bf_mpdu;
715 tx_info = IEEE80211_SKB_CB(skb);
716 rates = tx_info->control.rates;
717
718 for (i = 0; i < 4; i++) {
719 if (!rates[i].count || rates[i].idx < 0)
720 break;
721
722 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
723 return true;
724 }
725
726 return false;
727 }
728
729 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
730 struct ath_atx_tid *tid)
731 {
732 struct sk_buff *skb;
733 struct ieee80211_tx_info *tx_info;
734 struct ieee80211_tx_rate *rates;
735 u32 max_4ms_framelen, frmlen;
736 u16 aggr_limit, bt_aggr_limit, legacy = 0;
737 int q = tid->ac->txq->mac80211_qnum;
738 int i;
739
740 skb = bf->bf_mpdu;
741 tx_info = IEEE80211_SKB_CB(skb);
742 rates = bf->rates;
743
744 /*
745 * Find the lowest frame length among the rate series that will have a
746 * 4ms (or TXOP limited) transmit duration.
747 */
748 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
749
750 for (i = 0; i < 4; i++) {
751 int modeidx;
752
753 if (!rates[i].count)
754 continue;
755
756 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
757 legacy = 1;
758 break;
759 }
760
761 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
762 modeidx = MCS_HT40;
763 else
764 modeidx = MCS_HT20;
765
766 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
767 modeidx++;
768
769 frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
770 max_4ms_framelen = min(max_4ms_framelen, frmlen);
771 }
772
773 /*
774 * limit aggregate size by the minimum rate if rate selected is
775 * not a probe rate, if rate selected is a probe rate then
776 * avoid aggregation of this packet.
777 */
778 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
779 return 0;
780
781 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
782
783 /*
784 * Override the default aggregation limit for BTCOEX.
785 */
786 bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
787 if (bt_aggr_limit)
788 aggr_limit = bt_aggr_limit;
789
790 if (tid->an->maxampdu)
791 aggr_limit = min(aggr_limit, tid->an->maxampdu);
792
793 return aggr_limit;
794 }
795
796 /*
797 * Returns the number of delimiters to be added to
798 * meet the minimum required mpdudensity.
799 */
800 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
801 struct ath_buf *bf, u16 frmlen,
802 bool first_subfrm)
803 {
804 #define FIRST_DESC_NDELIMS 60
805 u32 nsymbits, nsymbols;
806 u16 minlen;
807 u8 flags, rix;
808 int width, streams, half_gi, ndelim, mindelim;
809 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
810
811 /* Select standard number of delimiters based on frame length alone */
812 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
813
814 /*
815 * If encryption enabled, hardware requires some more padding between
816 * subframes.
817 * TODO - this could be improved to be dependent on the rate.
818 * The hardware can keep up at lower rates, but not higher rates
819 */
820 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
821 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
822 ndelim += ATH_AGGR_ENCRYPTDELIM;
823
824 /*
825 * Add delimiter when using RTS/CTS with aggregation
826 * and non enterprise AR9003 card
827 */
828 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
829 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
830 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
831
832 /*
833 * Convert desired mpdu density from microeconds to bytes based
834 * on highest rate in rate series (i.e. first rate) to determine
835 * required minimum length for subframe. Take into account
836 * whether high rate is 20 or 40Mhz and half or full GI.
837 *
838 * If there is no mpdu density restriction, no further calculation
839 * is needed.
840 */
841
842 if (tid->an->mpdudensity == 0)
843 return ndelim;
844
845 rix = bf->rates[0].idx;
846 flags = bf->rates[0].flags;
847 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
848 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
849
850 if (half_gi)
851 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
852 else
853 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
854
855 if (nsymbols == 0)
856 nsymbols = 1;
857
858 streams = HT_RC_2_STREAMS(rix);
859 nsymbits = bits_per_symbol[rix % 8][width] * streams;
860 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
861
862 if (frmlen < minlen) {
863 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
864 ndelim = max(mindelim, ndelim);
865 }
866
867 return ndelim;
868 }
869
870 static struct ath_buf *
871 ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
872 struct ath_atx_tid *tid, struct sk_buff_head **q)
873 {
874 struct ieee80211_tx_info *tx_info;
875 struct ath_frame_info *fi;
876 struct sk_buff *skb;
877 struct ath_buf *bf;
878 u16 seqno;
879
880 while (1) {
881 *q = &tid->retry_q;
882 if (skb_queue_empty(*q))
883 *q = &tid->buf_q;
884
885 skb = skb_peek(*q);
886 if (!skb)
887 break;
888
889 fi = get_frame_info(skb);
890 bf = fi->bf;
891 if (!fi->bf)
892 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
893 else
894 bf->bf_state.stale = false;
895
896 if (!bf) {
897 __skb_unlink(skb, *q);
898 ath_txq_skb_done(sc, txq, skb);
899 ieee80211_free_txskb(sc->hw, skb);
900 continue;
901 }
902
903 bf->bf_next = NULL;
904 bf->bf_lastbf = bf;
905
906 tx_info = IEEE80211_SKB_CB(skb);
907 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
908
909 /*
910 * No aggregation session is running, but there may be frames
911 * from a previous session or a failed attempt in the queue.
912 * Send them out as normal data frames
913 */
914 if (!tid->active)
915 tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
916
917 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
918 bf->bf_state.bf_type = 0;
919 return bf;
920 }
921
922 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
923 seqno = bf->bf_state.seqno;
924
925 /* do not step over block-ack window */
926 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno))
927 break;
928
929 if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
930 struct ath_tx_status ts = {};
931 struct list_head bf_head;
932
933 INIT_LIST_HEAD(&bf_head);
934 list_add(&bf->list, &bf_head);
935 __skb_unlink(skb, *q);
936 ath_tx_update_baw(sc, tid, seqno);
937 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
938 continue;
939 }
940
941 return bf;
942 }
943
944 return NULL;
945 }
946
947 static bool
948 ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
949 struct ath_atx_tid *tid, struct list_head *bf_q,
950 struct ath_buf *bf_first, struct sk_buff_head *tid_q,
951 int *aggr_len)
952 {
953 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
954 struct ath_buf *bf = bf_first, *bf_prev = NULL;
955 int nframes = 0, ndelim;
956 u16 aggr_limit = 0, al = 0, bpad = 0,
957 al_delta, h_baw = tid->baw_size / 2;
958 struct ieee80211_tx_info *tx_info;
959 struct ath_frame_info *fi;
960 struct sk_buff *skb;
961 bool closed = false;
962
963 bf = bf_first;
964 aggr_limit = ath_lookup_rate(sc, bf, tid);
965
966 do {
967 skb = bf->bf_mpdu;
968 fi = get_frame_info(skb);
969
970 /* do not exceed aggregation limit */
971 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
972 if (nframes) {
973 if (aggr_limit < al + bpad + al_delta ||
974 ath_lookup_legacy(bf) || nframes >= h_baw)
975 break;
976
977 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
978 if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
979 !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
980 break;
981 }
982
983 /* add padding for previous frame to aggregation length */
984 al += bpad + al_delta;
985
986 /*
987 * Get the delimiters needed to meet the MPDU
988 * density for this node.
989 */
990 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
991 !nframes);
992 bpad = PADBYTES(al_delta) + (ndelim << 2);
993
994 nframes++;
995 bf->bf_next = NULL;
996
997 /* link buffers of this frame to the aggregate */
998 if (!fi->baw_tracked)
999 ath_tx_addto_baw(sc, tid, bf);
1000 bf->bf_state.ndelim = ndelim;
1001
1002 __skb_unlink(skb, tid_q);
1003 list_add_tail(&bf->list, bf_q);
1004 if (bf_prev)
1005 bf_prev->bf_next = bf;
1006
1007 bf_prev = bf;
1008
1009 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1010 if (!bf) {
1011 closed = true;
1012 break;
1013 }
1014 } while (ath_tid_has_buffered(tid));
1015
1016 bf = bf_first;
1017 bf->bf_lastbf = bf_prev;
1018
1019 if (bf == bf_prev) {
1020 al = get_frame_info(bf->bf_mpdu)->framelen;
1021 bf->bf_state.bf_type = BUF_AMPDU;
1022 } else {
1023 TX_STAT_INC(txq->axq_qnum, a_aggr);
1024 }
1025
1026 *aggr_len = al;
1027
1028 return closed;
1029 #undef PADBYTES
1030 }
1031
1032 /*
1033 * rix - rate index
1034 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1035 * width - 0 for 20 MHz, 1 for 40 MHz
1036 * half_gi - to use 4us v/s 3.6 us for symbol time
1037 */
1038 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1039 int width, int half_gi, bool shortPreamble)
1040 {
1041 u32 nbits, nsymbits, duration, nsymbols;
1042 int streams;
1043
1044 /* find number of symbols: PLCP + data */
1045 streams = HT_RC_2_STREAMS(rix);
1046 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1047 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1048 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1049
1050 if (!half_gi)
1051 duration = SYMBOL_TIME(nsymbols);
1052 else
1053 duration = SYMBOL_TIME_HALFGI(nsymbols);
1054
1055 /* addup duration for legacy/ht training and signal fields */
1056 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1057
1058 return duration;
1059 }
1060
1061 static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1062 {
1063 int streams = HT_RC_2_STREAMS(mcs);
1064 int symbols, bits;
1065 int bytes = 0;
1066
1067 usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1068 symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1069 bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1070 bits -= OFDM_PLCP_BITS;
1071 bytes = bits / 8;
1072 if (bytes > 65532)
1073 bytes = 65532;
1074
1075 return bytes;
1076 }
1077
1078 void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1079 {
1080 u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1081 int mcs;
1082
1083 /* 4ms is the default (and maximum) duration */
1084 if (!txop || txop > 4096)
1085 txop = 4096;
1086
1087 cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1088 cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1089 cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1090 cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1091 for (mcs = 0; mcs < 32; mcs++) {
1092 cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1093 cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1094 cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1095 cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1096 }
1097 }
1098
1099 static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1100 u8 rateidx)
1101 {
1102 u8 max_power;
1103 struct ath_hw *ah = sc->sc_ah;
1104
1105 if (sc->tx99_state)
1106 return MAX_RATE_POWER;
1107
1108 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1109 /* ar9002 does not support TPC for the moment */
1110 return MAX_RATE_POWER;
1111 }
1112
1113 if (!bf->bf_state.bfs_paprd) {
1114 struct sk_buff *skb = bf->bf_mpdu;
1115 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1116 struct ath_frame_info *fi = get_frame_info(skb);
1117
1118 if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1119 max_power = min(ah->tx_power_stbc[rateidx],
1120 fi->tx_power);
1121 else
1122 max_power = min(ah->tx_power[rateidx], fi->tx_power);
1123 } else {
1124 max_power = ah->paprd_training_power;
1125 }
1126
1127 return max_power;
1128 }
1129
1130 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1131 struct ath_tx_info *info, int len, bool rts)
1132 {
1133 struct ath_hw *ah = sc->sc_ah;
1134 struct ath_common *common = ath9k_hw_common(ah);
1135 struct sk_buff *skb;
1136 struct ieee80211_tx_info *tx_info;
1137 struct ieee80211_tx_rate *rates;
1138 const struct ieee80211_rate *rate;
1139 struct ieee80211_hdr *hdr;
1140 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1141 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1142 int i;
1143 u8 rix = 0;
1144
1145 skb = bf->bf_mpdu;
1146 tx_info = IEEE80211_SKB_CB(skb);
1147 rates = bf->rates;
1148 hdr = (struct ieee80211_hdr *)skb->data;
1149
1150 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1151 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1152 info->rtscts_rate = fi->rtscts_rate;
1153
1154 for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1155 bool is_40, is_sgi, is_sp;
1156 int phy;
1157
1158 if (!rates[i].count || (rates[i].idx < 0))
1159 continue;
1160
1161 rix = rates[i].idx;
1162 info->rates[i].Tries = rates[i].count;
1163
1164 /*
1165 * Handle RTS threshold for unaggregated HT frames.
1166 */
1167 if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1168 (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1169 unlikely(rts_thresh != (u32) -1)) {
1170 if (!rts_thresh || (len > rts_thresh))
1171 rts = true;
1172 }
1173
1174 if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1175 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1176 info->flags |= ATH9K_TXDESC_RTSENA;
1177 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1178 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1179 info->flags |= ATH9K_TXDESC_CTSENA;
1180 }
1181
1182 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1183 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1184 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1185 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1186
1187 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1188 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1189 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1190
1191 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1192 /* MCS rates */
1193 info->rates[i].Rate = rix | 0x80;
1194 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1195 ah->txchainmask, info->rates[i].Rate);
1196 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1197 is_40, is_sgi, is_sp);
1198 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1199 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1200
1201 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix);
1202 continue;
1203 }
1204
1205 /* legacy rates */
1206 rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1207 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1208 !(rate->flags & IEEE80211_RATE_ERP_G))
1209 phy = WLAN_RC_PHY_CCK;
1210 else
1211 phy = WLAN_RC_PHY_OFDM;
1212
1213 info->rates[i].Rate = rate->hw_value;
1214 if (rate->hw_value_short) {
1215 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1216 info->rates[i].Rate |= rate->hw_value_short;
1217 } else {
1218 is_sp = false;
1219 }
1220
1221 if (bf->bf_state.bfs_paprd)
1222 info->rates[i].ChSel = ah->txchainmask;
1223 else
1224 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1225 ah->txchainmask, info->rates[i].Rate);
1226
1227 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1228 phy, rate->bitrate * 100, len, rix, is_sp);
1229
1230 info->txpower[i] = ath_get_rate_txpower(sc, bf, rix);
1231 }
1232
1233 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1234 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1235 info->flags &= ~ATH9K_TXDESC_RTSENA;
1236
1237 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1238 if (info->flags & ATH9K_TXDESC_RTSENA)
1239 info->flags &= ~ATH9K_TXDESC_CTSENA;
1240 }
1241
1242 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1243 {
1244 struct ieee80211_hdr *hdr;
1245 enum ath9k_pkt_type htype;
1246 __le16 fc;
1247
1248 hdr = (struct ieee80211_hdr *)skb->data;
1249 fc = hdr->frame_control;
1250
1251 if (ieee80211_is_beacon(fc))
1252 htype = ATH9K_PKT_TYPE_BEACON;
1253 else if (ieee80211_is_probe_resp(fc))
1254 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1255 else if (ieee80211_is_atim(fc))
1256 htype = ATH9K_PKT_TYPE_ATIM;
1257 else if (ieee80211_is_pspoll(fc))
1258 htype = ATH9K_PKT_TYPE_PSPOLL;
1259 else
1260 htype = ATH9K_PKT_TYPE_NORMAL;
1261
1262 return htype;
1263 }
1264
1265 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1266 struct ath_txq *txq, int len)
1267 {
1268 struct ath_hw *ah = sc->sc_ah;
1269 struct ath_buf *bf_first = NULL;
1270 struct ath_tx_info info;
1271 u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1272 bool rts = false;
1273
1274 memset(&info, 0, sizeof(info));
1275 info.is_first = true;
1276 info.is_last = true;
1277 info.qcu = txq->axq_qnum;
1278
1279 while (bf) {
1280 struct sk_buff *skb = bf->bf_mpdu;
1281 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1282 struct ath_frame_info *fi = get_frame_info(skb);
1283 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1284
1285 info.type = get_hw_packet_type(skb);
1286 if (bf->bf_next)
1287 info.link = bf->bf_next->bf_daddr;
1288 else
1289 info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1290
1291 if (!bf_first) {
1292 bf_first = bf;
1293
1294 if (!sc->tx99_state)
1295 info.flags = ATH9K_TXDESC_INTREQ;
1296 if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1297 txq == sc->tx.uapsdq)
1298 info.flags |= ATH9K_TXDESC_CLRDMASK;
1299
1300 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1301 info.flags |= ATH9K_TXDESC_NOACK;
1302 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1303 info.flags |= ATH9K_TXDESC_LDPC;
1304
1305 if (bf->bf_state.bfs_paprd)
1306 info.flags |= (u32) bf->bf_state.bfs_paprd <<
1307 ATH9K_TXDESC_PAPRD_S;
1308
1309 /*
1310 * mac80211 doesn't handle RTS threshold for HT because
1311 * the decision has to be taken based on AMPDU length
1312 * and aggregation is done entirely inside ath9k.
1313 * Set the RTS/CTS flag for the first subframe based
1314 * on the threshold.
1315 */
1316 if (aggr && (bf == bf_first) &&
1317 unlikely(rts_thresh != (u32) -1)) {
1318 /*
1319 * "len" is the size of the entire AMPDU.
1320 */
1321 if (!rts_thresh || (len > rts_thresh))
1322 rts = true;
1323 }
1324
1325 if (!aggr)
1326 len = fi->framelen;
1327
1328 ath_buf_set_rate(sc, bf, &info, len, rts);
1329 }
1330
1331 info.buf_addr[0] = bf->bf_buf_addr;
1332 info.buf_len[0] = skb->len;
1333 info.pkt_len = fi->framelen;
1334 info.keyix = fi->keyix;
1335 info.keytype = fi->keytype;
1336
1337 if (aggr) {
1338 if (bf == bf_first)
1339 info.aggr = AGGR_BUF_FIRST;
1340 else if (bf == bf_first->bf_lastbf)
1341 info.aggr = AGGR_BUF_LAST;
1342 else
1343 info.aggr = AGGR_BUF_MIDDLE;
1344
1345 info.ndelim = bf->bf_state.ndelim;
1346 info.aggr_len = len;
1347 }
1348
1349 if (bf == bf_first->bf_lastbf)
1350 bf_first = NULL;
1351
1352 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1353 bf = bf->bf_next;
1354 }
1355 }
1356
1357 static void
1358 ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1359 struct ath_atx_tid *tid, struct list_head *bf_q,
1360 struct ath_buf *bf_first, struct sk_buff_head *tid_q)
1361 {
1362 struct ath_buf *bf = bf_first, *bf_prev = NULL;
1363 struct sk_buff *skb;
1364 int nframes = 0;
1365
1366 do {
1367 struct ieee80211_tx_info *tx_info;
1368 skb = bf->bf_mpdu;
1369
1370 nframes++;
1371 __skb_unlink(skb, tid_q);
1372 list_add_tail(&bf->list, bf_q);
1373 if (bf_prev)
1374 bf_prev->bf_next = bf;
1375 bf_prev = bf;
1376
1377 if (nframes >= 2)
1378 break;
1379
1380 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1381 if (!bf)
1382 break;
1383
1384 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1385 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU)
1386 break;
1387
1388 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1389 } while (1);
1390 }
1391
1392 static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1393 struct ath_atx_tid *tid, bool *stop)
1394 {
1395 struct ath_buf *bf;
1396 struct ieee80211_tx_info *tx_info;
1397 struct sk_buff_head *tid_q;
1398 struct list_head bf_q;
1399 int aggr_len = 0;
1400 bool aggr, last = true;
1401
1402 if (!ath_tid_has_buffered(tid))
1403 return false;
1404
1405 INIT_LIST_HEAD(&bf_q);
1406
1407 bf = ath_tx_get_tid_subframe(sc, txq, tid, &tid_q);
1408 if (!bf)
1409 return false;
1410
1411 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1412 aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1413 if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1414 (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1415 *stop = true;
1416 return false;
1417 }
1418
1419 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1420 if (aggr)
1421 last = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf,
1422 tid_q, &aggr_len);
1423 else
1424 ath_tx_form_burst(sc, txq, tid, &bf_q, bf, tid_q);
1425
1426 if (list_empty(&bf_q))
1427 return false;
1428
1429 if (tid->ac->clear_ps_filter || tid->an->no_ps_filter) {
1430 tid->ac->clear_ps_filter = false;
1431 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1432 }
1433
1434 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1435 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1436 return true;
1437 }
1438
1439 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1440 u16 tid, u16 *ssn)
1441 {
1442 struct ath_atx_tid *txtid;
1443 struct ath_txq *txq;
1444 struct ath_node *an;
1445 u8 density;
1446
1447 an = (struct ath_node *)sta->drv_priv;
1448 txtid = ATH_AN_2_TID(an, tid);
1449 txq = txtid->ac->txq;
1450
1451 ath_txq_lock(sc, txq);
1452
1453 /* update ampdu factor/density, they may have changed. This may happen
1454 * in HT IBSS when a beacon with HT-info is received after the station
1455 * has already been added.
1456 */
1457 if (sta->ht_cap.ht_supported) {
1458 an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1459 sta->ht_cap.ampdu_factor)) - 1;
1460 density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1461 an->mpdudensity = density;
1462 }
1463
1464 /* force sequence number allocation for pending frames */
1465 ath_tx_tid_change_state(sc, txtid);
1466
1467 txtid->active = true;
1468 *ssn = txtid->seq_start = txtid->seq_next;
1469 txtid->bar_index = -1;
1470
1471 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1472 txtid->baw_head = txtid->baw_tail = 0;
1473
1474 ath_txq_unlock_complete(sc, txq);
1475
1476 return 0;
1477 }
1478
1479 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1480 {
1481 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1482 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1483 struct ath_txq *txq = txtid->ac->txq;
1484
1485 ath_txq_lock(sc, txq);
1486 txtid->active = false;
1487 ath_tx_flush_tid(sc, txtid);
1488 ath_tx_tid_change_state(sc, txtid);
1489 ath_txq_unlock_complete(sc, txq);
1490 }
1491
1492 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1493 struct ath_node *an)
1494 {
1495 struct ath_atx_tid *tid;
1496 struct ath_atx_ac *ac;
1497 struct ath_txq *txq;
1498 bool buffered;
1499 int tidno;
1500
1501 for (tidno = 0, tid = &an->tid[tidno];
1502 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1503
1504 ac = tid->ac;
1505 txq = ac->txq;
1506
1507 ath_txq_lock(sc, txq);
1508
1509 if (!tid->sched) {
1510 ath_txq_unlock(sc, txq);
1511 continue;
1512 }
1513
1514 buffered = ath_tid_has_buffered(tid);
1515
1516 tid->sched = false;
1517 list_del(&tid->list);
1518
1519 if (ac->sched) {
1520 ac->sched = false;
1521 list_del(&ac->list);
1522 }
1523
1524 ath_txq_unlock(sc, txq);
1525
1526 ieee80211_sta_set_buffered(sta, tidno, buffered);
1527 }
1528 }
1529
1530 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1531 {
1532 struct ath_atx_tid *tid;
1533 struct ath_atx_ac *ac;
1534 struct ath_txq *txq;
1535 int tidno;
1536
1537 for (tidno = 0, tid = &an->tid[tidno];
1538 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
1539
1540 ac = tid->ac;
1541 txq = ac->txq;
1542
1543 ath_txq_lock(sc, txq);
1544 ac->clear_ps_filter = true;
1545
1546 if (ath_tid_has_buffered(tid)) {
1547 ath_tx_queue_tid(sc, txq, tid);
1548 ath_txq_schedule(sc, txq);
1549 }
1550
1551 ath_txq_unlock_complete(sc, txq);
1552 }
1553 }
1554
1555 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
1556 u16 tidno)
1557 {
1558 struct ath_atx_tid *tid;
1559 struct ath_node *an;
1560 struct ath_txq *txq;
1561
1562 an = (struct ath_node *)sta->drv_priv;
1563 tid = ATH_AN_2_TID(an, tidno);
1564 txq = tid->ac->txq;
1565
1566 ath_txq_lock(sc, txq);
1567
1568 tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1569
1570 if (ath_tid_has_buffered(tid)) {
1571 ath_tx_queue_tid(sc, txq, tid);
1572 ath_txq_schedule(sc, txq);
1573 }
1574
1575 ath_txq_unlock_complete(sc, txq);
1576 }
1577
1578 void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1579 struct ieee80211_sta *sta,
1580 u16 tids, int nframes,
1581 enum ieee80211_frame_release_type reason,
1582 bool more_data)
1583 {
1584 struct ath_softc *sc = hw->priv;
1585 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1586 struct ath_txq *txq = sc->tx.uapsdq;
1587 struct ieee80211_tx_info *info;
1588 struct list_head bf_q;
1589 struct ath_buf *bf_tail = NULL, *bf;
1590 struct sk_buff_head *tid_q;
1591 int sent = 0;
1592 int i;
1593
1594 INIT_LIST_HEAD(&bf_q);
1595 for (i = 0; tids && nframes; i++, tids >>= 1) {
1596 struct ath_atx_tid *tid;
1597
1598 if (!(tids & 1))
1599 continue;
1600
1601 tid = ATH_AN_2_TID(an, i);
1602
1603 ath_txq_lock(sc, tid->ac->txq);
1604 while (nframes > 0) {
1605 bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid, &tid_q);
1606 if (!bf)
1607 break;
1608
1609 __skb_unlink(bf->bf_mpdu, tid_q);
1610 list_add_tail(&bf->list, &bf_q);
1611 ath_set_rates(tid->an->vif, tid->an->sta, bf);
1612 if (bf_isampdu(bf)) {
1613 ath_tx_addto_baw(sc, tid, bf);
1614 bf->bf_state.bf_type &= ~BUF_AGGR;
1615 }
1616 if (bf_tail)
1617 bf_tail->bf_next = bf;
1618
1619 bf_tail = bf;
1620 nframes--;
1621 sent++;
1622 TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1623
1624 if (an->sta && !ath_tid_has_buffered(tid))
1625 ieee80211_sta_set_buffered(an->sta, i, false);
1626 }
1627 ath_txq_unlock_complete(sc, tid->ac->txq);
1628 }
1629
1630 if (list_empty(&bf_q))
1631 return;
1632
1633 info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1634 info->flags |= IEEE80211_TX_STATUS_EOSP;
1635
1636 bf = list_first_entry(&bf_q, struct ath_buf, list);
1637 ath_txq_lock(sc, txq);
1638 ath_tx_fill_desc(sc, bf, txq, 0);
1639 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1640 ath_txq_unlock(sc, txq);
1641 }
1642
1643 /********************/
1644 /* Queue Management */
1645 /********************/
1646
1647 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1648 {
1649 struct ath_hw *ah = sc->sc_ah;
1650 struct ath9k_tx_queue_info qi;
1651 static const int subtype_txq_to_hwq[] = {
1652 [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1653 [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1654 [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1655 [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1656 };
1657 int axq_qnum, i;
1658
1659 memset(&qi, 0, sizeof(qi));
1660 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1661 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1662 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1663 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1664 qi.tqi_physCompBuf = 0;
1665
1666 /*
1667 * Enable interrupts only for EOL and DESC conditions.
1668 * We mark tx descriptors to receive a DESC interrupt
1669 * when a tx queue gets deep; otherwise waiting for the
1670 * EOL to reap descriptors. Note that this is done to
1671 * reduce interrupt load and this only defers reaping
1672 * descriptors, never transmitting frames. Aside from
1673 * reducing interrupts this also permits more concurrency.
1674 * The only potential downside is if the tx queue backs
1675 * up in which case the top half of the kernel may backup
1676 * due to a lack of tx descriptors.
1677 *
1678 * The UAPSD queue is an exception, since we take a desc-
1679 * based intr on the EOSP frames.
1680 */
1681 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1682 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1683 } else {
1684 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1685 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1686 else
1687 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1688 TXQ_FLAG_TXDESCINT_ENABLE;
1689 }
1690 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1691 if (axq_qnum == -1) {
1692 /*
1693 * NB: don't print a message, this happens
1694 * normally on parts with too few tx queues
1695 */
1696 return NULL;
1697 }
1698 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1699 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1700
1701 txq->axq_qnum = axq_qnum;
1702 txq->mac80211_qnum = -1;
1703 txq->axq_link = NULL;
1704 __skb_queue_head_init(&txq->complete_q);
1705 INIT_LIST_HEAD(&txq->axq_q);
1706 spin_lock_init(&txq->axq_lock);
1707 txq->axq_depth = 0;
1708 txq->axq_ampdu_depth = 0;
1709 txq->axq_tx_inprogress = false;
1710 sc->tx.txqsetup |= 1<<axq_qnum;
1711
1712 txq->txq_headidx = txq->txq_tailidx = 0;
1713 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1714 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1715 }
1716 return &sc->tx.txq[axq_qnum];
1717 }
1718
1719 int ath_txq_update(struct ath_softc *sc, int qnum,
1720 struct ath9k_tx_queue_info *qinfo)
1721 {
1722 struct ath_hw *ah = sc->sc_ah;
1723 int error = 0;
1724 struct ath9k_tx_queue_info qi;
1725
1726 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1727
1728 ath9k_hw_get_txq_props(ah, qnum, &qi);
1729 qi.tqi_aifs = qinfo->tqi_aifs;
1730 qi.tqi_cwmin = qinfo->tqi_cwmin;
1731 qi.tqi_cwmax = qinfo->tqi_cwmax;
1732 qi.tqi_burstTime = qinfo->tqi_burstTime;
1733 qi.tqi_readyTime = qinfo->tqi_readyTime;
1734
1735 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1736 ath_err(ath9k_hw_common(sc->sc_ah),
1737 "Unable to update hardware queue %u!\n", qnum);
1738 error = -EIO;
1739 } else {
1740 ath9k_hw_resettxqueue(ah, qnum);
1741 }
1742
1743 return error;
1744 }
1745
1746 int ath_cabq_update(struct ath_softc *sc)
1747 {
1748 struct ath9k_tx_queue_info qi;
1749 struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1750 int qnum = sc->beacon.cabq->axq_qnum;
1751
1752 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1753
1754 qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1755 ATH_CABQ_READY_TIME) / 100;
1756 ath_txq_update(sc, qnum, &qi);
1757
1758 return 0;
1759 }
1760
1761 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1762 struct list_head *list)
1763 {
1764 struct ath_buf *bf, *lastbf;
1765 struct list_head bf_head;
1766 struct ath_tx_status ts;
1767
1768 memset(&ts, 0, sizeof(ts));
1769 ts.ts_status = ATH9K_TX_FLUSH;
1770 INIT_LIST_HEAD(&bf_head);
1771
1772 while (!list_empty(list)) {
1773 bf = list_first_entry(list, struct ath_buf, list);
1774
1775 if (bf->bf_state.stale) {
1776 list_del(&bf->list);
1777
1778 ath_tx_return_buffer(sc, bf);
1779 continue;
1780 }
1781
1782 lastbf = bf->bf_lastbf;
1783 list_cut_position(&bf_head, list, &lastbf->list);
1784 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1785 }
1786 }
1787
1788 /*
1789 * Drain a given TX queue (could be Beacon or Data)
1790 *
1791 * This assumes output has been stopped and
1792 * we do not need to block ath_tx_tasklet.
1793 */
1794 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1795 {
1796 ath_txq_lock(sc, txq);
1797
1798 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1799 int idx = txq->txq_tailidx;
1800
1801 while (!list_empty(&txq->txq_fifo[idx])) {
1802 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1803
1804 INCR(idx, ATH_TXFIFO_DEPTH);
1805 }
1806 txq->txq_tailidx = idx;
1807 }
1808
1809 txq->axq_link = NULL;
1810 txq->axq_tx_inprogress = false;
1811 ath_drain_txq_list(sc, txq, &txq->axq_q);
1812
1813 ath_txq_unlock_complete(sc, txq);
1814 }
1815
1816 bool ath_drain_all_txq(struct ath_softc *sc)
1817 {
1818 struct ath_hw *ah = sc->sc_ah;
1819 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1820 struct ath_txq *txq;
1821 int i;
1822 u32 npend = 0;
1823
1824 if (test_bit(ATH_OP_INVALID, &common->op_flags))
1825 return true;
1826
1827 ath9k_hw_abort_tx_dma(ah);
1828
1829 /* Check if any queue remains active */
1830 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1831 if (!ATH_TXQ_SETUP(sc, i))
1832 continue;
1833
1834 if (!sc->tx.txq[i].axq_depth)
1835 continue;
1836
1837 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1838 npend |= BIT(i);
1839 }
1840
1841 if (npend)
1842 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1843
1844 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1845 if (!ATH_TXQ_SETUP(sc, i))
1846 continue;
1847
1848 /*
1849 * The caller will resume queues with ieee80211_wake_queues.
1850 * Mark the queue as not stopped to prevent ath_tx_complete
1851 * from waking the queue too early.
1852 */
1853 txq = &sc->tx.txq[i];
1854 txq->stopped = false;
1855 ath_draintxq(sc, txq);
1856 }
1857
1858 return !npend;
1859 }
1860
1861 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1862 {
1863 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1864 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1865 }
1866
1867 /* For each acq entry, for each tid, try to schedule packets
1868 * for transmit until ampdu_depth has reached min Q depth.
1869 */
1870 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1871 {
1872 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1873 struct ath_atx_ac *ac, *last_ac;
1874 struct ath_atx_tid *tid, *last_tid;
1875 struct list_head *ac_list;
1876 bool sent = false;
1877
1878 if (txq->mac80211_qnum < 0)
1879 return;
1880
1881 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1882 return;
1883
1884 spin_lock_bh(&sc->chan_lock);
1885 ac_list = &sc->cur_chan->acq[txq->mac80211_qnum];
1886
1887 if (list_empty(ac_list)) {
1888 spin_unlock_bh(&sc->chan_lock);
1889 return;
1890 }
1891
1892 rcu_read_lock();
1893
1894 last_ac = list_entry(ac_list->prev, struct ath_atx_ac, list);
1895 while (!list_empty(ac_list)) {
1896 bool stop = false;
1897
1898 if (sc->cur_chan->stopped)
1899 break;
1900
1901 ac = list_first_entry(ac_list, struct ath_atx_ac, list);
1902 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1903 list_del(&ac->list);
1904 ac->sched = false;
1905
1906 while (!list_empty(&ac->tid_q)) {
1907
1908 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1909 list);
1910 list_del(&tid->list);
1911 tid->sched = false;
1912
1913 if (ath_tx_sched_aggr(sc, txq, tid, &stop))
1914 sent = true;
1915
1916 /*
1917 * add tid to round-robin queue if more frames
1918 * are pending for the tid
1919 */
1920 if (ath_tid_has_buffered(tid))
1921 ath_tx_queue_tid(sc, txq, tid);
1922
1923 if (stop || tid == last_tid)
1924 break;
1925 }
1926
1927 if (!list_empty(&ac->tid_q) && !ac->sched) {
1928 ac->sched = true;
1929 list_add_tail(&ac->list, ac_list);
1930 }
1931
1932 if (stop)
1933 break;
1934
1935 if (ac == last_ac) {
1936 if (!sent)
1937 break;
1938
1939 sent = false;
1940 last_ac = list_entry(ac_list->prev,
1941 struct ath_atx_ac, list);
1942 }
1943 }
1944
1945 rcu_read_unlock();
1946 spin_unlock_bh(&sc->chan_lock);
1947 }
1948
1949 void ath_txq_schedule_all(struct ath_softc *sc)
1950 {
1951 struct ath_txq *txq;
1952 int i;
1953
1954 for (i = 0; i < IEEE80211_NUM_ACS; i++) {
1955 txq = sc->tx.txq_map[i];
1956
1957 spin_lock_bh(&txq->axq_lock);
1958 ath_txq_schedule(sc, txq);
1959 spin_unlock_bh(&txq->axq_lock);
1960 }
1961 }
1962
1963 /***********/
1964 /* TX, DMA */
1965 /***********/
1966
1967 /*
1968 * Insert a chain of ath_buf (descriptors) on a txq and
1969 * assume the descriptors are already chained together by caller.
1970 */
1971 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1972 struct list_head *head, bool internal)
1973 {
1974 struct ath_hw *ah = sc->sc_ah;
1975 struct ath_common *common = ath9k_hw_common(ah);
1976 struct ath_buf *bf, *bf_last;
1977 bool puttxbuf = false;
1978 bool edma;
1979
1980 /*
1981 * Insert the frame on the outbound list and
1982 * pass it on to the hardware.
1983 */
1984
1985 if (list_empty(head))
1986 return;
1987
1988 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1989 bf = list_first_entry(head, struct ath_buf, list);
1990 bf_last = list_entry(head->prev, struct ath_buf, list);
1991
1992 ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
1993 txq->axq_qnum, txq->axq_depth);
1994
1995 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1996 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1997 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1998 puttxbuf = true;
1999 } else {
2000 list_splice_tail_init(head, &txq->axq_q);
2001
2002 if (txq->axq_link) {
2003 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2004 ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2005 txq->axq_qnum, txq->axq_link,
2006 ito64(bf->bf_daddr), bf->bf_desc);
2007 } else if (!edma)
2008 puttxbuf = true;
2009
2010 txq->axq_link = bf_last->bf_desc;
2011 }
2012
2013 if (puttxbuf) {
2014 TX_STAT_INC(txq->axq_qnum, puttxbuf);
2015 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2016 ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2017 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2018 }
2019
2020 if (!edma || sc->tx99_state) {
2021 TX_STAT_INC(txq->axq_qnum, txstart);
2022 ath9k_hw_txstart(ah, txq->axq_qnum);
2023 }
2024
2025 if (!internal) {
2026 while (bf) {
2027 txq->axq_depth++;
2028 if (bf_is_ampdu_not_probing(bf))
2029 txq->axq_ampdu_depth++;
2030
2031 bf_last = bf->bf_lastbf;
2032 bf = bf_last->bf_next;
2033 bf_last->bf_next = NULL;
2034 }
2035 }
2036 }
2037
2038 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2039 struct ath_atx_tid *tid, struct sk_buff *skb)
2040 {
2041 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2042 struct ath_frame_info *fi = get_frame_info(skb);
2043 struct list_head bf_head;
2044 struct ath_buf *bf = fi->bf;
2045
2046 INIT_LIST_HEAD(&bf_head);
2047 list_add_tail(&bf->list, &bf_head);
2048 bf->bf_state.bf_type = 0;
2049 if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2050 bf->bf_state.bf_type = BUF_AMPDU;
2051 ath_tx_addto_baw(sc, tid, bf);
2052 }
2053
2054 bf->bf_next = NULL;
2055 bf->bf_lastbf = bf;
2056 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2057 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2058 TX_STAT_INC(txq->axq_qnum, queued);
2059 }
2060
2061 static void setup_frame_info(struct ieee80211_hw *hw,
2062 struct ieee80211_sta *sta,
2063 struct sk_buff *skb,
2064 int framelen)
2065 {
2066 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2067 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2068 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2069 const struct ieee80211_rate *rate;
2070 struct ath_frame_info *fi = get_frame_info(skb);
2071 struct ath_node *an = NULL;
2072 enum ath9k_key_type keytype;
2073 bool short_preamble = false;
2074
2075 /*
2076 * We check if Short Preamble is needed for the CTS rate by
2077 * checking the BSS's global flag.
2078 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2079 */
2080 if (tx_info->control.vif &&
2081 tx_info->control.vif->bss_conf.use_short_preamble)
2082 short_preamble = true;
2083
2084 rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2085 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2086
2087 if (sta)
2088 an = (struct ath_node *) sta->drv_priv;
2089
2090 memset(fi, 0, sizeof(*fi));
2091 fi->txq = -1;
2092 if (hw_key)
2093 fi->keyix = hw_key->hw_key_idx;
2094 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2095 fi->keyix = an->ps_key;
2096 else
2097 fi->keyix = ATH9K_TXKEYIX_INVALID;
2098 fi->keytype = keytype;
2099 fi->framelen = framelen;
2100 fi->tx_power = MAX_RATE_POWER;
2101
2102 if (!rate)
2103 return;
2104 fi->rtscts_rate = rate->hw_value;
2105 if (short_preamble)
2106 fi->rtscts_rate |= rate->hw_value_short;
2107 }
2108
2109 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2110 {
2111 struct ath_hw *ah = sc->sc_ah;
2112 struct ath9k_channel *curchan = ah->curchan;
2113
2114 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2115 (chainmask == 0x7) && (rate < 0x90))
2116 return 0x3;
2117 else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2118 IS_CCK_RATE(rate))
2119 return 0x2;
2120 else
2121 return chainmask;
2122 }
2123
2124 /*
2125 * Assign a descriptor (and sequence number if necessary,
2126 * and map buffer for DMA. Frees skb on error
2127 */
2128 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2129 struct ath_txq *txq,
2130 struct ath_atx_tid *tid,
2131 struct sk_buff *skb)
2132 {
2133 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2134 struct ath_frame_info *fi = get_frame_info(skb);
2135 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2136 struct ath_buf *bf;
2137 int fragno;
2138 u16 seqno;
2139
2140 bf = ath_tx_get_buffer(sc);
2141 if (!bf) {
2142 ath_dbg(common, XMIT, "TX buffers are full\n");
2143 return NULL;
2144 }
2145
2146 ATH_TXBUF_RESET(bf);
2147
2148 if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2149 fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2150 seqno = tid->seq_next;
2151 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2152
2153 if (fragno)
2154 hdr->seq_ctrl |= cpu_to_le16(fragno);
2155
2156 if (!ieee80211_has_morefrags(hdr->frame_control))
2157 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2158
2159 bf->bf_state.seqno = seqno;
2160 }
2161
2162 bf->bf_mpdu = skb;
2163
2164 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2165 skb->len, DMA_TO_DEVICE);
2166 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2167 bf->bf_mpdu = NULL;
2168 bf->bf_buf_addr = 0;
2169 ath_err(ath9k_hw_common(sc->sc_ah),
2170 "dma_mapping_error() on TX\n");
2171 ath_tx_return_buffer(sc, bf);
2172 return NULL;
2173 }
2174
2175 fi->bf = bf;
2176
2177 return bf;
2178 }
2179
2180 void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2181 {
2182 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2183 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2184 struct ieee80211_vif *vif = info->control.vif;
2185 struct ath_vif *avp;
2186
2187 if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2188 return;
2189
2190 if (!vif)
2191 return;
2192
2193 avp = (struct ath_vif *)vif->drv_priv;
2194
2195 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2196 avp->seq_no += 0x10;
2197
2198 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2199 hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2200 }
2201
2202 static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2203 struct ath_tx_control *txctl)
2204 {
2205 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2206 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2207 struct ieee80211_sta *sta = txctl->sta;
2208 struct ieee80211_vif *vif = info->control.vif;
2209 struct ath_vif *avp;
2210 struct ath_softc *sc = hw->priv;
2211 int frmlen = skb->len + FCS_LEN;
2212 int padpos, padsize;
2213
2214 /* NOTE: sta can be NULL according to net/mac80211.h */
2215 if (sta)
2216 txctl->an = (struct ath_node *)sta->drv_priv;
2217 else if (vif && ieee80211_is_data(hdr->frame_control)) {
2218 avp = (void *)vif->drv_priv;
2219 txctl->an = &avp->mcast_node;
2220 }
2221
2222 if (info->control.hw_key)
2223 frmlen += info->control.hw_key->icv_len;
2224
2225 ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2226
2227 if ((vif && vif->type != NL80211_IFTYPE_AP &&
2228 vif->type != NL80211_IFTYPE_AP_VLAN) ||
2229 !ieee80211_is_data(hdr->frame_control))
2230 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2231
2232 /* Add the padding after the header if this is not already done */
2233 padpos = ieee80211_hdrlen(hdr->frame_control);
2234 padsize = padpos & 3;
2235 if (padsize && skb->len > padpos) {
2236 if (skb_headroom(skb) < padsize)
2237 return -ENOMEM;
2238
2239 skb_push(skb, padsize);
2240 memmove(skb->data, skb->data + padsize, padpos);
2241 }
2242
2243 setup_frame_info(hw, sta, skb, frmlen);
2244 return 0;
2245 }
2246
2247
2248 /* Upon failure caller should free skb */
2249 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2250 struct ath_tx_control *txctl)
2251 {
2252 struct ieee80211_hdr *hdr;
2253 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2254 struct ieee80211_sta *sta = txctl->sta;
2255 struct ieee80211_vif *vif = info->control.vif;
2256 struct ath_frame_info *fi = get_frame_info(skb);
2257 struct ath_vif *avp = NULL;
2258 struct ath_softc *sc = hw->priv;
2259 struct ath_txq *txq = txctl->txq;
2260 struct ath_atx_tid *tid = NULL;
2261 struct ath_buf *bf;
2262 bool queue, skip_uapsd = false, ps_resp;
2263 int q, ret;
2264
2265 if (vif)
2266 avp = (void *)vif->drv_priv;
2267
2268 if (info->flags & IEEE80211_TX_CTL_TX_OFFCHAN)
2269 txctl->force_channel = true;
2270
2271 ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2272
2273 ret = ath_tx_prepare(hw, skb, txctl);
2274 if (ret)
2275 return ret;
2276
2277 hdr = (struct ieee80211_hdr *) skb->data;
2278 /*
2279 * At this point, the vif, hw_key and sta pointers in the tx control
2280 * info are no longer valid (overwritten by the ath_frame_info data.
2281 */
2282
2283 q = skb_get_queue_mapping(skb);
2284
2285 ath_txq_lock(sc, txq);
2286 if (txq == sc->tx.txq_map[q]) {
2287 fi->txq = q;
2288 if (++txq->pending_frames > sc->tx.txq_max_pending[q] &&
2289 !txq->stopped) {
2290 if (ath9k_is_chanctx_enabled())
2291 ieee80211_stop_queue(sc->hw, info->hw_queue);
2292 else
2293 ieee80211_stop_queue(sc->hw, q);
2294 txq->stopped = true;
2295 }
2296 }
2297
2298 queue = ieee80211_is_data_present(hdr->frame_control);
2299
2300 /* Force queueing of all frames that belong to a virtual interface on
2301 * a different channel context, to ensure that they are sent on the
2302 * correct channel.
2303 */
2304 if (((avp && avp->chanctx != sc->cur_chan) ||
2305 sc->cur_chan->stopped) && !txctl->force_channel) {
2306 if (!txctl->an)
2307 txctl->an = &avp->mcast_node;
2308 queue = true;
2309 skip_uapsd = true;
2310 }
2311
2312 if (txctl->an && queue)
2313 tid = ath_get_skb_tid(sc, txctl->an, skb);
2314
2315 if (!skip_uapsd && ps_resp) {
2316 ath_txq_unlock(sc, txq);
2317 txq = sc->tx.uapsdq;
2318 ath_txq_lock(sc, txq);
2319 } else if (txctl->an && queue) {
2320 WARN_ON(tid->ac->txq != txctl->txq);
2321
2322 if (info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
2323 tid->ac->clear_ps_filter = true;
2324
2325 /*
2326 * Add this frame to software queue for scheduling later
2327 * for aggregation.
2328 */
2329 TX_STAT_INC(txq->axq_qnum, a_queued_sw);
2330 __skb_queue_tail(&tid->buf_q, skb);
2331 if (!txctl->an->sleeping)
2332 ath_tx_queue_tid(sc, txq, tid);
2333
2334 ath_txq_schedule(sc, txq);
2335 goto out;
2336 }
2337
2338 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2339 if (!bf) {
2340 ath_txq_skb_done(sc, txq, skb);
2341 if (txctl->paprd)
2342 dev_kfree_skb_any(skb);
2343 else
2344 ieee80211_free_txskb(sc->hw, skb);
2345 goto out;
2346 }
2347
2348 bf->bf_state.bfs_paprd = txctl->paprd;
2349
2350 if (txctl->paprd)
2351 bf->bf_state.bfs_paprd_timestamp = jiffies;
2352
2353 ath_set_rates(vif, sta, bf);
2354 ath_tx_send_normal(sc, txq, tid, skb);
2355
2356 out:
2357 ath_txq_unlock(sc, txq);
2358
2359 return 0;
2360 }
2361
2362 void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2363 struct sk_buff *skb)
2364 {
2365 struct ath_softc *sc = hw->priv;
2366 struct ath_tx_control txctl = {
2367 .txq = sc->beacon.cabq
2368 };
2369 struct ath_tx_info info = {};
2370 struct ieee80211_hdr *hdr;
2371 struct ath_buf *bf_tail = NULL;
2372 struct ath_buf *bf;
2373 LIST_HEAD(bf_q);
2374 int duration = 0;
2375 int max_duration;
2376
2377 max_duration =
2378 sc->cur_chan->beacon.beacon_interval * 1000 *
2379 sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2380
2381 do {
2382 struct ath_frame_info *fi = get_frame_info(skb);
2383
2384 if (ath_tx_prepare(hw, skb, &txctl))
2385 break;
2386
2387 bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2388 if (!bf)
2389 break;
2390
2391 bf->bf_lastbf = bf;
2392 ath_set_rates(vif, NULL, bf);
2393 ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2394 duration += info.rates[0].PktDuration;
2395 if (bf_tail)
2396 bf_tail->bf_next = bf;
2397
2398 list_add_tail(&bf->list, &bf_q);
2399 bf_tail = bf;
2400 skb = NULL;
2401
2402 if (duration > max_duration)
2403 break;
2404
2405 skb = ieee80211_get_buffered_bc(hw, vif);
2406 } while(skb);
2407
2408 if (skb)
2409 ieee80211_free_txskb(hw, skb);
2410
2411 if (list_empty(&bf_q))
2412 return;
2413
2414 bf = list_first_entry(&bf_q, struct ath_buf, list);
2415 hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2416
2417 if (hdr->frame_control & IEEE80211_FCTL_MOREDATA) {
2418 hdr->frame_control &= ~IEEE80211_FCTL_MOREDATA;
2419 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2420 sizeof(*hdr), DMA_TO_DEVICE);
2421 }
2422
2423 ath_txq_lock(sc, txctl.txq);
2424 ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2425 ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2426 TX_STAT_INC(txctl.txq->axq_qnum, queued);
2427 ath_txq_unlock(sc, txctl.txq);
2428 }
2429
2430 /*****************/
2431 /* TX Completion */
2432 /*****************/
2433
2434 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2435 int tx_flags, struct ath_txq *txq)
2436 {
2437 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2438 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2439 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2440 int padpos, padsize;
2441 unsigned long flags;
2442
2443 ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2444
2445 if (sc->sc_ah->caldata)
2446 set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2447
2448 if (!(tx_flags & ATH_TX_ERROR))
2449 /* Frame was ACKed */
2450 tx_info->flags |= IEEE80211_TX_STAT_ACK;
2451
2452 padpos = ieee80211_hdrlen(hdr->frame_control);
2453 padsize = padpos & 3;
2454 if (padsize && skb->len>padpos+padsize) {
2455 /*
2456 * Remove MAC header padding before giving the frame back to
2457 * mac80211.
2458 */
2459 memmove(skb->data + padsize, skb->data, padpos);
2460 skb_pull(skb, padsize);
2461 }
2462
2463 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2464 if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2465 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2466 ath_dbg(common, PS,
2467 "Going back to sleep after having received TX status (0x%lx)\n",
2468 sc->ps_flags & (PS_WAIT_FOR_BEACON |
2469 PS_WAIT_FOR_CAB |
2470 PS_WAIT_FOR_PSPOLL_DATA |
2471 PS_WAIT_FOR_TX_ACK));
2472 }
2473 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2474
2475 __skb_queue_tail(&txq->complete_q, skb);
2476 ath_txq_skb_done(sc, txq, skb);
2477 }
2478
2479 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2480 struct ath_txq *txq, struct list_head *bf_q,
2481 struct ath_tx_status *ts, int txok)
2482 {
2483 struct sk_buff *skb = bf->bf_mpdu;
2484 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2485 unsigned long flags;
2486 int tx_flags = 0;
2487
2488 if (!txok)
2489 tx_flags |= ATH_TX_ERROR;
2490
2491 if (ts->ts_status & ATH9K_TXERR_FILT)
2492 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2493
2494 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2495 bf->bf_buf_addr = 0;
2496 if (sc->tx99_state)
2497 goto skip_tx_complete;
2498
2499 if (bf->bf_state.bfs_paprd) {
2500 if (time_after(jiffies,
2501 bf->bf_state.bfs_paprd_timestamp +
2502 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2503 dev_kfree_skb_any(skb);
2504 else
2505 complete(&sc->paprd_complete);
2506 } else {
2507 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2508 ath_tx_complete(sc, skb, tx_flags, txq);
2509 }
2510 skip_tx_complete:
2511 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2512 * accidentally reference it later.
2513 */
2514 bf->bf_mpdu = NULL;
2515
2516 /*
2517 * Return the list of ath_buf of this mpdu to free queue
2518 */
2519 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2520 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2521 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2522 }
2523
2524 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2525 struct ath_tx_status *ts, int nframes, int nbad,
2526 int txok)
2527 {
2528 struct sk_buff *skb = bf->bf_mpdu;
2529 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2530 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2531 struct ieee80211_hw *hw = sc->hw;
2532 struct ath_hw *ah = sc->sc_ah;
2533 u8 i, tx_rateindex;
2534
2535 if (txok)
2536 tx_info->status.ack_signal = ts->ts_rssi;
2537
2538 tx_rateindex = ts->ts_rateindex;
2539 WARN_ON(tx_rateindex >= hw->max_rates);
2540
2541 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2542 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2543
2544 BUG_ON(nbad > nframes);
2545 }
2546 tx_info->status.ampdu_len = nframes;
2547 tx_info->status.ampdu_ack_len = nframes - nbad;
2548
2549 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2550 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2551 /*
2552 * If an underrun error is seen assume it as an excessive
2553 * retry only if max frame trigger level has been reached
2554 * (2 KB for single stream, and 4 KB for dual stream).
2555 * Adjust the long retry as if the frame was tried
2556 * hw->max_rate_tries times to affect how rate control updates
2557 * PER for the failed rate.
2558 * In case of congestion on the bus penalizing this type of
2559 * underruns should help hardware actually transmit new frames
2560 * successfully by eventually preferring slower rates.
2561 * This itself should also alleviate congestion on the bus.
2562 */
2563 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2564 ATH9K_TX_DELIM_UNDERRUN)) &&
2565 ieee80211_is_data(hdr->frame_control) &&
2566 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2567 tx_info->status.rates[tx_rateindex].count =
2568 hw->max_rate_tries;
2569 }
2570
2571 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2572 tx_info->status.rates[i].count = 0;
2573 tx_info->status.rates[i].idx = -1;
2574 }
2575
2576 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2577 }
2578
2579 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2580 {
2581 struct ath_hw *ah = sc->sc_ah;
2582 struct ath_common *common = ath9k_hw_common(ah);
2583 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2584 struct list_head bf_head;
2585 struct ath_desc *ds;
2586 struct ath_tx_status ts;
2587 int status;
2588
2589 ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2590 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2591 txq->axq_link);
2592
2593 ath_txq_lock(sc, txq);
2594 for (;;) {
2595 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2596 break;
2597
2598 if (list_empty(&txq->axq_q)) {
2599 txq->axq_link = NULL;
2600 ath_txq_schedule(sc, txq);
2601 break;
2602 }
2603 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2604
2605 /*
2606 * There is a race condition that a BH gets scheduled
2607 * after sw writes TxE and before hw re-load the last
2608 * descriptor to get the newly chained one.
2609 * Software must keep the last DONE descriptor as a
2610 * holding descriptor - software does so by marking
2611 * it with the STALE flag.
2612 */
2613 bf_held = NULL;
2614 if (bf->bf_state.stale) {
2615 bf_held = bf;
2616 if (list_is_last(&bf_held->list, &txq->axq_q))
2617 break;
2618
2619 bf = list_entry(bf_held->list.next, struct ath_buf,
2620 list);
2621 }
2622
2623 lastbf = bf->bf_lastbf;
2624 ds = lastbf->bf_desc;
2625
2626 memset(&ts, 0, sizeof(ts));
2627 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2628 if (status == -EINPROGRESS)
2629 break;
2630
2631 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2632
2633 /*
2634 * Remove ath_buf's of the same transmit unit from txq,
2635 * however leave the last descriptor back as the holding
2636 * descriptor for hw.
2637 */
2638 lastbf->bf_state.stale = true;
2639 INIT_LIST_HEAD(&bf_head);
2640 if (!list_is_singular(&lastbf->list))
2641 list_cut_position(&bf_head,
2642 &txq->axq_q, lastbf->list.prev);
2643
2644 if (bf_held) {
2645 list_del(&bf_held->list);
2646 ath_tx_return_buffer(sc, bf_held);
2647 }
2648
2649 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2650 }
2651 ath_txq_unlock_complete(sc, txq);
2652 }
2653
2654 void ath_tx_tasklet(struct ath_softc *sc)
2655 {
2656 struct ath_hw *ah = sc->sc_ah;
2657 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2658 int i;
2659
2660 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2661 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2662 ath_tx_processq(sc, &sc->tx.txq[i]);
2663 }
2664 }
2665
2666 void ath_tx_edma_tasklet(struct ath_softc *sc)
2667 {
2668 struct ath_tx_status ts;
2669 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2670 struct ath_hw *ah = sc->sc_ah;
2671 struct ath_txq *txq;
2672 struct ath_buf *bf, *lastbf;
2673 struct list_head bf_head;
2674 struct list_head *fifo_list;
2675 int status;
2676
2677 for (;;) {
2678 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2679 break;
2680
2681 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2682 if (status == -EINPROGRESS)
2683 break;
2684 if (status == -EIO) {
2685 ath_dbg(common, XMIT, "Error processing tx status\n");
2686 break;
2687 }
2688
2689 /* Process beacon completions separately */
2690 if (ts.qid == sc->beacon.beaconq) {
2691 sc->beacon.tx_processed = true;
2692 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2693
2694 if (ath9k_is_chanctx_enabled()) {
2695 ath_chanctx_event(sc, NULL,
2696 ATH_CHANCTX_EVENT_BEACON_SENT);
2697 }
2698
2699 ath9k_csa_update(sc);
2700 continue;
2701 }
2702
2703 txq = &sc->tx.txq[ts.qid];
2704
2705 ath_txq_lock(sc, txq);
2706
2707 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2708
2709 fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2710 if (list_empty(fifo_list)) {
2711 ath_txq_unlock(sc, txq);
2712 return;
2713 }
2714
2715 bf = list_first_entry(fifo_list, struct ath_buf, list);
2716 if (bf->bf_state.stale) {
2717 list_del(&bf->list);
2718 ath_tx_return_buffer(sc, bf);
2719 bf = list_first_entry(fifo_list, struct ath_buf, list);
2720 }
2721
2722 lastbf = bf->bf_lastbf;
2723
2724 INIT_LIST_HEAD(&bf_head);
2725 if (list_is_last(&lastbf->list, fifo_list)) {
2726 list_splice_tail_init(fifo_list, &bf_head);
2727 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2728
2729 if (!list_empty(&txq->axq_q)) {
2730 struct list_head bf_q;
2731
2732 INIT_LIST_HEAD(&bf_q);
2733 txq->axq_link = NULL;
2734 list_splice_tail_init(&txq->axq_q, &bf_q);
2735 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2736 }
2737 } else {
2738 lastbf->bf_state.stale = true;
2739 if (bf != lastbf)
2740 list_cut_position(&bf_head, fifo_list,
2741 lastbf->list.prev);
2742 }
2743
2744 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2745 ath_txq_unlock_complete(sc, txq);
2746 }
2747 }
2748
2749 /*****************/
2750 /* Init, Cleanup */
2751 /*****************/
2752
2753 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2754 {
2755 struct ath_descdma *dd = &sc->txsdma;
2756 u8 txs_len = sc->sc_ah->caps.txs_len;
2757
2758 dd->dd_desc_len = size * txs_len;
2759 dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2760 &dd->dd_desc_paddr, GFP_KERNEL);
2761 if (!dd->dd_desc)
2762 return -ENOMEM;
2763
2764 return 0;
2765 }
2766
2767 static int ath_tx_edma_init(struct ath_softc *sc)
2768 {
2769 int err;
2770
2771 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2772 if (!err)
2773 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2774 sc->txsdma.dd_desc_paddr,
2775 ATH_TXSTATUS_RING_SIZE);
2776
2777 return err;
2778 }
2779
2780 int ath_tx_init(struct ath_softc *sc, int nbufs)
2781 {
2782 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2783 int error = 0;
2784
2785 spin_lock_init(&sc->tx.txbuflock);
2786
2787 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2788 "tx", nbufs, 1, 1);
2789 if (error != 0) {
2790 ath_err(common,
2791 "Failed to allocate tx descriptors: %d\n", error);
2792 return error;
2793 }
2794
2795 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2796 "beacon", ATH_BCBUF, 1, 1);
2797 if (error != 0) {
2798 ath_err(common,
2799 "Failed to allocate beacon descriptors: %d\n", error);
2800 return error;
2801 }
2802
2803 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2804
2805 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2806 error = ath_tx_edma_init(sc);
2807
2808 return error;
2809 }
2810
2811 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2812 {
2813 struct ath_atx_tid *tid;
2814 struct ath_atx_ac *ac;
2815 int tidno, acno;
2816
2817 for (tidno = 0, tid = &an->tid[tidno];
2818 tidno < IEEE80211_NUM_TIDS;
2819 tidno++, tid++) {
2820 tid->an = an;
2821 tid->tidno = tidno;
2822 tid->seq_start = tid->seq_next = 0;
2823 tid->baw_size = WME_MAX_BA;
2824 tid->baw_head = tid->baw_tail = 0;
2825 tid->sched = false;
2826 tid->active = false;
2827 __skb_queue_head_init(&tid->buf_q);
2828 __skb_queue_head_init(&tid->retry_q);
2829 acno = TID_TO_WME_AC(tidno);
2830 tid->ac = &an->ac[acno];
2831 }
2832
2833 for (acno = 0, ac = &an->ac[acno];
2834 acno < IEEE80211_NUM_ACS; acno++, ac++) {
2835 ac->sched = false;
2836 ac->clear_ps_filter = true;
2837 ac->txq = sc->tx.txq_map[acno];
2838 INIT_LIST_HEAD(&ac->tid_q);
2839 }
2840 }
2841
2842 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2843 {
2844 struct ath_atx_ac *ac;
2845 struct ath_atx_tid *tid;
2846 struct ath_txq *txq;
2847 int tidno;
2848
2849 for (tidno = 0, tid = &an->tid[tidno];
2850 tidno < IEEE80211_NUM_TIDS; tidno++, tid++) {
2851
2852 ac = tid->ac;
2853 txq = ac->txq;
2854
2855 ath_txq_lock(sc, txq);
2856
2857 if (tid->sched) {
2858 list_del(&tid->list);
2859 tid->sched = false;
2860 }
2861
2862 if (ac->sched) {
2863 list_del(&ac->list);
2864 tid->ac->sched = false;
2865 }
2866
2867 ath_tid_drain(sc, txq, tid);
2868 tid->active = false;
2869
2870 ath_txq_unlock(sc, txq);
2871 }
2872 }
2873
2874 #ifdef CONFIG_ATH9K_TX99
2875
2876 int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2877 struct ath_tx_control *txctl)
2878 {
2879 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2880 struct ath_frame_info *fi = get_frame_info(skb);
2881 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2882 struct ath_buf *bf;
2883 int padpos, padsize;
2884
2885 padpos = ieee80211_hdrlen(hdr->frame_control);
2886 padsize = padpos & 3;
2887
2888 if (padsize && skb->len > padpos) {
2889 if (skb_headroom(skb) < padsize) {
2890 ath_dbg(common, XMIT,
2891 "tx99 padding failed\n");
2892 return -EINVAL;
2893 }
2894
2895 skb_push(skb, padsize);
2896 memmove(skb->data, skb->data + padsize, padpos);
2897 }
2898
2899 fi->keyix = ATH9K_TXKEYIX_INVALID;
2900 fi->framelen = skb->len + FCS_LEN;
2901 fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2902
2903 bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2904 if (!bf) {
2905 ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2906 return -EINVAL;
2907 }
2908
2909 ath_set_rates(sc->tx99_vif, NULL, bf);
2910
2911 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2912 ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2913
2914 ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2915
2916 return 0;
2917 }
2918
2919 #endif /* CONFIG_ATH9K_TX99 */