2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol
[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
52 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
53 struct ath_atx_tid
*tid
, struct sk_buff
*skb
);
54 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
55 int tx_flags
, struct ath_txq
*txq
);
56 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
57 struct ath_txq
*txq
, struct list_head
*bf_q
,
58 struct ath_tx_status
*ts
, int txok
);
59 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
60 struct list_head
*head
, bool internal
);
61 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
62 struct ath_tx_status
*ts
, int nframes
, int nbad
,
64 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
66 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
68 struct ath_atx_tid
*tid
,
78 /*********************/
79 /* Aggregation logic */
80 /*********************/
82 void ath_txq_lock(struct ath_softc
*sc
, struct ath_txq
*txq
)
83 __acquires(&txq
->axq_lock
)
85 spin_lock_bh(&txq
->axq_lock
);
88 void ath_txq_unlock(struct ath_softc
*sc
, struct ath_txq
*txq
)
89 __releases(&txq
->axq_lock
)
91 spin_unlock_bh(&txq
->axq_lock
);
94 void ath_txq_unlock_complete(struct ath_softc
*sc
, struct ath_txq
*txq
)
95 __releases(&txq
->axq_lock
)
97 struct sk_buff_head q
;
100 __skb_queue_head_init(&q
);
101 skb_queue_splice_init(&txq
->complete_q
, &q
);
102 spin_unlock_bh(&txq
->axq_lock
);
104 while ((skb
= __skb_dequeue(&q
)))
105 ieee80211_tx_status(sc
->hw
, skb
);
108 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
110 struct ath_atx_ac
*ac
= tid
->ac
;
119 list_add_tail(&tid
->list
, &ac
->tid_q
);
125 list_add_tail(&ac
->list
, &txq
->axq_acq
);
128 static struct ath_frame_info
*get_frame_info(struct sk_buff
*skb
)
130 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
131 BUILD_BUG_ON(sizeof(struct ath_frame_info
) >
132 sizeof(tx_info
->rate_driver_data
));
133 return (struct ath_frame_info
*) &tx_info
->rate_driver_data
[0];
136 static void ath_send_bar(struct ath_atx_tid
*tid
, u16 seqno
)
141 ieee80211_send_bar(tid
->an
->vif
, tid
->an
->sta
->addr
, tid
->tidno
,
142 seqno
<< IEEE80211_SEQ_SEQ_SHIFT
);
145 static void ath_set_rates(struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
148 ieee80211_get_tx_rates(vif
, sta
, bf
->bf_mpdu
, bf
->rates
,
149 ARRAY_SIZE(bf
->rates
));
152 static void ath_txq_skb_done(struct ath_softc
*sc
, struct ath_txq
*txq
,
157 q
= skb_get_queue_mapping(skb
);
158 if (txq
== sc
->tx
.uapsdq
)
159 txq
= sc
->tx
.txq_map
[q
];
161 if (txq
!= sc
->tx
.txq_map
[q
])
164 if (WARN_ON(--txq
->pending_frames
< 0))
165 txq
->pending_frames
= 0;
168 txq
->pending_frames
< sc
->tx
.txq_max_pending
[q
]) {
169 ieee80211_wake_queue(sc
->hw
, q
);
170 txq
->stopped
= false;
174 static struct ath_atx_tid
*
175 ath_get_skb_tid(struct ath_softc
*sc
, struct ath_node
*an
, struct sk_buff
*skb
)
177 u8 tidno
= skb
->priority
& IEEE80211_QOS_CTL_TID_MASK
;
178 return ATH_AN_2_TID(an
, tidno
);
181 static bool ath_tid_has_buffered(struct ath_atx_tid
*tid
)
183 return !skb_queue_empty(&tid
->buf_q
) || !skb_queue_empty(&tid
->retry_q
);
186 static struct sk_buff
*ath_tid_dequeue(struct ath_atx_tid
*tid
)
190 skb
= __skb_dequeue(&tid
->retry_q
);
192 skb
= __skb_dequeue(&tid
->buf_q
);
198 * ath_tx_tid_change_state:
199 * - clears a-mpdu flag of previous session
200 * - force sequence number allocation to fix next BlockAck Window
203 ath_tx_tid_change_state(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
205 struct ath_txq
*txq
= tid
->ac
->txq
;
206 struct ieee80211_tx_info
*tx_info
;
207 struct sk_buff
*skb
, *tskb
;
209 struct ath_frame_info
*fi
;
211 skb_queue_walk_safe(&tid
->buf_q
, skb
, tskb
) {
212 fi
= get_frame_info(skb
);
215 tx_info
= IEEE80211_SKB_CB(skb
);
216 tx_info
->flags
&= ~IEEE80211_TX_CTL_AMPDU
;
221 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
223 __skb_unlink(skb
, &tid
->buf_q
);
224 ath_txq_skb_done(sc
, txq
, skb
);
225 ieee80211_free_txskb(sc
->hw
, skb
);
232 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
234 struct ath_txq
*txq
= tid
->ac
->txq
;
237 struct list_head bf_head
;
238 struct ath_tx_status ts
;
239 struct ath_frame_info
*fi
;
240 bool sendbar
= false;
242 INIT_LIST_HEAD(&bf_head
);
244 memset(&ts
, 0, sizeof(ts
));
246 while ((skb
= __skb_dequeue(&tid
->retry_q
))) {
247 fi
= get_frame_info(skb
);
250 ath_txq_skb_done(sc
, txq
, skb
);
251 ieee80211_free_txskb(sc
->hw
, skb
);
255 if (fi
->baw_tracked
) {
256 ath_tx_update_baw(sc
, tid
, bf
->bf_state
.seqno
);
260 list_add_tail(&bf
->list
, &bf_head
);
261 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
265 ath_txq_unlock(sc
, txq
);
266 ath_send_bar(tid
, tid
->seq_start
);
267 ath_txq_lock(sc
, txq
);
271 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
276 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
277 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
279 __clear_bit(cindex
, tid
->tx_buf
);
281 while (tid
->baw_head
!= tid
->baw_tail
&& !test_bit(tid
->baw_head
, tid
->tx_buf
)) {
282 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
283 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
284 if (tid
->bar_index
>= 0)
289 static void ath_tx_addto_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
292 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
293 u16 seqno
= bf
->bf_state
.seqno
;
296 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
297 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
298 __set_bit(cindex
, tid
->tx_buf
);
301 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
302 (ATH_TID_MAX_BUFS
- 1))) {
303 tid
->baw_tail
= cindex
;
304 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
308 static void ath_tid_drain(struct ath_softc
*sc
, struct ath_txq
*txq
,
309 struct ath_atx_tid
*tid
)
314 struct list_head bf_head
;
315 struct ath_tx_status ts
;
316 struct ath_frame_info
*fi
;
318 memset(&ts
, 0, sizeof(ts
));
319 INIT_LIST_HEAD(&bf_head
);
321 while ((skb
= ath_tid_dequeue(tid
))) {
322 fi
= get_frame_info(skb
);
326 ath_tx_complete(sc
, skb
, ATH_TX_ERROR
, txq
);
330 list_add_tail(&bf
->list
, &bf_head
);
331 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
335 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_txq
*txq
,
336 struct sk_buff
*skb
, int count
)
338 struct ath_frame_info
*fi
= get_frame_info(skb
);
339 struct ath_buf
*bf
= fi
->bf
;
340 struct ieee80211_hdr
*hdr
;
341 int prev
= fi
->retries
;
343 TX_STAT_INC(txq
->axq_qnum
, a_retries
);
344 fi
->retries
+= count
;
349 hdr
= (struct ieee80211_hdr
*)skb
->data
;
350 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
351 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
352 sizeof(*hdr
), DMA_TO_DEVICE
);
355 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
357 struct ath_buf
*bf
= NULL
;
359 spin_lock_bh(&sc
->tx
.txbuflock
);
361 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
362 spin_unlock_bh(&sc
->tx
.txbuflock
);
366 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
369 spin_unlock_bh(&sc
->tx
.txbuflock
);
374 static void ath_tx_return_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
)
376 spin_lock_bh(&sc
->tx
.txbuflock
);
377 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
378 spin_unlock_bh(&sc
->tx
.txbuflock
);
381 static struct ath_buf
* ath_clone_txbuf(struct ath_softc
*sc
, struct ath_buf
*bf
)
385 tbf
= ath_tx_get_buffer(sc
);
389 ATH_TXBUF_RESET(tbf
);
391 tbf
->bf_mpdu
= bf
->bf_mpdu
;
392 tbf
->bf_buf_addr
= bf
->bf_buf_addr
;
393 memcpy(tbf
->bf_desc
, bf
->bf_desc
, sc
->sc_ah
->caps
.tx_desc_len
);
394 tbf
->bf_state
= bf
->bf_state
;
395 tbf
->bf_state
.stale
= false;
400 static void ath_tx_count_frames(struct ath_softc
*sc
, struct ath_buf
*bf
,
401 struct ath_tx_status
*ts
, int txok
,
402 int *nframes
, int *nbad
)
404 struct ath_frame_info
*fi
;
406 u32 ba
[WME_BA_BMP_SIZE
>> 5];
413 isaggr
= bf_isaggr(bf
);
415 seq_st
= ts
->ts_seqnum
;
416 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
420 fi
= get_frame_info(bf
->bf_mpdu
);
421 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_state
.seqno
);
424 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
432 static void ath_tx_complete_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
433 struct ath_buf
*bf
, struct list_head
*bf_q
,
434 struct ath_tx_status
*ts
, int txok
)
436 struct ath_node
*an
= NULL
;
438 struct ieee80211_sta
*sta
;
439 struct ieee80211_hw
*hw
= sc
->hw
;
440 struct ieee80211_hdr
*hdr
;
441 struct ieee80211_tx_info
*tx_info
;
442 struct ath_atx_tid
*tid
= NULL
;
443 struct ath_buf
*bf_next
, *bf_last
= bf
->bf_lastbf
;
444 struct list_head bf_head
;
445 struct sk_buff_head bf_pending
;
446 u16 seq_st
= 0, acked_cnt
= 0, txfail_cnt
= 0, seq_first
;
447 u32 ba
[WME_BA_BMP_SIZE
>> 5];
448 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0, nbad
= 0;
449 bool rc_update
= true, isba
;
450 struct ieee80211_tx_rate rates
[4];
451 struct ath_frame_info
*fi
;
453 bool flush
= !!(ts
->ts_status
& ATH9K_TX_FLUSH
);
458 hdr
= (struct ieee80211_hdr
*)skb
->data
;
460 tx_info
= IEEE80211_SKB_CB(skb
);
462 memcpy(rates
, bf
->rates
, sizeof(rates
));
464 retries
= ts
->ts_longretry
+ 1;
465 for (i
= 0; i
< ts
->ts_rateindex
; i
++)
466 retries
+= rates
[i
].count
;
470 sta
= ieee80211_find_sta_by_ifaddr(hw
, hdr
->addr1
, hdr
->addr2
);
474 INIT_LIST_HEAD(&bf_head
);
476 bf_next
= bf
->bf_next
;
478 if (!bf
->bf_state
.stale
|| bf_next
!= NULL
)
479 list_move_tail(&bf
->list
, &bf_head
);
481 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
, 0);
488 an
= (struct ath_node
*)sta
->drv_priv
;
489 tid
= ath_get_skb_tid(sc
, an
, skb
);
490 seq_first
= tid
->seq_start
;
491 isba
= ts
->ts_flags
& ATH9K_TX_BA
;
494 * The hardware occasionally sends a tx status for the wrong TID.
495 * In this case, the BA status cannot be considered valid and all
496 * subframes need to be retransmitted
498 * Only BlockAcks have a TID and therefore normal Acks cannot be
501 if (isba
&& tid
->tidno
!= ts
->tid
)
504 isaggr
= bf_isaggr(bf
);
505 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
507 if (isaggr
&& txok
) {
508 if (ts
->ts_flags
& ATH9K_TX_BA
) {
509 seq_st
= ts
->ts_seqnum
;
510 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
513 * AR5416 can become deaf/mute when BA
514 * issue happens. Chip needs to be reset.
515 * But AP code may have sychronization issues
516 * when perform internal reset in this routine.
517 * Only enable reset in STA mode for now.
519 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
)
524 __skb_queue_head_init(&bf_pending
);
526 ath_tx_count_frames(sc
, bf
, ts
, txok
, &nframes
, &nbad
);
528 u16 seqno
= bf
->bf_state
.seqno
;
530 txfail
= txpending
= sendbar
= 0;
531 bf_next
= bf
->bf_next
;
534 tx_info
= IEEE80211_SKB_CB(skb
);
535 fi
= get_frame_info(skb
);
537 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, seqno
) ||
540 * Outside of the current BlockAck window,
541 * maybe part of a previous session
544 } else if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, seqno
))) {
545 /* transmit completion, subframe is
546 * acked by block ack */
548 } else if (!isaggr
&& txok
) {
549 /* transmit completion */
553 } else if (fi
->retries
< ATH_MAX_SW_RETRIES
) {
554 if (txok
|| !an
->sleeping
)
555 ath_tx_set_retry(sc
, txq
, bf
->bf_mpdu
,
562 bar_index
= max_t(int, bar_index
,
563 ATH_BA_INDEX(seq_first
, seqno
));
567 * Make sure the last desc is reclaimed if it
568 * not a holding desc.
570 INIT_LIST_HEAD(&bf_head
);
571 if (bf_next
!= NULL
|| !bf_last
->bf_state
.stale
)
572 list_move_tail(&bf
->list
, &bf_head
);
576 * complete the acked-ones/xretried ones; update
579 ath_tx_update_baw(sc
, tid
, seqno
);
581 if (rc_update
&& (acked_cnt
== 1 || txfail_cnt
== 1)) {
582 memcpy(tx_info
->control
.rates
, rates
, sizeof(rates
));
583 ath_tx_rc_status(sc
, bf
, ts
, nframes
, nbad
, txok
);
587 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
,
590 if (tx_info
->flags
& IEEE80211_TX_STATUS_EOSP
) {
591 tx_info
->flags
&= ~IEEE80211_TX_STATUS_EOSP
;
592 ieee80211_sta_eosp(sta
);
594 /* retry the un-acked ones */
595 if (bf
->bf_next
== NULL
&& bf_last
->bf_state
.stale
) {
598 tbf
= ath_clone_txbuf(sc
, bf_last
);
600 * Update tx baw and complete the
601 * frame with failed status if we
605 ath_tx_update_baw(sc
, tid
, seqno
);
607 ath_tx_complete_buf(sc
, bf
, txq
,
609 bar_index
= max_t(int, bar_index
,
610 ATH_BA_INDEX(seq_first
, seqno
));
618 * Put this buffer to the temporary pending
619 * queue to retain ordering
621 __skb_queue_tail(&bf_pending
, skb
);
627 /* prepend un-acked frames to the beginning of the pending frame queue */
628 if (!skb_queue_empty(&bf_pending
)) {
630 ieee80211_sta_set_buffered(sta
, tid
->tidno
, true);
632 skb_queue_splice_tail(&bf_pending
, &tid
->retry_q
);
634 ath_tx_queue_tid(txq
, tid
);
636 if (ts
->ts_status
& (ATH9K_TXERR_FILT
| ATH9K_TXERR_XRETRY
))
637 tid
->ac
->clear_ps_filter
= true;
641 if (bar_index
>= 0) {
642 u16 bar_seq
= ATH_BA_INDEX2SEQ(seq_first
, bar_index
);
644 if (BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bar_seq
))
645 tid
->bar_index
= ATH_BA_INDEX(tid
->seq_start
, bar_seq
);
647 ath_txq_unlock(sc
, txq
);
648 ath_send_bar(tid
, ATH_BA_INDEX2SEQ(seq_first
, bar_index
+ 1));
649 ath_txq_lock(sc
, txq
);
655 ath9k_queue_reset(sc
, RESET_TYPE_TX_ERROR
);
658 static bool bf_is_ampdu_not_probing(struct ath_buf
*bf
)
660 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
661 return bf_isampdu(bf
) && !(info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
);
664 static void ath_tx_process_buffer(struct ath_softc
*sc
, struct ath_txq
*txq
,
665 struct ath_tx_status
*ts
, struct ath_buf
*bf
,
666 struct list_head
*bf_head
)
668 struct ieee80211_tx_info
*info
;
671 txok
= !(ts
->ts_status
& ATH9K_TXERR_MASK
);
672 flush
= !!(ts
->ts_status
& ATH9K_TX_FLUSH
);
673 txq
->axq_tx_inprogress
= false;
676 if (bf_is_ampdu_not_probing(bf
))
677 txq
->axq_ampdu_depth
--;
679 if (!bf_isampdu(bf
)) {
681 info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
682 memcpy(info
->control
.rates
, bf
->rates
,
683 sizeof(info
->control
.rates
));
684 ath_tx_rc_status(sc
, bf
, ts
, 1, txok
? 0 : 1, txok
);
686 ath_tx_complete_buf(sc
, bf
, txq
, bf_head
, ts
, txok
);
688 ath_tx_complete_aggr(sc
, txq
, bf
, bf_head
, ts
, txok
);
691 ath_txq_schedule(sc
, txq
);
694 static bool ath_lookup_legacy(struct ath_buf
*bf
)
697 struct ieee80211_tx_info
*tx_info
;
698 struct ieee80211_tx_rate
*rates
;
702 tx_info
= IEEE80211_SKB_CB(skb
);
703 rates
= tx_info
->control
.rates
;
705 for (i
= 0; i
< 4; i
++) {
706 if (!rates
[i
].count
|| rates
[i
].idx
< 0)
709 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
))
716 static u32
ath_lookup_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
717 struct ath_atx_tid
*tid
)
720 struct ieee80211_tx_info
*tx_info
;
721 struct ieee80211_tx_rate
*rates
;
722 u32 max_4ms_framelen
, frmlen
;
723 u16 aggr_limit
, bt_aggr_limit
, legacy
= 0;
724 int q
= tid
->ac
->txq
->mac80211_qnum
;
728 tx_info
= IEEE80211_SKB_CB(skb
);
732 * Find the lowest frame length among the rate series that will have a
733 * 4ms (or TXOP limited) transmit duration.
735 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
737 for (i
= 0; i
< 4; i
++) {
743 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
)) {
748 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
753 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
756 frmlen
= sc
->tx
.max_aggr_framelen
[q
][modeidx
][rates
[i
].idx
];
757 max_4ms_framelen
= min(max_4ms_framelen
, frmlen
);
761 * limit aggregate size by the minimum rate if rate selected is
762 * not a probe rate, if rate selected is a probe rate then
763 * avoid aggregation of this packet.
765 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
768 aggr_limit
= min(max_4ms_framelen
, (u32
)ATH_AMPDU_LIMIT_MAX
);
771 * Override the default aggregation limit for BTCOEX.
773 bt_aggr_limit
= ath9k_btcoex_aggr_limit(sc
, max_4ms_framelen
);
775 aggr_limit
= bt_aggr_limit
;
777 if (tid
->an
->maxampdu
)
778 aggr_limit
= min(aggr_limit
, tid
->an
->maxampdu
);
784 * Returns the number of delimiters to be added to
785 * meet the minimum required mpdudensity.
787 static int ath_compute_num_delims(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
788 struct ath_buf
*bf
, u16 frmlen
,
791 #define FIRST_DESC_NDELIMS 60
792 u32 nsymbits
, nsymbols
;
795 int width
, streams
, half_gi
, ndelim
, mindelim
;
796 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
798 /* Select standard number of delimiters based on frame length alone */
799 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
802 * If encryption enabled, hardware requires some more padding between
804 * TODO - this could be improved to be dependent on the rate.
805 * The hardware can keep up at lower rates, but not higher rates
807 if ((fi
->keyix
!= ATH9K_TXKEYIX_INVALID
) &&
808 !(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
))
809 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
812 * Add delimiter when using RTS/CTS with aggregation
813 * and non enterprise AR9003 card
815 if (first_subfrm
&& !AR_SREV_9580_10_OR_LATER(sc
->sc_ah
) &&
816 (sc
->sc_ah
->ent_mode
& AR_ENT_OTP_MIN_PKT_SIZE_DISABLE
))
817 ndelim
= max(ndelim
, FIRST_DESC_NDELIMS
);
820 * Convert desired mpdu density from microeconds to bytes based
821 * on highest rate in rate series (i.e. first rate) to determine
822 * required minimum length for subframe. Take into account
823 * whether high rate is 20 or 40Mhz and half or full GI.
825 * If there is no mpdu density restriction, no further calculation
829 if (tid
->an
->mpdudensity
== 0)
832 rix
= bf
->rates
[0].idx
;
833 flags
= bf
->rates
[0].flags
;
834 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
835 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
838 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(tid
->an
->mpdudensity
);
840 nsymbols
= NUM_SYMBOLS_PER_USEC(tid
->an
->mpdudensity
);
845 streams
= HT_RC_2_STREAMS(rix
);
846 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
847 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
849 if (frmlen
< minlen
) {
850 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
851 ndelim
= max(mindelim
, ndelim
);
857 static struct ath_buf
*
858 ath_tx_get_tid_subframe(struct ath_softc
*sc
, struct ath_txq
*txq
,
859 struct ath_atx_tid
*tid
, struct sk_buff_head
**q
)
861 struct ieee80211_tx_info
*tx_info
;
862 struct ath_frame_info
*fi
;
869 if (skb_queue_empty(*q
))
876 fi
= get_frame_info(skb
);
879 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
881 bf
->bf_state
.stale
= false;
884 __skb_unlink(skb
, *q
);
885 ath_txq_skb_done(sc
, txq
, skb
);
886 ieee80211_free_txskb(sc
->hw
, skb
);
893 tx_info
= IEEE80211_SKB_CB(skb
);
894 tx_info
->flags
&= ~IEEE80211_TX_CTL_CLEAR_PS_FILT
;
895 if (!(tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)) {
896 bf
->bf_state
.bf_type
= 0;
900 bf
->bf_state
.bf_type
= BUF_AMPDU
| BUF_AGGR
;
901 seqno
= bf
->bf_state
.seqno
;
903 /* do not step over block-ack window */
904 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, seqno
))
907 if (tid
->bar_index
> ATH_BA_INDEX(tid
->seq_start
, seqno
)) {
908 struct ath_tx_status ts
= {};
909 struct list_head bf_head
;
911 INIT_LIST_HEAD(&bf_head
);
912 list_add(&bf
->list
, &bf_head
);
913 __skb_unlink(skb
, *q
);
914 ath_tx_update_baw(sc
, tid
, seqno
);
915 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0);
926 ath_tx_form_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
927 struct ath_atx_tid
*tid
, struct list_head
*bf_q
,
928 struct ath_buf
*bf_first
, struct sk_buff_head
*tid_q
,
931 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
932 struct ath_buf
*bf
= bf_first
, *bf_prev
= NULL
;
933 int nframes
= 0, ndelim
;
934 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
935 al_delta
, h_baw
= tid
->baw_size
/ 2;
936 struct ieee80211_tx_info
*tx_info
;
937 struct ath_frame_info
*fi
;
942 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
946 fi
= get_frame_info(skb
);
948 /* do not exceed aggregation limit */
949 al_delta
= ATH_AGGR_DELIM_SZ
+ fi
->framelen
;
951 if (aggr_limit
< al
+ bpad
+ al_delta
||
952 ath_lookup_legacy(bf
) || nframes
>= h_baw
)
955 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
956 if ((tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
) ||
957 !(tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
))
961 /* add padding for previous frame to aggregation length */
962 al
+= bpad
+ al_delta
;
965 * Get the delimiters needed to meet the MPDU
966 * density for this node.
968 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, fi
->framelen
,
970 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
975 /* link buffers of this frame to the aggregate */
976 if (!fi
->baw_tracked
)
977 ath_tx_addto_baw(sc
, tid
, bf
);
978 bf
->bf_state
.ndelim
= ndelim
;
980 __skb_unlink(skb
, tid_q
);
981 list_add_tail(&bf
->list
, bf_q
);
983 bf_prev
->bf_next
= bf
;
987 bf
= ath_tx_get_tid_subframe(sc
, txq
, tid
, &tid_q
);
992 } while (ath_tid_has_buffered(tid
));
995 bf
->bf_lastbf
= bf_prev
;
998 al
= get_frame_info(bf
->bf_mpdu
)->framelen
;
999 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1001 TX_STAT_INC(txq
->axq_qnum
, a_aggr
);
1012 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1013 * width - 0 for 20 MHz, 1 for 40 MHz
1014 * half_gi - to use 4us v/s 3.6 us for symbol time
1016 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, int pktlen
,
1017 int width
, int half_gi
, bool shortPreamble
)
1019 u32 nbits
, nsymbits
, duration
, nsymbols
;
1022 /* find number of symbols: PLCP + data */
1023 streams
= HT_RC_2_STREAMS(rix
);
1024 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
1025 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
1026 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
1029 duration
= SYMBOL_TIME(nsymbols
);
1031 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
1033 /* addup duration for legacy/ht training and signal fields */
1034 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
1039 static int ath_max_framelen(int usec
, int mcs
, bool ht40
, bool sgi
)
1041 int streams
= HT_RC_2_STREAMS(mcs
);
1045 symbols
= sgi
? TIME_SYMBOLS_HALFGI(usec
) : TIME_SYMBOLS(usec
);
1046 bits
= symbols
* bits_per_symbol
[mcs
% 8][ht40
] * streams
;
1047 bits
-= OFDM_PLCP_BITS
;
1049 bytes
-= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
1056 void ath_update_max_aggr_framelen(struct ath_softc
*sc
, int queue
, int txop
)
1058 u16
*cur_ht20
, *cur_ht20_sgi
, *cur_ht40
, *cur_ht40_sgi
;
1061 /* 4ms is the default (and maximum) duration */
1062 if (!txop
|| txop
> 4096)
1065 cur_ht20
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT20
];
1066 cur_ht20_sgi
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT20_SGI
];
1067 cur_ht40
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT40
];
1068 cur_ht40_sgi
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT40_SGI
];
1069 for (mcs
= 0; mcs
< 32; mcs
++) {
1070 cur_ht20
[mcs
] = ath_max_framelen(txop
, mcs
, false, false);
1071 cur_ht20_sgi
[mcs
] = ath_max_framelen(txop
, mcs
, false, true);
1072 cur_ht40
[mcs
] = ath_max_framelen(txop
, mcs
, true, false);
1073 cur_ht40_sgi
[mcs
] = ath_max_framelen(txop
, mcs
, true, true);
1077 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
1078 struct ath_tx_info
*info
, int len
, bool rts
)
1080 struct ath_hw
*ah
= sc
->sc_ah
;
1081 struct sk_buff
*skb
;
1082 struct ieee80211_tx_info
*tx_info
;
1083 struct ieee80211_tx_rate
*rates
;
1084 const struct ieee80211_rate
*rate
;
1085 struct ieee80211_hdr
*hdr
;
1086 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
1087 u32 rts_thresh
= sc
->hw
->wiphy
->rts_threshold
;
1092 tx_info
= IEEE80211_SKB_CB(skb
);
1094 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1096 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1097 info
->dur_update
= !ieee80211_is_pspoll(hdr
->frame_control
);
1098 info
->rtscts_rate
= fi
->rtscts_rate
;
1100 for (i
= 0; i
< ARRAY_SIZE(bf
->rates
); i
++) {
1101 bool is_40
, is_sgi
, is_sp
;
1104 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
1108 info
->rates
[i
].Tries
= rates
[i
].count
;
1111 * Handle RTS threshold for unaggregated HT frames.
1113 if (bf_isampdu(bf
) && !bf_isaggr(bf
) &&
1114 (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) &&
1115 unlikely(rts_thresh
!= (u32
) -1)) {
1116 if (!rts_thresh
|| (len
> rts_thresh
))
1120 if (rts
|| rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
1121 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1122 info
->flags
|= ATH9K_TXDESC_RTSENA
;
1123 } else if (rates
[i
].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1124 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1125 info
->flags
|= ATH9K_TXDESC_CTSENA
;
1128 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
1129 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_2040
;
1130 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
1131 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_HALFGI
;
1133 is_sgi
= !!(rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
);
1134 is_40
= !!(rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
);
1135 is_sp
= !!(rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
);
1137 if (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) {
1139 info
->rates
[i
].Rate
= rix
| 0x80;
1140 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
1141 ah
->txchainmask
, info
->rates
[i
].Rate
);
1142 info
->rates
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, len
,
1143 is_40
, is_sgi
, is_sp
);
1144 if (rix
< 8 && (tx_info
->flags
& IEEE80211_TX_CTL_STBC
))
1145 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_STBC
;
1150 rate
= &sc
->sbands
[tx_info
->band
].bitrates
[rates
[i
].idx
];
1151 if ((tx_info
->band
== IEEE80211_BAND_2GHZ
) &&
1152 !(rate
->flags
& IEEE80211_RATE_ERP_G
))
1153 phy
= WLAN_RC_PHY_CCK
;
1155 phy
= WLAN_RC_PHY_OFDM
;
1157 info
->rates
[i
].Rate
= rate
->hw_value
;
1158 if (rate
->hw_value_short
) {
1159 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
1160 info
->rates
[i
].Rate
|= rate
->hw_value_short
;
1165 if (bf
->bf_state
.bfs_paprd
)
1166 info
->rates
[i
].ChSel
= ah
->txchainmask
;
1168 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
1169 ah
->txchainmask
, info
->rates
[i
].Rate
);
1171 info
->rates
[i
].PktDuration
= ath9k_hw_computetxtime(sc
->sc_ah
,
1172 phy
, rate
->bitrate
* 100, len
, rix
, is_sp
);
1175 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1176 if (bf_isaggr(bf
) && (len
> sc
->sc_ah
->caps
.rts_aggr_limit
))
1177 info
->flags
&= ~ATH9K_TXDESC_RTSENA
;
1179 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1180 if (info
->flags
& ATH9K_TXDESC_RTSENA
)
1181 info
->flags
&= ~ATH9K_TXDESC_CTSENA
;
1184 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1186 struct ieee80211_hdr
*hdr
;
1187 enum ath9k_pkt_type htype
;
1190 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1191 fc
= hdr
->frame_control
;
1193 if (ieee80211_is_beacon(fc
))
1194 htype
= ATH9K_PKT_TYPE_BEACON
;
1195 else if (ieee80211_is_probe_resp(fc
))
1196 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
1197 else if (ieee80211_is_atim(fc
))
1198 htype
= ATH9K_PKT_TYPE_ATIM
;
1199 else if (ieee80211_is_pspoll(fc
))
1200 htype
= ATH9K_PKT_TYPE_PSPOLL
;
1202 htype
= ATH9K_PKT_TYPE_NORMAL
;
1207 static void ath_tx_fill_desc(struct ath_softc
*sc
, struct ath_buf
*bf
,
1208 struct ath_txq
*txq
, int len
)
1210 struct ath_hw
*ah
= sc
->sc_ah
;
1211 struct ath_buf
*bf_first
= NULL
;
1212 struct ath_tx_info info
;
1213 u32 rts_thresh
= sc
->hw
->wiphy
->rts_threshold
;
1216 memset(&info
, 0, sizeof(info
));
1217 info
.is_first
= true;
1218 info
.is_last
= true;
1219 info
.txpower
= MAX_RATE_POWER
;
1220 info
.qcu
= txq
->axq_qnum
;
1223 struct sk_buff
*skb
= bf
->bf_mpdu
;
1224 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1225 struct ath_frame_info
*fi
= get_frame_info(skb
);
1226 bool aggr
= !!(bf
->bf_state
.bf_type
& BUF_AGGR
);
1228 info
.type
= get_hw_packet_type(skb
);
1230 info
.link
= bf
->bf_next
->bf_daddr
;
1232 info
.link
= (sc
->tx99_state
) ? bf
->bf_daddr
: 0;
1237 if (!sc
->tx99_state
)
1238 info
.flags
= ATH9K_TXDESC_INTREQ
;
1239 if ((tx_info
->flags
& IEEE80211_TX_CTL_CLEAR_PS_FILT
) ||
1240 txq
== sc
->tx
.uapsdq
)
1241 info
.flags
|= ATH9K_TXDESC_CLRDMASK
;
1243 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1244 info
.flags
|= ATH9K_TXDESC_NOACK
;
1245 if (tx_info
->flags
& IEEE80211_TX_CTL_LDPC
)
1246 info
.flags
|= ATH9K_TXDESC_LDPC
;
1248 if (bf
->bf_state
.bfs_paprd
)
1249 info
.flags
|= (u32
) bf
->bf_state
.bfs_paprd
<<
1250 ATH9K_TXDESC_PAPRD_S
;
1253 * mac80211 doesn't handle RTS threshold for HT because
1254 * the decision has to be taken based on AMPDU length
1255 * and aggregation is done entirely inside ath9k.
1256 * Set the RTS/CTS flag for the first subframe based
1259 if (aggr
&& (bf
== bf_first
) &&
1260 unlikely(rts_thresh
!= (u32
) -1)) {
1262 * "len" is the size of the entire AMPDU.
1264 if (!rts_thresh
|| (len
> rts_thresh
))
1271 ath_buf_set_rate(sc
, bf
, &info
, len
, rts
);
1274 info
.buf_addr
[0] = bf
->bf_buf_addr
;
1275 info
.buf_len
[0] = skb
->len
;
1276 info
.pkt_len
= fi
->framelen
;
1277 info
.keyix
= fi
->keyix
;
1278 info
.keytype
= fi
->keytype
;
1282 info
.aggr
= AGGR_BUF_FIRST
;
1283 else if (bf
== bf_first
->bf_lastbf
)
1284 info
.aggr
= AGGR_BUF_LAST
;
1286 info
.aggr
= AGGR_BUF_MIDDLE
;
1288 info
.ndelim
= bf
->bf_state
.ndelim
;
1289 info
.aggr_len
= len
;
1292 if (bf
== bf_first
->bf_lastbf
)
1295 ath9k_hw_set_txdesc(ah
, bf
->bf_desc
, &info
);
1301 ath_tx_form_burst(struct ath_softc
*sc
, struct ath_txq
*txq
,
1302 struct ath_atx_tid
*tid
, struct list_head
*bf_q
,
1303 struct ath_buf
*bf_first
, struct sk_buff_head
*tid_q
)
1305 struct ath_buf
*bf
= bf_first
, *bf_prev
= NULL
;
1306 struct sk_buff
*skb
;
1310 struct ieee80211_tx_info
*tx_info
;
1314 __skb_unlink(skb
, tid_q
);
1315 list_add_tail(&bf
->list
, bf_q
);
1317 bf_prev
->bf_next
= bf
;
1323 bf
= ath_tx_get_tid_subframe(sc
, txq
, tid
, &tid_q
);
1327 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1328 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)
1331 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1335 static bool ath_tx_sched_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
1336 struct ath_atx_tid
*tid
, bool *stop
)
1339 struct ieee80211_tx_info
*tx_info
;
1340 struct sk_buff_head
*tid_q
;
1341 struct list_head bf_q
;
1343 bool aggr
, last
= true;
1345 if (!ath_tid_has_buffered(tid
))
1348 INIT_LIST_HEAD(&bf_q
);
1350 bf
= ath_tx_get_tid_subframe(sc
, txq
, tid
, &tid_q
);
1354 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1355 aggr
= !!(tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
);
1356 if ((aggr
&& txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
) ||
1357 (!aggr
&& txq
->axq_depth
>= ATH_NON_AGGR_MIN_QDEPTH
)) {
1362 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1364 last
= ath_tx_form_aggr(sc
, txq
, tid
, &bf_q
, bf
,
1367 ath_tx_form_burst(sc
, txq
, tid
, &bf_q
, bf
, tid_q
);
1369 if (list_empty(&bf_q
))
1372 if (tid
->ac
->clear_ps_filter
|| tid
->an
->no_ps_filter
) {
1373 tid
->ac
->clear_ps_filter
= false;
1374 tx_info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1377 ath_tx_fill_desc(sc
, bf
, txq
, aggr_len
);
1378 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, false);
1382 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
1385 struct ath_atx_tid
*txtid
;
1386 struct ath_txq
*txq
;
1387 struct ath_node
*an
;
1390 an
= (struct ath_node
*)sta
->drv_priv
;
1391 txtid
= ATH_AN_2_TID(an
, tid
);
1392 txq
= txtid
->ac
->txq
;
1394 ath_txq_lock(sc
, txq
);
1396 /* update ampdu factor/density, they may have changed. This may happen
1397 * in HT IBSS when a beacon with HT-info is received after the station
1398 * has already been added.
1400 if (sta
->ht_cap
.ht_supported
) {
1401 an
->maxampdu
= (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR
+
1402 sta
->ht_cap
.ampdu_factor
)) - 1;
1403 density
= ath9k_parse_mpdudensity(sta
->ht_cap
.ampdu_density
);
1404 an
->mpdudensity
= density
;
1407 /* force sequence number allocation for pending frames */
1408 ath_tx_tid_change_state(sc
, txtid
);
1410 txtid
->active
= true;
1411 txtid
->paused
= true;
1412 *ssn
= txtid
->seq_start
= txtid
->seq_next
;
1413 txtid
->bar_index
= -1;
1415 memset(txtid
->tx_buf
, 0, sizeof(txtid
->tx_buf
));
1416 txtid
->baw_head
= txtid
->baw_tail
= 0;
1418 ath_txq_unlock_complete(sc
, txq
);
1423 void ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
1425 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
1426 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
1427 struct ath_txq
*txq
= txtid
->ac
->txq
;
1429 ath_txq_lock(sc
, txq
);
1430 txtid
->active
= false;
1431 txtid
->paused
= false;
1432 ath_tx_flush_tid(sc
, txtid
);
1433 ath_tx_tid_change_state(sc
, txtid
);
1434 ath_txq_unlock_complete(sc
, txq
);
1437 void ath_tx_aggr_sleep(struct ieee80211_sta
*sta
, struct ath_softc
*sc
,
1438 struct ath_node
*an
)
1440 struct ath_atx_tid
*tid
;
1441 struct ath_atx_ac
*ac
;
1442 struct ath_txq
*txq
;
1446 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1447 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
1455 ath_txq_lock(sc
, txq
);
1457 buffered
= ath_tid_has_buffered(tid
);
1460 list_del(&tid
->list
);
1464 list_del(&ac
->list
);
1467 ath_txq_unlock(sc
, txq
);
1469 ieee80211_sta_set_buffered(sta
, tidno
, buffered
);
1473 void ath_tx_aggr_wakeup(struct ath_softc
*sc
, struct ath_node
*an
)
1475 struct ath_atx_tid
*tid
;
1476 struct ath_atx_ac
*ac
;
1477 struct ath_txq
*txq
;
1480 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1481 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
1486 ath_txq_lock(sc
, txq
);
1487 ac
->clear_ps_filter
= true;
1489 if (!tid
->paused
&& ath_tid_has_buffered(tid
)) {
1490 ath_tx_queue_tid(txq
, tid
);
1491 ath_txq_schedule(sc
, txq
);
1494 ath_txq_unlock_complete(sc
, txq
);
1498 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
1501 struct ath_atx_tid
*tid
;
1502 struct ath_node
*an
;
1503 struct ath_txq
*txq
;
1505 an
= (struct ath_node
*)sta
->drv_priv
;
1506 tid
= ATH_AN_2_TID(an
, tidno
);
1509 ath_txq_lock(sc
, txq
);
1511 tid
->baw_size
= IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
1512 tid
->paused
= false;
1514 if (ath_tid_has_buffered(tid
)) {
1515 ath_tx_queue_tid(txq
, tid
);
1516 ath_txq_schedule(sc
, txq
);
1519 ath_txq_unlock_complete(sc
, txq
);
1522 void ath9k_release_buffered_frames(struct ieee80211_hw
*hw
,
1523 struct ieee80211_sta
*sta
,
1524 u16 tids
, int nframes
,
1525 enum ieee80211_frame_release_type reason
,
1528 struct ath_softc
*sc
= hw
->priv
;
1529 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
1530 struct ath_txq
*txq
= sc
->tx
.uapsdq
;
1531 struct ieee80211_tx_info
*info
;
1532 struct list_head bf_q
;
1533 struct ath_buf
*bf_tail
= NULL
, *bf
;
1534 struct sk_buff_head
*tid_q
;
1538 INIT_LIST_HEAD(&bf_q
);
1539 for (i
= 0; tids
&& nframes
; i
++, tids
>>= 1) {
1540 struct ath_atx_tid
*tid
;
1545 tid
= ATH_AN_2_TID(an
, i
);
1549 ath_txq_lock(sc
, tid
->ac
->txq
);
1550 while (nframes
> 0) {
1551 bf
= ath_tx_get_tid_subframe(sc
, sc
->tx
.uapsdq
, tid
, &tid_q
);
1555 __skb_unlink(bf
->bf_mpdu
, tid_q
);
1556 list_add_tail(&bf
->list
, &bf_q
);
1557 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1558 if (bf_isampdu(bf
)) {
1559 ath_tx_addto_baw(sc
, tid
, bf
);
1560 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1563 bf_tail
->bf_next
= bf
;
1568 TX_STAT_INC(txq
->axq_qnum
, a_queued_hw
);
1570 if (an
->sta
&& !ath_tid_has_buffered(tid
))
1571 ieee80211_sta_set_buffered(an
->sta
, i
, false);
1573 ath_txq_unlock_complete(sc
, tid
->ac
->txq
);
1576 if (list_empty(&bf_q
))
1579 info
= IEEE80211_SKB_CB(bf_tail
->bf_mpdu
);
1580 info
->flags
|= IEEE80211_TX_STATUS_EOSP
;
1582 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1583 ath_txq_lock(sc
, txq
);
1584 ath_tx_fill_desc(sc
, bf
, txq
, 0);
1585 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, false);
1586 ath_txq_unlock(sc
, txq
);
1589 /********************/
1590 /* Queue Management */
1591 /********************/
1593 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
1595 struct ath_hw
*ah
= sc
->sc_ah
;
1596 struct ath9k_tx_queue_info qi
;
1597 static const int subtype_txq_to_hwq
[] = {
1598 [IEEE80211_AC_BE
] = ATH_TXQ_AC_BE
,
1599 [IEEE80211_AC_BK
] = ATH_TXQ_AC_BK
,
1600 [IEEE80211_AC_VI
] = ATH_TXQ_AC_VI
,
1601 [IEEE80211_AC_VO
] = ATH_TXQ_AC_VO
,
1605 memset(&qi
, 0, sizeof(qi
));
1606 qi
.tqi_subtype
= subtype_txq_to_hwq
[subtype
];
1607 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
1608 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
1609 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
1610 qi
.tqi_physCompBuf
= 0;
1613 * Enable interrupts only for EOL and DESC conditions.
1614 * We mark tx descriptors to receive a DESC interrupt
1615 * when a tx queue gets deep; otherwise waiting for the
1616 * EOL to reap descriptors. Note that this is done to
1617 * reduce interrupt load and this only defers reaping
1618 * descriptors, never transmitting frames. Aside from
1619 * reducing interrupts this also permits more concurrency.
1620 * The only potential downside is if the tx queue backs
1621 * up in which case the top half of the kernel may backup
1622 * due to a lack of tx descriptors.
1624 * The UAPSD queue is an exception, since we take a desc-
1625 * based intr on the EOSP frames.
1627 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1628 qi
.tqi_qflags
= TXQ_FLAG_TXINT_ENABLE
;
1630 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
1631 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
1633 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
1634 TXQ_FLAG_TXDESCINT_ENABLE
;
1636 axq_qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
1637 if (axq_qnum
== -1) {
1639 * NB: don't print a message, this happens
1640 * normally on parts with too few tx queues
1644 if (!ATH_TXQ_SETUP(sc
, axq_qnum
)) {
1645 struct ath_txq
*txq
= &sc
->tx
.txq
[axq_qnum
];
1647 txq
->axq_qnum
= axq_qnum
;
1648 txq
->mac80211_qnum
= -1;
1649 txq
->axq_link
= NULL
;
1650 __skb_queue_head_init(&txq
->complete_q
);
1651 INIT_LIST_HEAD(&txq
->axq_q
);
1652 INIT_LIST_HEAD(&txq
->axq_acq
);
1653 spin_lock_init(&txq
->axq_lock
);
1655 txq
->axq_ampdu_depth
= 0;
1656 txq
->axq_tx_inprogress
= false;
1657 sc
->tx
.txqsetup
|= 1<<axq_qnum
;
1659 txq
->txq_headidx
= txq
->txq_tailidx
= 0;
1660 for (i
= 0; i
< ATH_TXFIFO_DEPTH
; i
++)
1661 INIT_LIST_HEAD(&txq
->txq_fifo
[i
]);
1663 return &sc
->tx
.txq
[axq_qnum
];
1666 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
1667 struct ath9k_tx_queue_info
*qinfo
)
1669 struct ath_hw
*ah
= sc
->sc_ah
;
1671 struct ath9k_tx_queue_info qi
;
1673 BUG_ON(sc
->tx
.txq
[qnum
].axq_qnum
!= qnum
);
1675 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
1676 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
1677 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
1678 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
1679 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
1680 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
1682 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
1683 ath_err(ath9k_hw_common(sc
->sc_ah
),
1684 "Unable to update hardware queue %u!\n", qnum
);
1687 ath9k_hw_resettxqueue(ah
, qnum
);
1693 int ath_cabq_update(struct ath_softc
*sc
)
1695 struct ath9k_tx_queue_info qi
;
1696 struct ath_beacon_config
*cur_conf
= &sc
->cur_beacon_conf
;
1697 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
1699 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
1701 qi
.tqi_readyTime
= (cur_conf
->beacon_interval
*
1702 ATH_CABQ_READY_TIME
) / 100;
1703 ath_txq_update(sc
, qnum
, &qi
);
1708 static void ath_drain_txq_list(struct ath_softc
*sc
, struct ath_txq
*txq
,
1709 struct list_head
*list
)
1711 struct ath_buf
*bf
, *lastbf
;
1712 struct list_head bf_head
;
1713 struct ath_tx_status ts
;
1715 memset(&ts
, 0, sizeof(ts
));
1716 ts
.ts_status
= ATH9K_TX_FLUSH
;
1717 INIT_LIST_HEAD(&bf_head
);
1719 while (!list_empty(list
)) {
1720 bf
= list_first_entry(list
, struct ath_buf
, list
);
1722 if (bf
->bf_state
.stale
) {
1723 list_del(&bf
->list
);
1725 ath_tx_return_buffer(sc
, bf
);
1729 lastbf
= bf
->bf_lastbf
;
1730 list_cut_position(&bf_head
, list
, &lastbf
->list
);
1731 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
1736 * Drain a given TX queue (could be Beacon or Data)
1738 * This assumes output has been stopped and
1739 * we do not need to block ath_tx_tasklet.
1741 void ath_draintxq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1743 ath_txq_lock(sc
, txq
);
1745 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1746 int idx
= txq
->txq_tailidx
;
1748 while (!list_empty(&txq
->txq_fifo
[idx
])) {
1749 ath_drain_txq_list(sc
, txq
, &txq
->txq_fifo
[idx
]);
1751 INCR(idx
, ATH_TXFIFO_DEPTH
);
1753 txq
->txq_tailidx
= idx
;
1756 txq
->axq_link
= NULL
;
1757 txq
->axq_tx_inprogress
= false;
1758 ath_drain_txq_list(sc
, txq
, &txq
->axq_q
);
1760 ath_txq_unlock_complete(sc
, txq
);
1763 bool ath_drain_all_txq(struct ath_softc
*sc
)
1765 struct ath_hw
*ah
= sc
->sc_ah
;
1766 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1767 struct ath_txq
*txq
;
1771 if (test_bit(SC_OP_INVALID
, &sc
->sc_flags
))
1774 ath9k_hw_abort_tx_dma(ah
);
1776 /* Check if any queue remains active */
1777 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1778 if (!ATH_TXQ_SETUP(sc
, i
))
1781 if (!sc
->tx
.txq
[i
].axq_depth
)
1784 if (ath9k_hw_numtxpending(ah
, sc
->tx
.txq
[i
].axq_qnum
))
1789 ath_err(common
, "Failed to stop TX DMA, queues=0x%03x!\n", npend
);
1791 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1792 if (!ATH_TXQ_SETUP(sc
, i
))
1796 * The caller will resume queues with ieee80211_wake_queues.
1797 * Mark the queue as not stopped to prevent ath_tx_complete
1798 * from waking the queue too early.
1800 txq
= &sc
->tx
.txq
[i
];
1801 txq
->stopped
= false;
1802 ath_draintxq(sc
, txq
);
1808 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1810 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1811 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1814 /* For each axq_acq entry, for each tid, try to schedule packets
1815 * for transmit until ampdu_depth has reached min Q depth.
1817 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
1819 struct ath_atx_ac
*ac
, *last_ac
;
1820 struct ath_atx_tid
*tid
, *last_tid
;
1823 if (test_bit(SC_OP_HW_RESET
, &sc
->sc_flags
) ||
1824 list_empty(&txq
->axq_acq
))
1829 last_ac
= list_entry(txq
->axq_acq
.prev
, struct ath_atx_ac
, list
);
1830 while (!list_empty(&txq
->axq_acq
)) {
1833 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
1834 last_tid
= list_entry(ac
->tid_q
.prev
, struct ath_atx_tid
, list
);
1835 list_del(&ac
->list
);
1838 while (!list_empty(&ac
->tid_q
)) {
1840 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
,
1842 list_del(&tid
->list
);
1848 if (ath_tx_sched_aggr(sc
, txq
, tid
, &stop
))
1852 * add tid to round-robin queue if more frames
1853 * are pending for the tid
1855 if (ath_tid_has_buffered(tid
))
1856 ath_tx_queue_tid(txq
, tid
);
1858 if (stop
|| tid
== last_tid
)
1862 if (!list_empty(&ac
->tid_q
) && !ac
->sched
) {
1864 list_add_tail(&ac
->list
, &txq
->axq_acq
);
1870 if (ac
== last_ac
) {
1875 last_ac
= list_entry(txq
->axq_acq
.prev
,
1876 struct ath_atx_ac
, list
);
1888 * Insert a chain of ath_buf (descriptors) on a txq and
1889 * assume the descriptors are already chained together by caller.
1891 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
1892 struct list_head
*head
, bool internal
)
1894 struct ath_hw
*ah
= sc
->sc_ah
;
1895 struct ath_common
*common
= ath9k_hw_common(ah
);
1896 struct ath_buf
*bf
, *bf_last
;
1897 bool puttxbuf
= false;
1901 * Insert the frame on the outbound list and
1902 * pass it on to the hardware.
1905 if (list_empty(head
))
1908 edma
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
);
1909 bf
= list_first_entry(head
, struct ath_buf
, list
);
1910 bf_last
= list_entry(head
->prev
, struct ath_buf
, list
);
1912 ath_dbg(common
, QUEUE
, "qnum: %d, txq depth: %d\n",
1913 txq
->axq_qnum
, txq
->axq_depth
);
1915 if (edma
&& list_empty(&txq
->txq_fifo
[txq
->txq_headidx
])) {
1916 list_splice_tail_init(head
, &txq
->txq_fifo
[txq
->txq_headidx
]);
1917 INCR(txq
->txq_headidx
, ATH_TXFIFO_DEPTH
);
1920 list_splice_tail_init(head
, &txq
->axq_q
);
1922 if (txq
->axq_link
) {
1923 ath9k_hw_set_desc_link(ah
, txq
->axq_link
, bf
->bf_daddr
);
1924 ath_dbg(common
, XMIT
, "link[%u] (%p)=%llx (%p)\n",
1925 txq
->axq_qnum
, txq
->axq_link
,
1926 ito64(bf
->bf_daddr
), bf
->bf_desc
);
1930 txq
->axq_link
= bf_last
->bf_desc
;
1934 TX_STAT_INC(txq
->axq_qnum
, puttxbuf
);
1935 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
1936 ath_dbg(common
, XMIT
, "TXDP[%u] = %llx (%p)\n",
1937 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
1940 if (!edma
|| sc
->tx99_state
) {
1941 TX_STAT_INC(txq
->axq_qnum
, txstart
);
1942 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
1948 if (bf_is_ampdu_not_probing(bf
))
1949 txq
->axq_ampdu_depth
++;
1951 bf_last
= bf
->bf_lastbf
;
1952 bf
= bf_last
->bf_next
;
1953 bf_last
->bf_next
= NULL
;
1958 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1959 struct ath_atx_tid
*tid
, struct sk_buff
*skb
)
1961 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1962 struct ath_frame_info
*fi
= get_frame_info(skb
);
1963 struct list_head bf_head
;
1964 struct ath_buf
*bf
= fi
->bf
;
1966 INIT_LIST_HEAD(&bf_head
);
1967 list_add_tail(&bf
->list
, &bf_head
);
1968 bf
->bf_state
.bf_type
= 0;
1969 if (tid
&& (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)) {
1970 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1971 ath_tx_addto_baw(sc
, tid
, bf
);
1976 ath_tx_fill_desc(sc
, bf
, txq
, fi
->framelen
);
1977 ath_tx_txqaddbuf(sc
, txq
, &bf_head
, false);
1978 TX_STAT_INC(txq
->axq_qnum
, queued
);
1981 static void setup_frame_info(struct ieee80211_hw
*hw
,
1982 struct ieee80211_sta
*sta
,
1983 struct sk_buff
*skb
,
1986 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1987 struct ieee80211_key_conf
*hw_key
= tx_info
->control
.hw_key
;
1988 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1989 const struct ieee80211_rate
*rate
;
1990 struct ath_frame_info
*fi
= get_frame_info(skb
);
1991 struct ath_node
*an
= NULL
;
1992 enum ath9k_key_type keytype
;
1993 bool short_preamble
= false;
1996 * We check if Short Preamble is needed for the CTS rate by
1997 * checking the BSS's global flag.
1998 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2000 if (tx_info
->control
.vif
&&
2001 tx_info
->control
.vif
->bss_conf
.use_short_preamble
)
2002 short_preamble
= true;
2004 rate
= ieee80211_get_rts_cts_rate(hw
, tx_info
);
2005 keytype
= ath9k_cmn_get_hw_crypto_keytype(skb
);
2008 an
= (struct ath_node
*) sta
->drv_priv
;
2010 memset(fi
, 0, sizeof(*fi
));
2012 fi
->keyix
= hw_key
->hw_key_idx
;
2013 else if (an
&& ieee80211_is_data(hdr
->frame_control
) && an
->ps_key
> 0)
2014 fi
->keyix
= an
->ps_key
;
2016 fi
->keyix
= ATH9K_TXKEYIX_INVALID
;
2017 fi
->keytype
= keytype
;
2018 fi
->framelen
= framelen
;
2022 fi
->rtscts_rate
= rate
->hw_value
;
2024 fi
->rtscts_rate
|= rate
->hw_value_short
;
2027 u8
ath_txchainmask_reduction(struct ath_softc
*sc
, u8 chainmask
, u32 rate
)
2029 struct ath_hw
*ah
= sc
->sc_ah
;
2030 struct ath9k_channel
*curchan
= ah
->curchan
;
2032 if ((ah
->caps
.hw_caps
& ATH9K_HW_CAP_APM
) && IS_CHAN_5GHZ(curchan
) &&
2033 (chainmask
== 0x7) && (rate
< 0x90))
2035 else if (AR_SREV_9462(ah
) && ath9k_hw_btcoex_is_enabled(ah
) &&
2043 * Assign a descriptor (and sequence number if necessary,
2044 * and map buffer for DMA. Frees skb on error
2046 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
2047 struct ath_txq
*txq
,
2048 struct ath_atx_tid
*tid
,
2049 struct sk_buff
*skb
)
2051 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2052 struct ath_frame_info
*fi
= get_frame_info(skb
);
2053 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2058 bf
= ath_tx_get_buffer(sc
);
2060 ath_dbg(common
, XMIT
, "TX buffers are full\n");
2064 ATH_TXBUF_RESET(bf
);
2067 fragno
= le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
;
2068 seqno
= tid
->seq_next
;
2069 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<< IEEE80211_SEQ_SEQ_SHIFT
);
2072 hdr
->seq_ctrl
|= cpu_to_le16(fragno
);
2074 if (!ieee80211_has_morefrags(hdr
->frame_control
))
2075 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
2077 bf
->bf_state
.seqno
= seqno
;
2082 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
2083 skb
->len
, DMA_TO_DEVICE
);
2084 if (unlikely(dma_mapping_error(sc
->dev
, bf
->bf_buf_addr
))) {
2086 bf
->bf_buf_addr
= 0;
2087 ath_err(ath9k_hw_common(sc
->sc_ah
),
2088 "dma_mapping_error() on TX\n");
2089 ath_tx_return_buffer(sc
, bf
);
2098 static int ath_tx_prepare(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2099 struct ath_tx_control
*txctl
)
2101 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2102 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2103 struct ieee80211_sta
*sta
= txctl
->sta
;
2104 struct ieee80211_vif
*vif
= info
->control
.vif
;
2105 struct ath_vif
*avp
;
2106 struct ath_softc
*sc
= hw
->priv
;
2107 int frmlen
= skb
->len
+ FCS_LEN
;
2108 int padpos
, padsize
;
2110 /* NOTE: sta can be NULL according to net/mac80211.h */
2112 txctl
->an
= (struct ath_node
*)sta
->drv_priv
;
2113 else if (vif
&& ieee80211_is_data(hdr
->frame_control
)) {
2114 avp
= (void *)vif
->drv_priv
;
2115 txctl
->an
= &avp
->mcast_node
;
2118 if (info
->control
.hw_key
)
2119 frmlen
+= info
->control
.hw_key
->icv_len
;
2122 * As a temporary workaround, assign seq# here; this will likely need
2123 * to be cleaned up to work better with Beacon transmission and virtual
2126 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
2127 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2128 sc
->tx
.seq_no
+= 0x10;
2129 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2130 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
2133 if ((vif
&& vif
->type
!= NL80211_IFTYPE_AP
&&
2134 vif
->type
!= NL80211_IFTYPE_AP_VLAN
) ||
2135 !ieee80211_is_data(hdr
->frame_control
))
2136 info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
2138 /* Add the padding after the header if this is not already done */
2139 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2140 padsize
= padpos
& 3;
2141 if (padsize
&& skb
->len
> padpos
) {
2142 if (skb_headroom(skb
) < padsize
)
2145 skb_push(skb
, padsize
);
2146 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
2149 setup_frame_info(hw
, sta
, skb
, frmlen
);
2154 /* Upon failure caller should free skb */
2155 int ath_tx_start(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2156 struct ath_tx_control
*txctl
)
2158 struct ieee80211_hdr
*hdr
;
2159 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2160 struct ieee80211_sta
*sta
= txctl
->sta
;
2161 struct ieee80211_vif
*vif
= info
->control
.vif
;
2162 struct ath_softc
*sc
= hw
->priv
;
2163 struct ath_txq
*txq
= txctl
->txq
;
2164 struct ath_atx_tid
*tid
= NULL
;
2169 ret
= ath_tx_prepare(hw
, skb
, txctl
);
2173 hdr
= (struct ieee80211_hdr
*) skb
->data
;
2175 * At this point, the vif, hw_key and sta pointers in the tx control
2176 * info are no longer valid (overwritten by the ath_frame_info data.
2179 q
= skb_get_queue_mapping(skb
);
2181 ath_txq_lock(sc
, txq
);
2182 if (txq
== sc
->tx
.txq_map
[q
] &&
2183 ++txq
->pending_frames
> sc
->tx
.txq_max_pending
[q
] &&
2185 ieee80211_stop_queue(sc
->hw
, q
);
2186 txq
->stopped
= true;
2189 if (info
->flags
& IEEE80211_TX_CTL_PS_RESPONSE
) {
2190 ath_txq_unlock(sc
, txq
);
2191 txq
= sc
->tx
.uapsdq
;
2192 ath_txq_lock(sc
, txq
);
2193 } else if (txctl
->an
&&
2194 ieee80211_is_data_present(hdr
->frame_control
)) {
2195 tid
= ath_get_skb_tid(sc
, txctl
->an
, skb
);
2197 WARN_ON(tid
->ac
->txq
!= txctl
->txq
);
2199 if (info
->flags
& IEEE80211_TX_CTL_CLEAR_PS_FILT
)
2200 tid
->ac
->clear_ps_filter
= true;
2203 * Add this frame to software queue for scheduling later
2206 TX_STAT_INC(txq
->axq_qnum
, a_queued_sw
);
2207 __skb_queue_tail(&tid
->buf_q
, skb
);
2208 if (!txctl
->an
->sleeping
)
2209 ath_tx_queue_tid(txq
, tid
);
2211 ath_txq_schedule(sc
, txq
);
2215 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
2217 ath_txq_skb_done(sc
, txq
, skb
);
2219 dev_kfree_skb_any(skb
);
2221 ieee80211_free_txskb(sc
->hw
, skb
);
2225 bf
->bf_state
.bfs_paprd
= txctl
->paprd
;
2228 bf
->bf_state
.bfs_paprd_timestamp
= jiffies
;
2230 ath_set_rates(vif
, sta
, bf
);
2231 ath_tx_send_normal(sc
, txq
, tid
, skb
);
2234 ath_txq_unlock(sc
, txq
);
2239 void ath_tx_cabq(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2240 struct sk_buff
*skb
)
2242 struct ath_softc
*sc
= hw
->priv
;
2243 struct ath_tx_control txctl
= {
2244 .txq
= sc
->beacon
.cabq
2246 struct ath_tx_info info
= {};
2247 struct ieee80211_hdr
*hdr
;
2248 struct ath_buf
*bf_tail
= NULL
;
2255 sc
->cur_beacon_conf
.beacon_interval
* 1000 *
2256 sc
->cur_beacon_conf
.dtim_period
/ ATH_BCBUF
;
2259 struct ath_frame_info
*fi
= get_frame_info(skb
);
2261 if (ath_tx_prepare(hw
, skb
, &txctl
))
2264 bf
= ath_tx_setup_buffer(sc
, txctl
.txq
, NULL
, skb
);
2269 ath_set_rates(vif
, NULL
, bf
);
2270 ath_buf_set_rate(sc
, bf
, &info
, fi
->framelen
, false);
2271 duration
+= info
.rates
[0].PktDuration
;
2273 bf_tail
->bf_next
= bf
;
2275 list_add_tail(&bf
->list
, &bf_q
);
2279 if (duration
> max_duration
)
2282 skb
= ieee80211_get_buffered_bc(hw
, vif
);
2286 ieee80211_free_txskb(hw
, skb
);
2288 if (list_empty(&bf_q
))
2291 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
2292 hdr
= (struct ieee80211_hdr
*) bf
->bf_mpdu
->data
;
2294 if (hdr
->frame_control
& IEEE80211_FCTL_MOREDATA
) {
2295 hdr
->frame_control
&= ~IEEE80211_FCTL_MOREDATA
;
2296 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
2297 sizeof(*hdr
), DMA_TO_DEVICE
);
2300 ath_txq_lock(sc
, txctl
.txq
);
2301 ath_tx_fill_desc(sc
, bf
, txctl
.txq
, 0);
2302 ath_tx_txqaddbuf(sc
, txctl
.txq
, &bf_q
, false);
2303 TX_STAT_INC(txctl
.txq
->axq_qnum
, queued
);
2304 ath_txq_unlock(sc
, txctl
.txq
);
2311 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
2312 int tx_flags
, struct ath_txq
*txq
)
2314 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2315 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2316 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
2317 int padpos
, padsize
;
2318 unsigned long flags
;
2320 ath_dbg(common
, XMIT
, "TX complete: skb: %p\n", skb
);
2322 if (sc
->sc_ah
->caldata
)
2323 set_bit(PAPRD_PACKET_SENT
, &sc
->sc_ah
->caldata
->cal_flags
);
2325 if (!(tx_flags
& ATH_TX_ERROR
))
2326 /* Frame was ACKed */
2327 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
2329 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2330 padsize
= padpos
& 3;
2331 if (padsize
&& skb
->len
>padpos
+padsize
) {
2333 * Remove MAC header padding before giving the frame back to
2336 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
2337 skb_pull(skb
, padsize
);
2340 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
2341 if ((sc
->ps_flags
& PS_WAIT_FOR_TX_ACK
) && !txq
->axq_depth
) {
2342 sc
->ps_flags
&= ~PS_WAIT_FOR_TX_ACK
;
2344 "Going back to sleep after having received TX status (0x%lx)\n",
2345 sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
2347 PS_WAIT_FOR_PSPOLL_DATA
|
2348 PS_WAIT_FOR_TX_ACK
));
2350 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
2352 __skb_queue_tail(&txq
->complete_q
, skb
);
2353 ath_txq_skb_done(sc
, txq
, skb
);
2356 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
2357 struct ath_txq
*txq
, struct list_head
*bf_q
,
2358 struct ath_tx_status
*ts
, int txok
)
2360 struct sk_buff
*skb
= bf
->bf_mpdu
;
2361 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2362 unsigned long flags
;
2366 tx_flags
|= ATH_TX_ERROR
;
2368 if (ts
->ts_status
& ATH9K_TXERR_FILT
)
2369 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
2371 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
, skb
->len
, DMA_TO_DEVICE
);
2372 bf
->bf_buf_addr
= 0;
2374 goto skip_tx_complete
;
2376 if (bf
->bf_state
.bfs_paprd
) {
2377 if (time_after(jiffies
,
2378 bf
->bf_state
.bfs_paprd_timestamp
+
2379 msecs_to_jiffies(ATH_PAPRD_TIMEOUT
)))
2380 dev_kfree_skb_any(skb
);
2382 complete(&sc
->paprd_complete
);
2384 ath_debug_stat_tx(sc
, bf
, ts
, txq
, tx_flags
);
2385 ath_tx_complete(sc
, skb
, tx_flags
, txq
);
2388 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2389 * accidentally reference it later.
2394 * Return the list of ath_buf of this mpdu to free queue
2396 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
2397 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
2398 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
2401 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
2402 struct ath_tx_status
*ts
, int nframes
, int nbad
,
2405 struct sk_buff
*skb
= bf
->bf_mpdu
;
2406 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2407 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2408 struct ieee80211_hw
*hw
= sc
->hw
;
2409 struct ath_hw
*ah
= sc
->sc_ah
;
2413 tx_info
->status
.ack_signal
= ts
->ts_rssi
;
2415 tx_rateindex
= ts
->ts_rateindex
;
2416 WARN_ON(tx_rateindex
>= hw
->max_rates
);
2418 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
2419 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
2421 BUG_ON(nbad
> nframes
);
2423 tx_info
->status
.ampdu_len
= nframes
;
2424 tx_info
->status
.ampdu_ack_len
= nframes
- nbad
;
2426 if ((ts
->ts_status
& ATH9K_TXERR_FILT
) == 0 &&
2427 (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
) == 0) {
2429 * If an underrun error is seen assume it as an excessive
2430 * retry only if max frame trigger level has been reached
2431 * (2 KB for single stream, and 4 KB for dual stream).
2432 * Adjust the long retry as if the frame was tried
2433 * hw->max_rate_tries times to affect how rate control updates
2434 * PER for the failed rate.
2435 * In case of congestion on the bus penalizing this type of
2436 * underruns should help hardware actually transmit new frames
2437 * successfully by eventually preferring slower rates.
2438 * This itself should also alleviate congestion on the bus.
2440 if (unlikely(ts
->ts_flags
& (ATH9K_TX_DATA_UNDERRUN
|
2441 ATH9K_TX_DELIM_UNDERRUN
)) &&
2442 ieee80211_is_data(hdr
->frame_control
) &&
2443 ah
->tx_trig_level
>= sc
->sc_ah
->config
.max_txtrig_level
)
2444 tx_info
->status
.rates
[tx_rateindex
].count
=
2448 for (i
= tx_rateindex
+ 1; i
< hw
->max_rates
; i
++) {
2449 tx_info
->status
.rates
[i
].count
= 0;
2450 tx_info
->status
.rates
[i
].idx
= -1;
2453 tx_info
->status
.rates
[tx_rateindex
].count
= ts
->ts_longretry
+ 1;
2456 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2458 struct ath_hw
*ah
= sc
->sc_ah
;
2459 struct ath_common
*common
= ath9k_hw_common(ah
);
2460 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
2461 struct list_head bf_head
;
2462 struct ath_desc
*ds
;
2463 struct ath_tx_status ts
;
2466 ath_dbg(common
, QUEUE
, "tx queue %d (%x), link %p\n",
2467 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
2470 ath_txq_lock(sc
, txq
);
2472 if (test_bit(SC_OP_HW_RESET
, &sc
->sc_flags
))
2475 if (list_empty(&txq
->axq_q
)) {
2476 txq
->axq_link
= NULL
;
2477 ath_txq_schedule(sc
, txq
);
2480 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2483 * There is a race condition that a BH gets scheduled
2484 * after sw writes TxE and before hw re-load the last
2485 * descriptor to get the newly chained one.
2486 * Software must keep the last DONE descriptor as a
2487 * holding descriptor - software does so by marking
2488 * it with the STALE flag.
2491 if (bf
->bf_state
.stale
) {
2493 if (list_is_last(&bf_held
->list
, &txq
->axq_q
))
2496 bf
= list_entry(bf_held
->list
.next
, struct ath_buf
,
2500 lastbf
= bf
->bf_lastbf
;
2501 ds
= lastbf
->bf_desc
;
2503 memset(&ts
, 0, sizeof(ts
));
2504 status
= ath9k_hw_txprocdesc(ah
, ds
, &ts
);
2505 if (status
== -EINPROGRESS
)
2508 TX_STAT_INC(txq
->axq_qnum
, txprocdesc
);
2511 * Remove ath_buf's of the same transmit unit from txq,
2512 * however leave the last descriptor back as the holding
2513 * descriptor for hw.
2515 lastbf
->bf_state
.stale
= true;
2516 INIT_LIST_HEAD(&bf_head
);
2517 if (!list_is_singular(&lastbf
->list
))
2518 list_cut_position(&bf_head
,
2519 &txq
->axq_q
, lastbf
->list
.prev
);
2522 list_del(&bf_held
->list
);
2523 ath_tx_return_buffer(sc
, bf_held
);
2526 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2528 ath_txq_unlock_complete(sc
, txq
);
2531 void ath_tx_tasklet(struct ath_softc
*sc
)
2533 struct ath_hw
*ah
= sc
->sc_ah
;
2534 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1) & ah
->intr_txqs
;
2537 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2538 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2539 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2543 void ath_tx_edma_tasklet(struct ath_softc
*sc
)
2545 struct ath_tx_status ts
;
2546 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2547 struct ath_hw
*ah
= sc
->sc_ah
;
2548 struct ath_txq
*txq
;
2549 struct ath_buf
*bf
, *lastbf
;
2550 struct list_head bf_head
;
2551 struct list_head
*fifo_list
;
2555 if (test_bit(SC_OP_HW_RESET
, &sc
->sc_flags
))
2558 status
= ath9k_hw_txprocdesc(ah
, NULL
, (void *)&ts
);
2559 if (status
== -EINPROGRESS
)
2561 if (status
== -EIO
) {
2562 ath_dbg(common
, XMIT
, "Error processing tx status\n");
2566 /* Process beacon completions separately */
2567 if (ts
.qid
== sc
->beacon
.beaconq
) {
2568 sc
->beacon
.tx_processed
= true;
2569 sc
->beacon
.tx_last
= !(ts
.ts_status
& ATH9K_TXERR_MASK
);
2571 ath9k_csa_is_finished(sc
);
2575 txq
= &sc
->tx
.txq
[ts
.qid
];
2577 ath_txq_lock(sc
, txq
);
2579 TX_STAT_INC(txq
->axq_qnum
, txprocdesc
);
2581 fifo_list
= &txq
->txq_fifo
[txq
->txq_tailidx
];
2582 if (list_empty(fifo_list
)) {
2583 ath_txq_unlock(sc
, txq
);
2587 bf
= list_first_entry(fifo_list
, struct ath_buf
, list
);
2588 if (bf
->bf_state
.stale
) {
2589 list_del(&bf
->list
);
2590 ath_tx_return_buffer(sc
, bf
);
2591 bf
= list_first_entry(fifo_list
, struct ath_buf
, list
);
2594 lastbf
= bf
->bf_lastbf
;
2596 INIT_LIST_HEAD(&bf_head
);
2597 if (list_is_last(&lastbf
->list
, fifo_list
)) {
2598 list_splice_tail_init(fifo_list
, &bf_head
);
2599 INCR(txq
->txq_tailidx
, ATH_TXFIFO_DEPTH
);
2601 if (!list_empty(&txq
->axq_q
)) {
2602 struct list_head bf_q
;
2604 INIT_LIST_HEAD(&bf_q
);
2605 txq
->axq_link
= NULL
;
2606 list_splice_tail_init(&txq
->axq_q
, &bf_q
);
2607 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, true);
2610 lastbf
->bf_state
.stale
= true;
2612 list_cut_position(&bf_head
, fifo_list
,
2616 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2617 ath_txq_unlock_complete(sc
, txq
);
2625 static int ath_txstatus_setup(struct ath_softc
*sc
, int size
)
2627 struct ath_descdma
*dd
= &sc
->txsdma
;
2628 u8 txs_len
= sc
->sc_ah
->caps
.txs_len
;
2630 dd
->dd_desc_len
= size
* txs_len
;
2631 dd
->dd_desc
= dmam_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
2632 &dd
->dd_desc_paddr
, GFP_KERNEL
);
2639 static int ath_tx_edma_init(struct ath_softc
*sc
)
2643 err
= ath_txstatus_setup(sc
, ATH_TXSTATUS_RING_SIZE
);
2645 ath9k_hw_setup_statusring(sc
->sc_ah
, sc
->txsdma
.dd_desc
,
2646 sc
->txsdma
.dd_desc_paddr
,
2647 ATH_TXSTATUS_RING_SIZE
);
2652 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2654 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2657 spin_lock_init(&sc
->tx
.txbuflock
);
2659 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
2663 "Failed to allocate tx descriptors: %d\n", error
);
2667 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
2668 "beacon", ATH_BCBUF
, 1, 1);
2671 "Failed to allocate beacon descriptors: %d\n", error
);
2675 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath_tx_complete_poll_work
);
2677 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
2678 error
= ath_tx_edma_init(sc
);
2683 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2685 struct ath_atx_tid
*tid
;
2686 struct ath_atx_ac
*ac
;
2689 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2690 tidno
< IEEE80211_NUM_TIDS
;
2694 tid
->seq_start
= tid
->seq_next
= 0;
2695 tid
->baw_size
= WME_MAX_BA
;
2696 tid
->baw_head
= tid
->baw_tail
= 0;
2698 tid
->paused
= false;
2699 tid
->active
= false;
2700 __skb_queue_head_init(&tid
->buf_q
);
2701 __skb_queue_head_init(&tid
->retry_q
);
2702 acno
= TID_TO_WME_AC(tidno
);
2703 tid
->ac
= &an
->ac
[acno
];
2706 for (acno
= 0, ac
= &an
->ac
[acno
];
2707 acno
< IEEE80211_NUM_ACS
; acno
++, ac
++) {
2709 ac
->clear_ps_filter
= true;
2710 ac
->txq
= sc
->tx
.txq_map
[acno
];
2711 INIT_LIST_HEAD(&ac
->tid_q
);
2715 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2717 struct ath_atx_ac
*ac
;
2718 struct ath_atx_tid
*tid
;
2719 struct ath_txq
*txq
;
2722 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2723 tidno
< IEEE80211_NUM_TIDS
; tidno
++, tid
++) {
2728 ath_txq_lock(sc
, txq
);
2731 list_del(&tid
->list
);
2736 list_del(&ac
->list
);
2737 tid
->ac
->sched
= false;
2740 ath_tid_drain(sc
, txq
, tid
);
2741 tid
->active
= false;
2743 ath_txq_unlock(sc
, txq
);
2747 #ifdef CONFIG_ATH9K_TX99
2749 int ath9k_tx99_send(struct ath_softc
*sc
, struct sk_buff
*skb
,
2750 struct ath_tx_control
*txctl
)
2752 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2753 struct ath_frame_info
*fi
= get_frame_info(skb
);
2754 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2756 int padpos
, padsize
;
2758 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2759 padsize
= padpos
& 3;
2761 if (padsize
&& skb
->len
> padpos
) {
2762 if (skb_headroom(skb
) < padsize
) {
2763 ath_dbg(common
, XMIT
,
2764 "tx99 padding failed\n");
2768 skb_push(skb
, padsize
);
2769 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
2772 fi
->keyix
= ATH9K_TXKEYIX_INVALID
;
2773 fi
->framelen
= skb
->len
+ FCS_LEN
;
2774 fi
->keytype
= ATH9K_KEY_TYPE_CLEAR
;
2776 bf
= ath_tx_setup_buffer(sc
, txctl
->txq
, NULL
, skb
);
2778 ath_dbg(common
, XMIT
, "tx99 buffer setup failed\n");
2782 ath_set_rates(sc
->tx99_vif
, NULL
, bf
);
2784 ath9k_hw_set_desc_link(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_daddr
);
2785 ath9k_hw_tx99_start(sc
->sc_ah
, txctl
->txq
->axq_qnum
);
2787 ath_tx_send_normal(sc
, txctl
->txq
, NULL
, skb
);
2792 #endif /* CONFIG_ATH9K_TX99 */