2 * Copyright (c) 2012-2016,2018-2019, The Linux Foundation. All rights reserved.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef WIL6210_TXRX_EDMA_H
18 #define WIL6210_TXRX_EDMA_H
22 /* limit status ring size in range [ring size..max ring size] */
23 #define WIL_SRING_SIZE_ORDER_MIN (WIL_RING_SIZE_ORDER_MIN)
24 #define WIL_SRING_SIZE_ORDER_MAX (WIL_RING_SIZE_ORDER_MAX)
25 /* RX sring order should be bigger than RX ring order */
26 #define WIL_RX_SRING_SIZE_ORDER_DEFAULT (12)
27 #define WIL_TX_SRING_SIZE_ORDER_DEFAULT (14)
28 #define WIL_RX_BUFF_ARR_SIZE_DEFAULT (2600)
30 #define WIL_DEFAULT_RX_STATUS_RING_ID 0
31 #define WIL_RX_DESC_RING_ID 0
32 #define WIL_RX_STATUS_IRQ_IDX 0
33 #define WIL_TX_STATUS_IRQ_IDX 1
35 #define WIL_EDMA_AGG_WATERMARK (0xffff)
36 #define WIL_EDMA_AGG_WATERMARK_POS (16)
38 #define WIL_EDMA_IDLE_TIME_LIMIT_USEC (50)
39 #define WIL_EDMA_TIME_UNIT_CLK_CYCLES (330) /* fits 1 usec */
42 #define WIL_RX_EDMA_ERROR_MIC (1)
43 #define WIL_RX_EDMA_ERROR_KEY (2) /* Key missing */
44 #define WIL_RX_EDMA_ERROR_REPLAY (3)
45 #define WIL_RX_EDMA_ERROR_AMSDU (4)
46 #define WIL_RX_EDMA_ERROR_FCS (7)
48 #define WIL_RX_EDMA_ERROR_L3_ERR (BIT(0) | BIT(1))
49 #define WIL_RX_EDMA_ERROR_L4_ERR (BIT(0) | BIT(1))
51 #define WIL_RX_EDMA_DLPF_LU_MISS_BIT BIT(11)
52 #define WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK 0x7
53 #define WIL_RX_EDMA_DLPF_LU_HIT_CID_TID_MASK 0xf
55 #define WIL_RX_EDMA_DLPF_LU_MISS_CID_POS 2
56 #define WIL_RX_EDMA_DLPF_LU_HIT_CID_POS 4
58 #define WIL_RX_EDMA_DLPF_LU_MISS_TID_POS 5
60 #define WIL_RX_EDMA_MID_VALID_BIT BIT(22)
62 #define WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS 16
63 #define WIL_EDMA_DESC_TX_MAC_CFG_0_QID_LEN 6
65 #define WIL_EDMA_DESC_TX_CFG_EOP_POS 0
66 #define WIL_EDMA_DESC_TX_CFG_EOP_LEN 1
68 #define WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS 3
69 #define WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_LEN 2
71 #define WIL_EDMA_DESC_TX_CFG_SEG_EN_POS 5
72 #define WIL_EDMA_DESC_TX_CFG_SEG_EN_LEN 1
74 #define WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS 6
75 #define WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_LEN 1
77 #define WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS 7
78 #define WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_LEN 1
80 #define WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS 15
81 #define WIL_EDMA_DESC_TX_CFG_L4_TYPE_LEN 1
83 #define WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS 5
84 #define WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_LEN 1
86 /* Enhanced Rx descriptor - MAC part
87 * [dword 0] : Reserved
88 * [dword 1] : Reserved
89 * [dword 2] : Reserved
91 * bit 0..15 : Buffer ID
92 * bit 16..31 : Reserved
94 struct wil_ring_rx_enhanced_mac
{
100 /* Enhanced Rx descriptor - DMA part
101 * [dword 0] - Reserved
103 * bit 0..31 : addr_low:32 The payload buffer address, bits 0-31
105 * bit 0..15 : addr_high_low:16 The payload buffer address, bits 32-47
106 * bit 16..31 : Reserved
108 * bit 0..15 : addr_high_high:16 The payload buffer address, bits 48-63
109 * bit 16..31 : length
111 struct wil_ring_rx_enhanced_dma
{
113 struct wil_ring_dma_addr addr
;
115 __le16 addr_high_high
;
119 struct wil_rx_enhanced_desc
{
120 struct wil_ring_rx_enhanced_mac mac
;
121 struct wil_ring_rx_enhanced_dma dma
;
124 /* Enhanced Tx descriptor - DMA part
128 * bit 0..31 : addr_low:32 The payload buffer address, bits 0-31
130 * bit 0..15 : addr_high_low:16 The payload buffer address, bits 32-47
131 * bit 16..23 : ip_length:8 The IP header length for the TX IP checksum
133 * bit 24..30 : mac_length:7
134 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6
136 * bit 0..15 : addr_high_high:16 The payload buffer address, bits 48-63
137 * bit 16..31 : length
139 struct wil_ring_tx_enhanced_dma
{
143 struct wil_ring_dma_addr addr
;
145 u8 b11
; /* 0..6: mac_length; 7:ip_version */
146 __le16 addr_high_high
;
150 /* Enhanced Tx descriptor - MAC part
152 * bit 0.. 9 : lifetime_expiry_value:10
153 * bit 10 : interrupt_en:1
154 * bit 11 : status_en:1
155 * bit 12..13 : txss_override:2
156 * bit 14 : timestamp_insertion:1
157 * bit 15 : duration_preserve:1
158 * bit 16..21 : reserved0:6
159 * bit 22..26 : mcs_index:5
161 * bit 28..30 : reserved1:3
162 * bit 31 : sn_preserved:1
164 * bit 0.. 3 : pkt_mode:4
165 * bit 4 : pkt_mode_en:1
166 * bit 5..14 : reserved0:10
167 * bit 15 : ack_policy_en:1
168 * bit 16..19 : dst_index:4
169 * bit 20 : dst_index_en:1
170 * bit 21..22 : ack_policy:2
171 * bit 23 : lifetime_en:1
172 * bit 24..30 : max_retry:7
173 * bit 31 : max_retry_en:1
175 * bit 0.. 7 : num_of_descriptors:8
176 * bit 8..17 : reserved:10
177 * bit 18..19 : l2_translation_type:2 00 - bypass, 01 - 802.3, 10 - 802.11
178 * bit 20 : snap_hdr_insertion_en:1
179 * bit 21 : vlan_removal_en:1
180 * bit 22..23 : reserved0:2
181 * bit 24 : Dest ID extension:1
182 * bit 25..31 : reserved0:7
184 * bit 0..15 : tso_mss:16
185 * bit 16..31 : descriptor_scratchpad:16 - mailbox between driver and ucode
187 struct wil_ring_tx_enhanced_mac
{
193 struct wil_tx_enhanced_desc
{
194 struct wil_ring_tx_enhanced_mac mac
;
195 struct wil_ring_tx_enhanced_dma dma
;
198 #define TX_STATUS_DESC_READY_POS 7
200 /* Enhanced TX status message
202 * bit 0.. 7 : Number of Descriptor:8 - The number of descriptors that
203 * are used to form the packets. It is needed for WB when
204 * releasing the packet
205 * bit 8..15 : tx_ring_id:8 The transmission ring ID that is related to
207 * bit 16..23 : Status:8 - The TX status Code
208 * 0x0 - A successful transmission
209 * 0x1 - Retry expired
210 * 0x2 - Lifetime Expired
212 * 0x4-0xFF - Reserved
213 * bit 24..30 : Reserved:7
214 * bit 31 : Descriptor Ready bit:1 - It is initiated to
215 * zero by the driver when the ring is created. It is set by the HW
216 * to one for each completed status message. Each wrap around,
217 * the DR bit value is flipped.
219 * bit 0..31 : timestamp:32 - Set when MPDU is transmitted.
221 * bit 0.. 4 : MCS:5 - The transmitted MCS value
223 * bit 6.. 7 : CB mode:2 - 0-DMG 1-EDMG 2-Wide
224 * bit 8..12 : QID:5 - The QID that was used for the transmission
225 * bit 13..15 : Reserved:3
226 * bit 16..20 : Num of MSDUs:5 - Number of MSDUs in the aggregation
227 * bit 21..22 : Reserved:2
228 * bit 23 : Retry:1 - An indication that the transmission was retried
229 * bit 24..31 : TX-Sector:8 - the antenna sector that was used for
232 * bit 0..11 : Sequence number:12 - The Sequence Number that was used
233 * for the MPDU transmission
234 * bit 12..31 : Reserved:20
236 struct wil_ring_tx_status
{
240 u8 desc_ready
; /* Only the last bit should be set */
243 u16 seq_number
; /* Only the first 12 bits */
247 /* Enhanced Rx status message - compressed part
249 * bit 0.. 2 : L2 Rx Status:3 - The L2 packet reception Status
250 * 0-Success, 1-MIC Error, 2-Key Error, 3-Replay Error,
251 * 4-A-MSDU Error, 5-Reserved, 6-Reserved, 7-FCS Error
252 * bit 3.. 4 : L3 Rx Status:2 - Bit0 - L3I - L3 identified and checksum
253 * calculated, Bit1- L3Err - IPv4 Checksum Error
254 * bit 5.. 6 : L4 Rx Status:2 - Bit0 - L4I - L4 identified and checksum
255 * calculated, Bit1- L4Err - TCP/UDP Checksum Error
257 * bit 8..19 : Flow ID:12 - MSDU flow ID
258 * bit 20..21 : MID:2 - The MAC ID
259 * bit 22 : MID_V:1 - The MAC ID field is valid
260 * bit 23 : L3T:1 - IP types: 0-IPv6, 1-IPv4
261 * bit 24 : L4T:1 - Layer 4 Type: 0-UDP, 1-TCP
262 * bit 25 : BC:1 - The received MPDU is broadcast
263 * bit 26 : MC:1 - The received MPDU is multicast
264 * bit 27 : Raw:1 - The MPDU received with no translation
265 * bit 28 : Sec:1 - The FC control (b14) - Frame Protected
266 * bit 29 : Error:1 - An error is set when (L2 status != 0) ||
267 * (L3 status == 3) || (L4 status == 3)
268 * bit 30 : EOP:1 - End of MSDU signaling. It is set to mark the end
269 * of the transfer, otherwise the status indicates buffer
271 * bit 31 : Descriptor Ready bit:1 - It is initiated to
272 * zero by the driver when the ring is created. It is set
273 * by the HW to one for each completed status message.
274 * Each wrap around, the DR bit value is flipped.
276 * bit 0.. 5 : MAC Len:6 - The number of bytes that are used for L2 header
277 * bit 6..11 : IPLEN:6 - The number of DW that are used for L3 header
278 * bit 12..15 : I4Len:4 - The number of DW that are used for L4 header
279 * bit 16..21 : MCS:6 - The received MCS field from the PLCP Header
280 * bit 22..23 : CB mode:2 - The CB Mode: 0-DMG, 1-EDMG, 2-Wide
281 * bit 24..27 : Data Offset:4 - The data offset, a code that describe the
282 * payload shift from the beginning of the buffer:
283 * 0 - 0 Bytes, 3 - 2 Bytes
284 * bit 28 : A-MSDU Present:1 - The QoS (b7) A-MSDU present field
285 * bit 29 : A-MSDU Type:1 The QoS (b8) A-MSDU Type field
286 * bit 30 : A-MPDU:1 - Packet is part of aggregated MPDU
287 * bit 31 : Key ID:1 - The extracted Key ID from the encryption header
289 * bit 0..15 : Buffer ID:16 - The Buffer Identifier
290 * bit 16..31 : Length:16 - It indicates the valid bytes that are stored
291 * in the current descriptor buffer. For multiple buffer
292 * descriptor, SW need to sum the total descriptor length
293 * in all buffers to produce the packet length
295 * bit 0..31 : timestamp:32 - The MPDU Timestamp.
297 struct wil_rx_status_compressed
{
305 /* Enhanced Rx status message - extension part
307 * bit 0.. 4 : QID:5 - The Queue Identifier that the packet is received
309 * bit 5.. 7 : Reserved:3
310 * bit 8..11 : TID:4 - The QoS (b3-0) TID Field
311 * bit 12..15 Source index:4 - The Source index that was found
312 during Parsing the TA. This field is used to define the
314 * bit 16..18 : Destination index:3 - The Destination index that
315 was found during Parsing the RA.
316 * bit 19..20 : DS Type:2 - The FC Control (b9-8) - From / To DS
317 * bit 21..22 : MIC ICR:2 - this signal tells the DMA to assert an
318 interrupt after it writes the packet
319 * bit 23 : ESOP:1 - The QoS (b4) ESOP field
321 * bit 25..31 : Reserved:7
323 * bit 0.. 1 : Frame Type:2 - The FC Control (b3-2) - MPDU Type
324 (management, data, control and extension)
325 * bit 2.. 5 : Syb type:4 - The FC Control (b7-4) - Frame Subtype
326 * bit 6..11 : Ext sub type:6 - The FC Control (b11-8) - Frame Extended
328 * bit 12..13 : ACK Policy:2 - The QoS (b6-5) ACK Policy fields
329 * bit 14 : DECRYPT_BYP:1 - The MPDU is bypass by the decryption unit
330 * bit 15..23 : Reserved:9
331 * bit 24..31 : RSSI/SNR:8 - The RSSI / SNR measurement for the received
334 * bit 0..11 : SN:12 - The received Sequence number field
335 * bit 12..15 : Reserved:4
336 * bit 16..31 : PN bits [15:0]:16
338 * bit 0..31 : PN bits [47:16]:32
340 struct wil_rx_status_extension
{
343 __le16 seq_num
; /* only lower 12 bits */
348 struct wil_rx_status_extended
{
349 struct wil_rx_status_compressed comp
;
350 struct wil_rx_status_extension ext
;
353 static inline void *wil_skb_rxstatus(struct sk_buff
*skb
)
355 return (void *)skb
->cb
;
358 static inline __le16
wil_rx_status_get_length(void *msg
)
360 return ((struct wil_rx_status_compressed
*)msg
)->length
;
363 static inline u8
wil_rx_status_get_mcs(void *msg
)
365 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d1
,
369 static inline u8
wil_rx_status_get_cb_mode(void *msg
)
371 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d1
,
375 static inline u16
wil_rx_status_get_flow_id(void *msg
)
377 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d0
,
381 static inline u8
wil_rx_status_get_mcast(void *msg
)
383 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d0
,
388 * In case of DLPF miss the parsing of flow Id should be as follows:
397 static inline u8
wil_rx_status_get_cid(void *msg
)
399 u16 val
= wil_rx_status_get_flow_id(msg
);
401 if (val
& WIL_RX_EDMA_DLPF_LU_MISS_BIT
)
402 /* CID is in bits 2..4 */
403 return (val
>> WIL_RX_EDMA_DLPF_LU_MISS_CID_POS
) &
404 WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK
;
406 /* CID is in bits 4..7 */
407 return (val
>> WIL_RX_EDMA_DLPF_LU_HIT_CID_POS
) &
408 WIL_RX_EDMA_DLPF_LU_HIT_CID_TID_MASK
;
411 static inline u8
wil_rx_status_get_tid(void *msg
)
413 u16 val
= wil_rx_status_get_flow_id(msg
);
415 if (val
& WIL_RX_EDMA_DLPF_LU_MISS_BIT
)
416 /* TID is in bits 5..7 */
417 return (val
>> WIL_RX_EDMA_DLPF_LU_MISS_TID_POS
) &
418 WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK
;
420 /* TID is in bits 0..3 */
421 return val
& WIL_RX_EDMA_DLPF_LU_MISS_CID_TID_MASK
;
424 static inline int wil_rx_status_get_eop(void *msg
) /* EoP = End of Packet */
426 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d0
,
430 static inline void wil_rx_status_reset_buff_id(struct wil_status_ring
*s
)
432 ((struct wil_rx_status_compressed
*)
433 (s
->va
+ (s
->elem_size
* s
->swhead
)))->buff_id
= 0;
436 static inline __le16
wil_rx_status_get_buff_id(void *msg
)
438 return ((struct wil_rx_status_compressed
*)msg
)->buff_id
;
441 static inline u8
wil_rx_status_get_data_offset(void *msg
)
443 u8 val
= WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d1
,
449 default: return 0xFF;
453 static inline int wil_rx_status_get_frame_type(struct wil6210_priv
*wil
,
456 if (wil
->use_compressed_rx_status
)
457 return IEEE80211_FTYPE_DATA
;
459 return WIL_GET_BITS(((struct wil_rx_status_extended
*)msg
)->ext
.d1
,
463 static inline int wil_rx_status_get_fc1(struct wil6210_priv
*wil
, void *msg
)
465 if (wil
->use_compressed_rx_status
)
468 return WIL_GET_BITS(((struct wil_rx_status_extended
*)msg
)->ext
.d1
,
472 static inline __le16
wil_rx_status_get_seq(struct wil6210_priv
*wil
, void *msg
)
474 if (wil
->use_compressed_rx_status
)
477 return ((struct wil_rx_status_extended
*)msg
)->ext
.seq_num
;
480 static inline u8
wil_rx_status_get_retry(void *msg
)
482 /* retry bit is missing in EDMA HW. return 1 to be on the safe side */
486 static inline int wil_rx_status_get_mid(void *msg
)
488 if (!(((struct wil_rx_status_compressed
*)msg
)->d0
&
489 WIL_RX_EDMA_MID_VALID_BIT
))
490 return 0; /* use the default MID */
492 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d0
,
496 static inline int wil_rx_status_get_error(void *msg
)
498 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d0
,
502 static inline int wil_rx_status_get_l2_rx_status(void *msg
)
504 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d0
,
508 static inline int wil_rx_status_get_l3_rx_status(void *msg
)
510 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d0
,
514 static inline int wil_rx_status_get_l4_rx_status(void *msg
)
516 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d0
,
520 /* L4 L3 Expected result
521 * 0 0 Ok. No L3 and no L4 known protocols found.
522 * Treated as L2 packet. (no offloads on this packet)
523 * 0 1 Ok. It means that L3 was found, and checksum check passed.
524 * No known L4 protocol was found.
525 * 0 2 It means that L3 protocol was found, and checksum check failed.
526 * No L4 known protocol was found.
527 * 1 any Ok. It means that L4 was found, and checksum check passed.
528 * 3 0 Not a possible scenario.
529 * 3 1 Recalculate. It means that L3 protocol was found, and checksum
530 * passed. But L4 checksum failed. Need to see if really failed,
531 * or due to fragmentation.
532 * 3 2 Both L3 and L4 checksum check failed.
534 static inline int wil_rx_status_get_checksum(void *msg
,
535 struct wil_net_stats
*stats
)
537 int l3_rx_status
= wil_rx_status_get_l3_rx_status(msg
);
538 int l4_rx_status
= wil_rx_status_get_l4_rx_status(msg
);
540 if (l4_rx_status
== 1)
541 return CHECKSUM_UNNECESSARY
;
543 if (l4_rx_status
== 0 && l3_rx_status
== 1)
544 return CHECKSUM_UNNECESSARY
;
546 if (l3_rx_status
== 0 && l4_rx_status
== 0)
548 return CHECKSUM_NONE
;
550 /* If HW reports bad checksum, let IP stack re-check it
551 * For example, HW doesn't understand Microsoft IP stack that
552 * mis-calculates TCP checksum - if it should be 0x0,
553 * it writes 0xffff in violation of RFC 1624
555 stats
->rx_csum_err
++;
556 return CHECKSUM_NONE
;
559 static inline int wil_rx_status_get_security(void *msg
)
561 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d0
,
565 static inline u8
wil_rx_status_get_key_id(void *msg
)
567 return WIL_GET_BITS(((struct wil_rx_status_compressed
*)msg
)->d1
,
571 static inline u8
wil_tx_status_get_mcs(struct wil_ring_tx_status
*msg
)
573 return WIL_GET_BITS(msg
->d2
, 0, 4);
576 static inline u32
wil_ring_next_head(struct wil_ring
*ring
)
578 return (ring
->swhead
+ 1) % ring
->size
;
581 static inline void wil_desc_set_addr_edma(struct wil_ring_dma_addr
*addr
,
582 __le16
*addr_high_high
,
585 addr
->addr_low
= cpu_to_le32(lower_32_bits(pa
));
586 addr
->addr_high
= cpu_to_le16((u16
)upper_32_bits(pa
));
587 *addr_high_high
= cpu_to_le16((u16
)(upper_32_bits(pa
) >> 16));
591 dma_addr_t
wil_tx_desc_get_addr_edma(struct wil_ring_tx_enhanced_dma
*dma
)
593 return le32_to_cpu(dma
->addr
.addr_low
) |
594 ((u64
)le16_to_cpu(dma
->addr
.addr_high
) << 32) |
595 ((u64
)le16_to_cpu(dma
->addr_high_high
) << 48);
599 dma_addr_t
wil_rx_desc_get_addr_edma(struct wil_ring_rx_enhanced_dma
*dma
)
601 return le32_to_cpu(dma
->addr
.addr_low
) |
602 ((u64
)le16_to_cpu(dma
->addr
.addr_high
) << 32) |
603 ((u64
)le16_to_cpu(dma
->addr_high_high
) << 48);
606 void wil_configure_interrupt_moderation_edma(struct wil6210_priv
*wil
);
607 int wil_tx_sring_handler(struct wil6210_priv
*wil
,
608 struct wil_status_ring
*sring
);
609 void wil_rx_handle_edma(struct wil6210_priv
*wil
, int *quota
);
610 void wil_init_txrx_ops_edma(struct wil6210_priv
*wil
);
612 #endif /* WIL6210_TXRX_EDMA_H */