2 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/netdevice.h>
21 #include <linux/wireless.h>
22 #include <net/cfg80211.h>
23 #include <linux/timex.h>
24 #include <linux/types.h>
25 #include "wil_platform.h"
27 extern bool no_fw_recovery
;
28 extern unsigned int mtu_max
;
29 extern unsigned short rx_ring_overflow_thrsh
;
31 extern u32 vring_idle_trsh
;
32 extern bool rx_align_2
;
35 #define WIL_NAME "wil6210"
36 #define WIL_FW_NAME "wil6210.fw" /* code */
37 #define WIL_FW2_NAME "wil6210.brd" /* board & radio parameters */
39 #define WIL_MAX_BUS_REQUEST_KBPS 800000 /* ~6.1Gbps */
42 * extract bits [@b0:@b1] (inclusive) from the value @x
43 * it should be @b0 <= @b1, or result is incorrect
45 static inline u32
WIL_GET_BITS(u32 x
, int b0
, int b1
)
47 return (x
>> b0
) & ((1 << (b1
- b0
+ 1)) - 1);
50 #define WIL6210_MEM_SIZE (2*1024*1024UL)
52 #define WIL_TX_Q_LEN_DEFAULT (4000)
53 #define WIL_RX_RING_SIZE_ORDER_DEFAULT (10)
54 #define WIL_TX_RING_SIZE_ORDER_DEFAULT (12)
55 #define WIL_BCAST_RING_SIZE_ORDER_DEFAULT (7)
56 #define WIL_BCAST_MCS0_LIMIT (1024) /* limit for MCS0 frame size */
57 /* limit ring size in range [32..32k] */
58 #define WIL_RING_SIZE_ORDER_MIN (5)
59 #define WIL_RING_SIZE_ORDER_MAX (15)
60 #define WIL6210_MAX_TX_RINGS (24) /* HW limit */
61 #define WIL6210_MAX_CID (8) /* HW limit */
62 #define WIL6210_NAPI_BUDGET (16) /* arbitrary */
63 #define WIL_MAX_AMPDU_SIZE (64 * 1024) /* FW/HW limit */
64 #define WIL_MAX_AGG_WSIZE (32) /* FW/HW limit */
65 /* Hardware offload block adds the following:
66 * 26 bytes - 3-address QoS data header
67 * 8 bytes - IV + EIV (for GCMP)
69 * 16 bytes - MIC (for GCMP)
72 #define WIL_MAX_MPDU_OVERHEAD (62)
74 /* Calculate MAC buffer size for the firmware. It includes all overhead,
75 * as it will go over the air, and need to be 8 byte aligned
77 static inline u32
wil_mtu2macbuf(u32 mtu
)
79 return ALIGN(mtu
+ WIL_MAX_MPDU_OVERHEAD
, 8);
82 /* MTU for Ethernet need to take into account 8-byte SNAP header
83 * to be added when encapsulating Ethernet frame into 802.11
85 #define WIL_MAX_ETH_MTU (IEEE80211_MAX_DATA_LEN_DMG - 8)
86 /* Max supported by wil6210 value for interrupt threshold is 5sec. */
87 #define WIL6210_ITR_TRSH_MAX (5000000)
88 #define WIL6210_ITR_TX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
89 #define WIL6210_ITR_RX_INTERFRAME_TIMEOUT_DEFAULT (13) /* usec */
90 #define WIL6210_ITR_TX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
91 #define WIL6210_ITR_RX_MAX_BURST_DURATION_DEFAULT (500) /* usec */
92 #define WIL6210_FW_RECOVERY_RETRIES (5) /* try to recover this many times */
93 #define WIL6210_FW_RECOVERY_TO msecs_to_jiffies(5000)
94 #define WIL6210_SCAN_TO msecs_to_jiffies(10000)
95 #define WIL6210_DISCONNECT_TO_MS (2000)
96 #define WIL6210_RX_HIGH_TRSH_INIT (0)
97 #define WIL6210_RX_HIGH_TRSH_DEFAULT \
98 (1 << (WIL_RX_RING_SIZE_ORDER_DEFAULT - 3))
99 /* Hardware definitions begin */
103 * RGF File | Host addr | FW addr
105 * user_rgf | 0x000000 | 0x880000
106 * dma_rgf | 0x001000 | 0x881000
107 * pcie_rgf | 0x002000 | 0x882000
111 /* Where various structures placed in host address space */
112 #define WIL6210_FW_HOST_OFF (0x880000UL)
114 #define HOSTADDR(fwaddr) (fwaddr - WIL6210_FW_HOST_OFF)
117 * Interrupt control registers block
119 * each interrupt controlled by the same bit in all registers
122 u32 ICC
; /* Cause Control, RW: 0 - W1C, 1 - COR */
123 u32 ICR
; /* Cause, W1C/COR depending on ICC */
124 u32 ICM
; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */
125 u32 ICS
; /* Cause Set, WO */
126 u32 IMV
; /* Mask, RW+S/C */
127 u32 IMS
; /* Mask Set, write 1 to set */
128 u32 IMC
; /* Mask Clear, write 1 to clear */
131 /* registers - FW addresses */
132 #define RGF_USER_USAGE_1 (0x880004)
133 #define RGF_USER_USAGE_6 (0x880018)
134 #define RGF_USER_HW_MACHINE_STATE (0x8801dc)
135 #define HW_MACHINE_BOOT_DONE (0x3fffffd)
136 #define RGF_USER_USER_CPU_0 (0x8801e0)
137 #define BIT_USER_USER_CPU_MAN_RST BIT(1) /* user_cpu_man_rst */
138 #define RGF_USER_MAC_CPU_0 (0x8801fc)
139 #define BIT_USER_MAC_CPU_MAN_RST BIT(1) /* mac_cpu_man_rst */
140 #define RGF_USER_USER_SCRATCH_PAD (0x8802bc)
141 #define RGF_USER_BL (0x880A3C) /* Boot Loader */
142 #define RGF_USER_FW_REV_ID (0x880a8c) /* chip revision */
143 #define RGF_USER_CLKS_CTL_0 (0x880abc)
144 #define BIT_USER_CLKS_CAR_AHB_SW_SEL BIT(1) /* ref clk/PLL */
145 #define BIT_USER_CLKS_RST_PWGD BIT(11) /* reset on "power good" */
146 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0 (0x880b04)
147 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1 (0x880b08)
148 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2 (0x880b0c)
149 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3 (0x880b10)
150 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14)
151 #define BIT_HPAL_PERST_FROM_PAD BIT(6)
152 #define BIT_CAR_PERST_RST BIT(7)
153 #define RGF_USER_USER_ICR (0x880b4c) /* struct RGF_ICR */
154 #define BIT_USER_USER_ICR_SW_INT_2 BIT(18)
155 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0 (0x880c18)
156 #define RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1 (0x880c2c)
157 #define RGF_USER_SPARROW_M_4 (0x880c50) /* Sparrow */
158 #define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF BIT(2)
160 #define RGF_DMA_EP_TX_ICR (0x881bb4) /* struct RGF_ICR */
161 #define BIT_DMA_EP_TX_ICR_TX_DONE BIT(0)
162 #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n) BIT(n+1) /* n = [0..23] */
163 #define RGF_DMA_EP_RX_ICR (0x881bd0) /* struct RGF_ICR */
164 #define BIT_DMA_EP_RX_ICR_RX_DONE BIT(0)
165 #define BIT_DMA_EP_RX_ICR_RX_HTRSH BIT(1)
166 #define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */
167 #define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0)
168 #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1)
169 #define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */
171 /* Legacy interrupt moderation control (before Sparrow v2)*/
172 #define RGF_DMA_ITR_CNT_TRSH (0x881c5c)
173 #define RGF_DMA_ITR_CNT_DATA (0x881c60)
174 #define RGF_DMA_ITR_CNT_CRL (0x881c64)
175 #define BIT_DMA_ITR_CNT_CRL_EN BIT(0)
176 #define BIT_DMA_ITR_CNT_CRL_EXT_TICK BIT(1)
177 #define BIT_DMA_ITR_CNT_CRL_FOREVER BIT(2)
178 #define BIT_DMA_ITR_CNT_CRL_CLR BIT(3)
179 #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH BIT(4)
181 /* Offload control (Sparrow B0+) */
182 #define RGF_DMA_OFUL_NID_0 (0x881cd4)
183 #define BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN BIT(0)
184 #define BIT_DMA_OFUL_NID_0_TX_EXT_TR_EN BIT(1)
185 #define BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC BIT(2)
186 #define BIT_DMA_OFUL_NID_0_TX_EXT_A3_SRC BIT(3)
188 /* New (sparrow v2+) interrupt moderation control */
189 #define RGF_DMA_ITR_TX_DESQ_NO_MOD (0x881d40)
190 #define RGF_DMA_ITR_TX_CNT_TRSH (0x881d34)
191 #define RGF_DMA_ITR_TX_CNT_DATA (0x881d38)
192 #define RGF_DMA_ITR_TX_CNT_CTL (0x881d3c)
193 #define BIT_DMA_ITR_TX_CNT_CTL_EN BIT(0)
194 #define BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL BIT(1)
195 #define BIT_DMA_ITR_TX_CNT_CTL_FOREVER BIT(2)
196 #define BIT_DMA_ITR_TX_CNT_CTL_CLR BIT(3)
197 #define BIT_DMA_ITR_TX_CNT_CTL_REACHED_TRESH BIT(4)
198 #define BIT_DMA_ITR_TX_CNT_CTL_CROSS_EN BIT(5)
199 #define BIT_DMA_ITR_TX_CNT_CTL_FREE_RUNNIG BIT(6)
200 #define RGF_DMA_ITR_TX_IDL_CNT_TRSH (0x881d60)
201 #define RGF_DMA_ITR_TX_IDL_CNT_DATA (0x881d64)
202 #define RGF_DMA_ITR_TX_IDL_CNT_CTL (0x881d68)
203 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EN BIT(0)
204 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1)
205 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_FOREVER BIT(2)
206 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR BIT(3)
207 #define BIT_DMA_ITR_TX_IDL_CNT_CTL_REACHED_TRESH BIT(4)
208 #define RGF_DMA_ITR_RX_DESQ_NO_MOD (0x881d50)
209 #define RGF_DMA_ITR_RX_CNT_TRSH (0x881d44)
210 #define RGF_DMA_ITR_RX_CNT_DATA (0x881d48)
211 #define RGF_DMA_ITR_RX_CNT_CTL (0x881d4c)
212 #define BIT_DMA_ITR_RX_CNT_CTL_EN BIT(0)
213 #define BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL BIT(1)
214 #define BIT_DMA_ITR_RX_CNT_CTL_FOREVER BIT(2)
215 #define BIT_DMA_ITR_RX_CNT_CTL_CLR BIT(3)
216 #define BIT_DMA_ITR_RX_CNT_CTL_REACHED_TRESH BIT(4)
217 #define BIT_DMA_ITR_RX_CNT_CTL_CROSS_EN BIT(5)
218 #define BIT_DMA_ITR_RX_CNT_CTL_FREE_RUNNIG BIT(6)
219 #define RGF_DMA_ITR_RX_IDL_CNT_TRSH (0x881d54)
220 #define RGF_DMA_ITR_RX_IDL_CNT_DATA (0x881d58)
221 #define RGF_DMA_ITR_RX_IDL_CNT_CTL (0x881d5c)
222 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EN BIT(0)
223 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL BIT(1)
224 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_FOREVER BIT(2)
225 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR BIT(3)
226 #define BIT_DMA_ITR_RX_IDL_CNT_CTL_REACHED_TRESH BIT(4)
228 #define RGF_DMA_PSEUDO_CAUSE (0x881c68)
229 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW (0x881c6c)
230 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW (0x881c70)
231 #define BIT_DMA_PSEUDO_CAUSE_RX BIT(0)
232 #define BIT_DMA_PSEUDO_CAUSE_TX BIT(1)
233 #define BIT_DMA_PSEUDO_CAUSE_MISC BIT(2)
235 #define RGF_HP_CTRL (0x88265c)
236 #define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4)
238 /* MAC timer, usec, for packet lifetime */
239 #define RGF_MAC_MTRL_COUNTER_0 (0x886aa8)
241 #define RGF_CAF_ICR (0x88946c) /* struct RGF_ICR */
242 #define RGF_CAF_OSC_CONTROL (0x88afa4)
243 #define BIT_CAF_OSC_XTAL_EN BIT(0)
244 #define RGF_CAF_PLL_LOCK_STATUS (0x88afec)
245 #define BIT_CAF_OSC_DIG_XTAL_STABLE BIT(0)
247 #define RGF_USER_JTAG_DEV_ID (0x880b34) /* device ID */
248 #define JTAG_DEV_ID_SPARROW_B0 (0x2632072f)
250 /* crash codes for FW/Ucode stored here */
251 #define RGF_FW_ASSERT_CODE (0x91f020)
252 #define RGF_UCODE_ASSERT_CODE (0x91f028)
256 HW_VER_SPARROW_B0
, /* JTAG_DEV_ID_SPARROW_B0 */
259 /* popular locations */
260 #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD
261 #define HOST_MBOX HOSTADDR(RGF_MBOX)
262 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2
264 /* ISR register bits */
265 #define ISR_MISC_FW_READY BIT_DMA_EP_MISC_ICR_FW_INT(0)
266 #define ISR_MISC_MBOX_EVT BIT_DMA_EP_MISC_ICR_FW_INT(1)
267 #define ISR_MISC_FW_ERROR BIT_DMA_EP_MISC_ICR_FW_INT(3)
269 /* Hardware definitions end */
271 u32 from
; /* linker address - from, inclusive */
272 u32 to
; /* linker address - to, exclusive */
273 u32 host
; /* PCI/Host address - BAR0 + 0x880000 */
274 const char *name
; /* for debugfs */
277 /* array size should be in sync with actual definition in the wmi.c */
278 extern const struct fw_map fw_mapping
[8];
281 * mk_cidxtid - construct @cidxtid field
285 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
287 static inline u8
mk_cidxtid(u8 cid
, u8 tid
)
289 return ((tid
& 0xf) << 4) | (cid
& 0xf);
293 * parse_cidxtid - parse @cidxtid field
294 * @cid: store CID value here
295 * @tid: store TID value here
297 * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
299 static inline void parse_cidxtid(u8 cidxtid
, u8
*cid
, u8
*tid
)
301 *cid
= cidxtid
& 0xf;
302 *tid
= (cidxtid
>> 4) & 0xf;
305 struct wil6210_mbox_ring
{
307 u16 entry_size
; /* max. size of mbox entry, incl. all headers */
313 struct wil6210_mbox_ring_desc
{
318 /* at HOST_OFF_WIL6210_MBOX_CTL */
319 struct wil6210_mbox_ctl
{
320 struct wil6210_mbox_ring tx
;
321 struct wil6210_mbox_ring rx
;
324 struct wil6210_mbox_hdr
{
326 __le16 len
; /* payload, bytes after this header */
332 #define WIL_MBOX_HDR_TYPE_WMI (0)
334 /* max. value for wil6210_mbox_hdr.len */
335 #define MAX_MBOXITEM_SIZE (240)
338 * struct wil6210_mbox_hdr_wmi - WMI header
341 * 00 - default, created by FW
342 * 01..0f - WiFi ports, driver to create
345 * @id: command/event ID
346 * @timestamp: FW fills for events, free-running msec timer
348 struct wil6210_mbox_hdr_wmi
{
355 struct pending_wmi_event
{
356 struct list_head list
;
358 struct wil6210_mbox_hdr hdr
;
359 struct wil6210_mbox_hdr_wmi wmi
;
364 enum { /* for wil_ctx.mapped_as */
365 wil_mapped_as_none
= 0,
366 wil_mapped_as_single
= 1,
367 wil_mapped_as_page
= 2,
371 * struct wil_ctx - software context for Vring descriptor
383 volatile union vring_desc
*va
; /* vring_desc[size], WriteBack by DMA */
384 u16 size
; /* number of vring_desc elements */
387 u32 hwtail
; /* write here to inform hw */
388 struct wil_ctx
*ctx
; /* ctx[size] - software context */
392 * Additional data for Tx Vring
394 struct vring_tx_data
{
397 cycles_t idle
, last_idle
, begin
;
398 u8 agg_wsize
; /* agreed aggregation window, 0 - no agg */
401 bool addba_in_progress
; /* if set, agg_xxx is for request in progress */
405 enum { /* for wil6210_priv.status */
406 wil_status_fwready
= 0, /* FW operational */
407 wil_status_fwconnecting
,
408 wil_status_fwconnected
,
410 wil_status_mbox_ready
, /* MBOX structures ready */
411 wil_status_irqen
, /* FIXME: interrupts enabled - for debug */
412 wil_status_napi_en
, /* NAPI enabled protected by wil->mutex */
413 wil_status_resetting
, /* reset in progress */
414 wil_status_last
/* keep last */
420 * struct tid_ampdu_rx - TID aggregation information (Rx).
422 * @reorder_buf: buffer to reorder incoming aggregated MPDUs
423 * @reorder_time: jiffies when skb was added
424 * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value)
425 * @reorder_timer: releases expired frames from the reorder buffer.
426 * @last_rx: jiffies of last rx activity
427 * @head_seq_num: head sequence number in reordering buffer.
428 * @stored_mpdu_num: number of MPDUs in reordering buffer
429 * @ssn: Starting Sequence Number expected to be aggregated.
430 * @buf_size: buffer size for incoming A-MPDUs
431 * @timeout: reset timer value (in TUs).
432 * @ssn_last_drop: SSN of the last dropped frame
433 * @total: total number of processed incoming frames
434 * @drop_dup: duplicate frames dropped for this reorder buffer
435 * @drop_old: old frames dropped for this reorder buffer
436 * @dialog_token: dialog token for aggregation session
437 * @first_time: true when this buffer used 1-st time
439 struct wil_tid_ampdu_rx
{
440 struct sk_buff
**reorder_buf
;
441 unsigned long *reorder_time
;
442 struct timer_list session_timer
;
443 struct timer_list reorder_timer
;
444 unsigned long last_rx
;
451 unsigned long long total
; /* frames processed */
452 unsigned long long drop_dup
;
453 unsigned long long drop_old
;
455 bool first_time
; /* is it 1-st time this buffer used? */
458 enum wil_sta_status
{
460 wil_sta_conn_pending
= 1,
461 wil_sta_connected
= 2,
464 #define WIL_STA_TID_NUM (16)
465 #define WIL_MCS_MAX (12) /* Maximum MCS supported */
467 struct wil_net_stats
{
468 unsigned long rx_packets
;
469 unsigned long tx_packets
;
470 unsigned long rx_bytes
;
471 unsigned long tx_bytes
;
472 unsigned long tx_errors
;
473 unsigned long rx_dropped
;
474 unsigned long rx_non_data_frame
;
475 unsigned long rx_short_frame
;
476 unsigned long rx_large_frame
;
478 u64 rx_per_mcs
[WIL_MCS_MAX
+ 1];
482 * struct wil_sta_info - data for peer
484 * Peer identified by its CID (connection ID)
485 * NIC performs beam forming for each peer;
486 * if no beam forming done, frame exchange is not
489 struct wil_sta_info
{
491 enum wil_sta_status status
;
492 struct wil_net_stats stats
;
494 struct wil_tid_ampdu_rx
*tid_rx
[WIL_STA_TID_NUM
];
495 spinlock_t tid_rx_lock
; /* guarding tid_rx array */
496 unsigned long tid_rx_timer_expired
[BITS_TO_LONGS(WIL_STA_TID_NUM
)];
497 unsigned long tid_rx_stop_requested
[BITS_TO_LONGS(WIL_STA_TID_NUM
)];
501 fw_recovery_idle
= 0,
502 fw_recovery_pending
= 1,
503 fw_recovery_running
= 2,
511 struct list_head list
;
512 /* request params, converted to CPU byte order - what we asked for */
521 struct list_head list
;
522 /* request params, converted to CPU byte order - what we asked for */
528 struct wil_probe_client_req
{
529 struct list_head list
;
535 /* alloc, free, and read operations must own the lock */
537 struct vring_tx_desc
*pring_va
;
539 struct desc_alloc_info
*descriptors
;
545 struct wil6210_priv
{
546 struct pci_dev
*pdev
;
547 struct wireless_dev
*wdev
;
549 DECLARE_BITMAP(status
, wil_status_last
);
553 DECLARE_BITMAP(hw_capabilities
, hw_capability_last
);
554 u8 n_mids
; /* number of additional MIDs as reported by FW */
555 u32 recovery_count
; /* num of FW recovery attempts in a short time */
556 u32 recovery_state
; /* FW recovery state machine */
557 unsigned long last_fw_recovery
; /* jiffies of last fw recovery */
558 wait_queue_head_t wq
; /* for all wait_event() use */
561 u32 privacy
; /* secure connection? */
562 u8 hidden_ssid
; /* relevant in AP mode */
563 u16 channel
; /* relevant in AP mode */
565 u32 ap_isolate
; /* no intra-BSS communication */
566 /* interrupt moderation */
567 u32 tx_max_burst_duration
;
568 u32 tx_interframe_timeout
;
569 u32 rx_max_burst_duration
;
570 u32 rx_interframe_timeout
;
571 /* cached ISR registers */
573 /* mailbox related */
574 struct mutex wmi_mutex
;
575 struct wil6210_mbox_ctl mbox_ctl
;
576 struct completion wmi_ready
;
577 struct completion wmi_call
;
579 u16 reply_id
; /**< wait for this WMI event */
582 struct workqueue_struct
*wmi_wq
; /* for deferred calls */
583 struct work_struct wmi_event_worker
;
584 struct workqueue_struct
*wq_service
;
585 struct work_struct disconnect_worker
;
586 struct work_struct fw_error_worker
; /* for FW error recovery */
587 struct timer_list connect_timer
;
588 struct timer_list scan_timer
; /* detect scan timeout */
589 struct list_head pending_wmi_ev
;
591 * protect pending_wmi_ev
592 * - fill in IRQ from wil6210_irq_misc,
593 * - consumed in thread by wmi_event_worker
595 spinlock_t wmi_ev_lock
;
596 struct napi_struct napi_rx
;
597 struct napi_struct napi_tx
;
599 struct list_head back_rx_pending
;
600 struct mutex back_rx_mutex
; /* protect @back_rx_pending */
601 struct work_struct back_rx_worker
;
602 struct list_head back_tx_pending
;
603 struct mutex back_tx_mutex
; /* protect @back_tx_pending */
604 struct work_struct back_tx_worker
;
606 struct list_head probe_client_pending
;
607 struct mutex probe_client_mutex
; /* protect @probe_client_pending */
608 struct work_struct probe_client_worker
;
610 struct vring vring_rx
;
611 struct vring vring_tx
[WIL6210_MAX_TX_RINGS
];
612 struct vring_tx_data vring_tx_data
[WIL6210_MAX_TX_RINGS
];
613 u8 vring2cid_tid
[WIL6210_MAX_TX_RINGS
][2]; /* [0] - CID, [1] - TID */
614 struct wil_sta_info sta
[WIL6210_MAX_CID
];
617 struct cfg80211_scan_request
*scan_request
;
619 struct mutex mutex
; /* for wil6210_priv access in wil_{up|down} */
621 atomic_t isr_count_rx
, isr_count_tx
;
623 struct dentry
*debug
;
624 struct debugfs_blob_wrapper blobs
[ARRAY_SIZE(fw_mapping
)];
626 void *platform_handle
;
627 struct wil_platform_ops platform_ops
;
632 #define wil_to_wiphy(i) (i->wdev->wiphy)
633 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i)))
634 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w))
635 #define wil_to_wdev(i) (i->wdev)
636 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w))
637 #define wil_to_ndev(i) (wil_to_wdev(i)->netdev)
638 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr))
641 void wil_dbg_trace(struct wil6210_priv
*wil
, const char *fmt
, ...);
643 void wil_err(struct wil6210_priv
*wil
, const char *fmt
, ...);
645 void wil_err_ratelimited(struct wil6210_priv
*wil
, const char *fmt
, ...);
647 void wil_info(struct wil6210_priv
*wil
, const char *fmt
, ...);
648 #define wil_dbg(wil, fmt, arg...) do { \
649 netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \
650 wil_dbg_trace(wil, fmt, ##arg); \
653 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg)
654 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg)
655 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg)
656 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg)
657 #define wil_dbg_pm(wil, fmt, arg...) wil_dbg(wil, "DBG[ PM ]" fmt, ##arg)
659 /* target operations */
661 static inline u32
wil_r(struct wil6210_priv
*wil
, u32 reg
)
663 return readl(wil
->csr
+ HOSTADDR(reg
));
666 /* register write. wmb() to make sure it is completed */
667 static inline void wil_w(struct wil6210_priv
*wil
, u32 reg
, u32 val
)
669 writel(val
, wil
->csr
+ HOSTADDR(reg
));
670 wmb(); /* wait for write to propagate to the HW */
673 /* register set = read, OR, write */
674 static inline void wil_s(struct wil6210_priv
*wil
, u32 reg
, u32 val
)
676 wil_w(wil
, reg
, wil_r(wil
, reg
) | val
);
679 /* register clear = read, AND with inverted, write */
680 static inline void wil_c(struct wil6210_priv
*wil
, u32 reg
, u32 val
)
682 wil_w(wil
, reg
, wil_r(wil
, reg
) & ~val
);
685 #if defined(CONFIG_DYNAMIC_DEBUG)
686 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \
687 groupsize, buf, len, ascii) \
688 print_hex_dump_debug("DBG[TXRX]" prefix_str,\
689 prefix_type, rowsize, \
690 groupsize, buf, len, ascii)
692 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize, \
693 groupsize, buf, len, ascii) \
694 print_hex_dump_debug("DBG[ WMI]" prefix_str,\
695 prefix_type, rowsize, \
696 groupsize, buf, len, ascii)
697 #else /* defined(CONFIG_DYNAMIC_DEBUG) */
699 void wil_hex_dump_txrx(const char *prefix_str
, int prefix_type
, int rowsize
,
700 int groupsize
, const void *buf
, size_t len
, bool ascii
)
705 void wil_hex_dump_wmi(const char *prefix_str
, int prefix_type
, int rowsize
,
706 int groupsize
, const void *buf
, size_t len
, bool ascii
)
709 #endif /* defined(CONFIG_DYNAMIC_DEBUG) */
711 void wil_memcpy_fromio_32(void *dst
, const volatile void __iomem
*src
,
713 void wil_memcpy_toio_32(volatile void __iomem
*dst
, const void *src
,
716 void *wil_if_alloc(struct device
*dev
);
717 void wil_if_free(struct wil6210_priv
*wil
);
718 int wil_if_add(struct wil6210_priv
*wil
);
719 void wil_if_remove(struct wil6210_priv
*wil
);
720 int wil_priv_init(struct wil6210_priv
*wil
);
721 void wil_priv_deinit(struct wil6210_priv
*wil
);
722 int wil_reset(struct wil6210_priv
*wil
, bool no_fw
);
723 void wil_fw_error_recovery(struct wil6210_priv
*wil
);
724 void wil_set_recovery_state(struct wil6210_priv
*wil
, int state
);
725 int wil_up(struct wil6210_priv
*wil
);
726 int __wil_up(struct wil6210_priv
*wil
);
727 int wil_down(struct wil6210_priv
*wil
);
728 int __wil_down(struct wil6210_priv
*wil
);
729 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring
*r
);
730 int wil_find_cid(struct wil6210_priv
*wil
, const u8
*mac
);
731 void wil_set_ethtoolops(struct net_device
*ndev
);
733 void __iomem
*wmi_buffer(struct wil6210_priv
*wil
, __le32 ptr
);
734 void __iomem
*wmi_addr(struct wil6210_priv
*wil
, u32 ptr
);
735 int wmi_read_hdr(struct wil6210_priv
*wil
, __le32 ptr
,
736 struct wil6210_mbox_hdr
*hdr
);
737 int wmi_send(struct wil6210_priv
*wil
, u16 cmdid
, void *buf
, u16 len
);
738 void wmi_recv_cmd(struct wil6210_priv
*wil
);
739 int wmi_call(struct wil6210_priv
*wil
, u16 cmdid
, void *buf
, u16 len
,
740 u16 reply_id
, void *reply
, u8 reply_size
, int to_msec
);
741 void wmi_event_worker(struct work_struct
*work
);
742 void wmi_event_flush(struct wil6210_priv
*wil
);
743 int wmi_set_ssid(struct wil6210_priv
*wil
, u8 ssid_len
, const void *ssid
);
744 int wmi_get_ssid(struct wil6210_priv
*wil
, u8
*ssid_len
, void *ssid
);
745 int wmi_set_channel(struct wil6210_priv
*wil
, int channel
);
746 int wmi_get_channel(struct wil6210_priv
*wil
, int *channel
);
747 int wmi_del_cipher_key(struct wil6210_priv
*wil
, u8 key_index
,
748 const void *mac_addr
, int key_usage
);
749 int wmi_add_cipher_key(struct wil6210_priv
*wil
, u8 key_index
,
750 const void *mac_addr
, int key_len
, const void *key
,
752 int wmi_echo(struct wil6210_priv
*wil
);
753 int wmi_set_ie(struct wil6210_priv
*wil
, u8 type
, u16 ie_len
, const void *ie
);
754 int wmi_rx_chain_add(struct wil6210_priv
*wil
, struct vring
*vring
);
755 int wmi_p2p_cfg(struct wil6210_priv
*wil
, int channel
);
756 int wmi_rxon(struct wil6210_priv
*wil
, bool on
);
757 int wmi_get_temperature(struct wil6210_priv
*wil
, u32
*t_m
, u32
*t_r
);
758 int wmi_disconnect_sta(struct wil6210_priv
*wil
, const u8
*mac
, u16 reason
,
759 bool full_disconnect
);
760 int wmi_addba(struct wil6210_priv
*wil
, u8 ringid
, u8 size
, u16 timeout
);
761 int wmi_delba_tx(struct wil6210_priv
*wil
, u8 ringid
, u16 reason
);
762 int wmi_delba_rx(struct wil6210_priv
*wil
, u8 cidxtid
, u16 reason
);
763 int wmi_addba_rx_resp(struct wil6210_priv
*wil
, u8 cid
, u8 tid
, u8 token
,
764 u16 status
, bool amsdu
, u16 agg_wsize
, u16 timeout
);
765 int wil_addba_rx_request(struct wil6210_priv
*wil
, u8 cidxtid
,
766 u8 dialog_token
, __le16 ba_param_set
,
767 __le16 ba_timeout
, __le16 ba_seq_ctrl
);
768 void wil_back_rx_worker(struct work_struct
*work
);
769 void wil_back_rx_flush(struct wil6210_priv
*wil
);
770 int wil_addba_tx_request(struct wil6210_priv
*wil
, u8 ringid
, u16 wsize
);
771 void wil_back_tx_worker(struct work_struct
*work
);
772 void wil_back_tx_flush(struct wil6210_priv
*wil
);
774 void wil6210_clear_irq(struct wil6210_priv
*wil
);
775 int wil6210_init_irq(struct wil6210_priv
*wil
, int irq
, bool use_msi
);
776 void wil6210_fini_irq(struct wil6210_priv
*wil
, int irq
);
777 void wil_mask_irq(struct wil6210_priv
*wil
);
778 void wil_unmask_irq(struct wil6210_priv
*wil
);
779 void wil_configure_interrupt_moderation(struct wil6210_priv
*wil
);
780 void wil_disable_irq(struct wil6210_priv
*wil
);
781 void wil_enable_irq(struct wil6210_priv
*wil
);
782 int wil_cfg80211_mgmt_tx(struct wiphy
*wiphy
, struct wireless_dev
*wdev
,
783 struct cfg80211_mgmt_tx_params
*params
,
786 int wil6210_debugfs_init(struct wil6210_priv
*wil
);
787 void wil6210_debugfs_remove(struct wil6210_priv
*wil
);
788 int wil_cid_fill_sinfo(struct wil6210_priv
*wil
, int cid
,
789 struct station_info
*sinfo
);
791 struct wireless_dev
*wil_cfg80211_init(struct device
*dev
);
792 void wil_wdev_free(struct wil6210_priv
*wil
);
794 int wmi_set_mac_address(struct wil6210_priv
*wil
, void *addr
);
795 int wmi_pcp_start(struct wil6210_priv
*wil
, int bi
, u8 wmi_nettype
,
796 u8 chan
, u8 hidden_ssid
);
797 int wmi_pcp_stop(struct wil6210_priv
*wil
);
798 void wil6210_disconnect(struct wil6210_priv
*wil
, const u8
*bssid
,
799 u16 reason_code
, bool from_event
);
800 void wil_probe_client_flush(struct wil6210_priv
*wil
);
801 void wil_probe_client_worker(struct work_struct
*work
);
803 int wil_rx_init(struct wil6210_priv
*wil
, u16 size
);
804 void wil_rx_fini(struct wil6210_priv
*wil
);
807 int wil_vring_init_tx(struct wil6210_priv
*wil
, int id
, int size
,
809 void wil_vring_fini_tx(struct wil6210_priv
*wil
, int id
);
810 int wil_tx_init(struct wil6210_priv
*wil
, int cid
);
811 int wil_vring_init_bcast(struct wil6210_priv
*wil
, int id
, int size
);
812 int wil_bcast_init(struct wil6210_priv
*wil
);
813 void wil_bcast_fini(struct wil6210_priv
*wil
);
815 netdev_tx_t
wil_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
);
816 int wil_tx_complete(struct wil6210_priv
*wil
, int ringid
);
817 void wil6210_unmask_irq_tx(struct wil6210_priv
*wil
);
820 void wil_rx_handle(struct wil6210_priv
*wil
, int *quota
);
821 void wil6210_unmask_irq_rx(struct wil6210_priv
*wil
);
823 int wil_iftype_nl2wmi(enum nl80211_iftype type
);
825 int wil_ioctl(struct wil6210_priv
*wil
, void __user
*data
, int cmd
);
826 int wil_request_firmware(struct wil6210_priv
*wil
, const char *name
);
828 int wil_can_suspend(struct wil6210_priv
*wil
, bool is_runtime
);
829 int wil_suspend(struct wil6210_priv
*wil
, bool is_runtime
);
830 int wil_resume(struct wil6210_priv
*wil
, bool is_runtime
);
832 int wil_fw_copy_crash_dump(struct wil6210_priv
*wil
, void *dest
, u32 size
);
833 void wil_fw_core_dump(struct wil6210_priv
*wil
);
835 #endif /* __WIL6210_H__ */