drivers/net/wireless/ath/wil6210/wil6210.h

   1 /*
   2  * Copyright (c) 2012 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef __WIL6210_H__
  18 #define __WIL6210_H__
  19
  20 #include <linux/netdevice.h>
  21 #include <linux/wireless.h>
  22 #include <net/cfg80211.h>
  23
  24 #define WIL_NAME "wil6210"
  25
  26 /**
  27  * extract bits [@b0:@b1] (inclusive) from the value @x
  28  * it should be @b0 <= @b1, or result is incorrect
  29  */
  30 static inline u32 WIL_GET_BITS(u32 x, int b0, int b1)
  31 {
  32         return (x >> b0) & ((1 << (b1 - b0 + 1)) - 1);
  33 }
  34
  35 #define WIL6210_MEM_SIZE (2*1024*1024UL)
  36
  37 #define WIL6210_RX_RING_SIZE    (128)
  38 #define WIL6210_TX_RING_SIZE    (128)
  39 #define WIL6210_MAX_TX_RINGS    (24) /* HW limit */
  40 #define WIL6210_MAX_CID         (8) /* HW limit */
  41 #define WIL6210_NAPI_BUDGET     (16) /* arbitrary */
  42 #define WIL6210_ITR_TRSH        (10000) /* arbitrary - about 15 IRQs/msec */
  43
  44 /* Hardware definitions begin */
  45
  46 /*
  47  * Mapping
  48  * RGF File      | Host addr    |  FW addr
  49  *               |              |
  50  * user_rgf      | 0x000000     | 0x880000
  51  *  dma_rgf      | 0x001000     | 0x881000
  52  * pcie_rgf      | 0x002000     | 0x882000
  53  *               |              |
  54  */
  55
  56 /* Where various structures placed in host address space */
  57 #define WIL6210_FW_HOST_OFF      (0x880000UL)
  58
  59 #define HOSTADDR(fwaddr)        (fwaddr - WIL6210_FW_HOST_OFF)
  60
  61 /*
  62  * Interrupt control registers block
  63  *
  64  * each interrupt controlled by the same bit in all registers
  65  */
  66 struct RGF_ICR {
  67         u32 ICC; /* Cause Control, RW: 0 - W1C, 1 - COR */
  68         u32 ICR; /* Cause, W1C/COR depending on ICC */
  69         u32 ICM; /* Cause masked (ICR & ~IMV), W1C/COR depending on ICC */
  70         u32 ICS; /* Cause Set, WO */
  71         u32 IMV; /* Mask, RW+S/C */
  72         u32 IMS; /* Mask Set, write 1 to set */
  73         u32 IMC; /* Mask Clear, write 1 to clear */
  74 } __packed;
  75
  76 /* registers - FW addresses */
  77 #define RGF_USER_USER_SCRATCH_PAD       (0x8802bc)
  78 #define RGF_USER_USER_ICR               (0x880b4c) /* struct RGF_ICR */
  79         #define BIT_USER_USER_ICR_SW_INT_2      BIT(18)
  80 #define RGF_USER_CLKS_CTL_SW_RST_MASK_0 (0x880b14)
  81 #define RGF_USER_MAC_CPU_0              (0x8801fc)
  82 #define RGF_USER_USER_CPU_0             (0x8801e0)
  83 #define RGF_USER_CLKS_CTL_SW_RST_VEC_0  (0x880b04)
  84 #define RGF_USER_CLKS_CTL_SW_RST_VEC_1  (0x880b08)
  85 #define RGF_USER_CLKS_CTL_SW_RST_VEC_2  (0x880b0c)
  86 #define RGF_USER_CLKS_CTL_SW_RST_VEC_3  (0x880b10)
  87
  88 #define RGF_DMA_PSEUDO_CAUSE            (0x881c68)
  89 #define RGF_DMA_PSEUDO_CAUSE_MASK_SW    (0x881c6c)
  90 #define RGF_DMA_PSEUDO_CAUSE_MASK_FW    (0x881c70)
  91         #define BIT_DMA_PSEUDO_CAUSE_RX         BIT(0)
  92         #define BIT_DMA_PSEUDO_CAUSE_TX         BIT(1)
  93         #define BIT_DMA_PSEUDO_CAUSE_MISC       BIT(2)
  94
  95 #define RGF_DMA_EP_TX_ICR               (0x881bb4) /* struct RGF_ICR */
  96         #define BIT_DMA_EP_TX_ICR_TX_DONE       BIT(0)
  97         #define BIT_DMA_EP_TX_ICR_TX_DONE_N(n)  BIT(n+1) /* n = [0..23] */
  98 #define RGF_DMA_EP_RX_ICR               (0x881bd0) /* struct RGF_ICR */
  99         #define BIT_DMA_EP_RX_ICR_RX_DONE       BIT(0)
 100 #define RGF_DMA_EP_MISC_ICR             (0x881bec) /* struct RGF_ICR */
 101         #define BIT_DMA_EP_MISC_ICR_RX_HTRSH    BIT(0)
 102         #define BIT_DMA_EP_MISC_ICR_TX_NO_ACT   BIT(1)
 103         #define BIT_DMA_EP_MISC_ICR_FW_INT(n)   BIT(28+n) /* n = [0..3] */
 104
 105 /* Interrupt moderation control */
 106 #define RGF_DMA_ITR_CNT_TRSH            (0x881c5c)
 107 #define RGF_DMA_ITR_CNT_DATA            (0x881c60)
 108 #define RGF_DMA_ITR_CNT_CRL             (0x881C64)
 109         #define BIT_DMA_ITR_CNT_CRL_EN          BIT(0)
 110         #define BIT_DMA_ITR_CNT_CRL_EXT_TICK    BIT(1)
 111         #define BIT_DMA_ITR_CNT_CRL_FOREVER     BIT(2)
 112         #define BIT_DMA_ITR_CNT_CRL_CLR         BIT(3)
 113         #define BIT_DMA_ITR_CNT_CRL_REACH_TRSH  BIT(4)
 114
 115 /* popular locations */
 116 #define HOST_MBOX   HOSTADDR(RGF_USER_USER_SCRATCH_PAD)
 117 #define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \
 118         offsetof(struct RGF_ICR, ICS))
 119 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2
 120
 121 /* ISR register bits */
 122 #define ISR_MISC_FW_READY       BIT_DMA_EP_MISC_ICR_FW_INT(0)
 123 #define ISR_MISC_MBOX_EVT       BIT_DMA_EP_MISC_ICR_FW_INT(1)
 124 #define ISR_MISC_FW_ERROR       BIT_DMA_EP_MISC_ICR_FW_INT(3)
 125
 126 /* Hardware definitions end */
 127
 128 /**
 129  * mk_cidxtid - construct @cidxtid field
 130  * @cid: CID value
 131  * @tid: TID value
 132  *
 133  * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
 134  */
 135 static inline u8 mk_cidxtid(u8 cid, u8 tid)
 136 {
 137         return ((tid & 0xf) << 4) | (cid & 0xf);
 138 }
 139
 140 /**
 141  * parse_cidxtid - parse @cidxtid field
 142  * @cid: store CID value here
 143  * @tid: store TID value here
 144  *
 145  * @cidxtid field encoded as bits 0..3 - CID; 4..7 - TID
 146  */
 147 static inline void parse_cidxtid(u8 cidxtid, u8 *cid, u8 *tid)
 148 {
 149         *cid = cidxtid & 0xf;
 150         *tid = (cidxtid >> 4) & 0xf;
 151 }
 152
 153 struct wil6210_mbox_ring {
 154         u32 base;
 155         u16 entry_size; /* max. size of mbox entry, incl. all headers */
 156         u16 size;
 157         u32 tail;
 158         u32 head;
 159 } __packed;
 160
 161 struct wil6210_mbox_ring_desc {
 162         __le32 sync;
 163         __le32 addr;
 164 } __packed;
 165
 166 /* at HOST_OFF_WIL6210_MBOX_CTL */
 167 struct wil6210_mbox_ctl {
 168         struct wil6210_mbox_ring tx;
 169         struct wil6210_mbox_ring rx;
 170 } __packed;
 171
 172 struct wil6210_mbox_hdr {
 173         __le16 seq;
 174         __le16 len; /* payload, bytes after this header */
 175         __le16 type;
 176         u8 flags;
 177         u8 reserved;
 178 } __packed;
 179
 180 #define WIL_MBOX_HDR_TYPE_WMI (0)
 181
 182 /* max. value for wil6210_mbox_hdr.len */
 183 #define MAX_MBOXITEM_SIZE   (240)
 184
 185 /**
 186  * struct wil6210_mbox_hdr_wmi - WMI header
 187  *
 188  * @mid: MAC ID
 189  *      00 - default, created by FW
 190  *      01..0f - WiFi ports, driver to create
 191  *      10..fe - debug
 192  *      ff - broadcast
 193  * @id: command/event ID
 194  * @timestamp: FW fills for events, free-running msec timer
 195  */
 196 struct wil6210_mbox_hdr_wmi {
 197         u8 mid;
 198         u8 reserved;
 199         __le16 id;
 200         __le32 timestamp;
 201 } __packed;
 202
 203 struct pending_wmi_event {
 204         struct list_head list;
 205         struct {
 206                 struct wil6210_mbox_hdr hdr;
 207                 struct wil6210_mbox_hdr_wmi wmi;
 208                 u8 data[0];
 209         } __packed event;
 210 };
 211
 212 /**
 213  * struct wil_ctx - software context for Vring descriptor
 214  */
 215 struct wil_ctx {
 216         struct sk_buff *skb;
 217         u8 nr_frags;
 218         u8 mapped_as_page:1;
 219 };
 220
 221 union vring_desc;
 222
 223 struct vring {
 224         dma_addr_t pa;
 225         volatile union vring_desc *va; /* vring_desc[size], WriteBack by DMA */
 226         u16 size; /* number of vring_desc elements */
 227         u32 swtail;
 228         u32 swhead;
 229         u32 hwtail; /* write here to inform hw */
 230         struct wil_ctx *ctx; /* ctx[size] - software context */
 231 };
 232
 233 enum { /* for wil6210_priv.status */
 234         wil_status_fwready = 0,
 235         wil_status_fwconnecting,
 236         wil_status_fwconnected,
 237         wil_status_dontscan,
 238         wil_status_reset_done,
 239         wil_status_irqen, /* FIXME: interrupts enabled - for debug */
 240 };
 241
 242 struct pci_dev;
 243
 244 /**
 245  * struct tid_ampdu_rx - TID aggregation information (Rx).
 246  *
 247  * @reorder_buf: buffer to reorder incoming aggregated MPDUs
 248  * @reorder_time: jiffies when skb was added
 249  * @session_timer: check if peer keeps Tx-ing on the TID (by timeout value)
 250  * @reorder_timer: releases expired frames from the reorder buffer.
 251  * @last_rx: jiffies of last rx activity
 252  * @head_seq_num: head sequence number in reordering buffer.
 253  * @stored_mpdu_num: number of MPDUs in reordering buffer
 254  * @ssn: Starting Sequence Number expected to be aggregated.
 255  * @buf_size: buffer size for incoming A-MPDUs
 256  * @timeout: reset timer value (in TUs).
 257  * @dialog_token: dialog token for aggregation session
 258  * @rcu_head: RCU head used for freeing this struct
 259  * @reorder_lock: serializes access to reorder buffer, see below.
 260  *
 261  * This structure's lifetime is managed by RCU, assignments to
 262  * the array holding it must hold the aggregation mutex.
 263  *
 264  * The @reorder_lock is used to protect the members of this
 265  * struct, except for @timeout, @buf_size and @dialog_token,
 266  * which are constant across the lifetime of the struct (the
 267  * dialog token being used only for debugging).
 268  */
 269 struct wil_tid_ampdu_rx {
 270         spinlock_t reorder_lock; /* see above */
 271         struct sk_buff **reorder_buf;
 272         unsigned long *reorder_time;
 273         struct timer_list session_timer;
 274         struct timer_list reorder_timer;
 275         unsigned long last_rx;
 276         u16 head_seq_num;
 277         u16 stored_mpdu_num;
 278         u16 ssn;
 279         u16 buf_size;
 280         u16 timeout;
 281         u8 dialog_token;
 282 };
 283
 284 struct wil6210_stats {
 285         u64 tsf;
 286         u32 snr;
 287         u16 last_mcs_rx;
 288         u16 bf_mcs; /* last BF, used for Tx */
 289         u16 my_rx_sector;
 290         u16 my_tx_sector;
 291         u16 peer_rx_sector;
 292         u16 peer_tx_sector;
 293 };
 294
 295 enum wil_sta_status {
 296         wil_sta_unused = 0,
 297         wil_sta_conn_pending = 1,
 298         wil_sta_connected = 2,
 299 };
 300
 301 #define WIL_STA_TID_NUM (16)
 302
 303 struct wil_net_stats {
 304         unsigned long   rx_packets;
 305         unsigned long   tx_packets;
 306         unsigned long   rx_bytes;
 307         unsigned long   tx_bytes;
 308         unsigned long   tx_errors;
 309         unsigned long   rx_dropped;
 310         u16 last_mcs_rx;
 311 };
 312
 313 /**
 314  * struct wil_sta_info - data for peer
 315  *
 316  * Peer identified by its CID (connection ID)
 317  * NIC performs beam forming for each peer;
 318  * if no beam forming done, frame exchange is not
 319  * possible.
 320  */
 321 struct wil_sta_info {
 322         u8 addr[ETH_ALEN];
 323         enum wil_sta_status status;
 324         struct wil_net_stats stats;
 325         bool data_port_open; /* can send any data, not only EAPOL */
 326         /* Rx BACK */
 327         struct wil_tid_ampdu_rx *tid_rx[WIL_STA_TID_NUM];
 328         unsigned long tid_rx_timer_expired[BITS_TO_LONGS(WIL_STA_TID_NUM)];
 329         unsigned long tid_rx_stop_requested[BITS_TO_LONGS(WIL_STA_TID_NUM)];
 330 };
 331
 332 struct wil6210_priv {
 333         struct pci_dev *pdev;
 334         int n_msi;
 335         struct wireless_dev *wdev;
 336         void __iomem *csr;
 337         ulong status;
 338         u32 fw_version;
 339         u8 n_mids; /* number of additional MIDs as reported by FW */
 340         /* profile */
 341         u32 monitor_flags;
 342         u32 secure_pcp; /* create secure PCP? */
 343         int sinfo_gen;
 344         /* cached ISR registers */
 345         u32 isr_misc;
 346         /* mailbox related */
 347         struct mutex wmi_mutex;
 348         struct wil6210_mbox_ctl mbox_ctl;
 349         struct completion wmi_ready;
 350         u16 wmi_seq;
 351         u16 reply_id; /**< wait for this WMI event */
 352         void *reply_buf;
 353         u16 reply_size;
 354         struct workqueue_struct *wmi_wq; /* for deferred calls */
 355         struct work_struct wmi_event_worker;
 356         struct workqueue_struct *wmi_wq_conn; /* for connect worker */
 357         struct work_struct connect_worker;
 358         struct work_struct disconnect_worker;
 359         struct timer_list connect_timer;
 360         int pending_connect_cid;
 361         struct list_head pending_wmi_ev;
 362         /*
 363          * protect pending_wmi_ev
 364          * - fill in IRQ from wil6210_irq_misc,
 365          * - consumed in thread by wmi_event_worker
 366          */
 367         spinlock_t wmi_ev_lock;
 368         struct napi_struct napi_rx;
 369         struct napi_struct napi_tx;
 370         /* DMA related */
 371         struct vring vring_rx;
 372         struct vring vring_tx[WIL6210_MAX_TX_RINGS];
 373         u8 vring2cid_tid[WIL6210_MAX_TX_RINGS][2]; /* [0] - CID, [1] - TID */
 374         struct wil_sta_info sta[WIL6210_MAX_CID];
 375         /* scan */
 376         struct cfg80211_scan_request *scan_request;
 377
 378         struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */
 379         /* statistics */
 380         struct wil6210_stats stats;
 381         /* debugfs */
 382         struct dentry *debug;
 383         struct debugfs_blob_wrapper fw_code_blob;
 384         struct debugfs_blob_wrapper fw_data_blob;
 385         struct debugfs_blob_wrapper fw_peri_blob;
 386         struct debugfs_blob_wrapper uc_code_blob;
 387         struct debugfs_blob_wrapper uc_data_blob;
 388         struct debugfs_blob_wrapper rgf_blob;
 389 };
 390
 391 #define wil_to_wiphy(i) (i->wdev->wiphy)
 392 #define wil_to_dev(i) (wiphy_dev(wil_to_wiphy(i)))
 393 #define wiphy_to_wil(w) (struct wil6210_priv *)(wiphy_priv(w))
 394 #define wil_to_wdev(i) (i->wdev)
 395 #define wdev_to_wil(w) (struct wil6210_priv *)(wdev_priv(w))
 396 #define wil_to_ndev(i) (wil_to_wdev(i)->netdev)
 397 #define ndev_to_wil(n) (wdev_to_wil(n->ieee80211_ptr))
 398
 399 int wil_dbg_trace(struct wil6210_priv *wil, const char *fmt, ...);
 400 int wil_err(struct wil6210_priv *wil, const char *fmt, ...);
 401 int wil_info(struct wil6210_priv *wil, const char *fmt, ...);
 402 #define wil_dbg(wil, fmt, arg...) do { \
 403         netdev_dbg(wil_to_ndev(wil), fmt, ##arg); \
 404         wil_dbg_trace(wil, fmt, ##arg); \
 405 } while (0)
 406
 407 #define wil_dbg_irq(wil, fmt, arg...) wil_dbg(wil, "DBG[ IRQ]" fmt, ##arg)
 408 #define wil_dbg_txrx(wil, fmt, arg...) wil_dbg(wil, "DBG[TXRX]" fmt, ##arg)
 409 #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg)
 410 #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg)
 411
 412 #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize,     \
 413                           groupsize, buf, len, ascii)           \
 414                           print_hex_dump_debug("DBG[TXRX]" prefix_str,\
 415                                          prefix_type, rowsize,  \
 416                                          groupsize, buf, len, ascii)
 417
 418 #define wil_hex_dump_wmi(prefix_str, prefix_type, rowsize,      \
 419                          groupsize, buf, len, ascii)            \
 420                          print_hex_dump_debug("DBG[ WMI]" prefix_str,\
 421                                         prefix_type, rowsize,   \
 422                                         groupsize, buf, len, ascii)
 423
 424 void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
 425                           size_t count);
 426 void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
 427                         size_t count);
 428
 429 void *wil_if_alloc(struct device *dev, void __iomem *csr);
 430 void wil_if_free(struct wil6210_priv *wil);
 431 int wil_if_add(struct wil6210_priv *wil);
 432 void wil_if_remove(struct wil6210_priv *wil);
 433 int wil_priv_init(struct wil6210_priv *wil);
 434 void wil_priv_deinit(struct wil6210_priv *wil);
 435 int wil_reset(struct wil6210_priv *wil);
 436 void wil_link_on(struct wil6210_priv *wil);
 437 void wil_link_off(struct wil6210_priv *wil);
 438 int wil_up(struct wil6210_priv *wil);
 439 int wil_down(struct wil6210_priv *wil);
 440 void wil_mbox_ring_le2cpus(struct wil6210_mbox_ring *r);
 441 int wil_find_cid(struct wil6210_priv *wil, const u8 *mac);
 442
 443 void __iomem *wmi_buffer(struct wil6210_priv *wil, __le32 ptr);
 444 void __iomem *wmi_addr(struct wil6210_priv *wil, u32 ptr);
 445 int wmi_read_hdr(struct wil6210_priv *wil, __le32 ptr,
 446                  struct wil6210_mbox_hdr *hdr);
 447 int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len);
 448 void wmi_recv_cmd(struct wil6210_priv *wil);
 449 int wmi_call(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len,
 450              u16 reply_id, void *reply, u8 reply_size, int to_msec);
 451 void wmi_event_worker(struct work_struct *work);
 452 void wmi_event_flush(struct wil6210_priv *wil);
 453 int wmi_set_ssid(struct wil6210_priv *wil, u8 ssid_len, const void *ssid);
 454 int wmi_get_ssid(struct wil6210_priv *wil, u8 *ssid_len, void *ssid);
 455 int wmi_set_channel(struct wil6210_priv *wil, int channel);
 456 int wmi_get_channel(struct wil6210_priv *wil, int *channel);
 457 int wmi_del_cipher_key(struct wil6210_priv *wil, u8 key_index,
 458                        const void *mac_addr);
 459 int wmi_add_cipher_key(struct wil6210_priv *wil, u8 key_index,
 460                        const void *mac_addr, int key_len, const void *key);
 461 int wmi_echo(struct wil6210_priv *wil);
 462 int wmi_set_ie(struct wil6210_priv *wil, u8 type, u16 ie_len, const void *ie);
 463 int wmi_rx_chain_add(struct wil6210_priv *wil, struct vring *vring);
 464 int wmi_p2p_cfg(struct wil6210_priv *wil, int channel);
 465 int wmi_rxon(struct wil6210_priv *wil, bool on);
 466 int wmi_get_temperature(struct wil6210_priv *wil, u32 *t_m, u32 *t_r);
 467 int wmi_disconnect_sta(struct wil6210_priv *wil, const u8 *mac, u16 reason);
 468
 469 int wil6210_init_irq(struct wil6210_priv *wil, int irq);
 470 void wil6210_fini_irq(struct wil6210_priv *wil, int irq);
 471 void wil6210_disable_irq(struct wil6210_priv *wil);
 472 void wil6210_enable_irq(struct wil6210_priv *wil);
 473
 474 int wil6210_debugfs_init(struct wil6210_priv *wil);
 475 void wil6210_debugfs_remove(struct wil6210_priv *wil);
 476
 477 struct wireless_dev *wil_cfg80211_init(struct device *dev);
 478 void wil_wdev_free(struct wil6210_priv *wil);
 479
 480 int wmi_set_mac_address(struct wil6210_priv *wil, void *addr);
 481 int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, u8 chan);
 482 int wmi_pcp_stop(struct wil6210_priv *wil);
 483 void wil6210_disconnect(struct wil6210_priv *wil, void *bssid);
 484
 485 int wil_rx_init(struct wil6210_priv *wil);
 486 void wil_rx_fini(struct wil6210_priv *wil);
 487
 488 /* TX API */
 489 int wil_vring_init_tx(struct wil6210_priv *wil, int id, int size,
 490                       int cid, int tid);
 491 void wil_vring_fini_tx(struct wil6210_priv *wil, int id);
 492
 493 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev);
 494 int wil_tx_complete(struct wil6210_priv *wil, int ringid);
 495 void wil6210_unmask_irq_tx(struct wil6210_priv *wil);
 496
 497 /* RX API */
 498 void wil_rx_handle(struct wil6210_priv *wil, int *quota);
 499 void wil6210_unmask_irq_rx(struct wil6210_priv *wil);
 500
 501 int wil_iftype_nl2wmi(enum nl80211_iftype type);
 502
 503 #endif /* __WIL6210_H__ */