2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 /* Set this to 1 to disable regulatory domain restrictions for channel tests.
22 * WARNING: This is for debuging only and has side effects (eg. scan takes too
23 * long and results timeouts). It's also illegal to tune to some of the
24 * supported frequencies in some countries, so use this at your own risk,
25 * you've been warned. */
29 #include <linux/types.h>
30 #include <net/mac80211.h>
35 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
36 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
37 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
38 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
39 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
40 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
41 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
42 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
43 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
44 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
45 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
46 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
47 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
48 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
49 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
50 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
51 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
52 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
53 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
54 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
55 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
56 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
57 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
58 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
59 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
60 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
61 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
62 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
64 /****************************\
65 GENERIC DRIVER DEFINITIONS
66 \****************************/
68 #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
70 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
71 printk(_level "ath5k %s: " _fmt, \
72 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
75 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
76 if (net_ratelimit()) \
77 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
80 #define ATH5K_INFO(_sc, _fmt, ...) \
81 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
83 #define ATH5K_WARN(_sc, _fmt, ...) \
84 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
86 #define ATH5K_ERR(_sc, _fmt, ...) \
87 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
90 * Some tuneable values (these should be changeable by the user)
92 #define AR5K_TUNE_DMA_BEACON_RESP 2
93 #define AR5K_TUNE_SW_BEACON_RESP 10
94 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
95 #define AR5K_TUNE_RADAR_ALERT false
96 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
97 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
98 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
99 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
100 * be the max value. */
101 #define AR5K_TUNE_RSSI_THRES 129
102 /* This must be set when setting the RSSI threshold otherwise it can
103 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
104 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
105 * track of it. Max value depends on harware. For AR5210 this is just 7.
106 * For AR5211+ this seems to be up to 255. */
107 #define AR5K_TUNE_BMISS_THRES 7
108 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
109 #define AR5K_TUNE_BEACON_INTERVAL 100
110 #define AR5K_TUNE_AIFS 2
111 #define AR5K_TUNE_AIFS_11B 2
112 #define AR5K_TUNE_AIFS_XR 0
113 #define AR5K_TUNE_CWMIN 15
114 #define AR5K_TUNE_CWMIN_11B 31
115 #define AR5K_TUNE_CWMIN_XR 3
116 #define AR5K_TUNE_CWMAX 1023
117 #define AR5K_TUNE_CWMAX_11B 1023
118 #define AR5K_TUNE_CWMAX_XR 7
119 #define AR5K_TUNE_NOISE_FLOOR -72
120 #define AR5K_TUNE_MAX_TXPOWER 60
121 #define AR5K_TUNE_DEFAULT_TXPOWER 30
122 #define AR5K_TUNE_TPC_TXPOWER true
123 #define AR5K_TUNE_ANT_DIVERSITY true
124 #define AR5K_TUNE_HWTXTRIES 4
126 /* token to use for aifs, cwmin, cwmax in MadWiFi */
127 #define AR5K_TXQ_USEDEFAULT ((u32) -1)
129 /* GENERIC CHIPSET DEFINITIONS */
149 * Common silicon revision/version values
152 enum ath5k_srev_type
{
157 struct ath5k_srev_name
{
159 enum ath5k_srev_type sr_type
;
163 #define AR5K_SREV_UNKNOWN 0xffff
165 #define AR5K_SREV_VER_AR5210 0x00
166 #define AR5K_SREV_VER_AR5311 0x10
167 #define AR5K_SREV_VER_AR5311A 0x20
168 #define AR5K_SREV_VER_AR5311B 0x30
169 #define AR5K_SREV_VER_AR5211 0x40
170 #define AR5K_SREV_VER_AR5212 0x50
171 #define AR5K_SREV_VER_AR5213 0x55
172 #define AR5K_SREV_VER_AR5213A 0x59
173 #define AR5K_SREV_VER_AR2413 0x78
174 #define AR5K_SREV_VER_AR2414 0x79
175 #define AR5K_SREV_VER_AR2424 0xa0 /* PCI-E */
176 #define AR5K_SREV_VER_AR5424 0xa3 /* PCI-E */
177 #define AR5K_SREV_VER_AR5413 0xa4
178 #define AR5K_SREV_VER_AR5414 0xa5
179 #define AR5K_SREV_VER_AR5416 0xc0 /* PCI-E */
180 #define AR5K_SREV_VER_AR5418 0xca /* PCI-E */
181 #define AR5K_SREV_VER_AR2425 0xe2 /* PCI-E */
183 #define AR5K_SREV_RAD_5110 0x00
184 #define AR5K_SREV_RAD_5111 0x10
185 #define AR5K_SREV_RAD_5111A 0x15
186 #define AR5K_SREV_RAD_2111 0x20
187 #define AR5K_SREV_RAD_5112 0x30
188 #define AR5K_SREV_RAD_5112A 0x35
189 #define AR5K_SREV_RAD_5112B 0x36
190 #define AR5K_SREV_RAD_2112 0x40
191 #define AR5K_SREV_RAD_2112A 0x45
192 #define AR5K_SREV_RAD_2112B 0x46
193 #define AR5K_SREV_RAD_SC0 0x50 /* Found on 2413/2414 */
194 #define AR5K_SREV_RAD_SC1 0x60 /* Found on 5413/5414 */
195 #define AR5K_SREV_RAD_SC2 0xa0 /* Found on 2424-5/5424 */
196 #define AR5K_SREV_RAD_5133 0xc0 /* MIMO found on 5418 */
200 #define IEEE80211_MAX_LEN 2500
202 /* TODO add support to mac80211 for vendor-specific rates and modes */
205 * Some of this information is based on Documentation from:
207 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
209 * Modulation for Atheros' eXtended Range - range enhancing extension that is
210 * supposed to double the distance an Atheros client device can keep a
211 * connection with an Atheros access point. This is achieved by increasing
212 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
213 * the 802.11 specifications demand. In addition, new (proprietary) data rates
214 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
216 * Please note that can you either use XR or TURBO but you cannot use both,
217 * they are exclusive.
220 #define MODULATION_XR 0x00000200
222 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
223 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
224 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
225 * channels. To use this feature your Access Point must also suport it.
226 * There is also a distinction between "static" and "dynamic" turbo modes:
228 * - Static: is the dumb version: devices set to this mode stick to it until
229 * the mode is turned off.
230 * - Dynamic: is the intelligent version, the network decides itself if it
231 * is ok to use turbo. As soon as traffic is detected on adjacent channels
232 * (which would get used in turbo mode), or when a non-turbo station joins
233 * the network, turbo mode won't be used until the situation changes again.
234 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
235 * monitors the used radio band in order to decide whether turbo mode may
238 * This article claims Super G sticks to bonding of channels 5 and 6 for
241 * http://www.pcworld.com/article/id,113428-page,1/article.html
243 * The channel bonding seems to be driver specific though. In addition to
244 * deciding what channels will be used, these "Turbo" modes are accomplished
245 * by also enabling the following features:
247 * - Bursting: allows multiple frames to be sent at once, rather than pausing
248 * after each frame. Bursting is a standards-compliant feature that can be
249 * used with any Access Point.
250 * - Fast frames: increases the amount of information that can be sent per
251 * frame, also resulting in a reduction of transmission overhead. It is a
252 * proprietary feature that needs to be supported by the Access Point.
253 * - Compression: data frames are compressed in real time using a Lempel Ziv
254 * algorithm. This is done transparently. Once this feature is enabled,
255 * compression and decompression takes place inside the chipset, without
256 * putting additional load on the host CPU.
259 #define MODULATION_TURBO 0x00000080
261 enum ath5k_driver_mode
{
263 AR5K_MODE_11A_TURBO
= 1,
266 AR5K_MODE_11G_TURBO
= 4,
271 /* adding this flag to rate_code enables short preamble, see ar5212_reg.h */
272 #define AR5K_SET_SHORT_PREAMBLE 0x04
282 struct ath5k_tx_status
{
294 #define AR5K_TXSTAT_ALTRATE 0x80
295 #define AR5K_TXERR_XRETRY 0x01
296 #define AR5K_TXERR_FILT 0x02
297 #define AR5K_TXERR_FIFO 0x04
300 * enum ath5k_tx_queue - Queue types used to classify tx queues.
301 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
302 * @AR5K_TX_QUEUE_DATA: A normal data queue
303 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
304 * @AR5K_TX_QUEUE_BEACON: The beacon queue
305 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
306 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
308 enum ath5k_tx_queue
{
309 AR5K_TX_QUEUE_INACTIVE
= 0,
311 AR5K_TX_QUEUE_XR_DATA
,
312 AR5K_TX_QUEUE_BEACON
,
317 #define AR5K_NUM_TX_QUEUES 10
318 #define AR5K_NUM_TX_QUEUES_NOQCU 2
321 * Queue syb-types to classify normal data queues.
322 * These are the 4 Access Categories as defined in
323 * WME spec. 0 is the lowest priority and 4 is the
324 * highest. Normal data that hasn't been classified
325 * goes to the Best Effort AC.
327 enum ath5k_tx_queue_subtype
{
328 AR5K_WME_AC_BK
= 0, /*Background traffic*/
329 AR5K_WME_AC_BE
, /*Best-effort (normal) traffic)*/
330 AR5K_WME_AC_VI
, /*Video traffic*/
331 AR5K_WME_AC_VO
, /*Voice traffic*/
335 * Queue ID numbers as returned by the hw functions, each number
336 * represents a hw queue. If hw does not support hw queues
337 * (eg 5210) all data goes in one queue. These match
338 * d80211 definitions (net80211/MadWiFi don't use them).
340 enum ath5k_tx_queue_id
{
341 AR5K_TX_QUEUE_ID_NOQCU_DATA
= 0,
342 AR5K_TX_QUEUE_ID_NOQCU_BEACON
= 1,
343 AR5K_TX_QUEUE_ID_DATA_MIN
= 0, /*IEEE80211_TX_QUEUE_DATA0*/
344 AR5K_TX_QUEUE_ID_DATA_MAX
= 4, /*IEEE80211_TX_QUEUE_DATA4*/
345 AR5K_TX_QUEUE_ID_DATA_SVP
= 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
346 AR5K_TX_QUEUE_ID_CAB
= 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
347 AR5K_TX_QUEUE_ID_BEACON
= 7, /*IEEE80211_TX_QUEUE_BEACON*/
348 AR5K_TX_QUEUE_ID_UAPSD
= 8,
349 AR5K_TX_QUEUE_ID_XR_DATA
= 9,
354 * Flags to set hw queue's parameters...
356 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
357 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
358 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
359 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
360 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
361 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0020 /* Disable random post-backoff */
362 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0040 /* Enable ready time expiry policy (?)*/
363 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0080 /* Enable backoff while bursting */
364 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0100 /* Disable backoff while bursting */
365 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0200 /* Enable hw compression -not implemented-*/
368 * A struct to hold tx queue's parameters
370 struct ath5k_txq_info
{
371 enum ath5k_tx_queue tqi_type
;
372 enum ath5k_tx_queue_subtype tqi_subtype
;
373 u16 tqi_flags
; /* Tx queue flags (see above) */
374 u32 tqi_aifs
; /* Arbitrated Interframe Space */
375 s32 tqi_cw_min
; /* Minimum Contention Window */
376 s32 tqi_cw_max
; /* Maximum Contention Window */
377 u32 tqi_cbr_period
; /* Constant bit rate period */
378 u32 tqi_cbr_overflow_limit
;
380 u32 tqi_ready_time
; /* Not used */
384 * Transmit packet types.
385 * These are not fully used inside OpenHAL yet
387 enum ath5k_pkt_type
{
388 AR5K_PKT_TYPE_NORMAL
= 0,
389 AR5K_PKT_TYPE_ATIM
= 1,
390 AR5K_PKT_TYPE_PSPOLL
= 2,
391 AR5K_PKT_TYPE_BEACON
= 3,
392 AR5K_PKT_TYPE_PROBE_RESP
= 4,
393 AR5K_PKT_TYPE_PIFS
= 5,
397 * TX power and TPC settings
399 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
400 ((0 & 1) << ((_v) + 6)) | \
401 (((ah->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
404 #define AR5K_TXPOWER_CCK(_r, _v) ( \
405 (ah->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
409 * DMA size definitions (2^n+2)
430 struct ath5k_rx_status
{
442 #define AR5K_RXERR_CRC 0x01
443 #define AR5K_RXERR_PHY 0x02
444 #define AR5K_RXERR_FIFO 0x04
445 #define AR5K_RXERR_DECRYPT 0x08
446 #define AR5K_RXERR_MIC 0x10
447 #define AR5K_RXKEYIX_INVALID ((u8) - 1)
448 #define AR5K_TXKEYIX_INVALID ((u32) - 1)
451 /**************************\
452 BEACON TIMERS DEFINITIONS
453 \**************************/
455 #define AR5K_BEACON_PERIOD 0x0000ffff
456 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
457 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
461 * struct ath5k_beacon_state - Per-station beacon timer state.
462 * @bs_interval: in TU's, can also include the above flags
463 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
464 * Point Coordination Function capable AP
466 struct ath5k_beacon_state
{
472 u16 bs_cfp_max_duration
;
473 u16 bs_cfp_du_remain
;
475 u16 bs_sleep_duration
;
476 u16 bs_bmiss_threshold
;
483 * TSF to TU conversion:
485 * TSF is a 64bit value in usec (microseconds).
486 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
487 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
489 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
492 /********************\
494 \********************/
497 * Atheros hardware descriptor
498 * This is read and written to by the hardware
501 u32 ds_link
; /* physical address of the next descriptor */
502 u32 ds_data
; /* physical address of data buffer (skb) */
505 struct ath5k_hw_5210_tx_desc ds_tx5210
;
506 struct ath5k_hw_5212_tx_desc ds_tx5212
;
507 struct ath5k_hw_all_rx_desc ds_rx
;
511 #define AR5K_RXDESC_INTREQ 0x0020
513 #define AR5K_TXDESC_CLRDMASK 0x0001
514 #define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/
515 #define AR5K_TXDESC_RTSENA 0x0004
516 #define AR5K_TXDESC_CTSENA 0x0008
517 #define AR5K_TXDESC_INTREQ 0x0010
518 #define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/
520 #define AR5K_SLOT_TIME_9 396
521 #define AR5K_SLOT_TIME_20 880
522 #define AR5K_SLOT_TIME_MAX 0xffff
525 #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
526 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */
527 #define CHANNEL_CCK 0x0020 /* CCK channel */
528 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
529 #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
530 #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
531 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
532 #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
533 #define CHANNEL_XR 0x0800 /* XR channel */
535 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
536 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
537 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
538 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
539 #define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
540 #define CHANNEL_108A CHANNEL_T
541 #define CHANNEL_108G CHANNEL_TG
542 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
544 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
547 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
548 #define CHANNEL_MODES CHANNEL_ALL
551 * Used internaly in OpenHAL (ar5211.c/ar5212.c
552 * for reset_tx_queue). Also see struct struct ieee80211_channel.
554 #define IS_CHAN_XR(_c) ((_c.hw_value & CHANNEL_XR) != 0)
555 #define IS_CHAN_B(_c) ((_c.hw_value & CHANNEL_B) != 0)
558 * The following structure will be used to map 2GHz channels to
559 * 5GHz Atheros channels.
561 struct ath5k_athchan_2ghz
{
572 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
574 * The rate code is used to get the RX rate or set the TX rate on the
575 * hardware descriptors. It is also used for internal modulation control
578 * This is the hardware rate map we are aware of:
580 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
581 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
583 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
584 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
586 * rate_code 17 18 19 20 21 22 23 24
587 * rate_kbps ? ? ? ? ? ? ? 11000
589 * rate_code 25 26 27 28 29 30 31 32
590 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
592 * "S" indicates CCK rates with short preamble.
594 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
595 * lowest 4 bits, so they are the same as below with a 0xF mask.
596 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
597 * We handle this in ath5k_setup_bands().
599 #define AR5K_MAX_RATES 32
602 #define ATH5K_RATE_CODE_1M 0x1B
603 #define ATH5K_RATE_CODE_2M 0x1A
604 #define ATH5K_RATE_CODE_5_5M 0x19
605 #define ATH5K_RATE_CODE_11M 0x18
607 #define ATH5K_RATE_CODE_6M 0x0B
608 #define ATH5K_RATE_CODE_9M 0x0F
609 #define ATH5K_RATE_CODE_12M 0x0A
610 #define ATH5K_RATE_CODE_18M 0x0E
611 #define ATH5K_RATE_CODE_24M 0x09
612 #define ATH5K_RATE_CODE_36M 0x0D
613 #define ATH5K_RATE_CODE_48M 0x08
614 #define ATH5K_RATE_CODE_54M 0x0C
616 #define ATH5K_RATE_CODE_XR_500K 0x07
617 #define ATH5K_RATE_CODE_XR_1M 0x02
618 #define ATH5K_RATE_CODE_XR_2M 0x06
619 #define ATH5K_RATE_CODE_XR_3M 0x01
626 #define AR5K_KEYCACHE_SIZE 8
628 /***********************\
629 HW RELATED DEFINITIONS
630 \***********************/
635 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
637 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
643 enum ath5k_ant_setting
{
644 AR5K_ANT_VARIABLE
= 0, /* variable by programming */
645 AR5K_ANT_FIXED_A
= 1, /* fixed to 11a frequencies */
646 AR5K_ANT_FIXED_B
= 2, /* fixed to 11b frequencies */
651 * Hardware interrupt abstraction
655 * enum ath5k_int - Hardware interrupt masks helpers
657 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
658 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
659 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
660 * @AR5K_INT_RXNOFRM: No frame received (?)
661 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
662 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
663 * LinkPtr is NULL. For more details, refer to:
664 * http://www.freepatentsonline.com/20030225739.html
665 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
666 * Note that Rx overrun is not always fatal, on some chips we can continue
667 * operation without reseting the card, that's why int_fatal is not
668 * common for all chips.
669 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
670 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
671 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
672 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
673 * We currently do increments on interrupt by
674 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
675 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
676 * checked. We should do this with ath5k_hw_update_mib_counters() but
677 * it seems we should also then do some noise immunity work.
678 * @AR5K_INT_RXPHY: RX PHY Error
679 * @AR5K_INT_RXKCM: ??
680 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
681 * beacon that must be handled in software. The alternative is if you
682 * have VEOL support, in that case you let the hardware deal with things.
683 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
684 * beacons from the AP have associated with, we should probably try to
685 * reassociate. When in IBSS mode this might mean we have not received
686 * any beacons from any local stations. Note that every station in an
687 * IBSS schedules to send beacons at the Target Beacon Transmission Time
688 * (TBTT) with a random backoff.
689 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
690 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
691 * until properly handled
692 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
693 * errors. These types of errors we can enable seem to be of type
694 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
695 * @AR5K_INT_GLOBAL: Seems to be used to clear and set the IER
696 * @AR5K_INT_NOCARD: signals the card has been removed
697 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
700 * These are mapped to take advantage of some common bits
701 * between the MACs, to be able to set intr properties
702 * easier. Some of them are not used yet inside hw.c. Most map
703 * to the respective hw interrupt value as they are common amogst different
707 AR5K_INT_RX
= 0x00000001, /* Not common */
708 AR5K_INT_RXDESC
= 0x00000002,
709 AR5K_INT_RXNOFRM
= 0x00000008,
710 AR5K_INT_RXEOL
= 0x00000010,
711 AR5K_INT_RXORN
= 0x00000020,
712 AR5K_INT_TX
= 0x00000040, /* Not common */
713 AR5K_INT_TXDESC
= 0x00000080,
714 AR5K_INT_TXURN
= 0x00000800,
715 AR5K_INT_MIB
= 0x00001000,
716 AR5K_INT_RXPHY
= 0x00004000,
717 AR5K_INT_RXKCM
= 0x00008000,
718 AR5K_INT_SWBA
= 0x00010000,
719 AR5K_INT_BMISS
= 0x00040000,
720 AR5K_INT_BNR
= 0x00100000, /* Not common */
721 AR5K_INT_GPIO
= 0x01000000,
722 AR5K_INT_FATAL
= 0x40000000, /* Not common */
723 AR5K_INT_GLOBAL
= 0x80000000,
725 AR5K_INT_COMMON
= AR5K_INT_RXNOFRM
737 AR5K_INT_NOCARD
= 0xffffffff
743 enum ath5k_power_mode
{
744 AR5K_PM_UNDEFINED
= 0,
748 AR5K_PM_NETWORK_SLEEP
,
752 * These match net80211 definitions (not used in
755 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
756 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
757 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
758 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
759 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
761 /* GPIO-controlled software LED */
762 #define AR5K_SOFTLED_PIN 0
763 #define AR5K_SOFTLED_ON 0
764 #define AR5K_SOFTLED_OFF 1
767 * Chipset capabilities -see ath5k_hw_get_capability-
768 * get_capability function is not yet fully implemented
769 * in OpenHAL so most of these don't work yet...
771 enum ath5k_capability_type
{
772 AR5K_CAP_REG_DMN
= 0, /* Used to get current reg. domain id */
773 AR5K_CAP_TKIP_MIC
= 2, /* Can handle TKIP MIC in hardware */
774 AR5K_CAP_TKIP_SPLIT
= 3, /* TKIP uses split keys */
775 AR5K_CAP_PHYCOUNTERS
= 4, /* PHY error counters */
776 AR5K_CAP_DIVERSITY
= 5, /* Supports fast diversity */
777 AR5K_CAP_NUM_TXQUEUES
= 6, /* Used to get max number of hw txqueues */
778 AR5K_CAP_VEOL
= 7, /* Supports virtual EOL */
779 AR5K_CAP_COMPRESSION
= 8, /* Supports compression */
780 AR5K_CAP_BURST
= 9, /* Supports packet bursting */
781 AR5K_CAP_FASTFRAME
= 10, /* Supports fast frames */
782 AR5K_CAP_TXPOW
= 11, /* Used to get global tx power limit */
783 AR5K_CAP_TPC
= 12, /* Can do per-packet tx power control (needed for 802.11a) */
784 AR5K_CAP_BSSIDMASK
= 13, /* Supports bssid mask */
785 AR5K_CAP_MCAST_KEYSRCH
= 14, /* Supports multicast key search */
786 AR5K_CAP_TSF_ADJUST
= 15, /* Supports beacon tsf adjust */
787 AR5K_CAP_XR
= 16, /* Supports XR mode */
788 AR5K_CAP_WME_TKIPMIC
= 17, /* Supports TKIP MIC when using WMM */
789 AR5K_CAP_CHAN_HALFRATE
= 18, /* Supports half rate channels */
790 AR5K_CAP_CHAN_QUARTERRATE
= 19, /* Supports quarter rate channels */
791 AR5K_CAP_RFSILENT
= 20, /* Supports RFsilent */
795 /* XXX: we *may* move cap_range stuff to struct wiphy */
796 struct ath5k_capabilities
{
798 * Supported PHY modes
799 * (ie. CHANNEL_A, CHANNEL_B, ...)
801 DECLARE_BITMAP(cap_mode
, AR5K_MODE_MAX
);
804 * Frequency range (without regulation restrictions)
814 * Values stored in the EEPROM (some of them...)
816 struct ath5k_eeprom_info cap_eeprom
;
827 /***************************************\
828 HARDWARE ABSTRACTION LAYER STRUCTURE
829 \***************************************/
835 #define AR5K_MAX_GPIO 10
836 #define AR5K_MAX_RF_BANKS 8
841 struct ath5k_softc
*ah_sc
;
842 void __iomem
*ah_iobase
;
844 enum ath5k_int ah_imr
;
846 enum ieee80211_if_types ah_op_mode
;
847 enum ath5k_power_mode ah_power_mode
;
848 struct ieee80211_channel ah_current_channel
;
853 enum ath5k_rfgain ah_rf_gain
;
859 u16 ah_radio_5ghz_revision
;
860 u16 ah_radio_2ghz_revision
;
863 enum ath5k_version ah_version
;
864 enum ath5k_radio ah_radio
;
870 #define ah_regdomain ah_capabilities.cap_regdomain.reg_current
871 #define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
872 #define ah_modes ah_capabilities.cap_mode
873 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
879 bool ah_software_retry
;
880 u32 ah_limit_tx_retries
;
882 u32 ah_antenna
[AR5K_EEPROM_N_MODES
][AR5K_ANT_MAX
];
883 bool ah_ant_diversity
;
885 u8 ah_sta_id
[ETH_ALEN
];
887 /* Current BSSID we are trying to assoc to / creating.
888 * This is passed by mac80211 on config_interface() and cached here for
890 u8 ah_bssid
[ETH_ALEN
];
892 u32 ah_gpio
[AR5K_MAX_GPIO
];
895 struct ath5k_capabilities ah_capabilities
;
897 struct ath5k_txq_info ah_txq
[AR5K_NUM_TX_QUEUES
];
900 u32 ah_txq_imr_txerr
;
901 u32 ah_txq_imr_txurn
;
902 u32 ah_txq_imr_txdesc
;
903 u32 ah_txq_imr_txeol
;
905 size_t ah_rf_banks_size
;
906 struct ath5k_gain ah_gain
;
907 u32 ah_offset
[AR5K_MAX_RF_BANKS
];
910 u16 txp_pcdac
[AR5K_EEPROM_POWER_TABLE_SIZE
];
911 u16 txp_rates
[AR5K_MAX_RATES
];
921 struct ieee80211_channel r_last_channel
;
924 /* noise floor from last periodic calibration */
930 int (*ah_setup_tx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
931 unsigned int, unsigned int, enum ath5k_pkt_type
, unsigned int,
932 unsigned int, unsigned int, unsigned int, unsigned int,
933 unsigned int, unsigned int, unsigned int);
934 int (*ah_setup_xtx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
935 unsigned int, unsigned int, unsigned int, unsigned int,
936 unsigned int, unsigned int);
937 int (*ah_proc_tx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
938 struct ath5k_tx_status
*);
939 int (*ah_proc_rx_desc
)(struct ath5k_hw
*, struct ath5k_desc
*,
940 struct ath5k_rx_status
*);
947 /* General Functions */
948 extern int ath5k_hw_register_timeout(struct ath5k_hw
*ah
, u32 reg
, u32 flag
, u32 val
, bool is_set
);
949 /* Attach/Detach Functions */
950 extern struct ath5k_hw
*ath5k_hw_attach(struct ath5k_softc
*sc
, u8 mac_version
);
951 extern const struct ath5k_rate_table
*ath5k_hw_get_rate_table(struct ath5k_hw
*ah
, unsigned int mode
);
952 extern void ath5k_hw_detach(struct ath5k_hw
*ah
);
953 /* Reset Functions */
954 extern int ath5k_hw_reset(struct ath5k_hw
*ah
, enum ieee80211_if_types op_mode
, struct ieee80211_channel
*channel
, bool change_channel
);
955 /* Power management functions */
956 extern int ath5k_hw_set_power(struct ath5k_hw
*ah
, enum ath5k_power_mode mode
, bool set_chip
, u16 sleep_duration
);
957 /* DMA Related Functions */
958 extern void ath5k_hw_start_rx(struct ath5k_hw
*ah
);
959 extern int ath5k_hw_stop_rx_dma(struct ath5k_hw
*ah
);
960 extern u32
ath5k_hw_get_rx_buf(struct ath5k_hw
*ah
);
961 extern void ath5k_hw_put_rx_buf(struct ath5k_hw
*ah
, u32 phys_addr
);
962 extern int ath5k_hw_tx_start(struct ath5k_hw
*ah
, unsigned int queue
);
963 extern int ath5k_hw_stop_tx_dma(struct ath5k_hw
*ah
, unsigned int queue
);
964 extern u32
ath5k_hw_get_tx_buf(struct ath5k_hw
*ah
, unsigned int queue
);
965 extern int ath5k_hw_put_tx_buf(struct ath5k_hw
*ah
, unsigned int queue
, u32 phys_addr
);
966 extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw
*ah
, bool increase
);
967 /* Interrupt handling */
968 extern bool ath5k_hw_is_intr_pending(struct ath5k_hw
*ah
);
969 extern int ath5k_hw_get_isr(struct ath5k_hw
*ah
, enum ath5k_int
*interrupt_mask
);
970 extern enum ath5k_int
ath5k_hw_set_intr(struct ath5k_hw
*ah
, enum ath5k_int new_mask
);
971 extern void ath5k_hw_update_mib_counters(struct ath5k_hw
*ah
, struct ieee80211_low_level_stats
*stats
);
972 /* EEPROM access functions */
973 extern int ath5k_hw_set_regdomain(struct ath5k_hw
*ah
, u16 regdomain
);
974 /* Protocol Control Unit Functions */
975 extern int ath5k_hw_set_opmode(struct ath5k_hw
*ah
);
976 /* BSSID Functions */
977 extern void ath5k_hw_get_lladdr(struct ath5k_hw
*ah
, u8
*mac
);
978 extern int ath5k_hw_set_lladdr(struct ath5k_hw
*ah
, const u8
*mac
);
979 extern void ath5k_hw_set_associd(struct ath5k_hw
*ah
, const u8
*bssid
, u16 assoc_id
);
980 extern int ath5k_hw_set_bssid_mask(struct ath5k_hw
*ah
, const u8
*mask
);
981 /* Receive start/stop functions */
982 extern void ath5k_hw_start_rx_pcu(struct ath5k_hw
*ah
);
983 extern void ath5k_hw_stop_pcu_recv(struct ath5k_hw
*ah
);
984 /* RX Filter functions */
985 extern void ath5k_hw_set_mcast_filter(struct ath5k_hw
*ah
, u32 filter0
, u32 filter1
);
986 extern int ath5k_hw_set_mcast_filterindex(struct ath5k_hw
*ah
, u32 index
);
987 extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw
*ah
, u32 index
);
988 extern u32
ath5k_hw_get_rx_filter(struct ath5k_hw
*ah
);
989 extern void ath5k_hw_set_rx_filter(struct ath5k_hw
*ah
, u32 filter
);
990 /* Beacon related functions */
991 extern u32
ath5k_hw_get_tsf32(struct ath5k_hw
*ah
);
992 extern u64
ath5k_hw_get_tsf64(struct ath5k_hw
*ah
);
993 extern void ath5k_hw_reset_tsf(struct ath5k_hw
*ah
);
994 extern void ath5k_hw_init_beacon(struct ath5k_hw
*ah
, u32 next_beacon
, u32 interval
);
996 extern int ath5k_hw_set_beacon_timers(struct ath5k_hw
*ah
, const struct ath5k_beacon_state
*state
);
997 extern void ath5k_hw_reset_beacon(struct ath5k_hw
*ah
);
998 extern int ath5k_hw_beaconq_finish(struct ath5k_hw
*ah
, unsigned long phys_addr
);
1001 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw
*ah
, bool high
);
1002 /* ACK/CTS Timeouts */
1003 extern int ath5k_hw_set_ack_timeout(struct ath5k_hw
*ah
, unsigned int timeout
);
1004 extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw
*ah
);
1005 extern int ath5k_hw_set_cts_timeout(struct ath5k_hw
*ah
, unsigned int timeout
);
1006 extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw
*ah
);
1007 /* Key table (WEP) functions */
1008 extern int ath5k_hw_reset_key(struct ath5k_hw
*ah
, u16 entry
);
1009 extern int ath5k_hw_is_key_valid(struct ath5k_hw
*ah
, u16 entry
);
1010 extern int ath5k_hw_set_key(struct ath5k_hw
*ah
, u16 entry
, const struct ieee80211_key_conf
*key
, const u8
*mac
);
1011 extern int ath5k_hw_set_key_lladdr(struct ath5k_hw
*ah
, u16 entry
, const u8
*mac
);
1012 /* Queue Control Unit, DFS Control Unit Functions */
1013 extern int ath5k_hw_setup_tx_queue(struct ath5k_hw
*ah
, enum ath5k_tx_queue queue_type
, struct ath5k_txq_info
*queue_info
);
1014 extern int ath5k_hw_setup_tx_queueprops(struct ath5k_hw
*ah
, int queue
, const struct ath5k_txq_info
*queue_info
);
1015 extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw
*ah
, int queue
, struct ath5k_txq_info
*queue_info
);
1016 extern void ath5k_hw_release_tx_queue(struct ath5k_hw
*ah
, unsigned int queue
);
1017 extern int ath5k_hw_reset_tx_queue(struct ath5k_hw
*ah
, unsigned int queue
);
1018 extern u32
ath5k_hw_num_tx_pending(struct ath5k_hw
*ah
, unsigned int queue
);
1019 extern int ath5k_hw_set_slot_time(struct ath5k_hw
*ah
, unsigned int slot_time
);
1020 extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw
*ah
);
1021 /* Hardware Descriptor Functions */
1022 extern int ath5k_hw_setup_rx_desc(struct ath5k_hw
*ah
, struct ath5k_desc
*desc
, u32 size
, unsigned int flags
);
1023 /* GPIO Functions */
1024 extern void ath5k_hw_set_ledstate(struct ath5k_hw
*ah
, unsigned int state
);
1025 extern int ath5k_hw_set_gpio_output(struct ath5k_hw
*ah
, u32 gpio
);
1026 extern int ath5k_hw_set_gpio_input(struct ath5k_hw
*ah
, u32 gpio
);
1027 extern u32
ath5k_hw_get_gpio(struct ath5k_hw
*ah
, u32 gpio
);
1028 extern int ath5k_hw_set_gpio(struct ath5k_hw
*ah
, u32 gpio
, u32 val
);
1029 extern void ath5k_hw_set_gpio_intr(struct ath5k_hw
*ah
, unsigned int gpio
, u32 interrupt_level
);
1030 /* Misc functions */
1031 extern int ath5k_hw_get_capability(struct ath5k_hw
*ah
, enum ath5k_capability_type cap_type
, u32 capability
, u32
*result
);
1034 /* Initial register settings functions */
1035 extern int ath5k_hw_write_initvals(struct ath5k_hw
*ah
, u8 mode
, bool change_channel
);
1037 extern int ath5k_hw_rfregs(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
, unsigned int mode
);
1038 extern int ath5k_hw_rfgain(struct ath5k_hw
*ah
, unsigned int freq
);
1039 extern enum ath5k_rfgain
ath5k_hw_get_rf_gain(struct ath5k_hw
*ah
);
1040 extern int ath5k_hw_set_rfgain_opt(struct ath5k_hw
*ah
);
1043 /* PHY/RF channel functions */
1044 extern bool ath5k_channel_ok(struct ath5k_hw
*ah
, u16 freq
, unsigned int flags
);
1045 extern int ath5k_hw_channel(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
);
1046 /* PHY calibration */
1047 extern int ath5k_hw_phy_calibrate(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
);
1048 extern int ath5k_hw_phy_disable(struct ath5k_hw
*ah
);
1049 /* Misc PHY functions */
1050 extern u16
ath5k_hw_radio_revision(struct ath5k_hw
*ah
, unsigned int chan
);
1051 extern void ath5k_hw_set_def_antenna(struct ath5k_hw
*ah
, unsigned int ant
);
1052 extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw
*ah
);
1053 extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw
*ah
, short freq
);
1054 /* TX power setup */
1055 extern int ath5k_hw_txpower(struct ath5k_hw
*ah
, struct ieee80211_channel
*channel
, unsigned int txpower
);
1056 extern int ath5k_hw_set_txpower_limit(struct ath5k_hw
*ah
, unsigned int power
);
1059 static inline u32
ath5k_hw_reg_read(struct ath5k_hw
*ah
, u16 reg
)
1061 return ioread32(ah
->ah_iobase
+ reg
);
1064 static inline void ath5k_hw_reg_write(struct ath5k_hw
*ah
, u32 val
, u16 reg
)
1066 iowrite32(val
, ah
->ah_iobase
+ reg
);