2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
70 MODULE_AUTHOR("Jiri Slaby");
71 MODULE_AUTHOR("Nick Kossifidis");
72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74 MODULE_LICENSE("Dual BSD/GPL");
75 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
79 static struct pci_device_id ath5k_pci_id_table
[] __devinitdata
= {
80 { PCI_VDEVICE(ATHEROS
, 0x0207), .driver_data
= AR5K_AR5210
}, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS
, 0x0007), .driver_data
= AR5K_AR5210
}, /* 5210 */
82 { PCI_VDEVICE(ATHEROS
, 0x0011), .driver_data
= AR5K_AR5211
}, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS
, 0x0012), .driver_data
= AR5K_AR5211
}, /* 5211 */
84 { PCI_VDEVICE(ATHEROS
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 5212 */
85 { PCI_VDEVICE(3COM_2
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 5212 */
86 { PCI_VDEVICE(3COM
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS
, 0x1014), .driver_data
= AR5K_AR5212
}, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS
, 0x0014), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS
, 0x0015), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS
, 0x0016), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS
, 0x0017), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS
, 0x0018), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS
, 0x0019), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS
, 0x001a), .driver_data
= AR5K_AR5212
}, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS
, 0x001b), .driver_data
= AR5K_AR5212
}, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS
, 0x001c), .driver_data
= AR5K_AR5212
}, /* PCI-E cards */
97 { PCI_VDEVICE(ATHEROS
, 0x001d), .driver_data
= AR5K_AR5212
}, /* 2417 Nala */
100 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
103 static struct ath5k_srev_name srev_names
[] = {
104 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
105 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
106 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
107 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
108 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
109 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
110 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
111 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
112 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
113 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
114 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
115 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
116 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
117 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
118 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
119 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
120 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
121 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
122 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
123 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
124 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
125 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
126 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
127 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
128 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
129 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
130 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
131 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
132 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
133 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
134 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
135 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
136 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
137 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
138 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
139 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
142 static struct ieee80211_rate ath5k_rates
[] = {
144 .hw_value
= ATH5K_RATE_CODE_1M
, },
146 .hw_value
= ATH5K_RATE_CODE_2M
,
147 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
148 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
150 .hw_value
= ATH5K_RATE_CODE_5_5M
,
151 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
152 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
154 .hw_value
= ATH5K_RATE_CODE_11M
,
155 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
156 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
158 .hw_value
= ATH5K_RATE_CODE_6M
,
161 .hw_value
= ATH5K_RATE_CODE_9M
,
164 .hw_value
= ATH5K_RATE_CODE_12M
,
167 .hw_value
= ATH5K_RATE_CODE_18M
,
170 .hw_value
= ATH5K_RATE_CODE_24M
,
173 .hw_value
= ATH5K_RATE_CODE_36M
,
176 .hw_value
= ATH5K_RATE_CODE_48M
,
179 .hw_value
= ATH5K_RATE_CODE_54M
,
185 * Prototypes - PCI stack related functions
187 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
188 const struct pci_device_id
*id
);
189 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
191 static int ath5k_pci_suspend(struct pci_dev
*pdev
,
193 static int ath5k_pci_resume(struct pci_dev
*pdev
);
195 #define ath5k_pci_suspend NULL
196 #define ath5k_pci_resume NULL
197 #endif /* CONFIG_PM */
199 static struct pci_driver ath5k_pci_driver
= {
201 .id_table
= ath5k_pci_id_table
,
202 .probe
= ath5k_pci_probe
,
203 .remove
= __devexit_p(ath5k_pci_remove
),
204 .suspend
= ath5k_pci_suspend
,
205 .resume
= ath5k_pci_resume
,
211 * Prototypes - MAC 802.11 stack related functions
213 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
214 static int ath5k_reset(struct ath5k_softc
*sc
, bool stop
, bool change_channel
);
215 static int ath5k_reset_wake(struct ath5k_softc
*sc
);
216 static int ath5k_start(struct ieee80211_hw
*hw
);
217 static void ath5k_stop(struct ieee80211_hw
*hw
);
218 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
219 struct ieee80211_if_init_conf
*conf
);
220 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
221 struct ieee80211_if_init_conf
*conf
);
222 static int ath5k_config(struct ieee80211_hw
*hw
,
223 struct ieee80211_conf
*conf
);
224 static int ath5k_config_interface(struct ieee80211_hw
*hw
,
225 struct ieee80211_vif
*vif
,
226 struct ieee80211_if_conf
*conf
);
227 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
228 unsigned int changed_flags
,
229 unsigned int *new_flags
,
230 int mc_count
, struct dev_mc_list
*mclist
);
231 static int ath5k_set_key(struct ieee80211_hw
*hw
,
232 enum set_key_cmd cmd
,
233 const u8
*local_addr
, const u8
*addr
,
234 struct ieee80211_key_conf
*key
);
235 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
236 struct ieee80211_low_level_stats
*stats
);
237 static int ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
238 struct ieee80211_tx_queue_stats
*stats
);
239 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
240 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
241 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
242 struct sk_buff
*skb
);
243 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
244 struct ieee80211_vif
*vif
,
245 struct ieee80211_bss_conf
*bss_conf
,
248 static struct ieee80211_ops ath5k_hw_ops
= {
250 .start
= ath5k_start
,
252 .add_interface
= ath5k_add_interface
,
253 .remove_interface
= ath5k_remove_interface
,
254 .config
= ath5k_config
,
255 .config_interface
= ath5k_config_interface
,
256 .configure_filter
= ath5k_configure_filter
,
257 .set_key
= ath5k_set_key
,
258 .get_stats
= ath5k_get_stats
,
260 .get_tx_stats
= ath5k_get_tx_stats
,
261 .get_tsf
= ath5k_get_tsf
,
262 .reset_tsf
= ath5k_reset_tsf
,
263 .bss_info_changed
= ath5k_bss_info_changed
,
267 * Prototypes - Internal functions
270 static int ath5k_attach(struct pci_dev
*pdev
,
271 struct ieee80211_hw
*hw
);
272 static void ath5k_detach(struct pci_dev
*pdev
,
273 struct ieee80211_hw
*hw
);
274 /* Channel/mode setup */
275 static inline short ath5k_ieee2mhz(short chan
);
276 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
277 struct ieee80211_channel
*channels
,
280 static int ath5k_setup_bands(struct ieee80211_hw
*hw
);
281 static int ath5k_chan_set(struct ath5k_softc
*sc
,
282 struct ieee80211_channel
*chan
);
283 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
285 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
287 /* Descriptor setup */
288 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
289 struct pci_dev
*pdev
);
290 static void ath5k_desc_free(struct ath5k_softc
*sc
,
291 struct pci_dev
*pdev
);
293 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
294 struct ath5k_buf
*bf
);
295 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
296 struct ath5k_buf
*bf
);
297 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
298 struct ath5k_buf
*bf
)
303 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
305 dev_kfree_skb_any(bf
->skb
);
310 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
311 int qtype
, int subtype
);
312 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
313 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
314 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
315 struct ath5k_txq
*txq
);
316 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
317 static void ath5k_txq_release(struct ath5k_softc
*sc
);
319 static int ath5k_rx_start(struct ath5k_softc
*sc
);
320 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
321 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
322 struct ath5k_desc
*ds
,
324 struct ath5k_rx_status
*rs
);
325 static void ath5k_tasklet_rx(unsigned long data
);
327 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
328 struct ath5k_txq
*txq
);
329 static void ath5k_tasklet_tx(unsigned long data
);
330 /* Beacon handling */
331 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
332 struct ath5k_buf
*bf
);
333 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
334 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
335 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
337 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
339 u64 tsf
= ath5k_hw_get_tsf64(ah
);
341 if ((tsf
& 0x7fff) < rstamp
)
344 return (tsf
& ~0x7fff) | rstamp
;
347 /* Interrupt handling */
348 static int ath5k_init(struct ath5k_softc
*sc
, bool is_resume
);
349 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
350 static int ath5k_stop_hw(struct ath5k_softc
*sc
, bool is_suspend
);
351 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
352 static void ath5k_tasklet_reset(unsigned long data
);
354 static void ath5k_calibrate(unsigned long data
);
356 static int ath5k_init_leds(struct ath5k_softc
*sc
);
357 static void ath5k_led_enable(struct ath5k_softc
*sc
);
358 static void ath5k_led_off(struct ath5k_softc
*sc
);
359 static void ath5k_unregister_leds(struct ath5k_softc
*sc
);
362 * Module init/exit functions
371 ret
= pci_register_driver(&ath5k_pci_driver
);
373 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
383 pci_unregister_driver(&ath5k_pci_driver
);
385 ath5k_debug_finish();
388 module_init(init_ath5k_pci
);
389 module_exit(exit_ath5k_pci
);
392 /********************\
393 * PCI Initialization *
394 \********************/
397 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
399 const char *name
= "xxxxx";
402 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
403 if (srev_names
[i
].sr_type
!= type
)
406 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
407 name
= srev_names
[i
].sr_name
;
409 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
410 name
= srev_names
[i
].sr_name
;
419 ath5k_pci_probe(struct pci_dev
*pdev
,
420 const struct pci_device_id
*id
)
423 struct ath5k_softc
*sc
;
424 struct ieee80211_hw
*hw
;
428 ret
= pci_enable_device(pdev
);
430 dev_err(&pdev
->dev
, "can't enable device\n");
434 /* XXX 32-bit addressing only */
435 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
437 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
442 * Cache line size is used to size and align various
443 * structures used to communicate with the hardware.
445 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
448 * Linux 2.4.18 (at least) writes the cache line size
449 * register as a 16-bit wide register which is wrong.
450 * We must have this setup properly for rx buffer
451 * DMA to work so force a reasonable value here if it
454 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
455 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
458 * The default setting of latency timer yields poor results,
459 * set it to the value used by other systems. It may be worth
460 * tweaking this setting more.
462 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
464 /* Enable bus mastering */
465 pci_set_master(pdev
);
468 * Disable the RETRY_TIMEOUT register (0x41) to keep
469 * PCI Tx retries from interfering with C3 CPU state.
471 pci_write_config_byte(pdev
, 0x41, 0);
473 ret
= pci_request_region(pdev
, 0, "ath5k");
475 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
479 mem
= pci_iomap(pdev
, 0, 0);
481 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
487 * Allocate hw (mac80211 main struct)
488 * and hw->priv (driver private data)
490 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
492 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
497 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
499 /* Initialize driver private data */
500 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
501 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
502 IEEE80211_HW_SIGNAL_DBM
|
503 IEEE80211_HW_NOISE_DBM
;
505 hw
->wiphy
->interface_modes
=
506 BIT(NL80211_IFTYPE_STATION
) |
507 BIT(NL80211_IFTYPE_ADHOC
) |
508 BIT(NL80211_IFTYPE_MESH_POINT
);
510 hw
->extra_tx_headroom
= 2;
511 hw
->channel_change_time
= 5000;
516 ath5k_debug_init_device(sc
);
519 * Mark the device as detached to avoid processing
520 * interrupts until setup is complete.
522 __set_bit(ATH_STAT_INVALID
, sc
->status
);
524 sc
->iobase
= mem
; /* So we can unmap it on detach */
525 sc
->cachelsz
= csz
* sizeof(u32
); /* convert to bytes */
526 sc
->opmode
= NL80211_IFTYPE_STATION
;
527 mutex_init(&sc
->lock
);
528 spin_lock_init(&sc
->rxbuflock
);
529 spin_lock_init(&sc
->txbuflock
);
530 spin_lock_init(&sc
->block
);
532 /* Set private data */
533 pci_set_drvdata(pdev
, hw
);
535 /* Setup interrupt handler */
536 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
538 ATH5K_ERR(sc
, "request_irq failed\n");
542 /* Initialize device */
543 sc
->ah
= ath5k_hw_attach(sc
, id
->driver_data
);
544 if (IS_ERR(sc
->ah
)) {
545 ret
= PTR_ERR(sc
->ah
);
549 /* set up multi-rate retry capabilities */
550 if (sc
->ah
->ah_version
== AR5K_AR5212
) {
551 hw
->max_altrates
= 3;
552 hw
->max_altrate_tries
= 11;
555 /* Finish private driver data initialization */
556 ret
= ath5k_attach(pdev
, hw
);
560 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
561 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
563 sc
->ah
->ah_phy_revision
);
565 if (!sc
->ah
->ah_single_chip
) {
566 /* Single chip radio (!RF5111) */
567 if (sc
->ah
->ah_radio_5ghz_revision
&&
568 !sc
->ah
->ah_radio_2ghz_revision
) {
569 /* No 5GHz support -> report 2GHz radio */
570 if (!test_bit(AR5K_MODE_11A
,
571 sc
->ah
->ah_capabilities
.cap_mode
)) {
572 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
573 ath5k_chip_name(AR5K_VERSION_RAD
,
574 sc
->ah
->ah_radio_5ghz_revision
),
575 sc
->ah
->ah_radio_5ghz_revision
);
576 /* No 2GHz support (5110 and some
577 * 5Ghz only cards) -> report 5Ghz radio */
578 } else if (!test_bit(AR5K_MODE_11B
,
579 sc
->ah
->ah_capabilities
.cap_mode
)) {
580 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
581 ath5k_chip_name(AR5K_VERSION_RAD
,
582 sc
->ah
->ah_radio_5ghz_revision
),
583 sc
->ah
->ah_radio_5ghz_revision
);
584 /* Multiband radio */
586 ATH5K_INFO(sc
, "RF%s multiband radio found"
588 ath5k_chip_name(AR5K_VERSION_RAD
,
589 sc
->ah
->ah_radio_5ghz_revision
),
590 sc
->ah
->ah_radio_5ghz_revision
);
593 /* Multi chip radio (RF5111 - RF2111) ->
594 * report both 2GHz/5GHz radios */
595 else if (sc
->ah
->ah_radio_5ghz_revision
&&
596 sc
->ah
->ah_radio_2ghz_revision
){
597 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
598 ath5k_chip_name(AR5K_VERSION_RAD
,
599 sc
->ah
->ah_radio_5ghz_revision
),
600 sc
->ah
->ah_radio_5ghz_revision
);
601 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
602 ath5k_chip_name(AR5K_VERSION_RAD
,
603 sc
->ah
->ah_radio_2ghz_revision
),
604 sc
->ah
->ah_radio_2ghz_revision
);
609 /* ready to process interrupts */
610 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
614 ath5k_hw_detach(sc
->ah
);
616 free_irq(pdev
->irq
, sc
);
618 ieee80211_free_hw(hw
);
620 pci_iounmap(pdev
, mem
);
622 pci_release_region(pdev
, 0);
624 pci_disable_device(pdev
);
629 static void __devexit
630 ath5k_pci_remove(struct pci_dev
*pdev
)
632 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
633 struct ath5k_softc
*sc
= hw
->priv
;
635 ath5k_debug_finish_device(sc
);
636 ath5k_detach(pdev
, hw
);
637 ath5k_hw_detach(sc
->ah
);
638 free_irq(pdev
->irq
, sc
);
639 pci_iounmap(pdev
, sc
->iobase
);
640 pci_release_region(pdev
, 0);
641 pci_disable_device(pdev
);
642 ieee80211_free_hw(hw
);
647 ath5k_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
649 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
650 struct ath5k_softc
*sc
= hw
->priv
;
654 ath5k_stop_hw(sc
, true);
656 free_irq(pdev
->irq
, sc
);
657 pci_save_state(pdev
);
658 pci_disable_device(pdev
);
659 pci_set_power_state(pdev
, PCI_D3hot
);
665 ath5k_pci_resume(struct pci_dev
*pdev
)
667 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
668 struct ath5k_softc
*sc
= hw
->priv
;
671 pci_restore_state(pdev
);
673 err
= pci_enable_device(pdev
);
678 * Suspend/Resume resets the PCI configuration space, so we have to
679 * re-disable the RETRY_TIMEOUT register (0x41) to keep
680 * PCI Tx retries from interfering with C3 CPU state
682 pci_write_config_byte(pdev
, 0x41, 0);
684 err
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
686 ATH5K_ERR(sc
, "request_irq failed\n");
690 err
= ath5k_init(sc
, true);
693 ath5k_led_enable(sc
);
697 free_irq(pdev
->irq
, sc
);
699 pci_disable_device(pdev
);
702 #endif /* CONFIG_PM */
705 /***********************\
706 * Driver Initialization *
707 \***********************/
710 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
712 struct ath5k_softc
*sc
= hw
->priv
;
713 struct ath5k_hw
*ah
= sc
->ah
;
717 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
720 * Check if the MAC has multi-rate retry support.
721 * We do this by trying to setup a fake extended
722 * descriptor. MAC's that don't have support will
723 * return false w/o doing anything. MAC's that do
724 * support it will return true w/o doing anything.
726 ret
= ah
->ah_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
730 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
733 * Collect the channel list. The 802.11 layer
734 * is resposible for filtering this list based
735 * on settings like the phy mode and regulatory
736 * domain restrictions.
738 ret
= ath5k_setup_bands(hw
);
740 ATH5K_ERR(sc
, "can't get channels\n");
744 /* NB: setup here so ath5k_rate_update is happy */
745 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
746 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
748 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
751 * Allocate tx+rx descriptors and populate the lists.
753 ret
= ath5k_desc_alloc(sc
, pdev
);
755 ATH5K_ERR(sc
, "can't allocate descriptors\n");
760 * Allocate hardware transmit queues: one queue for
761 * beacon frames and one data queue for each QoS
762 * priority. Note that hw functions handle reseting
763 * these queues at the needed time.
765 ret
= ath5k_beaconq_setup(ah
);
767 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
772 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
773 if (IS_ERR(sc
->txq
)) {
774 ATH5K_ERR(sc
, "can't setup xmit queue\n");
775 ret
= PTR_ERR(sc
->txq
);
779 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
780 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
781 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
782 setup_timer(&sc
->calib_tim
, ath5k_calibrate
, (unsigned long)sc
);
784 ath5k_hw_get_lladdr(ah
, mac
);
785 SET_IEEE80211_PERM_ADDR(hw
, mac
);
786 /* All MAC address bits matter for ACKs */
787 memset(sc
->bssidmask
, 0xff, ETH_ALEN
);
788 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
790 ret
= ieee80211_register_hw(hw
);
792 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
800 ath5k_txq_release(sc
);
802 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
804 ath5k_desc_free(sc
, pdev
);
810 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
812 struct ath5k_softc
*sc
= hw
->priv
;
815 * NB: the order of these is important:
816 * o call the 802.11 layer before detaching ath5k_hw to
817 * insure callbacks into the driver to delete global
818 * key cache entries can be handled
819 * o reclaim the tx queue data structures after calling
820 * the 802.11 layer as we'll get called back to reclaim
821 * node state and potentially want to use them
822 * o to cleanup the tx queues the hal is called, so detach
824 * XXX: ??? detach ath5k_hw ???
825 * Other than that, it's straightforward...
827 ieee80211_unregister_hw(hw
);
828 ath5k_desc_free(sc
, pdev
);
829 ath5k_txq_release(sc
);
830 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
831 ath5k_unregister_leds(sc
);
834 * NB: can't reclaim these until after ieee80211_ifdetach
835 * returns because we'll get called back to reclaim node
836 * state and potentially want to use them.
843 /********************\
844 * Channel/mode setup *
845 \********************/
848 * Convert IEEE channel number to MHz frequency.
851 ath5k_ieee2mhz(short chan
)
853 if (chan
<= 14 || chan
>= 27)
854 return ieee80211chan2mhz(chan
);
856 return 2212 + chan
* 20;
860 ath5k_copy_channels(struct ath5k_hw
*ah
,
861 struct ieee80211_channel
*channels
,
865 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
867 if (!test_bit(mode
, ah
->ah_modes
))
872 case AR5K_MODE_11A_TURBO
:
873 /* 1..220, but 2GHz frequencies are filtered by check_channel */
875 chfreq
= CHANNEL_5GHZ
;
879 case AR5K_MODE_11G_TURBO
:
881 chfreq
= CHANNEL_2GHZ
;
884 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
888 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
890 freq
= ath5k_ieee2mhz(ch
);
892 /* Check if channel is supported by the chipset */
893 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
896 /* Write channel info and increment counter */
897 channels
[count
].center_freq
= freq
;
898 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
899 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
903 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
905 case AR5K_MODE_11A_TURBO
:
906 case AR5K_MODE_11G_TURBO
:
907 channels
[count
].hw_value
= chfreq
|
908 CHANNEL_OFDM
| CHANNEL_TURBO
;
911 channels
[count
].hw_value
= CHANNEL_B
;
922 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
926 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
927 sc
->rate_idx
[b
->band
][i
] = -1;
929 for (i
= 0; i
< b
->n_bitrates
; i
++) {
930 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
931 if (b
->bitrates
[i
].hw_value_short
)
932 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
937 ath5k_setup_bands(struct ieee80211_hw
*hw
)
939 struct ath5k_softc
*sc
= hw
->priv
;
940 struct ath5k_hw
*ah
= sc
->ah
;
941 struct ieee80211_supported_band
*sband
;
942 int max_c
, count_c
= 0;
945 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
946 max_c
= ARRAY_SIZE(sc
->channels
);
949 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
950 sband
->band
= IEEE80211_BAND_2GHZ
;
951 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
953 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
955 memcpy(sband
->bitrates
, &ath5k_rates
[0],
956 sizeof(struct ieee80211_rate
) * 12);
957 sband
->n_bitrates
= 12;
959 sband
->channels
= sc
->channels
;
960 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
961 AR5K_MODE_11G
, max_c
);
963 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
964 count_c
= sband
->n_channels
;
966 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
968 memcpy(sband
->bitrates
, &ath5k_rates
[0],
969 sizeof(struct ieee80211_rate
) * 4);
970 sband
->n_bitrates
= 4;
972 /* 5211 only supports B rates and uses 4bit rate codes
973 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
976 if (ah
->ah_version
== AR5K_AR5211
) {
977 for (i
= 0; i
< 4; i
++) {
978 sband
->bitrates
[i
].hw_value
=
979 sband
->bitrates
[i
].hw_value
& 0xF;
980 sband
->bitrates
[i
].hw_value_short
=
981 sband
->bitrates
[i
].hw_value_short
& 0xF;
985 sband
->channels
= sc
->channels
;
986 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
987 AR5K_MODE_11B
, max_c
);
989 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
990 count_c
= sband
->n_channels
;
993 ath5k_setup_rate_idx(sc
, sband
);
995 /* 5GHz band, A mode */
996 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
997 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
998 sband
->band
= IEEE80211_BAND_5GHZ
;
999 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
1001 memcpy(sband
->bitrates
, &ath5k_rates
[4],
1002 sizeof(struct ieee80211_rate
) * 8);
1003 sband
->n_bitrates
= 8;
1005 sband
->channels
= &sc
->channels
[count_c
];
1006 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1007 AR5K_MODE_11A
, max_c
);
1009 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
1011 ath5k_setup_rate_idx(sc
, sband
);
1013 ath5k_debug_dump_bands(sc
);
1019 * Set/change channels. If the channel is really being changed,
1020 * it's done by reseting the chip. To accomplish this we must
1021 * first cleanup any pending DMA, then restart stuff after a la
1025 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1027 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "(%u MHz) -> (%u MHz)\n",
1028 sc
->curchan
->center_freq
, chan
->center_freq
);
1030 if (chan
->center_freq
!= sc
->curchan
->center_freq
||
1031 chan
->hw_value
!= sc
->curchan
->hw_value
) {
1034 sc
->curband
= &sc
->sbands
[chan
->band
];
1037 * To switch channels clear any pending DMA operations;
1038 * wait long enough for the RX fifo to drain, reset the
1039 * hardware at the new frequency, and then re-enable
1040 * the relevant bits of the h/w.
1042 return ath5k_reset(sc
, true, true);
1049 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1053 if (mode
== AR5K_MODE_11A
) {
1054 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1056 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1061 ath5k_mode_setup(struct ath5k_softc
*sc
)
1063 struct ath5k_hw
*ah
= sc
->ah
;
1066 /* configure rx filter */
1067 rfilt
= sc
->filter_flags
;
1068 ath5k_hw_set_rx_filter(ah
, rfilt
);
1070 if (ath5k_hw_hasbssidmask(ah
))
1071 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1073 /* configure operational mode */
1074 ath5k_hw_set_opmode(ah
);
1076 ath5k_hw_set_mcast_filter(ah
, 0, 0);
1077 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1081 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
1083 WARN_ON(hw_rix
< 0 || hw_rix
> AR5K_MAX_RATES
);
1084 return sc
->rate_idx
[sc
->curband
->band
][hw_rix
];
1092 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1094 struct ath5k_hw
*ah
= sc
->ah
;
1095 struct sk_buff
*skb
= bf
->skb
;
1096 struct ath5k_desc
*ds
;
1098 if (likely(skb
== NULL
)) {
1102 * Allocate buffer with headroom_needed space for the
1103 * fake physical layer header at the start.
1105 skb
= dev_alloc_skb(sc
->rxbufsize
+ sc
->cachelsz
- 1);
1106 if (unlikely(skb
== NULL
)) {
1107 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1108 sc
->rxbufsize
+ sc
->cachelsz
- 1);
1112 * Cache-line-align. This is important (for the
1113 * 5210 at least) as not doing so causes bogus data
1116 off
= ((unsigned long)skb
->data
) % sc
->cachelsz
;
1118 skb_reserve(skb
, sc
->cachelsz
- off
);
1121 bf
->skbaddr
= pci_map_single(sc
->pdev
,
1122 skb
->data
, sc
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1123 if (unlikely(pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
))) {
1124 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1132 * Setup descriptors. For receive we always terminate
1133 * the descriptor list with a self-linked entry so we'll
1134 * not get overrun under high load (as can happen with a
1135 * 5212 when ANI processing enables PHY error frames).
1137 * To insure the last descriptor is self-linked we create
1138 * each descriptor as self-linked and add it to the end. As
1139 * each additional descriptor is added the previous self-linked
1140 * entry is ``fixed'' naturally. This should be safe even
1141 * if DMA is happening. When processing RX interrupts we
1142 * never remove/process the last, self-linked, entry on the
1143 * descriptor list. This insures the hardware always has
1144 * someplace to write a new frame.
1147 ds
->ds_link
= bf
->daddr
; /* link to self */
1148 ds
->ds_data
= bf
->skbaddr
;
1149 ah
->ah_setup_rx_desc(ah
, ds
,
1150 skb_tailroom(skb
), /* buffer size */
1153 if (sc
->rxlink
!= NULL
)
1154 *sc
->rxlink
= bf
->daddr
;
1155 sc
->rxlink
= &ds
->ds_link
;
1160 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1162 struct ath5k_hw
*ah
= sc
->ah
;
1163 struct ath5k_txq
*txq
= sc
->txq
;
1164 struct ath5k_desc
*ds
= bf
->desc
;
1165 struct sk_buff
*skb
= bf
->skb
;
1166 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1167 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1168 struct ieee80211_rate
*rate
;
1169 unsigned int mrr_rate
[3], mrr_tries
[3];
1172 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1174 /* XXX endianness */
1175 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1178 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1179 flags
|= AR5K_TXDESC_NOACK
;
1183 if (info
->control
.hw_key
) {
1184 keyidx
= info
->control
.hw_key
->hw_key_idx
;
1185 pktlen
+= info
->control
.hw_key
->icv_len
;
1187 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1188 ieee80211_get_hdrlen_from_skb(skb
), AR5K_PKT_TYPE_NORMAL
,
1189 (sc
->power_level
* 2),
1190 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1191 info
->control
.retry_limit
, keyidx
, 0, flags
, 0, 0);
1195 memset(mrr_rate
, 0, sizeof(mrr_rate
));
1196 memset(mrr_tries
, 0, sizeof(mrr_tries
));
1197 for (i
= 0; i
< 3; i
++) {
1198 rate
= ieee80211_get_alt_retry_rate(sc
->hw
, info
, i
);
1202 mrr_rate
[i
] = rate
->hw_value
;
1203 mrr_tries
[i
] = info
->control
.retries
[i
].limit
;
1206 ah
->ah_setup_mrr_tx_desc(ah
, ds
,
1207 mrr_rate
[0], mrr_tries
[0],
1208 mrr_rate
[1], mrr_tries
[1],
1209 mrr_rate
[2], mrr_tries
[2]);
1212 ds
->ds_data
= bf
->skbaddr
;
1214 spin_lock_bh(&txq
->lock
);
1215 list_add_tail(&bf
->list
, &txq
->q
);
1216 sc
->tx_stats
[txq
->qnum
].len
++;
1217 if (txq
->link
== NULL
) /* is this first packet? */
1218 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
1219 else /* no, so only link it */
1220 *txq
->link
= bf
->daddr
;
1222 txq
->link
= &ds
->ds_link
;
1223 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
1225 spin_unlock_bh(&txq
->lock
);
1229 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1233 /*******************\
1234 * Descriptors setup *
1235 \*******************/
1238 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1240 struct ath5k_desc
*ds
;
1241 struct ath5k_buf
*bf
;
1246 /* allocate descriptors */
1247 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1248 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1249 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1250 if (sc
->desc
== NULL
) {
1251 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1256 da
= sc
->desc_daddr
;
1257 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1258 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1260 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1261 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1263 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1269 INIT_LIST_HEAD(&sc
->rxbuf
);
1270 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1273 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1276 INIT_LIST_HEAD(&sc
->txbuf
);
1277 sc
->txbuf_len
= ATH_TXBUF
;
1278 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1279 da
+= sizeof(*ds
)) {
1282 list_add_tail(&bf
->list
, &sc
->txbuf
);
1292 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1299 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1301 struct ath5k_buf
*bf
;
1303 ath5k_txbuf_free(sc
, sc
->bbuf
);
1304 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1305 ath5k_txbuf_free(sc
, bf
);
1306 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1307 ath5k_txbuf_free(sc
, bf
);
1309 /* Free memory associated with all descriptors */
1310 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1324 static struct ath5k_txq
*
1325 ath5k_txq_setup(struct ath5k_softc
*sc
,
1326 int qtype
, int subtype
)
1328 struct ath5k_hw
*ah
= sc
->ah
;
1329 struct ath5k_txq
*txq
;
1330 struct ath5k_txq_info qi
= {
1331 .tqi_subtype
= subtype
,
1332 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1333 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1334 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1339 * Enable interrupts only for EOL and DESC conditions.
1340 * We mark tx descriptors to receive a DESC interrupt
1341 * when a tx queue gets deep; otherwise waiting for the
1342 * EOL to reap descriptors. Note that this is done to
1343 * reduce interrupt load and this only defers reaping
1344 * descriptors, never transmitting frames. Aside from
1345 * reducing interrupts this also permits more concurrency.
1346 * The only potential downside is if the tx queue backs
1347 * up in which case the top half of the kernel may backup
1348 * due to a lack of tx descriptors.
1350 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1351 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1352 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1355 * NB: don't print a message, this happens
1356 * normally on parts with too few tx queues
1358 return ERR_PTR(qnum
);
1360 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1361 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1362 qnum
, ARRAY_SIZE(sc
->txqs
));
1363 ath5k_hw_release_tx_queue(ah
, qnum
);
1364 return ERR_PTR(-EINVAL
);
1366 txq
= &sc
->txqs
[qnum
];
1370 INIT_LIST_HEAD(&txq
->q
);
1371 spin_lock_init(&txq
->lock
);
1374 return &sc
->txqs
[qnum
];
1378 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1380 struct ath5k_txq_info qi
= {
1381 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1382 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1383 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1384 /* NB: for dynamic turbo, don't enable any other interrupts */
1385 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1388 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1392 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1394 struct ath5k_hw
*ah
= sc
->ah
;
1395 struct ath5k_txq_info qi
;
1398 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1401 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1402 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1404 * Always burst out beacon and CAB traffic
1405 * (aifs = cwmin = cwmax = 0)
1410 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
1412 * Adhoc mode; backoff between 0 and (2 * cw_min).
1416 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1419 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1420 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1421 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1423 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1425 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1426 "hardware queue!\n", __func__
);
1430 return ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */;
1434 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1436 struct ath5k_buf
*bf
, *bf0
;
1439 * NB: this assumes output has been stopped and
1440 * we do not need to block ath5k_tx_tasklet
1442 spin_lock_bh(&txq
->lock
);
1443 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1444 ath5k_debug_printtxbuf(sc
, bf
);
1446 ath5k_txbuf_free(sc
, bf
);
1448 spin_lock_bh(&sc
->txbuflock
);
1449 sc
->tx_stats
[txq
->qnum
].len
--;
1450 list_move_tail(&bf
->list
, &sc
->txbuf
);
1452 spin_unlock_bh(&sc
->txbuflock
);
1455 spin_unlock_bh(&txq
->lock
);
1459 * Drain the transmit queues and reclaim resources.
1462 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1464 struct ath5k_hw
*ah
= sc
->ah
;
1467 /* XXX return value */
1468 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1469 /* don't touch the hardware if marked invalid */
1470 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1471 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1472 ath5k_hw_get_txdp(ah
, sc
->bhalq
));
1473 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1474 if (sc
->txqs
[i
].setup
) {
1475 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1476 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1479 ath5k_hw_get_txdp(ah
,
1484 ieee80211_wake_queues(sc
->hw
); /* XXX move to callers */
1486 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1487 if (sc
->txqs
[i
].setup
)
1488 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1492 ath5k_txq_release(struct ath5k_softc
*sc
)
1494 struct ath5k_txq
*txq
= sc
->txqs
;
1497 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1499 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1512 * Enable the receive h/w following a reset.
1515 ath5k_rx_start(struct ath5k_softc
*sc
)
1517 struct ath5k_hw
*ah
= sc
->ah
;
1518 struct ath5k_buf
*bf
;
1521 sc
->rxbufsize
= roundup(IEEE80211_MAX_LEN
, sc
->cachelsz
);
1523 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rxbufsize %u\n",
1524 sc
->cachelsz
, sc
->rxbufsize
);
1528 spin_lock_bh(&sc
->rxbuflock
);
1529 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1530 ret
= ath5k_rxbuf_setup(sc
, bf
);
1532 spin_unlock_bh(&sc
->rxbuflock
);
1536 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1537 spin_unlock_bh(&sc
->rxbuflock
);
1539 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1540 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1541 ath5k_mode_setup(sc
); /* set filters, etc. */
1542 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1550 * Disable the receive h/w in preparation for a reset.
1553 ath5k_rx_stop(struct ath5k_softc
*sc
)
1555 struct ath5k_hw
*ah
= sc
->ah
;
1557 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1558 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1559 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1561 ath5k_debug_printrxbuffs(sc
, ah
);
1563 sc
->rxlink
= NULL
; /* just in case */
1567 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1568 struct sk_buff
*skb
, struct ath5k_rx_status
*rs
)
1570 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1571 unsigned int keyix
, hlen
;
1573 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1574 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1575 return RX_FLAG_DECRYPTED
;
1577 /* Apparently when a default key is used to decrypt the packet
1578 the hw does not set the index used to decrypt. In such cases
1579 get the index from the packet. */
1580 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1581 if (ieee80211_has_protected(hdr
->frame_control
) &&
1582 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1583 skb
->len
>= hlen
+ 4) {
1584 keyix
= skb
->data
[hlen
+ 3] >> 6;
1586 if (test_bit(keyix
, sc
->keymap
))
1587 return RX_FLAG_DECRYPTED
;
1595 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1596 struct ieee80211_rx_status
*rxs
)
1600 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1602 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1603 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1604 memcmp(mgmt
->bssid
, sc
->ah
->ah_bssid
, ETH_ALEN
) == 0) {
1606 * Received an IBSS beacon with the same BSSID. Hardware *must*
1607 * have updated the local TSF. We have to work around various
1608 * hardware bugs, though...
1610 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1611 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1612 hw_tu
= TSF_TO_TU(tsf
);
1614 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1615 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1616 (unsigned long long)bc_tstamp
,
1617 (unsigned long long)rxs
->mactime
,
1618 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1619 (unsigned long long)tsf
);
1622 * Sometimes the HW will give us a wrong tstamp in the rx
1623 * status, causing the timestamp extension to go wrong.
1624 * (This seems to happen especially with beacon frames bigger
1625 * than 78 byte (incl. FCS))
1626 * But we know that the receive timestamp must be later than the
1627 * timestamp of the beacon since HW must have synced to that.
1629 * NOTE: here we assume mactime to be after the frame was
1630 * received, not like mac80211 which defines it at the start.
1632 if (bc_tstamp
> rxs
->mactime
) {
1633 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1634 "fixing mactime from %llx to %llx\n",
1635 (unsigned long long)rxs
->mactime
,
1636 (unsigned long long)tsf
);
1641 * Local TSF might have moved higher than our beacon timers,
1642 * in that case we have to update them to continue sending
1643 * beacons. This also takes care of synchronizing beacon sending
1644 * times with other stations.
1646 if (hw_tu
>= sc
->nexttbtt
)
1647 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1653 ath5k_tasklet_rx(unsigned long data
)
1655 struct ieee80211_rx_status rxs
= {};
1656 struct ath5k_rx_status rs
= {};
1657 struct sk_buff
*skb
;
1658 struct ath5k_softc
*sc
= (void *)data
;
1659 struct ath5k_buf
*bf
, *bf_last
;
1660 struct ath5k_desc
*ds
;
1665 spin_lock(&sc
->rxbuflock
);
1666 if (list_empty(&sc
->rxbuf
)) {
1667 ATH5K_WARN(sc
, "empty rx buf pool\n");
1670 bf_last
= list_entry(sc
->rxbuf
.prev
, struct ath5k_buf
, list
);
1674 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1675 BUG_ON(bf
->skb
== NULL
);
1680 * last buffer must not be freed to ensure proper hardware
1681 * function. When the hardware finishes also a packet next to
1682 * it, we are sure, it doesn't use it anymore and we can go on.
1687 struct ath5k_buf
*bf_next
= list_entry(bf
->list
.next
,
1688 struct ath5k_buf
, list
);
1689 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, bf_next
->desc
,
1694 /* skip the overwritten one (even status is martian) */
1698 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1699 if (unlikely(ret
== -EINPROGRESS
))
1701 else if (unlikely(ret
)) {
1702 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1703 spin_unlock(&sc
->rxbuflock
);
1707 if (unlikely(rs
.rs_more
)) {
1708 ATH5K_WARN(sc
, "unsupported jumbo\n");
1712 if (unlikely(rs
.rs_status
)) {
1713 if (rs
.rs_status
& AR5K_RXERR_PHY
)
1715 if (rs
.rs_status
& AR5K_RXERR_DECRYPT
) {
1717 * Decrypt error. If the error occurred
1718 * because there was no hardware key, then
1719 * let the frame through so the upper layers
1720 * can process it. This is necessary for 5210
1721 * parts which have no way to setup a ``clear''
1724 * XXX do key cache faulting
1726 if (rs
.rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1727 !(rs
.rs_status
& AR5K_RXERR_CRC
))
1730 if (rs
.rs_status
& AR5K_RXERR_MIC
) {
1731 rxs
.flag
|= RX_FLAG_MMIC_ERROR
;
1735 /* let crypto-error packets fall through in MNTR */
1737 ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1738 sc
->opmode
!= NL80211_IFTYPE_MONITOR
)
1742 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
1743 PCI_DMA_FROMDEVICE
);
1746 skb_put(skb
, rs
.rs_datalen
);
1749 * the hardware adds a padding to 4 byte boundaries between
1750 * the header and the payload data if the header length is
1751 * not multiples of 4 - remove it
1753 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1756 memmove(skb
->data
+ pad
, skb
->data
, hdrlen
);
1761 * always extend the mac timestamp, since this information is
1762 * also needed for proper IBSS merging.
1764 * XXX: it might be too late to do it here, since rs_tstamp is
1765 * 15bit only. that means TSF extension has to be done within
1766 * 32768usec (about 32ms). it might be necessary to move this to
1767 * the interrupt handler, like it is done in madwifi.
1769 * Unfortunately we don't know when the hardware takes the rx
1770 * timestamp (beginning of phy frame, data frame, end of rx?).
1771 * The only thing we know is that it is hardware specific...
1772 * On AR5213 it seems the rx timestamp is at the end of the
1773 * frame, but i'm not sure.
1775 * NOTE: mac80211 defines mactime at the beginning of the first
1776 * data symbol. Since we don't have any time references it's
1777 * impossible to comply to that. This affects IBSS merge only
1778 * right now, so it's not too bad...
1780 rxs
.mactime
= ath5k_extend_tsf(sc
->ah
, rs
.rs_tstamp
);
1781 rxs
.flag
|= RX_FLAG_TSFT
;
1783 rxs
.freq
= sc
->curchan
->center_freq
;
1784 rxs
.band
= sc
->curband
->band
;
1786 rxs
.noise
= sc
->ah
->ah_noise_floor
;
1787 rxs
.signal
= rxs
.noise
+ rs
.rs_rssi
;
1788 rxs
.qual
= rs
.rs_rssi
* 100 / 64;
1790 rxs
.antenna
= rs
.rs_antenna
;
1791 rxs
.rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
.rs_rate
);
1792 rxs
.flag
|= ath5k_rx_decrypted(sc
, ds
, skb
, &rs
);
1794 if (rxs
.rate_idx
>= 0 && rs
.rs_rate
==
1795 sc
->curband
->bitrates
[rxs
.rate_idx
].hw_value_short
)
1796 rxs
.flag
|= RX_FLAG_SHORTPRE
;
1798 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1800 /* check beacons in IBSS mode */
1801 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1802 ath5k_check_ibss_tsf(sc
, skb
, &rxs
);
1804 __ieee80211_rx(sc
->hw
, skb
, &rxs
);
1806 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1807 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1809 spin_unlock(&sc
->rxbuflock
);
1820 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1822 struct ath5k_tx_status ts
= {};
1823 struct ath5k_buf
*bf
, *bf0
;
1824 struct ath5k_desc
*ds
;
1825 struct sk_buff
*skb
;
1826 struct ieee80211_tx_info
*info
;
1829 spin_lock(&txq
->lock
);
1830 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1833 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1834 if (unlikely(ret
== -EINPROGRESS
))
1836 else if (unlikely(ret
)) {
1837 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
1843 info
= IEEE80211_SKB_CB(skb
);
1846 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1849 memset(&info
->status
, 0, sizeof(info
->status
));
1850 info
->tx_rate_idx
= ath5k_hw_to_driver_rix(sc
,
1851 ts
.ts_rate
[ts
.ts_final_idx
]);
1852 info
->status
.retry_count
= ts
.ts_longretry
;
1854 for (i
= 0; i
< 4; i
++) {
1855 struct ieee80211_tx_altrate
*r
=
1856 &info
->status
.retries
[i
];
1858 if (ts
.ts_rate
[i
]) {
1859 r
->rate_idx
= ath5k_hw_to_driver_rix(sc
, ts
.ts_rate
[i
]);
1860 r
->limit
= ts
.ts_retry
[i
];
1867 info
->status
.excessive_retries
= 0;
1868 if (unlikely(ts
.ts_status
)) {
1869 sc
->ll_stats
.dot11ACKFailureCount
++;
1870 if (ts
.ts_status
& AR5K_TXERR_XRETRY
)
1871 info
->status
.excessive_retries
= 1;
1872 else if (ts
.ts_status
& AR5K_TXERR_FILT
)
1873 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1875 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1876 info
->status
.ack_signal
= ts
.ts_rssi
;
1879 ieee80211_tx_status(sc
->hw
, skb
);
1880 sc
->tx_stats
[txq
->qnum
].count
++;
1882 spin_lock(&sc
->txbuflock
);
1883 sc
->tx_stats
[txq
->qnum
].len
--;
1884 list_move_tail(&bf
->list
, &sc
->txbuf
);
1886 spin_unlock(&sc
->txbuflock
);
1888 if (likely(list_empty(&txq
->q
)))
1890 spin_unlock(&txq
->lock
);
1891 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
1892 ieee80211_wake_queues(sc
->hw
);
1896 ath5k_tasklet_tx(unsigned long data
)
1898 struct ath5k_softc
*sc
= (void *)data
;
1900 ath5k_tx_processq(sc
, sc
->txq
);
1909 * Setup the beacon frame for transmit.
1912 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1914 struct sk_buff
*skb
= bf
->skb
;
1915 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1916 struct ath5k_hw
*ah
= sc
->ah
;
1917 struct ath5k_desc
*ds
;
1918 int ret
, antenna
= 0;
1921 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1923 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1924 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1925 (unsigned long long)bf
->skbaddr
);
1926 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
1927 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
1933 flags
= AR5K_TXDESC_NOACK
;
1934 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1935 ds
->ds_link
= bf
->daddr
; /* self-linked */
1936 flags
|= AR5K_TXDESC_VEOL
;
1938 * Let hardware handle antenna switching if txantenna is not set
1943 * Switch antenna every 4 beacons if txantenna is not set
1944 * XXX assumes two antennas
1947 antenna
= sc
->bsent
& 4 ? 2 : 1;
1950 ds
->ds_data
= bf
->skbaddr
;
1951 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1952 ieee80211_get_hdrlen_from_skb(skb
),
1953 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
1954 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1955 1, AR5K_TXKEYIX_INVALID
,
1956 antenna
, flags
, 0, 0);
1962 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1967 * Transmit a beacon frame at SWBA. Dynamic updates to the
1968 * frame contents are done as needed and the slot time is
1969 * also adjusted based on current state.
1971 * this is usually called from interrupt context (ath5k_intr())
1972 * but also from ath5k_beacon_config() in IBSS mode which in turn
1973 * can be called from a tasklet and user context
1976 ath5k_beacon_send(struct ath5k_softc
*sc
)
1978 struct ath5k_buf
*bf
= sc
->bbuf
;
1979 struct ath5k_hw
*ah
= sc
->ah
;
1981 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1983 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
1984 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
1985 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
1989 * Check if the previous beacon has gone out. If
1990 * not don't don't try to post another, skip this
1991 * period and wait for the next. Missed beacons
1992 * indicate a problem and should not occur. If we
1993 * miss too many consecutive beacons reset the device.
1995 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
1997 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1998 "missed %u consecutive beacons\n", sc
->bmisscount
);
1999 if (sc
->bmisscount
> 3) { /* NB: 3 is a guess */
2000 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2001 "stuck beacon time (%u missed)\n",
2003 tasklet_schedule(&sc
->restq
);
2007 if (unlikely(sc
->bmisscount
!= 0)) {
2008 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2009 "resume beacon xmit after %u misses\n",
2015 * Stop any current dma and put the new frame on the queue.
2016 * This should never fail since we check above that no frames
2017 * are still pending on the queue.
2019 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
2020 ATH5K_WARN(sc
, "beacon queue %u didn't stop?\n", sc
->bhalq
);
2021 /* NB: hw still stops DMA, so proceed */
2024 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
2025 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
2026 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2027 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2034 * ath5k_beacon_update_timers - update beacon timers
2036 * @sc: struct ath5k_softc pointer we are operating on
2037 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2038 * beacon timer update based on the current HW TSF.
2040 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2041 * of a received beacon or the current local hardware TSF and write it to the
2042 * beacon timer registers.
2044 * This is called in a variety of situations, e.g. when a beacon is received,
2045 * when a TSF update has been detected, but also when an new IBSS is created or
2046 * when we otherwise know we have to update the timers, but we keep it in this
2047 * function to have it all together in one place.
2050 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2052 struct ath5k_hw
*ah
= sc
->ah
;
2053 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2056 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2057 if (WARN_ON(!intval
))
2060 /* beacon TSF converted to TU */
2061 bc_tu
= TSF_TO_TU(bc_tsf
);
2063 /* current TSF converted to TU */
2064 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2065 hw_tu
= TSF_TO_TU(hw_tsf
);
2068 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2071 * no beacons received, called internally.
2072 * just need to refresh timers based on HW TSF.
2074 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2075 } else if (bc_tsf
== 0) {
2077 * no beacon received, probably called by ath5k_reset_tsf().
2078 * reset TSF to start with 0.
2081 intval
|= AR5K_BEACON_RESET_TSF
;
2082 } else if (bc_tsf
> hw_tsf
) {
2084 * beacon received, SW merge happend but HW TSF not yet updated.
2085 * not possible to reconfigure timers yet, but next time we
2086 * receive a beacon with the same BSSID, the hardware will
2087 * automatically update the TSF and then we need to reconfigure
2090 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2091 "need to wait for HW TSF sync\n");
2095 * most important case for beacon synchronization between STA.
2097 * beacon received and HW TSF has been already updated by HW.
2098 * update next TBTT based on the TSF of the beacon, but make
2099 * sure it is ahead of our local TSF timer.
2101 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2105 sc
->nexttbtt
= nexttbtt
;
2107 intval
|= AR5K_BEACON_ENA
;
2108 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2111 * debugging output last in order to preserve the time critical aspect
2115 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2116 "reconfigured timers based on HW TSF\n");
2117 else if (bc_tsf
== 0)
2118 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2119 "reset HW TSF and timers\n");
2121 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2122 "updated timers based on beacon TSF\n");
2124 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2125 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2126 (unsigned long long) bc_tsf
,
2127 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2128 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2129 intval
& AR5K_BEACON_PERIOD
,
2130 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2131 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2136 * ath5k_beacon_config - Configure the beacon queues and interrupts
2138 * @sc: struct ath5k_softc pointer we are operating on
2140 * When operating in station mode we want to receive a BMISS interrupt when we
2141 * stop seeing beacons from the AP we've associated with so we can look for
2142 * another AP to associate with.
2144 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2145 * interrupts to detect TSF updates only.
2147 * AP mode is missing.
2150 ath5k_beacon_config(struct ath5k_softc
*sc
)
2152 struct ath5k_hw
*ah
= sc
->ah
;
2154 ath5k_hw_set_imr(ah
, 0);
2156 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2158 if (sc
->opmode
== NL80211_IFTYPE_STATION
) {
2159 sc
->imask
|= AR5K_INT_BMISS
;
2160 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2162 * In IBSS mode we use a self-linked tx descriptor and let the
2163 * hardware send the beacons automatically. We have to load it
2165 * We use the SWBA interrupt only to keep track of the beacon
2166 * timers in order to detect automatic TSF updates.
2168 ath5k_beaconq_config(sc
);
2170 sc
->imask
|= AR5K_INT_SWBA
;
2172 if (ath5k_hw_hasveol(ah
)) {
2173 spin_lock(&sc
->block
);
2174 ath5k_beacon_send(sc
);
2175 spin_unlock(&sc
->block
);
2180 ath5k_hw_set_imr(ah
, sc
->imask
);
2184 /********************\
2185 * Interrupt handling *
2186 \********************/
2189 ath5k_init(struct ath5k_softc
*sc
, bool is_resume
)
2191 struct ath5k_hw
*ah
= sc
->ah
;
2194 mutex_lock(&sc
->lock
);
2196 if (is_resume
&& !test_bit(ATH_STAT_STARTED
, sc
->status
))
2199 __clear_bit(ATH_STAT_STARTED
, sc
->status
);
2201 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2204 * Stop anything previously setup. This is safe
2205 * no matter this is the first time through or not.
2207 ath5k_stop_locked(sc
);
2210 * The basic interface to setting the hardware in a good
2211 * state is ``reset''. On return the hardware is known to
2212 * be powered up and with interrupts disabled. This must
2213 * be followed by initialization of the appropriate bits
2214 * and then setup of the interrupt mask.
2216 sc
->curchan
= sc
->hw
->conf
.channel
;
2217 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2218 sc
->imask
= AR5K_INT_RX
| AR5K_INT_TX
| AR5K_INT_RXEOL
|
2219 AR5K_INT_RXORN
| AR5K_INT_FATAL
| AR5K_INT_GLOBAL
|
2221 ret
= ath5k_reset(sc
, false, false);
2226 * Reset the key cache since some parts do not reset the
2227 * contents on initial power up or resume from suspend.
2229 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
2230 ath5k_hw_reset_key(ah
, i
);
2232 __set_bit(ATH_STAT_STARTED
, sc
->status
);
2234 /* Set ack to be sent at low bit-rates */
2235 ath5k_hw_set_ack_bitrate_high(ah
, false);
2237 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2238 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2244 mutex_unlock(&sc
->lock
);
2249 ath5k_stop_locked(struct ath5k_softc
*sc
)
2251 struct ath5k_hw
*ah
= sc
->ah
;
2253 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2254 test_bit(ATH_STAT_INVALID
, sc
->status
));
2257 * Shutdown the hardware and driver:
2258 * stop output from above
2259 * disable interrupts
2261 * turn off the radio
2262 * clear transmit machinery
2263 * clear receive machinery
2264 * drain and release tx queues
2265 * reclaim beacon resources
2266 * power down hardware
2268 * Note that some of this work is not possible if the
2269 * hardware is gone (invalid).
2271 ieee80211_stop_queues(sc
->hw
);
2273 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2275 ath5k_hw_set_imr(ah
, 0);
2276 synchronize_irq(sc
->pdev
->irq
);
2278 ath5k_txq_cleanup(sc
);
2279 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2281 ath5k_hw_phy_disable(ah
);
2289 * Stop the device, grabbing the top-level lock to protect
2290 * against concurrent entry through ath5k_init (which can happen
2291 * if another thread does a system call and the thread doing the
2292 * stop is preempted).
2295 ath5k_stop_hw(struct ath5k_softc
*sc
, bool is_suspend
)
2299 mutex_lock(&sc
->lock
);
2300 ret
= ath5k_stop_locked(sc
);
2301 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2303 * Set the chip in full sleep mode. Note that we are
2304 * careful to do this only when bringing the interface
2305 * completely to a stop. When the chip is in this state
2306 * it must be carefully woken up or references to
2307 * registers in the PCI clock domain may freeze the bus
2308 * (and system). This varies by chip and is mostly an
2309 * issue with newer parts that go to sleep more quickly.
2311 if (sc
->ah
->ah_mac_srev
>= 0x78) {
2314 * don't put newer MAC revisions > 7.8 to sleep because
2315 * of the above mentioned problems
2317 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mac version > 7.8, "
2318 "not putting device to sleep\n");
2320 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2321 "putting device to full sleep\n");
2322 ath5k_hw_set_power(sc
->ah
, AR5K_PM_FULL_SLEEP
, true, 0);
2325 ath5k_txbuf_free(sc
, sc
->bbuf
);
2327 __clear_bit(ATH_STAT_STARTED
, sc
->status
);
2330 mutex_unlock(&sc
->lock
);
2332 del_timer_sync(&sc
->calib_tim
);
2333 tasklet_kill(&sc
->rxtq
);
2334 tasklet_kill(&sc
->txtq
);
2335 tasklet_kill(&sc
->restq
);
2341 ath5k_intr(int irq
, void *dev_id
)
2343 struct ath5k_softc
*sc
= dev_id
;
2344 struct ath5k_hw
*ah
= sc
->ah
;
2345 enum ath5k_int status
;
2346 unsigned int counter
= 1000;
2348 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2349 !ath5k_hw_is_intr_pending(ah
)))
2354 * Figure out the reason(s) for the interrupt. Note
2355 * that get_isr returns a pseudo-ISR that may include
2356 * bits we haven't explicitly enabled so we mask the
2357 * value to insure we only process bits we requested.
2359 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2360 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2362 status
&= sc
->imask
; /* discard unasked for bits */
2363 if (unlikely(status
& AR5K_INT_FATAL
)) {
2365 * Fatal errors are unrecoverable.
2366 * Typically these are caused by DMA errors.
2368 tasklet_schedule(&sc
->restq
);
2369 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2370 tasklet_schedule(&sc
->restq
);
2372 if (status
& AR5K_INT_SWBA
) {
2374 * Software beacon alert--time to send a beacon.
2375 * Handle beacon transmission directly; deferring
2376 * this is too slow to meet timing constraints
2379 * In IBSS mode we use this interrupt just to
2380 * keep track of the next TBTT (target beacon
2381 * transmission time) in order to detect wether
2382 * automatic TSF updates happened.
2384 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2385 /* XXX: only if VEOL suppported */
2386 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2387 sc
->nexttbtt
+= sc
->bintval
;
2388 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2389 "SWBA nexttbtt: %x hw_tu: %x "
2393 (unsigned long long) tsf
);
2395 spin_lock(&sc
->block
);
2396 ath5k_beacon_send(sc
);
2397 spin_unlock(&sc
->block
);
2400 if (status
& AR5K_INT_RXEOL
) {
2402 * NB: the hardware should re-read the link when
2403 * RXE bit is written, but it doesn't work at
2404 * least on older hardware revs.
2408 if (status
& AR5K_INT_TXURN
) {
2409 /* bump tx trigger level */
2410 ath5k_hw_update_tx_triglevel(ah
, true);
2412 if (status
& AR5K_INT_RX
)
2413 tasklet_schedule(&sc
->rxtq
);
2414 if (status
& AR5K_INT_TX
)
2415 tasklet_schedule(&sc
->txtq
);
2416 if (status
& AR5K_INT_BMISS
) {
2418 if (status
& AR5K_INT_MIB
) {
2420 * These stats are also used for ANI i think
2421 * so how about updating them more often ?
2423 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2426 } while (ath5k_hw_is_intr_pending(ah
) && counter
-- > 0);
2428 if (unlikely(!counter
))
2429 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2435 ath5k_tasklet_reset(unsigned long data
)
2437 struct ath5k_softc
*sc
= (void *)data
;
2439 ath5k_reset_wake(sc
);
2443 * Periodically recalibrate the PHY to account
2444 * for temperature/environment changes.
2447 ath5k_calibrate(unsigned long data
)
2449 struct ath5k_softc
*sc
= (void *)data
;
2450 struct ath5k_hw
*ah
= sc
->ah
;
2452 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2453 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2454 sc
->curchan
->hw_value
);
2456 if (ath5k_hw_get_rf_gain(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2458 * Rfgain is out of bounds, reset the chip
2459 * to load new gain values.
2461 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2462 ath5k_reset_wake(sc
);
2464 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2465 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2466 ieee80211_frequency_to_channel(
2467 sc
->curchan
->center_freq
));
2469 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2470 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2480 ath5k_led_enable(struct ath5k_softc
*sc
)
2482 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
2483 ath5k_hw_set_gpio_output(sc
->ah
, sc
->led_pin
);
2489 ath5k_led_on(struct ath5k_softc
*sc
)
2491 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2493 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, sc
->led_on
);
2497 ath5k_led_off(struct ath5k_softc
*sc
)
2499 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2501 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, !sc
->led_on
);
2505 ath5k_led_brightness_set(struct led_classdev
*led_dev
,
2506 enum led_brightness brightness
)
2508 struct ath5k_led
*led
= container_of(led_dev
, struct ath5k_led
,
2511 if (brightness
== LED_OFF
)
2512 ath5k_led_off(led
->sc
);
2514 ath5k_led_on(led
->sc
);
2518 ath5k_register_led(struct ath5k_softc
*sc
, struct ath5k_led
*led
,
2519 const char *name
, char *trigger
)
2524 strncpy(led
->name
, name
, sizeof(led
->name
));
2525 led
->led_dev
.name
= led
->name
;
2526 led
->led_dev
.default_trigger
= trigger
;
2527 led
->led_dev
.brightness_set
= ath5k_led_brightness_set
;
2529 err
= led_classdev_register(&sc
->pdev
->dev
, &led
->led_dev
);
2532 ATH5K_WARN(sc
, "could not register LED %s\n", name
);
2539 ath5k_unregister_led(struct ath5k_led
*led
)
2543 led_classdev_unregister(&led
->led_dev
);
2544 ath5k_led_off(led
->sc
);
2549 ath5k_unregister_leds(struct ath5k_softc
*sc
)
2551 ath5k_unregister_led(&sc
->rx_led
);
2552 ath5k_unregister_led(&sc
->tx_led
);
2557 ath5k_init_leds(struct ath5k_softc
*sc
)
2560 struct ieee80211_hw
*hw
= sc
->hw
;
2561 struct pci_dev
*pdev
= sc
->pdev
;
2562 char name
[ATH5K_LED_MAX_NAME_LEN
+ 1];
2565 * Auto-enable soft led processing for IBM cards and for
2566 * 5211 minipci cards.
2568 if (pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5212_IBM
||
2569 pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5211
) {
2570 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2572 sc
->led_on
= 0; /* active low */
2574 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2575 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
) {
2576 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2578 sc
->led_on
= 1; /* active high */
2580 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2583 ath5k_led_enable(sc
);
2585 snprintf(name
, sizeof(name
), "ath5k-%s::rx", wiphy_name(hw
->wiphy
));
2586 ret
= ath5k_register_led(sc
, &sc
->rx_led
, name
,
2587 ieee80211_get_rx_led_name(hw
));
2591 snprintf(name
, sizeof(name
), "ath5k-%s::tx", wiphy_name(hw
->wiphy
));
2592 ret
= ath5k_register_led(sc
, &sc
->tx_led
, name
,
2593 ieee80211_get_tx_led_name(hw
));
2599 /********************\
2600 * Mac80211 functions *
2601 \********************/
2604 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2606 struct ath5k_softc
*sc
= hw
->priv
;
2607 struct ath5k_buf
*bf
;
2608 unsigned long flags
;
2612 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2614 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2615 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2618 * the hardware expects the header padded to 4 byte boundaries
2619 * if this is not the case we add the padding after the header
2621 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2624 if (skb_headroom(skb
) < pad
) {
2625 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2626 " headroom to pad %d\n", hdrlen
, pad
);
2630 memmove(skb
->data
, skb
->data
+pad
, hdrlen
);
2633 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2634 if (list_empty(&sc
->txbuf
)) {
2635 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2636 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2637 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
2640 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2641 list_del(&bf
->list
);
2643 if (list_empty(&sc
->txbuf
))
2644 ieee80211_stop_queues(hw
);
2645 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2649 if (ath5k_txbuf_setup(sc
, bf
)) {
2651 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2652 list_add_tail(&bf
->list
, &sc
->txbuf
);
2654 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2655 dev_kfree_skb_any(skb
);
2663 ath5k_reset(struct ath5k_softc
*sc
, bool stop
, bool change_channel
)
2665 struct ath5k_hw
*ah
= sc
->ah
;
2668 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2671 ath5k_hw_set_imr(ah
, 0);
2672 ath5k_txq_cleanup(sc
);
2675 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
2677 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2682 * This is needed only to setup initial state
2683 * but it's best done after a reset.
2685 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2687 ret
= ath5k_rx_start(sc
);
2689 ATH5K_ERR(sc
, "can't start recv logic\n");
2694 * Change channels and update the h/w rate map if we're switching;
2695 * e.g. 11a to 11b/g.
2697 * We may be doing a reset in response to an ioctl that changes the
2698 * channel so update any state that might change as a result.
2702 /* ath5k_chan_change(sc, c); */
2704 ath5k_beacon_config(sc
);
2705 /* intrs are enabled by ath5k_beacon_config */
2713 ath5k_reset_wake(struct ath5k_softc
*sc
)
2717 ret
= ath5k_reset(sc
, true, true);
2719 ieee80211_wake_queues(sc
->hw
);
2724 static int ath5k_start(struct ieee80211_hw
*hw
)
2726 return ath5k_init(hw
->priv
, false);
2729 static void ath5k_stop(struct ieee80211_hw
*hw
)
2731 ath5k_stop_hw(hw
->priv
, false);
2734 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2735 struct ieee80211_if_init_conf
*conf
)
2737 struct ath5k_softc
*sc
= hw
->priv
;
2740 mutex_lock(&sc
->lock
);
2746 sc
->vif
= conf
->vif
;
2748 switch (conf
->type
) {
2749 case NL80211_IFTYPE_STATION
:
2750 case NL80211_IFTYPE_ADHOC
:
2751 case NL80211_IFTYPE_MONITOR
:
2752 sc
->opmode
= conf
->type
;
2759 /* Set to a reasonable value. Note that this will
2760 * be set to mac80211's value at ath5k_config(). */
2765 mutex_unlock(&sc
->lock
);
2770 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2771 struct ieee80211_if_init_conf
*conf
)
2773 struct ath5k_softc
*sc
= hw
->priv
;
2775 mutex_lock(&sc
->lock
);
2776 if (sc
->vif
!= conf
->vif
)
2781 mutex_unlock(&sc
->lock
);
2785 * TODO: Phy disable/diversity etc
2788 ath5k_config(struct ieee80211_hw
*hw
,
2789 struct ieee80211_conf
*conf
)
2791 struct ath5k_softc
*sc
= hw
->priv
;
2793 sc
->bintval
= conf
->beacon_int
;
2794 sc
->power_level
= conf
->power_level
;
2796 return ath5k_chan_set(sc
, conf
->channel
);
2800 ath5k_config_interface(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2801 struct ieee80211_if_conf
*conf
)
2803 struct ath5k_softc
*sc
= hw
->priv
;
2804 struct ath5k_hw
*ah
= sc
->ah
;
2807 mutex_lock(&sc
->lock
);
2808 if (sc
->vif
!= vif
) {
2813 /* Cache for later use during resets */
2814 memcpy(ah
->ah_bssid
, conf
->bssid
, ETH_ALEN
);
2815 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2816 * a clean way of letting us retrieve this yet. */
2817 ath5k_hw_set_associd(ah
, ah
->ah_bssid
, 0);
2821 if (conf
->changed
& IEEE80211_IFCC_BEACON
&&
2822 vif
->type
== NL80211_IFTYPE_ADHOC
) {
2823 struct sk_buff
*beacon
= ieee80211_beacon_get(hw
, vif
);
2828 /* call old handler for now */
2829 ath5k_beacon_update(hw
, beacon
);
2832 mutex_unlock(&sc
->lock
);
2834 return ath5k_reset_wake(sc
);
2836 mutex_unlock(&sc
->lock
);
2840 #define SUPPORTED_FIF_FLAGS \
2841 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2842 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2843 FIF_BCN_PRBRESP_PROMISC
2845 * o always accept unicast, broadcast, and multicast traffic
2846 * o multicast traffic for all BSSIDs will be enabled if mac80211
2848 * o maintain current state of phy ofdm or phy cck error reception.
2849 * If the hardware detects any of these type of errors then
2850 * ath5k_hw_get_rx_filter() will pass to us the respective
2851 * hardware filters to be able to receive these type of frames.
2852 * o probe request frames are accepted only when operating in
2853 * hostap, adhoc, or monitor modes
2854 * o enable promiscuous mode according to the interface state
2856 * - when operating in adhoc mode so the 802.11 layer creates
2857 * node table entries for peers,
2858 * - when operating in station mode for collecting rssi data when
2859 * the station is otherwise quiet, or
2862 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2863 unsigned int changed_flags
,
2864 unsigned int *new_flags
,
2865 int mc_count
, struct dev_mc_list
*mclist
)
2867 struct ath5k_softc
*sc
= hw
->priv
;
2868 struct ath5k_hw
*ah
= sc
->ah
;
2869 u32 mfilt
[2], val
, rfilt
;
2876 /* Only deal with supported flags */
2877 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2878 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2880 /* If HW detects any phy or radar errors, leave those filters on.
2881 * Also, always enable Unicast, Broadcasts and Multicast
2882 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2883 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2884 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2885 AR5K_RX_FILTER_MCAST
);
2887 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2888 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2889 rfilt
|= AR5K_RX_FILTER_PROM
;
2890 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2893 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
2896 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2897 if (*new_flags
& FIF_ALLMULTI
) {
2901 for (i
= 0; i
< mc_count
; i
++) {
2904 /* calculate XOR of eight 6-bit values */
2905 val
= get_unaligned_le32(mclist
->dmi_addr
+ 0);
2906 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2907 val
= get_unaligned_le32(mclist
->dmi_addr
+ 3);
2908 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2910 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2911 /* XXX: we might be able to just do this instead,
2912 * but not sure, needs testing, if we do use this we'd
2913 * neet to inform below to not reset the mcast */
2914 /* ath5k_hw_set_mcast_filterindex(ah,
2915 * mclist->dmi_addr[5]); */
2916 mclist
= mclist
->next
;
2920 /* This is the best we can do */
2921 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
2922 rfilt
|= AR5K_RX_FILTER_PHYERR
;
2924 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2925 * and probes for any BSSID, this needs testing */
2926 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
2927 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
2929 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2930 * set we should only pass on control frames for this
2931 * station. This needs testing. I believe right now this
2932 * enables *all* control frames, which is OK.. but
2933 * but we should see if we can improve on granularity */
2934 if (*new_flags
& FIF_CONTROL
)
2935 rfilt
|= AR5K_RX_FILTER_CONTROL
;
2937 /* Additional settings per mode -- this is per ath5k */
2939 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2941 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2942 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2943 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2944 if (sc
->opmode
!= NL80211_IFTYPE_STATION
)
2945 rfilt
|= AR5K_RX_FILTER_PROBEREQ
;
2946 if (sc
->opmode
!= NL80211_IFTYPE_AP
&&
2947 sc
->opmode
!= NL80211_IFTYPE_MESH_POINT
&&
2948 test_bit(ATH_STAT_PROMISC
, sc
->status
))
2949 rfilt
|= AR5K_RX_FILTER_PROM
;
2950 if ((sc
->opmode
== NL80211_IFTYPE_STATION
&& sc
->assoc
) ||
2951 sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2952 rfilt
|= AR5K_RX_FILTER_BEACON
;
2956 ath5k_hw_set_rx_filter(ah
,rfilt
);
2958 /* Set multicast bits */
2959 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
2960 /* Set the cached hw filter flags, this will alter actually
2962 sc
->filter_flags
= rfilt
;
2966 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
2967 const u8
*local_addr
, const u8
*addr
,
2968 struct ieee80211_key_conf
*key
)
2970 struct ath5k_softc
*sc
= hw
->priv
;
2975 /* XXX: fix hardware encryption, its not working. For now
2976 * allow software encryption */
2986 mutex_lock(&sc
->lock
);
2990 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
, addr
);
2992 ATH5K_ERR(sc
, "can't set the key\n");
2995 __set_bit(key
->keyidx
, sc
->keymap
);
2996 key
->hw_key_idx
= key
->keyidx
;
2999 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
3000 __clear_bit(key
->keyidx
, sc
->keymap
);
3009 mutex_unlock(&sc
->lock
);
3014 ath5k_get_stats(struct ieee80211_hw
*hw
,
3015 struct ieee80211_low_level_stats
*stats
)
3017 struct ath5k_softc
*sc
= hw
->priv
;
3018 struct ath5k_hw
*ah
= sc
->ah
;
3021 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
3023 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
3029 ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
3030 struct ieee80211_tx_queue_stats
*stats
)
3032 struct ath5k_softc
*sc
= hw
->priv
;
3034 memcpy(stats
, &sc
->tx_stats
, sizeof(sc
->tx_stats
));
3040 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3042 struct ath5k_softc
*sc
= hw
->priv
;
3044 return ath5k_hw_get_tsf64(sc
->ah
);
3048 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3050 struct ath5k_softc
*sc
= hw
->priv
;
3053 * in IBSS mode we need to update the beacon timers too.
3054 * this will also reset the TSF if we call it with 0
3056 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
3057 ath5k_beacon_update_timers(sc
, 0);
3059 ath5k_hw_reset_tsf(sc
->ah
);
3063 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
3065 struct ath5k_softc
*sc
= hw
->priv
;
3066 unsigned long flags
;
3069 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3071 if (sc
->opmode
!= NL80211_IFTYPE_ADHOC
) {
3076 spin_lock_irqsave(&sc
->block
, flags
);
3077 ath5k_txbuf_free(sc
, sc
->bbuf
);
3078 sc
->bbuf
->skb
= skb
;
3079 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
);
3081 sc
->bbuf
->skb
= NULL
;
3082 spin_unlock_irqrestore(&sc
->block
, flags
);
3084 ath5k_beacon_config(sc
);
3092 set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
3094 struct ath5k_softc
*sc
= hw
->priv
;
3095 struct ath5k_hw
*ah
= sc
->ah
;
3097 rfilt
= ath5k_hw_get_rx_filter(ah
);
3099 rfilt
|= AR5K_RX_FILTER_BEACON
;
3101 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
3102 ath5k_hw_set_rx_filter(ah
, rfilt
);
3103 sc
->filter_flags
= rfilt
;
3106 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
3107 struct ieee80211_vif
*vif
,
3108 struct ieee80211_bss_conf
*bss_conf
,
3111 struct ath5k_softc
*sc
= hw
->priv
;
3112 if (changes
& BSS_CHANGED_ASSOC
) {
3113 mutex_lock(&sc
->lock
);
3114 sc
->assoc
= bss_conf
->assoc
;
3115 if (sc
->opmode
== NL80211_IFTYPE_STATION
)
3116 set_beacon_filter(hw
, sc
->assoc
);
3117 mutex_unlock(&sc
->lock
);