2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
70 MODULE_AUTHOR("Jiri Slaby");
71 MODULE_AUTHOR("Nick Kossifidis");
72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
74 MODULE_LICENSE("Dual BSD/GPL");
75 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
79 static struct pci_device_id ath5k_pci_id_table
[] __devinitdata
= {
80 { PCI_VDEVICE(ATHEROS
, 0x0207), .driver_data
= AR5K_AR5210
}, /* 5210 early */
81 { PCI_VDEVICE(ATHEROS
, 0x0007), .driver_data
= AR5K_AR5210
}, /* 5210 */
82 { PCI_VDEVICE(ATHEROS
, 0x0011), .driver_data
= AR5K_AR5211
}, /* 5311 - this is on AHB bus !*/
83 { PCI_VDEVICE(ATHEROS
, 0x0012), .driver_data
= AR5K_AR5211
}, /* 5211 */
84 { PCI_VDEVICE(ATHEROS
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 5212 */
85 { PCI_VDEVICE(3COM_2
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 5212 */
86 { PCI_VDEVICE(3COM
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 3CRDAG675 5212 */
87 { PCI_VDEVICE(ATHEROS
, 0x1014), .driver_data
= AR5K_AR5212
}, /* IBM minipci 5212 */
88 { PCI_VDEVICE(ATHEROS
, 0x0014), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS
, 0x0015), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS
, 0x0016), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS
, 0x0017), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS
, 0x0018), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS
, 0x0019), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS
, 0x001a), .driver_data
= AR5K_AR5212
}, /* 2413 Griffin-lite */
95 { PCI_VDEVICE(ATHEROS
, 0x001b), .driver_data
= AR5K_AR5212
}, /* 5413 Eagle */
96 { PCI_VDEVICE(ATHEROS
, 0x001c), .driver_data
= AR5K_AR5212
}, /* PCI-E cards */
97 { PCI_VDEVICE(ATHEROS
, 0x001d), .driver_data
= AR5K_AR5212
}, /* 2417 Nala */
100 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
103 static struct ath5k_srev_name srev_names
[] = {
104 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
105 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
106 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
107 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
108 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
109 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
110 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
111 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
112 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
113 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
114 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
115 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
116 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
117 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
118 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
119 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
120 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
121 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
122 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
123 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
124 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
125 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
126 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
127 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
128 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
129 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
130 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
131 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
132 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
133 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
134 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
135 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
136 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
137 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
138 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
139 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
142 static struct ieee80211_rate ath5k_rates
[] = {
144 .hw_value
= ATH5K_RATE_CODE_1M
, },
146 .hw_value
= ATH5K_RATE_CODE_2M
,
147 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
148 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
150 .hw_value
= ATH5K_RATE_CODE_5_5M
,
151 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
152 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
154 .hw_value
= ATH5K_RATE_CODE_11M
,
155 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
156 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
158 .hw_value
= ATH5K_RATE_CODE_6M
,
161 .hw_value
= ATH5K_RATE_CODE_9M
,
164 .hw_value
= ATH5K_RATE_CODE_12M
,
167 .hw_value
= ATH5K_RATE_CODE_18M
,
170 .hw_value
= ATH5K_RATE_CODE_24M
,
173 .hw_value
= ATH5K_RATE_CODE_36M
,
176 .hw_value
= ATH5K_RATE_CODE_48M
,
179 .hw_value
= ATH5K_RATE_CODE_54M
,
185 * Prototypes - PCI stack related functions
187 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
188 const struct pci_device_id
*id
);
189 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
191 static int ath5k_pci_suspend(struct pci_dev
*pdev
,
193 static int ath5k_pci_resume(struct pci_dev
*pdev
);
195 #define ath5k_pci_suspend NULL
196 #define ath5k_pci_resume NULL
197 #endif /* CONFIG_PM */
199 static struct pci_driver ath5k_pci_driver
= {
201 .id_table
= ath5k_pci_id_table
,
202 .probe
= ath5k_pci_probe
,
203 .remove
= __devexit_p(ath5k_pci_remove
),
204 .suspend
= ath5k_pci_suspend
,
205 .resume
= ath5k_pci_resume
,
211 * Prototypes - MAC 802.11 stack related functions
213 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
214 static int ath5k_reset(struct ath5k_softc
*sc
, bool stop
, bool change_channel
);
215 static int ath5k_reset_wake(struct ath5k_softc
*sc
);
216 static int ath5k_start(struct ieee80211_hw
*hw
);
217 static void ath5k_stop(struct ieee80211_hw
*hw
);
218 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
219 struct ieee80211_if_init_conf
*conf
);
220 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
221 struct ieee80211_if_init_conf
*conf
);
222 static int ath5k_config(struct ieee80211_hw
*hw
, u32 changed
);
223 static int ath5k_config_interface(struct ieee80211_hw
*hw
,
224 struct ieee80211_vif
*vif
,
225 struct ieee80211_if_conf
*conf
);
226 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
227 unsigned int changed_flags
,
228 unsigned int *new_flags
,
229 int mc_count
, struct dev_mc_list
*mclist
);
230 static int ath5k_set_key(struct ieee80211_hw
*hw
,
231 enum set_key_cmd cmd
,
232 const u8
*local_addr
, const u8
*addr
,
233 struct ieee80211_key_conf
*key
);
234 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
235 struct ieee80211_low_level_stats
*stats
);
236 static int ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
237 struct ieee80211_tx_queue_stats
*stats
);
238 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
239 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
240 static int ath5k_beacon_update(struct ath5k_softc
*sc
, struct sk_buff
*skb
);
242 static struct ieee80211_ops ath5k_hw_ops
= {
244 .start
= ath5k_start
,
246 .add_interface
= ath5k_add_interface
,
247 .remove_interface
= ath5k_remove_interface
,
248 .config
= ath5k_config
,
249 .config_interface
= ath5k_config_interface
,
250 .configure_filter
= ath5k_configure_filter
,
251 .set_key
= ath5k_set_key
,
252 .get_stats
= ath5k_get_stats
,
254 .get_tx_stats
= ath5k_get_tx_stats
,
255 .get_tsf
= ath5k_get_tsf
,
256 .reset_tsf
= ath5k_reset_tsf
,
260 * Prototypes - Internal functions
263 static int ath5k_attach(struct pci_dev
*pdev
,
264 struct ieee80211_hw
*hw
);
265 static void ath5k_detach(struct pci_dev
*pdev
,
266 struct ieee80211_hw
*hw
);
267 /* Channel/mode setup */
268 static inline short ath5k_ieee2mhz(short chan
);
269 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
270 struct ieee80211_channel
*channels
,
273 static int ath5k_setup_bands(struct ieee80211_hw
*hw
);
274 static int ath5k_chan_set(struct ath5k_softc
*sc
,
275 struct ieee80211_channel
*chan
);
276 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
278 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
280 /* Descriptor setup */
281 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
282 struct pci_dev
*pdev
);
283 static void ath5k_desc_free(struct ath5k_softc
*sc
,
284 struct pci_dev
*pdev
);
286 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
287 struct ath5k_buf
*bf
);
288 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
289 struct ath5k_buf
*bf
);
290 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
291 struct ath5k_buf
*bf
)
296 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
298 dev_kfree_skb_any(bf
->skb
);
303 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
304 int qtype
, int subtype
);
305 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
306 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
307 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
308 struct ath5k_txq
*txq
);
309 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
310 static void ath5k_txq_release(struct ath5k_softc
*sc
);
312 static int ath5k_rx_start(struct ath5k_softc
*sc
);
313 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
314 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
315 struct ath5k_desc
*ds
,
317 struct ath5k_rx_status
*rs
);
318 static void ath5k_tasklet_rx(unsigned long data
);
320 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
321 struct ath5k_txq
*txq
);
322 static void ath5k_tasklet_tx(unsigned long data
);
323 /* Beacon handling */
324 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
325 struct ath5k_buf
*bf
);
326 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
327 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
328 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
330 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
332 u64 tsf
= ath5k_hw_get_tsf64(ah
);
334 if ((tsf
& 0x7fff) < rstamp
)
337 return (tsf
& ~0x7fff) | rstamp
;
340 /* Interrupt handling */
341 static int ath5k_init(struct ath5k_softc
*sc
, bool is_resume
);
342 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
343 static int ath5k_stop_hw(struct ath5k_softc
*sc
, bool is_suspend
);
344 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
345 static void ath5k_tasklet_reset(unsigned long data
);
347 static void ath5k_calibrate(unsigned long data
);
349 static int ath5k_init_leds(struct ath5k_softc
*sc
);
350 static void ath5k_led_enable(struct ath5k_softc
*sc
);
351 static void ath5k_led_off(struct ath5k_softc
*sc
);
352 static void ath5k_unregister_leds(struct ath5k_softc
*sc
);
355 * Module init/exit functions
364 ret
= pci_register_driver(&ath5k_pci_driver
);
366 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
376 pci_unregister_driver(&ath5k_pci_driver
);
378 ath5k_debug_finish();
381 module_init(init_ath5k_pci
);
382 module_exit(exit_ath5k_pci
);
385 /********************\
386 * PCI Initialization *
387 \********************/
390 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
392 const char *name
= "xxxxx";
395 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
396 if (srev_names
[i
].sr_type
!= type
)
399 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
400 name
= srev_names
[i
].sr_name
;
402 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
403 name
= srev_names
[i
].sr_name
;
412 ath5k_pci_probe(struct pci_dev
*pdev
,
413 const struct pci_device_id
*id
)
416 struct ath5k_softc
*sc
;
417 struct ieee80211_hw
*hw
;
421 ret
= pci_enable_device(pdev
);
423 dev_err(&pdev
->dev
, "can't enable device\n");
427 /* XXX 32-bit addressing only */
428 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
430 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
435 * Cache line size is used to size and align various
436 * structures used to communicate with the hardware.
438 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
441 * Linux 2.4.18 (at least) writes the cache line size
442 * register as a 16-bit wide register which is wrong.
443 * We must have this setup properly for rx buffer
444 * DMA to work so force a reasonable value here if it
447 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
448 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
451 * The default setting of latency timer yields poor results,
452 * set it to the value used by other systems. It may be worth
453 * tweaking this setting more.
455 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
457 /* Enable bus mastering */
458 pci_set_master(pdev
);
461 * Disable the RETRY_TIMEOUT register (0x41) to keep
462 * PCI Tx retries from interfering with C3 CPU state.
464 pci_write_config_byte(pdev
, 0x41, 0);
466 ret
= pci_request_region(pdev
, 0, "ath5k");
468 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
472 mem
= pci_iomap(pdev
, 0, 0);
474 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
480 * Allocate hw (mac80211 main struct)
481 * and hw->priv (driver private data)
483 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
485 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
490 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
492 /* Initialize driver private data */
493 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
494 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
495 IEEE80211_HW_SIGNAL_DBM
|
496 IEEE80211_HW_NOISE_DBM
;
498 hw
->wiphy
->interface_modes
=
499 BIT(NL80211_IFTYPE_STATION
) |
500 BIT(NL80211_IFTYPE_ADHOC
) |
501 BIT(NL80211_IFTYPE_MESH_POINT
);
503 hw
->extra_tx_headroom
= 2;
504 hw
->channel_change_time
= 5000;
509 ath5k_debug_init_device(sc
);
512 * Mark the device as detached to avoid processing
513 * interrupts until setup is complete.
515 __set_bit(ATH_STAT_INVALID
, sc
->status
);
517 sc
->iobase
= mem
; /* So we can unmap it on detach */
518 sc
->cachelsz
= csz
* sizeof(u32
); /* convert to bytes */
519 sc
->opmode
= NL80211_IFTYPE_STATION
;
520 mutex_init(&sc
->lock
);
521 spin_lock_init(&sc
->rxbuflock
);
522 spin_lock_init(&sc
->txbuflock
);
523 spin_lock_init(&sc
->block
);
525 /* Set private data */
526 pci_set_drvdata(pdev
, hw
);
528 /* Setup interrupt handler */
529 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
531 ATH5K_ERR(sc
, "request_irq failed\n");
535 /* Initialize device */
536 sc
->ah
= ath5k_hw_attach(sc
, id
->driver_data
);
537 if (IS_ERR(sc
->ah
)) {
538 ret
= PTR_ERR(sc
->ah
);
542 /* set up multi-rate retry capabilities */
543 if (sc
->ah
->ah_version
== AR5K_AR5212
) {
545 hw
->max_rate_tries
= 11;
548 /* Finish private driver data initialization */
549 ret
= ath5k_attach(pdev
, hw
);
553 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
554 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
556 sc
->ah
->ah_phy_revision
);
558 if (!sc
->ah
->ah_single_chip
) {
559 /* Single chip radio (!RF5111) */
560 if (sc
->ah
->ah_radio_5ghz_revision
&&
561 !sc
->ah
->ah_radio_2ghz_revision
) {
562 /* No 5GHz support -> report 2GHz radio */
563 if (!test_bit(AR5K_MODE_11A
,
564 sc
->ah
->ah_capabilities
.cap_mode
)) {
565 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
566 ath5k_chip_name(AR5K_VERSION_RAD
,
567 sc
->ah
->ah_radio_5ghz_revision
),
568 sc
->ah
->ah_radio_5ghz_revision
);
569 /* No 2GHz support (5110 and some
570 * 5Ghz only cards) -> report 5Ghz radio */
571 } else if (!test_bit(AR5K_MODE_11B
,
572 sc
->ah
->ah_capabilities
.cap_mode
)) {
573 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
574 ath5k_chip_name(AR5K_VERSION_RAD
,
575 sc
->ah
->ah_radio_5ghz_revision
),
576 sc
->ah
->ah_radio_5ghz_revision
);
577 /* Multiband radio */
579 ATH5K_INFO(sc
, "RF%s multiband radio found"
581 ath5k_chip_name(AR5K_VERSION_RAD
,
582 sc
->ah
->ah_radio_5ghz_revision
),
583 sc
->ah
->ah_radio_5ghz_revision
);
586 /* Multi chip radio (RF5111 - RF2111) ->
587 * report both 2GHz/5GHz radios */
588 else if (sc
->ah
->ah_radio_5ghz_revision
&&
589 sc
->ah
->ah_radio_2ghz_revision
){
590 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
591 ath5k_chip_name(AR5K_VERSION_RAD
,
592 sc
->ah
->ah_radio_5ghz_revision
),
593 sc
->ah
->ah_radio_5ghz_revision
);
594 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
595 ath5k_chip_name(AR5K_VERSION_RAD
,
596 sc
->ah
->ah_radio_2ghz_revision
),
597 sc
->ah
->ah_radio_2ghz_revision
);
602 /* ready to process interrupts */
603 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
607 ath5k_hw_detach(sc
->ah
);
609 free_irq(pdev
->irq
, sc
);
611 ieee80211_free_hw(hw
);
613 pci_iounmap(pdev
, mem
);
615 pci_release_region(pdev
, 0);
617 pci_disable_device(pdev
);
622 static void __devexit
623 ath5k_pci_remove(struct pci_dev
*pdev
)
625 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
626 struct ath5k_softc
*sc
= hw
->priv
;
628 ath5k_debug_finish_device(sc
);
629 ath5k_detach(pdev
, hw
);
630 ath5k_hw_detach(sc
->ah
);
631 free_irq(pdev
->irq
, sc
);
632 pci_iounmap(pdev
, sc
->iobase
);
633 pci_release_region(pdev
, 0);
634 pci_disable_device(pdev
);
635 ieee80211_free_hw(hw
);
640 ath5k_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
642 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
643 struct ath5k_softc
*sc
= hw
->priv
;
647 ath5k_stop_hw(sc
, true);
649 free_irq(pdev
->irq
, sc
);
650 pci_save_state(pdev
);
651 pci_disable_device(pdev
);
652 pci_set_power_state(pdev
, PCI_D3hot
);
658 ath5k_pci_resume(struct pci_dev
*pdev
)
660 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
661 struct ath5k_softc
*sc
= hw
->priv
;
664 pci_restore_state(pdev
);
666 err
= pci_enable_device(pdev
);
671 * Suspend/Resume resets the PCI configuration space, so we have to
672 * re-disable the RETRY_TIMEOUT register (0x41) to keep
673 * PCI Tx retries from interfering with C3 CPU state
675 pci_write_config_byte(pdev
, 0x41, 0);
677 err
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
679 ATH5K_ERR(sc
, "request_irq failed\n");
683 err
= ath5k_init(sc
, true);
686 ath5k_led_enable(sc
);
690 free_irq(pdev
->irq
, sc
);
692 pci_disable_device(pdev
);
695 #endif /* CONFIG_PM */
698 /***********************\
699 * Driver Initialization *
700 \***********************/
703 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
705 struct ath5k_softc
*sc
= hw
->priv
;
706 struct ath5k_hw
*ah
= sc
->ah
;
710 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
713 * Check if the MAC has multi-rate retry support.
714 * We do this by trying to setup a fake extended
715 * descriptor. MAC's that don't have support will
716 * return false w/o doing anything. MAC's that do
717 * support it will return true w/o doing anything.
719 ret
= ah
->ah_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
723 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
726 * Collect the channel list. The 802.11 layer
727 * is resposible for filtering this list based
728 * on settings like the phy mode and regulatory
729 * domain restrictions.
731 ret
= ath5k_setup_bands(hw
);
733 ATH5K_ERR(sc
, "can't get channels\n");
737 /* NB: setup here so ath5k_rate_update is happy */
738 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
739 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
741 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
744 * Allocate tx+rx descriptors and populate the lists.
746 ret
= ath5k_desc_alloc(sc
, pdev
);
748 ATH5K_ERR(sc
, "can't allocate descriptors\n");
753 * Allocate hardware transmit queues: one queue for
754 * beacon frames and one data queue for each QoS
755 * priority. Note that hw functions handle reseting
756 * these queues at the needed time.
758 ret
= ath5k_beaconq_setup(ah
);
760 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
765 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
766 if (IS_ERR(sc
->txq
)) {
767 ATH5K_ERR(sc
, "can't setup xmit queue\n");
768 ret
= PTR_ERR(sc
->txq
);
772 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
773 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
774 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
775 setup_timer(&sc
->calib_tim
, ath5k_calibrate
, (unsigned long)sc
);
777 ath5k_hw_get_lladdr(ah
, mac
);
778 SET_IEEE80211_PERM_ADDR(hw
, mac
);
779 /* All MAC address bits matter for ACKs */
780 memset(sc
->bssidmask
, 0xff, ETH_ALEN
);
781 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
783 ret
= ieee80211_register_hw(hw
);
785 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
793 ath5k_txq_release(sc
);
795 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
797 ath5k_desc_free(sc
, pdev
);
803 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
805 struct ath5k_softc
*sc
= hw
->priv
;
808 * NB: the order of these is important:
809 * o call the 802.11 layer before detaching ath5k_hw to
810 * insure callbacks into the driver to delete global
811 * key cache entries can be handled
812 * o reclaim the tx queue data structures after calling
813 * the 802.11 layer as we'll get called back to reclaim
814 * node state and potentially want to use them
815 * o to cleanup the tx queues the hal is called, so detach
817 * XXX: ??? detach ath5k_hw ???
818 * Other than that, it's straightforward...
820 ieee80211_unregister_hw(hw
);
821 ath5k_desc_free(sc
, pdev
);
822 ath5k_txq_release(sc
);
823 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
824 ath5k_unregister_leds(sc
);
827 * NB: can't reclaim these until after ieee80211_ifdetach
828 * returns because we'll get called back to reclaim node
829 * state and potentially want to use them.
836 /********************\
837 * Channel/mode setup *
838 \********************/
841 * Convert IEEE channel number to MHz frequency.
844 ath5k_ieee2mhz(short chan
)
846 if (chan
<= 14 || chan
>= 27)
847 return ieee80211chan2mhz(chan
);
849 return 2212 + chan
* 20;
853 ath5k_copy_channels(struct ath5k_hw
*ah
,
854 struct ieee80211_channel
*channels
,
858 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
860 if (!test_bit(mode
, ah
->ah_modes
))
865 case AR5K_MODE_11A_TURBO
:
866 /* 1..220, but 2GHz frequencies are filtered by check_channel */
868 chfreq
= CHANNEL_5GHZ
;
872 case AR5K_MODE_11G_TURBO
:
874 chfreq
= CHANNEL_2GHZ
;
877 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
881 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
883 freq
= ath5k_ieee2mhz(ch
);
885 /* Check if channel is supported by the chipset */
886 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
889 /* Write channel info and increment counter */
890 channels
[count
].center_freq
= freq
;
891 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
892 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
896 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
898 case AR5K_MODE_11A_TURBO
:
899 case AR5K_MODE_11G_TURBO
:
900 channels
[count
].hw_value
= chfreq
|
901 CHANNEL_OFDM
| CHANNEL_TURBO
;
904 channels
[count
].hw_value
= CHANNEL_B
;
915 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
919 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
920 sc
->rate_idx
[b
->band
][i
] = -1;
922 for (i
= 0; i
< b
->n_bitrates
; i
++) {
923 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
924 if (b
->bitrates
[i
].hw_value_short
)
925 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
930 ath5k_setup_bands(struct ieee80211_hw
*hw
)
932 struct ath5k_softc
*sc
= hw
->priv
;
933 struct ath5k_hw
*ah
= sc
->ah
;
934 struct ieee80211_supported_band
*sband
;
935 int max_c
, count_c
= 0;
938 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
939 max_c
= ARRAY_SIZE(sc
->channels
);
942 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
943 sband
->band
= IEEE80211_BAND_2GHZ
;
944 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
946 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
948 memcpy(sband
->bitrates
, &ath5k_rates
[0],
949 sizeof(struct ieee80211_rate
) * 12);
950 sband
->n_bitrates
= 12;
952 sband
->channels
= sc
->channels
;
953 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
954 AR5K_MODE_11G
, max_c
);
956 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
957 count_c
= sband
->n_channels
;
959 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
961 memcpy(sband
->bitrates
, &ath5k_rates
[0],
962 sizeof(struct ieee80211_rate
) * 4);
963 sband
->n_bitrates
= 4;
965 /* 5211 only supports B rates and uses 4bit rate codes
966 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
969 if (ah
->ah_version
== AR5K_AR5211
) {
970 for (i
= 0; i
< 4; i
++) {
971 sband
->bitrates
[i
].hw_value
=
972 sband
->bitrates
[i
].hw_value
& 0xF;
973 sband
->bitrates
[i
].hw_value_short
=
974 sband
->bitrates
[i
].hw_value_short
& 0xF;
978 sband
->channels
= sc
->channels
;
979 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
980 AR5K_MODE_11B
, max_c
);
982 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
983 count_c
= sband
->n_channels
;
986 ath5k_setup_rate_idx(sc
, sband
);
988 /* 5GHz band, A mode */
989 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
990 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
991 sband
->band
= IEEE80211_BAND_5GHZ
;
992 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
994 memcpy(sband
->bitrates
, &ath5k_rates
[4],
995 sizeof(struct ieee80211_rate
) * 8);
996 sband
->n_bitrates
= 8;
998 sband
->channels
= &sc
->channels
[count_c
];
999 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1000 AR5K_MODE_11A
, max_c
);
1002 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
1004 ath5k_setup_rate_idx(sc
, sband
);
1006 ath5k_debug_dump_bands(sc
);
1012 * Set/change channels. If the channel is really being changed,
1013 * it's done by reseting the chip. To accomplish this we must
1014 * first cleanup any pending DMA, then restart stuff after a la
1018 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1020 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "(%u MHz) -> (%u MHz)\n",
1021 sc
->curchan
->center_freq
, chan
->center_freq
);
1023 if (chan
->center_freq
!= sc
->curchan
->center_freq
||
1024 chan
->hw_value
!= sc
->curchan
->hw_value
) {
1027 sc
->curband
= &sc
->sbands
[chan
->band
];
1030 * To switch channels clear any pending DMA operations;
1031 * wait long enough for the RX fifo to drain, reset the
1032 * hardware at the new frequency, and then re-enable
1033 * the relevant bits of the h/w.
1035 return ath5k_reset(sc
, true, true);
1042 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1046 if (mode
== AR5K_MODE_11A
) {
1047 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1049 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1054 ath5k_mode_setup(struct ath5k_softc
*sc
)
1056 struct ath5k_hw
*ah
= sc
->ah
;
1059 /* configure rx filter */
1060 rfilt
= sc
->filter_flags
;
1061 ath5k_hw_set_rx_filter(ah
, rfilt
);
1063 if (ath5k_hw_hasbssidmask(ah
))
1064 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1066 /* configure operational mode */
1067 ath5k_hw_set_opmode(ah
);
1069 ath5k_hw_set_mcast_filter(ah
, 0, 0);
1070 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1074 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
1076 WARN_ON(hw_rix
< 0 || hw_rix
> AR5K_MAX_RATES
);
1077 return sc
->rate_idx
[sc
->curband
->band
][hw_rix
];
1085 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1087 struct ath5k_hw
*ah
= sc
->ah
;
1088 struct sk_buff
*skb
= bf
->skb
;
1089 struct ath5k_desc
*ds
;
1091 if (likely(skb
== NULL
)) {
1095 * Allocate buffer with headroom_needed space for the
1096 * fake physical layer header at the start.
1098 skb
= dev_alloc_skb(sc
->rxbufsize
+ sc
->cachelsz
- 1);
1099 if (unlikely(skb
== NULL
)) {
1100 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1101 sc
->rxbufsize
+ sc
->cachelsz
- 1);
1105 * Cache-line-align. This is important (for the
1106 * 5210 at least) as not doing so causes bogus data
1109 off
= ((unsigned long)skb
->data
) % sc
->cachelsz
;
1111 skb_reserve(skb
, sc
->cachelsz
- off
);
1114 bf
->skbaddr
= pci_map_single(sc
->pdev
,
1115 skb
->data
, sc
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1116 if (unlikely(pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
))) {
1117 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1125 * Setup descriptors. For receive we always terminate
1126 * the descriptor list with a self-linked entry so we'll
1127 * not get overrun under high load (as can happen with a
1128 * 5212 when ANI processing enables PHY error frames).
1130 * To insure the last descriptor is self-linked we create
1131 * each descriptor as self-linked and add it to the end. As
1132 * each additional descriptor is added the previous self-linked
1133 * entry is ``fixed'' naturally. This should be safe even
1134 * if DMA is happening. When processing RX interrupts we
1135 * never remove/process the last, self-linked, entry on the
1136 * descriptor list. This insures the hardware always has
1137 * someplace to write a new frame.
1140 ds
->ds_link
= bf
->daddr
; /* link to self */
1141 ds
->ds_data
= bf
->skbaddr
;
1142 ah
->ah_setup_rx_desc(ah
, ds
,
1143 skb_tailroom(skb
), /* buffer size */
1146 if (sc
->rxlink
!= NULL
)
1147 *sc
->rxlink
= bf
->daddr
;
1148 sc
->rxlink
= &ds
->ds_link
;
1153 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1155 struct ath5k_hw
*ah
= sc
->ah
;
1156 struct ath5k_txq
*txq
= sc
->txq
;
1157 struct ath5k_desc
*ds
= bf
->desc
;
1158 struct sk_buff
*skb
= bf
->skb
;
1159 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1160 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1161 struct ieee80211_rate
*rate
;
1162 unsigned int mrr_rate
[3], mrr_tries
[3];
1165 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1167 /* XXX endianness */
1168 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1171 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1172 flags
|= AR5K_TXDESC_NOACK
;
1176 if (info
->control
.hw_key
) {
1177 keyidx
= info
->control
.hw_key
->hw_key_idx
;
1178 pktlen
+= info
->control
.hw_key
->icv_len
;
1180 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1181 ieee80211_get_hdrlen_from_skb(skb
), AR5K_PKT_TYPE_NORMAL
,
1182 (sc
->power_level
* 2),
1183 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1184 info
->control
.rates
[0].count
, keyidx
, 0, flags
, 0, 0);
1188 memset(mrr_rate
, 0, sizeof(mrr_rate
));
1189 memset(mrr_tries
, 0, sizeof(mrr_tries
));
1190 for (i
= 0; i
< 3; i
++) {
1191 rate
= ieee80211_get_alt_retry_rate(sc
->hw
, info
, i
);
1195 mrr_rate
[i
] = rate
->hw_value
;
1196 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
1199 ah
->ah_setup_mrr_tx_desc(ah
, ds
,
1200 mrr_rate
[0], mrr_tries
[0],
1201 mrr_rate
[1], mrr_tries
[1],
1202 mrr_rate
[2], mrr_tries
[2]);
1205 ds
->ds_data
= bf
->skbaddr
;
1207 spin_lock_bh(&txq
->lock
);
1208 list_add_tail(&bf
->list
, &txq
->q
);
1209 sc
->tx_stats
[txq
->qnum
].len
++;
1210 if (txq
->link
== NULL
) /* is this first packet? */
1211 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
1212 else /* no, so only link it */
1213 *txq
->link
= bf
->daddr
;
1215 txq
->link
= &ds
->ds_link
;
1216 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
1218 spin_unlock_bh(&txq
->lock
);
1222 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1226 /*******************\
1227 * Descriptors setup *
1228 \*******************/
1231 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1233 struct ath5k_desc
*ds
;
1234 struct ath5k_buf
*bf
;
1239 /* allocate descriptors */
1240 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1241 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1242 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1243 if (sc
->desc
== NULL
) {
1244 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1249 da
= sc
->desc_daddr
;
1250 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1251 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1253 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1254 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1256 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1262 INIT_LIST_HEAD(&sc
->rxbuf
);
1263 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1266 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1269 INIT_LIST_HEAD(&sc
->txbuf
);
1270 sc
->txbuf_len
= ATH_TXBUF
;
1271 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1272 da
+= sizeof(*ds
)) {
1275 list_add_tail(&bf
->list
, &sc
->txbuf
);
1285 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1292 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1294 struct ath5k_buf
*bf
;
1296 ath5k_txbuf_free(sc
, sc
->bbuf
);
1297 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1298 ath5k_txbuf_free(sc
, bf
);
1299 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1300 ath5k_txbuf_free(sc
, bf
);
1302 /* Free memory associated with all descriptors */
1303 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1317 static struct ath5k_txq
*
1318 ath5k_txq_setup(struct ath5k_softc
*sc
,
1319 int qtype
, int subtype
)
1321 struct ath5k_hw
*ah
= sc
->ah
;
1322 struct ath5k_txq
*txq
;
1323 struct ath5k_txq_info qi
= {
1324 .tqi_subtype
= subtype
,
1325 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1326 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1327 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1332 * Enable interrupts only for EOL and DESC conditions.
1333 * We mark tx descriptors to receive a DESC interrupt
1334 * when a tx queue gets deep; otherwise waiting for the
1335 * EOL to reap descriptors. Note that this is done to
1336 * reduce interrupt load and this only defers reaping
1337 * descriptors, never transmitting frames. Aside from
1338 * reducing interrupts this also permits more concurrency.
1339 * The only potential downside is if the tx queue backs
1340 * up in which case the top half of the kernel may backup
1341 * due to a lack of tx descriptors.
1343 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1344 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1345 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1348 * NB: don't print a message, this happens
1349 * normally on parts with too few tx queues
1351 return ERR_PTR(qnum
);
1353 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1354 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1355 qnum
, ARRAY_SIZE(sc
->txqs
));
1356 ath5k_hw_release_tx_queue(ah
, qnum
);
1357 return ERR_PTR(-EINVAL
);
1359 txq
= &sc
->txqs
[qnum
];
1363 INIT_LIST_HEAD(&txq
->q
);
1364 spin_lock_init(&txq
->lock
);
1367 return &sc
->txqs
[qnum
];
1371 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1373 struct ath5k_txq_info qi
= {
1374 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1375 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1376 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1377 /* NB: for dynamic turbo, don't enable any other interrupts */
1378 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1381 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1385 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1387 struct ath5k_hw
*ah
= sc
->ah
;
1388 struct ath5k_txq_info qi
;
1391 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1394 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1395 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1397 * Always burst out beacon and CAB traffic
1398 * (aifs = cwmin = cwmax = 0)
1403 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
1405 * Adhoc mode; backoff between 0 and (2 * cw_min).
1409 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1412 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1413 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1414 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1416 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1418 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1419 "hardware queue!\n", __func__
);
1423 return ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */;
1427 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1429 struct ath5k_buf
*bf
, *bf0
;
1432 * NB: this assumes output has been stopped and
1433 * we do not need to block ath5k_tx_tasklet
1435 spin_lock_bh(&txq
->lock
);
1436 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1437 ath5k_debug_printtxbuf(sc
, bf
);
1439 ath5k_txbuf_free(sc
, bf
);
1441 spin_lock_bh(&sc
->txbuflock
);
1442 sc
->tx_stats
[txq
->qnum
].len
--;
1443 list_move_tail(&bf
->list
, &sc
->txbuf
);
1445 spin_unlock_bh(&sc
->txbuflock
);
1448 spin_unlock_bh(&txq
->lock
);
1452 * Drain the transmit queues and reclaim resources.
1455 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1457 struct ath5k_hw
*ah
= sc
->ah
;
1460 /* XXX return value */
1461 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1462 /* don't touch the hardware if marked invalid */
1463 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1464 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1465 ath5k_hw_get_txdp(ah
, sc
->bhalq
));
1466 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1467 if (sc
->txqs
[i
].setup
) {
1468 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1469 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1472 ath5k_hw_get_txdp(ah
,
1477 ieee80211_wake_queues(sc
->hw
); /* XXX move to callers */
1479 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1480 if (sc
->txqs
[i
].setup
)
1481 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1485 ath5k_txq_release(struct ath5k_softc
*sc
)
1487 struct ath5k_txq
*txq
= sc
->txqs
;
1490 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1492 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1505 * Enable the receive h/w following a reset.
1508 ath5k_rx_start(struct ath5k_softc
*sc
)
1510 struct ath5k_hw
*ah
= sc
->ah
;
1511 struct ath5k_buf
*bf
;
1514 sc
->rxbufsize
= roundup(IEEE80211_MAX_LEN
, sc
->cachelsz
);
1516 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rxbufsize %u\n",
1517 sc
->cachelsz
, sc
->rxbufsize
);
1521 spin_lock_bh(&sc
->rxbuflock
);
1522 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1523 ret
= ath5k_rxbuf_setup(sc
, bf
);
1525 spin_unlock_bh(&sc
->rxbuflock
);
1529 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1530 spin_unlock_bh(&sc
->rxbuflock
);
1532 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1533 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1534 ath5k_mode_setup(sc
); /* set filters, etc. */
1535 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1543 * Disable the receive h/w in preparation for a reset.
1546 ath5k_rx_stop(struct ath5k_softc
*sc
)
1548 struct ath5k_hw
*ah
= sc
->ah
;
1550 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1551 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1552 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1554 ath5k_debug_printrxbuffs(sc
, ah
);
1556 sc
->rxlink
= NULL
; /* just in case */
1560 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1561 struct sk_buff
*skb
, struct ath5k_rx_status
*rs
)
1563 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1564 unsigned int keyix
, hlen
;
1566 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1567 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1568 return RX_FLAG_DECRYPTED
;
1570 /* Apparently when a default key is used to decrypt the packet
1571 the hw does not set the index used to decrypt. In such cases
1572 get the index from the packet. */
1573 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1574 if (ieee80211_has_protected(hdr
->frame_control
) &&
1575 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1576 skb
->len
>= hlen
+ 4) {
1577 keyix
= skb
->data
[hlen
+ 3] >> 6;
1579 if (test_bit(keyix
, sc
->keymap
))
1580 return RX_FLAG_DECRYPTED
;
1588 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1589 struct ieee80211_rx_status
*rxs
)
1593 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1595 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1596 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1597 memcmp(mgmt
->bssid
, sc
->ah
->ah_bssid
, ETH_ALEN
) == 0) {
1599 * Received an IBSS beacon with the same BSSID. Hardware *must*
1600 * have updated the local TSF. We have to work around various
1601 * hardware bugs, though...
1603 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1604 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1605 hw_tu
= TSF_TO_TU(tsf
);
1607 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1608 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1609 (unsigned long long)bc_tstamp
,
1610 (unsigned long long)rxs
->mactime
,
1611 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1612 (unsigned long long)tsf
);
1615 * Sometimes the HW will give us a wrong tstamp in the rx
1616 * status, causing the timestamp extension to go wrong.
1617 * (This seems to happen especially with beacon frames bigger
1618 * than 78 byte (incl. FCS))
1619 * But we know that the receive timestamp must be later than the
1620 * timestamp of the beacon since HW must have synced to that.
1622 * NOTE: here we assume mactime to be after the frame was
1623 * received, not like mac80211 which defines it at the start.
1625 if (bc_tstamp
> rxs
->mactime
) {
1626 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1627 "fixing mactime from %llx to %llx\n",
1628 (unsigned long long)rxs
->mactime
,
1629 (unsigned long long)tsf
);
1634 * Local TSF might have moved higher than our beacon timers,
1635 * in that case we have to update them to continue sending
1636 * beacons. This also takes care of synchronizing beacon sending
1637 * times with other stations.
1639 if (hw_tu
>= sc
->nexttbtt
)
1640 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1646 ath5k_tasklet_rx(unsigned long data
)
1648 struct ieee80211_rx_status rxs
= {};
1649 struct ath5k_rx_status rs
= {};
1650 struct sk_buff
*skb
;
1651 struct ath5k_softc
*sc
= (void *)data
;
1652 struct ath5k_buf
*bf
, *bf_last
;
1653 struct ath5k_desc
*ds
;
1658 spin_lock(&sc
->rxbuflock
);
1659 if (list_empty(&sc
->rxbuf
)) {
1660 ATH5K_WARN(sc
, "empty rx buf pool\n");
1663 bf_last
= list_entry(sc
->rxbuf
.prev
, struct ath5k_buf
, list
);
1667 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1668 BUG_ON(bf
->skb
== NULL
);
1673 * last buffer must not be freed to ensure proper hardware
1674 * function. When the hardware finishes also a packet next to
1675 * it, we are sure, it doesn't use it anymore and we can go on.
1680 struct ath5k_buf
*bf_next
= list_entry(bf
->list
.next
,
1681 struct ath5k_buf
, list
);
1682 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, bf_next
->desc
,
1687 /* skip the overwritten one (even status is martian) */
1691 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1692 if (unlikely(ret
== -EINPROGRESS
))
1694 else if (unlikely(ret
)) {
1695 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1696 spin_unlock(&sc
->rxbuflock
);
1700 if (unlikely(rs
.rs_more
)) {
1701 ATH5K_WARN(sc
, "unsupported jumbo\n");
1705 if (unlikely(rs
.rs_status
)) {
1706 if (rs
.rs_status
& AR5K_RXERR_PHY
)
1708 if (rs
.rs_status
& AR5K_RXERR_DECRYPT
) {
1710 * Decrypt error. If the error occurred
1711 * because there was no hardware key, then
1712 * let the frame through so the upper layers
1713 * can process it. This is necessary for 5210
1714 * parts which have no way to setup a ``clear''
1717 * XXX do key cache faulting
1719 if (rs
.rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1720 !(rs
.rs_status
& AR5K_RXERR_CRC
))
1723 if (rs
.rs_status
& AR5K_RXERR_MIC
) {
1724 rxs
.flag
|= RX_FLAG_MMIC_ERROR
;
1728 /* let crypto-error packets fall through in MNTR */
1730 ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1731 sc
->opmode
!= NL80211_IFTYPE_MONITOR
)
1735 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
1736 PCI_DMA_FROMDEVICE
);
1739 skb_put(skb
, rs
.rs_datalen
);
1742 * the hardware adds a padding to 4 byte boundaries between
1743 * the header and the payload data if the header length is
1744 * not multiples of 4 - remove it
1746 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1749 memmove(skb
->data
+ pad
, skb
->data
, hdrlen
);
1754 * always extend the mac timestamp, since this information is
1755 * also needed for proper IBSS merging.
1757 * XXX: it might be too late to do it here, since rs_tstamp is
1758 * 15bit only. that means TSF extension has to be done within
1759 * 32768usec (about 32ms). it might be necessary to move this to
1760 * the interrupt handler, like it is done in madwifi.
1762 * Unfortunately we don't know when the hardware takes the rx
1763 * timestamp (beginning of phy frame, data frame, end of rx?).
1764 * The only thing we know is that it is hardware specific...
1765 * On AR5213 it seems the rx timestamp is at the end of the
1766 * frame, but i'm not sure.
1768 * NOTE: mac80211 defines mactime at the beginning of the first
1769 * data symbol. Since we don't have any time references it's
1770 * impossible to comply to that. This affects IBSS merge only
1771 * right now, so it's not too bad...
1773 rxs
.mactime
= ath5k_extend_tsf(sc
->ah
, rs
.rs_tstamp
);
1774 rxs
.flag
|= RX_FLAG_TSFT
;
1776 rxs
.freq
= sc
->curchan
->center_freq
;
1777 rxs
.band
= sc
->curband
->band
;
1779 rxs
.noise
= sc
->ah
->ah_noise_floor
;
1780 rxs
.signal
= rxs
.noise
+ rs
.rs_rssi
;
1782 /* An rssi of 35 indicates you should be able use
1783 * 54 Mbps reliably. A more elaborate scheme can be used
1784 * here but it requires a map of SNR/throughput for each
1785 * possible mode used */
1786 rxs
.qual
= rs
.rs_rssi
* 100 / 35;
1788 /* rssi can be more than 35 though, anything above that
1789 * should be considered at 100% */
1793 rxs
.antenna
= rs
.rs_antenna
;
1794 rxs
.rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
.rs_rate
);
1795 rxs
.flag
|= ath5k_rx_decrypted(sc
, ds
, skb
, &rs
);
1797 if (rxs
.rate_idx
>= 0 && rs
.rs_rate
==
1798 sc
->curband
->bitrates
[rxs
.rate_idx
].hw_value_short
)
1799 rxs
.flag
|= RX_FLAG_SHORTPRE
;
1801 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1803 /* check beacons in IBSS mode */
1804 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1805 ath5k_check_ibss_tsf(sc
, skb
, &rxs
);
1807 __ieee80211_rx(sc
->hw
, skb
, &rxs
);
1809 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1810 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1812 spin_unlock(&sc
->rxbuflock
);
1823 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1825 struct ath5k_tx_status ts
= {};
1826 struct ath5k_buf
*bf
, *bf0
;
1827 struct ath5k_desc
*ds
;
1828 struct sk_buff
*skb
;
1829 struct ieee80211_tx_info
*info
;
1832 spin_lock(&txq
->lock
);
1833 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1836 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1837 if (unlikely(ret
== -EINPROGRESS
))
1839 else if (unlikely(ret
)) {
1840 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
1846 info
= IEEE80211_SKB_CB(skb
);
1849 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1852 ieee80211_tx_info_clear_status(info
);
1853 for (i
= 0; i
< 4; i
++) {
1854 struct ieee80211_tx_rate
*r
=
1855 &info
->status
.rates
[i
];
1857 if (ts
.ts_rate
[i
]) {
1858 r
->idx
= ath5k_hw_to_driver_rix(sc
, ts
.ts_rate
[i
]);
1859 r
->count
= ts
.ts_retry
[i
];
1866 /* count the successful attempt as well */
1867 info
->status
.rates
[ts
.ts_final_idx
].count
++;
1869 if (unlikely(ts
.ts_status
)) {
1870 sc
->ll_stats
.dot11ACKFailureCount
++;
1871 if (ts
.ts_status
& AR5K_TXERR_FILT
)
1872 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1874 info
->flags
|= IEEE80211_TX_STAT_ACK
;
1875 info
->status
.ack_signal
= ts
.ts_rssi
;
1878 ieee80211_tx_status(sc
->hw
, skb
);
1879 sc
->tx_stats
[txq
->qnum
].count
++;
1881 spin_lock(&sc
->txbuflock
);
1882 sc
->tx_stats
[txq
->qnum
].len
--;
1883 list_move_tail(&bf
->list
, &sc
->txbuf
);
1885 spin_unlock(&sc
->txbuflock
);
1887 if (likely(list_empty(&txq
->q
)))
1889 spin_unlock(&txq
->lock
);
1890 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
1891 ieee80211_wake_queues(sc
->hw
);
1895 ath5k_tasklet_tx(unsigned long data
)
1897 struct ath5k_softc
*sc
= (void *)data
;
1899 ath5k_tx_processq(sc
, sc
->txq
);
1908 * Setup the beacon frame for transmit.
1911 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1913 struct sk_buff
*skb
= bf
->skb
;
1914 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1915 struct ath5k_hw
*ah
= sc
->ah
;
1916 struct ath5k_desc
*ds
;
1917 int ret
, antenna
= 0;
1920 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1922 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
1923 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
1924 (unsigned long long)bf
->skbaddr
);
1925 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
1926 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
1932 flags
= AR5K_TXDESC_NOACK
;
1933 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
1934 ds
->ds_link
= bf
->daddr
; /* self-linked */
1935 flags
|= AR5K_TXDESC_VEOL
;
1937 * Let hardware handle antenna switching if txantenna is not set
1942 * Switch antenna every 4 beacons if txantenna is not set
1943 * XXX assumes two antennas
1946 antenna
= sc
->bsent
& 4 ? 2 : 1;
1949 ds
->ds_data
= bf
->skbaddr
;
1950 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
1951 ieee80211_get_hdrlen_from_skb(skb
),
1952 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
1953 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
1954 1, AR5K_TXKEYIX_INVALID
,
1955 antenna
, flags
, 0, 0);
1961 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1966 * Transmit a beacon frame at SWBA. Dynamic updates to the
1967 * frame contents are done as needed and the slot time is
1968 * also adjusted based on current state.
1970 * this is usually called from interrupt context (ath5k_intr())
1971 * but also from ath5k_beacon_config() in IBSS mode which in turn
1972 * can be called from a tasklet and user context
1975 ath5k_beacon_send(struct ath5k_softc
*sc
)
1977 struct ath5k_buf
*bf
= sc
->bbuf
;
1978 struct ath5k_hw
*ah
= sc
->ah
;
1980 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
1982 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
1983 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
1984 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
1988 * Check if the previous beacon has gone out. If
1989 * not don't don't try to post another, skip this
1990 * period and wait for the next. Missed beacons
1991 * indicate a problem and should not occur. If we
1992 * miss too many consecutive beacons reset the device.
1994 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
1996 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1997 "missed %u consecutive beacons\n", sc
->bmisscount
);
1998 if (sc
->bmisscount
> 3) { /* NB: 3 is a guess */
1999 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2000 "stuck beacon time (%u missed)\n",
2002 tasklet_schedule(&sc
->restq
);
2006 if (unlikely(sc
->bmisscount
!= 0)) {
2007 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2008 "resume beacon xmit after %u misses\n",
2014 * Stop any current dma and put the new frame on the queue.
2015 * This should never fail since we check above that no frames
2016 * are still pending on the queue.
2018 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
2019 ATH5K_WARN(sc
, "beacon queue %u didn't stop?\n", sc
->bhalq
);
2020 /* NB: hw still stops DMA, so proceed */
2023 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
2024 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
2025 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2026 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2033 * ath5k_beacon_update_timers - update beacon timers
2035 * @sc: struct ath5k_softc pointer we are operating on
2036 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2037 * beacon timer update based on the current HW TSF.
2039 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2040 * of a received beacon or the current local hardware TSF and write it to the
2041 * beacon timer registers.
2043 * This is called in a variety of situations, e.g. when a beacon is received,
2044 * when a TSF update has been detected, but also when an new IBSS is created or
2045 * when we otherwise know we have to update the timers, but we keep it in this
2046 * function to have it all together in one place.
2049 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2051 struct ath5k_hw
*ah
= sc
->ah
;
2052 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2055 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2056 if (WARN_ON(!intval
))
2059 /* beacon TSF converted to TU */
2060 bc_tu
= TSF_TO_TU(bc_tsf
);
2062 /* current TSF converted to TU */
2063 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2064 hw_tu
= TSF_TO_TU(hw_tsf
);
2067 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2070 * no beacons received, called internally.
2071 * just need to refresh timers based on HW TSF.
2073 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2074 } else if (bc_tsf
== 0) {
2076 * no beacon received, probably called by ath5k_reset_tsf().
2077 * reset TSF to start with 0.
2080 intval
|= AR5K_BEACON_RESET_TSF
;
2081 } else if (bc_tsf
> hw_tsf
) {
2083 * beacon received, SW merge happend but HW TSF not yet updated.
2084 * not possible to reconfigure timers yet, but next time we
2085 * receive a beacon with the same BSSID, the hardware will
2086 * automatically update the TSF and then we need to reconfigure
2089 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2090 "need to wait for HW TSF sync\n");
2094 * most important case for beacon synchronization between STA.
2096 * beacon received and HW TSF has been already updated by HW.
2097 * update next TBTT based on the TSF of the beacon, but make
2098 * sure it is ahead of our local TSF timer.
2100 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2104 sc
->nexttbtt
= nexttbtt
;
2106 intval
|= AR5K_BEACON_ENA
;
2107 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2110 * debugging output last in order to preserve the time critical aspect
2114 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2115 "reconfigured timers based on HW TSF\n");
2116 else if (bc_tsf
== 0)
2117 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2118 "reset HW TSF and timers\n");
2120 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2121 "updated timers based on beacon TSF\n");
2123 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2124 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2125 (unsigned long long) bc_tsf
,
2126 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2127 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2128 intval
& AR5K_BEACON_PERIOD
,
2129 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2130 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2135 * ath5k_beacon_config - Configure the beacon queues and interrupts
2137 * @sc: struct ath5k_softc pointer we are operating on
2139 * When operating in station mode we want to receive a BMISS interrupt when we
2140 * stop seeing beacons from the AP we've associated with so we can look for
2141 * another AP to associate with.
2143 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2144 * interrupts to detect TSF updates only.
2147 ath5k_beacon_config(struct ath5k_softc
*sc
)
2149 struct ath5k_hw
*ah
= sc
->ah
;
2151 ath5k_hw_set_imr(ah
, 0);
2153 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2155 if (sc
->opmode
== NL80211_IFTYPE_STATION
) {
2156 sc
->imask
|= AR5K_INT_BMISS
;
2157 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
||
2158 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
||
2159 sc
->opmode
== NL80211_IFTYPE_AP
) {
2161 * In IBSS mode we use a self-linked tx descriptor and let the
2162 * hardware send the beacons automatically. We have to load it
2164 * We use the SWBA interrupt only to keep track of the beacon
2165 * timers in order to detect automatic TSF updates.
2167 ath5k_beaconq_config(sc
);
2169 sc
->imask
|= AR5K_INT_SWBA
;
2171 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2172 if (ath5k_hw_hasveol(ah
)) {
2173 spin_lock(&sc
->block
);
2174 ath5k_beacon_send(sc
);
2175 spin_unlock(&sc
->block
);
2178 ath5k_beacon_update_timers(sc
, -1);
2181 ath5k_hw_set_imr(ah
, sc
->imask
);
2185 /********************\
2186 * Interrupt handling *
2187 \********************/
2190 ath5k_init(struct ath5k_softc
*sc
, bool is_resume
)
2192 struct ath5k_hw
*ah
= sc
->ah
;
2195 mutex_lock(&sc
->lock
);
2197 if (is_resume
&& !test_bit(ATH_STAT_STARTED
, sc
->status
))
2200 __clear_bit(ATH_STAT_STARTED
, sc
->status
);
2202 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2205 * Stop anything previously setup. This is safe
2206 * no matter this is the first time through or not.
2208 ath5k_stop_locked(sc
);
2211 * The basic interface to setting the hardware in a good
2212 * state is ``reset''. On return the hardware is known to
2213 * be powered up and with interrupts disabled. This must
2214 * be followed by initialization of the appropriate bits
2215 * and then setup of the interrupt mask.
2217 sc
->curchan
= sc
->hw
->conf
.channel
;
2218 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2219 sc
->imask
= AR5K_INT_RXOK
| AR5K_INT_TXOK
| AR5K_INT_RXEOL
|
2220 AR5K_INT_RXORN
| AR5K_INT_FATAL
| AR5K_INT_GLOBAL
|
2222 ret
= ath5k_reset(sc
, false, false);
2227 * Reset the key cache since some parts do not reset the
2228 * contents on initial power up or resume from suspend.
2230 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
2231 ath5k_hw_reset_key(ah
, i
);
2233 __set_bit(ATH_STAT_STARTED
, sc
->status
);
2235 /* Set ack to be sent at low bit-rates */
2236 ath5k_hw_set_ack_bitrate_high(ah
, false);
2238 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2239 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2245 mutex_unlock(&sc
->lock
);
2250 ath5k_stop_locked(struct ath5k_softc
*sc
)
2252 struct ath5k_hw
*ah
= sc
->ah
;
2254 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2255 test_bit(ATH_STAT_INVALID
, sc
->status
));
2258 * Shutdown the hardware and driver:
2259 * stop output from above
2260 * disable interrupts
2262 * turn off the radio
2263 * clear transmit machinery
2264 * clear receive machinery
2265 * drain and release tx queues
2266 * reclaim beacon resources
2267 * power down hardware
2269 * Note that some of this work is not possible if the
2270 * hardware is gone (invalid).
2272 ieee80211_stop_queues(sc
->hw
);
2274 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2276 ath5k_hw_set_imr(ah
, 0);
2277 synchronize_irq(sc
->pdev
->irq
);
2279 ath5k_txq_cleanup(sc
);
2280 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2282 ath5k_hw_phy_disable(ah
);
2290 * Stop the device, grabbing the top-level lock to protect
2291 * against concurrent entry through ath5k_init (which can happen
2292 * if another thread does a system call and the thread doing the
2293 * stop is preempted).
2296 ath5k_stop_hw(struct ath5k_softc
*sc
, bool is_suspend
)
2300 mutex_lock(&sc
->lock
);
2301 ret
= ath5k_stop_locked(sc
);
2302 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2304 * Set the chip in full sleep mode. Note that we are
2305 * careful to do this only when bringing the interface
2306 * completely to a stop. When the chip is in this state
2307 * it must be carefully woken up or references to
2308 * registers in the PCI clock domain may freeze the bus
2309 * (and system). This varies by chip and is mostly an
2310 * issue with newer parts that go to sleep more quickly.
2312 if (sc
->ah
->ah_mac_srev
>= 0x78) {
2315 * don't put newer MAC revisions > 7.8 to sleep because
2316 * of the above mentioned problems
2318 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mac version > 7.8, "
2319 "not putting device to sleep\n");
2321 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2322 "putting device to full sleep\n");
2323 ath5k_hw_set_power(sc
->ah
, AR5K_PM_FULL_SLEEP
, true, 0);
2326 ath5k_txbuf_free(sc
, sc
->bbuf
);
2328 __clear_bit(ATH_STAT_STARTED
, sc
->status
);
2331 mutex_unlock(&sc
->lock
);
2333 del_timer_sync(&sc
->calib_tim
);
2334 tasklet_kill(&sc
->rxtq
);
2335 tasklet_kill(&sc
->txtq
);
2336 tasklet_kill(&sc
->restq
);
2342 ath5k_intr(int irq
, void *dev_id
)
2344 struct ath5k_softc
*sc
= dev_id
;
2345 struct ath5k_hw
*ah
= sc
->ah
;
2346 enum ath5k_int status
;
2347 unsigned int counter
= 1000;
2349 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2350 !ath5k_hw_is_intr_pending(ah
)))
2355 * Figure out the reason(s) for the interrupt. Note
2356 * that get_isr returns a pseudo-ISR that may include
2357 * bits we haven't explicitly enabled so we mask the
2358 * value to insure we only process bits we requested.
2360 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2361 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2363 status
&= sc
->imask
; /* discard unasked for bits */
2364 if (unlikely(status
& AR5K_INT_FATAL
)) {
2366 * Fatal errors are unrecoverable.
2367 * Typically these are caused by DMA errors.
2369 tasklet_schedule(&sc
->restq
);
2370 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2371 tasklet_schedule(&sc
->restq
);
2373 if (status
& AR5K_INT_SWBA
) {
2375 * Software beacon alert--time to send a beacon.
2376 * Handle beacon transmission directly; deferring
2377 * this is too slow to meet timing constraints
2380 * In IBSS mode we use this interrupt just to
2381 * keep track of the next TBTT (target beacon
2382 * transmission time) in order to detect wether
2383 * automatic TSF updates happened.
2385 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2386 /* XXX: only if VEOL suppported */
2387 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2388 sc
->nexttbtt
+= sc
->bintval
;
2389 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2390 "SWBA nexttbtt: %x hw_tu: %x "
2394 (unsigned long long) tsf
);
2396 spin_lock(&sc
->block
);
2397 ath5k_beacon_send(sc
);
2398 spin_unlock(&sc
->block
);
2401 if (status
& AR5K_INT_RXEOL
) {
2403 * NB: the hardware should re-read the link when
2404 * RXE bit is written, but it doesn't work at
2405 * least on older hardware revs.
2409 if (status
& AR5K_INT_TXURN
) {
2410 /* bump tx trigger level */
2411 ath5k_hw_update_tx_triglevel(ah
, true);
2413 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2414 tasklet_schedule(&sc
->rxtq
);
2415 if (status
& (AR5K_INT_TXOK
| AR5K_INT_TXDESC
2416 | AR5K_INT_TXERR
| AR5K_INT_TXEOL
))
2417 tasklet_schedule(&sc
->txtq
);
2418 if (status
& AR5K_INT_BMISS
) {
2420 if (status
& AR5K_INT_MIB
) {
2422 * These stats are also used for ANI i think
2423 * so how about updating them more often ?
2425 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2428 } while (ath5k_hw_is_intr_pending(ah
) && counter
-- > 0);
2430 if (unlikely(!counter
))
2431 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2437 ath5k_tasklet_reset(unsigned long data
)
2439 struct ath5k_softc
*sc
= (void *)data
;
2441 ath5k_reset_wake(sc
);
2445 * Periodically recalibrate the PHY to account
2446 * for temperature/environment changes.
2449 ath5k_calibrate(unsigned long data
)
2451 struct ath5k_softc
*sc
= (void *)data
;
2452 struct ath5k_hw
*ah
= sc
->ah
;
2454 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2455 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2456 sc
->curchan
->hw_value
);
2458 if (ath5k_hw_get_rf_gain(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2460 * Rfgain is out of bounds, reset the chip
2461 * to load new gain values.
2463 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2464 ath5k_reset_wake(sc
);
2466 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2467 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2468 ieee80211_frequency_to_channel(
2469 sc
->curchan
->center_freq
));
2471 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2472 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2482 ath5k_led_enable(struct ath5k_softc
*sc
)
2484 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
2485 ath5k_hw_set_gpio_output(sc
->ah
, sc
->led_pin
);
2491 ath5k_led_on(struct ath5k_softc
*sc
)
2493 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2495 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, sc
->led_on
);
2499 ath5k_led_off(struct ath5k_softc
*sc
)
2501 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2503 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, !sc
->led_on
);
2507 ath5k_led_brightness_set(struct led_classdev
*led_dev
,
2508 enum led_brightness brightness
)
2510 struct ath5k_led
*led
= container_of(led_dev
, struct ath5k_led
,
2513 if (brightness
== LED_OFF
)
2514 ath5k_led_off(led
->sc
);
2516 ath5k_led_on(led
->sc
);
2520 ath5k_register_led(struct ath5k_softc
*sc
, struct ath5k_led
*led
,
2521 const char *name
, char *trigger
)
2526 strncpy(led
->name
, name
, sizeof(led
->name
));
2527 led
->led_dev
.name
= led
->name
;
2528 led
->led_dev
.default_trigger
= trigger
;
2529 led
->led_dev
.brightness_set
= ath5k_led_brightness_set
;
2531 err
= led_classdev_register(&sc
->pdev
->dev
, &led
->led_dev
);
2533 ATH5K_WARN(sc
, "could not register LED %s\n", name
);
2540 ath5k_unregister_led(struct ath5k_led
*led
)
2544 led_classdev_unregister(&led
->led_dev
);
2545 ath5k_led_off(led
->sc
);
2550 ath5k_unregister_leds(struct ath5k_softc
*sc
)
2552 ath5k_unregister_led(&sc
->rx_led
);
2553 ath5k_unregister_led(&sc
->tx_led
);
2558 ath5k_init_leds(struct ath5k_softc
*sc
)
2561 struct ieee80211_hw
*hw
= sc
->hw
;
2562 struct pci_dev
*pdev
= sc
->pdev
;
2563 char name
[ATH5K_LED_MAX_NAME_LEN
+ 1];
2566 * Auto-enable soft led processing for IBM cards and for
2567 * 5211 minipci cards.
2569 if (pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5212_IBM
||
2570 pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5211
) {
2571 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2573 sc
->led_on
= 0; /* active low */
2575 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2576 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
) {
2577 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
2579 sc
->led_on
= 1; /* active high */
2581 if (!test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
2584 ath5k_led_enable(sc
);
2586 snprintf(name
, sizeof(name
), "ath5k-%s::rx", wiphy_name(hw
->wiphy
));
2587 ret
= ath5k_register_led(sc
, &sc
->rx_led
, name
,
2588 ieee80211_get_rx_led_name(hw
));
2592 snprintf(name
, sizeof(name
), "ath5k-%s::tx", wiphy_name(hw
->wiphy
));
2593 ret
= ath5k_register_led(sc
, &sc
->tx_led
, name
,
2594 ieee80211_get_tx_led_name(hw
));
2600 /********************\
2601 * Mac80211 functions *
2602 \********************/
2605 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2607 struct ath5k_softc
*sc
= hw
->priv
;
2608 struct ath5k_buf
*bf
;
2609 unsigned long flags
;
2613 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2615 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2616 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2619 * the hardware expects the header padded to 4 byte boundaries
2620 * if this is not the case we add the padding after the header
2622 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2625 if (skb_headroom(skb
) < pad
) {
2626 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2627 " headroom to pad %d\n", hdrlen
, pad
);
2631 memmove(skb
->data
, skb
->data
+pad
, hdrlen
);
2634 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2635 if (list_empty(&sc
->txbuf
)) {
2636 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2637 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2638 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
2641 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2642 list_del(&bf
->list
);
2644 if (list_empty(&sc
->txbuf
))
2645 ieee80211_stop_queues(hw
);
2646 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2650 if (ath5k_txbuf_setup(sc
, bf
)) {
2652 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2653 list_add_tail(&bf
->list
, &sc
->txbuf
);
2655 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2656 dev_kfree_skb_any(skb
);
2664 ath5k_reset(struct ath5k_softc
*sc
, bool stop
, bool change_channel
)
2666 struct ath5k_hw
*ah
= sc
->ah
;
2669 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2672 ath5k_hw_set_imr(ah
, 0);
2673 ath5k_txq_cleanup(sc
);
2676 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
2678 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2683 * This is needed only to setup initial state
2684 * but it's best done after a reset.
2686 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2688 ret
= ath5k_rx_start(sc
);
2690 ATH5K_ERR(sc
, "can't start recv logic\n");
2695 * Change channels and update the h/w rate map if we're switching;
2696 * e.g. 11a to 11b/g.
2698 * We may be doing a reset in response to an ioctl that changes the
2699 * channel so update any state that might change as a result.
2703 /* ath5k_chan_change(sc, c); */
2705 ath5k_beacon_config(sc
);
2706 /* intrs are enabled by ath5k_beacon_config */
2714 ath5k_reset_wake(struct ath5k_softc
*sc
)
2718 ret
= ath5k_reset(sc
, true, true);
2720 ieee80211_wake_queues(sc
->hw
);
2725 static int ath5k_start(struct ieee80211_hw
*hw
)
2727 return ath5k_init(hw
->priv
, false);
2730 static void ath5k_stop(struct ieee80211_hw
*hw
)
2732 ath5k_stop_hw(hw
->priv
, false);
2735 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2736 struct ieee80211_if_init_conf
*conf
)
2738 struct ath5k_softc
*sc
= hw
->priv
;
2741 mutex_lock(&sc
->lock
);
2747 sc
->vif
= conf
->vif
;
2749 switch (conf
->type
) {
2750 case NL80211_IFTYPE_AP
:
2751 case NL80211_IFTYPE_STATION
:
2752 case NL80211_IFTYPE_ADHOC
:
2753 case NL80211_IFTYPE_MESH_POINT
:
2754 case NL80211_IFTYPE_MONITOR
:
2755 sc
->opmode
= conf
->type
;
2762 /* Set to a reasonable value. Note that this will
2763 * be set to mac80211's value at ath5k_config(). */
2768 mutex_unlock(&sc
->lock
);
2773 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2774 struct ieee80211_if_init_conf
*conf
)
2776 struct ath5k_softc
*sc
= hw
->priv
;
2778 mutex_lock(&sc
->lock
);
2779 if (sc
->vif
!= conf
->vif
)
2784 mutex_unlock(&sc
->lock
);
2788 * TODO: Phy disable/diversity etc
2791 ath5k_config(struct ieee80211_hw
*hw
, u32 changed
)
2793 struct ath5k_softc
*sc
= hw
->priv
;
2794 struct ieee80211_conf
*conf
= &hw
->conf
;
2796 sc
->bintval
= conf
->beacon_int
;
2797 sc
->power_level
= conf
->power_level
;
2799 return ath5k_chan_set(sc
, conf
->channel
);
2803 ath5k_config_interface(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2804 struct ieee80211_if_conf
*conf
)
2806 struct ath5k_softc
*sc
= hw
->priv
;
2807 struct ath5k_hw
*ah
= sc
->ah
;
2810 mutex_lock(&sc
->lock
);
2811 if (sc
->vif
!= vif
) {
2815 if (conf
->changed
& IEEE80211_IFCC_BSSID
&& conf
->bssid
) {
2816 /* Cache for later use during resets */
2817 memcpy(ah
->ah_bssid
, conf
->bssid
, ETH_ALEN
);
2818 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2819 * a clean way of letting us retrieve this yet. */
2820 ath5k_hw_set_associd(ah
, ah
->ah_bssid
, 0);
2823 if (conf
->changed
& IEEE80211_IFCC_BEACON
&&
2824 (vif
->type
== NL80211_IFTYPE_ADHOC
||
2825 vif
->type
== NL80211_IFTYPE_MESH_POINT
||
2826 vif
->type
== NL80211_IFTYPE_AP
)) {
2827 struct sk_buff
*beacon
= ieee80211_beacon_get(hw
, vif
);
2832 ath5k_beacon_update(sc
, beacon
);
2834 mutex_unlock(&sc
->lock
);
2836 return ath5k_reset_wake(sc
);
2838 mutex_unlock(&sc
->lock
);
2842 #define SUPPORTED_FIF_FLAGS \
2843 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2844 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2845 FIF_BCN_PRBRESP_PROMISC
2847 * o always accept unicast, broadcast, and multicast traffic
2848 * o multicast traffic for all BSSIDs will be enabled if mac80211
2850 * o maintain current state of phy ofdm or phy cck error reception.
2851 * If the hardware detects any of these type of errors then
2852 * ath5k_hw_get_rx_filter() will pass to us the respective
2853 * hardware filters to be able to receive these type of frames.
2854 * o probe request frames are accepted only when operating in
2855 * hostap, adhoc, or monitor modes
2856 * o enable promiscuous mode according to the interface state
2858 * - when operating in adhoc mode so the 802.11 layer creates
2859 * node table entries for peers,
2860 * - when operating in station mode for collecting rssi data when
2861 * the station is otherwise quiet, or
2864 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2865 unsigned int changed_flags
,
2866 unsigned int *new_flags
,
2867 int mc_count
, struct dev_mc_list
*mclist
)
2869 struct ath5k_softc
*sc
= hw
->priv
;
2870 struct ath5k_hw
*ah
= sc
->ah
;
2871 u32 mfilt
[2], val
, rfilt
;
2878 /* Only deal with supported flags */
2879 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2880 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2882 /* If HW detects any phy or radar errors, leave those filters on.
2883 * Also, always enable Unicast, Broadcasts and Multicast
2884 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2885 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2886 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2887 AR5K_RX_FILTER_MCAST
);
2889 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2890 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2891 rfilt
|= AR5K_RX_FILTER_PROM
;
2892 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2894 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
2898 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2899 if (*new_flags
& FIF_ALLMULTI
) {
2903 for (i
= 0; i
< mc_count
; i
++) {
2906 /* calculate XOR of eight 6-bit values */
2907 val
= get_unaligned_le32(mclist
->dmi_addr
+ 0);
2908 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2909 val
= get_unaligned_le32(mclist
->dmi_addr
+ 3);
2910 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2912 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2913 /* XXX: we might be able to just do this instead,
2914 * but not sure, needs testing, if we do use this we'd
2915 * neet to inform below to not reset the mcast */
2916 /* ath5k_hw_set_mcast_filterindex(ah,
2917 * mclist->dmi_addr[5]); */
2918 mclist
= mclist
->next
;
2922 /* This is the best we can do */
2923 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
2924 rfilt
|= AR5K_RX_FILTER_PHYERR
;
2926 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2927 * and probes for any BSSID, this needs testing */
2928 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
2929 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
2931 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2932 * set we should only pass on control frames for this
2933 * station. This needs testing. I believe right now this
2934 * enables *all* control frames, which is OK.. but
2935 * but we should see if we can improve on granularity */
2936 if (*new_flags
& FIF_CONTROL
)
2937 rfilt
|= AR5K_RX_FILTER_CONTROL
;
2939 /* Additional settings per mode -- this is per ath5k */
2941 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2943 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2944 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2945 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2946 if (sc
->opmode
!= NL80211_IFTYPE_STATION
)
2947 rfilt
|= AR5K_RX_FILTER_PROBEREQ
;
2948 if (sc
->opmode
!= NL80211_IFTYPE_AP
&&
2949 sc
->opmode
!= NL80211_IFTYPE_MESH_POINT
&&
2950 test_bit(ATH_STAT_PROMISC
, sc
->status
))
2951 rfilt
|= AR5K_RX_FILTER_PROM
;
2952 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
2953 rfilt
|= AR5K_RX_FILTER_BEACON
;
2954 if (sc
->opmode
== NL80211_IFTYPE_MESH_POINT
)
2955 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2956 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2959 ath5k_hw_set_rx_filter(ah
, rfilt
);
2961 /* Set multicast bits */
2962 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
2963 /* Set the cached hw filter flags, this will alter actually
2965 sc
->filter_flags
= rfilt
;
2969 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
2970 const u8
*local_addr
, const u8
*addr
,
2971 struct ieee80211_key_conf
*key
)
2973 struct ath5k_softc
*sc
= hw
->priv
;
2978 /* XXX: fix hardware encryption, its not working. For now
2979 * allow software encryption */
2989 mutex_lock(&sc
->lock
);
2993 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
, addr
);
2995 ATH5K_ERR(sc
, "can't set the key\n");
2998 __set_bit(key
->keyidx
, sc
->keymap
);
2999 key
->hw_key_idx
= key
->keyidx
;
3002 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
3003 __clear_bit(key
->keyidx
, sc
->keymap
);
3012 mutex_unlock(&sc
->lock
);
3017 ath5k_get_stats(struct ieee80211_hw
*hw
,
3018 struct ieee80211_low_level_stats
*stats
)
3020 struct ath5k_softc
*sc
= hw
->priv
;
3021 struct ath5k_hw
*ah
= sc
->ah
;
3024 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
3026 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
3032 ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
3033 struct ieee80211_tx_queue_stats
*stats
)
3035 struct ath5k_softc
*sc
= hw
->priv
;
3037 memcpy(stats
, &sc
->tx_stats
, sizeof(sc
->tx_stats
));
3043 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3045 struct ath5k_softc
*sc
= hw
->priv
;
3047 return ath5k_hw_get_tsf64(sc
->ah
);
3051 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3053 struct ath5k_softc
*sc
= hw
->priv
;
3056 * in IBSS mode we need to update the beacon timers too.
3057 * this will also reset the TSF if we call it with 0
3059 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
3060 ath5k_beacon_update_timers(sc
, 0);
3062 ath5k_hw_reset_tsf(sc
->ah
);
3066 ath5k_beacon_update(struct ath5k_softc
*sc
, struct sk_buff
*skb
)
3068 unsigned long flags
;
3071 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3073 spin_lock_irqsave(&sc
->block
, flags
);
3074 ath5k_txbuf_free(sc
, sc
->bbuf
);
3075 sc
->bbuf
->skb
= skb
;
3076 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
);
3078 sc
->bbuf
->skb
= NULL
;
3079 spin_unlock_irqrestore(&sc
->block
, flags
);
3081 ath5k_beacon_config(sc
);