2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
47 #include <linux/netdevice.h>
48 #include <linux/cache.h>
49 #include <linux/pci.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
53 #include <net/ieee80211_radiotap.h>
55 #include <asm/unaligned.h>
66 static int ath5k_calinterval
= 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
74 MODULE_AUTHOR("Jiri Slaby");
75 MODULE_AUTHOR("Nick Kossifidis");
76 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
77 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
78 MODULE_LICENSE("Dual BSD/GPL");
79 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
83 static struct pci_device_id ath5k_pci_id_table
[] __devinitdata
= {
84 { PCI_VDEVICE(ATHEROS
, 0x0207), .driver_data
= AR5K_AR5210
}, /* 5210 early */
85 { PCI_VDEVICE(ATHEROS
, 0x0007), .driver_data
= AR5K_AR5210
}, /* 5210 */
86 { PCI_VDEVICE(ATHEROS
, 0x0011), .driver_data
= AR5K_AR5211
}, /* 5311 - this is on AHB bus !*/
87 { PCI_VDEVICE(ATHEROS
, 0x0012), .driver_data
= AR5K_AR5211
}, /* 5211 */
88 { PCI_VDEVICE(ATHEROS
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 5212 */
89 { PCI_VDEVICE(3COM_2
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 5212 */
90 { PCI_VDEVICE(3COM
, 0x0013), .driver_data
= AR5K_AR5212
}, /* 3com 3CRDAG675 5212 */
91 { PCI_VDEVICE(ATHEROS
, 0x1014), .driver_data
= AR5K_AR5212
}, /* IBM minipci 5212 */
92 { PCI_VDEVICE(ATHEROS
, 0x0014), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS
, 0x0015), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS
, 0x0016), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS
, 0x0017), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS
, 0x0018), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS
, 0x0019), .driver_data
= AR5K_AR5212
}, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS
, 0x001a), .driver_data
= AR5K_AR5212
}, /* 2413 Griffin-lite */
99 { PCI_VDEVICE(ATHEROS
, 0x001b), .driver_data
= AR5K_AR5212
}, /* 5413 Eagle */
100 { PCI_VDEVICE(ATHEROS
, 0x001c), .driver_data
= AR5K_AR5212
}, /* 5424 Condor (PCI-E)*/
101 { PCI_VDEVICE(ATHEROS
, 0x0023), .driver_data
= AR5K_AR5212
}, /* 5416 */
102 { PCI_VDEVICE(ATHEROS
, 0x0024), .driver_data
= AR5K_AR5212
}, /* 5418 */
105 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
108 static struct ath5k_srev_name srev_names
[] = {
109 { "5210", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5210
},
110 { "5311", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311
},
111 { "5311A", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311A
},
112 { "5311B", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5311B
},
113 { "5211", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5211
},
114 { "5212", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5212
},
115 { "5213", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5213
},
116 { "5213A", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5213A
},
117 { "2413", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2413
},
118 { "2414", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2414
},
119 { "2424", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2424
},
120 { "5424", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5424
},
121 { "5413", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5413
},
122 { "5414", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5414
},
123 { "5416", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5416
},
124 { "5418", AR5K_VERSION_VER
, AR5K_SREV_VER_AR5418
},
125 { "2425", AR5K_VERSION_VER
, AR5K_SREV_VER_AR2425
},
126 { "xxxxx", AR5K_VERSION_VER
, AR5K_SREV_UNKNOWN
},
127 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
128 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
129 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
130 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
131 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
132 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
133 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
134 { "SChip", AR5K_VERSION_RAD
, AR5K_SREV_RAD_SC0
},
135 { "SChip", AR5K_VERSION_RAD
, AR5K_SREV_RAD_SC1
},
136 { "SChip", AR5K_VERSION_RAD
, AR5K_SREV_RAD_SC2
},
137 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
138 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
142 * Prototypes - PCI stack related functions
144 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
145 const struct pci_device_id
*id
);
146 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
148 static int ath5k_pci_suspend(struct pci_dev
*pdev
,
150 static int ath5k_pci_resume(struct pci_dev
*pdev
);
152 #define ath5k_pci_suspend NULL
153 #define ath5k_pci_resume NULL
154 #endif /* CONFIG_PM */
156 static struct pci_driver ath5k_pci_driver
= {
158 .id_table
= ath5k_pci_id_table
,
159 .probe
= ath5k_pci_probe
,
160 .remove
= __devexit_p(ath5k_pci_remove
),
161 .suspend
= ath5k_pci_suspend
,
162 .resume
= ath5k_pci_resume
,
168 * Prototypes - MAC 802.11 stack related functions
170 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
171 struct ieee80211_tx_control
*ctl
);
172 static int ath5k_reset(struct ieee80211_hw
*hw
);
173 static int ath5k_start(struct ieee80211_hw
*hw
);
174 static void ath5k_stop(struct ieee80211_hw
*hw
);
175 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
176 struct ieee80211_if_init_conf
*conf
);
177 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
178 struct ieee80211_if_init_conf
*conf
);
179 static int ath5k_config(struct ieee80211_hw
*hw
,
180 struct ieee80211_conf
*conf
);
181 static int ath5k_config_interface(struct ieee80211_hw
*hw
,
182 struct ieee80211_vif
*vif
,
183 struct ieee80211_if_conf
*conf
);
184 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
185 unsigned int changed_flags
,
186 unsigned int *new_flags
,
187 int mc_count
, struct dev_mc_list
*mclist
);
188 static int ath5k_set_key(struct ieee80211_hw
*hw
,
189 enum set_key_cmd cmd
,
190 const u8
*local_addr
, const u8
*addr
,
191 struct ieee80211_key_conf
*key
);
192 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
193 struct ieee80211_low_level_stats
*stats
);
194 static int ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
195 struct ieee80211_tx_queue_stats
*stats
);
196 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
197 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
198 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
200 struct ieee80211_tx_control
*ctl
);
202 static struct ieee80211_ops ath5k_hw_ops
= {
204 .start
= ath5k_start
,
206 .add_interface
= ath5k_add_interface
,
207 .remove_interface
= ath5k_remove_interface
,
208 .config
= ath5k_config
,
209 .config_interface
= ath5k_config_interface
,
210 .configure_filter
= ath5k_configure_filter
,
211 .set_key
= ath5k_set_key
,
212 .get_stats
= ath5k_get_stats
,
214 .get_tx_stats
= ath5k_get_tx_stats
,
215 .get_tsf
= ath5k_get_tsf
,
216 .reset_tsf
= ath5k_reset_tsf
,
217 .beacon_update
= ath5k_beacon_update
,
221 * Prototypes - Internal functions
224 static int ath5k_attach(struct pci_dev
*pdev
,
225 struct ieee80211_hw
*hw
);
226 static void ath5k_detach(struct pci_dev
*pdev
,
227 struct ieee80211_hw
*hw
);
228 /* Channel/mode setup */
229 static inline short ath5k_ieee2mhz(short chan
);
230 static unsigned int ath5k_copy_rates(struct ieee80211_rate
*rates
,
231 const struct ath5k_rate_table
*rt
,
233 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
234 struct ieee80211_channel
*channels
,
237 static int ath5k_getchannels(struct ieee80211_hw
*hw
);
238 static int ath5k_chan_set(struct ath5k_softc
*sc
,
239 struct ieee80211_channel
*chan
);
240 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
242 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
243 static void ath5k_set_total_hw_rates(struct ath5k_softc
*sc
);
245 /* Descriptor setup */
246 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
247 struct pci_dev
*pdev
);
248 static void ath5k_desc_free(struct ath5k_softc
*sc
,
249 struct pci_dev
*pdev
);
251 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
252 struct ath5k_buf
*bf
);
253 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
254 struct ath5k_buf
*bf
,
255 struct ieee80211_tx_control
*ctl
);
257 static inline void ath5k_txbuf_free(struct ath5k_softc
*sc
,
258 struct ath5k_buf
*bf
)
263 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
265 dev_kfree_skb(bf
->skb
);
270 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
271 int qtype
, int subtype
);
272 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
273 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
274 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
275 struct ath5k_txq
*txq
);
276 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
277 static void ath5k_txq_release(struct ath5k_softc
*sc
);
279 static int ath5k_rx_start(struct ath5k_softc
*sc
);
280 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
281 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
282 struct ath5k_desc
*ds
,
284 struct ath5k_rx_status
*rs
);
285 static void ath5k_tasklet_rx(unsigned long data
);
287 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
288 struct ath5k_txq
*txq
);
289 static void ath5k_tasklet_tx(unsigned long data
);
290 /* Beacon handling */
291 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
292 struct ath5k_buf
*bf
,
293 struct ieee80211_tx_control
*ctl
);
294 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
295 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
296 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
298 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
300 u64 tsf
= ath5k_hw_get_tsf64(ah
);
302 if ((tsf
& 0x7fff) < rstamp
)
305 return (tsf
& ~0x7fff) | rstamp
;
308 /* Interrupt handling */
309 static int ath5k_init(struct ath5k_softc
*sc
);
310 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
311 static int ath5k_stop_hw(struct ath5k_softc
*sc
);
312 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
313 static void ath5k_tasklet_reset(unsigned long data
);
315 static void ath5k_calibrate(unsigned long data
);
317 static void ath5k_led_off(unsigned long data
);
318 static void ath5k_led_blink(struct ath5k_softc
*sc
,
321 static void ath5k_led_event(struct ath5k_softc
*sc
,
326 * Module init/exit functions
335 ret
= pci_register_driver(&ath5k_pci_driver
);
337 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
347 pci_unregister_driver(&ath5k_pci_driver
);
349 ath5k_debug_finish();
352 module_init(init_ath5k_pci
);
353 module_exit(exit_ath5k_pci
);
356 /********************\
357 * PCI Initialization *
358 \********************/
361 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
363 const char *name
= "xxxxx";
366 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
367 if (srev_names
[i
].sr_type
!= type
)
369 if ((val
& 0xff) < srev_names
[i
+ 1].sr_val
) {
370 name
= srev_names
[i
].sr_name
;
379 ath5k_pci_probe(struct pci_dev
*pdev
,
380 const struct pci_device_id
*id
)
383 struct ath5k_softc
*sc
;
384 struct ieee80211_hw
*hw
;
388 ret
= pci_enable_device(pdev
);
390 dev_err(&pdev
->dev
, "can't enable device\n");
394 /* XXX 32-bit addressing only */
395 ret
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
397 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
402 * Cache line size is used to size and align various
403 * structures used to communicate with the hardware.
405 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
408 * Linux 2.4.18 (at least) writes the cache line size
409 * register as a 16-bit wide register which is wrong.
410 * We must have this setup properly for rx buffer
411 * DMA to work so force a reasonable value here if it
414 csz
= L1_CACHE_BYTES
/ sizeof(u32
);
415 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
418 * The default setting of latency timer yields poor results,
419 * set it to the value used by other systems. It may be worth
420 * tweaking this setting more.
422 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
424 /* Enable bus mastering */
425 pci_set_master(pdev
);
428 * Disable the RETRY_TIMEOUT register (0x41) to keep
429 * PCI Tx retries from interfering with C3 CPU state.
431 pci_write_config_byte(pdev
, 0x41, 0);
433 ret
= pci_request_region(pdev
, 0, "ath5k");
435 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
439 mem
= pci_iomap(pdev
, 0, 0);
441 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
447 * Allocate hw (mac80211 main struct)
448 * and hw->priv (driver private data)
450 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
452 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
457 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
459 /* Initialize driver private data */
460 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
461 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
462 IEEE80211_HW_SIGNAL_DBM
|
463 IEEE80211_HW_NOISE_DBM
;
464 hw
->extra_tx_headroom
= 2;
465 hw
->channel_change_time
= 5000;
470 ath5k_debug_init_device(sc
);
473 * Mark the device as detached to avoid processing
474 * interrupts until setup is complete.
476 __set_bit(ATH_STAT_INVALID
, sc
->status
);
478 sc
->iobase
= mem
; /* So we can unmap it on detach */
479 sc
->cachelsz
= csz
* sizeof(u32
); /* convert to bytes */
480 sc
->opmode
= IEEE80211_IF_TYPE_STA
;
481 mutex_init(&sc
->lock
);
482 spin_lock_init(&sc
->rxbuflock
);
483 spin_lock_init(&sc
->txbuflock
);
485 /* Set private data */
486 pci_set_drvdata(pdev
, hw
);
488 /* Enable msi for devices that support it */
489 pci_enable_msi(pdev
);
491 /* Setup interrupt handler */
492 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
494 ATH5K_ERR(sc
, "request_irq failed\n");
498 /* Initialize device */
499 sc
->ah
= ath5k_hw_attach(sc
, id
->driver_data
);
500 if (IS_ERR(sc
->ah
)) {
501 ret
= PTR_ERR(sc
->ah
);
505 /* Finish private driver data initialization */
506 ret
= ath5k_attach(pdev
, hw
);
510 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
511 ath5k_chip_name(AR5K_VERSION_VER
,sc
->ah
->ah_mac_srev
),
513 sc
->ah
->ah_phy_revision
);
515 if (!sc
->ah
->ah_single_chip
) {
516 /* Single chip radio (!RF5111) */
517 if (sc
->ah
->ah_radio_5ghz_revision
&&
518 !sc
->ah
->ah_radio_2ghz_revision
) {
519 /* No 5GHz support -> report 2GHz radio */
520 if (!test_bit(AR5K_MODE_11A
,
521 sc
->ah
->ah_capabilities
.cap_mode
)) {
522 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
523 ath5k_chip_name(AR5K_VERSION_RAD
,
524 sc
->ah
->ah_radio_5ghz_revision
),
525 sc
->ah
->ah_radio_5ghz_revision
);
526 /* No 2GHz support (5110 and some
527 * 5Ghz only cards) -> report 5Ghz radio */
528 } else if (!test_bit(AR5K_MODE_11B
,
529 sc
->ah
->ah_capabilities
.cap_mode
)) {
530 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
531 ath5k_chip_name(AR5K_VERSION_RAD
,
532 sc
->ah
->ah_radio_5ghz_revision
),
533 sc
->ah
->ah_radio_5ghz_revision
);
534 /* Multiband radio */
536 ATH5K_INFO(sc
, "RF%s multiband radio found"
538 ath5k_chip_name(AR5K_VERSION_RAD
,
539 sc
->ah
->ah_radio_5ghz_revision
),
540 sc
->ah
->ah_radio_5ghz_revision
);
543 /* Multi chip radio (RF5111 - RF2111) ->
544 * report both 2GHz/5GHz radios */
545 else if (sc
->ah
->ah_radio_5ghz_revision
&&
546 sc
->ah
->ah_radio_2ghz_revision
){
547 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
548 ath5k_chip_name(AR5K_VERSION_RAD
,
549 sc
->ah
->ah_radio_5ghz_revision
),
550 sc
->ah
->ah_radio_5ghz_revision
);
551 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
552 ath5k_chip_name(AR5K_VERSION_RAD
,
553 sc
->ah
->ah_radio_2ghz_revision
),
554 sc
->ah
->ah_radio_2ghz_revision
);
559 /* ready to process interrupts */
560 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
564 ath5k_hw_detach(sc
->ah
);
566 free_irq(pdev
->irq
, sc
);
568 pci_disable_msi(pdev
);
569 ieee80211_free_hw(hw
);
571 pci_iounmap(pdev
, mem
);
573 pci_release_region(pdev
, 0);
575 pci_disable_device(pdev
);
580 static void __devexit
581 ath5k_pci_remove(struct pci_dev
*pdev
)
583 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
584 struct ath5k_softc
*sc
= hw
->priv
;
586 ath5k_debug_finish_device(sc
);
587 ath5k_detach(pdev
, hw
);
588 ath5k_hw_detach(sc
->ah
);
589 free_irq(pdev
->irq
, sc
);
590 pci_disable_msi(pdev
);
591 pci_iounmap(pdev
, sc
->iobase
);
592 pci_release_region(pdev
, 0);
593 pci_disable_device(pdev
);
594 ieee80211_free_hw(hw
);
599 ath5k_pci_suspend(struct pci_dev
*pdev
, pm_message_t state
)
601 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
602 struct ath5k_softc
*sc
= hw
->priv
;
604 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
))
605 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, 1);
608 pci_save_state(pdev
);
609 pci_disable_device(pdev
);
610 pci_set_power_state(pdev
, PCI_D3hot
);
616 ath5k_pci_resume(struct pci_dev
*pdev
)
618 struct ieee80211_hw
*hw
= pci_get_drvdata(pdev
);
619 struct ath5k_softc
*sc
= hw
->priv
;
620 struct ath5k_hw
*ah
= sc
->ah
;
623 err
= pci_set_power_state(pdev
, PCI_D0
);
627 err
= pci_enable_device(pdev
);
631 pci_restore_state(pdev
);
633 * Suspend/Resume resets the PCI configuration space, so we have to
634 * re-disable the RETRY_TIMEOUT register (0x41) to keep
635 * PCI Tx retries from interfering with C3 CPU state
637 pci_write_config_byte(pdev
, 0x41, 0);
640 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
641 ath5k_hw_set_gpio_output(ah
, sc
->led_pin
);
642 ath5k_hw_set_gpio(ah
, sc
->led_pin
, 0);
646 * Reset the key cache since some parts do not
647 * reset the contents on initial power up or resume.
649 * FIXME: This may need to be revisited when mac80211 becomes
650 * aware of suspend/resume.
652 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
653 ath5k_hw_reset_key(ah
, i
);
657 #endif /* CONFIG_PM */
661 /***********************\
662 * Driver Initialization *
663 \***********************/
666 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
668 struct ath5k_softc
*sc
= hw
->priv
;
669 struct ath5k_hw
*ah
= sc
->ah
;
674 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
677 * Check if the MAC has multi-rate retry support.
678 * We do this by trying to setup a fake extended
679 * descriptor. MAC's that don't have support will
680 * return false w/o doing anything. MAC's that do
681 * support it will return true w/o doing anything.
683 ret
= ah
->ah_setup_xtx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
687 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
690 * Reset the key cache since some parts do not
691 * reset the contents on initial power up.
693 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
694 ath5k_hw_reset_key(ah
, i
);
697 * Collect the channel list. The 802.11 layer
698 * is resposible for filtering this list based
699 * on settings like the phy mode and regulatory
700 * domain restrictions.
702 ret
= ath5k_getchannels(hw
);
704 ATH5K_ERR(sc
, "can't get channels\n");
708 /* Set *_rates so we can map hw rate index */
709 ath5k_set_total_hw_rates(sc
);
711 /* NB: setup here so ath5k_rate_update is happy */
712 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
713 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
715 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
718 * Allocate tx+rx descriptors and populate the lists.
720 ret
= ath5k_desc_alloc(sc
, pdev
);
722 ATH5K_ERR(sc
, "can't allocate descriptors\n");
727 * Allocate hardware transmit queues: one queue for
728 * beacon frames and one data queue for each QoS
729 * priority. Note that hw functions handle reseting
730 * these queues at the needed time.
732 ret
= ath5k_beaconq_setup(ah
);
734 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
739 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
740 if (IS_ERR(sc
->txq
)) {
741 ATH5K_ERR(sc
, "can't setup xmit queue\n");
742 ret
= PTR_ERR(sc
->txq
);
746 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
747 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
748 tasklet_init(&sc
->restq
, ath5k_tasklet_reset
, (unsigned long)sc
);
749 setup_timer(&sc
->calib_tim
, ath5k_calibrate
, (unsigned long)sc
);
750 setup_timer(&sc
->led_tim
, ath5k_led_off
, (unsigned long)sc
);
752 sc
->led_on
= 0; /* low true */
754 * Auto-enable soft led processing for IBM cards and for
755 * 5211 minipci cards.
757 if (pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5212_IBM
||
758 pdev
->device
== PCI_DEVICE_ID_ATHEROS_AR5211
) {
759 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
762 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
763 if (pdev
->subsystem_vendor
== PCI_VENDOR_ID_COMPAQ
) {
764 __set_bit(ATH_STAT_LEDSOFT
, sc
->status
);
767 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
768 ath5k_hw_set_gpio_output(ah
, sc
->led_pin
);
769 ath5k_hw_set_gpio(ah
, sc
->led_pin
, !sc
->led_on
);
772 ath5k_hw_get_lladdr(ah
, mac
);
773 SET_IEEE80211_PERM_ADDR(hw
, mac
);
774 /* All MAC address bits matter for ACKs */
775 memset(sc
->bssidmask
, 0xff, ETH_ALEN
);
776 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
778 ret
= ieee80211_register_hw(hw
);
780 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
786 ath5k_txq_release(sc
);
788 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
790 ath5k_desc_free(sc
, pdev
);
796 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
798 struct ath5k_softc
*sc
= hw
->priv
;
801 * NB: the order of these is important:
802 * o call the 802.11 layer before detaching ath5k_hw to
803 * insure callbacks into the driver to delete global
804 * key cache entries can be handled
805 * o reclaim the tx queue data structures after calling
806 * the 802.11 layer as we'll get called back to reclaim
807 * node state and potentially want to use them
808 * o to cleanup the tx queues the hal is called, so detach
810 * XXX: ??? detach ath5k_hw ???
811 * Other than that, it's straightforward...
813 ieee80211_unregister_hw(hw
);
814 ath5k_desc_free(sc
, pdev
);
815 ath5k_txq_release(sc
);
816 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
819 * NB: can't reclaim these until after ieee80211_ifdetach
820 * returns because we'll get called back to reclaim node
821 * state and potentially want to use them.
828 /********************\
829 * Channel/mode setup *
830 \********************/
833 * Convert IEEE channel number to MHz frequency.
836 ath5k_ieee2mhz(short chan
)
838 if (chan
<= 14 || chan
>= 27)
839 return ieee80211chan2mhz(chan
);
841 return 2212 + chan
* 20;
845 ath5k_copy_rates(struct ieee80211_rate
*rates
,
846 const struct ath5k_rate_table
*rt
,
849 unsigned int i
, count
;
854 for (i
= 0, count
= 0; i
< rt
->rate_count
&& max
> 0; i
++) {
855 rates
[count
].bitrate
= rt
->rates
[i
].rate_kbps
/ 100;
856 rates
[count
].hw_value
= rt
->rates
[i
].rate_code
;
857 rates
[count
].flags
= rt
->rates
[i
].modulation
;
866 ath5k_copy_channels(struct ath5k_hw
*ah
,
867 struct ieee80211_channel
*channels
,
871 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
873 if (!test_bit(mode
, ah
->ah_modes
))
878 case AR5K_MODE_11A_TURBO
:
879 /* 1..220, but 2GHz frequencies are filtered by check_channel */
881 chfreq
= CHANNEL_5GHZ
;
885 case AR5K_MODE_11G_TURBO
:
887 chfreq
= CHANNEL_2GHZ
;
890 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
894 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
896 freq
= ath5k_ieee2mhz(ch
);
898 /* Check if channel is supported by the chipset */
899 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
902 /* Write channel info and increment counter */
903 channels
[count
].center_freq
= freq
;
904 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
905 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
909 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
911 case AR5K_MODE_11A_TURBO
:
912 case AR5K_MODE_11G_TURBO
:
913 channels
[count
].hw_value
= chfreq
|
914 CHANNEL_OFDM
| CHANNEL_TURBO
;
917 channels
[count
].hw_value
= CHANNEL_B
;
928 ath5k_getchannels(struct ieee80211_hw
*hw
)
930 struct ath5k_softc
*sc
= hw
->priv
;
931 struct ath5k_hw
*ah
= sc
->ah
;
932 struct ieee80211_supported_band
*sbands
= sc
->sbands
;
933 const struct ath5k_rate_table
*hw_rates
;
934 unsigned int max_r
, max_c
, count_r
, count_c
;
935 int mode2g
= AR5K_MODE_11G
;
937 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
939 max_r
= ARRAY_SIZE(sc
->rates
);
940 max_c
= ARRAY_SIZE(sc
->channels
);
941 count_r
= count_c
= 0;
944 if (!test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
945 mode2g
= AR5K_MODE_11B
;
946 if (!test_bit(AR5K_MODE_11B
,
947 sc
->ah
->ah_capabilities
.cap_mode
))
952 struct ieee80211_supported_band
*sband
=
953 &sbands
[IEEE80211_BAND_2GHZ
];
955 sband
->bitrates
= sc
->rates
;
956 sband
->channels
= sc
->channels
;
958 sband
->band
= IEEE80211_BAND_2GHZ
;
959 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
962 hw_rates
= ath5k_hw_get_rate_table(ah
, mode2g
);
963 sband
->n_bitrates
= ath5k_copy_rates(sband
->bitrates
,
966 count_c
= sband
->n_channels
;
967 count_r
= sband
->n_bitrates
;
969 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
978 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
979 struct ieee80211_supported_band
*sband
=
980 &sbands
[IEEE80211_BAND_5GHZ
];
982 sband
->bitrates
= &sc
->rates
[count_r
];
983 sband
->channels
= &sc
->channels
[count_c
];
985 sband
->band
= IEEE80211_BAND_5GHZ
;
986 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
987 AR5K_MODE_11A
, max_c
);
989 hw_rates
= ath5k_hw_get_rate_table(ah
, AR5K_MODE_11A
);
990 sband
->n_bitrates
= ath5k_copy_rates(sband
->bitrates
,
993 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
996 ath5k_debug_dump_bands(sc
);
1002 * Set/change channels. If the channel is really being changed,
1003 * it's done by reseting the chip. To accomplish this we must
1004 * first cleanup any pending DMA, then restart stuff after a la
1008 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1010 struct ath5k_hw
*ah
= sc
->ah
;
1013 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "(%u MHz) -> (%u MHz)\n",
1014 sc
->curchan
->center_freq
, chan
->center_freq
);
1016 if (chan
->center_freq
!= sc
->curchan
->center_freq
||
1017 chan
->hw_value
!= sc
->curchan
->hw_value
) {
1020 sc
->curband
= &sc
->sbands
[chan
->band
];
1023 * To switch channels clear any pending DMA operations;
1024 * wait long enough for the RX fifo to drain, reset the
1025 * hardware at the new frequency, and then re-enable
1026 * the relevant bits of the h/w.
1028 ath5k_hw_set_intr(ah
, 0); /* disable interrupts */
1029 ath5k_txq_cleanup(sc
); /* clear pending tx frames */
1030 ath5k_rx_stop(sc
); /* turn off frame recv */
1031 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
1033 ATH5K_ERR(sc
, "%s: unable to reset channel "
1034 "(%u Mhz)\n", __func__
, chan
->center_freq
);
1038 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
1041 * Re-enable rx framework.
1043 ret
= ath5k_rx_start(sc
);
1045 ATH5K_ERR(sc
, "%s: unable to restart recv logic\n",
1051 * Change channels and update the h/w rate map
1052 * if we're switching; e.g. 11a to 11b/g.
1056 /* ath5k_chan_change(sc, chan); */
1058 ath5k_beacon_config(sc
);
1060 * Re-enable interrupts.
1062 ath5k_hw_set_intr(ah
, sc
->imask
);
1069 * TODO: CLEAN THIS !!!
1072 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1074 if (unlikely(test_bit(ATH_STAT_LEDSOFT
, sc
->status
))) {
1075 /* from Atheros NDIS driver, w/ permission */
1076 static const struct {
1077 u16 rate
; /* tx/rx 802.11 rate */
1078 u16 timeOn
; /* LED on time (ms) */
1079 u16 timeOff
; /* LED off time (ms) */
1096 const struct ath5k_rate_table
*rt
=
1097 ath5k_hw_get_rate_table(sc
->ah
, mode
);
1102 memset(sc
->hwmap
, 0, sizeof(sc
->hwmap
));
1103 for (i
= 0; i
< 32; i
++) {
1104 u8 ix
= rt
->rate_code_to_index
[i
];
1106 sc
->hwmap
[i
].ledon
= msecs_to_jiffies(500);
1107 sc
->hwmap
[i
].ledoff
= msecs_to_jiffies(130);
1110 sc
->hwmap
[i
].txflags
= IEEE80211_RADIOTAP_F_DATAPAD
;
1111 /* receive frames include FCS */
1112 sc
->hwmap
[i
].rxflags
= sc
->hwmap
[i
].txflags
|
1113 IEEE80211_RADIOTAP_F_FCS
;
1114 /* setup blink rate table to avoid per-packet lookup */
1115 for (j
= 0; j
< ARRAY_SIZE(blinkrates
) - 1; j
++)
1116 if (blinkrates
[j
].rate
== /* XXX why 7f? */
1117 (rt
->rates
[ix
].dot11_rate
&0x7f))
1120 sc
->hwmap
[i
].ledon
= msecs_to_jiffies(blinkrates
[j
].
1122 sc
->hwmap
[i
].ledoff
= msecs_to_jiffies(blinkrates
[j
].
1129 if (mode
== AR5K_MODE_11A
) {
1130 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1132 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1137 ath5k_mode_setup(struct ath5k_softc
*sc
)
1139 struct ath5k_hw
*ah
= sc
->ah
;
1142 /* configure rx filter */
1143 rfilt
= sc
->filter_flags
;
1144 ath5k_hw_set_rx_filter(ah
, rfilt
);
1146 if (ath5k_hw_hasbssidmask(ah
))
1147 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1149 /* configure operational mode */
1150 ath5k_hw_set_opmode(ah
);
1152 ath5k_hw_set_mcast_filter(ah
, 0, 0);
1153 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1157 * Match the hw provided rate index (through descriptors)
1158 * to an index for sc->curband->bitrates, so it can be used
1161 * This one is a little bit tricky but i think i'm right
1164 * We have 4 rate tables in the following order:
1168 * 802.11g (12 rates)
1169 * that make the hw rate table.
1171 * Lets take a 5211 for example that supports a and b modes only.
1172 * First comes the 802.11a table and then 802.11b (total 12 rates).
1173 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1174 * if it returns 2 it points to the second 802.11a rate etc.
1176 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1177 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1178 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1181 ath5k_set_total_hw_rates(struct ath5k_softc
*sc
) {
1183 struct ath5k_hw
*ah
= sc
->ah
;
1185 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
1188 if (test_bit(AR5K_MODE_11B
, ah
->ah_modes
))
1191 if (test_bit(AR5K_MODE_11G
, ah
->ah_modes
))
1194 /* XXX: Need to see what what happens when
1195 xr disable bits in eeprom are set */
1196 if (ah
->ah_version
>= AR5K_AR5212
)
1202 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
) {
1206 if(sc
->curband
->band
== IEEE80211_BAND_2GHZ
) {
1207 /* We setup a g ratetable for both b/g modes */
1209 hw_rix
- sc
->b_rates
- sc
->a_rates
- sc
->xr_rates
;
1211 mac80211_rix
= hw_rix
- sc
->xr_rates
;
1214 /* Something went wrong, fallback to basic rate for this band */
1215 if ((mac80211_rix
>= sc
->curband
->n_bitrates
) ||
1216 (mac80211_rix
<= 0 ))
1219 return mac80211_rix
;
1230 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1232 struct ath5k_hw
*ah
= sc
->ah
;
1233 struct sk_buff
*skb
= bf
->skb
;
1234 struct ath5k_desc
*ds
;
1236 if (likely(skb
== NULL
)) {
1240 * Allocate buffer with headroom_needed space for the
1241 * fake physical layer header at the start.
1243 skb
= dev_alloc_skb(sc
->rxbufsize
+ sc
->cachelsz
- 1);
1244 if (unlikely(skb
== NULL
)) {
1245 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1246 sc
->rxbufsize
+ sc
->cachelsz
- 1);
1250 * Cache-line-align. This is important (for the
1251 * 5210 at least) as not doing so causes bogus data
1254 off
= ((unsigned long)skb
->data
) % sc
->cachelsz
;
1256 skb_reserve(skb
, sc
->cachelsz
- off
);
1259 bf
->skbaddr
= pci_map_single(sc
->pdev
,
1260 skb
->data
, sc
->rxbufsize
, PCI_DMA_FROMDEVICE
);
1261 if (unlikely(pci_dma_mapping_error(bf
->skbaddr
))) {
1262 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1270 * Setup descriptors. For receive we always terminate
1271 * the descriptor list with a self-linked entry so we'll
1272 * not get overrun under high load (as can happen with a
1273 * 5212 when ANI processing enables PHY error frames).
1275 * To insure the last descriptor is self-linked we create
1276 * each descriptor as self-linked and add it to the end. As
1277 * each additional descriptor is added the previous self-linked
1278 * entry is ``fixed'' naturally. This should be safe even
1279 * if DMA is happening. When processing RX interrupts we
1280 * never remove/process the last, self-linked, entry on the
1281 * descriptor list. This insures the hardware always has
1282 * someplace to write a new frame.
1285 ds
->ds_link
= bf
->daddr
; /* link to self */
1286 ds
->ds_data
= bf
->skbaddr
;
1287 ath5k_hw_setup_rx_desc(ah
, ds
,
1288 skb_tailroom(skb
), /* buffer size */
1291 if (sc
->rxlink
!= NULL
)
1292 *sc
->rxlink
= bf
->daddr
;
1293 sc
->rxlink
= &ds
->ds_link
;
1298 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
,
1299 struct ieee80211_tx_control
*ctl
)
1301 struct ath5k_hw
*ah
= sc
->ah
;
1302 struct ath5k_txq
*txq
= sc
->txq
;
1303 struct ath5k_desc
*ds
= bf
->desc
;
1304 struct sk_buff
*skb
= bf
->skb
;
1305 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1308 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1310 /* XXX endianness */
1311 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1314 if (ctl
->flags
& IEEE80211_TXCTL_NO_ACK
)
1315 flags
|= AR5K_TXDESC_NOACK
;
1319 if (!(ctl
->flags
& IEEE80211_TXCTL_DO_NOT_ENCRYPT
)) {
1320 keyidx
= ctl
->hw_key
->hw_key_idx
;
1321 pktlen
+= ctl
->icv_len
;
1324 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1325 ieee80211_get_hdrlen_from_skb(skb
), AR5K_PKT_TYPE_NORMAL
,
1326 (sc
->power_level
* 2), ctl
->tx_rate
->hw_value
,
1327 ctl
->retry_limit
, keyidx
, 0, flags
, 0, 0);
1332 ds
->ds_data
= bf
->skbaddr
;
1334 spin_lock_bh(&txq
->lock
);
1335 list_add_tail(&bf
->list
, &txq
->q
);
1336 sc
->tx_stats
[txq
->qnum
].len
++;
1337 if (txq
->link
== NULL
) /* is this first packet? */
1338 ath5k_hw_put_tx_buf(ah
, txq
->qnum
, bf
->daddr
);
1339 else /* no, so only link it */
1340 *txq
->link
= bf
->daddr
;
1342 txq
->link
= &ds
->ds_link
;
1343 ath5k_hw_tx_start(ah
, txq
->qnum
);
1344 spin_unlock_bh(&txq
->lock
);
1348 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1352 /*******************\
1353 * Descriptors setup *
1354 \*******************/
1357 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1359 struct ath5k_desc
*ds
;
1360 struct ath5k_buf
*bf
;
1365 /* allocate descriptors */
1366 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1367 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1368 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1369 if (sc
->desc
== NULL
) {
1370 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1375 da
= sc
->desc_daddr
;
1376 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1377 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1379 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1380 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1382 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1388 INIT_LIST_HEAD(&sc
->rxbuf
);
1389 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1392 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1395 INIT_LIST_HEAD(&sc
->txbuf
);
1396 sc
->txbuf_len
= ATH_TXBUF
;
1397 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1398 da
+= sizeof(*ds
)) {
1401 list_add_tail(&bf
->list
, &sc
->txbuf
);
1411 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1418 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1420 struct ath5k_buf
*bf
;
1422 ath5k_txbuf_free(sc
, sc
->bbuf
);
1423 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1424 ath5k_txbuf_free(sc
, bf
);
1425 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1426 ath5k_txbuf_free(sc
, bf
);
1428 /* Free memory associated with all descriptors */
1429 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1443 static struct ath5k_txq
*
1444 ath5k_txq_setup(struct ath5k_softc
*sc
,
1445 int qtype
, int subtype
)
1447 struct ath5k_hw
*ah
= sc
->ah
;
1448 struct ath5k_txq
*txq
;
1449 struct ath5k_txq_info qi
= {
1450 .tqi_subtype
= subtype
,
1451 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1452 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1453 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1458 * Enable interrupts only for EOL and DESC conditions.
1459 * We mark tx descriptors to receive a DESC interrupt
1460 * when a tx queue gets deep; otherwise waiting for the
1461 * EOL to reap descriptors. Note that this is done to
1462 * reduce interrupt load and this only defers reaping
1463 * descriptors, never transmitting frames. Aside from
1464 * reducing interrupts this also permits more concurrency.
1465 * The only potential downside is if the tx queue backs
1466 * up in which case the top half of the kernel may backup
1467 * due to a lack of tx descriptors.
1469 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1470 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1471 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1474 * NB: don't print a message, this happens
1475 * normally on parts with too few tx queues
1477 return ERR_PTR(qnum
);
1479 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1480 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1481 qnum
, ARRAY_SIZE(sc
->txqs
));
1482 ath5k_hw_release_tx_queue(ah
, qnum
);
1483 return ERR_PTR(-EINVAL
);
1485 txq
= &sc
->txqs
[qnum
];
1489 INIT_LIST_HEAD(&txq
->q
);
1490 spin_lock_init(&txq
->lock
);
1493 return &sc
->txqs
[qnum
];
1497 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1499 struct ath5k_txq_info qi
= {
1500 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1501 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1502 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1503 /* NB: for dynamic turbo, don't enable any other interrupts */
1504 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1507 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1511 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1513 struct ath5k_hw
*ah
= sc
->ah
;
1514 struct ath5k_txq_info qi
;
1517 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1520 if (sc
->opmode
== IEEE80211_IF_TYPE_AP
) {
1522 * Always burst out beacon and CAB traffic
1523 * (aifs = cwmin = cwmax = 0)
1528 } else if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
1530 * Adhoc mode; backoff between 0 and (2 * cw_min).
1534 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1537 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1538 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1539 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1541 ret
= ath5k_hw_setup_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1543 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1544 "hardware queue!\n", __func__
);
1548 return ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */;
1552 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1554 struct ath5k_buf
*bf
, *bf0
;
1557 * NB: this assumes output has been stopped and
1558 * we do not need to block ath5k_tx_tasklet
1560 spin_lock_bh(&txq
->lock
);
1561 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1562 ath5k_debug_printtxbuf(sc
, bf
);
1564 ath5k_txbuf_free(sc
, bf
);
1566 spin_lock_bh(&sc
->txbuflock
);
1567 sc
->tx_stats
[txq
->qnum
].len
--;
1568 list_move_tail(&bf
->list
, &sc
->txbuf
);
1570 spin_unlock_bh(&sc
->txbuflock
);
1573 spin_unlock_bh(&txq
->lock
);
1577 * Drain the transmit queues and reclaim resources.
1580 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1582 struct ath5k_hw
*ah
= sc
->ah
;
1585 /* XXX return value */
1586 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1587 /* don't touch the hardware if marked invalid */
1588 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1589 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1590 ath5k_hw_get_tx_buf(ah
, sc
->bhalq
));
1591 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1592 if (sc
->txqs
[i
].setup
) {
1593 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1594 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1597 ath5k_hw_get_tx_buf(ah
,
1602 ieee80211_start_queues(sc
->hw
); /* XXX move to callers */
1604 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1605 if (sc
->txqs
[i
].setup
)
1606 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1610 ath5k_txq_release(struct ath5k_softc
*sc
)
1612 struct ath5k_txq
*txq
= sc
->txqs
;
1615 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1617 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1630 * Enable the receive h/w following a reset.
1633 ath5k_rx_start(struct ath5k_softc
*sc
)
1635 struct ath5k_hw
*ah
= sc
->ah
;
1636 struct ath5k_buf
*bf
;
1639 sc
->rxbufsize
= roundup(IEEE80211_MAX_LEN
, sc
->cachelsz
);
1641 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rxbufsize %u\n",
1642 sc
->cachelsz
, sc
->rxbufsize
);
1646 spin_lock_bh(&sc
->rxbuflock
);
1647 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1648 ret
= ath5k_rxbuf_setup(sc
, bf
);
1650 spin_unlock_bh(&sc
->rxbuflock
);
1654 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1655 spin_unlock_bh(&sc
->rxbuflock
);
1657 ath5k_hw_put_rx_buf(ah
, bf
->daddr
);
1658 ath5k_hw_start_rx(ah
); /* enable recv descriptors */
1659 ath5k_mode_setup(sc
); /* set filters, etc. */
1660 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1668 * Disable the receive h/w in preparation for a reset.
1671 ath5k_rx_stop(struct ath5k_softc
*sc
)
1673 struct ath5k_hw
*ah
= sc
->ah
;
1675 ath5k_hw_stop_pcu_recv(ah
); /* disable PCU */
1676 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1677 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1678 mdelay(3); /* 3ms is long enough for 1 frame */
1680 ath5k_debug_printrxbuffs(sc
, ah
);
1682 sc
->rxlink
= NULL
; /* just in case */
1686 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct ath5k_desc
*ds
,
1687 struct sk_buff
*skb
, struct ath5k_rx_status
*rs
)
1689 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1690 unsigned int keyix
, hlen
= ieee80211_get_hdrlen_from_skb(skb
);
1692 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1693 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1694 return RX_FLAG_DECRYPTED
;
1696 /* Apparently when a default key is used to decrypt the packet
1697 the hw does not set the index used to decrypt. In such cases
1698 get the index from the packet. */
1699 if ((le16_to_cpu(hdr
->frame_control
) & IEEE80211_FCTL_PROTECTED
) &&
1700 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1701 skb
->len
>= hlen
+ 4) {
1702 keyix
= skb
->data
[hlen
+ 3] >> 6;
1704 if (test_bit(keyix
, sc
->keymap
))
1705 return RX_FLAG_DECRYPTED
;
1713 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1714 struct ieee80211_rx_status
*rxs
)
1718 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1720 if ((le16_to_cpu(mgmt
->frame_control
) & IEEE80211_FCTL_FTYPE
) ==
1721 IEEE80211_FTYPE_MGMT
&&
1722 (le16_to_cpu(mgmt
->frame_control
) & IEEE80211_FCTL_STYPE
) ==
1723 IEEE80211_STYPE_BEACON
&&
1724 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1725 memcmp(mgmt
->bssid
, sc
->ah
->ah_bssid
, ETH_ALEN
) == 0) {
1727 * Received an IBSS beacon with the same BSSID. Hardware *must*
1728 * have updated the local TSF. We have to work around various
1729 * hardware bugs, though...
1731 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1732 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1733 hw_tu
= TSF_TO_TU(tsf
);
1735 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1736 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1737 (unsigned long long)bc_tstamp
,
1738 (unsigned long long)rxs
->mactime
,
1739 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1740 (unsigned long long)tsf
);
1743 * Sometimes the HW will give us a wrong tstamp in the rx
1744 * status, causing the timestamp extension to go wrong.
1745 * (This seems to happen especially with beacon frames bigger
1746 * than 78 byte (incl. FCS))
1747 * But we know that the receive timestamp must be later than the
1748 * timestamp of the beacon since HW must have synced to that.
1750 * NOTE: here we assume mactime to be after the frame was
1751 * received, not like mac80211 which defines it at the start.
1753 if (bc_tstamp
> rxs
->mactime
) {
1754 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1755 "fixing mactime from %llx to %llx\n",
1756 (unsigned long long)rxs
->mactime
,
1757 (unsigned long long)tsf
);
1762 * Local TSF might have moved higher than our beacon timers,
1763 * in that case we have to update them to continue sending
1764 * beacons. This also takes care of synchronizing beacon sending
1765 * times with other stations.
1767 if (hw_tu
>= sc
->nexttbtt
)
1768 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1774 ath5k_tasklet_rx(unsigned long data
)
1776 struct ieee80211_rx_status rxs
= {};
1777 struct ath5k_rx_status rs
= {};
1778 struct sk_buff
*skb
;
1779 struct ath5k_softc
*sc
= (void *)data
;
1780 struct ath5k_buf
*bf
;
1781 struct ath5k_desc
*ds
;
1786 spin_lock(&sc
->rxbuflock
);
1788 if (unlikely(list_empty(&sc
->rxbuf
))) {
1789 ATH5K_WARN(sc
, "empty rx buf pool\n");
1792 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1793 BUG_ON(bf
->skb
== NULL
);
1797 /* TODO only one segment */
1798 pci_dma_sync_single_for_cpu(sc
->pdev
, sc
->desc_daddr
,
1799 sc
->desc_len
, PCI_DMA_FROMDEVICE
);
1801 if (unlikely(ds
->ds_link
== bf
->daddr
)) /* this is the end */
1804 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
1805 if (unlikely(ret
== -EINPROGRESS
))
1807 else if (unlikely(ret
)) {
1808 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
1809 spin_unlock(&sc
->rxbuflock
);
1813 if (unlikely(rs
.rs_more
)) {
1814 ATH5K_WARN(sc
, "unsupported jumbo\n");
1818 if (unlikely(rs
.rs_status
)) {
1819 if (rs
.rs_status
& AR5K_RXERR_PHY
)
1821 if (rs
.rs_status
& AR5K_RXERR_DECRYPT
) {
1823 * Decrypt error. If the error occurred
1824 * because there was no hardware key, then
1825 * let the frame through so the upper layers
1826 * can process it. This is necessary for 5210
1827 * parts which have no way to setup a ``clear''
1830 * XXX do key cache faulting
1832 if (rs
.rs_keyix
== AR5K_RXKEYIX_INVALID
&&
1833 !(rs
.rs_status
& AR5K_RXERR_CRC
))
1836 if (rs
.rs_status
& AR5K_RXERR_MIC
) {
1837 rxs
.flag
|= RX_FLAG_MMIC_ERROR
;
1841 /* let crypto-error packets fall through in MNTR */
1843 ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
1844 sc
->opmode
!= IEEE80211_IF_TYPE_MNTR
)
1848 pci_dma_sync_single_for_cpu(sc
->pdev
, bf
->skbaddr
,
1849 rs
.rs_datalen
, PCI_DMA_FROMDEVICE
);
1850 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, sc
->rxbufsize
,
1851 PCI_DMA_FROMDEVICE
);
1854 skb_put(skb
, rs
.rs_datalen
);
1857 * the hardware adds a padding to 4 byte boundaries between
1858 * the header and the payload data if the header length is
1859 * not multiples of 4 - remove it
1861 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
1864 memmove(skb
->data
+ pad
, skb
->data
, hdrlen
);
1869 * always extend the mac timestamp, since this information is
1870 * also needed for proper IBSS merging.
1872 * XXX: it might be too late to do it here, since rs_tstamp is
1873 * 15bit only. that means TSF extension has to be done within
1874 * 32768usec (about 32ms). it might be necessary to move this to
1875 * the interrupt handler, like it is done in madwifi.
1877 * Unfortunately we don't know when the hardware takes the rx
1878 * timestamp (beginning of phy frame, data frame, end of rx?).
1879 * The only thing we know is that it is hardware specific...
1880 * On AR5213 it seems the rx timestamp is at the end of the
1881 * frame, but i'm not sure.
1883 * NOTE: mac80211 defines mactime at the beginning of the first
1884 * data symbol. Since we don't have any time references it's
1885 * impossible to comply to that. This affects IBSS merge only
1886 * right now, so it's not too bad...
1888 rxs
.mactime
= ath5k_extend_tsf(sc
->ah
, rs
.rs_tstamp
);
1889 rxs
.flag
|= RX_FLAG_TSFT
;
1891 rxs
.freq
= sc
->curchan
->center_freq
;
1892 rxs
.band
= sc
->curband
->band
;
1894 rxs
.noise
= sc
->ah
->ah_noise_floor
;
1895 rxs
.signal
= rxs
.noise
+ rs
.rs_rssi
;
1896 rxs
.qual
= rs
.rs_rssi
* 100 / 64;
1898 rxs
.antenna
= rs
.rs_antenna
;
1899 rxs
.rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
.rs_rate
);
1900 rxs
.flag
|= ath5k_rx_decrypted(sc
, ds
, skb
, &rs
);
1902 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1904 /* check beacons in IBSS mode */
1905 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
)
1906 ath5k_check_ibss_tsf(sc
, skb
, &rxs
);
1908 __ieee80211_rx(sc
->hw
, skb
, &rxs
);
1909 sc
->led_rxrate
= rs
.rs_rate
;
1910 ath5k_led_event(sc
, ATH_LED_RX
);
1912 list_move_tail(&bf
->list
, &sc
->rxbuf
);
1913 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
1914 spin_unlock(&sc
->rxbuflock
);
1925 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1927 struct ieee80211_tx_status txs
= {};
1928 struct ath5k_tx_status ts
= {};
1929 struct ath5k_buf
*bf
, *bf0
;
1930 struct ath5k_desc
*ds
;
1931 struct sk_buff
*skb
;
1934 spin_lock(&txq
->lock
);
1935 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1938 /* TODO only one segment */
1939 pci_dma_sync_single_for_cpu(sc
->pdev
, sc
->desc_daddr
,
1940 sc
->desc_len
, PCI_DMA_FROMDEVICE
);
1941 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
1942 if (unlikely(ret
== -EINPROGRESS
))
1944 else if (unlikely(ret
)) {
1945 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
1952 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
1955 txs
.control
= bf
->ctl
;
1956 txs
.retry_count
= ts
.ts_shortretry
+ ts
.ts_longretry
/ 6;
1957 if (unlikely(ts
.ts_status
)) {
1958 sc
->ll_stats
.dot11ACKFailureCount
++;
1959 if (ts
.ts_status
& AR5K_TXERR_XRETRY
)
1960 txs
.excessive_retries
= 1;
1961 else if (ts
.ts_status
& AR5K_TXERR_FILT
)
1962 txs
.flags
|= IEEE80211_TX_STATUS_TX_FILTERED
;
1964 txs
.flags
|= IEEE80211_TX_STATUS_ACK
;
1965 txs
.ack_signal
= ts
.ts_rssi
;
1968 ieee80211_tx_status(sc
->hw
, skb
, &txs
);
1969 sc
->tx_stats
[txq
->qnum
].count
++;
1971 spin_lock(&sc
->txbuflock
);
1972 sc
->tx_stats
[txq
->qnum
].len
--;
1973 list_move_tail(&bf
->list
, &sc
->txbuf
);
1975 spin_unlock(&sc
->txbuflock
);
1977 if (likely(list_empty(&txq
->q
)))
1979 spin_unlock(&txq
->lock
);
1980 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
1981 ieee80211_wake_queues(sc
->hw
);
1985 ath5k_tasklet_tx(unsigned long data
)
1987 struct ath5k_softc
*sc
= (void *)data
;
1989 ath5k_tx_processq(sc
, sc
->txq
);
1991 ath5k_led_event(sc
, ATH_LED_TX
);
2002 * Setup the beacon frame for transmit.
2005 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
,
2006 struct ieee80211_tx_control
*ctl
)
2008 struct sk_buff
*skb
= bf
->skb
;
2009 struct ath5k_hw
*ah
= sc
->ah
;
2010 struct ath5k_desc
*ds
;
2011 int ret
, antenna
= 0;
2014 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
2016 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
2017 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
2018 (unsigned long long)bf
->skbaddr
);
2019 if (pci_dma_mapping_error(bf
->skbaddr
)) {
2020 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
2026 flags
= AR5K_TXDESC_NOACK
;
2027 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
&& ath5k_hw_hasveol(ah
)) {
2028 ds
->ds_link
= bf
->daddr
; /* self-linked */
2029 flags
|= AR5K_TXDESC_VEOL
;
2031 * Let hardware handle antenna switching if txantenna is not set
2036 * Switch antenna every 4 beacons if txantenna is not set
2037 * XXX assumes two antennas
2040 antenna
= sc
->bsent
& 4 ? 2 : 1;
2043 ds
->ds_data
= bf
->skbaddr
;
2044 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
2045 ieee80211_get_hdrlen_from_skb(skb
),
2046 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
2047 ctl
->tx_rate
->hw_value
, 1, AR5K_TXKEYIX_INVALID
,
2048 antenna
, flags
, 0, 0);
2054 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
2059 * Transmit a beacon frame at SWBA. Dynamic updates to the
2060 * frame contents are done as needed and the slot time is
2061 * also adjusted based on current state.
2063 * this is usually called from interrupt context (ath5k_intr())
2064 * but also from ath5k_beacon_config() in IBSS mode which in turn
2065 * can be called from a tasklet and user context
2068 ath5k_beacon_send(struct ath5k_softc
*sc
)
2070 struct ath5k_buf
*bf
= sc
->bbuf
;
2071 struct ath5k_hw
*ah
= sc
->ah
;
2073 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
2075 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== IEEE80211_IF_TYPE_STA
||
2076 sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)) {
2077 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
2081 * Check if the previous beacon has gone out. If
2082 * not don't don't try to post another, skip this
2083 * period and wait for the next. Missed beacons
2084 * indicate a problem and should not occur. If we
2085 * miss too many consecutive beacons reset the device.
2087 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
2089 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2090 "missed %u consecutive beacons\n", sc
->bmisscount
);
2091 if (sc
->bmisscount
> 3) { /* NB: 3 is a guess */
2092 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2093 "stuck beacon time (%u missed)\n",
2095 tasklet_schedule(&sc
->restq
);
2099 if (unlikely(sc
->bmisscount
!= 0)) {
2100 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2101 "resume beacon xmit after %u misses\n",
2107 * Stop any current dma and put the new frame on the queue.
2108 * This should never fail since we check above that no frames
2109 * are still pending on the queue.
2111 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
2112 ATH5K_WARN(sc
, "beacon queue %u didn't stop?\n", sc
->bhalq
);
2113 /* NB: hw still stops DMA, so proceed */
2115 pci_dma_sync_single_for_cpu(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
2118 ath5k_hw_put_tx_buf(ah
, sc
->bhalq
, bf
->daddr
);
2119 ath5k_hw_tx_start(ah
, sc
->bhalq
);
2120 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2121 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2128 * ath5k_beacon_update_timers - update beacon timers
2130 * @sc: struct ath5k_softc pointer we are operating on
2131 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2132 * beacon timer update based on the current HW TSF.
2134 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2135 * of a received beacon or the current local hardware TSF and write it to the
2136 * beacon timer registers.
2138 * This is called in a variety of situations, e.g. when a beacon is received,
2139 * when a TSF update has been detected, but also when an new IBSS is created or
2140 * when we otherwise know we have to update the timers, but we keep it in this
2141 * function to have it all together in one place.
2144 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2146 struct ath5k_hw
*ah
= sc
->ah
;
2147 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2150 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2151 if (WARN_ON(!intval
))
2154 /* beacon TSF converted to TU */
2155 bc_tu
= TSF_TO_TU(bc_tsf
);
2157 /* current TSF converted to TU */
2158 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2159 hw_tu
= TSF_TO_TU(hw_tsf
);
2162 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2165 * no beacons received, called internally.
2166 * just need to refresh timers based on HW TSF.
2168 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2169 } else if (bc_tsf
== 0) {
2171 * no beacon received, probably called by ath5k_reset_tsf().
2172 * reset TSF to start with 0.
2175 intval
|= AR5K_BEACON_RESET_TSF
;
2176 } else if (bc_tsf
> hw_tsf
) {
2178 * beacon received, SW merge happend but HW TSF not yet updated.
2179 * not possible to reconfigure timers yet, but next time we
2180 * receive a beacon with the same BSSID, the hardware will
2181 * automatically update the TSF and then we need to reconfigure
2184 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2185 "need to wait for HW TSF sync\n");
2189 * most important case for beacon synchronization between STA.
2191 * beacon received and HW TSF has been already updated by HW.
2192 * update next TBTT based on the TSF of the beacon, but make
2193 * sure it is ahead of our local TSF timer.
2195 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2199 sc
->nexttbtt
= nexttbtt
;
2201 intval
|= AR5K_BEACON_ENA
;
2202 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2205 * debugging output last in order to preserve the time critical aspect
2209 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2210 "reconfigured timers based on HW TSF\n");
2211 else if (bc_tsf
== 0)
2212 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2213 "reset HW TSF and timers\n");
2215 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2216 "updated timers based on beacon TSF\n");
2218 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2219 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2220 (unsigned long long) bc_tsf
,
2221 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2222 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2223 intval
& AR5K_BEACON_PERIOD
,
2224 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2225 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2230 * ath5k_beacon_config - Configure the beacon queues and interrupts
2232 * @sc: struct ath5k_softc pointer we are operating on
2234 * When operating in station mode we want to receive a BMISS interrupt when we
2235 * stop seeing beacons from the AP we've associated with so we can look for
2236 * another AP to associate with.
2238 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2239 * interrupts to detect TSF updates only.
2241 * AP mode is missing.
2244 ath5k_beacon_config(struct ath5k_softc
*sc
)
2246 struct ath5k_hw
*ah
= sc
->ah
;
2248 ath5k_hw_set_intr(ah
, 0);
2251 if (sc
->opmode
== IEEE80211_IF_TYPE_STA
) {
2252 sc
->imask
|= AR5K_INT_BMISS
;
2253 } else if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
2255 * In IBSS mode we use a self-linked tx descriptor and let the
2256 * hardware send the beacons automatically. We have to load it
2258 * We use the SWBA interrupt only to keep track of the beacon
2259 * timers in order to detect automatic TSF updates.
2261 ath5k_beaconq_config(sc
);
2263 sc
->imask
|= AR5K_INT_SWBA
;
2265 if (ath5k_hw_hasveol(ah
))
2266 ath5k_beacon_send(sc
);
2270 ath5k_hw_set_intr(ah
, sc
->imask
);
2274 /********************\
2275 * Interrupt handling *
2276 \********************/
2279 ath5k_init(struct ath5k_softc
*sc
)
2283 mutex_lock(&sc
->lock
);
2285 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2288 * Stop anything previously setup. This is safe
2289 * no matter this is the first time through or not.
2291 ath5k_stop_locked(sc
);
2294 * The basic interface to setting the hardware in a good
2295 * state is ``reset''. On return the hardware is known to
2296 * be powered up and with interrupts disabled. This must
2297 * be followed by initialization of the appropriate bits
2298 * and then setup of the interrupt mask.
2300 sc
->curchan
= sc
->hw
->conf
.channel
;
2301 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2302 ret
= ath5k_hw_reset(sc
->ah
, sc
->opmode
, sc
->curchan
, false);
2304 ATH5K_ERR(sc
, "unable to reset hardware: %d\n", ret
);
2308 * This is needed only to setup initial state
2309 * but it's best done after a reset.
2311 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2314 * Setup the hardware after reset: the key cache
2315 * is filled as needed and the receive engine is
2316 * set going. Frame transmit is handled entirely
2317 * in the frame output path; there's nothing to do
2318 * here except setup the interrupt mask.
2320 ret
= ath5k_rx_start(sc
);
2325 * Enable interrupts.
2327 sc
->imask
= AR5K_INT_RX
| AR5K_INT_TX
| AR5K_INT_RXEOL
|
2328 AR5K_INT_RXORN
| AR5K_INT_FATAL
| AR5K_INT_GLOBAL
|
2331 ath5k_hw_set_intr(sc
->ah
, sc
->imask
);
2332 /* Set ack to be sent at low bit-rates */
2333 ath5k_hw_set_ack_bitrate_high(sc
->ah
, false);
2335 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2336 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2340 mutex_unlock(&sc
->lock
);
2345 ath5k_stop_locked(struct ath5k_softc
*sc
)
2347 struct ath5k_hw
*ah
= sc
->ah
;
2349 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2350 test_bit(ATH_STAT_INVALID
, sc
->status
));
2353 * Shutdown the hardware and driver:
2354 * stop output from above
2355 * disable interrupts
2357 * turn off the radio
2358 * clear transmit machinery
2359 * clear receive machinery
2360 * drain and release tx queues
2361 * reclaim beacon resources
2362 * power down hardware
2364 * Note that some of this work is not possible if the
2365 * hardware is gone (invalid).
2367 ieee80211_stop_queues(sc
->hw
);
2369 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2370 if (test_bit(ATH_STAT_LEDSOFT
, sc
->status
)) {
2371 del_timer_sync(&sc
->led_tim
);
2372 ath5k_hw_set_gpio(ah
, sc
->led_pin
, !sc
->led_on
);
2373 __clear_bit(ATH_STAT_LEDBLINKING
, sc
->status
);
2375 ath5k_hw_set_intr(ah
, 0);
2377 ath5k_txq_cleanup(sc
);
2378 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2380 ath5k_hw_phy_disable(ah
);
2388 * Stop the device, grabbing the top-level lock to protect
2389 * against concurrent entry through ath5k_init (which can happen
2390 * if another thread does a system call and the thread doing the
2391 * stop is preempted).
2394 ath5k_stop_hw(struct ath5k_softc
*sc
)
2398 mutex_lock(&sc
->lock
);
2399 ret
= ath5k_stop_locked(sc
);
2400 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2402 * Set the chip in full sleep mode. Note that we are
2403 * careful to do this only when bringing the interface
2404 * completely to a stop. When the chip is in this state
2405 * it must be carefully woken up or references to
2406 * registers in the PCI clock domain may freeze the bus
2407 * (and system). This varies by chip and is mostly an
2408 * issue with newer parts that go to sleep more quickly.
2410 if (sc
->ah
->ah_mac_srev
>= 0x78) {
2413 * don't put newer MAC revisions > 7.8 to sleep because
2414 * of the above mentioned problems
2416 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mac version > 7.8, "
2417 "not putting device to sleep\n");
2419 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2420 "putting device to full sleep\n");
2421 ath5k_hw_set_power(sc
->ah
, AR5K_PM_FULL_SLEEP
, true, 0);
2424 ath5k_txbuf_free(sc
, sc
->bbuf
);
2425 mutex_unlock(&sc
->lock
);
2427 del_timer_sync(&sc
->calib_tim
);
2433 ath5k_intr(int irq
, void *dev_id
)
2435 struct ath5k_softc
*sc
= dev_id
;
2436 struct ath5k_hw
*ah
= sc
->ah
;
2437 enum ath5k_int status
;
2438 unsigned int counter
= 1000;
2440 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2441 !ath5k_hw_is_intr_pending(ah
)))
2446 * Figure out the reason(s) for the interrupt. Note
2447 * that get_isr returns a pseudo-ISR that may include
2448 * bits we haven't explicitly enabled so we mask the
2449 * value to insure we only process bits we requested.
2451 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2452 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2454 status
&= sc
->imask
; /* discard unasked for bits */
2455 if (unlikely(status
& AR5K_INT_FATAL
)) {
2457 * Fatal errors are unrecoverable.
2458 * Typically these are caused by DMA errors.
2460 tasklet_schedule(&sc
->restq
);
2461 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2462 tasklet_schedule(&sc
->restq
);
2464 if (status
& AR5K_INT_SWBA
) {
2466 * Software beacon alert--time to send a beacon.
2467 * Handle beacon transmission directly; deferring
2468 * this is too slow to meet timing constraints
2471 * In IBSS mode we use this interrupt just to
2472 * keep track of the next TBTT (target beacon
2473 * transmission time) in order to detect wether
2474 * automatic TSF updates happened.
2476 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
2477 /* XXX: only if VEOL suppported */
2478 u64 tsf
= ath5k_hw_get_tsf64(ah
);
2479 sc
->nexttbtt
+= sc
->bintval
;
2480 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2481 "SWBA nexttbtt: %x hw_tu: %x "
2485 (unsigned long long) tsf
);
2487 ath5k_beacon_send(sc
);
2490 if (status
& AR5K_INT_RXEOL
) {
2492 * NB: the hardware should re-read the link when
2493 * RXE bit is written, but it doesn't work at
2494 * least on older hardware revs.
2498 if (status
& AR5K_INT_TXURN
) {
2499 /* bump tx trigger level */
2500 ath5k_hw_update_tx_triglevel(ah
, true);
2502 if (status
& AR5K_INT_RX
)
2503 tasklet_schedule(&sc
->rxtq
);
2504 if (status
& AR5K_INT_TX
)
2505 tasklet_schedule(&sc
->txtq
);
2506 if (status
& AR5K_INT_BMISS
) {
2508 if (status
& AR5K_INT_MIB
) {
2510 * These stats are also used for ANI i think
2511 * so how about updating them more often ?
2513 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
2516 } while (ath5k_hw_is_intr_pending(ah
) && counter
-- > 0);
2518 if (unlikely(!counter
))
2519 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2525 ath5k_tasklet_reset(unsigned long data
)
2527 struct ath5k_softc
*sc
= (void *)data
;
2529 ath5k_reset(sc
->hw
);
2533 * Periodically recalibrate the PHY to account
2534 * for temperature/environment changes.
2537 ath5k_calibrate(unsigned long data
)
2539 struct ath5k_softc
*sc
= (void *)data
;
2540 struct ath5k_hw
*ah
= sc
->ah
;
2542 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2543 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2544 sc
->curchan
->hw_value
);
2546 if (ath5k_hw_get_rf_gain(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2548 * Rfgain is out of bounds, reset the chip
2549 * to load new gain values.
2551 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2552 ath5k_reset(sc
->hw
);
2554 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2555 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2556 ieee80211_frequency_to_channel(
2557 sc
->curchan
->center_freq
));
2559 mod_timer(&sc
->calib_tim
, round_jiffies(jiffies
+
2560 msecs_to_jiffies(ath5k_calinterval
* 1000)));
2570 ath5k_led_off(unsigned long data
)
2572 struct ath5k_softc
*sc
= (void *)data
;
2574 if (test_bit(ATH_STAT_LEDENDBLINK
, sc
->status
))
2575 __clear_bit(ATH_STAT_LEDBLINKING
, sc
->status
);
2577 __set_bit(ATH_STAT_LEDENDBLINK
, sc
->status
);
2578 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, !sc
->led_on
);
2579 mod_timer(&sc
->led_tim
, jiffies
+ sc
->led_off
);
2584 * Blink the LED according to the specified on/off times.
2587 ath5k_led_blink(struct ath5k_softc
*sc
, unsigned int on
,
2590 ATH5K_DBG(sc
, ATH5K_DEBUG_LED
, "on %u off %u\n", on
, off
);
2591 ath5k_hw_set_gpio(sc
->ah
, sc
->led_pin
, sc
->led_on
);
2592 __set_bit(ATH_STAT_LEDBLINKING
, sc
->status
);
2593 __clear_bit(ATH_STAT_LEDENDBLINK
, sc
->status
);
2595 mod_timer(&sc
->led_tim
, jiffies
+ on
);
2599 ath5k_led_event(struct ath5k_softc
*sc
, int event
)
2601 if (likely(!test_bit(ATH_STAT_LEDSOFT
, sc
->status
)))
2603 if (unlikely(test_bit(ATH_STAT_LEDBLINKING
, sc
->status
)))
2604 return; /* don't interrupt active blink */
2607 ath5k_led_blink(sc
, sc
->hwmap
[sc
->led_txrate
].ledon
,
2608 sc
->hwmap
[sc
->led_txrate
].ledoff
);
2611 ath5k_led_blink(sc
, sc
->hwmap
[sc
->led_rxrate
].ledon
,
2612 sc
->hwmap
[sc
->led_rxrate
].ledoff
);
2620 /********************\
2621 * Mac80211 functions *
2622 \********************/
2625 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2626 struct ieee80211_tx_control
*ctl
)
2628 struct ath5k_softc
*sc
= hw
->priv
;
2629 struct ath5k_buf
*bf
;
2630 unsigned long flags
;
2634 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2636 if (sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)
2637 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2640 * the hardware expects the header padded to 4 byte boundaries
2641 * if this is not the case we add the padding after the header
2643 hdrlen
= ieee80211_get_hdrlen_from_skb(skb
);
2646 if (skb_headroom(skb
) < pad
) {
2647 ATH5K_ERR(sc
, "tx hdrlen not %%4: %d not enough"
2648 " headroom to pad %d\n", hdrlen
, pad
);
2652 memmove(skb
->data
, skb
->data
+pad
, hdrlen
);
2655 sc
->led_txrate
= ctl
->tx_rate
->hw_value
;
2657 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2658 if (list_empty(&sc
->txbuf
)) {
2659 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2660 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2661 ieee80211_stop_queue(hw
, ctl
->queue
);
2664 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2665 list_del(&bf
->list
);
2667 if (list_empty(&sc
->txbuf
))
2668 ieee80211_stop_queues(hw
);
2669 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2673 if (ath5k_txbuf_setup(sc
, bf
, ctl
)) {
2675 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2676 list_add_tail(&bf
->list
, &sc
->txbuf
);
2678 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2679 dev_kfree_skb_any(skb
);
2687 ath5k_reset(struct ieee80211_hw
*hw
)
2689 struct ath5k_softc
*sc
= hw
->priv
;
2690 struct ath5k_hw
*ah
= sc
->ah
;
2693 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2695 ath5k_hw_set_intr(ah
, 0);
2696 ath5k_txq_cleanup(sc
);
2699 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, true);
2700 if (unlikely(ret
)) {
2701 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2704 ath5k_hw_set_txpower_limit(sc
->ah
, 0);
2706 ret
= ath5k_rx_start(sc
);
2707 if (unlikely(ret
)) {
2708 ATH5K_ERR(sc
, "can't start recv logic\n");
2712 * We may be doing a reset in response to an ioctl
2713 * that changes the channel so update any state that
2714 * might change as a result.
2718 /* ath5k_chan_change(sc, c); */
2719 ath5k_beacon_config(sc
);
2720 /* intrs are started by ath5k_beacon_config */
2722 ieee80211_wake_queues(hw
);
2729 static int ath5k_start(struct ieee80211_hw
*hw
)
2731 return ath5k_init(hw
->priv
);
2734 static void ath5k_stop(struct ieee80211_hw
*hw
)
2736 ath5k_stop_hw(hw
->priv
);
2739 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
2740 struct ieee80211_if_init_conf
*conf
)
2742 struct ath5k_softc
*sc
= hw
->priv
;
2745 mutex_lock(&sc
->lock
);
2751 sc
->vif
= conf
->vif
;
2753 switch (conf
->type
) {
2754 case IEEE80211_IF_TYPE_STA
:
2755 case IEEE80211_IF_TYPE_IBSS
:
2756 case IEEE80211_IF_TYPE_MNTR
:
2757 sc
->opmode
= conf
->type
;
2765 mutex_unlock(&sc
->lock
);
2770 ath5k_remove_interface(struct ieee80211_hw
*hw
,
2771 struct ieee80211_if_init_conf
*conf
)
2773 struct ath5k_softc
*sc
= hw
->priv
;
2775 mutex_lock(&sc
->lock
);
2776 if (sc
->vif
!= conf
->vif
)
2781 mutex_unlock(&sc
->lock
);
2785 * TODO: Phy disable/diversity etc
2788 ath5k_config(struct ieee80211_hw
*hw
,
2789 struct ieee80211_conf
*conf
)
2791 struct ath5k_softc
*sc
= hw
->priv
;
2793 sc
->bintval
= conf
->beacon_int
;
2794 sc
->power_level
= conf
->power_level
;
2796 return ath5k_chan_set(sc
, conf
->channel
);
2800 ath5k_config_interface(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2801 struct ieee80211_if_conf
*conf
)
2803 struct ath5k_softc
*sc
= hw
->priv
;
2804 struct ath5k_hw
*ah
= sc
->ah
;
2807 /* Set to a reasonable value. Note that this will
2808 * be set to mac80211's value at ath5k_config(). */
2810 mutex_lock(&sc
->lock
);
2811 if (sc
->vif
!= vif
) {
2816 /* Cache for later use during resets */
2817 memcpy(ah
->ah_bssid
, conf
->bssid
, ETH_ALEN
);
2818 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2819 * a clean way of letting us retrieve this yet. */
2820 ath5k_hw_set_associd(ah
, ah
->ah_bssid
, 0);
2822 mutex_unlock(&sc
->lock
);
2824 return ath5k_reset(hw
);
2826 mutex_unlock(&sc
->lock
);
2830 #define SUPPORTED_FIF_FLAGS \
2831 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2832 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2833 FIF_BCN_PRBRESP_PROMISC
2835 * o always accept unicast, broadcast, and multicast traffic
2836 * o multicast traffic for all BSSIDs will be enabled if mac80211
2838 * o maintain current state of phy ofdm or phy cck error reception.
2839 * If the hardware detects any of these type of errors then
2840 * ath5k_hw_get_rx_filter() will pass to us the respective
2841 * hardware filters to be able to receive these type of frames.
2842 * o probe request frames are accepted only when operating in
2843 * hostap, adhoc, or monitor modes
2844 * o enable promiscuous mode according to the interface state
2846 * - when operating in adhoc mode so the 802.11 layer creates
2847 * node table entries for peers,
2848 * - when operating in station mode for collecting rssi data when
2849 * the station is otherwise quiet, or
2852 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
2853 unsigned int changed_flags
,
2854 unsigned int *new_flags
,
2855 int mc_count
, struct dev_mc_list
*mclist
)
2857 struct ath5k_softc
*sc
= hw
->priv
;
2858 struct ath5k_hw
*ah
= sc
->ah
;
2859 u32 mfilt
[2], val
, rfilt
;
2866 /* Only deal with supported flags */
2867 changed_flags
&= SUPPORTED_FIF_FLAGS
;
2868 *new_flags
&= SUPPORTED_FIF_FLAGS
;
2870 /* If HW detects any phy or radar errors, leave those filters on.
2871 * Also, always enable Unicast, Broadcasts and Multicast
2872 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2873 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
2874 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
2875 AR5K_RX_FILTER_MCAST
);
2877 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
2878 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
2879 rfilt
|= AR5K_RX_FILTER_PROM
;
2880 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
2883 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
2886 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2887 if (*new_flags
& FIF_ALLMULTI
) {
2891 for (i
= 0; i
< mc_count
; i
++) {
2894 /* calculate XOR of eight 6-bit values */
2895 val
= get_unaligned_le32(mclist
->dmi_addr
+ 0);
2896 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2897 val
= get_unaligned_le32(mclist
->dmi_addr
+ 3);
2898 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
2900 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
2901 /* XXX: we might be able to just do this instead,
2902 * but not sure, needs testing, if we do use this we'd
2903 * neet to inform below to not reset the mcast */
2904 /* ath5k_hw_set_mcast_filterindex(ah,
2905 * mclist->dmi_addr[5]); */
2906 mclist
= mclist
->next
;
2910 /* This is the best we can do */
2911 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
2912 rfilt
|= AR5K_RX_FILTER_PHYERR
;
2914 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2915 * and probes for any BSSID, this needs testing */
2916 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
2917 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
2919 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2920 * set we should only pass on control frames for this
2921 * station. This needs testing. I believe right now this
2922 * enables *all* control frames, which is OK.. but
2923 * but we should see if we can improve on granularity */
2924 if (*new_flags
& FIF_CONTROL
)
2925 rfilt
|= AR5K_RX_FILTER_CONTROL
;
2927 /* Additional settings per mode -- this is per ath5k */
2929 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2931 if (sc
->opmode
== IEEE80211_IF_TYPE_MNTR
)
2932 rfilt
|= AR5K_RX_FILTER_CONTROL
| AR5K_RX_FILTER_BEACON
|
2933 AR5K_RX_FILTER_PROBEREQ
| AR5K_RX_FILTER_PROM
;
2934 if (sc
->opmode
!= IEEE80211_IF_TYPE_STA
)
2935 rfilt
|= AR5K_RX_FILTER_PROBEREQ
;
2936 if (sc
->opmode
!= IEEE80211_IF_TYPE_AP
&&
2937 test_bit(ATH_STAT_PROMISC
, sc
->status
))
2938 rfilt
|= AR5K_RX_FILTER_PROM
;
2939 if (sc
->opmode
== IEEE80211_IF_TYPE_STA
||
2940 sc
->opmode
== IEEE80211_IF_TYPE_IBSS
) {
2941 rfilt
|= AR5K_RX_FILTER_BEACON
;
2945 ath5k_hw_set_rx_filter(ah
,rfilt
);
2947 /* Set multicast bits */
2948 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
2949 /* Set the cached hw filter flags, this will alter actually
2951 sc
->filter_flags
= rfilt
;
2955 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
2956 const u8
*local_addr
, const u8
*addr
,
2957 struct ieee80211_key_conf
*key
)
2959 struct ath5k_softc
*sc
= hw
->priv
;
2964 /* XXX: fix hardware encryption, its not working. For now
2965 * allow software encryption */
2975 mutex_lock(&sc
->lock
);
2979 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
, addr
);
2981 ATH5K_ERR(sc
, "can't set the key\n");
2984 __set_bit(key
->keyidx
, sc
->keymap
);
2985 key
->hw_key_idx
= key
->keyidx
;
2988 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
2989 __clear_bit(key
->keyidx
, sc
->keymap
);
2997 mutex_unlock(&sc
->lock
);
3002 ath5k_get_stats(struct ieee80211_hw
*hw
,
3003 struct ieee80211_low_level_stats
*stats
)
3005 struct ath5k_softc
*sc
= hw
->priv
;
3006 struct ath5k_hw
*ah
= sc
->ah
;
3009 ath5k_hw_update_mib_counters(ah
, &sc
->ll_stats
);
3011 memcpy(stats
, &sc
->ll_stats
, sizeof(sc
->ll_stats
));
3017 ath5k_get_tx_stats(struct ieee80211_hw
*hw
,
3018 struct ieee80211_tx_queue_stats
*stats
)
3020 struct ath5k_softc
*sc
= hw
->priv
;
3022 memcpy(stats
, &sc
->tx_stats
, sizeof(sc
->tx_stats
));
3028 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3030 struct ath5k_softc
*sc
= hw
->priv
;
3032 return ath5k_hw_get_tsf64(sc
->ah
);
3036 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3038 struct ath5k_softc
*sc
= hw
->priv
;
3041 * in IBSS mode we need to update the beacon timers too.
3042 * this will also reset the TSF if we call it with 0
3044 if (sc
->opmode
== IEEE80211_IF_TYPE_IBSS
)
3045 ath5k_beacon_update_timers(sc
, 0);
3047 ath5k_hw_reset_tsf(sc
->ah
);
3051 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
3052 struct ieee80211_tx_control
*ctl
)
3054 struct ath5k_softc
*sc
= hw
->priv
;
3057 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3059 mutex_lock(&sc
->lock
);
3061 if (sc
->opmode
!= IEEE80211_IF_TYPE_IBSS
) {
3066 ath5k_txbuf_free(sc
, sc
->bbuf
);
3067 sc
->bbuf
->skb
= skb
;
3068 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
, ctl
);
3070 sc
->bbuf
->skb
= NULL
;
3072 ath5k_beacon_config(sc
);
3075 mutex_unlock(&sc
->lock
);