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Merge branches 'pxa-ian' and 'pxa-xm270' into pxa
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath5k / hw.c
1 /*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23 /*
24 * HW related functions for Atheros Wireless LAN devices.
25 */
26
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29
30 #include "reg.h"
31 #include "base.h"
32 #include "debug.h"
33
34 /*Rate tables*/
35 static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A;
36 static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B;
37 static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G;
38 static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO;
39 static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
40
41 /*Prototypes*/
42 static int ath5k_hw_nic_reset(struct ath5k_hw *, u32);
43 static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool);
44 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
45 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
46 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
47 unsigned int, unsigned int);
48 static int ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
49 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
50 unsigned int);
51 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
52 struct ath5k_tx_status *);
53 static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
54 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
55 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
56 unsigned int, unsigned int);
57 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *,
58 struct ath5k_tx_status *);
59 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *, struct ath5k_desc *,
60 struct ath5k_rx_status *);
61 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *, struct ath5k_desc *,
62 struct ath5k_rx_status *);
63 static int ath5k_hw_get_capabilities(struct ath5k_hw *);
64
65 static int ath5k_eeprom_init(struct ath5k_hw *);
66 static int ath5k_eeprom_read_mac(struct ath5k_hw *, u8 *);
67
68 static int ath5k_hw_enable_pspoll(struct ath5k_hw *, u8 *, u16);
69 static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
70
71 /*
72 * Enable to overwrite the country code (use "00" for debug)
73 */
74 #if 0
75 #define COUNTRYCODE "00"
76 #endif
77
78 /*******************\
79 General Functions
80 \*******************/
81
82 /*
83 * Functions used internaly
84 */
85
86 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
87 {
88 return turbo ? (usec * 80) : (usec * 40);
89 }
90
91 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
92 {
93 return turbo ? (clock / 80) : (clock / 40);
94 }
95
96 /*
97 * Check if a register write has been completed
98 */
99 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
100 bool is_set)
101 {
102 int i;
103 u32 data;
104
105 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
106 data = ath5k_hw_reg_read(ah, reg);
107 if (is_set && (data & flag))
108 break;
109 else if ((data & flag) == val)
110 break;
111 udelay(15);
112 }
113
114 return (i <= 0) ? -EAGAIN : 0;
115 }
116
117
118 /***************************************\
119 Attach/Detach Functions
120 \***************************************/
121
122 /*
123 * Power On Self Test helper function
124 */
125 static int ath5k_hw_post(struct ath5k_hw *ah)
126 {
127
128 int i, c;
129 u16 cur_reg;
130 u16 regs[2] = {AR5K_STA_ID0, AR5K_PHY(8)};
131 u32 var_pattern;
132 u32 static_pattern[4] = {
133 0x55555555, 0xaaaaaaaa,
134 0x66666666, 0x99999999
135 };
136 u32 init_val;
137 u32 cur_val;
138
139 for (c = 0; c < 2; c++) {
140
141 cur_reg = regs[c];
142 init_val = ath5k_hw_reg_read(ah, cur_reg);
143
144 for (i = 0; i < 256; i++) {
145 var_pattern = i << 16 | i;
146 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
147 cur_val = ath5k_hw_reg_read(ah, cur_reg);
148
149 if (cur_val != var_pattern) {
150 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
151 return -EAGAIN;
152 }
153
154 /* Found on ndiswrapper dumps */
155 var_pattern = 0x0039080f;
156 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
157 }
158
159 for (i = 0; i < 4; i++) {
160 var_pattern = static_pattern[i];
161 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
162 cur_val = ath5k_hw_reg_read(ah, cur_reg);
163
164 if (cur_val != var_pattern) {
165 ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
166 return -EAGAIN;
167 }
168
169 /* Found on ndiswrapper dumps */
170 var_pattern = 0x003b080f;
171 ath5k_hw_reg_write(ah, var_pattern, cur_reg);
172 }
173 }
174
175 return 0;
176
177 }
178
179 /*
180 * Check if the device is supported and initialize the needed structs
181 */
182 struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
183 {
184 struct ath5k_hw *ah;
185 struct pci_dev *pdev = sc->pdev;
186 u8 mac[ETH_ALEN];
187 int ret;
188 u32 srev;
189
190 /*If we passed the test malloc a ath5k_hw struct*/
191 ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
192 if (ah == NULL) {
193 ret = -ENOMEM;
194 ATH5K_ERR(sc, "out of memory\n");
195 goto err;
196 }
197
198 ah->ah_sc = sc;
199 ah->ah_iobase = sc->iobase;
200
201 /*
202 * HW information
203 */
204
205 ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
206 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
207 ah->ah_turbo = false;
208 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
209 ah->ah_imr = 0;
210 ah->ah_atim_window = 0;
211 ah->ah_aifs = AR5K_TUNE_AIFS;
212 ah->ah_cw_min = AR5K_TUNE_CWMIN;
213 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
214 ah->ah_software_retry = false;
215 ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
216
217 /*
218 * Set the mac revision based on the pci id
219 */
220 ah->ah_version = mac_version;
221
222 /*Fill the ath5k_hw struct with the needed functions*/
223 if (ah->ah_version == AR5K_AR5212)
224 ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
225 else if (ah->ah_version == AR5K_AR5211)
226 ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
227
228 if (ah->ah_version == AR5K_AR5212) {
229 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
230 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
231 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
232 } else {
233 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
234 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
235 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
236 }
237
238 if (ah->ah_version == AR5K_AR5212)
239 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
240 else if (ah->ah_version <= AR5K_AR5211)
241 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
242
243 /* Bring device out of sleep and reset it's units */
244 ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true);
245 if (ret)
246 goto err_free;
247
248 /* Get MAC, PHY and RADIO revisions */
249 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
250 ah->ah_mac_srev = srev;
251 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
252 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
253 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
254 0xffffffff;
255 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
256 CHANNEL_5GHZ);
257
258 if (ah->ah_version == AR5K_AR5210)
259 ah->ah_radio_2ghz_revision = 0;
260 else
261 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
262 CHANNEL_2GHZ);
263
264 /* Return on unsuported chips (unsupported eeprom etc) */
265 if ((srev >= AR5K_SREV_VER_AR5416) &&
266 (srev < AR5K_SREV_VER_AR2425)) {
267 ATH5K_ERR(sc, "Device not yet supported.\n");
268 ret = -ENODEV;
269 goto err_free;
270 } else if (srev == AR5K_SREV_VER_AR2425) {
271 ATH5K_WARN(sc, "Support for RF2425 is under development.\n");
272 }
273
274 /* Identify single chip solutions */
275 if (((srev <= AR5K_SREV_VER_AR5414) &&
276 (srev >= AR5K_SREV_VER_AR2413)) ||
277 (srev == AR5K_SREV_VER_AR2425)) {
278 ah->ah_single_chip = true;
279 } else {
280 ah->ah_single_chip = false;
281 }
282
283 /* Single chip radio */
284 if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
285 ah->ah_radio_2ghz_revision = 0;
286
287 /* Identify the radio chip*/
288 if (ah->ah_version == AR5K_AR5210) {
289 ah->ah_radio = AR5K_RF5110;
290 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
291 ah->ah_radio = AR5K_RF5111;
292 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5111;
293 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC0) {
294
295 ah->ah_radio = AR5K_RF5112;
296
297 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
298 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
299 } else {
300 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
301 }
302
303 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
304 ah->ah_radio = AR5K_RF2413;
305 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
306 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC2) {
307 ah->ah_radio = AR5K_RF5413;
308 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
309 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5133) {
310
311 /* AR5424 */
312 if (srev >= AR5K_SREV_VER_AR5424) {
313 ah->ah_radio = AR5K_RF5413;
314 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5424;
315 /* AR2424 */
316 } else {
317 ah->ah_radio = AR5K_RF2413; /* For testing */
318 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112A;
319 }
320
321 /*
322 * Register returns 0x4 for radio revision
323 * so ath5k_hw_radio_revision doesn't parse the value
324 * correctly. For now we are based on mac's srev to
325 * identify RF2425 radio.
326 */
327 } else if (srev == AR5K_SREV_VER_AR2425) {
328 ah->ah_radio = AR5K_RF2425;
329 ah->ah_phy_spending = AR5K_PHY_SPENDING_RF5112;
330 }
331
332 ah->ah_phy = AR5K_PHY(0);
333
334 /*
335 * Identify AR5212-based PCI-E cards
336 * And write some initial settings.
337 *
338 * (doing a "strings" on ndis driver
339 * -ar5211.sys- reveals the following
340 * pci-e related functions:
341 *
342 * pcieClockReq
343 * pcieRxErrNotify
344 * pcieL1SKPEnable
345 * pcieAspm
346 * pcieDisableAspmOnRfWake
347 * pciePowerSaveEnable
348 *
349 * I guess these point to ClockReq but
350 * i'm not sure.)
351 */
352 if ((ah->ah_version == AR5K_AR5212) && (pdev->is_pcie)) {
353 ath5k_hw_reg_write(ah, 0x9248fc00, 0x4080);
354 ath5k_hw_reg_write(ah, 0x24924924, 0x4080);
355 ath5k_hw_reg_write(ah, 0x28000039, 0x4080);
356 ath5k_hw_reg_write(ah, 0x53160824, 0x4080);
357 ath5k_hw_reg_write(ah, 0xe5980579, 0x4080);
358 ath5k_hw_reg_write(ah, 0x001defff, 0x4080);
359 ath5k_hw_reg_write(ah, 0x1aaabe40, 0x4080);
360 ath5k_hw_reg_write(ah, 0xbe105554, 0x4080);
361 ath5k_hw_reg_write(ah, 0x000e3007, 0x4080);
362 ath5k_hw_reg_write(ah, 0x00000000, 0x4084);
363 }
364
365 /*
366 * POST
367 */
368 ret = ath5k_hw_post(ah);
369 if (ret)
370 goto err_free;
371
372 /*
373 * Get card capabilities, values, ...
374 */
375
376 ret = ath5k_eeprom_init(ah);
377 if (ret) {
378 ATH5K_ERR(sc, "unable to init EEPROM\n");
379 goto err_free;
380 }
381
382 /* Get misc capabilities */
383 ret = ath5k_hw_get_capabilities(ah);
384 if (ret) {
385 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
386 sc->pdev->device);
387 goto err_free;
388 }
389
390 /* Get MAC address */
391 ret = ath5k_eeprom_read_mac(ah, mac);
392 if (ret) {
393 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
394 sc->pdev->device);
395 goto err_free;
396 }
397
398 ath5k_hw_set_lladdr(ah, mac);
399 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
400 memset(ah->ah_bssid, 0xff, ETH_ALEN);
401 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
402 ath5k_hw_set_opmode(ah);
403
404 ath5k_hw_set_rfgain_opt(ah);
405
406 return ah;
407 err_free:
408 kfree(ah);
409 err:
410 return ERR_PTR(ret);
411 }
412
413 /*
414 * Bring up MAC + PHY Chips
415 */
416 static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
417 {
418 struct pci_dev *pdev = ah->ah_sc->pdev;
419 u32 turbo, mode, clock, bus_flags;
420 int ret;
421
422 turbo = 0;
423 mode = 0;
424 clock = 0;
425
426 ATH5K_TRACE(ah->ah_sc);
427
428 /* Wakeup the device */
429 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
430 if (ret) {
431 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
432 return ret;
433 }
434
435 if (ah->ah_version != AR5K_AR5210) {
436 /*
437 * Get channel mode flags
438 */
439
440 if (ah->ah_radio >= AR5K_RF5112) {
441 mode = AR5K_PHY_MODE_RAD_RF5112;
442 clock = AR5K_PHY_PLL_RF5112;
443 } else {
444 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
445 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
446 }
447
448 if (flags & CHANNEL_2GHZ) {
449 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
450 clock |= AR5K_PHY_PLL_44MHZ;
451
452 if (flags & CHANNEL_CCK) {
453 mode |= AR5K_PHY_MODE_MOD_CCK;
454 } else if (flags & CHANNEL_OFDM) {
455 /* XXX Dynamic OFDM/CCK is not supported by the
456 * AR5211 so we set MOD_OFDM for plain g (no
457 * CCK headers) operation. We need to test
458 * this, 5211 might support ofdm-only g after
459 * all, there are also initial register values
460 * in the code for g mode (see initvals.c). */
461 if (ah->ah_version == AR5K_AR5211)
462 mode |= AR5K_PHY_MODE_MOD_OFDM;
463 else
464 mode |= AR5K_PHY_MODE_MOD_DYN;
465 } else {
466 ATH5K_ERR(ah->ah_sc,
467 "invalid radio modulation mode\n");
468 return -EINVAL;
469 }
470 } else if (flags & CHANNEL_5GHZ) {
471 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
472 clock |= AR5K_PHY_PLL_40MHZ;
473
474 if (flags & CHANNEL_OFDM)
475 mode |= AR5K_PHY_MODE_MOD_OFDM;
476 else {
477 ATH5K_ERR(ah->ah_sc,
478 "invalid radio modulation mode\n");
479 return -EINVAL;
480 }
481 } else {
482 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
483 return -EINVAL;
484 }
485
486 if (flags & CHANNEL_TURBO)
487 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
488 } else { /* Reset the device */
489
490 /* ...enable Atheros turbo mode if requested */
491 if (flags & CHANNEL_TURBO)
492 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
493 AR5K_PHY_TURBO);
494 }
495
496 /* reseting PCI on PCI-E cards results card to hang
497 * and always return 0xffff... so we ingore that flag
498 * for PCI-E cards */
499 bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
500
501 /* Reset chipset */
502 ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
503 AR5K_RESET_CTL_BASEBAND | bus_flags);
504 if (ret) {
505 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
506 return -EIO;
507 }
508
509 if (ah->ah_version == AR5K_AR5210)
510 udelay(2300);
511
512 /* ...wakeup again!*/
513 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
514 if (ret) {
515 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
516 return ret;
517 }
518
519 /* ...final warm reset */
520 if (ath5k_hw_nic_reset(ah, 0)) {
521 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
522 return -EIO;
523 }
524
525 if (ah->ah_version != AR5K_AR5210) {
526 /* ...set the PHY operating mode */
527 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
528 udelay(300);
529
530 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
531 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
532 }
533
534 return 0;
535 }
536
537 /*
538 * Get the rate table for a specific operation mode
539 */
540 const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah,
541 unsigned int mode)
542 {
543 ATH5K_TRACE(ah->ah_sc);
544
545 if (!test_bit(mode, ah->ah_capabilities.cap_mode))
546 return NULL;
547
548 /* Get rate tables */
549 switch (mode) {
550 case AR5K_MODE_11A:
551 return &ath5k_rt_11a;
552 case AR5K_MODE_11A_TURBO:
553 return &ath5k_rt_turbo;
554 case AR5K_MODE_11B:
555 return &ath5k_rt_11b;
556 case AR5K_MODE_11G:
557 return &ath5k_rt_11g;
558 case AR5K_MODE_11G_TURBO:
559 return &ath5k_rt_xr;
560 }
561
562 return NULL;
563 }
564
565 /*
566 * Free the ath5k_hw struct
567 */
568 void ath5k_hw_detach(struct ath5k_hw *ah)
569 {
570 ATH5K_TRACE(ah->ah_sc);
571
572 __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
573
574 if (ah->ah_rf_banks != NULL)
575 kfree(ah->ah_rf_banks);
576
577 /* assume interrupts are down */
578 kfree(ah);
579 }
580
581 /****************************\
582 Reset function and helpers
583 \****************************/
584
585 /**
586 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
587 *
588 * @ah: the &struct ath5k_hw
589 * @channel: the currently set channel upon reset
590 *
591 * Write the OFDM timings for the AR5212 upon reset. This is a helper for
592 * ath5k_hw_reset(). This seems to tune the PLL a specified frequency
593 * depending on the bandwidth of the channel.
594 *
595 */
596 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
597 struct ieee80211_channel *channel)
598 {
599 /* Get exponent and mantissa and set it */
600 u32 coef_scaled, coef_exp, coef_man,
601 ds_coef_exp, ds_coef_man, clock;
602
603 if (!(ah->ah_version == AR5K_AR5212) ||
604 !(channel->hw_value & CHANNEL_OFDM))
605 BUG();
606
607 /* Seems there are two PLLs, one for baseband sampling and one
608 * for tuning. Tuning basebands are 40 MHz or 80MHz when in
609 * turbo. */
610 clock = channel->hw_value & CHANNEL_TURBO ? 80 : 40;
611 coef_scaled = ((5 * (clock << 24)) / 2) /
612 channel->center_freq;
613
614 for (coef_exp = 31; coef_exp > 0; coef_exp--)
615 if ((coef_scaled >> coef_exp) & 0x1)
616 break;
617
618 if (!coef_exp)
619 return -EINVAL;
620
621 coef_exp = 14 - (coef_exp - 24);
622 coef_man = coef_scaled +
623 (1 << (24 - coef_exp - 1));
624 ds_coef_man = coef_man >> (24 - coef_exp);
625 ds_coef_exp = coef_exp - 16;
626
627 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
628 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
629 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
630 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
631
632 return 0;
633 }
634
635 /**
636 * ath5k_hw_write_rate_duration - set rate duration during hw resets
637 *
638 * @ah: the &struct ath5k_hw
639 * @mode: one of enum ath5k_driver_mode
640 *
641 * Write the rate duration table for the current mode upon hw reset. This
642 * is a helper for ath5k_hw_reset(). It seems all this is doing is setting
643 * an ACK timeout for the hardware for the current mode for each rate. The
644 * rates which are capable of short preamble (802.11b rates 2Mbps, 5.5Mbps,
645 * and 11Mbps) have another register for the short preamble ACK timeout
646 * calculation.
647 *
648 */
649 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
650 unsigned int mode)
651 {
652 struct ath5k_softc *sc = ah->ah_sc;
653 const struct ath5k_rate_table *rt;
654 struct ieee80211_rate srate = {};
655 unsigned int i;
656
657 /* Get rate table for the current operating mode */
658 rt = ath5k_hw_get_rate_table(ah, mode);
659
660 /* Write rate duration table */
661 for (i = 0; i < rt->rate_count; i++) {
662 const struct ath5k_rate *rate, *control_rate;
663
664 u32 reg;
665 u16 tx_time;
666
667 rate = &rt->rates[i];
668 control_rate = &rt->rates[rate->control_rate];
669
670 /* Set ACK timeout */
671 reg = AR5K_RATE_DUR(rate->rate_code);
672
673 srate.bitrate = control_rate->rate_kbps/100;
674
675 /* An ACK frame consists of 10 bytes. If you add the FCS,
676 * which ieee80211_generic_frame_duration() adds,
677 * its 14 bytes. Note we use the control rate and not the
678 * actual rate for this rate. See mac80211 tx.c
679 * ieee80211_duration() for a brief description of
680 * what rate we should choose to TX ACKs. */
681 tx_time = le16_to_cpu(ieee80211_generic_frame_duration(sc->hw,
682 sc->vif, 10, &srate));
683
684 ath5k_hw_reg_write(ah, tx_time, reg);
685
686 if (!HAS_SHPREAMBLE(i))
687 continue;
688
689 /*
690 * We're not distinguishing short preamble here,
691 * This is true, all we'll get is a longer value here
692 * which is not necessarilly bad. We could use
693 * export ieee80211_frame_duration() but that needs to be
694 * fixed first to be properly used by mac802111 drivers:
695 *
696 * - remove erp stuff and let the routine figure ofdm
697 * erp rates
698 * - remove passing argument ieee80211_local as
699 * drivers don't have access to it
700 * - move drivers using ieee80211_generic_frame_duration()
701 * to this
702 */
703 ath5k_hw_reg_write(ah, tx_time,
704 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
705 }
706 }
707
708 /*
709 * Main reset function
710 */
711 int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
712 struct ieee80211_channel *channel, bool change_channel)
713 {
714 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
715 struct pci_dev *pdev = ah->ah_sc->pdev;
716 u32 data, s_seq, s_ant, s_led[3], dma_size;
717 unsigned int i, mode, freq, ee_mode, ant[2];
718 int ret;
719
720 ATH5K_TRACE(ah->ah_sc);
721
722 s_seq = 0;
723 s_ant = 0;
724 ee_mode = 0;
725 freq = 0;
726 mode = 0;
727
728 /*
729 * Save some registers before a reset
730 */
731 /*DCU/Antenna selection not available on 5210*/
732 if (ah->ah_version != AR5K_AR5210) {
733 if (change_channel) {
734 /* Seq number for queue 0 -do this for all queues ? */
735 s_seq = ath5k_hw_reg_read(ah,
736 AR5K_QUEUE_DFS_SEQNUM(0));
737 /*Default antenna*/
738 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
739 }
740 }
741
742 /*GPIOs*/
743 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
744 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
745 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
746
747 if (change_channel && ah->ah_rf_banks != NULL)
748 ath5k_hw_get_rf_gain(ah);
749
750
751 /*Wakeup the device*/
752 ret = ath5k_hw_nic_wakeup(ah, channel->hw_value, false);
753 if (ret)
754 return ret;
755
756 /*
757 * Initialize operating mode
758 */
759 ah->ah_op_mode = op_mode;
760
761 /*
762 * 5111/5112 Settings
763 * 5210 only comes with RF5110
764 */
765 if (ah->ah_version != AR5K_AR5210) {
766 if (ah->ah_radio != AR5K_RF5111 &&
767 ah->ah_radio != AR5K_RF5112 &&
768 ah->ah_radio != AR5K_RF5413 &&
769 ah->ah_radio != AR5K_RF2413 &&
770 ah->ah_radio != AR5K_RF2425) {
771 ATH5K_ERR(ah->ah_sc,
772 "invalid phy radio: %u\n", ah->ah_radio);
773 return -EINVAL;
774 }
775
776 switch (channel->hw_value & CHANNEL_MODES) {
777 case CHANNEL_A:
778 mode = AR5K_MODE_11A;
779 freq = AR5K_INI_RFGAIN_5GHZ;
780 ee_mode = AR5K_EEPROM_MODE_11A;
781 break;
782 case CHANNEL_G:
783 mode = AR5K_MODE_11G;
784 freq = AR5K_INI_RFGAIN_2GHZ;
785 ee_mode = AR5K_EEPROM_MODE_11G;
786 break;
787 case CHANNEL_B:
788 mode = AR5K_MODE_11B;
789 freq = AR5K_INI_RFGAIN_2GHZ;
790 ee_mode = AR5K_EEPROM_MODE_11B;
791 break;
792 case CHANNEL_T:
793 mode = AR5K_MODE_11A_TURBO;
794 freq = AR5K_INI_RFGAIN_5GHZ;
795 ee_mode = AR5K_EEPROM_MODE_11A;
796 break;
797 /*Is this ok on 5211 too ?*/
798 case CHANNEL_TG:
799 mode = AR5K_MODE_11G_TURBO;
800 freq = AR5K_INI_RFGAIN_2GHZ;
801 ee_mode = AR5K_EEPROM_MODE_11G;
802 break;
803 case CHANNEL_XR:
804 if (ah->ah_version == AR5K_AR5211) {
805 ATH5K_ERR(ah->ah_sc,
806 "XR mode not available on 5211");
807 return -EINVAL;
808 }
809 mode = AR5K_MODE_XR;
810 freq = AR5K_INI_RFGAIN_5GHZ;
811 ee_mode = AR5K_EEPROM_MODE_11A;
812 break;
813 default:
814 ATH5K_ERR(ah->ah_sc,
815 "invalid channel: %d\n", channel->center_freq);
816 return -EINVAL;
817 }
818
819 /* PHY access enable */
820 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
821
822 }
823
824 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
825 if (ret)
826 return ret;
827
828 /*
829 * 5211/5212 Specific
830 */
831 if (ah->ah_version != AR5K_AR5210) {
832 /*
833 * Write initial RF gain settings
834 * This should work for both 5111/5112
835 */
836 ret = ath5k_hw_rfgain(ah, freq);
837 if (ret)
838 return ret;
839
840 mdelay(1);
841
842 /*
843 * Write some more initial register settings
844 */
845 if (ah->ah_version == AR5K_AR5212) {
846 ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11));
847
848 if (channel->hw_value == CHANNEL_G)
849 if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413)
850 ath5k_hw_reg_write(ah, 0x00f80d80,
851 AR5K_PHY(83));
852 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424)
853 ath5k_hw_reg_write(ah, 0x00380140,
854 AR5K_PHY(83));
855 else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425)
856 ath5k_hw_reg_write(ah, 0x00fc0ec0,
857 AR5K_PHY(83));
858 else /* 2425 */
859 ath5k_hw_reg_write(ah, 0x00fc0fc0,
860 AR5K_PHY(83));
861 else
862 ath5k_hw_reg_write(ah, 0x00000000,
863 AR5K_PHY(83));
864
865 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);
866 ath5k_hw_reg_write(ah, 0x0000000f, 0x8060);
867 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
868 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
869 }
870
871 /* Fix for first revision of the RF5112 RF chipset */
872 if (ah->ah_radio >= AR5K_RF5112 &&
873 ah->ah_radio_5ghz_revision <
874 AR5K_SREV_RAD_5112A) {
875 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
876 AR5K_PHY_CCKTXCTL);
877 if (channel->hw_value & CHANNEL_5GHZ)
878 data = 0xffb81020;
879 else
880 data = 0xffb80d20;
881 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
882 }
883
884 /*
885 * Set TX power (FIXME)
886 */
887 ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER);
888 if (ret)
889 return ret;
890
891 /* Write rate duration table only on AR5212 and if
892 * virtual interface has already been brought up
893 * XXX: rethink this after new mode changes to
894 * mac80211 are integrated */
895 if (ah->ah_version == AR5K_AR5212 &&
896 ah->ah_sc->vif != NULL)
897 ath5k_hw_write_rate_duration(ah, mode);
898
899 /*
900 * Write RF registers
901 * TODO:Does this work on 5211 (5111) ?
902 */
903 ret = ath5k_hw_rfregs(ah, channel, mode);
904 if (ret)
905 return ret;
906
907 /*
908 * Configure additional registers
909 */
910
911 /* Write OFDM timings on 5212*/
912 if (ah->ah_version == AR5K_AR5212 &&
913 channel->hw_value & CHANNEL_OFDM) {
914 ret = ath5k_hw_write_ofdm_timings(ah, channel);
915 if (ret)
916 return ret;
917 }
918
919 /*Enable/disable 802.11b mode on 5111
920 (enable 2111 frequency converter + CCK)*/
921 if (ah->ah_radio == AR5K_RF5111) {
922 if (mode == AR5K_MODE_11B)
923 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
924 AR5K_TXCFG_B_MODE);
925 else
926 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
927 AR5K_TXCFG_B_MODE);
928 }
929
930 /*
931 * Set channel and calibrate the PHY
932 */
933 ret = ath5k_hw_channel(ah, channel);
934 if (ret)
935 return ret;
936
937 /* Set antenna mode */
938 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x44),
939 ah->ah_antenna[ee_mode][0], 0xfffffc06);
940
941 /*
942 * In case a fixed antenna was set as default
943 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
944 * registers.
945 */
946 if (s_ant != 0){
947 if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
948 ant[0] = ant[1] = AR5K_ANT_FIXED_A;
949 else /* 2 - Aux */
950 ant[0] = ant[1] = AR5K_ANT_FIXED_B;
951 } else {
952 ant[0] = AR5K_ANT_FIXED_A;
953 ant[1] = AR5K_ANT_FIXED_B;
954 }
955
956 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
957 AR5K_PHY_ANT_SWITCH_TABLE_0);
958 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
959 AR5K_PHY_ANT_SWITCH_TABLE_1);
960
961 /* Commit values from EEPROM */
962 if (ah->ah_radio == AR5K_RF5111)
963 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
964 AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip);
965
966 ath5k_hw_reg_write(ah,
967 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
968 AR5K_PHY(0x5a));
969
970 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x11),
971 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
972 0xffffc07f);
973 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x12),
974 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
975 0xfffc0fff);
976 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x14),
977 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
978 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
979 0xffff0000);
980
981 ath5k_hw_reg_write(ah,
982 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
983 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
984 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
985 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d));
986
987 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x0a),
988 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
989 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x19),
990 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
991 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x49), 4, 0xffffff01);
992
993 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
994 AR5K_PHY_IQ_CORR_ENABLE |
995 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
996 ee->ee_q_cal[ee_mode]);
997
998 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
999 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
1000 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
1001 ee->ee_margin_tx_rx[ee_mode]);
1002
1003 } else {
1004 mdelay(1);
1005 /* Disable phy and wait */
1006 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
1007 mdelay(1);
1008 }
1009
1010 /*
1011 * Restore saved values
1012 */
1013 /*DCU/Antenna selection not available on 5210*/
1014 if (ah->ah_version != AR5K_AR5210) {
1015 ath5k_hw_reg_write(ah, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
1016 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
1017 }
1018 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
1019 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
1020 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
1021
1022 /*
1023 * Misc
1024 */
1025 /* XXX: add ah->aid once mac80211 gives this to us */
1026 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
1027
1028 ath5k_hw_set_opmode(ah);
1029 /*PISR/SISR Not available on 5210*/
1030 if (ah->ah_version != AR5K_AR5210) {
1031 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
1032 /* If we later allow tuning for this, store into sc structure */
1033 data = AR5K_TUNE_RSSI_THRES |
1034 AR5K_TUNE_BMISS_THRES << AR5K_RSSI_THR_BMISS_S;
1035 ath5k_hw_reg_write(ah, data, AR5K_RSSI_THR);
1036 }
1037
1038 /*
1039 * Set Rx/Tx DMA Configuration
1040 *
1041 * Set maximum DMA size (512) except for PCI-E cards since
1042 * it causes rx overruns and tx errors (tested on 5424 but since
1043 * rx overruns also occur on 5416/5418 with madwifi we set 128
1044 * for all PCI-E cards to be safe).
1045 *
1046 * In dumps this is 128 for allchips.
1047 *
1048 * XXX: need to check 5210 for this
1049 * TODO: Check out tx triger level, it's always 64 on dumps but I
1050 * guess we can tweak it and see how it goes ;-)
1051 */
1052 dma_size = (pdev->is_pcie) ? AR5K_DMASIZE_128B : AR5K_DMASIZE_512B;
1053 if (ah->ah_version != AR5K_AR5210) {
1054 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1055 AR5K_TXCFG_SDMAMR, dma_size);
1056 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG,
1057 AR5K_RXCFG_SDMAMW, dma_size);
1058 }
1059
1060 /*
1061 * Enable the PHY and wait until completion
1062 */
1063 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1064
1065 /*
1066 * 5111/5112 Specific
1067 */
1068 if (ah->ah_version != AR5K_AR5210) {
1069 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
1070 AR5K_PHY_RX_DELAY_M;
1071 data = (channel->hw_value & CHANNEL_CCK) ?
1072 ((data << 2) / 22) : (data / 10);
1073
1074 udelay(100 + data);
1075 } else {
1076 mdelay(1);
1077 }
1078
1079 /*
1080 * Enable calibration and wait until completion
1081 */
1082 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1083 AR5K_PHY_AGCCTL_CAL);
1084
1085 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1086 AR5K_PHY_AGCCTL_CAL, 0, false)) {
1087 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1088 channel->center_freq);
1089 return -EAGAIN;
1090 }
1091
1092 ret = ath5k_hw_noise_floor_calibration(ah, channel->center_freq);
1093 if (ret)
1094 return ret;
1095
1096 ah->ah_calibration = false;
1097
1098 /* A and G modes can use QAM modulation which requires enabling
1099 * I and Q calibration. Don't bother in B mode. */
1100 if (!(mode == AR5K_MODE_11B)) {
1101 ah->ah_calibration = true;
1102 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1103 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1104 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1105 AR5K_PHY_IQ_RUN);
1106 }
1107
1108 /*
1109 * Reset queues and start beacon timers at the end of the reset routine
1110 */
1111 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
1112 /*No QCU on 5210*/
1113 if (ah->ah_version != AR5K_AR5210)
1114 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(i), i);
1115
1116 ret = ath5k_hw_reset_tx_queue(ah, i);
1117 if (ret) {
1118 ATH5K_ERR(ah->ah_sc,
1119 "failed to reset TX queue #%d\n", i);
1120 return ret;
1121 }
1122 }
1123
1124 /* Pre-enable interrupts on 5211/5212*/
1125 if (ah->ah_version != AR5K_AR5210)
1126 ath5k_hw_set_intr(ah, AR5K_INT_RX | AR5K_INT_TX |
1127 AR5K_INT_FATAL);
1128
1129 /*
1130 * Set RF kill flags if supported by the device (read from the EEPROM)
1131 * Disable gpio_intr for now since it results system hang.
1132 * TODO: Handle this in ath5k_intr
1133 */
1134 #if 0
1135 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
1136 ath5k_hw_set_gpio_input(ah, 0);
1137 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
1138 if (ah->ah_gpio[0] == 0)
1139 ath5k_hw_set_gpio_intr(ah, 0, 1);
1140 else
1141 ath5k_hw_set_gpio_intr(ah, 0, 0);
1142 }
1143 #endif
1144
1145 /*
1146 * Set the 32MHz reference clock on 5212 phy clock sleep register
1147 *
1148 * TODO: Find out how to switch to external 32Khz clock to save power
1149 */
1150 if (ah->ah_version == AR5K_AR5212) {
1151 ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
1152 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
1153 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL);
1154 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
1155 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
1156 ath5k_hw_reg_write(ah, ah->ah_phy_spending, AR5K_PHY_SPENDING);
1157 }
1158
1159 if (ah->ah_version == AR5K_AR5212) {
1160 ath5k_hw_reg_write(ah, 0x000100aa, 0x8118);
1161 ath5k_hw_reg_write(ah, 0x00003210, 0x811c);
1162 ath5k_hw_reg_write(ah, 0x00000052, 0x8108);
1163 if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2413)
1164 ath5k_hw_reg_write(ah, 0x00000004, 0x8120);
1165 }
1166
1167 /*
1168 * Disable beacons and reset the register
1169 */
1170 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
1171 AR5K_BEACON_RESET_TSF);
1172
1173 return 0;
1174 }
1175
1176 /*
1177 * Reset chipset
1178 */
1179 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
1180 {
1181 int ret;
1182 u32 mask = val ? val : ~0U;
1183
1184 ATH5K_TRACE(ah->ah_sc);
1185
1186 /* Read-and-clear RX Descriptor Pointer*/
1187 ath5k_hw_reg_read(ah, AR5K_RXDP);
1188
1189 /*
1190 * Reset the device and wait until success
1191 */
1192 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
1193
1194 /* Wait at least 128 PCI clocks */
1195 udelay(15);
1196
1197 if (ah->ah_version == AR5K_AR5210) {
1198 val &= AR5K_RESET_CTL_CHIP;
1199 mask &= AR5K_RESET_CTL_CHIP;
1200 } else {
1201 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1202 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1203 }
1204
1205 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
1206
1207 /*
1208 * Reset configuration register (for hw byte-swap). Note that this
1209 * is only set for big endian. We do the necessary magic in
1210 * AR5K_INIT_CFG.
1211 */
1212 if ((val & AR5K_RESET_CTL_PCU) == 0)
1213 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
1214
1215 return ret;
1216 }
1217
1218 /*
1219 * Power management functions
1220 */
1221
1222 /*
1223 * Sleep control
1224 */
1225 int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1226 bool set_chip, u16 sleep_duration)
1227 {
1228 unsigned int i;
1229 u32 staid;
1230
1231 ATH5K_TRACE(ah->ah_sc);
1232 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
1233
1234 switch (mode) {
1235 case AR5K_PM_AUTO:
1236 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
1237 /* fallthrough */
1238 case AR5K_PM_NETWORK_SLEEP:
1239 if (set_chip)
1240 ath5k_hw_reg_write(ah,
1241 AR5K_SLEEP_CTL_SLE | sleep_duration,
1242 AR5K_SLEEP_CTL);
1243
1244 staid |= AR5K_STA_ID1_PWR_SV;
1245 break;
1246
1247 case AR5K_PM_FULL_SLEEP:
1248 if (set_chip)
1249 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
1250 AR5K_SLEEP_CTL);
1251
1252 staid |= AR5K_STA_ID1_PWR_SV;
1253 break;
1254
1255 case AR5K_PM_AWAKE:
1256 if (!set_chip)
1257 goto commit;
1258
1259 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1260 AR5K_SLEEP_CTL);
1261
1262 for (i = 5000; i > 0; i--) {
1263 /* Check if the chip did wake up */
1264 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1265 AR5K_PCICFG_SPWR_DN) == 0)
1266 break;
1267
1268 /* Wait a bit and retry */
1269 udelay(200);
1270 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1271 AR5K_SLEEP_CTL);
1272 }
1273
1274 /* Fail if the chip didn't wake up */
1275 if (i <= 0)
1276 return -EIO;
1277
1278 staid &= ~AR5K_STA_ID1_PWR_SV;
1279 break;
1280
1281 default:
1282 return -EINVAL;
1283 }
1284
1285 commit:
1286 ah->ah_power_mode = mode;
1287 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
1288
1289 return 0;
1290 }
1291
1292 /***********************\
1293 DMA Related Functions
1294 \***********************/
1295
1296 /*
1297 * Receive functions
1298 */
1299
1300 /*
1301 * Start DMA receive
1302 */
1303 void ath5k_hw_start_rx(struct ath5k_hw *ah)
1304 {
1305 ATH5K_TRACE(ah->ah_sc);
1306 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
1307 }
1308
1309 /*
1310 * Stop DMA receive
1311 */
1312 int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
1313 {
1314 unsigned int i;
1315
1316 ATH5K_TRACE(ah->ah_sc);
1317 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
1318
1319 /*
1320 * It may take some time to disable the DMA receive unit
1321 */
1322 for (i = 2000; i > 0 &&
1323 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
1324 i--)
1325 udelay(10);
1326
1327 return i ? 0 : -EBUSY;
1328 }
1329
1330 /*
1331 * Get the address of the RX Descriptor
1332 */
1333 u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah)
1334 {
1335 return ath5k_hw_reg_read(ah, AR5K_RXDP);
1336 }
1337
1338 /*
1339 * Set the address of the RX Descriptor
1340 */
1341 void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr)
1342 {
1343 ATH5K_TRACE(ah->ah_sc);
1344
1345 /*TODO:Shouldn't we check if RX is enabled first ?*/
1346 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
1347 }
1348
1349 /*
1350 * Transmit functions
1351 */
1352
1353 /*
1354 * Start DMA transmit for a specific queue
1355 * (see also QCU/DCU functions)
1356 */
1357 int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue)
1358 {
1359 u32 tx_queue;
1360
1361 ATH5K_TRACE(ah->ah_sc);
1362 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1363
1364 /* Return if queue is declared inactive */
1365 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1366 return -EIO;
1367
1368 if (ah->ah_version == AR5K_AR5210) {
1369 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1370
1371 /*
1372 * Set the queue by type on 5210
1373 */
1374 switch (ah->ah_txq[queue].tqi_type) {
1375 case AR5K_TX_QUEUE_DATA:
1376 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
1377 break;
1378 case AR5K_TX_QUEUE_BEACON:
1379 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1380 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
1381 AR5K_BSR);
1382 break;
1383 case AR5K_TX_QUEUE_CAB:
1384 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1385 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
1386 AR5K_BCR_BDMAE, AR5K_BSR);
1387 break;
1388 default:
1389 return -EINVAL;
1390 }
1391 /* Start queue */
1392 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1393 } else {
1394 /* Return if queue is disabled */
1395 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
1396 return -EIO;
1397
1398 /* Start queue */
1399 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
1400 }
1401
1402 return 0;
1403 }
1404
1405 /*
1406 * Stop DMA transmit for a specific queue
1407 * (see also QCU/DCU functions)
1408 */
1409 int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
1410 {
1411 unsigned int i = 100;
1412 u32 tx_queue, pending;
1413
1414 ATH5K_TRACE(ah->ah_sc);
1415 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1416
1417 /* Return if queue is declared inactive */
1418 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1419 return -EIO;
1420
1421 if (ah->ah_version == AR5K_AR5210) {
1422 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1423
1424 /*
1425 * Set by queue type
1426 */
1427 switch (ah->ah_txq[queue].tqi_type) {
1428 case AR5K_TX_QUEUE_DATA:
1429 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
1430 break;
1431 case AR5K_TX_QUEUE_BEACON:
1432 case AR5K_TX_QUEUE_CAB:
1433 /* XXX Fix me... */
1434 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
1435 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
1436 break;
1437 default:
1438 return -EINVAL;
1439 }
1440
1441 /* Stop queue */
1442 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1443 } else {
1444 /*
1445 * Schedule TX disable and wait until queue is empty
1446 */
1447 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
1448
1449 /*Check for pending frames*/
1450 do {
1451 pending = ath5k_hw_reg_read(ah,
1452 AR5K_QUEUE_STATUS(queue)) &
1453 AR5K_QCU_STS_FRMPENDCNT;
1454 udelay(100);
1455 } while (--i && pending);
1456
1457 /* Clear register */
1458 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
1459 }
1460
1461 /* TODO: Check for success else return error */
1462 return 0;
1463 }
1464
1465 /*
1466 * Get the address of the TX Descriptor for a specific queue
1467 * (see also QCU/DCU functions)
1468 */
1469 u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue)
1470 {
1471 u16 tx_reg;
1472
1473 ATH5K_TRACE(ah->ah_sc);
1474 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1475
1476 /*
1477 * Get the transmit queue descriptor pointer from the selected queue
1478 */
1479 /*5210 doesn't have QCU*/
1480 if (ah->ah_version == AR5K_AR5210) {
1481 switch (ah->ah_txq[queue].tqi_type) {
1482 case AR5K_TX_QUEUE_DATA:
1483 tx_reg = AR5K_NOQCU_TXDP0;
1484 break;
1485 case AR5K_TX_QUEUE_BEACON:
1486 case AR5K_TX_QUEUE_CAB:
1487 tx_reg = AR5K_NOQCU_TXDP1;
1488 break;
1489 default:
1490 return 0xffffffff;
1491 }
1492 } else {
1493 tx_reg = AR5K_QUEUE_TXDP(queue);
1494 }
1495
1496 return ath5k_hw_reg_read(ah, tx_reg);
1497 }
1498
1499 /*
1500 * Set the address of the TX Descriptor for a specific queue
1501 * (see also QCU/DCU functions)
1502 */
1503 int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
1504 {
1505 u16 tx_reg;
1506
1507 ATH5K_TRACE(ah->ah_sc);
1508 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1509
1510 /*
1511 * Set the transmit queue descriptor pointer register by type
1512 * on 5210
1513 */
1514 if (ah->ah_version == AR5K_AR5210) {
1515 switch (ah->ah_txq[queue].tqi_type) {
1516 case AR5K_TX_QUEUE_DATA:
1517 tx_reg = AR5K_NOQCU_TXDP0;
1518 break;
1519 case AR5K_TX_QUEUE_BEACON:
1520 case AR5K_TX_QUEUE_CAB:
1521 tx_reg = AR5K_NOQCU_TXDP1;
1522 break;
1523 default:
1524 return -EINVAL;
1525 }
1526 } else {
1527 /*
1528 * Set the transmit queue descriptor pointer for
1529 * the selected queue on QCU for 5211+
1530 * (this won't work if the queue is still active)
1531 */
1532 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
1533 return -EIO;
1534
1535 tx_reg = AR5K_QUEUE_TXDP(queue);
1536 }
1537
1538 /* Set descriptor pointer */
1539 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
1540
1541 return 0;
1542 }
1543
1544 /*
1545 * Update tx trigger level
1546 */
1547 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
1548 {
1549 u32 trigger_level, imr;
1550 int ret = -EIO;
1551
1552 ATH5K_TRACE(ah->ah_sc);
1553
1554 /*
1555 * Disable interrupts by setting the mask
1556 */
1557 imr = ath5k_hw_set_intr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
1558
1559 /*TODO: Boundary check on trigger_level*/
1560 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
1561 AR5K_TXCFG_TXFULL);
1562
1563 if (!increase) {
1564 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
1565 goto done;
1566 } else
1567 trigger_level +=
1568 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
1569
1570 /*
1571 * Update trigger level on success
1572 */
1573 if (ah->ah_version == AR5K_AR5210)
1574 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
1575 else
1576 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1577 AR5K_TXCFG_TXFULL, trigger_level);
1578
1579 ret = 0;
1580
1581 done:
1582 /*
1583 * Restore interrupt mask
1584 */
1585 ath5k_hw_set_intr(ah, imr);
1586
1587 return ret;
1588 }
1589
1590 /*
1591 * Interrupt handling
1592 */
1593
1594 /*
1595 * Check if we have pending interrupts
1596 */
1597 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
1598 {
1599 ATH5K_TRACE(ah->ah_sc);
1600 return ath5k_hw_reg_read(ah, AR5K_INTPEND);
1601 }
1602
1603 /*
1604 * Get interrupt mask (ISR)
1605 */
1606 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
1607 {
1608 u32 data;
1609
1610 ATH5K_TRACE(ah->ah_sc);
1611
1612 /*
1613 * Read interrupt status from the Interrupt Status register
1614 * on 5210
1615 */
1616 if (ah->ah_version == AR5K_AR5210) {
1617 data = ath5k_hw_reg_read(ah, AR5K_ISR);
1618 if (unlikely(data == AR5K_INT_NOCARD)) {
1619 *interrupt_mask = data;
1620 return -ENODEV;
1621 }
1622 } else {
1623 /*
1624 * Read interrupt status from the Read-And-Clear shadow register
1625 * Note: PISR/SISR Not available on 5210
1626 */
1627 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
1628 }
1629
1630 /*
1631 * Get abstract interrupt mask (driver-compatible)
1632 */
1633 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
1634
1635 if (unlikely(data == AR5K_INT_NOCARD))
1636 return -ENODEV;
1637
1638 if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
1639 *interrupt_mask |= AR5K_INT_RX;
1640
1641 if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR
1642 | AR5K_ISR_TXDESC | AR5K_ISR_TXEOL))
1643 *interrupt_mask |= AR5K_INT_TX;
1644
1645 if (ah->ah_version != AR5K_AR5210) {
1646 /*HIU = Host Interface Unit (PCI etc)*/
1647 if (unlikely(data & (AR5K_ISR_HIUERR)))
1648 *interrupt_mask |= AR5K_INT_FATAL;
1649
1650 /*Beacon Not Ready*/
1651 if (unlikely(data & (AR5K_ISR_BNR)))
1652 *interrupt_mask |= AR5K_INT_BNR;
1653 }
1654
1655 /*
1656 * XXX: BMISS interrupts may occur after association.
1657 * I found this on 5210 code but it needs testing. If this is
1658 * true we should disable them before assoc and re-enable them
1659 * after a successfull assoc + some jiffies.
1660 */
1661 #if 0
1662 interrupt_mask &= ~AR5K_INT_BMISS;
1663 #endif
1664
1665 /*
1666 * In case we didn't handle anything,
1667 * print the register value.
1668 */
1669 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
1670 ATH5K_PRINTF("0x%08x\n", data);
1671
1672 return 0;
1673 }
1674
1675 /*
1676 * Set interrupt mask
1677 */
1678 enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask)
1679 {
1680 enum ath5k_int old_mask, int_mask;
1681
1682 /*
1683 * Disable card interrupts to prevent any race conditions
1684 * (they will be re-enabled afterwards).
1685 */
1686 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
1687
1688 old_mask = ah->ah_imr;
1689
1690 /*
1691 * Add additional, chipset-dependent interrupt mask flags
1692 * and write them to the IMR (interrupt mask register).
1693 */
1694 int_mask = new_mask & AR5K_INT_COMMON;
1695
1696 if (new_mask & AR5K_INT_RX)
1697 int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN |
1698 AR5K_IMR_RXDESC;
1699
1700 if (new_mask & AR5K_INT_TX)
1701 int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC |
1702 AR5K_IMR_TXURN;
1703
1704 if (ah->ah_version != AR5K_AR5210) {
1705 if (new_mask & AR5K_INT_FATAL) {
1706 int_mask |= AR5K_IMR_HIUERR;
1707 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_MCABT |
1708 AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR);
1709 }
1710 }
1711
1712 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
1713
1714 /* Store new interrupt mask */
1715 ah->ah_imr = new_mask;
1716
1717 /* ..re-enable interrupts */
1718 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
1719
1720 return old_mask;
1721 }
1722
1723
1724 /*************************\
1725 EEPROM access functions
1726 \*************************/
1727
1728 /*
1729 * Read from eeprom
1730 */
1731 static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
1732 {
1733 u32 status, timeout;
1734
1735 ATH5K_TRACE(ah->ah_sc);
1736 /*
1737 * Initialize EEPROM access
1738 */
1739 if (ah->ah_version == AR5K_AR5210) {
1740 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1741 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
1742 } else {
1743 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1744 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1745 AR5K_EEPROM_CMD_READ);
1746 }
1747
1748 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1749 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1750 if (status & AR5K_EEPROM_STAT_RDDONE) {
1751 if (status & AR5K_EEPROM_STAT_RDERR)
1752 return -EIO;
1753 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
1754 0xffff);
1755 return 0;
1756 }
1757 udelay(15);
1758 }
1759
1760 return -ETIMEDOUT;
1761 }
1762
1763 /*
1764 * Write to eeprom - currently disabled, use at your own risk
1765 */
1766 #if 0
1767 static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
1768 {
1769
1770 u32 status, timeout;
1771
1772 ATH5K_TRACE(ah->ah_sc);
1773
1774 /*
1775 * Initialize eeprom access
1776 */
1777
1778 if (ah->ah_version == AR5K_AR5210) {
1779 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1780 } else {
1781 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1782 AR5K_EEPROM_CMD_RESET);
1783 }
1784
1785 /*
1786 * Write data to data register
1787 */
1788
1789 if (ah->ah_version == AR5K_AR5210) {
1790 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_BASE + (4 * offset));
1791 } else {
1792 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1793 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_DATA);
1794 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1795 AR5K_EEPROM_CMD_WRITE);
1796 }
1797
1798 /*
1799 * Check status
1800 */
1801
1802 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1803 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1804 if (status & AR5K_EEPROM_STAT_WRDONE) {
1805 if (status & AR5K_EEPROM_STAT_WRERR)
1806 return EIO;
1807 return 0;
1808 }
1809 udelay(15);
1810 }
1811
1812 ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!");
1813 return -EIO;
1814 }
1815 #endif
1816
1817 /*
1818 * Translate binary channel representation in EEPROM to frequency
1819 */
1820 static u16 ath5k_eeprom_bin2freq(struct ath5k_hw *ah, u16 bin, unsigned int mode)
1821 {
1822 u16 val;
1823
1824 if (bin == AR5K_EEPROM_CHANNEL_DIS)
1825 return bin;
1826
1827 if (mode == AR5K_EEPROM_MODE_11A) {
1828 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1829 val = (5 * bin) + 4800;
1830 else
1831 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
1832 (bin * 10) + 5100;
1833 } else {
1834 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1835 val = bin + 2300;
1836 else
1837 val = bin + 2400;
1838 }
1839
1840 return val;
1841 }
1842
1843 /*
1844 * Read antenna infos from eeprom
1845 */
1846 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
1847 unsigned int mode)
1848 {
1849 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1850 u32 o = *offset;
1851 u16 val;
1852 int ret, i = 0;
1853
1854 AR5K_EEPROM_READ(o++, val);
1855 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1856 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f;
1857 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1858
1859 AR5K_EEPROM_READ(o++, val);
1860 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1861 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1862 ee->ee_ant_control[mode][i++] = val & 0x3f;
1863
1864 AR5K_EEPROM_READ(o++, val);
1865 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
1866 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
1867 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
1868
1869 AR5K_EEPROM_READ(o++, val);
1870 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
1871 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
1872 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
1873 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1874
1875 AR5K_EEPROM_READ(o++, val);
1876 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1877 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1878 ee->ee_ant_control[mode][i++] = val & 0x3f;
1879
1880 /* Get antenna modes */
1881 ah->ah_antenna[mode][0] =
1882 (ee->ee_ant_control[mode][0] << 4) | 0x1;
1883 ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
1884 ee->ee_ant_control[mode][1] |
1885 (ee->ee_ant_control[mode][2] << 6) |
1886 (ee->ee_ant_control[mode][3] << 12) |
1887 (ee->ee_ant_control[mode][4] << 18) |
1888 (ee->ee_ant_control[mode][5] << 24);
1889 ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
1890 ee->ee_ant_control[mode][6] |
1891 (ee->ee_ant_control[mode][7] << 6) |
1892 (ee->ee_ant_control[mode][8] << 12) |
1893 (ee->ee_ant_control[mode][9] << 18) |
1894 (ee->ee_ant_control[mode][10] << 24);
1895
1896 /* return new offset */
1897 *offset = o;
1898
1899 return 0;
1900 }
1901
1902 /*
1903 * Read supported modes from eeprom
1904 */
1905 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
1906 unsigned int mode)
1907 {
1908 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1909 u32 o = *offset;
1910 u16 val;
1911 int ret;
1912
1913 AR5K_EEPROM_READ(o++, val);
1914 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
1915 ee->ee_thr_62[mode] = val & 0xff;
1916
1917 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1918 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
1919
1920 AR5K_EEPROM_READ(o++, val);
1921 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
1922 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
1923
1924 AR5K_EEPROM_READ(o++, val);
1925 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
1926
1927 if ((val & 0xff) & 0x80)
1928 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
1929 else
1930 ee->ee_noise_floor_thr[mode] = val & 0xff;
1931
1932 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1933 ee->ee_noise_floor_thr[mode] =
1934 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
1935
1936 AR5K_EEPROM_READ(o++, val);
1937 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
1938 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
1939 ee->ee_xpd[mode] = val & 0x1;
1940
1941 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
1942 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
1943
1944 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
1945 AR5K_EEPROM_READ(o++, val);
1946 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
1947
1948 if (mode == AR5K_EEPROM_MODE_11A)
1949 ee->ee_xr_power[mode] = val & 0x3f;
1950 else {
1951 ee->ee_ob[mode][0] = val & 0x7;
1952 ee->ee_db[mode][0] = (val >> 3) & 0x7;
1953 }
1954 }
1955
1956 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
1957 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
1958 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
1959 } else {
1960 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
1961
1962 AR5K_EEPROM_READ(o++, val);
1963 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
1964
1965 if (mode == AR5K_EEPROM_MODE_11G)
1966 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
1967 }
1968
1969 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
1970 mode == AR5K_EEPROM_MODE_11A) {
1971 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1972 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1973 }
1974
1975 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
1976 mode == AR5K_EEPROM_MODE_11G)
1977 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
1978
1979 /* return new offset */
1980 *offset = o;
1981
1982 return 0;
1983 }
1984
1985 /*
1986 * Initialize eeprom & capabilities structs
1987 */
1988 static int ath5k_eeprom_init(struct ath5k_hw *ah)
1989 {
1990 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1991 unsigned int mode, i;
1992 int ret;
1993 u32 offset;
1994 u16 val;
1995
1996 /* Initial TX thermal adjustment values */
1997 ee->ee_tx_clip = 4;
1998 ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
1999 ee->ee_gain_select = 1;
2000
2001 /*
2002 * Read values from EEPROM and store them in the capability structure
2003 */
2004 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
2005 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
2006 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
2007 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
2008 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
2009
2010 /* Return if we have an old EEPROM */
2011 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
2012 return 0;
2013
2014 #ifdef notyet
2015 /*
2016 * Validate the checksum of the EEPROM date. There are some
2017 * devices with invalid EEPROMs.
2018 */
2019 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
2020 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
2021 cksum ^= val;
2022 }
2023 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
2024 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
2025 return -EIO;
2026 }
2027 #endif
2028
2029 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
2030 ee_ant_gain);
2031
2032 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2033 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
2034 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
2035 }
2036
2037 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
2038 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
2039 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
2040 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
2041
2042 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
2043 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
2044 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
2045 }
2046
2047 /*
2048 * Get conformance test limit values
2049 */
2050 offset = AR5K_EEPROM_CTL(ah->ah_ee_version);
2051 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ah->ah_ee_version);
2052
2053 for (i = 0; i < ee->ee_ctls; i++) {
2054 AR5K_EEPROM_READ(offset++, val);
2055 ee->ee_ctl[i] = (val >> 8) & 0xff;
2056 ee->ee_ctl[i + 1] = val & 0xff;
2057 }
2058
2059 /*
2060 * Get values for 802.11a (5GHz)
2061 */
2062 mode = AR5K_EEPROM_MODE_11A;
2063
2064 ee->ee_turbo_max_power[mode] =
2065 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
2066
2067 offset = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
2068
2069 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2070 if (ret)
2071 return ret;
2072
2073 AR5K_EEPROM_READ(offset++, val);
2074 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2075 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
2076 ee->ee_db[mode][3] = (val >> 2) & 0x7;
2077 ee->ee_ob[mode][2] = (val << 1) & 0x7;
2078
2079 AR5K_EEPROM_READ(offset++, val);
2080 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
2081 ee->ee_db[mode][2] = (val >> 12) & 0x7;
2082 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
2083 ee->ee_db[mode][1] = (val >> 6) & 0x7;
2084 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
2085 ee->ee_db[mode][0] = val & 0x7;
2086
2087 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2088 if (ret)
2089 return ret;
2090
2091 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
2092 AR5K_EEPROM_READ(offset++, val);
2093 ee->ee_margin_tx_rx[mode] = val & 0x3f;
2094 }
2095
2096 /*
2097 * Get values for 802.11b (2.4GHz)
2098 */
2099 mode = AR5K_EEPROM_MODE_11B;
2100 offset = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
2101
2102 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2103 if (ret)
2104 return ret;
2105
2106 AR5K_EEPROM_READ(offset++, val);
2107 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2108 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
2109 ee->ee_db[mode][1] = val & 0x7;
2110
2111 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2112 if (ret)
2113 return ret;
2114
2115 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2116 AR5K_EEPROM_READ(offset++, val);
2117 ee->ee_cal_pier[mode][0] =
2118 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2119 ee->ee_cal_pier[mode][1] =
2120 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
2121
2122 AR5K_EEPROM_READ(offset++, val);
2123 ee->ee_cal_pier[mode][2] =
2124 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2125 }
2126
2127 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
2128 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
2129
2130 /*
2131 * Get values for 802.11g (2.4GHz)
2132 */
2133 mode = AR5K_EEPROM_MODE_11G;
2134 offset = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
2135
2136 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
2137 if (ret)
2138 return ret;
2139
2140 AR5K_EEPROM_READ(offset++, val);
2141 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
2142 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
2143 ee->ee_db[mode][1] = val & 0x7;
2144
2145 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
2146 if (ret)
2147 return ret;
2148
2149 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
2150 AR5K_EEPROM_READ(offset++, val);
2151 ee->ee_cal_pier[mode][0] =
2152 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2153 ee->ee_cal_pier[mode][1] =
2154 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
2155
2156 AR5K_EEPROM_READ(offset++, val);
2157 ee->ee_turbo_max_power[mode] = val & 0x7f;
2158 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
2159
2160 AR5K_EEPROM_READ(offset++, val);
2161 ee->ee_cal_pier[mode][2] =
2162 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
2163
2164 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
2165 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
2166
2167 AR5K_EEPROM_READ(offset++, val);
2168 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
2169 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
2170
2171 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
2172 AR5K_EEPROM_READ(offset++, val);
2173 ee->ee_cck_ofdm_gain_delta = val & 0xff;
2174 }
2175 }
2176
2177 /*
2178 * Read 5GHz EEPROM channels
2179 */
2180
2181 return 0;
2182 }
2183
2184 /*
2185 * Read the MAC address from eeprom
2186 */
2187 static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
2188 {
2189 u8 mac_d[ETH_ALEN];
2190 u32 total, offset;
2191 u16 data;
2192 int octet, ret;
2193
2194 memset(mac, 0, ETH_ALEN);
2195 memset(mac_d, 0, ETH_ALEN);
2196
2197 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
2198 if (ret)
2199 return ret;
2200
2201 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
2202 ret = ath5k_hw_eeprom_read(ah, offset, &data);
2203 if (ret)
2204 return ret;
2205
2206 total += data;
2207 mac_d[octet + 1] = data & 0xff;
2208 mac_d[octet] = data >> 8;
2209 octet += 2;
2210 }
2211
2212 memcpy(mac, mac_d, ETH_ALEN);
2213
2214 if (!total || total == 3 * 0xffff)
2215 return -EINVAL;
2216
2217 return 0;
2218 }
2219
2220 /*
2221 * Fill the capabilities struct
2222 */
2223 static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2224 {
2225 u16 ee_header;
2226
2227 ATH5K_TRACE(ah->ah_sc);
2228 /* Capabilities stored in the EEPROM */
2229 ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
2230
2231 if (ah->ah_version == AR5K_AR5210) {
2232 /*
2233 * Set radio capabilities
2234 * (The AR5110 only supports the middle 5GHz band)
2235 */
2236 ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
2237 ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
2238 ah->ah_capabilities.cap_range.range_2ghz_min = 0;
2239 ah->ah_capabilities.cap_range.range_2ghz_max = 0;
2240
2241 /* Set supported modes */
2242 __set_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode);
2243 __set_bit(AR5K_MODE_11A_TURBO, ah->ah_capabilities.cap_mode);
2244 } else {
2245 /*
2246 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
2247 * XXX and from 2312 to 2732GHz. There are problems with the
2248 * XXX current ieee80211 implementation because the IEEE
2249 * XXX channel mapping does not support negative channel
2250 * XXX numbers (2312MHz is channel -19). Of course, this
2251 * XXX doesn't matter because these channels are out of range
2252 * XXX but some regulation domains like MKK (Japan) will
2253 * XXX support frequencies somewhere around 4.8GHz.
2254 */
2255
2256 /*
2257 * Set radio capabilities
2258 */
2259
2260 if (AR5K_EEPROM_HDR_11A(ee_header)) {
2261 ah->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
2262 ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
2263
2264 /* Set supported modes */
2265 __set_bit(AR5K_MODE_11A,
2266 ah->ah_capabilities.cap_mode);
2267 __set_bit(AR5K_MODE_11A_TURBO,
2268 ah->ah_capabilities.cap_mode);
2269 if (ah->ah_version == AR5K_AR5212)
2270 __set_bit(AR5K_MODE_11G_TURBO,
2271 ah->ah_capabilities.cap_mode);
2272 }
2273
2274 /* Enable 802.11b if a 2GHz capable radio (2111/5112) is
2275 * connected */
2276 if (AR5K_EEPROM_HDR_11B(ee_header) ||
2277 AR5K_EEPROM_HDR_11G(ee_header)) {
2278 ah->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
2279 ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
2280
2281 if (AR5K_EEPROM_HDR_11B(ee_header))
2282 __set_bit(AR5K_MODE_11B,
2283 ah->ah_capabilities.cap_mode);
2284
2285 if (AR5K_EEPROM_HDR_11G(ee_header))
2286 __set_bit(AR5K_MODE_11G,
2287 ah->ah_capabilities.cap_mode);
2288 }
2289 }
2290
2291 /* GPIO */
2292 ah->ah_gpio_npins = AR5K_NUM_GPIO;
2293
2294 /* Set number of supported TX queues */
2295 if (ah->ah_version == AR5K_AR5210)
2296 ah->ah_capabilities.cap_queues.q_tx_num =
2297 AR5K_NUM_TX_QUEUES_NOQCU;
2298 else
2299 ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
2300
2301 return 0;
2302 }
2303
2304 /*********************************\
2305 Protocol Control Unit Functions
2306 \*********************************/
2307
2308 /*
2309 * Set Operation mode
2310 */
2311 int ath5k_hw_set_opmode(struct ath5k_hw *ah)
2312 {
2313 u32 pcu_reg, beacon_reg, low_id, high_id;
2314
2315 pcu_reg = 0;
2316 beacon_reg = 0;
2317
2318 ATH5K_TRACE(ah->ah_sc);
2319
2320 switch (ah->ah_op_mode) {
2321 case IEEE80211_IF_TYPE_IBSS:
2322 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA |
2323 (ah->ah_version == AR5K_AR5210 ?
2324 AR5K_STA_ID1_NO_PSPOLL : 0);
2325 beacon_reg |= AR5K_BCR_ADHOC;
2326 break;
2327
2328 case IEEE80211_IF_TYPE_AP:
2329 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA |
2330 (ah->ah_version == AR5K_AR5210 ?
2331 AR5K_STA_ID1_NO_PSPOLL : 0);
2332 beacon_reg |= AR5K_BCR_AP;
2333 break;
2334
2335 case IEEE80211_IF_TYPE_STA:
2336 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2337 (ah->ah_version == AR5K_AR5210 ?
2338 AR5K_STA_ID1_PWR_SV : 0);
2339 case IEEE80211_IF_TYPE_MNTR:
2340 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2341 (ah->ah_version == AR5K_AR5210 ?
2342 AR5K_STA_ID1_NO_PSPOLL : 0);
2343 break;
2344
2345 default:
2346 return -EINVAL;
2347 }
2348
2349 /*
2350 * Set PCU registers
2351 */
2352 low_id = AR5K_LOW_ID(ah->ah_sta_id);
2353 high_id = AR5K_HIGH_ID(ah->ah_sta_id);
2354 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2355 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
2356
2357 /*
2358 * Set Beacon Control Register on 5210
2359 */
2360 if (ah->ah_version == AR5K_AR5210)
2361 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
2362
2363 return 0;
2364 }
2365
2366 /*
2367 * BSSID Functions
2368 */
2369
2370 /*
2371 * Get station id
2372 */
2373 void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
2374 {
2375 ATH5K_TRACE(ah->ah_sc);
2376 memcpy(mac, ah->ah_sta_id, ETH_ALEN);
2377 }
2378
2379 /*
2380 * Set station id
2381 */
2382 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
2383 {
2384 u32 low_id, high_id;
2385
2386 ATH5K_TRACE(ah->ah_sc);
2387 /* Set new station ID */
2388 memcpy(ah->ah_sta_id, mac, ETH_ALEN);
2389
2390 low_id = AR5K_LOW_ID(mac);
2391 high_id = AR5K_HIGH_ID(mac);
2392
2393 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2394 ath5k_hw_reg_write(ah, high_id, AR5K_STA_ID1);
2395
2396 return 0;
2397 }
2398
2399 /*
2400 * Set BSSID
2401 */
2402 void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
2403 {
2404 u32 low_id, high_id;
2405 u16 tim_offset = 0;
2406
2407 /*
2408 * Set simple BSSID mask on 5212
2409 */
2410 if (ah->ah_version == AR5K_AR5212) {
2411 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM0);
2412 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_BSS_IDM1);
2413 }
2414
2415 /*
2416 * Set BSSID which triggers the "SME Join" operation
2417 */
2418 low_id = AR5K_LOW_ID(bssid);
2419 high_id = AR5K_HIGH_ID(bssid);
2420 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0);
2421 ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
2422 AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
2423
2424 if (assoc_id == 0) {
2425 ath5k_hw_disable_pspoll(ah);
2426 return;
2427 }
2428
2429 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
2430 tim_offset ? tim_offset + 4 : 0);
2431
2432 ath5k_hw_enable_pspoll(ah, NULL, 0);
2433 }
2434 /**
2435 * ath5k_hw_set_bssid_mask - set common bits we should listen to
2436 *
2437 * The bssid_mask is a utility used by AR5212 hardware to inform the hardware
2438 * which bits of the interface's MAC address should be looked at when trying
2439 * to decide which packets to ACK. In station mode every bit matters. In AP
2440 * mode with a single BSS every bit matters as well. In AP mode with
2441 * multiple BSSes not every bit matters.
2442 *
2443 * @ah: the &struct ath5k_hw
2444 * @mask: the bssid_mask, a u8 array of size ETH_ALEN
2445 *
2446 * Note that this is a simple filter and *does* not filter out all
2447 * relevant frames. Some non-relevant frames will get through, probability
2448 * jocks are welcomed to compute.
2449 *
2450 * When handling multiple BSSes (or VAPs) you can get the BSSID mask by
2451 * computing the set of:
2452 *
2453 * ~ ( MAC XOR BSSID )
2454 *
2455 * When you do this you are essentially computing the common bits. Later it
2456 * is assumed the harware will "and" (&) the BSSID mask with the MAC address
2457 * to obtain the relevant bits which should match on the destination frame.
2458 *
2459 * Simple example: on your card you have have two BSSes you have created with
2460 * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
2461 * There is another BSSID-03 but you are not part of it. For simplicity's sake,
2462 * assuming only 4 bits for a mac address and for BSSIDs you can then have:
2463 *
2464 * \
2465 * MAC: 0001 |
2466 * BSSID-01: 0100 | --> Belongs to us
2467 * BSSID-02: 1001 |
2468 * /
2469 * -------------------
2470 * BSSID-03: 0110 | --> External
2471 * -------------------
2472 *
2473 * Our bssid_mask would then be:
2474 *
2475 * On loop iteration for BSSID-01:
2476 * ~(0001 ^ 0100) -> ~(0101)
2477 * -> 1010
2478 * bssid_mask = 1010
2479 *
2480 * On loop iteration for BSSID-02:
2481 * bssid_mask &= ~(0001 ^ 1001)
2482 * bssid_mask = (1010) & ~(0001 ^ 1001)
2483 * bssid_mask = (1010) & ~(1001)
2484 * bssid_mask = (1010) & (0110)
2485 * bssid_mask = 0010
2486 *
2487 * A bssid_mask of 0010 means "only pay attention to the second least
2488 * significant bit". This is because its the only bit common
2489 * amongst the MAC and all BSSIDs we support. To findout what the real
2490 * common bit is we can simply "&" the bssid_mask now with any BSSID we have
2491 * or our MAC address (we assume the hardware uses the MAC address).
2492 *
2493 * Now, suppose there's an incoming frame for BSSID-03:
2494 *
2495 * IFRAME-01: 0110
2496 *
2497 * An easy eye-inspeciton of this already should tell you that this frame
2498 * will not pass our check. This is beacuse the bssid_mask tells the
2499 * hardware to only look at the second least significant bit and the
2500 * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
2501 * as 1, which does not match 0.
2502 *
2503 * So with IFRAME-01 we *assume* the hardware will do:
2504 *
2505 * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2506 * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
2507 * --> allow = (0010) == 0000 ? 1 : 0;
2508 * --> allow = 0
2509 *
2510 * Lets now test a frame that should work:
2511 *
2512 * IFRAME-02: 0001 (we should allow)
2513 *
2514 * allow = (0001 & 1010) == 1010
2515 *
2516 * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2517 * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
2518 * --> allow = (0010) == (0010)
2519 * --> allow = 1
2520 *
2521 * Other examples:
2522 *
2523 * IFRAME-03: 0100 --> allowed
2524 * IFRAME-04: 1001 --> allowed
2525 * IFRAME-05: 1101 --> allowed but its not for us!!!
2526 *
2527 */
2528 int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
2529 {
2530 u32 low_id, high_id;
2531 ATH5K_TRACE(ah->ah_sc);
2532
2533 if (ah->ah_version == AR5K_AR5212) {
2534 low_id = AR5K_LOW_ID(mask);
2535 high_id = AR5K_HIGH_ID(mask);
2536
2537 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0);
2538 ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1);
2539
2540 return 0;
2541 }
2542
2543 return -EIO;
2544 }
2545
2546 /*
2547 * Receive start/stop functions
2548 */
2549
2550 /*
2551 * Start receive on PCU
2552 */
2553 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
2554 {
2555 ATH5K_TRACE(ah->ah_sc);
2556 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2557
2558 /* TODO: ANI Support */
2559 }
2560
2561 /*
2562 * Stop receive on PCU
2563 */
2564 void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah)
2565 {
2566 ATH5K_TRACE(ah->ah_sc);
2567 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2568
2569 /* TODO: ANI Support */
2570 }
2571
2572 /*
2573 * RX Filter functions
2574 */
2575
2576 /*
2577 * Set multicast filter
2578 */
2579 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
2580 {
2581 ATH5K_TRACE(ah->ah_sc);
2582 /* Set the multicat filter */
2583 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
2584 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
2585 }
2586
2587 /*
2588 * Set multicast filter by index
2589 */
2590 int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index)
2591 {
2592
2593 ATH5K_TRACE(ah->ah_sc);
2594 if (index >= 64)
2595 return -EINVAL;
2596 else if (index >= 32)
2597 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1,
2598 (1 << (index - 32)));
2599 else
2600 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2601
2602 return 0;
2603 }
2604
2605 /*
2606 * Clear Multicast filter by index
2607 */
2608 int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
2609 {
2610
2611 ATH5K_TRACE(ah->ah_sc);
2612 if (index >= 64)
2613 return -EINVAL;
2614 else if (index >= 32)
2615 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1,
2616 (1 << (index - 32)));
2617 else
2618 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2619
2620 return 0;
2621 }
2622
2623 /*
2624 * Get current rx filter
2625 */
2626 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
2627 {
2628 u32 data, filter = 0;
2629
2630 ATH5K_TRACE(ah->ah_sc);
2631 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
2632
2633 /*Radar detection for 5212*/
2634 if (ah->ah_version == AR5K_AR5212) {
2635 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
2636
2637 if (data & AR5K_PHY_ERR_FIL_RADAR)
2638 filter |= AR5K_RX_FILTER_RADARERR;
2639 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
2640 filter |= AR5K_RX_FILTER_PHYERR;
2641 }
2642
2643 return filter;
2644 }
2645
2646 /*
2647 * Set rx filter
2648 */
2649 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
2650 {
2651 u32 data = 0;
2652
2653 ATH5K_TRACE(ah->ah_sc);
2654
2655 /* Set PHY error filter register on 5212*/
2656 if (ah->ah_version == AR5K_AR5212) {
2657 if (filter & AR5K_RX_FILTER_RADARERR)
2658 data |= AR5K_PHY_ERR_FIL_RADAR;
2659 if (filter & AR5K_RX_FILTER_PHYERR)
2660 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
2661 }
2662
2663 /*
2664 * The AR5210 uses promiscous mode to detect radar activity
2665 */
2666 if (ah->ah_version == AR5K_AR5210 &&
2667 (filter & AR5K_RX_FILTER_RADARERR)) {
2668 filter &= ~AR5K_RX_FILTER_RADARERR;
2669 filter |= AR5K_RX_FILTER_PROM;
2670 }
2671
2672 /*Zero length DMA*/
2673 if (data)
2674 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2675 else
2676 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2677
2678 /*Write RX Filter register*/
2679 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
2680
2681 /*Write PHY error filter register on 5212*/
2682 if (ah->ah_version == AR5K_AR5212)
2683 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
2684
2685 }
2686
2687 /*
2688 * Beacon related functions
2689 */
2690
2691 /*
2692 * Get a 32bit TSF
2693 */
2694 u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah)
2695 {
2696 ATH5K_TRACE(ah->ah_sc);
2697 return ath5k_hw_reg_read(ah, AR5K_TSF_L32);
2698 }
2699
2700 /*
2701 * Get the full 64bit TSF
2702 */
2703 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
2704 {
2705 u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
2706 ATH5K_TRACE(ah->ah_sc);
2707
2708 return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32);
2709 }
2710
2711 /*
2712 * Force a TSF reset
2713 */
2714 void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
2715 {
2716 ATH5K_TRACE(ah->ah_sc);
2717 AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
2718 }
2719
2720 /*
2721 * Initialize beacon timers
2722 */
2723 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
2724 {
2725 u32 timer1, timer2, timer3;
2726
2727 ATH5K_TRACE(ah->ah_sc);
2728 /*
2729 * Set the additional timers by mode
2730 */
2731 switch (ah->ah_op_mode) {
2732 case IEEE80211_IF_TYPE_STA:
2733 if (ah->ah_version == AR5K_AR5210) {
2734 timer1 = 0xffffffff;
2735 timer2 = 0xffffffff;
2736 } else {
2737 timer1 = 0x0000ffff;
2738 timer2 = 0x0007ffff;
2739 }
2740 break;
2741
2742 default:
2743 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
2744 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
2745 }
2746
2747 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
2748
2749 /*
2750 * Set the beacon register and enable all timers.
2751 * (next beacon, DMA beacon, software beacon, ATIM window time)
2752 */
2753 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
2754 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
2755 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
2756 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
2757
2758 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
2759 AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE),
2760 AR5K_BEACON);
2761 }
2762
2763 #if 0
2764 /*
2765 * Set beacon timers
2766 */
2767 int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
2768 const struct ath5k_beacon_state *state)
2769 {
2770 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
2771
2772 /*
2773 * TODO: should be changed through *state
2774 * review struct ath5k_beacon_state struct
2775 *
2776 * XXX: These are used for cfp period bellow, are they
2777 * ok ? Is it O.K. for tsf here to be 0 or should we use
2778 * get_tsf ?
2779 */
2780 u32 dtim_count = 0; /* XXX */
2781 u32 cfp_count = 0; /* XXX */
2782 u32 tsf = 0; /* XXX */
2783
2784 ATH5K_TRACE(ah->ah_sc);
2785 /* Return on an invalid beacon state */
2786 if (state->bs_interval < 1)
2787 return -EINVAL;
2788
2789 interval = state->bs_interval;
2790 dtim = state->bs_dtim_period;
2791
2792 /*
2793 * PCF support?
2794 */
2795 if (state->bs_cfp_period > 0) {
2796 /*
2797 * Enable PCF mode and set the CFP
2798 * (Contention Free Period) and timer registers
2799 */
2800 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
2801 state->bs_interval;
2802 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
2803 state->bs_interval;
2804
2805 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
2806 AR5K_STA_ID1_DEFAULT_ANTENNA |
2807 AR5K_STA_ID1_PCF);
2808 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
2809 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
2810 AR5K_CFP_DUR);
2811 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
2812 next_cfp)) << 3, AR5K_TIMER2);
2813 } else {
2814 /* Disable PCF mode */
2815 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2816 AR5K_STA_ID1_DEFAULT_ANTENNA |
2817 AR5K_STA_ID1_PCF);
2818 }
2819
2820 /*
2821 * Enable the beacon timer register
2822 */
2823 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
2824
2825 /*
2826 * Start the beacon timers
2827 */
2828 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &~
2829 (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
2830 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
2831 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
2832 AR5K_BEACON_PERIOD), AR5K_BEACON);
2833
2834 /*
2835 * Write new beacon miss threshold, if it appears to be valid
2836 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
2837 * and return if its not in range. We can test this by reading value and
2838 * setting value to a largest value and seeing which values register.
2839 */
2840
2841 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
2842 state->bs_bmiss_threshold);
2843
2844 /*
2845 * Set sleep control register
2846 * XXX: Didn't find this in 5210 code but since this register
2847 * exists also in ar5k's 5210 headers i leave it as common code.
2848 */
2849 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
2850 (state->bs_sleep_duration - 3) << 3);
2851
2852 /*
2853 * Set enhanced sleep registers on 5212
2854 */
2855 if (ah->ah_version == AR5K_AR5212) {
2856 if (state->bs_sleep_duration > state->bs_interval &&
2857 roundup(state->bs_sleep_duration, interval) ==
2858 state->bs_sleep_duration)
2859 interval = state->bs_sleep_duration;
2860
2861 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
2862 roundup(state->bs_sleep_duration, dtim) ==
2863 state->bs_sleep_duration))
2864 dtim = state->bs_sleep_duration;
2865
2866 if (interval > dtim)
2867 return -EINVAL;
2868
2869 next_beacon = interval == dtim ? state->bs_next_dtim :
2870 state->bs_next_beacon;
2871
2872 ath5k_hw_reg_write(ah,
2873 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
2874 AR5K_SLEEP0_NEXT_DTIM) |
2875 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
2876 AR5K_SLEEP0_ENH_SLEEP_EN |
2877 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
2878
2879 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
2880 AR5K_SLEEP1_NEXT_TIM) |
2881 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
2882
2883 ath5k_hw_reg_write(ah,
2884 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
2885 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
2886 }
2887
2888 return 0;
2889 }
2890
2891 /*
2892 * Reset beacon timers
2893 */
2894 void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
2895 {
2896 ATH5K_TRACE(ah->ah_sc);
2897 /*
2898 * Disable beacon timer
2899 */
2900 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
2901
2902 /*
2903 * Disable some beacon register values
2904 */
2905 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2906 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
2907 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
2908 }
2909
2910 /*
2911 * Wait for beacon queue to finish
2912 */
2913 int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
2914 {
2915 unsigned int i;
2916 int ret;
2917
2918 ATH5K_TRACE(ah->ah_sc);
2919
2920 /* 5210 doesn't have QCU*/
2921 if (ah->ah_version == AR5K_AR5210) {
2922 /*
2923 * Wait for beaconn queue to finish by checking
2924 * Control Register and Beacon Status Register.
2925 */
2926 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
2927 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
2928 ||
2929 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
2930 break;
2931 udelay(10);
2932 }
2933
2934 /* Timeout... */
2935 if (i <= 0) {
2936 /*
2937 * Re-schedule the beacon queue
2938 */
2939 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
2940 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
2941 AR5K_BCR);
2942
2943 return -EIO;
2944 }
2945 ret = 0;
2946 } else {
2947 /*5211/5212*/
2948 ret = ath5k_hw_register_timeout(ah,
2949 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
2950 AR5K_QCU_STS_FRMPENDCNT, 0, false);
2951
2952 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
2953 return -EIO;
2954 }
2955
2956 return ret;
2957 }
2958 #endif
2959
2960 /*
2961 * Update mib counters (statistics)
2962 */
2963 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
2964 struct ieee80211_low_level_stats *stats)
2965 {
2966 ATH5K_TRACE(ah->ah_sc);
2967
2968 /* Read-And-Clear */
2969 stats->dot11ACKFailureCount += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
2970 stats->dot11RTSFailureCount += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
2971 stats->dot11RTSSuccessCount += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
2972 stats->dot11FCSErrorCount += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
2973
2974 /* XXX: Should we use this to track beacon count ?
2975 * -we read it anyway to clear the register */
2976 ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
2977
2978 /* Reset profile count registers on 5212*/
2979 if (ah->ah_version == AR5K_AR5212) {
2980 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
2981 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
2982 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
2983 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
2984 }
2985 }
2986
2987 /** ath5k_hw_set_ack_bitrate - set bitrate for ACKs
2988 *
2989 * @ah: the &struct ath5k_hw
2990 * @high: determines if to use low bit rate or now
2991 */
2992 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
2993 {
2994 if (ah->ah_version != AR5K_AR5212)
2995 return;
2996 else {
2997 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
2998 if (high)
2999 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
3000 else
3001 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
3002 }
3003 }
3004
3005
3006 /*
3007 * ACK/CTS Timeouts
3008 */
3009
3010 /*
3011 * Set ACK timeout on PCU
3012 */
3013 int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
3014 {
3015 ATH5K_TRACE(ah->ah_sc);
3016 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
3017 ah->ah_turbo) <= timeout)
3018 return -EINVAL;
3019
3020 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
3021 ath5k_hw_htoclock(timeout, ah->ah_turbo));
3022
3023 return 0;
3024 }
3025
3026 /*
3027 * Read the ACK timeout from PCU
3028 */
3029 unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
3030 {
3031 ATH5K_TRACE(ah->ah_sc);
3032
3033 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
3034 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo);
3035 }
3036
3037 /*
3038 * Set CTS timeout on PCU
3039 */
3040 int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
3041 {
3042 ATH5K_TRACE(ah->ah_sc);
3043 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
3044 ah->ah_turbo) <= timeout)
3045 return -EINVAL;
3046
3047 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
3048 ath5k_hw_htoclock(timeout, ah->ah_turbo));
3049
3050 return 0;
3051 }
3052
3053 /*
3054 * Read CTS timeout from PCU
3055 */
3056 unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
3057 {
3058 ATH5K_TRACE(ah->ah_sc);
3059 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
3060 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo);
3061 }
3062
3063 /*
3064 * Key table (WEP) functions
3065 */
3066
3067 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
3068 {
3069 unsigned int i;
3070
3071 ATH5K_TRACE(ah->ah_sc);
3072 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3073
3074 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
3075 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
3076
3077 /*
3078 * Set NULL encryption on AR5212+
3079 *
3080 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
3081 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
3082 *
3083 * Note2: Windows driver (ndiswrapper) sets this to
3084 * 0x00000714 instead of 0x00000007
3085 */
3086 if (ah->ah_version > AR5K_AR5211)
3087 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
3088 AR5K_KEYTABLE_TYPE(entry));
3089
3090 return 0;
3091 }
3092
3093 int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry)
3094 {
3095 ATH5K_TRACE(ah->ah_sc);
3096 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3097
3098 /* Check the validation flag at the end of the entry */
3099 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) &
3100 AR5K_KEYTABLE_VALID;
3101 }
3102
3103 int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
3104 const struct ieee80211_key_conf *key, const u8 *mac)
3105 {
3106 unsigned int i;
3107 __le32 key_v[5] = {};
3108 u32 keytype;
3109
3110 ATH5K_TRACE(ah->ah_sc);
3111
3112 /* key->keylen comes in from mac80211 in bytes */
3113
3114 if (key->keylen > AR5K_KEYTABLE_SIZE / 8)
3115 return -EOPNOTSUPP;
3116
3117 switch (key->keylen) {
3118 /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit */
3119 case 40 / 8:
3120 memcpy(&key_v[0], key->key, 5);
3121 keytype = AR5K_KEYTABLE_TYPE_40;
3122 break;
3123
3124 /* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit */
3125 case 104 / 8:
3126 memcpy(&key_v[0], &key->key[0], 6);
3127 memcpy(&key_v[2], &key->key[6], 6);
3128 memcpy(&key_v[4], &key->key[12], 1);
3129 keytype = AR5K_KEYTABLE_TYPE_104;
3130 break;
3131 /* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit */
3132 case 128 / 8:
3133 memcpy(&key_v[0], &key->key[0], 6);
3134 memcpy(&key_v[2], &key->key[6], 6);
3135 memcpy(&key_v[4], &key->key[12], 4);
3136 keytype = AR5K_KEYTABLE_TYPE_128;
3137 break;
3138
3139 default:
3140 return -EINVAL; /* shouldn't happen */
3141 }
3142
3143 for (i = 0; i < ARRAY_SIZE(key_v); i++)
3144 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
3145 AR5K_KEYTABLE_OFF(entry, i));
3146
3147 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
3148
3149 return ath5k_hw_set_key_lladdr(ah, entry, mac);
3150 }
3151
3152 int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
3153 {
3154 u32 low_id, high_id;
3155
3156 ATH5K_TRACE(ah->ah_sc);
3157 /* Invalid entry (key table overflow) */
3158 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3159
3160 /* MAC may be NULL if it's a broadcast key. In this case no need to
3161 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
3162 if (unlikely(mac == NULL)) {
3163 low_id = 0xffffffff;
3164 high_id = 0xffff | AR5K_KEYTABLE_VALID;
3165 } else {
3166 low_id = AR5K_LOW_ID(mac);
3167 high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID;
3168 }
3169
3170 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
3171 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
3172
3173 return 0;
3174 }
3175
3176
3177 /********************************************\
3178 Queue Control Unit, DFS Control Unit Functions
3179 \********************************************/
3180
3181 /*
3182 * Initialize a transmit queue
3183 */
3184 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
3185 struct ath5k_txq_info *queue_info)
3186 {
3187 unsigned int queue;
3188 int ret;
3189
3190 ATH5K_TRACE(ah->ah_sc);
3191
3192 /*
3193 * Get queue by type
3194 */
3195 /*5210 only has 2 queues*/
3196 if (ah->ah_version == AR5K_AR5210) {
3197 switch (queue_type) {
3198 case AR5K_TX_QUEUE_DATA:
3199 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
3200 break;
3201 case AR5K_TX_QUEUE_BEACON:
3202 case AR5K_TX_QUEUE_CAB:
3203 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
3204 break;
3205 default:
3206 return -EINVAL;
3207 }
3208 } else {
3209 switch (queue_type) {
3210 case AR5K_TX_QUEUE_DATA:
3211 for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
3212 ah->ah_txq[queue].tqi_type !=
3213 AR5K_TX_QUEUE_INACTIVE; queue++) {
3214
3215 if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
3216 return -EINVAL;
3217 }
3218 break;
3219 case AR5K_TX_QUEUE_UAPSD:
3220 queue = AR5K_TX_QUEUE_ID_UAPSD;
3221 break;
3222 case AR5K_TX_QUEUE_BEACON:
3223 queue = AR5K_TX_QUEUE_ID_BEACON;
3224 break;
3225 case AR5K_TX_QUEUE_CAB:
3226 queue = AR5K_TX_QUEUE_ID_CAB;
3227 break;
3228 case AR5K_TX_QUEUE_XR_DATA:
3229 if (ah->ah_version != AR5K_AR5212)
3230 ATH5K_ERR(ah->ah_sc,
3231 "XR data queues only supported in"
3232 " 5212!\n");
3233 queue = AR5K_TX_QUEUE_ID_XR_DATA;
3234 break;
3235 default:
3236 return -EINVAL;
3237 }
3238 }
3239
3240 /*
3241 * Setup internal queue structure
3242 */
3243 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
3244 ah->ah_txq[queue].tqi_type = queue_type;
3245
3246 if (queue_info != NULL) {
3247 queue_info->tqi_type = queue_type;
3248 ret = ath5k_hw_setup_tx_queueprops(ah, queue, queue_info);
3249 if (ret)
3250 return ret;
3251 }
3252 /*
3253 * We use ah_txq_status to hold a temp value for
3254 * the Secondary interrupt mask registers on 5211+
3255 * check out ath5k_hw_reset_tx_queue
3256 */
3257 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
3258
3259 return queue;
3260 }
3261
3262 /*
3263 * Setup a transmit queue
3264 */
3265 int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue,
3266 const struct ath5k_txq_info *queue_info)
3267 {
3268 ATH5K_TRACE(ah->ah_sc);
3269 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3270
3271 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3272 return -EIO;
3273
3274 memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
3275
3276 /*XXX: Is this supported on 5210 ?*/
3277 if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
3278 ((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
3279 (queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
3280 queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
3281 ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
3282
3283 return 0;
3284 }
3285
3286 /*
3287 * Get properties for a specific transmit queue
3288 */
3289 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
3290 struct ath5k_txq_info *queue_info)
3291 {
3292 ATH5K_TRACE(ah->ah_sc);
3293 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
3294 return 0;
3295 }
3296
3297 /*
3298 * Set a transmit queue inactive
3299 */
3300 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3301 {
3302 ATH5K_TRACE(ah->ah_sc);
3303 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
3304 return;
3305
3306 /* This queue will be skipped in further operations */
3307 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
3308 /*For SIMR setup*/
3309 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
3310 }
3311
3312 /*
3313 * Set DFS params for a transmit queue
3314 */
3315 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3316 {
3317 u32 cw_min, cw_max, retry_lg, retry_sh;
3318 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
3319
3320 ATH5K_TRACE(ah->ah_sc);
3321 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3322
3323 tq = &ah->ah_txq[queue];
3324
3325 if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
3326 return 0;
3327
3328 if (ah->ah_version == AR5K_AR5210) {
3329 /* Only handle data queues, others will be ignored */
3330 if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
3331 return 0;
3332
3333 /* Set Slot time */
3334 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3335 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
3336 AR5K_SLOT_TIME);
3337 /* Set ACK_CTS timeout */
3338 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3339 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
3340 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
3341 /* Set Transmit Latency */
3342 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3343 AR5K_INIT_TRANSMIT_LATENCY_TURBO :
3344 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
3345 /* Set IFS0 */
3346 if (ah->ah_turbo)
3347 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
3348 (ah->ah_aifs + tq->tqi_aifs) *
3349 AR5K_INIT_SLOT_TIME_TURBO) <<
3350 AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
3351 AR5K_IFS0);
3352 else
3353 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
3354 (ah->ah_aifs + tq->tqi_aifs) *
3355 AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
3356 AR5K_INIT_SIFS, AR5K_IFS0);
3357
3358 /* Set IFS1 */
3359 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3360 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3361 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
3362 /* Set PHY register 0x9844 (??) */
3363 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3364 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 :
3365 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C,
3366 AR5K_PHY(17));
3367 /* Set Frame Control Register */
3368 ath5k_hw_reg_write(ah, ah->ah_turbo ?
3369 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
3370 AR5K_PHY_TURBO_SHORT | 0x2020) :
3371 (AR5K_PHY_FRAME_CTL_INI | 0x1020),
3372 AR5K_PHY_FRAME_CTL_5210);
3373 }
3374
3375 /*
3376 * Calculate cwmin/max by channel mode
3377 */
3378 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
3379 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
3380 ah->ah_aifs = AR5K_TUNE_AIFS;
3381 /*XR is only supported on 5212*/
3382 if (IS_CHAN_XR(ah->ah_current_channel) &&
3383 ah->ah_version == AR5K_AR5212) {
3384 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
3385 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
3386 ah->ah_aifs = AR5K_TUNE_AIFS_XR;
3387 /*B mode is not supported on 5210*/
3388 } else if (IS_CHAN_B(ah->ah_current_channel) &&
3389 ah->ah_version != AR5K_AR5210) {
3390 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
3391 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
3392 ah->ah_aifs = AR5K_TUNE_AIFS_11B;
3393 }
3394
3395 cw_min = 1;
3396 while (cw_min < ah->ah_cw_min)
3397 cw_min = (cw_min << 1) | 1;
3398
3399 cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
3400 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
3401 cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
3402 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
3403
3404 /*
3405 * Calculate and set retry limits
3406 */
3407 if (ah->ah_software_retry) {
3408 /* XXX Need to test this */
3409 retry_lg = ah->ah_limit_tx_retries;
3410 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
3411 AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
3412 } else {
3413 retry_lg = AR5K_INIT_LG_RETRY;
3414 retry_sh = AR5K_INIT_SH_RETRY;
3415 }
3416
3417 /*No QCU/DCU [5210]*/
3418 if (ah->ah_version == AR5K_AR5210) {
3419 ath5k_hw_reg_write(ah,
3420 (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
3421 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3422 AR5K_NODCU_RETRY_LMT_SLG_RETRY)
3423 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3424 AR5K_NODCU_RETRY_LMT_SSH_RETRY)
3425 | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
3426 | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
3427 AR5K_NODCU_RETRY_LMT);
3428 } else {
3429 /*QCU/DCU [5211+]*/
3430 ath5k_hw_reg_write(ah,
3431 AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3432 AR5K_DCU_RETRY_LMT_SLG_RETRY) |
3433 AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3434 AR5K_DCU_RETRY_LMT_SSH_RETRY) |
3435 AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
3436 AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
3437 AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
3438
3439 /*===Rest is also for QCU/DCU only [5211+]===*/
3440
3441 /*
3442 * Set initial content window (cw_min/cw_max)
3443 * and arbitrated interframe space (aifs)...
3444 */
3445 ath5k_hw_reg_write(ah,
3446 AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
3447 AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
3448 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
3449 AR5K_DCU_LCL_IFS_AIFS),
3450 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
3451
3452 /*
3453 * Set misc registers
3454 */
3455 ath5k_hw_reg_write(ah, AR5K_QCU_MISC_DCU_EARLY,
3456 AR5K_QUEUE_MISC(queue));
3457
3458 if (tq->tqi_cbr_period) {
3459 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
3460 AR5K_QCU_CBRCFG_INTVAL) |
3461 AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
3462 AR5K_QCU_CBRCFG_ORN_THRES),
3463 AR5K_QUEUE_CBRCFG(queue));
3464 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3465 AR5K_QCU_MISC_FRSHED_CBR);
3466 if (tq->tqi_cbr_overflow_limit)
3467 AR5K_REG_ENABLE_BITS(ah,
3468 AR5K_QUEUE_MISC(queue),
3469 AR5K_QCU_MISC_CBR_THRES_ENABLE);
3470 }
3471
3472 if (tq->tqi_ready_time)
3473 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
3474 AR5K_QCU_RDYTIMECFG_INTVAL) |
3475 AR5K_QCU_RDYTIMECFG_ENABLE,
3476 AR5K_QUEUE_RDYTIMECFG(queue));
3477
3478 if (tq->tqi_burst_time) {
3479 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
3480 AR5K_DCU_CHAN_TIME_DUR) |
3481 AR5K_DCU_CHAN_TIME_ENABLE,
3482 AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
3483
3484 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
3485 AR5K_REG_ENABLE_BITS(ah,
3486 AR5K_QUEUE_MISC(queue),
3487 AR5K_QCU_MISC_TXE);
3488 }
3489
3490 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
3491 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
3492 AR5K_QUEUE_DFS_MISC(queue));
3493
3494 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
3495 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
3496 AR5K_QUEUE_DFS_MISC(queue));
3497
3498 /*
3499 * Set registers by queue type
3500 */
3501 switch (tq->tqi_type) {
3502 case AR5K_TX_QUEUE_BEACON:
3503 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3504 AR5K_QCU_MISC_FRSHED_DBA_GT |
3505 AR5K_QCU_MISC_CBREXP_BCN |
3506 AR5K_QCU_MISC_BCN_ENABLE);
3507
3508 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3509 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3510 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
3511 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
3512 AR5K_DCU_MISC_BCN_ENABLE);
3513
3514 ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -
3515 (AR5K_TUNE_SW_BEACON_RESP -
3516 AR5K_TUNE_DMA_BEACON_RESP) -
3517 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
3518 AR5K_QCU_RDYTIMECFG_ENABLE,
3519 AR5K_QUEUE_RDYTIMECFG(queue));
3520 break;
3521
3522 case AR5K_TX_QUEUE_CAB:
3523 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3524 AR5K_QCU_MISC_FRSHED_DBA_GT |
3525 AR5K_QCU_MISC_CBREXP |
3526 AR5K_QCU_MISC_CBREXP_BCN);
3527
3528 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3529 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3530 AR5K_DCU_MISC_ARBLOCK_CTL_S));
3531 break;
3532
3533 case AR5K_TX_QUEUE_UAPSD:
3534 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3535 AR5K_QCU_MISC_CBREXP);
3536 break;
3537
3538 case AR5K_TX_QUEUE_DATA:
3539 default:
3540 break;
3541 }
3542
3543 /*
3544 * Enable interrupts for this tx queue
3545 * in the secondary interrupt mask registers
3546 */
3547 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
3548 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
3549
3550 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
3551 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
3552
3553 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
3554 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
3555
3556 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
3557 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
3558
3559 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
3560 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
3561
3562
3563 /* Update secondary interrupt mask registers */
3564 ah->ah_txq_imr_txok &= ah->ah_txq_status;
3565 ah->ah_txq_imr_txerr &= ah->ah_txq_status;
3566 ah->ah_txq_imr_txurn &= ah->ah_txq_status;
3567 ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
3568 ah->ah_txq_imr_txeol &= ah->ah_txq_status;
3569
3570 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
3571 AR5K_SIMR0_QCU_TXOK) |
3572 AR5K_REG_SM(ah->ah_txq_imr_txdesc,
3573 AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
3574 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
3575 AR5K_SIMR1_QCU_TXERR) |
3576 AR5K_REG_SM(ah->ah_txq_imr_txeol,
3577 AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
3578 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txurn,
3579 AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
3580 }
3581
3582 return 0;
3583 }
3584
3585 /*
3586 * Get number of pending frames
3587 * for a specific queue [5211+]
3588 */
3589 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) {
3590 ATH5K_TRACE(ah->ah_sc);
3591 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3592
3593 /* Return if queue is declared inactive */
3594 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3595 return false;
3596
3597 /* XXX: How about AR5K_CFG_TXCNT ? */
3598 if (ah->ah_version == AR5K_AR5210)
3599 return false;
3600
3601 return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT;
3602 }
3603
3604 /*
3605 * Set slot time
3606 */
3607 int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
3608 {
3609 ATH5K_TRACE(ah->ah_sc);
3610 if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
3611 return -EINVAL;
3612
3613 if (ah->ah_version == AR5K_AR5210)
3614 ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
3615 ah->ah_turbo), AR5K_SLOT_TIME);
3616 else
3617 ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);
3618
3619 return 0;
3620 }
3621
3622 /*
3623 * Get slot time
3624 */
3625 unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah)
3626 {
3627 ATH5K_TRACE(ah->ah_sc);
3628 if (ah->ah_version == AR5K_AR5210)
3629 return ath5k_hw_clocktoh(ath5k_hw_reg_read(ah,
3630 AR5K_SLOT_TIME) & 0xffff, ah->ah_turbo);
3631 else
3632 return ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
3633 }
3634
3635
3636 /******************************\
3637 Hardware Descriptor Functions
3638 \******************************/
3639
3640 /*
3641 * TX Descriptor
3642 */
3643
3644 /*
3645 * Initialize the 2-word tx descriptor on 5210/5211
3646 */
3647 static int
3648 ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3649 unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
3650 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
3651 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
3652 unsigned int rtscts_rate, unsigned int rtscts_duration)
3653 {
3654 u32 frame_type;
3655 struct ath5k_hw_2w_tx_ctl *tx_ctl;
3656 unsigned int frame_len;
3657
3658 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
3659
3660 /*
3661 * Validate input
3662 * - Zero retries don't make sense.
3663 * - A zero rate will put the HW into a mode where it continously sends
3664 * noise on the channel, so it is important to avoid this.
3665 */
3666 if (unlikely(tx_tries0 == 0)) {
3667 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3668 WARN_ON(1);
3669 return -EINVAL;
3670 }
3671 if (unlikely(tx_rate0 == 0)) {
3672 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3673 WARN_ON(1);
3674 return -EINVAL;
3675 }
3676
3677 /* Clear descriptor */
3678 memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
3679
3680 /* Setup control descriptor */
3681
3682 /* Verify and set frame length */
3683
3684 /* remove padding we might have added before */
3685 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3686
3687 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
3688 return -EINVAL;
3689
3690 tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
3691
3692 /* Verify and set buffer length */
3693
3694 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3695 if(type == AR5K_PKT_TYPE_BEACON)
3696 pkt_len = roundup(pkt_len, 4);
3697
3698 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
3699 return -EINVAL;
3700
3701 tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
3702
3703 /*
3704 * Verify and set header length
3705 * XXX: I only found that on 5210 code, does it work on 5211 ?
3706 */
3707 if (ah->ah_version == AR5K_AR5210) {
3708 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
3709 return -EINVAL;
3710 tx_ctl->tx_control_0 |=
3711 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
3712 }
3713
3714 /*Diferences between 5210-5211*/
3715 if (ah->ah_version == AR5K_AR5210) {
3716 switch (type) {
3717 case AR5K_PKT_TYPE_BEACON:
3718 case AR5K_PKT_TYPE_PROBE_RESP:
3719 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
3720 case AR5K_PKT_TYPE_PIFS:
3721 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
3722 default:
3723 frame_type = type /*<< 2 ?*/;
3724 }
3725
3726 tx_ctl->tx_control_0 |=
3727 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
3728 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3729 } else {
3730 tx_ctl->tx_control_0 |=
3731 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
3732 AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
3733 tx_ctl->tx_control_1 |=
3734 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
3735 }
3736 #define _TX_FLAGS(_c, _flag) \
3737 if (flags & AR5K_TXDESC_##_flag) \
3738 tx_ctl->tx_control_##_c |= \
3739 AR5K_2W_TX_DESC_CTL##_c##_##_flag
3740
3741 _TX_FLAGS(0, CLRDMASK);
3742 _TX_FLAGS(0, VEOL);
3743 _TX_FLAGS(0, INTREQ);
3744 _TX_FLAGS(0, RTSENA);
3745 _TX_FLAGS(1, NOACK);
3746
3747 #undef _TX_FLAGS
3748
3749 /*
3750 * WEP crap
3751 */
3752 if (key_index != AR5K_TXKEYIX_INVALID) {
3753 tx_ctl->tx_control_0 |=
3754 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3755 tx_ctl->tx_control_1 |=
3756 AR5K_REG_SM(key_index,
3757 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3758 }
3759
3760 /*
3761 * RTS/CTS Duration [5210 ?]
3762 */
3763 if ((ah->ah_version == AR5K_AR5210) &&
3764 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
3765 tx_ctl->tx_control_1 |= rtscts_duration &
3766 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
3767
3768 return 0;
3769 }
3770
3771 /*
3772 * Initialize the 4-word tx descriptor on 5212
3773 */
3774 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3775 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
3776 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
3777 unsigned int tx_tries0, unsigned int key_index,
3778 unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate,
3779 unsigned int rtscts_duration)
3780 {
3781 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3782 unsigned int frame_len;
3783
3784 ATH5K_TRACE(ah->ah_sc);
3785 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3786
3787 /*
3788 * Validate input
3789 * - Zero retries don't make sense.
3790 * - A zero rate will put the HW into a mode where it continously sends
3791 * noise on the channel, so it is important to avoid this.
3792 */
3793 if (unlikely(tx_tries0 == 0)) {
3794 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3795 WARN_ON(1);
3796 return -EINVAL;
3797 }
3798 if (unlikely(tx_rate0 == 0)) {
3799 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3800 WARN_ON(1);
3801 return -EINVAL;
3802 }
3803
3804 /* Clear descriptor */
3805 memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
3806
3807 /* Setup control descriptor */
3808
3809 /* Verify and set frame length */
3810
3811 /* remove padding we might have added before */
3812 frame_len = pkt_len - (hdr_len & 3) + FCS_LEN;
3813
3814 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
3815 return -EINVAL;
3816
3817 tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
3818
3819 /* Verify and set buffer length */
3820
3821 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3822 if(type == AR5K_PKT_TYPE_BEACON)
3823 pkt_len = roundup(pkt_len, 4);
3824
3825 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
3826 return -EINVAL;
3827
3828 tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
3829
3830 tx_ctl->tx_control_0 |=
3831 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
3832 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
3833 tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
3834 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
3835 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
3836 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
3837 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3838
3839 #define _TX_FLAGS(_c, _flag) \
3840 if (flags & AR5K_TXDESC_##_flag) \
3841 tx_ctl->tx_control_##_c |= \
3842 AR5K_4W_TX_DESC_CTL##_c##_##_flag
3843
3844 _TX_FLAGS(0, CLRDMASK);
3845 _TX_FLAGS(0, VEOL);
3846 _TX_FLAGS(0, INTREQ);
3847 _TX_FLAGS(0, RTSENA);
3848 _TX_FLAGS(0, CTSENA);
3849 _TX_FLAGS(1, NOACK);
3850
3851 #undef _TX_FLAGS
3852
3853 /*
3854 * WEP crap
3855 */
3856 if (key_index != AR5K_TXKEYIX_INVALID) {
3857 tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3858 tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
3859 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3860 }
3861
3862 /*
3863 * RTS/CTS
3864 */
3865 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
3866 if ((flags & AR5K_TXDESC_RTSENA) &&
3867 (flags & AR5K_TXDESC_CTSENA))
3868 return -EINVAL;
3869 tx_ctl->tx_control_2 |= rtscts_duration &
3870 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
3871 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
3872 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
3873 }
3874
3875 return 0;
3876 }
3877
3878 /*
3879 * Initialize a 4-word multirate tx descriptor on 5212
3880 */
3881 static int
3882 ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3883 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
3884 unsigned int tx_rate3, u_int tx_tries3)
3885 {
3886 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3887
3888 /*
3889 * Rates can be 0 as long as the retry count is 0 too.
3890 * A zero rate and nonzero retry count will put the HW into a mode where
3891 * it continously sends noise on the channel, so it is important to
3892 * avoid this.
3893 */
3894 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
3895 (tx_rate2 == 0 && tx_tries2 != 0) ||
3896 (tx_rate3 == 0 && tx_tries3 != 0))) {
3897 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3898 WARN_ON(1);
3899 return -EINVAL;
3900 }
3901
3902 if (ah->ah_version == AR5K_AR5212) {
3903 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3904
3905 #define _XTX_TRIES(_n) \
3906 if (tx_tries##_n) { \
3907 tx_ctl->tx_control_2 |= \
3908 AR5K_REG_SM(tx_tries##_n, \
3909 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
3910 tx_ctl->tx_control_3 |= \
3911 AR5K_REG_SM(tx_rate##_n, \
3912 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
3913 }
3914
3915 _XTX_TRIES(1);
3916 _XTX_TRIES(2);
3917 _XTX_TRIES(3);
3918
3919 #undef _XTX_TRIES
3920
3921 return 1;
3922 }
3923
3924 return 0;
3925 }
3926
3927 /*
3928 * Proccess the tx status descriptor on 5210/5211
3929 */
3930 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
3931 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
3932 {
3933 struct ath5k_hw_2w_tx_ctl *tx_ctl;
3934 struct ath5k_hw_tx_status *tx_status;
3935
3936 ATH5K_TRACE(ah->ah_sc);
3937
3938 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
3939 tx_status = &desc->ud.ds_tx5210.tx_stat;
3940
3941 /* No frame has been send or error */
3942 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3943 return -EINPROGRESS;
3944
3945 /*
3946 * Get descriptor status
3947 */
3948 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3949 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3950 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3951 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3952 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3953 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3954 /*TODO: ts->ts_virtcol + test*/
3955 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3956 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3957 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3958 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3959 ts->ts_antenna = 1;
3960 ts->ts_status = 0;
3961 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_0,
3962 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3963
3964 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3965 if (tx_status->tx_status_0 &
3966 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3967 ts->ts_status |= AR5K_TXERR_XRETRY;
3968
3969 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3970 ts->ts_status |= AR5K_TXERR_FIFO;
3971
3972 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3973 ts->ts_status |= AR5K_TXERR_FILT;
3974 }
3975
3976 return 0;
3977 }
3978
3979 /*
3980 * Proccess a tx descriptor on 5212
3981 */
3982 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
3983 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
3984 {
3985 struct ath5k_hw_4w_tx_ctl *tx_ctl;
3986 struct ath5k_hw_tx_status *tx_status;
3987
3988 ATH5K_TRACE(ah->ah_sc);
3989
3990 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
3991 tx_status = &desc->ud.ds_tx5212.tx_stat;
3992
3993 /* No frame has been send or error */
3994 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3995 return -EINPROGRESS;
3996
3997 /*
3998 * Get descriptor status
3999 */
4000 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
4001 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
4002 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
4003 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
4004 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
4005 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
4006 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
4007 AR5K_DESC_TX_STATUS1_SEQ_NUM);
4008 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
4009 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
4010 ts->ts_antenna = (tx_status->tx_status_1 &
4011 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
4012 ts->ts_status = 0;
4013
4014 switch (AR5K_REG_MS(tx_status->tx_status_1,
4015 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
4016 case 0:
4017 ts->ts_rate = tx_ctl->tx_control_3 &
4018 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
4019 break;
4020 case 1:
4021 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
4022 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
4023 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
4024 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
4025 break;
4026 case 2:
4027 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
4028 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
4029 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
4030 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
4031 break;
4032 case 3:
4033 ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
4034 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
4035 ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
4036 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
4037 break;
4038 }
4039
4040 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
4041 if (tx_status->tx_status_0 &
4042 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
4043 ts->ts_status |= AR5K_TXERR_XRETRY;
4044
4045 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
4046 ts->ts_status |= AR5K_TXERR_FIFO;
4047
4048 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
4049 ts->ts_status |= AR5K_TXERR_FILT;
4050 }
4051
4052 return 0;
4053 }
4054
4055 /*
4056 * RX Descriptor
4057 */
4058
4059 /*
4060 * Initialize an rx descriptor
4061 */
4062 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
4063 u32 size, unsigned int flags)
4064 {
4065 struct ath5k_hw_rx_ctl *rx_ctl;
4066
4067 ATH5K_TRACE(ah->ah_sc);
4068 rx_ctl = &desc->ud.ds_rx.rx_ctl;
4069
4070 /*
4071 * Clear the descriptor
4072 * If we don't clean the status descriptor,
4073 * while scanning we get too many results,
4074 * most of them virtual, after some secs
4075 * of scanning system hangs. M.F.
4076 */
4077 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
4078
4079 /* Setup descriptor */
4080 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
4081 if (unlikely(rx_ctl->rx_control_1 != size))
4082 return -EINVAL;
4083
4084 if (flags & AR5K_RXDESC_INTREQ)
4085 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
4086
4087 return 0;
4088 }
4089
4090 /*
4091 * Proccess the rx status descriptor on 5210/5211
4092 */
4093 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
4094 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
4095 {
4096 struct ath5k_hw_rx_status *rx_status;
4097
4098 rx_status = &desc->ud.ds_rx.u.rx_stat;
4099
4100 /* No frame received / not ready */
4101 if (unlikely((rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE)
4102 == 0))
4103 return -EINPROGRESS;
4104
4105 /*
4106 * Frame receive status
4107 */
4108 rs->rs_datalen = rx_status->rx_status_0 &
4109 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
4110 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4111 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4112 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4113 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
4114 rs->rs_antenna = rx_status->rx_status_0 &
4115 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4116 rs->rs_more = rx_status->rx_status_0 &
4117 AR5K_5210_RX_DESC_STATUS0_MORE;
4118 /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
4119 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4120 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4121 rs->rs_status = 0;
4122 rs->rs_phyerr = 0;
4123
4124 /*
4125 * Key table status
4126 */
4127 if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
4128 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4129 AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
4130 else
4131 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
4132
4133 /*
4134 * Receive/descriptor errors
4135 */
4136 if ((rx_status->rx_status_1 &
4137 AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4138 if (rx_status->rx_status_1 &
4139 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
4140 rs->rs_status |= AR5K_RXERR_CRC;
4141
4142 if (rx_status->rx_status_1 &
4143 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
4144 rs->rs_status |= AR5K_RXERR_FIFO;
4145
4146 if (rx_status->rx_status_1 &
4147 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
4148 rs->rs_status |= AR5K_RXERR_PHY;
4149 rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
4150 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
4151 }
4152
4153 if (rx_status->rx_status_1 &
4154 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4155 rs->rs_status |= AR5K_RXERR_DECRYPT;
4156 }
4157
4158 return 0;
4159 }
4160
4161 /*
4162 * Proccess the rx status descriptor on 5212
4163 */
4164 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
4165 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
4166 {
4167 struct ath5k_hw_rx_status *rx_status;
4168 struct ath5k_hw_rx_error *rx_err;
4169
4170 ATH5K_TRACE(ah->ah_sc);
4171 rx_status = &desc->ud.ds_rx.u.rx_stat;
4172
4173 /* Overlay on error */
4174 rx_err = &desc->ud.ds_rx.u.rx_err;
4175
4176 /* No frame received / not ready */
4177 if (unlikely((rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE)
4178 == 0))
4179 return -EINPROGRESS;
4180
4181 /*
4182 * Frame receive status
4183 */
4184 rs->rs_datalen = rx_status->rx_status_0 &
4185 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
4186 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4187 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4188 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4189 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
4190 rs->rs_antenna = rx_status->rx_status_0 &
4191 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4192 rs->rs_more = rx_status->rx_status_0 &
4193 AR5K_5212_RX_DESC_STATUS0_MORE;
4194 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4195 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4196 rs->rs_status = 0;
4197 rs->rs_phyerr = 0;
4198
4199 /*
4200 * Key table status
4201 */
4202 if (rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
4203 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4204 AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
4205 else
4206 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
4207
4208 /*
4209 * Receive/descriptor errors
4210 */
4211 if ((rx_status->rx_status_1 &
4212 AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4213 if (rx_status->rx_status_1 &
4214 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
4215 rs->rs_status |= AR5K_RXERR_CRC;
4216
4217 if (rx_status->rx_status_1 &
4218 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
4219 rs->rs_status |= AR5K_RXERR_PHY;
4220 rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1,
4221 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
4222 }
4223
4224 if (rx_status->rx_status_1 &
4225 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4226 rs->rs_status |= AR5K_RXERR_DECRYPT;
4227
4228 if (rx_status->rx_status_1 &
4229 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
4230 rs->rs_status |= AR5K_RXERR_MIC;
4231 }
4232
4233 return 0;
4234 }
4235
4236
4237 /****************\
4238 GPIO Functions
4239 \****************/
4240
4241 /*
4242 * Set led state
4243 */
4244 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
4245 {
4246 u32 led;
4247 /*5210 has different led mode handling*/
4248 u32 led_5210;
4249
4250 ATH5K_TRACE(ah->ah_sc);
4251
4252 /*Reset led status*/
4253 if (ah->ah_version != AR5K_AR5210)
4254 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
4255 AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED);
4256 else
4257 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_LED);
4258
4259 /*
4260 * Some blinking values, define at your wish
4261 */
4262 switch (state) {
4263 case AR5K_LED_SCAN:
4264 case AR5K_LED_AUTH:
4265 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND;
4266 led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL;
4267 break;
4268
4269 case AR5K_LED_INIT:
4270 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE;
4271 led_5210 = AR5K_PCICFG_LED_PEND;
4272 break;
4273
4274 case AR5K_LED_ASSOC:
4275 case AR5K_LED_RUN:
4276 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC;
4277 led_5210 = AR5K_PCICFG_LED_ASSOC;
4278 break;
4279
4280 default:
4281 led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE;
4282 led_5210 = AR5K_PCICFG_LED_PEND;
4283 break;
4284 }
4285
4286 /*Write new status to the register*/
4287 if (ah->ah_version != AR5K_AR5210)
4288 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led);
4289 else
4290 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
4291 }
4292
4293 /*
4294 * Set GPIO outputs
4295 */
4296 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
4297 {
4298 ATH5K_TRACE(ah->ah_sc);
4299 if (gpio > AR5K_NUM_GPIO)
4300 return -EINVAL;
4301
4302 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4303 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
4304
4305 return 0;
4306 }
4307
4308 /*
4309 * Set GPIO inputs
4310 */
4311 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
4312 {
4313 ATH5K_TRACE(ah->ah_sc);
4314 if (gpio > AR5K_NUM_GPIO)
4315 return -EINVAL;
4316
4317 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4318 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
4319
4320 return 0;
4321 }
4322
4323 /*
4324 * Get GPIO state
4325 */
4326 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
4327 {
4328 ATH5K_TRACE(ah->ah_sc);
4329 if (gpio > AR5K_NUM_GPIO)
4330 return 0xffffffff;
4331
4332 /* GPIO input magic */
4333 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
4334 0x1;
4335 }
4336
4337 /*
4338 * Set GPIO state
4339 */
4340 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
4341 {
4342 u32 data;
4343 ATH5K_TRACE(ah->ah_sc);
4344
4345 if (gpio > AR5K_NUM_GPIO)
4346 return -EINVAL;
4347
4348 /* GPIO output magic */
4349 data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
4350
4351 data &= ~(1 << gpio);
4352 data |= (val & 1) << gpio;
4353
4354 ath5k_hw_reg_write(ah, data, AR5K_GPIODO);
4355
4356 return 0;
4357 }
4358
4359 /*
4360 * Initialize the GPIO interrupt (RFKill switch)
4361 */
4362 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
4363 u32 interrupt_level)
4364 {
4365 u32 data;
4366
4367 ATH5K_TRACE(ah->ah_sc);
4368 if (gpio > AR5K_NUM_GPIO)
4369 return;
4370
4371 /*
4372 * Set the GPIO interrupt
4373 */
4374 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
4375 ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
4376 AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
4377 (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
4378
4379 ath5k_hw_reg_write(ah, interrupt_level ? data :
4380 (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
4381
4382 ah->ah_imr |= AR5K_IMR_GPIO;
4383
4384 /* Enable GPIO interrupts */
4385 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO);
4386 }
4387
4388
4389
4390
4391 /****************\
4392 Misc functions
4393 \****************/
4394
4395 int ath5k_hw_get_capability(struct ath5k_hw *ah,
4396 enum ath5k_capability_type cap_type,
4397 u32 capability, u32 *result)
4398 {
4399 ATH5K_TRACE(ah->ah_sc);
4400
4401 switch (cap_type) {
4402 case AR5K_CAP_NUM_TXQUEUES:
4403 if (result) {
4404 if (ah->ah_version == AR5K_AR5210)
4405 *result = AR5K_NUM_TX_QUEUES_NOQCU;
4406 else
4407 *result = AR5K_NUM_TX_QUEUES;
4408 goto yes;
4409 }
4410 case AR5K_CAP_VEOL:
4411 goto yes;
4412 case AR5K_CAP_COMPRESSION:
4413 if (ah->ah_version == AR5K_AR5212)
4414 goto yes;
4415 else
4416 goto no;
4417 case AR5K_CAP_BURST:
4418 goto yes;
4419 case AR5K_CAP_TPC:
4420 goto yes;
4421 case AR5K_CAP_BSSIDMASK:
4422 if (ah->ah_version == AR5K_AR5212)
4423 goto yes;
4424 else
4425 goto no;
4426 case AR5K_CAP_XR:
4427 if (ah->ah_version == AR5K_AR5212)
4428 goto yes;
4429 else
4430 goto no;
4431 default:
4432 goto no;
4433 }
4434
4435 no:
4436 return -EINVAL;
4437 yes:
4438 return 0;
4439 }
4440
4441 static int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
4442 u16 assoc_id)
4443 {
4444 ATH5K_TRACE(ah->ah_sc);
4445
4446 if (ah->ah_version == AR5K_AR5210) {
4447 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
4448 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4449 return 0;
4450 }
4451
4452 return -EIO;
4453 }
4454
4455 static int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
4456 {
4457 ATH5K_TRACE(ah->ah_sc);
4458
4459 if (ah->ah_version == AR5K_AR5210) {
4460 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
4461 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4462 return 0;
4463 }
4464
4465 return -EIO;
4466 }
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