2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 /*********************************\
24 * Protocol Control Unit Functions *
25 \*********************************/
37 * ath5k_hw_set_opmode - Set PCU operating mode
39 * @ah: The &struct ath5k_hw
41 * Initialize PCU for the various operating modes (AP/STA etc)
43 * NOTE: ah->ah_op_mode must be set before calling this.
45 int ath5k_hw_set_opmode(struct ath5k_hw
*ah
)
47 u32 pcu_reg
, beacon_reg
, low_id
, high_id
;
50 /* Preserve rest settings */
51 pcu_reg
= ath5k_hw_reg_read(ah
, AR5K_STA_ID1
) & 0xffff0000;
52 pcu_reg
&= ~(AR5K_STA_ID1_ADHOC
| AR5K_STA_ID1_AP
53 | AR5K_STA_ID1_KEYSRCH_MODE
54 | (ah
->ah_version
== AR5K_AR5210
?
55 (AR5K_STA_ID1_PWR_SV
| AR5K_STA_ID1_NO_PSPOLL
) : 0));
59 ATH5K_TRACE(ah
->ah_sc
);
61 switch (ah
->ah_op_mode
) {
62 case NL80211_IFTYPE_ADHOC
:
63 pcu_reg
|= AR5K_STA_ID1_ADHOC
| AR5K_STA_ID1_KEYSRCH_MODE
;
64 beacon_reg
|= AR5K_BCR_ADHOC
;
65 if (ah
->ah_version
== AR5K_AR5210
)
66 pcu_reg
|= AR5K_STA_ID1_NO_PSPOLL
;
68 AR5K_REG_ENABLE_BITS(ah
, AR5K_CFG
, AR5K_CFG_IBSS
);
71 case NL80211_IFTYPE_AP
:
72 case NL80211_IFTYPE_MESH_POINT
:
73 pcu_reg
|= AR5K_STA_ID1_AP
| AR5K_STA_ID1_KEYSRCH_MODE
;
74 beacon_reg
|= AR5K_BCR_AP
;
75 if (ah
->ah_version
== AR5K_AR5210
)
76 pcu_reg
|= AR5K_STA_ID1_NO_PSPOLL
;
78 AR5K_REG_DISABLE_BITS(ah
, AR5K_CFG
, AR5K_CFG_IBSS
);
81 case NL80211_IFTYPE_STATION
:
82 pcu_reg
|= AR5K_STA_ID1_KEYSRCH_MODE
83 | (ah
->ah_version
== AR5K_AR5210
?
84 AR5K_STA_ID1_PWR_SV
: 0);
85 case NL80211_IFTYPE_MONITOR
:
86 pcu_reg
|= AR5K_STA_ID1_KEYSRCH_MODE
87 | (ah
->ah_version
== AR5K_AR5210
?
88 AR5K_STA_ID1_NO_PSPOLL
: 0);
98 low_id
= AR5K_LOW_ID(ah
->ah_sta_id
);
99 high_id
= AR5K_HIGH_ID(ah
->ah_sta_id
);
100 ath5k_hw_reg_write(ah
, low_id
, AR5K_STA_ID0
);
101 ath5k_hw_reg_write(ah
, pcu_reg
| high_id
, AR5K_STA_ID1
);
104 * Set Beacon Control Register on 5210
106 if (ah
->ah_version
== AR5K_AR5210
)
107 ath5k_hw_reg_write(ah
, beacon_reg
, AR5K_BCR
);
113 * ath5k_hw_update - Update mib counters (mac layer statistics)
115 * @ah: The &struct ath5k_hw
116 * @stats: The &struct ieee80211_low_level_stats we use to track
117 * statistics on the driver
119 * Reads MIB counters from PCU and updates sw statistics. Must be
120 * called after a MIB interrupt.
122 void ath5k_hw_update_mib_counters(struct ath5k_hw
*ah
,
123 struct ieee80211_low_level_stats
*stats
)
125 ATH5K_TRACE(ah
->ah_sc
);
128 stats
->dot11ACKFailureCount
+= ath5k_hw_reg_read(ah
, AR5K_ACK_FAIL
);
129 stats
->dot11RTSFailureCount
+= ath5k_hw_reg_read(ah
, AR5K_RTS_FAIL
);
130 stats
->dot11RTSSuccessCount
+= ath5k_hw_reg_read(ah
, AR5K_RTS_OK
);
131 stats
->dot11FCSErrorCount
+= ath5k_hw_reg_read(ah
, AR5K_FCS_FAIL
);
133 /* XXX: Should we use this to track beacon count ?
134 * -we read it anyway to clear the register */
135 ath5k_hw_reg_read(ah
, AR5K_BEACON_CNT
);
137 /* Reset profile count registers on 5212*/
138 if (ah
->ah_version
== AR5K_AR5212
) {
139 ath5k_hw_reg_write(ah
, 0, AR5K_PROFCNT_TX
);
140 ath5k_hw_reg_write(ah
, 0, AR5K_PROFCNT_RX
);
141 ath5k_hw_reg_write(ah
, 0, AR5K_PROFCNT_RXCLR
);
142 ath5k_hw_reg_write(ah
, 0, AR5K_PROFCNT_CYCLE
);
145 /* TODO: Handle ANI stats */
149 * ath5k_hw_set_ack_bitrate - set bitrate for ACKs
151 * @ah: The &struct ath5k_hw
152 * @high: Flag to determine if we want to use high transmition rate
155 * If high flag is set, we tell hw to use a set of control rates based on
156 * the current transmition rate (check out control_rates array inside reset.c).
157 * If not hw just uses the lowest rate available for the current modulation
158 * scheme being used (1Mbit for CCK and 6Mbits for OFDM).
160 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw
*ah
, bool high
)
162 if (ah
->ah_version
!= AR5K_AR5212
)
165 u32 val
= AR5K_STA_ID1_BASE_RATE_11B
| AR5K_STA_ID1_ACKCTS_6MB
;
167 AR5K_REG_ENABLE_BITS(ah
, AR5K_STA_ID1
, val
);
169 AR5K_REG_DISABLE_BITS(ah
, AR5K_STA_ID1
, val
);
179 * ath5k_hw_het_ack_timeout - Get ACK timeout from PCU in usec
181 * @ah: The &struct ath5k_hw
183 unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw
*ah
)
185 ATH5K_TRACE(ah
->ah_sc
);
187 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah
,
188 AR5K_TIME_OUT
), AR5K_TIME_OUT_ACK
), ah
->ah_turbo
);
192 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
194 * @ah: The &struct ath5k_hw
195 * @timeout: Timeout in usec
197 int ath5k_hw_set_ack_timeout(struct ath5k_hw
*ah
, unsigned int timeout
)
199 ATH5K_TRACE(ah
->ah_sc
);
200 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK
),
201 ah
->ah_turbo
) <= timeout
)
204 AR5K_REG_WRITE_BITS(ah
, AR5K_TIME_OUT
, AR5K_TIME_OUT_ACK
,
205 ath5k_hw_htoclock(timeout
, ah
->ah_turbo
));
211 * ath5k_hw_get_cts_timeout - Get CTS timeout from PCU in usec
213 * @ah: The &struct ath5k_hw
215 unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw
*ah
)
217 ATH5K_TRACE(ah
->ah_sc
);
218 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah
,
219 AR5K_TIME_OUT
), AR5K_TIME_OUT_CTS
), ah
->ah_turbo
);
223 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
225 * @ah: The &struct ath5k_hw
226 * @timeout: Timeout in usec
228 int ath5k_hw_set_cts_timeout(struct ath5k_hw
*ah
, unsigned int timeout
)
230 ATH5K_TRACE(ah
->ah_sc
);
231 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS
),
232 ah
->ah_turbo
) <= timeout
)
235 AR5K_REG_WRITE_BITS(ah
, AR5K_TIME_OUT
, AR5K_TIME_OUT_CTS
,
236 ath5k_hw_htoclock(timeout
, ah
->ah_turbo
));
247 * ath5k_hw_get_lladdr - Get station id
249 * @ah: The &struct ath5k_hw
250 * @mac: The card's mac address
252 * Initialize ah->ah_sta_id using the mac address provided
255 * TODO: Remove it once we merge ath5k_softc and ath5k_hw
257 void ath5k_hw_get_lladdr(struct ath5k_hw
*ah
, u8
*mac
)
259 ATH5K_TRACE(ah
->ah_sc
);
260 memcpy(mac
, ah
->ah_sta_id
, ETH_ALEN
);
264 * ath5k_hw_set_lladdr - Set station id
266 * @ah: The &struct ath5k_hw
267 * @mac: The card's mac address
269 * Set station id on hw using the provided mac address
271 int ath5k_hw_set_lladdr(struct ath5k_hw
*ah
, const u8
*mac
)
276 ATH5K_TRACE(ah
->ah_sc
);
277 /* Set new station ID */
278 memcpy(ah
->ah_sta_id
, mac
, ETH_ALEN
);
280 pcu_reg
= ath5k_hw_reg_read(ah
, AR5K_STA_ID1
) & 0xffff0000;
282 low_id
= AR5K_LOW_ID(mac
);
283 high_id
= AR5K_HIGH_ID(mac
);
285 ath5k_hw_reg_write(ah
, low_id
, AR5K_STA_ID0
);
286 ath5k_hw_reg_write(ah
, pcu_reg
| high_id
, AR5K_STA_ID1
);
292 * ath5k_hw_set_associd - Set BSSID for association
294 * @ah: The &struct ath5k_hw
296 * @assoc_id: Assoc id
298 * Sets the BSSID which trigers the "SME Join" operation
300 void ath5k_hw_set_associd(struct ath5k_hw
*ah
, const u8
*bssid
, u16 assoc_id
)
306 * Set simple BSSID mask on 5212
308 if (ah
->ah_version
== AR5K_AR5212
) {
309 ath5k_hw_reg_write(ah
, AR5K_LOW_ID(ah
->ah_bssid_mask
),
311 ath5k_hw_reg_write(ah
, AR5K_HIGH_ID(ah
->ah_bssid_mask
),
316 * Set BSSID which triggers the "SME Join" operation
318 low_id
= AR5K_LOW_ID(bssid
);
319 high_id
= AR5K_HIGH_ID(bssid
);
320 ath5k_hw_reg_write(ah
, low_id
, AR5K_BSS_ID0
);
321 ath5k_hw_reg_write(ah
, high_id
| ((assoc_id
& 0x3fff) <<
322 AR5K_BSS_ID1_AID_S
), AR5K_BSS_ID1
);
325 ath5k_hw_disable_pspoll(ah
);
329 AR5K_REG_WRITE_BITS(ah
, AR5K_BEACON
, AR5K_BEACON_TIM
,
330 tim_offset
? tim_offset
+ 4 : 0);
332 ath5k_hw_enable_pspoll(ah
, NULL
, 0);
336 * ath5k_hw_set_bssid_mask - filter out bssids we listen
338 * @ah: the &struct ath5k_hw
339 * @mask: the bssid_mask, a u8 array of size ETH_ALEN
341 * BSSID masking is a method used by AR5212 and newer hardware to inform PCU
342 * which bits of the interface's MAC address should be looked at when trying
343 * to decide which packets to ACK. In station mode and AP mode with a single
344 * BSS every bit matters since we lock to only one BSS. In AP mode with
345 * multiple BSSes (virtual interfaces) not every bit matters because hw must
346 * accept frames for all BSSes and so we tweak some bits of our mac address
347 * in order to have multiple BSSes.
349 * NOTE: This is a simple filter and does *not* filter out all
350 * relevant frames. Some frames that are not for us might get ACKed from us
351 * by PCU because they just match the mask.
353 * When handling multiple BSSes you can get the BSSID mask by computing the
354 * set of ~ ( MAC XOR BSSID ) for all bssids we handle.
356 * When you do this you are essentially computing the common bits of all your
357 * BSSes. Later it is assumed the harware will "and" (&) the BSSID mask with
358 * the MAC address to obtain the relevant bits and compare the result with
359 * (frame's BSSID & mask) to see if they match.
362 * Simple example: on your card you have have two BSSes you have created with
363 * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
364 * There is another BSSID-03 but you are not part of it. For simplicity's sake,
365 * assuming only 4 bits for a mac address and for BSSIDs you can then have:
369 * BSSID-01: 0100 | --> Belongs to us
372 * -------------------
373 * BSSID-03: 0110 | --> External
374 * -------------------
376 * Our bssid_mask would then be:
378 * On loop iteration for BSSID-01:
379 * ~(0001 ^ 0100) -> ~(0101)
383 * On loop iteration for BSSID-02:
384 * bssid_mask &= ~(0001 ^ 1001)
385 * bssid_mask = (1010) & ~(0001 ^ 1001)
386 * bssid_mask = (1010) & ~(1001)
387 * bssid_mask = (1010) & (0110)
390 * A bssid_mask of 0010 means "only pay attention to the second least
391 * significant bit". This is because its the only bit common
392 * amongst the MAC and all BSSIDs we support. To findout what the real
393 * common bit is we can simply "&" the bssid_mask now with any BSSID we have
394 * or our MAC address (we assume the hardware uses the MAC address).
396 * Now, suppose there's an incoming frame for BSSID-03:
400 * An easy eye-inspeciton of this already should tell you that this frame
401 * will not pass our check. This is beacuse the bssid_mask tells the
402 * hardware to only look at the second least significant bit and the
403 * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
404 * as 1, which does not match 0.
406 * So with IFRAME-01 we *assume* the hardware will do:
408 * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
409 * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
410 * --> allow = (0010) == 0000 ? 1 : 0;
413 * Lets now test a frame that should work:
415 * IFRAME-02: 0001 (we should allow)
417 * allow = (0001 & 1010) == 1010
419 * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
420 * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
421 * --> allow = (0010) == (0010)
426 * IFRAME-03: 0100 --> allowed
427 * IFRAME-04: 1001 --> allowed
428 * IFRAME-05: 1101 --> allowed but its not for us!!!
431 int ath5k_hw_set_bssid_mask(struct ath5k_hw
*ah
, const u8
*mask
)
434 ATH5K_TRACE(ah
->ah_sc
);
436 /* Cache bssid mask so that we can restore it
438 memcpy(ah
->ah_bssid_mask
, mask
, ETH_ALEN
);
439 if (ah
->ah_version
== AR5K_AR5212
) {
440 low_id
= AR5K_LOW_ID(mask
);
441 high_id
= AR5K_HIGH_ID(mask
);
443 ath5k_hw_reg_write(ah
, low_id
, AR5K_BSS_IDM0
);
444 ath5k_hw_reg_write(ah
, high_id
, AR5K_BSS_IDM1
);
458 * ath5k_hw_start_rx_pcu - Start RX engine
460 * @ah: The &struct ath5k_hw
462 * Starts RX engine on PCU so that hw can process RXed frames
465 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
466 * TODO: Init ANI here
468 void ath5k_hw_start_rx_pcu(struct ath5k_hw
*ah
)
470 ATH5K_TRACE(ah
->ah_sc
);
471 AR5K_REG_DISABLE_BITS(ah
, AR5K_DIAG_SW
, AR5K_DIAG_SW_DIS_RX
);
475 * at5k_hw_stop_rx_pcu - Stop RX engine
477 * @ah: The &struct ath5k_hw
479 * Stops RX engine on PCU
481 * TODO: Detach ANI here
483 void ath5k_hw_stop_rx_pcu(struct ath5k_hw
*ah
)
485 ATH5K_TRACE(ah
->ah_sc
);
486 AR5K_REG_ENABLE_BITS(ah
, AR5K_DIAG_SW
, AR5K_DIAG_SW_DIS_RX
);
490 * Set multicast filter
492 void ath5k_hw_set_mcast_filter(struct ath5k_hw
*ah
, u32 filter0
, u32 filter1
)
494 ATH5K_TRACE(ah
->ah_sc
);
495 /* Set the multicat filter */
496 ath5k_hw_reg_write(ah
, filter0
, AR5K_MCAST_FILTER0
);
497 ath5k_hw_reg_write(ah
, filter1
, AR5K_MCAST_FILTER1
);
501 * Set multicast filter by index
503 int ath5k_hw_set_mcast_filter_idx(struct ath5k_hw
*ah
, u32 index
)
506 ATH5K_TRACE(ah
->ah_sc
);
509 else if (index
>= 32)
510 AR5K_REG_ENABLE_BITS(ah
, AR5K_MCAST_FILTER1
,
511 (1 << (index
- 32)));
513 AR5K_REG_ENABLE_BITS(ah
, AR5K_MCAST_FILTER0
, (1 << index
));
519 * Clear Multicast filter by index
521 int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw
*ah
, u32 index
)
524 ATH5K_TRACE(ah
->ah_sc
);
527 else if (index
>= 32)
528 AR5K_REG_DISABLE_BITS(ah
, AR5K_MCAST_FILTER1
,
529 (1 << (index
- 32)));
531 AR5K_REG_DISABLE_BITS(ah
, AR5K_MCAST_FILTER0
, (1 << index
));
537 * ath5k_hw_get_rx_filter - Get current rx filter
539 * @ah: The &struct ath5k_hw
541 * Returns the RX filter by reading rx filter and
542 * phy error filter registers. RX filter is used
543 * to set the allowed frame types that PCU will accept
544 * and pass to the driver. For a list of frame types
547 u32
ath5k_hw_get_rx_filter(struct ath5k_hw
*ah
)
549 u32 data
, filter
= 0;
551 ATH5K_TRACE(ah
->ah_sc
);
552 filter
= ath5k_hw_reg_read(ah
, AR5K_RX_FILTER
);
554 /*Radar detection for 5212*/
555 if (ah
->ah_version
== AR5K_AR5212
) {
556 data
= ath5k_hw_reg_read(ah
, AR5K_PHY_ERR_FIL
);
558 if (data
& AR5K_PHY_ERR_FIL_RADAR
)
559 filter
|= AR5K_RX_FILTER_RADARERR
;
560 if (data
& (AR5K_PHY_ERR_FIL_OFDM
| AR5K_PHY_ERR_FIL_CCK
))
561 filter
|= AR5K_RX_FILTER_PHYERR
;
568 * ath5k_hw_set_rx_filter - Set rx filter
570 * @ah: The &struct ath5k_hw
571 * @filter: RX filter mask (see reg.h)
573 * Sets RX filter register and also handles PHY error filter
574 * register on 5212 and newer chips so that we have proper PHY
577 void ath5k_hw_set_rx_filter(struct ath5k_hw
*ah
, u32 filter
)
581 ATH5K_TRACE(ah
->ah_sc
);
583 /* Set PHY error filter register on 5212*/
584 if (ah
->ah_version
== AR5K_AR5212
) {
585 if (filter
& AR5K_RX_FILTER_RADARERR
)
586 data
|= AR5K_PHY_ERR_FIL_RADAR
;
587 if (filter
& AR5K_RX_FILTER_PHYERR
)
588 data
|= AR5K_PHY_ERR_FIL_OFDM
| AR5K_PHY_ERR_FIL_CCK
;
592 * The AR5210 uses promiscous mode to detect radar activity
594 if (ah
->ah_version
== AR5K_AR5210
&&
595 (filter
& AR5K_RX_FILTER_RADARERR
)) {
596 filter
&= ~AR5K_RX_FILTER_RADARERR
;
597 filter
|= AR5K_RX_FILTER_PROM
;
600 /*Zero length DMA (phy error reporting) */
602 AR5K_REG_ENABLE_BITS(ah
, AR5K_RXCFG
, AR5K_RXCFG_ZLFDMA
);
604 AR5K_REG_DISABLE_BITS(ah
, AR5K_RXCFG
, AR5K_RXCFG_ZLFDMA
);
606 /*Write RX Filter register*/
607 ath5k_hw_reg_write(ah
, filter
& 0xff, AR5K_RX_FILTER
);
609 /*Write PHY error filter register on 5212*/
610 if (ah
->ah_version
== AR5K_AR5212
)
611 ath5k_hw_reg_write(ah
, data
, AR5K_PHY_ERR_FIL
);
621 * ath5k_hw_get_tsf32 - Get a 32bit TSF
623 * @ah: The &struct ath5k_hw
625 * Returns lower 32 bits of current TSF
627 u32
ath5k_hw_get_tsf32(struct ath5k_hw
*ah
)
629 ATH5K_TRACE(ah
->ah_sc
);
630 return ath5k_hw_reg_read(ah
, AR5K_TSF_L32
);
634 * ath5k_hw_get_tsf64 - Get the full 64bit TSF
636 * @ah: The &struct ath5k_hw
638 * Returns the current TSF
640 u64
ath5k_hw_get_tsf64(struct ath5k_hw
*ah
)
642 u64 tsf
= ath5k_hw_reg_read(ah
, AR5K_TSF_U32
);
643 ATH5K_TRACE(ah
->ah_sc
);
645 return ath5k_hw_reg_read(ah
, AR5K_TSF_L32
) | (tsf
<< 32);
649 * ath5k_hw_reset_tsf - Force a TSF reset
651 * @ah: The &struct ath5k_hw
653 * Forces a TSF reset on PCU
655 void ath5k_hw_reset_tsf(struct ath5k_hw
*ah
)
659 ATH5K_TRACE(ah
->ah_sc
);
661 val
= ath5k_hw_reg_read(ah
, AR5K_BEACON
) | AR5K_BEACON_RESET_TSF
;
664 * Each write to the RESET_TSF bit toggles a hardware internal
665 * signal to reset TSF, but if left high it will cause a TSF reset
666 * on the next chip reset as well. Thus we always write the value
667 * twice to clear the signal.
669 ath5k_hw_reg_write(ah
, val
, AR5K_BEACON
);
670 ath5k_hw_reg_write(ah
, val
, AR5K_BEACON
);
674 * Initialize beacon timers
676 void ath5k_hw_init_beacon(struct ath5k_hw
*ah
, u32 next_beacon
, u32 interval
)
678 u32 timer1
, timer2
, timer3
;
680 ATH5K_TRACE(ah
->ah_sc
);
682 * Set the additional timers by mode
684 switch (ah
->ah_op_mode
) {
685 case NL80211_IFTYPE_MONITOR
:
686 case NL80211_IFTYPE_STATION
:
687 /* In STA mode timer1 is used as next wakeup
688 * timer and timer2 as next CFP duration start
689 * timer. Both in 1/8TUs. */
690 /* TODO: PCF handling */
691 if (ah
->ah_version
== AR5K_AR5210
) {
698 /* Mark associated AP as PCF incapable for now */
699 AR5K_REG_DISABLE_BITS(ah
, AR5K_STA_ID1
, AR5K_STA_ID1_PCF
);
701 case NL80211_IFTYPE_ADHOC
:
702 AR5K_REG_ENABLE_BITS(ah
, AR5K_TXCFG
, AR5K_TXCFG_ADHOC_BCN_ATIM
);
704 /* On non-STA modes timer1 is used as next DMA
705 * beacon alert (DBA) timer and timer2 as next
706 * software beacon alert. Both in 1/8TUs. */
707 timer1
= (next_beacon
- AR5K_TUNE_DMA_BEACON_RESP
) << 3;
708 timer2
= (next_beacon
- AR5K_TUNE_SW_BEACON_RESP
) << 3;
712 /* Timer3 marks the end of our ATIM window
713 * a zero length window is not allowed because
714 * we 'll get no beacons */
715 timer3
= next_beacon
+ (ah
->ah_atim_window
? ah
->ah_atim_window
: 1);
718 * Set the beacon register and enable all timers.
720 /* When in AP mode zero timer0 to start TSF */
721 if (ah
->ah_op_mode
== NL80211_IFTYPE_AP
)
722 ath5k_hw_reg_write(ah
, 0, AR5K_TIMER0
);
724 ath5k_hw_reg_write(ah
, next_beacon
, AR5K_TIMER0
);
725 ath5k_hw_reg_write(ah
, timer1
, AR5K_TIMER1
);
726 ath5k_hw_reg_write(ah
, timer2
, AR5K_TIMER2
);
727 ath5k_hw_reg_write(ah
, timer3
, AR5K_TIMER3
);
729 /* Force a TSF reset if requested and enable beacons */
730 if (interval
& AR5K_BEACON_RESET_TSF
)
731 ath5k_hw_reset_tsf(ah
);
733 ath5k_hw_reg_write(ah
, interval
& (AR5K_BEACON_PERIOD
|
737 /* Flush any pending BMISS interrupts on ISR by
738 * performing a clear-on-write operation on PISR
739 * register for the BMISS bit (writing a bit on
740 * ISR togles a reset for that bit and leaves
741 * the rest bits intact) */
742 if (ah
->ah_version
== AR5K_AR5210
)
743 ath5k_hw_reg_write(ah
, AR5K_ISR_BMISS
, AR5K_ISR
);
745 ath5k_hw_reg_write(ah
, AR5K_ISR_BMISS
, AR5K_PISR
);
747 /* TODO: Set enchanced sleep registers on AR5212
748 * based on vif->bss_conf params, until then
749 * disable power save reporting.*/
750 AR5K_REG_DISABLE_BITS(ah
, AR5K_STA_ID1
, AR5K_STA_ID1_PWR_SV
);
758 int ath5k_hw_set_beacon_timers(struct ath5k_hw
*ah
,
759 const struct ath5k_beacon_state
*state
)
761 u32 cfp_period
, next_cfp
, dtim
, interval
, next_beacon
;
764 * TODO: should be changed through *state
765 * review struct ath5k_beacon_state struct
767 * XXX: These are used for cfp period bellow, are they
768 * ok ? Is it O.K. for tsf here to be 0 or should we use
771 u32 dtim_count
= 0; /* XXX */
772 u32 cfp_count
= 0; /* XXX */
773 u32 tsf
= 0; /* XXX */
775 ATH5K_TRACE(ah
->ah_sc
);
776 /* Return on an invalid beacon state */
777 if (state
->bs_interval
< 1)
780 interval
= state
->bs_interval
;
781 dtim
= state
->bs_dtim_period
;
786 if (state
->bs_cfp_period
> 0) {
788 * Enable PCF mode and set the CFP
789 * (Contention Free Period) and timer registers
791 cfp_period
= state
->bs_cfp_period
* state
->bs_dtim_period
*
793 next_cfp
= (cfp_count
* state
->bs_dtim_period
+ dtim_count
) *
796 AR5K_REG_ENABLE_BITS(ah
, AR5K_STA_ID1
,
797 AR5K_STA_ID1_DEFAULT_ANTENNA
|
799 ath5k_hw_reg_write(ah
, cfp_period
, AR5K_CFP_PERIOD
);
800 ath5k_hw_reg_write(ah
, state
->bs_cfp_max_duration
,
802 ath5k_hw_reg_write(ah
, (tsf
+ (next_cfp
== 0 ? cfp_period
:
803 next_cfp
)) << 3, AR5K_TIMER2
);
805 /* Disable PCF mode */
806 AR5K_REG_DISABLE_BITS(ah
, AR5K_STA_ID1
,
807 AR5K_STA_ID1_DEFAULT_ANTENNA
|
812 * Enable the beacon timer register
814 ath5k_hw_reg_write(ah
, state
->bs_next_beacon
, AR5K_TIMER0
);
817 * Start the beacon timers
819 ath5k_hw_reg_write(ah
, (ath5k_hw_reg_read(ah
, AR5K_BEACON
) &
820 ~(AR5K_BEACON_PERIOD
| AR5K_BEACON_TIM
)) |
821 AR5K_REG_SM(state
->bs_tim_offset
? state
->bs_tim_offset
+ 4 : 0,
822 AR5K_BEACON_TIM
) | AR5K_REG_SM(state
->bs_interval
,
823 AR5K_BEACON_PERIOD
), AR5K_BEACON
);
826 * Write new beacon miss threshold, if it appears to be valid
827 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
828 * and return if its not in range. We can test this by reading value and
829 * setting value to a largest value and seeing which values register.
832 AR5K_REG_WRITE_BITS(ah
, AR5K_RSSI_THR
, AR5K_RSSI_THR_BMISS
,
833 state
->bs_bmiss_threshold
);
836 * Set sleep control register
837 * XXX: Didn't find this in 5210 code but since this register
838 * exists also in ar5k's 5210 headers i leave it as common code.
840 AR5K_REG_WRITE_BITS(ah
, AR5K_SLEEP_CTL
, AR5K_SLEEP_CTL_SLDUR
,
841 (state
->bs_sleep_duration
- 3) << 3);
844 * Set enhanced sleep registers on 5212
846 if (ah
->ah_version
== AR5K_AR5212
) {
847 if (state
->bs_sleep_duration
> state
->bs_interval
&&
848 roundup(state
->bs_sleep_duration
, interval
) ==
849 state
->bs_sleep_duration
)
850 interval
= state
->bs_sleep_duration
;
852 if (state
->bs_sleep_duration
> dtim
&& (dtim
== 0 ||
853 roundup(state
->bs_sleep_duration
, dtim
) ==
854 state
->bs_sleep_duration
))
855 dtim
= state
->bs_sleep_duration
;
860 next_beacon
= interval
== dtim
? state
->bs_next_dtim
:
861 state
->bs_next_beacon
;
863 ath5k_hw_reg_write(ah
,
864 AR5K_REG_SM((state
->bs_next_dtim
- 3) << 3,
865 AR5K_SLEEP0_NEXT_DTIM
) |
866 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO
) |
867 AR5K_SLEEP0_ENH_SLEEP_EN
|
868 AR5K_SLEEP0_ASSUME_DTIM
, AR5K_SLEEP0
);
870 ath5k_hw_reg_write(ah
, AR5K_REG_SM((next_beacon
- 3) << 3,
871 AR5K_SLEEP1_NEXT_TIM
) |
872 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO
), AR5K_SLEEP1
);
874 ath5k_hw_reg_write(ah
,
875 AR5K_REG_SM(interval
, AR5K_SLEEP2_TIM_PER
) |
876 AR5K_REG_SM(dtim
, AR5K_SLEEP2_DTIM_PER
), AR5K_SLEEP2
);
883 * Reset beacon timers
885 void ath5k_hw_reset_beacon(struct ath5k_hw
*ah
)
887 ATH5K_TRACE(ah
->ah_sc
);
889 * Disable beacon timer
891 ath5k_hw_reg_write(ah
, 0, AR5K_TIMER0
);
894 * Disable some beacon register values
896 AR5K_REG_DISABLE_BITS(ah
, AR5K_STA_ID1
,
897 AR5K_STA_ID1_DEFAULT_ANTENNA
| AR5K_STA_ID1_PCF
);
898 ath5k_hw_reg_write(ah
, AR5K_BEACON_PERIOD
, AR5K_BEACON
);
902 * Wait for beacon queue to finish
904 int ath5k_hw_beaconq_finish(struct ath5k_hw
*ah
, unsigned long phys_addr
)
909 ATH5K_TRACE(ah
->ah_sc
);
911 /* 5210 doesn't have QCU*/
912 if (ah
->ah_version
== AR5K_AR5210
) {
914 * Wait for beaconn queue to finish by checking
915 * Control Register and Beacon Status Register.
917 for (i
= AR5K_TUNE_BEACON_INTERVAL
/ 2; i
> 0; i
--) {
918 if (!(ath5k_hw_reg_read(ah
, AR5K_BSR
) & AR5K_BSR_TXQ1F
)
920 !(ath5k_hw_reg_read(ah
, AR5K_CR
) & AR5K_BSR_TXQ1F
))
928 * Re-schedule the beacon queue
930 ath5k_hw_reg_write(ah
, phys_addr
, AR5K_NOQCU_TXDP1
);
931 ath5k_hw_reg_write(ah
, AR5K_BCR_TQ1V
| AR5K_BCR_BDMAE
,
939 ret
= ath5k_hw_register_timeout(ah
,
940 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON
),
941 AR5K_QCU_STS_FRMPENDCNT
, 0, false);
943 if (AR5K_REG_READ_Q(ah
, AR5K_QCU_TXE
, AR5K_TX_QUEUE_ID_BEACON
))
952 /*********************\
953 * Key table functions *
954 \*********************/
957 * Reset a key entry on the table
959 int ath5k_hw_reset_key(struct ath5k_hw
*ah
, u16 entry
)
961 unsigned int i
, type
;
962 u16 micentry
= entry
+ AR5K_KEYTABLE_MIC_OFFSET
;
964 ATH5K_TRACE(ah
->ah_sc
);
965 AR5K_ASSERT_ENTRY(entry
, AR5K_KEYTABLE_SIZE
);
967 type
= ath5k_hw_reg_read(ah
, AR5K_KEYTABLE_TYPE(entry
));
969 for (i
= 0; i
< AR5K_KEYCACHE_SIZE
; i
++)
970 ath5k_hw_reg_write(ah
, 0, AR5K_KEYTABLE_OFF(entry
, i
));
972 /* Reset associated MIC entry if TKIP
973 * is enabled located at offset (entry + 64) */
974 if (type
== AR5K_KEYTABLE_TYPE_TKIP
) {
975 AR5K_ASSERT_ENTRY(micentry
, AR5K_KEYTABLE_SIZE
);
976 for (i
= 0; i
< AR5K_KEYCACHE_SIZE
/ 2 ; i
++)
977 ath5k_hw_reg_write(ah
, 0,
978 AR5K_KEYTABLE_OFF(micentry
, i
));
982 * Set NULL encryption on AR5212+
984 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
985 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
987 * Note2: Windows driver (ndiswrapper) sets this to
988 * 0x00000714 instead of 0x00000007
990 if (ah
->ah_version
> AR5K_AR5211
) {
991 ath5k_hw_reg_write(ah
, AR5K_KEYTABLE_TYPE_NULL
,
992 AR5K_KEYTABLE_TYPE(entry
));
994 if (type
== AR5K_KEYTABLE_TYPE_TKIP
) {
995 ath5k_hw_reg_write(ah
, AR5K_KEYTABLE_TYPE_NULL
,
996 AR5K_KEYTABLE_TYPE(micentry
));
1004 * Check if a table entry is valid
1006 int ath5k_hw_is_key_valid(struct ath5k_hw
*ah
, u16 entry
)
1008 ATH5K_TRACE(ah
->ah_sc
);
1009 AR5K_ASSERT_ENTRY(entry
, AR5K_KEYTABLE_SIZE
);
1011 /* Check the validation flag at the end of the entry */
1012 return ath5k_hw_reg_read(ah
, AR5K_KEYTABLE_MAC1(entry
)) &
1013 AR5K_KEYTABLE_VALID
;
1017 int ath5k_keycache_type(const struct ieee80211_key_conf
*key
)
1021 return AR5K_KEYTABLE_TYPE_TKIP
;
1023 return AR5K_KEYTABLE_TYPE_CCM
;
1025 if (key
->keylen
== LEN_WEP40
)
1026 return AR5K_KEYTABLE_TYPE_40
;
1027 else if (key
->keylen
== LEN_WEP104
)
1028 return AR5K_KEYTABLE_TYPE_104
;
1034 * Set a key entry on the table
1036 int ath5k_hw_set_key(struct ath5k_hw
*ah
, u16 entry
,
1037 const struct ieee80211_key_conf
*key
, const u8
*mac
)
1041 __le32 key_v
[5] = {};
1042 __le32 key0
= 0, key1
= 0;
1043 __le32
*rxmic
, *txmic
;
1045 u16 micentry
= entry
+ AR5K_KEYTABLE_MIC_OFFSET
;
1049 ATH5K_TRACE(ah
->ah_sc
);
1051 is_tkip
= (key
->alg
== ALG_TKIP
);
1054 * key->keylen comes in from mac80211 in bytes.
1055 * TKIP is 128 bit + 128 bit mic
1057 keylen
= (is_tkip
) ? (128 / 8) : key
->keylen
;
1059 if (entry
> AR5K_KEYTABLE_SIZE
||
1060 (is_tkip
&& micentry
> AR5K_KEYTABLE_SIZE
))
1063 if (unlikely(keylen
> 16))
1066 keytype
= ath5k_keycache_type(key
);
1071 * each key block is 6 bytes wide, written as pairs of
1072 * alternating 32 and 16 bit le values.
1075 for (i
= 0; keylen
>= 6; keylen
-= 6) {
1076 memcpy(&key_v
[i
], key_ptr
, 6);
1081 memcpy(&key_v
[i
], key_ptr
, keylen
);
1083 /* intentionally corrupt key until mic is installed */
1085 key0
= key_v
[0] = ~key_v
[0];
1086 key1
= key_v
[1] = ~key_v
[1];
1089 for (i
= 0; i
< ARRAY_SIZE(key_v
); i
++)
1090 ath5k_hw_reg_write(ah
, le32_to_cpu(key_v
[i
]),
1091 AR5K_KEYTABLE_OFF(entry
, i
));
1093 ath5k_hw_reg_write(ah
, keytype
, AR5K_KEYTABLE_TYPE(entry
));
1096 /* Install rx/tx MIC */
1097 rxmic
= (__le32
*) &key
->key
[16];
1098 txmic
= (__le32
*) &key
->key
[24];
1100 if (ah
->ah_combined_mic
) {
1101 key_v
[0] = rxmic
[0];
1102 key_v
[1] = cpu_to_le32(le32_to_cpu(txmic
[0]) >> 16);
1103 key_v
[2] = rxmic
[1];
1104 key_v
[3] = cpu_to_le32(le32_to_cpu(txmic
[0]) & 0xffff);
1105 key_v
[4] = txmic
[1];
1107 key_v
[0] = rxmic
[0];
1109 key_v
[2] = rxmic
[1];
1113 for (i
= 0; i
< ARRAY_SIZE(key_v
); i
++)
1114 ath5k_hw_reg_write(ah
, le32_to_cpu(key_v
[i
]),
1115 AR5K_KEYTABLE_OFF(micentry
, i
));
1117 ath5k_hw_reg_write(ah
, AR5K_KEYTABLE_TYPE_NULL
,
1118 AR5K_KEYTABLE_TYPE(micentry
));
1119 ath5k_hw_reg_write(ah
, 0, AR5K_KEYTABLE_MAC0(micentry
));
1120 ath5k_hw_reg_write(ah
, 0, AR5K_KEYTABLE_MAC1(micentry
));
1122 /* restore first 2 words of key */
1123 ath5k_hw_reg_write(ah
, le32_to_cpu(~key0
),
1124 AR5K_KEYTABLE_OFF(entry
, 0));
1125 ath5k_hw_reg_write(ah
, le32_to_cpu(~key1
),
1126 AR5K_KEYTABLE_OFF(entry
, 1));
1129 return ath5k_hw_set_key_lladdr(ah
, entry
, mac
);
1132 int ath5k_hw_set_key_lladdr(struct ath5k_hw
*ah
, u16 entry
, const u8
*mac
)
1134 u32 low_id
, high_id
;
1136 ATH5K_TRACE(ah
->ah_sc
);
1137 /* Invalid entry (key table overflow) */
1138 AR5K_ASSERT_ENTRY(entry
, AR5K_KEYTABLE_SIZE
);
1140 /* MAC may be NULL if it's a broadcast key. In this case no need to
1141 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
1143 low_id
= 0xffffffff;
1144 high_id
= 0xffff | AR5K_KEYTABLE_VALID
;
1146 low_id
= AR5K_LOW_ID(mac
);
1147 high_id
= AR5K_HIGH_ID(mac
) | AR5K_KEYTABLE_VALID
;
1150 ath5k_hw_reg_write(ah
, low_id
, AR5K_KEYTABLE_MAC0(entry
));
1151 ath5k_hw_reg_write(ah
, high_id
, AR5K_KEYTABLE_MAC1(entry
));