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[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath9k / ath9k.h
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef ATH9K_H
18 #define ATH9K_H
19
20 #include <linux/io.h>
21
22 #define ATHEROS_VENDOR_ID 0x168c
23
24 #define AR5416_DEVID_PCI 0x0023
25 #define AR5416_DEVID_PCIE 0x0024
26 #define AR9160_DEVID_PCI 0x0027
27 #define AR9280_DEVID_PCI 0x0029
28 #define AR9280_DEVID_PCIE 0x002a
29
30 #define AR5416_AR9100_DEVID 0x000b
31
32 #define AR_SUBVENDOR_ID_NOG 0x0e11
33 #define AR_SUBVENDOR_ID_NEW_A 0x7065
34
35 #define ATH9K_TXERR_XRETRY 0x01
36 #define ATH9K_TXERR_FILT 0x02
37 #define ATH9K_TXERR_FIFO 0x04
38 #define ATH9K_TXERR_XTXOP 0x08
39 #define ATH9K_TXERR_TIMER_EXPIRED 0x10
40
41 #define ATH9K_TX_BA 0x01
42 #define ATH9K_TX_PWRMGMT 0x02
43 #define ATH9K_TX_DESC_CFG_ERR 0x04
44 #define ATH9K_TX_DATA_UNDERRUN 0x08
45 #define ATH9K_TX_DELIM_UNDERRUN 0x10
46 #define ATH9K_TX_SW_ABORTED 0x40
47 #define ATH9K_TX_SW_FILTERED 0x80
48
49 #define NBBY 8
50
51 struct ath_tx_status {
52 u32 ts_tstamp;
53 u16 ts_seqnum;
54 u8 ts_status;
55 u8 ts_ratecode;
56 u8 ts_rateindex;
57 int8_t ts_rssi;
58 u8 ts_shortretry;
59 u8 ts_longretry;
60 u8 ts_virtcol;
61 u8 ts_antenna;
62 u8 ts_flags;
63 int8_t ts_rssi_ctl0;
64 int8_t ts_rssi_ctl1;
65 int8_t ts_rssi_ctl2;
66 int8_t ts_rssi_ext0;
67 int8_t ts_rssi_ext1;
68 int8_t ts_rssi_ext2;
69 u8 pad[3];
70 u32 ba_low;
71 u32 ba_high;
72 u32 evm0;
73 u32 evm1;
74 u32 evm2;
75 };
76
77 struct ath_rx_status {
78 u32 rs_tstamp;
79 u16 rs_datalen;
80 u8 rs_status;
81 u8 rs_phyerr;
82 int8_t rs_rssi;
83 u8 rs_keyix;
84 u8 rs_rate;
85 u8 rs_antenna;
86 u8 rs_more;
87 int8_t rs_rssi_ctl0;
88 int8_t rs_rssi_ctl1;
89 int8_t rs_rssi_ctl2;
90 int8_t rs_rssi_ext0;
91 int8_t rs_rssi_ext1;
92 int8_t rs_rssi_ext2;
93 u8 rs_isaggr;
94 u8 rs_moreaggr;
95 u8 rs_num_delims;
96 u8 rs_flags;
97 u32 evm0;
98 u32 evm1;
99 u32 evm2;
100 };
101
102 #define ATH9K_RXERR_CRC 0x01
103 #define ATH9K_RXERR_PHY 0x02
104 #define ATH9K_RXERR_FIFO 0x04
105 #define ATH9K_RXERR_DECRYPT 0x08
106 #define ATH9K_RXERR_MIC 0x10
107
108 #define ATH9K_RX_MORE 0x01
109 #define ATH9K_RX_MORE_AGGR 0x02
110 #define ATH9K_RX_GI 0x04
111 #define ATH9K_RX_2040 0x08
112 #define ATH9K_RX_DELIM_CRC_PRE 0x10
113 #define ATH9K_RX_DELIM_CRC_POST 0x20
114 #define ATH9K_RX_DECRYPT_BUSY 0x40
115
116 #define ATH9K_RXKEYIX_INVALID ((u8)-1)
117 #define ATH9K_TXKEYIX_INVALID ((u32)-1)
118
119 struct ath_desc {
120 u32 ds_link;
121 u32 ds_data;
122 u32 ds_ctl0;
123 u32 ds_ctl1;
124 u32 ds_hw[20];
125 union {
126 struct ath_tx_status tx;
127 struct ath_rx_status rx;
128 void *stats;
129 } ds_us;
130 void *ds_vdata;
131 } __packed;
132
133 #define ds_txstat ds_us.tx
134 #define ds_rxstat ds_us.rx
135 #define ds_stat ds_us.stats
136
137 #define ATH9K_TXDESC_CLRDMASK 0x0001
138 #define ATH9K_TXDESC_NOACK 0x0002
139 #define ATH9K_TXDESC_RTSENA 0x0004
140 #define ATH9K_TXDESC_CTSENA 0x0008
141 #define ATH9K_TXDESC_INTREQ 0x0010
142 #define ATH9K_TXDESC_VEOL 0x0020
143 #define ATH9K_TXDESC_EXT_ONLY 0x0040
144 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080
145 #define ATH9K_TXDESC_VMF 0x0100
146 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200
147 #define ATH9K_TXDESC_CAB 0x0400
148
149 #define ATH9K_RXDESC_INTREQ 0x0020
150
151 enum wireless_mode {
152 ATH9K_MODE_11A = 0,
153 ATH9K_MODE_11B = 2,
154 ATH9K_MODE_11G = 3,
155 ATH9K_MODE_11NA_HT20 = 6,
156 ATH9K_MODE_11NG_HT20 = 7,
157 ATH9K_MODE_11NA_HT40PLUS = 8,
158 ATH9K_MODE_11NA_HT40MINUS = 9,
159 ATH9K_MODE_11NG_HT40PLUS = 10,
160 ATH9K_MODE_11NG_HT40MINUS = 11,
161 ATH9K_MODE_MAX
162 };
163
164 enum ath9k_hw_caps {
165 ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
166 ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
167 ATH9K_HW_CAP_MIC_CKIP = BIT(2),
168 ATH9K_HW_CAP_MIC_TKIP = BIT(3),
169 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
170 ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
171 ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
172 ATH9K_HW_CAP_VEOL = BIT(7),
173 ATH9K_HW_CAP_BSSIDMASK = BIT(8),
174 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),
175 ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),
176 ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),
177 ATH9K_HW_CAP_HT = BIT(12),
178 ATH9K_HW_CAP_GTT = BIT(13),
179 ATH9K_HW_CAP_FASTCC = BIT(14),
180 ATH9K_HW_CAP_RFSILENT = BIT(15),
181 ATH9K_HW_CAP_WOW = BIT(16),
182 ATH9K_HW_CAP_CST = BIT(17),
183 ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
184 ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
185 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
186 ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
187 };
188
189 enum ath9k_capability_type {
190 ATH9K_CAP_CIPHER = 0,
191 ATH9K_CAP_TKIP_MIC,
192 ATH9K_CAP_TKIP_SPLIT,
193 ATH9K_CAP_PHYCOUNTERS,
194 ATH9K_CAP_DIVERSITY,
195 ATH9K_CAP_TXPOW,
196 ATH9K_CAP_PHYDIAG,
197 ATH9K_CAP_MCAST_KEYSRCH,
198 ATH9K_CAP_TSF_ADJUST,
199 ATH9K_CAP_WME_TKIPMIC,
200 ATH9K_CAP_RFSILENT,
201 ATH9K_CAP_ANT_CFG_2GHZ,
202 ATH9K_CAP_ANT_CFG_5GHZ
203 };
204
205 struct ath9k_hw_capabilities {
206 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
207 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
208 u16 total_queues;
209 u16 keycache_size;
210 u16 low_5ghz_chan, high_5ghz_chan;
211 u16 low_2ghz_chan, high_2ghz_chan;
212 u16 num_mr_retries;
213 u16 rts_aggr_limit;
214 u8 tx_chainmask;
215 u8 rx_chainmask;
216 u16 tx_triglevel_max;
217 u16 reg_cap;
218 u8 num_gpio_pins;
219 u8 num_antcfg_2ghz;
220 u8 num_antcfg_5ghz;
221 };
222
223 struct ath9k_ops_config {
224 int dma_beacon_response_time;
225 int sw_beacon_response_time;
226 int additional_swba_backoff;
227 int ack_6mb;
228 int cwm_ignore_extcca;
229 u8 pcie_powersave_enable;
230 u8 pcie_l1skp_enable;
231 u8 pcie_clock_req;
232 u32 pcie_waen;
233 int pcie_power_reset;
234 u8 pcie_restore;
235 u8 analog_shiftreg;
236 u8 ht_enable;
237 u32 ofdm_trig_low;
238 u32 ofdm_trig_high;
239 u32 cck_trig_high;
240 u32 cck_trig_low;
241 u32 enable_ani;
242 u8 noise_immunity_level;
243 u32 ofdm_weaksignal_det;
244 u32 cck_weaksignal_thr;
245 u8 spur_immunity_level;
246 u8 firstep_level;
247 int8_t rssi_thr_high;
248 int8_t rssi_thr_low;
249 u16 diversity_control;
250 u16 antenna_switch_swap;
251 int serialize_regmode;
252 int intr_mitigation;
253 #define SPUR_DISABLE 0
254 #define SPUR_ENABLE_IOCTL 1
255 #define SPUR_ENABLE_EEPROM 2
256 #define AR_EEPROM_MODAL_SPURS 5
257 #define AR_SPUR_5413_1 1640
258 #define AR_SPUR_5413_2 1200
259 #define AR_NO_SPUR 0x8000
260 #define AR_BASE_FREQ_2GHZ 2300
261 #define AR_BASE_FREQ_5GHZ 4900
262 #define AR_SPUR_FEEQ_BOUND_HT40 19
263 #define AR_SPUR_FEEQ_BOUND_HT20 10
264 int spurmode;
265 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
266 };
267
268 enum ath9k_tx_queue {
269 ATH9K_TX_QUEUE_INACTIVE = 0,
270 ATH9K_TX_QUEUE_DATA,
271 ATH9K_TX_QUEUE_BEACON,
272 ATH9K_TX_QUEUE_CAB,
273 ATH9K_TX_QUEUE_UAPSD,
274 ATH9K_TX_QUEUE_PSPOLL
275 };
276
277 #define ATH9K_NUM_TX_QUEUES 10
278
279 enum ath9k_tx_queue_subtype {
280 ATH9K_WME_AC_BK = 0,
281 ATH9K_WME_AC_BE,
282 ATH9K_WME_AC_VI,
283 ATH9K_WME_AC_VO,
284 ATH9K_WME_UPSD
285 };
286
287 enum ath9k_tx_queue_flags {
288 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
289 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
290 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
291 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
292 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
293 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
294 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
295 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
296 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
297 };
298
299 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
300
301 #define ATH9K_DECOMP_MASK_SIZE 128
302 #define ATH9K_READY_TIME_LO_BOUND 50
303 #define ATH9K_READY_TIME_HI_BOUND 96
304
305 enum ath9k_pkt_type {
306 ATH9K_PKT_TYPE_NORMAL = 0,
307 ATH9K_PKT_TYPE_ATIM,
308 ATH9K_PKT_TYPE_PSPOLL,
309 ATH9K_PKT_TYPE_BEACON,
310 ATH9K_PKT_TYPE_PROBE_RESP,
311 ATH9K_PKT_TYPE_CHIRP,
312 ATH9K_PKT_TYPE_GRP_POLL,
313 };
314
315 struct ath9k_tx_queue_info {
316 u32 tqi_ver;
317 enum ath9k_tx_queue tqi_type;
318 enum ath9k_tx_queue_subtype tqi_subtype;
319 enum ath9k_tx_queue_flags tqi_qflags;
320 u32 tqi_priority;
321 u32 tqi_aifs;
322 u32 tqi_cwmin;
323 u32 tqi_cwmax;
324 u16 tqi_shretry;
325 u16 tqi_lgretry;
326 u32 tqi_cbrPeriod;
327 u32 tqi_cbrOverflowLimit;
328 u32 tqi_burstTime;
329 u32 tqi_readyTime;
330 u32 tqi_physCompBuf;
331 u32 tqi_intFlags;
332 };
333
334 enum ath9k_rx_filter {
335 ATH9K_RX_FILTER_UCAST = 0x00000001,
336 ATH9K_RX_FILTER_MCAST = 0x00000002,
337 ATH9K_RX_FILTER_BCAST = 0x00000004,
338 ATH9K_RX_FILTER_CONTROL = 0x00000008,
339 ATH9K_RX_FILTER_BEACON = 0x00000010,
340 ATH9K_RX_FILTER_PROM = 0x00000020,
341 ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
342 ATH9K_RX_FILTER_PSPOLL = 0x00004000,
343 ATH9K_RX_FILTER_PHYERR = 0x00000100,
344 ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
345 };
346
347 enum ath9k_int {
348 ATH9K_INT_RX = 0x00000001,
349 ATH9K_INT_RXDESC = 0x00000002,
350 ATH9K_INT_RXNOFRM = 0x00000008,
351 ATH9K_INT_RXEOL = 0x00000010,
352 ATH9K_INT_RXORN = 0x00000020,
353 ATH9K_INT_TX = 0x00000040,
354 ATH9K_INT_TXDESC = 0x00000080,
355 ATH9K_INT_TIM_TIMER = 0x00000100,
356 ATH9K_INT_TXURN = 0x00000800,
357 ATH9K_INT_MIB = 0x00001000,
358 ATH9K_INT_RXPHY = 0x00004000,
359 ATH9K_INT_RXKCM = 0x00008000,
360 ATH9K_INT_SWBA = 0x00010000,
361 ATH9K_INT_BMISS = 0x00040000,
362 ATH9K_INT_BNR = 0x00100000,
363 ATH9K_INT_TIM = 0x00200000,
364 ATH9K_INT_DTIM = 0x00400000,
365 ATH9K_INT_DTIMSYNC = 0x00800000,
366 ATH9K_INT_GPIO = 0x01000000,
367 ATH9K_INT_CABEND = 0x02000000,
368 ATH9K_INT_CST = 0x10000000,
369 ATH9K_INT_GTT = 0x20000000,
370 ATH9K_INT_FATAL = 0x40000000,
371 ATH9K_INT_GLOBAL = 0x80000000,
372 ATH9K_INT_BMISC = ATH9K_INT_TIM |
373 ATH9K_INT_DTIM |
374 ATH9K_INT_DTIMSYNC |
375 ATH9K_INT_CABEND,
376 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
377 ATH9K_INT_RXDESC |
378 ATH9K_INT_RXEOL |
379 ATH9K_INT_RXORN |
380 ATH9K_INT_TXURN |
381 ATH9K_INT_TXDESC |
382 ATH9K_INT_MIB |
383 ATH9K_INT_RXPHY |
384 ATH9K_INT_RXKCM |
385 ATH9K_INT_SWBA |
386 ATH9K_INT_BMISS |
387 ATH9K_INT_GPIO,
388 ATH9K_INT_NOCARD = 0xffffffff
389 };
390
391 struct ath9k_rate_table {
392 int rateCount;
393 u8 rateCodeToIndex[256];
394 struct {
395 u8 valid;
396 u8 phy;
397 u32 rateKbps;
398 u8 rateCode;
399 u8 shortPreamble;
400 u8 dot11Rate;
401 u8 controlRate;
402 u16 lpAckDuration;
403 u16 spAckDuration;
404 } info[32];
405 };
406
407 #define ATH9K_RATESERIES_RTS_CTS 0x0001
408 #define ATH9K_RATESERIES_2040 0x0002
409 #define ATH9K_RATESERIES_HALFGI 0x0004
410
411 struct ath9k_11n_rate_series {
412 u32 Tries;
413 u32 Rate;
414 u32 PktDuration;
415 u32 ChSel;
416 u32 RateFlags;
417 };
418
419 #define CHANNEL_CW_INT 0x00002
420 #define CHANNEL_CCK 0x00020
421 #define CHANNEL_OFDM 0x00040
422 #define CHANNEL_2GHZ 0x00080
423 #define CHANNEL_5GHZ 0x00100
424 #define CHANNEL_PASSIVE 0x00200
425 #define CHANNEL_DYN 0x00400
426 #define CHANNEL_HALF 0x04000
427 #define CHANNEL_QUARTER 0x08000
428 #define CHANNEL_HT20 0x10000
429 #define CHANNEL_HT40PLUS 0x20000
430 #define CHANNEL_HT40MINUS 0x40000
431
432 #define CHANNEL_INTERFERENCE 0x01
433 #define CHANNEL_DFS 0x02
434 #define CHANNEL_4MS_LIMIT 0x04
435 #define CHANNEL_DFS_CLEAR 0x08
436 #define CHANNEL_DISALLOW_ADHOC 0x10
437 #define CHANNEL_PER_11D_ADHOC 0x20
438
439 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
440 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
441 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
442 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
443 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
444 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
445 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
446 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
447 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
448 #define CHANNEL_ALL \
449 (CHANNEL_OFDM| \
450 CHANNEL_CCK| \
451 CHANNEL_2GHZ | \
452 CHANNEL_5GHZ | \
453 CHANNEL_HT20 | \
454 CHANNEL_HT40PLUS | \
455 CHANNEL_HT40MINUS)
456
457 struct ath9k_channel {
458 u16 channel;
459 u32 channelFlags;
460 u8 privFlags;
461 int8_t maxRegTxPower;
462 int8_t maxTxPower;
463 int8_t minTxPower;
464 u32 chanmode;
465 int32_t CalValid;
466 bool oneTimeCalsDone;
467 int8_t iCoff;
468 int8_t qCoff;
469 int16_t rawNoiseFloor;
470 int8_t antennaMax;
471 u32 regDmnFlags;
472 u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */
473 #ifdef ATH_NF_PER_CHAN
474 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
475 #endif
476 };
477
478 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
479 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
480 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
481 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
482 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
483 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
484 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
485 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
486 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
487 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
488 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
489 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
490 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
491 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
492 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
493 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
494
495 /* These macros check chanmode and not channelFlags */
496 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
497 ((_c)->chanmode == CHANNEL_G_HT20))
498 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
499 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
500 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
501 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
502 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
503
504 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
505 #define IS_CHAN_A_5MHZ_SPACED(_c) \
506 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
507 (((_c)->channel % 20) != 0) && \
508 (((_c)->channel % 10) != 0))
509
510 struct ath9k_keyval {
511 u8 kv_type;
512 u8 kv_pad;
513 u16 kv_len;
514 u8 kv_val[16];
515 u8 kv_mic[8];
516 u8 kv_txmic[8];
517 };
518
519 enum ath9k_key_type {
520 ATH9K_KEY_TYPE_CLEAR,
521 ATH9K_KEY_TYPE_WEP,
522 ATH9K_KEY_TYPE_AES,
523 ATH9K_KEY_TYPE_TKIP,
524 };
525
526 enum ath9k_cipher {
527 ATH9K_CIPHER_WEP = 0,
528 ATH9K_CIPHER_AES_OCB = 1,
529 ATH9K_CIPHER_AES_CCM = 2,
530 ATH9K_CIPHER_CKIP = 3,
531 ATH9K_CIPHER_TKIP = 4,
532 ATH9K_CIPHER_CLR = 5,
533 ATH9K_CIPHER_MIC = 127
534 };
535
536 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
537 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
538 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
539 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
540 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
541 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
542 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
543 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
544 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
545
546 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
547 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
548 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
549 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
550 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
551 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
552
553 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
554 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
555
556 #define SD_NO_CTL 0xE0
557 #define NO_CTL 0xff
558 #define CTL_MODE_M 7
559 #define CTL_11A 0
560 #define CTL_11B 1
561 #define CTL_11G 2
562 #define CTL_2GHT20 5
563 #define CTL_5GHT20 6
564 #define CTL_2GHT40 7
565 #define CTL_5GHT40 8
566
567 #define AR_EEPROM_MAC(i) (0x1d+(i))
568
569 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
570 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
571 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
572 #define AR_EEPROM_RFSILENT_POLARITY_S 1
573
574 #define CTRY_DEBUG 0x1ff
575 #define CTRY_DEFAULT 0
576
577 enum reg_ext_bitmap {
578 REG_EXT_JAPAN_MIDBAND = 1,
579 REG_EXT_FCC_DFS_HT40 = 2,
580 REG_EXT_JAPAN_NONDFS_HT40 = 3,
581 REG_EXT_JAPAN_DFS_HT40 = 4
582 };
583
584 struct ath9k_country_entry {
585 u16 countryCode;
586 u16 regDmnEnum;
587 u16 regDmn5G;
588 u16 regDmn2G;
589 u8 isMultidomain;
590 u8 iso[3];
591 };
592
593 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
594 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
595
596 #define SM(_v, _f) (((_v) << _f##_S) & _f)
597 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
598 #define REG_RMW(_a, _r, _set, _clr) \
599 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
600 #define REG_RMW_FIELD(_a, _r, _f, _v) \
601 REG_WRITE(_a, _r, \
602 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
603 #define REG_SET_BIT(_a, _r, _f) \
604 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
605 #define REG_CLR_BIT(_a, _r, _f) \
606 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
607
608 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
609
610 #define INIT_AIFS 2
611 #define INIT_CWMIN 15
612 #define INIT_CWMIN_11B 31
613 #define INIT_CWMAX 1023
614 #define INIT_SH_RETRY 10
615 #define INIT_LG_RETRY 10
616 #define INIT_SSH_RETRY 32
617 #define INIT_SLG_RETRY 32
618
619 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
620
621 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
622 #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
623
624 #define IEEE80211_WEP_IVLEN 3
625 #define IEEE80211_WEP_KIDLEN 1
626 #define IEEE80211_WEP_CRCLEN 4
627 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
628 (IEEE80211_WEP_IVLEN + \
629 IEEE80211_WEP_KIDLEN + \
630 IEEE80211_WEP_CRCLEN))
631 #define MAX_RATE_POWER 63
632
633 enum ath9k_power_mode {
634 ATH9K_PM_AWAKE = 0,
635 ATH9K_PM_FULL_SLEEP,
636 ATH9K_PM_NETWORK_SLEEP,
637 ATH9K_PM_UNDEFINED
638 };
639
640 struct ath9k_mib_stats {
641 u32 ackrcv_bad;
642 u32 rts_bad;
643 u32 rts_good;
644 u32 fcs_bad;
645 u32 beacons;
646 };
647
648 enum ath9k_ant_setting {
649 ATH9K_ANT_VARIABLE = 0,
650 ATH9K_ANT_FIXED_A,
651 ATH9K_ANT_FIXED_B
652 };
653
654 enum ath9k_opmode {
655 ATH9K_M_STA = 1,
656 ATH9K_M_IBSS = 0,
657 ATH9K_M_HOSTAP = 6,
658 ATH9K_M_MONITOR = 8
659 };
660
661 #define ATH9K_SLOT_TIME_6 6
662 #define ATH9K_SLOT_TIME_9 9
663 #define ATH9K_SLOT_TIME_20 20
664
665 enum ath9k_ht_macmode {
666 ATH9K_HT_MACMODE_20 = 0,
667 ATH9K_HT_MACMODE_2040 = 1,
668 };
669
670 enum ath9k_ht_extprotspacing {
671 ATH9K_HT_EXTPROTSPACING_20 = 0,
672 ATH9K_HT_EXTPROTSPACING_25 = 1,
673 };
674
675 struct ath9k_ht_cwm {
676 enum ath9k_ht_macmode ht_macmode;
677 enum ath9k_ht_extprotspacing ht_extprotspacing;
678 };
679
680 enum ath9k_ani_cmd {
681 ATH9K_ANI_PRESENT = 0x1,
682 ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
683 ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
684 ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
685 ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
686 ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
687 ATH9K_ANI_MODE = 0x40,
688 ATH9K_ANI_PHYERR_RESET = 0x80,
689 ATH9K_ANI_ALL = 0xff
690 };
691
692 enum phytype {
693 PHY_DS,
694 PHY_FH,
695 PHY_OFDM,
696 PHY_HT,
697 };
698 #define PHY_CCK PHY_DS
699
700 enum ath9k_tp_scale {
701 ATH9K_TP_SCALE_MAX = 0,
702 ATH9K_TP_SCALE_50,
703 ATH9K_TP_SCALE_25,
704 ATH9K_TP_SCALE_12,
705 ATH9K_TP_SCALE_MIN
706 };
707
708 enum ser_reg_mode {
709 SER_REG_MODE_OFF = 0,
710 SER_REG_MODE_ON = 1,
711 SER_REG_MODE_AUTO = 2,
712 };
713
714 #define AR_PHY_CCA_MAX_GOOD_VALUE -85
715 #define AR_PHY_CCA_MAX_HIGH_VALUE -62
716 #define AR_PHY_CCA_MIN_BAD_VALUE -121
717 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
718 #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
719
720 #define ATH9K_NF_CAL_HIST_MAX 5
721 #define NUM_NF_READINGS 6
722
723 struct ath9k_nfcal_hist {
724 int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
725 u8 currIndex;
726 int16_t privNF;
727 u8 invalidNFcount;
728 };
729
730 struct ath9k_beacon_state {
731 u32 bs_nexttbtt;
732 u32 bs_nextdtim;
733 u32 bs_intval;
734 #define ATH9K_BEACON_PERIOD 0x0000ffff
735 #define ATH9K_BEACON_ENA 0x00800000
736 #define ATH9K_BEACON_RESET_TSF 0x01000000
737 u32 bs_dtimperiod;
738 u16 bs_cfpperiod;
739 u16 bs_cfpmaxduration;
740 u32 bs_cfpnext;
741 u16 bs_timoffset;
742 u16 bs_bmissthreshold;
743 u32 bs_sleepduration;
744 };
745
746 struct ath9k_node_stats {
747 u32 ns_avgbrssi;
748 u32 ns_avgrssi;
749 u32 ns_avgtxrssi;
750 u32 ns_avgtxrate;
751 };
752
753 #define ATH9K_RSSI_EP_MULTIPLIER (1<<7)
754
755 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
756 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
757 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
758 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
759 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
760
761 enum {
762 ATH9K_RESET_POWER_ON,
763 ATH9K_RESET_WARM,
764 ATH9K_RESET_COLD,
765 };
766
767 #define AH_USE_EEPROM 0x1
768
769 struct ath_hal {
770 u32 ah_magic;
771 u16 ah_devid;
772 u16 ah_subvendorid;
773 u32 ah_macVersion;
774 u16 ah_macRev;
775 u16 ah_phyRev;
776 u16 ah_analog5GhzRev;
777 u16 ah_analog2GhzRev;
778
779 void __iomem *ah_sh;
780 struct ath_softc *ah_sc;
781 enum ath9k_opmode ah_opmode;
782 struct ath9k_ops_config ah_config;
783 struct ath9k_hw_capabilities ah_caps;
784
785 u16 ah_countryCode;
786 u32 ah_flags;
787 int16_t ah_powerLimit;
788 u16 ah_maxPowerLevel;
789 u32 ah_tpScale;
790 u16 ah_currentRD;
791 u16 ah_currentRDExt;
792 u16 ah_currentRDInUse;
793 u16 ah_currentRD5G;
794 u16 ah_currentRD2G;
795 char ah_iso[4];
796
797 struct ath9k_channel ah_channels[150];
798 struct ath9k_channel *ah_curchan;
799 u32 ah_nchan;
800
801 bool ah_isPciExpress;
802 u16 ah_txTrigLevel;
803 u16 ah_rfsilent;
804 u32 ah_rfkill_gpio;
805 u32 ah_rfkill_polarity;
806
807 #ifndef ATH_NF_PER_CHAN
808 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
809 #endif
810 };
811
812 struct chan_centers {
813 u16 synth_center;
814 u16 ctl_center;
815 u16 ext_center;
816 };
817
818 int ath_hal_getcapability(struct ath_hal *ah,
819 enum ath9k_capability_type type,
820 u32 capability,
821 u32 *result);
822 const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
823 u32 mode);
824 void ath9k_hw_detach(struct ath_hal *ah);
825 struct ath_hal *ath9k_hw_attach(u16 devid,
826 struct ath_softc *sc,
827 void __iomem *mem,
828 int *error);
829 bool ath9k_regd_init_channels(struct ath_hal *ah,
830 u32 maxchans, u32 *nchans,
831 u8 *regclassids,
832 u32 maxregids, u32 *nregids,
833 u16 cc,
834 bool enableOutdoor,
835 bool enableExtendedChannels);
836 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
837 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah,
838 enum ath9k_int ints);
839 bool ath9k_hw_reset(struct ath_hal *ah,
840 struct ath9k_channel *chan,
841 enum ath9k_ht_macmode macmode,
842 u8 txchainmask, u8 rxchainmask,
843 enum ath9k_ht_extprotspacing extprotspacing,
844 bool bChannelChange,
845 int *status);
846 bool ath9k_hw_phy_disable(struct ath_hal *ah);
847 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
848 bool *isCalDone);
849 void ath9k_hw_ani_monitor(struct ath_hal *ah,
850 const struct ath9k_node_stats *stats,
851 struct ath9k_channel *chan);
852 bool ath9k_hw_calibrate(struct ath_hal *ah,
853 struct ath9k_channel *chan,
854 u8 rxchainmask,
855 bool longcal,
856 bool *isCalDone);
857 s16 ath9k_hw_getchan_noise(struct ath_hal *ah,
858 struct ath9k_channel *chan);
859 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
860 u16 assocId);
861 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
862 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
863 u16 assocId);
864 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
865 void ath9k_hw_reset_tsf(struct ath_hal *ah);
866 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
867 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
868 const u8 *mac);
869 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
870 u16 entry,
871 const struct ath9k_keyval *k,
872 const u8 *mac,
873 int xorKey);
874 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
875 u32 setting);
876 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
877 bool ath9k_hw_intrpend(struct ath_hal *ah);
878 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
879 bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
880 bool bIncTrigLevel);
881 void ath9k_hw_procmibevent(struct ath_hal *ah,
882 const struct ath9k_node_stats *stats);
883 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
884 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
885 bool ath9k_hw_phycounters(struct ath_hal *ah);
886 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
887 bool ath9k_hw_getcapability(struct ath_hal *ah,
888 enum ath9k_capability_type type,
889 u32 capability,
890 u32 *result);
891 bool ath9k_hw_setcapability(struct ath_hal *ah,
892 enum ath9k_capability_type type,
893 u32 capability,
894 u32 setting,
895 int *status);
896 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
897 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
898 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
899 bool ath9k_hw_setbssidmask(struct ath_hal *ah,
900 const u8 *mask);
901 bool ath9k_hw_setpower(struct ath_hal *ah,
902 enum ath9k_power_mode mode);
903 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
904 u64 ath9k_hw_gettsf64(struct ath_hal *ah);
905 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
906 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
907 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
908 enum ath9k_ant_setting settings,
909 struct ath9k_channel *chan,
910 u8 *tx_chainmask,
911 u8 *rx_chainmask,
912 u8 *antenna_cfgd);
913 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
914 int ath9k_hw_select_antconfig(struct ath_hal *ah,
915 u32 cfg);
916 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
917 u32 txdp);
918 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
919 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
920 const struct ath9k_rate_table *rates,
921 u32 frameLen, u16 rateix,
922 bool shortPreamble);
923 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
924 struct ath_desc *lastds,
925 u32 durUpdateEn, u32 rtsctsRate,
926 u32 rtsctsDuration,
927 struct ath9k_11n_rate_series series[],
928 u32 nseries, u32 flags);
929 void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
930 struct ath_desc *ds,
931 u32 burstDuration);
932 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
933 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
934 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
935 u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
936 u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
937 struct ath9k_channel *chan);
938 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
939 bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
940 struct ath9k_tx_queue_info *qinfo);
941 bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
942 const struct ath9k_tx_queue_info *qinfo);
943 struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah,
944 const struct ath9k_channel *c);
945 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
946 u32 pktLen, enum ath9k_pkt_type type,
947 u32 txPower, u32 keyIx,
948 enum ath9k_key_type keyType, u32 flags);
949 bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
950 u32 segLen, bool firstSeg,
951 bool lastSeg,
952 const struct ath_desc *ds0);
953 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
954 u32 *rxc_pcnt,
955 u32 *rxf_pcnt,
956 u32 *txf_pcnt);
957 void ath9k_hw_dmaRegDump(struct ath_hal *ah);
958 void ath9k_hw_beaconinit(struct ath_hal *ah,
959 u32 next_beacon, u32 beacon_period);
960 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
961 const struct ath9k_beacon_state *bs);
962 bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
963 u32 size, u32 flags);
964 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
965 void ath9k_hw_rxena(struct ath_hal *ah);
966 void ath9k_hw_setopmode(struct ath_hal *ah);
967 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
968 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
969 u32 filter1);
970 u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
971 void ath9k_hw_startpcureceive(struct ath_hal *ah);
972 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
973 bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
974 int ath9k_hw_rxprocdesc(struct ath_hal *ah,
975 struct ath_desc *ds, u32 pa,
976 struct ath_desc *nds, u64 tsf);
977 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
978 int ath9k_hw_txprocdesc(struct ath_hal *ah,
979 struct ath_desc *ds);
980 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
981 u32 numDelims);
982 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
983 u32 aggrLen);
984 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
985 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
986 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
987 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
988 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
989 struct ath_desc *ds, u32 vmf);
990 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
991 bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
992 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
993 const struct ath9k_tx_queue_info *qinfo);
994 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
995 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
996 bool ath9k_hw_disable(struct ath_hal *ah);
997 void ath9k_hw_rfdetach(struct ath_hal *ah);
998 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
999 struct ath9k_channel *chan,
1000 struct chan_centers *centers);
1001 bool ath9k_get_channel_edges(struct ath_hal *ah,
1002 u16 flags, u16 *low,
1003 u16 *high);
1004 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
1005 u32 ah_signal_type);
1006 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 value);
1007 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio);
1008 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio);
1009 #endif
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