drivers/net/wireless/ath9k/ath9k.h

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef ATH9K_H
  18 #define ATH9K_H
  19
  20 #include <linux/io.h>
  21
  22 #define ATHEROS_VENDOR_ID       0x168c
  23
  24 #define AR5416_DEVID_PCI        0x0023
  25 #define AR5416_DEVID_PCIE       0x0024
  26 #define AR9160_DEVID_PCI        0x0027
  27 #define AR9280_DEVID_PCI        0x0029
  28 #define AR9280_DEVID_PCIE       0x002a
  29
  30 #define AR5416_AR9100_DEVID     0x000b
  31
  32 #define AR_SUBVENDOR_ID_NOG     0x0e11
  33 #define AR_SUBVENDOR_ID_NEW_A   0x7065
  34
  35 #define ATH9K_TXERR_XRETRY         0x01
  36 #define ATH9K_TXERR_FILT           0x02
  37 #define ATH9K_TXERR_FIFO           0x04
  38 #define ATH9K_TXERR_XTXOP          0x08
  39 #define ATH9K_TXERR_TIMER_EXPIRED  0x10
  40
  41 #define ATH9K_TX_BA                0x01
  42 #define ATH9K_TX_PWRMGMT           0x02
  43 #define ATH9K_TX_DESC_CFG_ERR      0x04
  44 #define ATH9K_TX_DATA_UNDERRUN     0x08
  45 #define ATH9K_TX_DELIM_UNDERRUN    0x10
  46 #define ATH9K_TX_SW_ABORTED        0x40
  47 #define ATH9K_TX_SW_FILTERED       0x80
  48
  49 #define NBBY    8
  50
  51 struct ath_tx_status {
  52         u32 ts_tstamp;
  53         u16 ts_seqnum;
  54         u8 ts_status;
  55         u8 ts_ratecode;
  56         u8 ts_rateindex;
  57         int8_t ts_rssi;
  58         u8 ts_shortretry;
  59         u8 ts_longretry;
  60         u8 ts_virtcol;
  61         u8 ts_antenna;
  62         u8 ts_flags;
  63         int8_t ts_rssi_ctl0;
  64         int8_t ts_rssi_ctl1;
  65         int8_t ts_rssi_ctl2;
  66         int8_t ts_rssi_ext0;
  67         int8_t ts_rssi_ext1;
  68         int8_t ts_rssi_ext2;
  69         u8 pad[3];
  70         u32 ba_low;
  71         u32 ba_high;
  72         u32 evm0;
  73         u32 evm1;
  74         u32 evm2;
  75 };
  76
  77 struct ath_rx_status {
  78         u32 rs_tstamp;
  79         u16 rs_datalen;
  80         u8 rs_status;
  81         u8 rs_phyerr;
  82         int8_t rs_rssi;
  83         u8 rs_keyix;
  84         u8 rs_rate;
  85         u8 rs_antenna;
  86         u8 rs_more;
  87         int8_t rs_rssi_ctl0;
  88         int8_t rs_rssi_ctl1;
  89         int8_t rs_rssi_ctl2;
  90         int8_t rs_rssi_ext0;
  91         int8_t rs_rssi_ext1;
  92         int8_t rs_rssi_ext2;
  93         u8 rs_isaggr;
  94         u8 rs_moreaggr;
  95         u8 rs_num_delims;
  96         u8 rs_flags;
  97         u32 evm0;
  98         u32 evm1;
  99         u32 evm2;
 100 };
 101
 102 #define ATH9K_RXERR_CRC           0x01
 103 #define ATH9K_RXERR_PHY           0x02
 104 #define ATH9K_RXERR_FIFO          0x04
 105 #define ATH9K_RXERR_DECRYPT       0x08
 106 #define ATH9K_RXERR_MIC           0x10
 107
 108 #define ATH9K_RX_MORE             0x01
 109 #define ATH9K_RX_MORE_AGGR        0x02
 110 #define ATH9K_RX_GI               0x04
 111 #define ATH9K_RX_2040             0x08
 112 #define ATH9K_RX_DELIM_CRC_PRE    0x10
 113 #define ATH9K_RX_DELIM_CRC_POST   0x20
 114 #define ATH9K_RX_DECRYPT_BUSY     0x40
 115
 116 #define ATH9K_RXKEYIX_INVALID   ((u8)-1)
 117 #define ATH9K_TXKEYIX_INVALID   ((u32)-1)
 118
 119 struct ath_desc {
 120         u32 ds_link;
 121         u32 ds_data;
 122         u32 ds_ctl0;
 123         u32 ds_ctl1;
 124         u32 ds_hw[20];
 125         union {
 126                 struct ath_tx_status tx;
 127                 struct ath_rx_status rx;
 128                 void *stats;
 129         } ds_us;
 130         void *ds_vdata;
 131 } __packed;
 132
 133 #define ds_txstat       ds_us.tx
 134 #define ds_rxstat       ds_us.rx
 135 #define ds_stat         ds_us.stats
 136
 137 #define ATH9K_TXDESC_CLRDMASK           0x0001
 138 #define ATH9K_TXDESC_NOACK              0x0002
 139 #define ATH9K_TXDESC_RTSENA             0x0004
 140 #define ATH9K_TXDESC_CTSENA             0x0008
 141 #define ATH9K_TXDESC_INTREQ             0x0010
 142 #define ATH9K_TXDESC_VEOL               0x0020
 143 #define ATH9K_TXDESC_EXT_ONLY           0x0040
 144 #define ATH9K_TXDESC_EXT_AND_CTL        0x0080
 145 #define ATH9K_TXDESC_VMF                0x0100
 146 #define ATH9K_TXDESC_FRAG_IS_ON         0x0200
 147
 148 #define ATH9K_RXDESC_INTREQ             0x0020
 149
 150 enum wireless_mode {
 151         ATH9K_MODE_11A = 0,
 152         ATH9K_MODE_11B = 2,
 153         ATH9K_MODE_11G = 3,
 154         ATH9K_MODE_11NA_HT20 = 6,
 155         ATH9K_MODE_11NG_HT20 = 7,
 156         ATH9K_MODE_11NA_HT40PLUS = 8,
 157         ATH9K_MODE_11NA_HT40MINUS = 9,
 158         ATH9K_MODE_11NG_HT40PLUS = 10,
 159         ATH9K_MODE_11NG_HT40MINUS = 11,
 160         ATH9K_MODE_MAX
 161 };
 162
 163 enum ath9k_hw_caps {
 164         ATH9K_HW_CAP_CHAN_SPREAD                = BIT(0),
 165         ATH9K_HW_CAP_MIC_AESCCM                 = BIT(1),
 166         ATH9K_HW_CAP_MIC_CKIP                   = BIT(2),
 167         ATH9K_HW_CAP_MIC_TKIP                   = BIT(3),
 168         ATH9K_HW_CAP_CIPHER_AESCCM              = BIT(4),
 169         ATH9K_HW_CAP_CIPHER_CKIP                = BIT(5),
 170         ATH9K_HW_CAP_CIPHER_TKIP                = BIT(6),
 171         ATH9K_HW_CAP_VEOL                       = BIT(7),
 172         ATH9K_HW_CAP_BSSIDMASK                  = BIT(8),
 173         ATH9K_HW_CAP_MCAST_KEYSEARCH            = BIT(9),
 174         ATH9K_HW_CAP_CHAN_HALFRATE              = BIT(10),
 175         ATH9K_HW_CAP_CHAN_QUARTERRATE           = BIT(11),
 176         ATH9K_HW_CAP_HT                         = BIT(12),
 177         ATH9K_HW_CAP_GTT                        = BIT(13),
 178         ATH9K_HW_CAP_FASTCC                     = BIT(14),
 179         ATH9K_HW_CAP_RFSILENT                   = BIT(15),
 180         ATH9K_HW_CAP_WOW                        = BIT(16),
 181         ATH9K_HW_CAP_CST                        = BIT(17),
 182         ATH9K_HW_CAP_ENHANCEDPM                 = BIT(18),
 183         ATH9K_HW_CAP_AUTOSLEEP                  = BIT(19),
 184         ATH9K_HW_CAP_4KB_SPLITTRANS             = BIT(20),
 185         ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT     = BIT(21),
 186 };
 187
 188 enum ath9k_capability_type {
 189         ATH9K_CAP_CIPHER = 0,
 190         ATH9K_CAP_TKIP_MIC,
 191         ATH9K_CAP_TKIP_SPLIT,
 192         ATH9K_CAP_PHYCOUNTERS,
 193         ATH9K_CAP_DIVERSITY,
 194         ATH9K_CAP_TXPOW,
 195         ATH9K_CAP_PHYDIAG,
 196         ATH9K_CAP_MCAST_KEYSRCH,
 197         ATH9K_CAP_TSF_ADJUST,
 198         ATH9K_CAP_WME_TKIPMIC,
 199         ATH9K_CAP_RFSILENT,
 200         ATH9K_CAP_ANT_CFG_2GHZ,
 201         ATH9K_CAP_ANT_CFG_5GHZ
 202 };
 203
 204 struct ath9k_hw_capabilities {
 205         u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
 206         DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
 207         u16 total_queues;
 208         u16 keycache_size;
 209         u16 low_5ghz_chan, high_5ghz_chan;
 210         u16 low_2ghz_chan, high_2ghz_chan;
 211         u16 num_mr_retries;
 212         u16 rts_aggr_limit;
 213         u8 tx_chainmask;
 214         u8 rx_chainmask;
 215         u16 tx_triglevel_max;
 216         u16 reg_cap;
 217         u8 num_gpio_pins;
 218         u8 num_antcfg_2ghz;
 219         u8 num_antcfg_5ghz;
 220 };
 221
 222 struct ath9k_ops_config {
 223         int dma_beacon_response_time;
 224         int sw_beacon_response_time;
 225         int additional_swba_backoff;
 226         int ack_6mb;
 227         int cwm_ignore_extcca;
 228         u8 pcie_powersave_enable;
 229         u8 pcie_l1skp_enable;
 230         u8 pcie_clock_req;
 231         u32 pcie_waen;
 232         int pcie_power_reset;
 233         u8 pcie_restore;
 234         u8 analog_shiftreg;
 235         u8 ht_enable;
 236         u32 ofdm_trig_low;
 237         u32 ofdm_trig_high;
 238         u32 cck_trig_high;
 239         u32 cck_trig_low;
 240         u32 enable_ani;
 241         u8 noise_immunity_level;
 242         u32 ofdm_weaksignal_det;
 243         u32 cck_weaksignal_thr;
 244         u8 spur_immunity_level;
 245         u8 firstep_level;
 246         int8_t rssi_thr_high;
 247         int8_t rssi_thr_low;
 248         u16 diversity_control;
 249         u16 antenna_switch_swap;
 250         int serialize_regmode;
 251         int intr_mitigation;
 252 #define SPUR_DISABLE            0
 253 #define SPUR_ENABLE_IOCTL       1
 254 #define SPUR_ENABLE_EEPROM      2
 255 #define AR_EEPROM_MODAL_SPURS   5
 256 #define AR_SPUR_5413_1          1640
 257 #define AR_SPUR_5413_2          1200
 258 #define AR_NO_SPUR              0x8000
 259 #define AR_BASE_FREQ_2GHZ       2300
 260 #define AR_BASE_FREQ_5GHZ       4900
 261 #define AR_SPUR_FEEQ_BOUND_HT40 19
 262 #define AR_SPUR_FEEQ_BOUND_HT20 10
 263         int spurmode;
 264         u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
 265 };
 266
 267 enum ath9k_tx_queue {
 268         ATH9K_TX_QUEUE_INACTIVE = 0,
 269         ATH9K_TX_QUEUE_DATA,
 270         ATH9K_TX_QUEUE_BEACON,
 271         ATH9K_TX_QUEUE_CAB,
 272         ATH9K_TX_QUEUE_UAPSD,
 273         ATH9K_TX_QUEUE_PSPOLL
 274 };
 275
 276 #define ATH9K_NUM_TX_QUEUES 10
 277
 278 enum ath9k_tx_queue_subtype {
 279         ATH9K_WME_AC_BK = 0,
 280         ATH9K_WME_AC_BE,
 281         ATH9K_WME_AC_VI,
 282         ATH9K_WME_AC_VO,
 283         ATH9K_WME_UPSD
 284 };
 285
 286 enum ath9k_tx_queue_flags {
 287         TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
 288         TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
 289         TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
 290         TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
 291         TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
 292         TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
 293         TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
 294         TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
 295         TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
 296 };
 297
 298 #define ATH9K_TXQ_USEDEFAULT ((u32) -1)
 299
 300 #define ATH9K_DECOMP_MASK_SIZE     128
 301 #define ATH9K_READY_TIME_LO_BOUND  50
 302 #define ATH9K_READY_TIME_HI_BOUND  96
 303
 304 enum ath9k_pkt_type {
 305         ATH9K_PKT_TYPE_NORMAL = 0,
 306         ATH9K_PKT_TYPE_ATIM,
 307         ATH9K_PKT_TYPE_PSPOLL,
 308         ATH9K_PKT_TYPE_BEACON,
 309         ATH9K_PKT_TYPE_PROBE_RESP,
 310         ATH9K_PKT_TYPE_CHIRP,
 311         ATH9K_PKT_TYPE_GRP_POLL,
 312 };
 313
 314 struct ath9k_tx_queue_info {
 315         u32 tqi_ver;
 316         enum ath9k_tx_queue tqi_type;
 317         enum ath9k_tx_queue_subtype tqi_subtype;
 318         enum ath9k_tx_queue_flags tqi_qflags;
 319         u32 tqi_priority;
 320         u32 tqi_aifs;
 321         u32 tqi_cwmin;
 322         u32 tqi_cwmax;
 323         u16 tqi_shretry;
 324         u16 tqi_lgretry;
 325         u32 tqi_cbrPeriod;
 326         u32 tqi_cbrOverflowLimit;
 327         u32 tqi_burstTime;
 328         u32 tqi_readyTime;
 329         u32 tqi_physCompBuf;
 330         u32 tqi_intFlags;
 331 };
 332
 333 enum ath9k_rx_filter {
 334         ATH9K_RX_FILTER_UCAST = 0x00000001,
 335         ATH9K_RX_FILTER_MCAST = 0x00000002,
 336         ATH9K_RX_FILTER_BCAST = 0x00000004,
 337         ATH9K_RX_FILTER_CONTROL = 0x00000008,
 338         ATH9K_RX_FILTER_BEACON = 0x00000010,
 339         ATH9K_RX_FILTER_PROM = 0x00000020,
 340         ATH9K_RX_FILTER_PROBEREQ = 0x00000080,
 341         ATH9K_RX_FILTER_PSPOLL = 0x00004000,
 342         ATH9K_RX_FILTER_PHYERR = 0x00000100,
 343         ATH9K_RX_FILTER_PHYRADAR = 0x00002000,
 344 };
 345
 346 enum ath9k_int {
 347         ATH9K_INT_RX = 0x00000001,
 348         ATH9K_INT_RXDESC = 0x00000002,
 349         ATH9K_INT_RXNOFRM = 0x00000008,
 350         ATH9K_INT_RXEOL = 0x00000010,
 351         ATH9K_INT_RXORN = 0x00000020,
 352         ATH9K_INT_TX = 0x00000040,
 353         ATH9K_INT_TXDESC = 0x00000080,
 354         ATH9K_INT_TIM_TIMER = 0x00000100,
 355         ATH9K_INT_TXURN = 0x00000800,
 356         ATH9K_INT_MIB = 0x00001000,
 357         ATH9K_INT_RXPHY = 0x00004000,
 358         ATH9K_INT_RXKCM = 0x00008000,
 359         ATH9K_INT_SWBA = 0x00010000,
 360         ATH9K_INT_BMISS = 0x00040000,
 361         ATH9K_INT_BNR = 0x00100000,
 362         ATH9K_INT_TIM = 0x00200000,
 363         ATH9K_INT_DTIM = 0x00400000,
 364         ATH9K_INT_DTIMSYNC = 0x00800000,
 365         ATH9K_INT_GPIO = 0x01000000,
 366         ATH9K_INT_CABEND = 0x02000000,
 367         ATH9K_INT_CST = 0x10000000,
 368         ATH9K_INT_GTT = 0x20000000,
 369         ATH9K_INT_FATAL = 0x40000000,
 370         ATH9K_INT_GLOBAL = 0x80000000,
 371         ATH9K_INT_BMISC = ATH9K_INT_TIM |
 372                 ATH9K_INT_DTIM |
 373                 ATH9K_INT_DTIMSYNC |
 374                 ATH9K_INT_CABEND,
 375         ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
 376                 ATH9K_INT_RXDESC |
 377                 ATH9K_INT_RXEOL |
 378                 ATH9K_INT_RXORN |
 379                 ATH9K_INT_TXURN |
 380                 ATH9K_INT_TXDESC |
 381                 ATH9K_INT_MIB |
 382                 ATH9K_INT_RXPHY |
 383                 ATH9K_INT_RXKCM |
 384                 ATH9K_INT_SWBA |
 385                 ATH9K_INT_BMISS |
 386                 ATH9K_INT_GPIO,
 387         ATH9K_INT_NOCARD = 0xffffffff
 388 };
 389
 390 struct ath9k_rate_table {
 391         int rateCount;
 392         u8 rateCodeToIndex[256];
 393         struct {
 394                 u8 valid;
 395                 u8 phy;
 396                 u32 rateKbps;
 397                 u8 rateCode;
 398                 u8 shortPreamble;
 399                 u8 dot11Rate;
 400                 u8 controlRate;
 401                 u16 lpAckDuration;
 402                 u16 spAckDuration;
 403         } info[32];
 404 };
 405
 406 #define ATH9K_RATESERIES_RTS_CTS  0x0001
 407 #define ATH9K_RATESERIES_2040     0x0002
 408 #define ATH9K_RATESERIES_HALFGI   0x0004
 409
 410 struct ath9k_11n_rate_series {
 411         u32 Tries;
 412         u32 Rate;
 413         u32 PktDuration;
 414         u32 ChSel;
 415         u32 RateFlags;
 416 };
 417
 418 #define CHANNEL_CW_INT    0x00002
 419 #define CHANNEL_CCK       0x00020
 420 #define CHANNEL_OFDM      0x00040
 421 #define CHANNEL_2GHZ      0x00080
 422 #define CHANNEL_5GHZ      0x00100
 423 #define CHANNEL_PASSIVE   0x00200
 424 #define CHANNEL_DYN       0x00400
 425 #define CHANNEL_HALF      0x04000
 426 #define CHANNEL_QUARTER   0x08000
 427 #define CHANNEL_HT20      0x10000
 428 #define CHANNEL_HT40PLUS  0x20000
 429 #define CHANNEL_HT40MINUS 0x40000
 430
 431 #define CHANNEL_INTERFERENCE    0x01
 432 #define CHANNEL_DFS             0x02
 433 #define CHANNEL_4MS_LIMIT       0x04
 434 #define CHANNEL_DFS_CLEAR       0x08
 435 #define CHANNEL_DISALLOW_ADHOC  0x10
 436 #define CHANNEL_PER_11D_ADHOC   0x20
 437
 438 #define CHANNEL_A           (CHANNEL_5GHZ|CHANNEL_OFDM)
 439 #define CHANNEL_B           (CHANNEL_2GHZ|CHANNEL_CCK)
 440 #define CHANNEL_G           (CHANNEL_2GHZ|CHANNEL_OFDM)
 441 #define CHANNEL_G_HT20      (CHANNEL_2GHZ|CHANNEL_HT20)
 442 #define CHANNEL_A_HT20      (CHANNEL_5GHZ|CHANNEL_HT20)
 443 #define CHANNEL_G_HT40PLUS  (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
 444 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
 445 #define CHANNEL_A_HT40PLUS  (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
 446 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
 447 #define CHANNEL_ALL                             \
 448         (CHANNEL_OFDM|                          \
 449          CHANNEL_CCK|                           \
 450          CHANNEL_2GHZ |                         \
 451          CHANNEL_5GHZ |                         \
 452          CHANNEL_HT20 |                         \
 453          CHANNEL_HT40PLUS |                     \
 454          CHANNEL_HT40MINUS)
 455
 456 struct ath9k_channel {
 457         u16 channel;
 458         u32 channelFlags;
 459         u8 privFlags;
 460         int8_t maxRegTxPower;
 461         int8_t maxTxPower;
 462         int8_t minTxPower;
 463         u32 chanmode;
 464         int32_t CalValid;
 465         bool oneTimeCalsDone;
 466         int8_t iCoff;
 467         int8_t qCoff;
 468         int16_t rawNoiseFloor;
 469         int8_t antennaMax;
 470         u32 regDmnFlags;
 471         u32 conformanceTestLimit[3]; /* 0:11a, 1: 11b, 2:11g */
 472 #ifdef ATH_NF_PER_CHAN
 473         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 474 #endif
 475 };
 476
 477 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
 478        (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
 479        (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
 480        (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
 481 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
 482 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
 483        (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
 484        (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
 485        (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
 486 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
 487 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
 488 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
 489 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
 490 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
 491 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
 492 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
 493
 494 /* These macros check chanmode and not channelFlags */
 495 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
 496                           ((_c)->chanmode == CHANNEL_G_HT20))
 497 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) ||     \
 498                           ((_c)->chanmode == CHANNEL_A_HT40MINUS) ||    \
 499                           ((_c)->chanmode == CHANNEL_G_HT40PLUS) ||     \
 500                           ((_c)->chanmode == CHANNEL_G_HT40MINUS))
 501 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
 502
 503 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
 504 #define IS_CHAN_A_5MHZ_SPACED(_c)                       \
 505         ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) &&  \
 506          (((_c)->channel % 20) != 0) &&                 \
 507          (((_c)->channel % 10) != 0))
 508
 509 struct ath9k_keyval {
 510         u8 kv_type;
 511         u8 kv_pad;
 512         u16 kv_len;
 513         u8 kv_val[16];
 514         u8 kv_mic[8];
 515         u8 kv_txmic[8];
 516 };
 517
 518 enum ath9k_key_type {
 519         ATH9K_KEY_TYPE_CLEAR,
 520         ATH9K_KEY_TYPE_WEP,
 521         ATH9K_KEY_TYPE_AES,
 522         ATH9K_KEY_TYPE_TKIP,
 523 };
 524
 525 enum ath9k_cipher {
 526         ATH9K_CIPHER_WEP = 0,
 527         ATH9K_CIPHER_AES_OCB = 1,
 528         ATH9K_CIPHER_AES_CCM = 2,
 529         ATH9K_CIPHER_CKIP = 3,
 530         ATH9K_CIPHER_TKIP = 4,
 531         ATH9K_CIPHER_CLR = 5,
 532         ATH9K_CIPHER_MIC = 127
 533 };
 534
 535 #define AR_EEPROM_EEPCAP_COMPRESS_DIS   0x0001
 536 #define AR_EEPROM_EEPCAP_AES_DIS        0x0002
 537 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS  0x0004
 538 #define AR_EEPROM_EEPCAP_BURST_DIS      0x0008
 539 #define AR_EEPROM_EEPCAP_MAXQCU         0x01F0
 540 #define AR_EEPROM_EEPCAP_MAXQCU_S       4
 541 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN  0x0200
 542 #define AR_EEPROM_EEPCAP_KC_ENTRIES     0xF000
 543 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S   12
 544
 545 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND   0x0040
 546 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN    0x0080
 547 #define AR_EEPROM_EEREGCAP_EN_KK_U2         0x0100
 548 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND    0x0200
 549 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD     0x0400
 550 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A    0x0800
 551
 552 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0  0x4000
 553 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
 554
 555 #define SD_NO_CTL               0xE0
 556 #define NO_CTL                  0xff
 557 #define CTL_MODE_M              7
 558 #define CTL_11A                 0
 559 #define CTL_11B                 1
 560 #define CTL_11G                 2
 561 #define CTL_2GHT20              5
 562 #define CTL_5GHT20              6
 563 #define CTL_2GHT40              7
 564 #define CTL_5GHT40              8
 565
 566 #define AR_EEPROM_MAC(i)        (0x1d+(i))
 567 #define EEP_SCALE       100
 568 #define EEP_DELTA       10
 569
 570 #define AR_EEPROM_RFSILENT_GPIO_SEL     0x001c
 571 #define AR_EEPROM_RFSILENT_GPIO_SEL_S   2
 572 #define AR_EEPROM_RFSILENT_POLARITY     0x0002
 573 #define AR_EEPROM_RFSILENT_POLARITY_S   1
 574
 575 #define CTRY_DEBUG 0x1ff
 576 #define CTRY_DEFAULT 0
 577
 578 enum reg_ext_bitmap {
 579         REG_EXT_JAPAN_MIDBAND = 1,
 580         REG_EXT_FCC_DFS_HT40 = 2,
 581         REG_EXT_JAPAN_NONDFS_HT40 = 3,
 582         REG_EXT_JAPAN_DFS_HT40 = 4
 583 };
 584
 585 struct ath9k_country_entry {
 586         u16 countryCode;
 587         u16 regDmnEnum;
 588         u16 regDmn5G;
 589         u16 regDmn2G;
 590         u8 isMultidomain;
 591         u8 iso[3];
 592 };
 593
 594 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
 595 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
 596
 597 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
 598 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
 599 #define REG_RMW(_a, _r, _set, _clr)    \
 600         REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
 601 #define REG_RMW_FIELD(_a, _r, _f, _v) \
 602         REG_WRITE(_a, _r, \
 603         (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
 604 #define REG_SET_BIT(_a, _r, _f) \
 605         REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
 606 #define REG_CLR_BIT(_a, _r, _f) \
 607         REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
 608
 609 #define ATH9K_COMP_BUF_MAX_SIZE   9216
 610 #define ATH9K_COMP_BUF_ALIGN_SIZE 512
 611
 612 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS   0x00000001
 613
 614 #define INIT_AIFS       2
 615 #define INIT_CWMIN      15
 616 #define INIT_CWMIN_11B  31
 617 #define INIT_CWMAX      1023
 618 #define INIT_SH_RETRY   10
 619 #define INIT_LG_RETRY   10
 620 #define INIT_SSH_RETRY  32
 621 #define INIT_SLG_RETRY  32
 622
 623 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
 624
 625 #define ATH_AMPDU_LIMIT_MAX      (64 * 1024 - 1)
 626 #define ATH_AMPDU_LIMIT_DEFAULT  ATH_AMPDU_LIMIT_MAX
 627
 628 #define IEEE80211_WEP_IVLEN      3
 629 #define IEEE80211_WEP_KIDLEN     1
 630 #define IEEE80211_WEP_CRCLEN     4
 631 #define IEEE80211_MAX_MPDU_LEN  (3840 + FCS_LEN +               \
 632                                  (IEEE80211_WEP_IVLEN +         \
 633                                   IEEE80211_WEP_KIDLEN +        \
 634                                   IEEE80211_WEP_CRCLEN))
 635 #define IEEE80211_MAX_LEN       (2300 + FCS_LEN +               \
 636                                  (IEEE80211_WEP_IVLEN +         \
 637                                   IEEE80211_WEP_KIDLEN +        \
 638                                   IEEE80211_WEP_CRCLEN))
 639
 640 #define MAX_REG_ADD_COUNT   129
 641 #define MAX_RATE_POWER 63
 642
 643 enum ath9k_power_mode {
 644         ATH9K_PM_AWAKE = 0,
 645         ATH9K_PM_FULL_SLEEP,
 646         ATH9K_PM_NETWORK_SLEEP,
 647         ATH9K_PM_UNDEFINED
 648 };
 649
 650 struct ath9k_mib_stats {
 651         u32 ackrcv_bad;
 652         u32 rts_bad;
 653         u32 rts_good;
 654         u32 fcs_bad;
 655         u32 beacons;
 656 };
 657
 658 enum ath9k_ant_setting {
 659         ATH9K_ANT_VARIABLE = 0,
 660         ATH9K_ANT_FIXED_A,
 661         ATH9K_ANT_FIXED_B
 662 };
 663
 664 enum ath9k_opmode {
 665         ATH9K_M_STA = 1,
 666         ATH9K_M_IBSS = 0,
 667         ATH9K_M_HOSTAP = 6,
 668         ATH9K_M_MONITOR = 8
 669 };
 670
 671 #define ATH9K_SLOT_TIME_6 6
 672 #define ATH9K_SLOT_TIME_9 9
 673 #define ATH9K_SLOT_TIME_20 20
 674
 675 enum ath9k_ht_macmode {
 676         ATH9K_HT_MACMODE_20 = 0,
 677         ATH9K_HT_MACMODE_2040 = 1,
 678 };
 679
 680 enum ath9k_ht_extprotspacing {
 681         ATH9K_HT_EXTPROTSPACING_20 = 0,
 682         ATH9K_HT_EXTPROTSPACING_25 = 1,
 683 };
 684
 685 struct ath9k_ht_cwm {
 686         enum ath9k_ht_macmode ht_macmode;
 687         enum ath9k_ht_extprotspacing ht_extprotspacing;
 688 };
 689
 690 enum ath9k_ani_cmd {
 691         ATH9K_ANI_PRESENT = 0x1,
 692         ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
 693         ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
 694         ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
 695         ATH9K_ANI_FIRSTEP_LEVEL = 0x10,
 696         ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
 697         ATH9K_ANI_MODE = 0x40,
 698         ATH9K_ANI_PHYERR_RESET = 0x80,
 699         ATH9K_ANI_ALL = 0xff
 700 };
 701
 702 enum phytype {
 703         PHY_DS,
 704         PHY_FH,
 705         PHY_OFDM,
 706         PHY_HT,
 707 };
 708 #define PHY_CCK PHY_DS
 709
 710 enum start_adhoc_option {
 711         START_ADHOC_NO_11A,
 712         START_ADHOC_PER_11D,
 713         START_ADHOC_IN_11A,
 714         START_ADHOC_IN_11B,
 715 };
 716
 717 enum ath9k_tp_scale {
 718         ATH9K_TP_SCALE_MAX = 0,
 719         ATH9K_TP_SCALE_50,
 720         ATH9K_TP_SCALE_25,
 721         ATH9K_TP_SCALE_12,
 722         ATH9K_TP_SCALE_MIN
 723 };
 724
 725 enum ser_reg_mode {
 726         SER_REG_MODE_OFF = 0,
 727         SER_REG_MODE_ON = 1,
 728         SER_REG_MODE_AUTO = 2,
 729 };
 730
 731 #define AR_PHY_CCA_MAX_GOOD_VALUE               -85
 732 #define AR_PHY_CCA_MAX_HIGH_VALUE               -62
 733 #define AR_PHY_CCA_MIN_BAD_VALUE                -121
 734 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT     3
 735 #define AR_PHY_CCA_FILTERWINDOW_LENGTH          5
 736
 737 #define ATH9K_NF_CAL_HIST_MAX           5
 738 #define NUM_NF_READINGS                 6
 739
 740 struct ath9k_nfcal_hist {
 741         int16_t nfCalBuffer[ATH9K_NF_CAL_HIST_MAX];
 742         u8 currIndex;
 743         int16_t privNF;
 744         u8 invalidNFcount;
 745 };
 746
 747 struct ath9k_beacon_state {
 748         u32 bs_nexttbtt;
 749         u32 bs_nextdtim;
 750         u32 bs_intval;
 751 #define ATH9K_BEACON_PERIOD       0x0000ffff
 752 #define ATH9K_BEACON_ENA          0x00800000
 753 #define ATH9K_BEACON_RESET_TSF    0x01000000
 754         u32 bs_dtimperiod;
 755         u16 bs_cfpperiod;
 756         u16 bs_cfpmaxduration;
 757         u32 bs_cfpnext;
 758         u16 bs_timoffset;
 759         u16 bs_bmissthreshold;
 760         u32 bs_sleepduration;
 761 };
 762
 763 struct ath9k_node_stats {
 764         u32 ns_avgbrssi;
 765         u32 ns_avgrssi;
 766         u32 ns_avgtxrssi;
 767         u32 ns_avgtxrate;
 768 };
 769
 770 #define ATH9K_RSSI_EP_MULTIPLIER  (1<<7)
 771
 772 enum ath9k_gpio_output_mux_type {
 773         ATH9K_GPIO_OUTPUT_MUX_AS_OUTPUT,
 774         ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
 775         ATH9K_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
 776         ATH9K_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
 777         ATH9K_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
 778         ATH9K_GPIO_OUTPUT_MUX_NUM_ENTRIES
 779 };
 780
 781 enum {
 782         ATH9K_RESET_POWER_ON,
 783         ATH9K_RESET_WARM,
 784         ATH9K_RESET_COLD,
 785 };
 786
 787 #define AH_USE_EEPROM   0x1
 788
 789 struct ath_hal {
 790         u32 ah_magic;
 791         u16 ah_devid;
 792         u16 ah_subvendorid;
 793         struct ath_softc *ah_sc;
 794         void __iomem *ah_sh;
 795         u16 ah_countryCode;
 796         u32 ah_macVersion;
 797         u16 ah_macRev;
 798         u16 ah_phyRev;
 799         u16 ah_analog5GhzRev;
 800         u16 ah_analog2GhzRev;
 801         u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE];
 802         u32 ah_flags;
 803         enum ath9k_opmode ah_opmode;
 804         struct ath9k_ops_config ah_config;
 805         struct ath9k_hw_capabilities ah_caps;
 806         int16_t ah_powerLimit;
 807         u16 ah_maxPowerLevel;
 808         u32 ah_tpScale;
 809         u16 ah_currentRD;
 810         u16 ah_currentRDExt;
 811         u16 ah_currentRDInUse;
 812         u16 ah_currentRD5G;
 813         u16 ah_currentRD2G;
 814         char ah_iso[4];
 815         enum start_adhoc_option ah_adHocMode;
 816         bool ah_commonMode;
 817         struct ath9k_channel ah_channels[150];
 818         u32 ah_nchan;
 819         struct ath9k_channel *ah_curchan;
 820         u16 ah_rfsilent;
 821         bool ah_rfkillEnabled;
 822         bool ah_isPciExpress;
 823         u16 ah_txTrigLevel;
 824 #ifndef ATH_NF_PER_CHAN
 825         struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
 826 #endif
 827 };
 828
 829 struct chan_centers {
 830         u16 synth_center;
 831         u16 ctl_center;
 832         u16 ext_center;
 833 };
 834
 835 int ath_hal_getcapability(struct ath_hal *ah,
 836                           enum ath9k_capability_type type,
 837                           u32 capability,
 838                           u32 *result);
 839 const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
 840                                                      u32 mode);
 841 void ath9k_hw_detach(struct ath_hal *ah);
 842 struct ath_hal *ath9k_hw_attach(u16 devid,
 843                                 struct ath_softc *sc,
 844                                 void __iomem *mem,
 845                                 int *error);
 846 bool ath9k_regd_init_channels(struct ath_hal *ah,
 847                               u32 maxchans, u32 *nchans,
 848                               u8 *regclassids,
 849                               u32 maxregids, u32 *nregids,
 850                               u16 cc,
 851                               bool enableOutdoor,
 852                               bool enableExtendedChannels);
 853 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
 854 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah,
 855                                      enum ath9k_int ints);
 856 bool ath9k_hw_reset(struct ath_hal *ah, enum ath9k_opmode opmode,
 857                     struct ath9k_channel *chan,
 858                     enum ath9k_ht_macmode macmode,
 859                     u8 txchainmask, u8 rxchainmask,
 860                     enum ath9k_ht_extprotspacing extprotspacing,
 861                     bool bChannelChange,
 862                     int *status);
 863 bool ath9k_hw_phy_disable(struct ath_hal *ah);
 864 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct ath9k_channel *chan,
 865                              bool *isCalDone);
 866 void ath9k_hw_ani_monitor(struct ath_hal *ah,
 867                           const struct ath9k_node_stats *stats,
 868                           struct ath9k_channel *chan);
 869 bool ath9k_hw_calibrate(struct ath_hal *ah,
 870                         struct ath9k_channel *chan,
 871                         u8 rxchainmask,
 872                         bool longcal,
 873                         bool *isCalDone);
 874 int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
 875                                struct ath9k_channel *chan);
 876 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
 877                             u16 assocId);
 878 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits);
 879 void ath9k_hw_write_associd(struct ath_hal *ah, const u8 *bssid,
 880                             u16 assocId);
 881 bool ath9k_hw_stoptxdma(struct ath_hal *ah, u32 q);
 882 void ath9k_hw_reset_tsf(struct ath_hal *ah);
 883 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry);
 884 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry,
 885                         const u8 *mac);
 886 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
 887                                  u16 entry,
 888                                  const struct ath9k_keyval *k,
 889                                  const u8 *mac,
 890                                  int xorKey);
 891 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
 892                             u32 setting);
 893 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
 894 bool ath9k_hw_intrpend(struct ath_hal *ah);
 895 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked);
 896 bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
 897                                 bool bIncTrigLevel);
 898 void ath9k_hw_procmibevent(struct ath_hal *ah,
 899                            const struct ath9k_node_stats *stats);
 900 bool ath9k_hw_setrxabort(struct ath_hal *ah, bool set);
 901 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode);
 902 bool ath9k_hw_phycounters(struct ath_hal *ah);
 903 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
 904 bool ath9k_hw_getcapability(struct ath_hal *ah,
 905                             enum ath9k_capability_type type,
 906                             u32 capability,
 907                             u32 *result);
 908 bool ath9k_hw_setcapability(struct ath_hal *ah,
 909                             enum ath9k_capability_type type,
 910                             u32 capability,
 911                             u32 setting,
 912                             int *status);
 913 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
 914 void ath9k_hw_getmac(struct ath_hal *ah, u8 *mac);
 915 void ath9k_hw_getbssidmask(struct ath_hal *ah, u8 *mask);
 916 bool ath9k_hw_setbssidmask(struct ath_hal *ah,
 917                            const u8 *mask);
 918 bool ath9k_hw_setpower(struct ath_hal *ah,
 919                        enum ath9k_power_mode mode);
 920 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah);
 921 u64 ath9k_hw_gettsf64(struct ath_hal *ah);
 922 u32 ath9k_hw_getdefantenna(struct ath_hal *ah);
 923 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us);
 924 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
 925                                enum ath9k_ant_setting settings,
 926                                struct ath9k_channel *chan,
 927                                u8 *tx_chainmask,
 928                                u8 *rx_chainmask,
 929                                u8 *antenna_cfgd);
 930 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna);
 931 int ath9k_hw_select_antconfig(struct ath_hal *ah,
 932                               u32 cfg);
 933 bool ath9k_hw_puttxbuf(struct ath_hal *ah, u32 q,
 934                        u32 txdp);
 935 bool ath9k_hw_txstart(struct ath_hal *ah, u32 q);
 936 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
 937                                  const struct ath9k_rate_table *rates,
 938                                  u32 frameLen, u16 rateix,
 939                                  bool shortPreamble);
 940 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
 941                                   struct ath_desc *lastds,
 942                                   u32 durUpdateEn, u32 rtsctsRate,
 943                                   u32 rtsctsDuration,
 944                                   struct ath9k_11n_rate_series series[],
 945                                   u32 nseries, u32 flags);
 946 void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
 947                                    struct ath_desc *ds,
 948                                    u32 burstDuration);
 949 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
 950 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
 951 bool ath9k_hw_resettxqueue(struct ath_hal *ah, u32 q);
 952 u32 ath9k_regd_get_ctl(struct ath_hal *ah, struct ath9k_channel *chan);
 953 u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
 954                                      struct ath9k_channel *chan);
 955 u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
 956 bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
 957                             struct ath9k_tx_queue_info *qinfo);
 958 bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
 959                             const struct ath9k_tx_queue_info *qinfo);
 960 struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah,
 961                                               const struct ath9k_channel *c);
 962 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
 963                             u32 pktLen, enum ath9k_pkt_type type,
 964                             u32 txPower, u32 keyIx,
 965                             enum ath9k_key_type keyType, u32 flags);
 966 bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
 967                          u32 segLen, bool firstSeg,
 968                          bool lastSeg,
 969                          const struct ath_desc *ds0);
 970 u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
 971                                         u32 *rxc_pcnt,
 972                                         u32 *rxf_pcnt,
 973                                         u32 *txf_pcnt);
 974 void ath9k_hw_dmaRegDump(struct ath_hal *ah);
 975 void ath9k_hw_beaconinit(struct ath_hal *ah,
 976                          u32 next_beacon, u32 beacon_period);
 977 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
 978                                     const struct ath9k_beacon_state *bs);
 979 bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
 980                           u32 size, u32 flags);
 981 void ath9k_hw_putrxbuf(struct ath_hal *ah, u32 rxdp);
 982 void ath9k_hw_rxena(struct ath_hal *ah);
 983 void ath9k_hw_setopmode(struct ath_hal *ah);
 984 bool ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac);
 985 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0,
 986                              u32 filter1);
 987 u32 ath9k_hw_getrxfilter(struct ath_hal *ah);
 988 void ath9k_hw_startpcureceive(struct ath_hal *ah);
 989 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
 990 bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
 991 int ath9k_hw_rxprocdesc(struct ath_hal *ah,
 992                         struct ath_desc *ds, u32 pa,
 993                         struct ath_desc *nds, u64 tsf);
 994 u32 ath9k_hw_gettxbuf(struct ath_hal *ah, u32 q);
 995 int ath9k_hw_txprocdesc(struct ath_hal *ah,
 996                         struct ath_desc *ds);
 997 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
 998                                  u32 numDelims);
 999 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
1000                                 u32 aggrLen);
1001 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1002 bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u32 q);
1003 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u32 *txqs);
1004 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1005 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
1006                                      struct ath_desc *ds, u32 vmf);
1007 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
1008 bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
1009 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
1010                           const struct ath9k_tx_queue_info *qinfo);
1011 u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
1012 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
1013 bool ath9k_hw_disable(struct ath_hal *ah);
1014 void ath9k_hw_rfdetach(struct ath_hal *ah);
1015 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
1016                                   struct ath9k_channel *chan,
1017                                   struct chan_centers *centers);
1018 bool ath9k_get_channel_edges(struct ath_hal *ah,
1019                              u16 flags, u16 *low,
1020                              u16 *high);
1021 #endif