2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/version.h>
21 #include <linux/autoconf.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/skbuff.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
30 #include <linux/tcp.h>
32 #include <linux/delay.h>
33 #include <linux/wait.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/sched.h>
37 #include <linux/list.h>
38 #include <asm/byteorder.h>
39 #include <linux/scatterlist.h>
41 #include <net/mac80211.h>
42 #include <linux/leds.h>
43 #include <linux/rfkill.h>
54 /* Macro to expand scalars to 64-bit objects */
56 #define ito64(x) (sizeof(x) == 8) ? \
57 (((unsigned long long int)(x)) & (0xff)) : \
59 (((unsigned long long int)(x)) & 0xffff) : \
60 ((sizeof(x) == 32) ? \
61 (((unsigned long long int)(x)) & 0xffffffff) : \
62 (unsigned long long int)(x))
64 /* increment with wrap-around */
65 #define INCR(_l, _sz) do { \
67 (_l) &= ((_sz) - 1); \
70 /* decrement with wrap-around */
71 #define DECR(_l, _sz) do { \
73 (_l) &= ((_sz) - 1); \
76 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
78 #define ASSERT(exp) do { \
79 if (unlikely(!(exp))) { \
84 #define TSF_TO_TU(_h,_l) \
85 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
88 #define memzero(_buf, _len) memset(_buf, 0, _len)
90 #define ATH9K_BH_STATUS_INTACT 0
91 #define ATH9K_BH_STATUS_CHANGE 1
93 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
95 static inline unsigned long get_timestamp(void)
97 return ((jiffies
/ HZ
) * 1000) + (jiffies
% HZ
) * (1000 / HZ
);
100 static const u8 ath_bcast_mac
[ETH_ALEN
] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
107 ATH_DBG_RESET
= 0x00000001,
108 ATH_DBG_PHY_IO
= 0x00000002,
109 ATH_DBG_REG_IO
= 0x00000004,
110 ATH_DBG_QUEUE
= 0x00000008,
111 ATH_DBG_EEPROM
= 0x00000010,
112 ATH_DBG_NF_CAL
= 0x00000020,
113 ATH_DBG_CALIBRATE
= 0x00000040,
114 ATH_DBG_CHANNEL
= 0x00000080,
115 ATH_DBG_INTERRUPT
= 0x00000100,
116 ATH_DBG_REGULATORY
= 0x00000200,
117 ATH_DBG_ANI
= 0x00000400,
118 ATH_DBG_POWER_MGMT
= 0x00000800,
119 ATH_DBG_XMIT
= 0x00001000,
120 ATH_DBG_BEACON
= 0x00002000,
121 ATH_DBG_RATE
= 0x00004000,
122 ATH_DBG_CONFIG
= 0x00008000,
123 ATH_DBG_KEYCACHE
= 0x00010000,
124 ATH_DBG_AGGR
= 0x00020000,
125 ATH_DBG_FATAL
= 0x00040000,
126 ATH_DBG_ANY
= 0xffffffff
129 #define DBG_DEFAULT (ATH_DBG_FATAL)
131 #define DPRINTF(sc, _m, _fmt, ...) do { \
132 if (sc->sc_debug & (_m)) \
133 printk(_fmt , ##__VA_ARGS__); \
136 /***************************/
137 /* Load-time Configuration */
138 /***************************/
140 /* Per-instance load-time (note: NOT run-time) configurations
141 * for Atheros Device */
145 u16 txpowlimit_override
;
146 u8 cabqReadytime
; /* Cabq Readytime % */
147 u8 swBeaconProcess
; /* Process received beacons in SW (vs HW) */
150 /***********************/
151 /* Chainmask Selection */
152 /***********************/
154 #define ATH_CHAINMASK_SEL_TIMEOUT 6000
155 /* Default - Number of last RSSI values that is used for
156 * chainmask selection */
157 #define ATH_CHAINMASK_SEL_RSSI_CNT 10
158 /* Means use 3x3 chainmask instead of configured chainmask */
159 #define ATH_CHAINMASK_SEL_3X3 7
160 /* Default - Rssi threshold below which we have to switch to 3x3 */
161 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
162 /* Default - Rssi threshold above which we have to switch to
163 * user configured values */
164 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
165 /* Struct to store the chainmask select related info */
166 struct ath_chainmask_sel
{
167 struct timer_list timer
;
168 int cur_tx_mask
; /* user configured or 3x3 */
169 int cur_rx_mask
; /* user configured or 3x3 */
171 u8 switch_allowed
:1, /* timer will set this */
175 int ath_chainmask_sel_logic(struct ath_softc
*sc
, struct ath_node
*an
);
176 void ath_update_chainmask(struct ath_softc
*sc
, int is_ht
);
178 /*************************/
179 /* Descriptor Management */
180 /*************************/
182 #define ATH_TXBUF_RESET(_bf) do { \
183 (_bf)->bf_status = 0; \
184 (_bf)->bf_lastbf = NULL; \
185 (_bf)->bf_lastfrm = NULL; \
186 (_bf)->bf_next = NULL; \
187 memzero(&((_bf)->bf_state), \
188 sizeof(struct ath_buf_state)); \
198 BUF_SHORT_PREAMBLE
= BIT(6),
201 BUF_AGGR_BURST
= BIT(9),
202 BUF_CALC_AIRTIME
= BIT(10),
205 struct ath_buf_state
{
206 int bfs_nframes
; /* # frames in aggregate */
207 u16 bfs_al
; /* length of aggregate */
208 u16 bfs_frmlen
; /* length of frame */
209 int bfs_seqno
; /* sequence number */
210 int bfs_tidno
; /* tid of this frame */
211 int bfs_retries
; /* current retries */
212 struct ath_rc_series bfs_rcs
[4]; /* rate series */
213 u32 bf_type
; /* BUF_* (enum buffer_type) */
214 /* key type use to encrypt this frame */
215 enum ath9k_key_type bfs_keytype
;
218 #define bf_nframes bf_state.bfs_nframes
219 #define bf_al bf_state.bfs_al
220 #define bf_frmlen bf_state.bfs_frmlen
221 #define bf_retries bf_state.bfs_retries
222 #define bf_seqno bf_state.bfs_seqno
223 #define bf_tidno bf_state.bfs_tidno
224 #define bf_rcs bf_state.bfs_rcs
225 #define bf_keytype bf_state.bfs_keytype
226 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
227 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
228 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
229 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
230 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
231 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
232 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
233 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
234 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
235 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
238 * Abstraction of a contiguous buffer to transmit/receive. There is only
239 * a single hw descriptor encapsulated here.
242 struct list_head list
;
243 struct list_head
*last
;
244 struct ath_buf
*bf_lastbf
; /* last buf of this unit (a frame or
246 struct ath_buf
*bf_lastfrm
; /* last buf of this frame */
247 struct ath_buf
*bf_next
; /* next subframe in the aggregate */
248 struct ath_buf
*bf_rifslast
; /* last buf for RIFS burst */
249 void *bf_mpdu
; /* enclosing frame structure */
250 void *bf_node
; /* pointer to the node */
251 struct ath_desc
*bf_desc
; /* virtual addr of desc */
252 dma_addr_t bf_daddr
; /* physical addr of desc */
253 dma_addr_t bf_buf_addr
; /* physical addr of data buffer */
255 u16 bf_flags
; /* tx descriptor flags */
256 struct ath_buf_state bf_state
; /* buffer state */
257 dma_addr_t bf_dmacontext
;
261 * reset the rx buffer.
262 * any new fields added to the athbuf and require
263 * reset need to be added to this macro.
264 * currently bf_status is the only one requires that
267 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
269 /* hw processing complete, desc processed by hal */
270 #define ATH_BUFSTATUS_DONE 0x00000001
271 /* hw processing complete, desc hold for hw */
272 #define ATH_BUFSTATUS_STALE 0x00000002
273 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
274 #define ATH_BUFSTATUS_FREE 0x00000004
276 /* DMA state for tx/rx descriptors */
280 struct ath_desc
*dd_desc
; /* descriptors */
281 dma_addr_t dd_desc_paddr
; /* physical addr of dd_desc */
282 u32 dd_desc_len
; /* size of dd_desc */
283 struct ath_buf
*dd_bufptr
; /* associated buffers */
284 dma_addr_t dd_dmacontext
;
287 /* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
289 struct ath_rx_context
{
290 struct ath_buf
*ctx_rxbuf
; /* associated ath_buf for rx */
292 #define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
294 int ath_descdma_setup(struct ath_softc
*sc
,
295 struct ath_descdma
*dd
,
296 struct list_head
*head
,
300 int ath_desc_alloc(struct ath_softc
*sc
);
301 void ath_desc_free(struct ath_softc
*sc
);
302 void ath_descdma_cleanup(struct ath_softc
*sc
,
303 struct ath_descdma
*dd
,
304 struct list_head
*head
);
310 #define ATH_MAX_ANTENNA 3
311 #define ATH_RXBUF 512
312 #define ATH_RX_TIMEOUT 40 /* 40 milliseconds */
313 #define WME_NUM_TID 16
314 #define IEEE80211_BAR_CTL_TID_M 0xF000 /* tid mask */
315 #define IEEE80211_BAR_CTL_TID_S 2 /* tid shift */
318 ATH_RX_NON_CONSUMED
= 0,
322 /* per frame rx status block */
323 struct ath_recv_status
{
324 u64 tsf
; /* mac tsf */
325 int8_t rssi
; /* RSSI (noise floor ajusted) */
326 int8_t rssictl
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
327 int8_t rssiextn
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
328 int8_t abs_rssi
; /* absolute RSSI */
329 u8 rateieee
; /* data rate received (IEEE rate code) */
330 u8 ratecode
; /* phy rate code */
331 int rateKbps
; /* data rate received (Kbps) */
332 int antenna
; /* rx antenna */
333 int flags
; /* status of associated skb */
334 #define ATH_RX_FCS_ERROR 0x01
335 #define ATH_RX_MIC_ERROR 0x02
336 #define ATH_RX_DECRYPT_ERROR 0x04
337 #define ATH_RX_RSSI_VALID 0x08
338 /* if any of ctl,extn chainrssis are valid */
339 #define ATH_RX_CHAIN_RSSI_VALID 0x10
340 /* if extn chain rssis are valid */
341 #define ATH_RX_RSSI_EXTN_VALID 0x20
342 /* set if 40Mhz, clear if 20Mhz */
343 #define ATH_RX_40MHZ 0x40
344 /* set if short GI, clear if full GI */
345 #define ATH_RX_SHORT_GI 0x80
349 struct sk_buff
*rx_wbuf
;
350 unsigned long rx_time
; /* system time when received */
351 struct ath_recv_status rx_status
; /* cached rx status */
354 /* Per-TID aggregate receiver state for a node */
357 struct ath_rxbuf
*rxbuf
; /* re-ordering buffer */
358 struct timer_list timer
;
360 int baw_head
; /* seq_next at head */
361 int baw_tail
; /* tail of block-ack window */
362 int seq_reset
; /* need to reset start sequence */
363 int addba_exchangecomplete
;
364 u16 seq_next
; /* next expected sequence */
365 u16 baw_size
; /* block-ack window size */
368 /* Per-node receiver aggregate state */
370 struct ath_arx_tid tid
[WME_NUM_TID
];
373 int ath_startrecv(struct ath_softc
*sc
);
374 bool ath_stoprecv(struct ath_softc
*sc
);
375 void ath_flushrecv(struct ath_softc
*sc
);
376 u32
ath_calcrxfilter(struct ath_softc
*sc
);
377 void ath_rx_node_init(struct ath_softc
*sc
, struct ath_node
*an
);
378 void ath_rx_node_free(struct ath_softc
*sc
, struct ath_node
*an
);
379 void ath_rx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
);
380 void ath_handle_rx_intr(struct ath_softc
*sc
);
381 int ath_rx_init(struct ath_softc
*sc
, int nbufs
);
382 void ath_rx_cleanup(struct ath_softc
*sc
);
383 int ath_rx_tasklet(struct ath_softc
*sc
, int flush
);
384 int ath_rx_input(struct ath_softc
*sc
,
385 struct ath_node
*node
,
388 struct ath_recv_status
*rx_status
,
389 enum ATH_RX_TYPE
*status
);
390 int _ath_rx_indicate(struct ath_softc
*sc
,
392 struct ath_recv_status
*status
,
394 int ath_rx_subframe(struct ath_node
*an
, struct sk_buff
*skb
,
395 struct ath_recv_status
*status
);
401 #define ATH_TXBUF 512
402 /* max number of transmit attempts (tries) */
403 #define ATH_TXMAXTRY 13
404 /* max number of 11n transmit attempts (tries) */
405 #define ATH_11N_TXMAXTRY 10
406 /* max number of tries for management and control frames */
407 #define ATH_MGT_TXMAXTRY 4
408 #define WME_BA_BMP_SIZE 64
409 #define WME_MAX_BA WME_BA_BMP_SIZE
410 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
411 #define TID_TO_WME_AC(_tid) \
412 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
413 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
414 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
418 /* Wireless Multimedia Extension Defines */
419 #define WME_AC_BE 0 /* best effort */
420 #define WME_AC_BK 1 /* background */
421 #define WME_AC_VI 2 /* video */
422 #define WME_AC_VO 3 /* voice */
427 ATH_SM_PWRSAV_STATIC
,
428 ATH_SM_PWRSAV_DYNAMIC
,
432 * Data transmit queue state. One of these exists for each
433 * hardware transmit queue. Packets sent to us from above
434 * are assigned to queues based on their priority. Not all
435 * devices support a complete set of hardware transmit queues.
436 * For those devices the array sc_ac2q will map multiple
437 * priorities to fewer hardware queues (typically all to one
441 u32 axq_qnum
; /* hardware q number */
442 u32
*axq_link
; /* link ptr in last TX desc */
443 struct list_head axq_q
; /* transmit queue */
445 unsigned long axq_lockflags
; /* intr state when must cli */
446 u32 axq_depth
; /* queue depth */
447 u8 axq_aggr_depth
; /* aggregates queued */
448 u32 axq_totalqueued
; /* total ever queued */
450 /* count to determine if descriptor should generate int on this txq. */
453 bool stopped
; /* Is mac80211 queue stopped ? */
454 struct ath_buf
*axq_linkbuf
; /* virtual addr of last buffer*/
456 /* first desc of the last descriptor that contains CTS */
457 struct ath_desc
*axq_lastdsWithCTS
;
459 /* final desc of the gating desc that determines whether
460 lastdsWithCTS has been DMA'ed or not */
461 struct ath_desc
*axq_gatingds
;
463 struct list_head axq_acq
;
466 /* per TID aggregate tx state for a destination */
468 struct list_head list
; /* round-robin tid entry */
469 struct list_head buf_q
; /* pending buffers */
471 struct ath_atx_ac
*ac
;
472 struct ath_buf
*tx_buf
[ATH_TID_MAX_BUFS
]; /* active tx frames */
477 int baw_head
; /* first un-acked tx buffer */
478 int baw_tail
; /* next unused tx buffer slot */
481 int cleanup_inprogress
;
482 u32 addba_exchangecomplete
:1;
483 int32_t addba_exchangeinprogress
;
484 int addba_exchangeattempts
;
487 /* per access-category aggregate tx state for a destination */
489 int sched
; /* dest-ac is scheduled */
490 int qnum
; /* H/W queue number associated
492 struct list_head list
; /* round-robin txq entry */
493 struct list_head tid_q
; /* queue of TIDs with buffers */
496 /* per dest tx state */
498 struct ath_atx_tid tid
[WME_NUM_TID
];
499 struct ath_atx_ac ac
[WME_NUM_AC
];
502 /* per-frame tx control block */
503 struct ath_tx_control
{
510 enum ath9k_pkt_type atype
;
511 enum ath9k_key_type keytype
;
520 struct ath_softc
*dev
;
521 dma_addr_t dmacontext
;
524 /* per frame tx status block */
525 struct ath_xmit_status
{
526 int retries
; /* number of retries to successufully
527 transmit this frame */
528 int flags
; /* status of transmit */
529 #define ATH_TX_ERROR 0x01
530 #define ATH_TX_XRETRY 0x02
531 #define ATH_TX_BAR 0x04
535 int rssi
; /* RSSI (noise floor ajusted) */
536 int rssictl
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
537 int rssiextn
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
538 int rateieee
; /* data rate xmitted (IEEE rate code) */
539 int rateKbps
; /* data rate xmitted (Kbps) */
540 int ratecode
; /* phy rate code */
541 int flags
; /* validity flags */
542 /* if any of ctl,extn chain rssis are valid */
543 #define ATH_TX_CHAIN_RSSI_VALID 0x01
544 /* if extn chain rssis are valid */
545 #define ATH_TX_RSSI_EXTN_VALID 0x02
546 u32 airtime
; /* time on air per final tx rate */
549 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
);
550 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
);
551 int ath_tx_setup(struct ath_softc
*sc
, int haltype
);
552 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
);
553 void ath_tx_draintxq(struct ath_softc
*sc
,
554 struct ath_txq
*txq
, bool retry_tx
);
555 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
);
556 void ath_tx_node_cleanup(struct ath_softc
*sc
,
557 struct ath_node
*an
, bool bh_flag
);
558 void ath_tx_node_free(struct ath_softc
*sc
, struct ath_node
*an
);
559 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
);
560 int ath_tx_init(struct ath_softc
*sc
, int nbufs
);
561 int ath_tx_cleanup(struct ath_softc
*sc
);
562 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
);
563 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
564 struct ath9k_tx_queue_info
*q
);
565 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
);
566 void ath_tx_tasklet(struct ath_softc
*sc
);
567 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
);
568 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
);
569 void ath_notify_txq_status(struct ath_softc
*sc
, u16 queue_depth
);
570 void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
571 struct ath_xmit_status
*tx_status
, struct ath_node
*an
);
572 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
);
574 /**********************/
575 /* Node / Aggregation */
576 /**********************/
578 /* indicates the node is clened up */
579 #define ATH_NODE_CLEAN 0x1
580 /* indicates the node is 80211 power save */
581 #define ATH_NODE_PWRSAVE 0x2
583 #define ADDBA_EXCHANGE_ATTEMPTS 10
584 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
585 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
586 /* number of delimiters for encryption padding */
587 #define ATH_AGGR_ENCRYPTDELIM 10
588 /* minimum h/w qdepth to be sustained to maximize aggregation */
589 #define ATH_AGGR_MIN_QDEPTH 2
590 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
591 #define IEEE80211_SEQ_SEQ_SHIFT 4
592 #define IEEE80211_SEQ_MAX 4096
593 #define IEEE80211_MIN_AMPDU_BUF 0x8
595 /* return whether a bit at index _n in bitmap _bm is set
596 * _sz is the size of the bitmap */
597 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
598 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
600 /* return block-ack bitmap index given sequence and starting sequence */
601 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
603 /* returns delimiter padding required given the packet length */
604 #define ATH_AGGR_GET_NDELIM(_len) \
605 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
606 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
608 #define BAW_WITHIN(_start, _bawsz, _seqno) \
609 ((((_seqno) - (_start)) & 4095) < (_bawsz))
611 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
612 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
613 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
614 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
616 enum ATH_AGGR_STATUS
{
624 enum ATH_AGGR_CHECK
{
627 AGGR_CLEANUP_PROGRESS
,
628 AGGR_EXCHANGE_PROGRESS
,
632 struct aggr_rifs_param
{
633 int param_max_frames
;
637 struct ath_rc_series
*param_rcs
;
640 /* Per-node aggregation state */
641 struct ath_node_aggr
{
642 struct ath_atx tx
; /* node transmit state */
643 struct ath_arx rx
; /* node receive state */
646 /* driver-specific node state */
648 struct list_head list
;
649 struct ath_softc
*an_sc
;
651 struct ath_chainmask_sel an_chainmask_sel
;
652 struct ath_node_aggr an_aggr
;
653 u8 an_smmode
; /* SM Power save mode */
655 u8 an_addr
[ETH_ALEN
];
658 void ath_tx_resume_tid(struct ath_softc
*sc
,
659 struct ath_atx_tid
*tid
);
660 enum ATH_AGGR_CHECK
ath_tx_aggr_check(struct ath_softc
*sc
,
661 struct ath_node
*an
, u8 tidno
);
662 void ath_tx_aggr_teardown(struct ath_softc
*sc
,
663 struct ath_node
*an
, u8 tidno
);
664 void ath_rx_aggr_teardown(struct ath_softc
*sc
,
665 struct ath_node
*an
, u8 tidno
);
666 int ath_rx_aggr_start(struct ath_softc
*sc
,
670 int ath_rx_aggr_stop(struct ath_softc
*sc
,
673 int ath_tx_aggr_start(struct ath_softc
*sc
,
677 int ath_tx_aggr_stop(struct ath_softc
*sc
,
680 void ath_newassoc(struct ath_softc
*sc
,
681 struct ath_node
*node
, int isnew
, int isuapsd
);
682 struct ath_node
*ath_node_attach(struct ath_softc
*sc
,
683 u8 addr
[ETH_ALEN
], int if_id
);
684 void ath_node_detach(struct ath_softc
*sc
, struct ath_node
*an
, bool bh_flag
);
685 struct ath_node
*ath_node_get(struct ath_softc
*sc
, u8 addr
[ETH_ALEN
]);
686 void ath_node_put(struct ath_softc
*sc
, struct ath_node
*an
, bool bh_flag
);
687 struct ath_node
*ath_node_find(struct ath_softc
*sc
, u8
*addr
);
689 /*******************/
690 /* Beacon Handling */
691 /*******************/
694 * Regardless of the number of beacons we stagger, (i.e. regardless of the
695 * number of BSSIDs) if a given beacon does not go out even after waiting this
696 * number of beacon intervals, the game's up.
698 #define BSTUCK_THRESH (9 * ATH_BCBUF)
699 #define ATH_BCBUF 4 /* number of beacon buffers */
700 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
701 #define ATH_DEFAULT_BMISS_LIMIT 10
702 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
704 /* beacon configuration */
705 struct ath_beacon_config
{
715 } u
; /* last received beacon/probe response timestamp of this BSS. */
718 void ath9k_beacon_tasklet(unsigned long data
);
719 void ath_beacon_config(struct ath_softc
*sc
, int if_id
);
720 int ath_beaconq_setup(struct ath_hal
*ah
);
721 int ath_beacon_alloc(struct ath_softc
*sc
, int if_id
);
722 void ath_bstuck_process(struct ath_softc
*sc
);
723 void ath_beacon_return(struct ath_softc
*sc
, struct ath_vap
*avp
);
724 void ath_beacon_sync(struct ath_softc
*sc
, int if_id
);
725 void ath_get_beaconconfig(struct ath_softc
*sc
,
727 struct ath_beacon_config
*conf
);
733 * Define the scheme that we select MAC address for multiple
734 * BSS on the same radio. The very first VAP will just use the MAC
735 * address from the EEPROM. For the next 3 VAPs, we set the
736 * U/L bit (bit 1) in MAC address, and use the next two bits as the
740 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
741 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
743 /* VAP configuration (from protocol layer) */
744 struct ath_vap_config
{
745 u32 av_fixed_rateset
;
746 u32 av_fixed_retryset
;
749 /* driver-specific vap state */
751 struct ieee80211_vif
*av_if_data
;
752 enum ath9k_opmode av_opmode
; /* VAP operational mode */
753 struct ath_buf
*av_bcbuf
; /* beacon buffer */
754 struct ath_tx_control av_btxctl
; /* txctl information for beacon */
755 int av_bslot
; /* beacon slot index */
756 struct ath_vap_config av_config
;/* vap configuration parameters*/
757 struct ath_rate_node
*rc_node
;
760 int ath_vap_attach(struct ath_softc
*sc
,
762 struct ieee80211_vif
*if_data
,
763 enum ath9k_opmode opmode
);
764 int ath_vap_detach(struct ath_softc
*sc
, int if_id
);
765 int ath_vap_config(struct ath_softc
*sc
,
766 int if_id
, struct ath_vap_config
*if_config
);
768 /*********************/
769 /* Antenna diversity */
770 /*********************/
772 #define ATH_ANT_DIV_MAX_CFG 2
773 #define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
774 #define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
776 enum ATH_ANT_DIV_STATE
{
778 ATH_ANT_DIV_SCAN
, /* evaluating antenna */
782 struct ath_softc
*antdiv_sc
;
784 enum ATH_ANT_DIV_STATE antdiv_state
;
785 u8 antdiv_num_antcfg
;
788 int32_t antdivf_rssitrig
;
789 int32_t antdiv_lastbrssi
[ATH_ANT_DIV_MAX_CFG
];
790 u64 antdiv_lastbtsf
[ATH_ANT_DIV_MAX_CFG
];
791 u64 antdiv_laststatetsf
;
792 u8 antdiv_bssid
[ETH_ALEN
];
795 void ath_slow_ant_div_init(struct ath_antdiv
*antdiv
,
796 struct ath_softc
*sc
, int32_t rssitrig
);
797 void ath_slow_ant_div_start(struct ath_antdiv
*antdiv
,
800 void ath_slow_ant_div_stop(struct ath_antdiv
*antdiv
);
801 void ath_slow_ant_div(struct ath_antdiv
*antdiv
,
802 struct ieee80211_hdr
*wh
,
803 struct ath_rx_status
*rx_stats
);
804 void ath_setdefantenna(void *sc
, u32 antenna
);
806 /********************/
808 /********************/
810 #define ATH_LED_PIN 1
820 struct ath_softc
*sc
;
821 struct led_classdev led_cdev
;
822 enum ath_led_type led_type
;
828 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
831 struct rfkill
*rfkill
;
832 struct delayed_work rfkill_poll
;
833 char rfkill_name
[32];
836 /********************/
837 /* Main driver core */
838 /********************/
841 * Default cache line size, in bytes.
842 * Used when PCI device not fully initialized by bootrom/BIOS
844 #define DEFAULT_CACHELINE 32
845 #define ATH_DEFAULT_NOISE_FLOOR -95
846 #define ATH_REGCLASSIDS_MAX 10
847 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
848 #define ATH_MAX_SW_RETRIES 10
849 #define ATH_CHAN_MAX 255
850 #define IEEE80211_WEP_NKID 4 /* number of key ids */
851 #define IEEE80211_RATE_VAL 0x7f
853 * The key cache is used for h/w cipher state and also for
854 * tracking station state such as the current tx antenna.
855 * We also setup a mapping table between key cache slot indices
856 * and station state to short-circuit node lookups on rx.
857 * Different parts have different size key caches. We handle
858 * up to ATH_KEYMAX entries (could dynamically allocate state).
860 #define ATH_KEYMAX 128 /* max key cache size we handle */
862 #define ATH_IF_ID_ANY 0xff
863 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
865 #define RSSI_LPF_THRESHOLD -20
866 #define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
867 #define ATH_RATE_DUMMY_MARKER 0
868 #define ATH_RSSI_LPF_LEN 10
869 #define ATH_RSSI_DUMMY_MARKER 0x127
871 #define ATH_EP_MUL(x, mul) ((x) * (mul))
872 #define ATH_EP_RND(x, mul) \
873 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
874 #define ATH_RSSI_OUT(x) \
875 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
876 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
877 #define ATH_RSSI_IN(x) \
878 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
879 #define ATH_LPF_RSSI(x, y, len) \
880 ((x != ATH_RSSI_DUMMY_MARKER) ? \
881 (((x) * ((len) - 1) + (y)) / (len)) : (y))
882 #define ATH_RSSI_LPF(x, y) do { \
883 if ((y) >= RSSI_LPF_THRESHOLD) \
884 x = ATH_LPF_RSSI((x), \
885 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
902 enum ath9k_ht_macmode tx_chan_width
;
908 #define SC_OP_INVALID BIT(0)
909 #define SC_OP_BEACONS BIT(1)
910 #define SC_OP_RXAGGR BIT(2)
911 #define SC_OP_TXAGGR BIT(3)
912 #define SC_OP_CHAINMASK_UPDATE BIT(4)
913 #define SC_OP_FULL_RESET BIT(5)
914 #define SC_OP_NO_RESET BIT(6)
915 #define SC_OP_PREAMBLE_SHORT BIT(7)
916 #define SC_OP_PROTECT_ENABLE BIT(8)
917 #define SC_OP_RXFLUSH BIT(9)
918 #define SC_OP_LED_ASSOCIATED BIT(10)
919 #define SC_OP_RFKILL_REGISTERED BIT(11)
920 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
921 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
924 struct ieee80211_hw
*hw
;
925 struct pci_dev
*pdev
;
926 struct tasklet_struct intr_tq
;
927 struct tasklet_struct bcon_tasklet
;
928 struct ath_config sc_config
;
929 struct ath_hal
*sc_ah
;
930 struct ath_rate_softc
*sc_rc
;
933 u8 sc_curbssid
[ETH_ALEN
];
934 u8 sc_myaddr
[ETH_ALEN
];
935 u8 sc_bssidmask
[ETH_ALEN
];
939 u32 sc_flags
; /* SC_OP_* */
940 unsigned int rx_filter
;
944 int sc_slotupdate
; /* slot to next advance fsm */
946 int sc_bslot
[ATH_BCBUF
];
949 enum ath9k_int sc_imask
;
950 enum wireless_mode sc_curmode
; /* current phy mode */
951 enum PROT_MODE sc_protmode
;
953 u8 sc_nbcnvaps
; /* # of vaps sending beacons */
954 u16 sc_nvaps
; /* # of active virtual ap's */
955 struct ath_vap
*sc_vaps
[ATH_BCBUF
];
958 u8 sc_defant
; /* current default antenna */
959 u8 sc_rxotherant
; /* rx's on non-default antenna */
961 struct ath9k_node_stats sc_halstats
; /* station-mode rssi stats */
962 struct list_head node_list
;
963 struct ath_ht_info sc_ht_info
;
964 enum ath9k_ht_extprotspacing sc_ht_extprotspacing
;
966 #ifdef CONFIG_SLOW_ANT_DIV
967 struct ath_antdiv sc_antdiv
;
970 OK
, /* no change needed */
971 UPDATE
, /* update pending */
972 COMMIT
/* beacon sent, commit change */
973 } sc_updateslot
; /* slot time update fsm */
976 u32 sc_keymax
; /* size of key cache */
977 DECLARE_BITMAP(sc_keymap
, ATH_KEYMAX
); /* key use bit map */
978 u8 sc_splitmic
; /* split TKIP MIC keys */
982 struct list_head sc_rxbuf
;
983 struct ath_descdma sc_rxdma
;
984 int sc_rxbufsize
; /* rx size based on mtu */
985 u32
*sc_rxlink
; /* link ptr in last RX desc */
988 struct list_head sc_txbuf
;
989 struct ath_txq sc_txq
[ATH9K_NUM_TX_QUEUES
];
990 struct ath_descdma sc_txdma
;
992 u32 sc_txintrperiod
; /* tx interrupt batching */
993 int sc_haltype2q
[ATH9K_WME_AC_VO
+1]; /* HAL WME AC -> h/w qnum */
994 u16 seq_no
; /* TX sequence number */
997 struct ath9k_tx_queue_info sc_beacon_qi
;
998 struct ath_descdma sc_bdma
;
999 struct ath_txq
*sc_cabq
;
1000 struct list_head sc_bbuf
;
1003 u32 ast_be_xmit
; /* beacons transmitted */
1006 struct ieee80211_rate rates
[IEEE80211_NUM_BANDS
][ATH_RATE_MAX
];
1007 const struct ath9k_rate_table
*sc_currates
;
1008 u8 sc_rixmap
[256]; /* IEEE to h/w rate table ix */
1009 u8 sc_protrix
; /* protection rate index */
1011 u32 rateKbps
; /* transfer rate in kbs */
1012 u8 ieeerate
; /* IEEE rate */
1013 } sc_hwmap
[256]; /* h/w rate ix mappings */
1016 struct ieee80211_channel channels
[IEEE80211_NUM_BANDS
][ATH_CHAN_MAX
];
1017 struct ieee80211_supported_band sbands
[IEEE80211_NUM_BANDS
];
1020 spinlock_t sc_rxflushlock
;
1021 spinlock_t sc_rxbuflock
;
1022 spinlock_t sc_txbuflock
;
1023 spinlock_t sc_resetlock
;
1024 spinlock_t node_lock
;
1027 struct ath_led radio_led
;
1028 struct ath_led assoc_led
;
1029 struct ath_led tx_led
;
1030 struct ath_led rx_led
;
1033 struct ath_rfkill rf_kill
;
1036 int ath_init(u16 devid
, struct ath_softc
*sc
);
1037 void ath_deinit(struct ath_softc
*sc
);
1038 int ath_open(struct ath_softc
*sc
, struct ath9k_channel
*initial_chan
);
1039 int ath_suspend(struct ath_softc
*sc
);
1040 irqreturn_t
ath_isr(int irq
, void *dev
);
1041 int ath_reset(struct ath_softc
*sc
, bool retry_tx
);
1042 int ath_set_channel(struct ath_softc
*sc
, struct ath9k_channel
*hchan
);
1044 /*********************/
1045 /* Utility Functions */
1046 /*********************/
1048 void ath_key_reset(struct ath_softc
*sc
, u16 keyix
, int freeslot
);
1049 int ath_keyset(struct ath_softc
*sc
,
1051 struct ath9k_keyval
*hk
,
1052 const u8 mac
[ETH_ALEN
]);
1053 int ath_get_hal_qnum(u16 queue
, struct ath_softc
*sc
);
1054 int ath_get_mac80211_qnum(u32 queue
, struct ath_softc
*sc
);
1055 void ath_setslottime(struct ath_softc
*sc
);
1056 void ath_update_txpow(struct ath_softc
*sc
);
1057 int ath_cabq_update(struct ath_softc
*);
1058 void ath_get_currentCountry(struct ath_softc
*sc
,
1059 struct ath9k_country_entry
*ctry
);
1060 u64
ath_extend_tsf(struct ath_softc
*sc
, u32 rstamp
);