2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/version.h>
21 #include <linux/autoconf.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/skbuff.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
30 #include <linux/tcp.h>
32 #include <linux/delay.h>
33 #include <linux/wait.h>
34 #include <linux/pci.h>
35 #include <linux/interrupt.h>
36 #include <linux/sched.h>
37 #include <linux/list.h>
38 #include <asm/byteorder.h>
39 #include <linux/scatterlist.h>
41 #include <net/mac80211.h>
42 #include <linux/leds.h>
43 #include <linux/rfkill.h>
54 /* Macro to expand scalars to 64-bit objects */
56 #define ito64(x) (sizeof(x) == 8) ? \
57 (((unsigned long long int)(x)) & (0xff)) : \
59 (((unsigned long long int)(x)) & 0xffff) : \
60 ((sizeof(x) == 32) ? \
61 (((unsigned long long int)(x)) & 0xffffffff) : \
62 (unsigned long long int)(x))
64 /* increment with wrap-around */
65 #define INCR(_l, _sz) do { \
67 (_l) &= ((_sz) - 1); \
70 /* decrement with wrap-around */
71 #define DECR(_l, _sz) do { \
73 (_l) &= ((_sz) - 1); \
76 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
78 #define ASSERT(exp) do { \
79 if (unlikely(!(exp))) { \
84 #define TSF_TO_TU(_h,_l) \
85 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
87 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
89 static inline unsigned long get_timestamp(void)
91 return ((jiffies
/ HZ
) * 1000) + (jiffies
% HZ
) * (1000 / HZ
);
94 static const u8 ath_bcast_mac
[ETH_ALEN
] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
101 ATH_DBG_RESET
= 0x00000001,
102 ATH_DBG_PHY_IO
= 0x00000002,
103 ATH_DBG_REG_IO
= 0x00000004,
104 ATH_DBG_QUEUE
= 0x00000008,
105 ATH_DBG_EEPROM
= 0x00000010,
106 ATH_DBG_NF_CAL
= 0x00000020,
107 ATH_DBG_CALIBRATE
= 0x00000040,
108 ATH_DBG_CHANNEL
= 0x00000080,
109 ATH_DBG_INTERRUPT
= 0x00000100,
110 ATH_DBG_REGULATORY
= 0x00000200,
111 ATH_DBG_ANI
= 0x00000400,
112 ATH_DBG_POWER_MGMT
= 0x00000800,
113 ATH_DBG_XMIT
= 0x00001000,
114 ATH_DBG_BEACON
= 0x00002000,
115 ATH_DBG_RATE
= 0x00004000,
116 ATH_DBG_CONFIG
= 0x00008000,
117 ATH_DBG_KEYCACHE
= 0x00010000,
118 ATH_DBG_AGGR
= 0x00020000,
119 ATH_DBG_FATAL
= 0x00040000,
120 ATH_DBG_ANY
= 0xffffffff
123 #define DBG_DEFAULT (ATH_DBG_FATAL)
125 #define DPRINTF(sc, _m, _fmt, ...) do { \
126 if (sc->sc_debug & (_m)) \
127 printk(_fmt , ##__VA_ARGS__); \
130 /***************************/
131 /* Load-time Configuration */
132 /***************************/
134 /* Per-instance load-time (note: NOT run-time) configurations
135 * for Atheros Device */
139 u16 txpowlimit_override
;
140 u8 cabqReadytime
; /* Cabq Readytime % */
141 u8 swBeaconProcess
; /* Process received beacons in SW (vs HW) */
144 /***********************/
145 /* Chainmask Selection */
146 /***********************/
148 #define ATH_CHAINMASK_SEL_TIMEOUT 6000
149 /* Default - Number of last RSSI values that is used for
150 * chainmask selection */
151 #define ATH_CHAINMASK_SEL_RSSI_CNT 10
152 /* Means use 3x3 chainmask instead of configured chainmask */
153 #define ATH_CHAINMASK_SEL_3X3 7
154 /* Default - Rssi threshold below which we have to switch to 3x3 */
155 #define ATH_CHAINMASK_SEL_UP_RSSI_THRES 20
156 /* Default - Rssi threshold above which we have to switch to
157 * user configured values */
158 #define ATH_CHAINMASK_SEL_DOWN_RSSI_THRES 35
159 /* Struct to store the chainmask select related info */
160 struct ath_chainmask_sel
{
161 struct timer_list timer
;
162 int cur_tx_mask
; /* user configured or 3x3 */
163 int cur_rx_mask
; /* user configured or 3x3 */
165 u8 switch_allowed
:1, /* timer will set this */
169 int ath_chainmask_sel_logic(struct ath_softc
*sc
, struct ath_node
*an
);
170 void ath_update_chainmask(struct ath_softc
*sc
, int is_ht
);
172 /*************************/
173 /* Descriptor Management */
174 /*************************/
176 #define ATH_TXBUF_RESET(_bf) do { \
177 (_bf)->bf_status = 0; \
178 (_bf)->bf_lastbf = NULL; \
179 (_bf)->bf_lastfrm = NULL; \
180 (_bf)->bf_next = NULL; \
181 memset(&((_bf)->bf_state), 0, \
182 sizeof(struct ath_buf_state)); \
192 BUF_SHORT_PREAMBLE
= BIT(6),
195 BUF_AGGR_BURST
= BIT(9),
196 BUF_CALC_AIRTIME
= BIT(10),
199 struct ath_buf_state
{
200 int bfs_nframes
; /* # frames in aggregate */
201 u16 bfs_al
; /* length of aggregate */
202 u16 bfs_frmlen
; /* length of frame */
203 int bfs_seqno
; /* sequence number */
204 int bfs_tidno
; /* tid of this frame */
205 int bfs_retries
; /* current retries */
206 struct ath_rc_series bfs_rcs
[4]; /* rate series */
207 u32 bf_type
; /* BUF_* (enum buffer_type) */
208 /* key type use to encrypt this frame */
210 enum ath9k_key_type bfs_keytype
;
213 #define bf_nframes bf_state.bfs_nframes
214 #define bf_al bf_state.bfs_al
215 #define bf_frmlen bf_state.bfs_frmlen
216 #define bf_retries bf_state.bfs_retries
217 #define bf_seqno bf_state.bfs_seqno
218 #define bf_tidno bf_state.bfs_tidno
219 #define bf_rcs bf_state.bfs_rcs
220 #define bf_keyix bf_state.bfs_keyix
221 #define bf_keytype bf_state.bfs_keytype
222 #define bf_isdata(bf) (bf->bf_state.bf_type & BUF_DATA)
223 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
224 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
225 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
226 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
227 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
228 #define bf_isshpreamble(bf) (bf->bf_state.bf_type & BUF_SHORT_PREAMBLE)
229 #define bf_isbar(bf) (bf->bf_state.bf_type & BUF_BAR)
230 #define bf_ispspoll(bf) (bf->bf_state.bf_type & BUF_PSPOLL)
231 #define bf_isaggrburst(bf) (bf->bf_state.bf_type & BUF_AGGR_BURST)
234 * Abstraction of a contiguous buffer to transmit/receive. There is only
235 * a single hw descriptor encapsulated here.
238 struct list_head list
;
239 struct list_head
*last
;
240 struct ath_buf
*bf_lastbf
; /* last buf of this unit (a frame or
242 struct ath_buf
*bf_lastfrm
; /* last buf of this frame */
243 struct ath_buf
*bf_next
; /* next subframe in the aggregate */
244 struct ath_buf
*bf_rifslast
; /* last buf for RIFS burst */
245 void *bf_mpdu
; /* enclosing frame structure */
246 struct ath_desc
*bf_desc
; /* virtual addr of desc */
247 dma_addr_t bf_daddr
; /* physical addr of desc */
248 dma_addr_t bf_buf_addr
; /* physical addr of data buffer */
250 u16 bf_flags
; /* tx descriptor flags */
251 struct ath_buf_state bf_state
; /* buffer state */
252 dma_addr_t bf_dmacontext
;
256 * reset the rx buffer.
257 * any new fields added to the athbuf and require
258 * reset need to be added to this macro.
259 * currently bf_status is the only one requires that
262 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
264 /* hw processing complete, desc processed by hal */
265 #define ATH_BUFSTATUS_DONE 0x00000001
266 /* hw processing complete, desc hold for hw */
267 #define ATH_BUFSTATUS_STALE 0x00000002
268 /* Rx-only: OS is done with this packet and it's ok to queued it to hw */
269 #define ATH_BUFSTATUS_FREE 0x00000004
271 /* DMA state for tx/rx descriptors */
275 struct ath_desc
*dd_desc
; /* descriptors */
276 dma_addr_t dd_desc_paddr
; /* physical addr of dd_desc */
277 u32 dd_desc_len
; /* size of dd_desc */
278 struct ath_buf
*dd_bufptr
; /* associated buffers */
279 dma_addr_t dd_dmacontext
;
282 /* Abstraction of a received RX MPDU/MMPDU, or a RX fragment */
284 struct ath_rx_context
{
285 struct ath_buf
*ctx_rxbuf
; /* associated ath_buf for rx */
287 #define ATH_RX_CONTEXT(skb) ((struct ath_rx_context *)skb->cb)
289 int ath_descdma_setup(struct ath_softc
*sc
,
290 struct ath_descdma
*dd
,
291 struct list_head
*head
,
295 int ath_desc_alloc(struct ath_softc
*sc
);
296 void ath_desc_free(struct ath_softc
*sc
);
297 void ath_descdma_cleanup(struct ath_softc
*sc
,
298 struct ath_descdma
*dd
,
299 struct list_head
*head
);
305 #define ATH_MAX_ANTENNA 3
306 #define ATH_RXBUF 512
307 #define WME_NUM_TID 16
309 /* per frame rx status block */
310 struct ath_recv_status
{
311 u64 tsf
; /* mac tsf */
312 int8_t rssi
; /* RSSI (noise floor ajusted) */
313 int8_t rssictl
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
314 int8_t rssiextn
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
315 int8_t abs_rssi
; /* absolute RSSI */
316 u8 rateieee
; /* data rate received (IEEE rate code) */
317 u8 ratecode
; /* phy rate code */
318 int rateKbps
; /* data rate received (Kbps) */
319 int antenna
; /* rx antenna */
320 int flags
; /* status of associated skb */
321 #define ATH_RX_FCS_ERROR 0x01
322 #define ATH_RX_MIC_ERROR 0x02
323 #define ATH_RX_DECRYPT_ERROR 0x04
324 #define ATH_RX_RSSI_VALID 0x08
325 /* if any of ctl,extn chainrssis are valid */
326 #define ATH_RX_CHAIN_RSSI_VALID 0x10
327 /* if extn chain rssis are valid */
328 #define ATH_RX_RSSI_EXTN_VALID 0x20
329 /* set if 40Mhz, clear if 20Mhz */
330 #define ATH_RX_40MHZ 0x40
331 /* set if short GI, clear if full GI */
332 #define ATH_RX_SHORT_GI 0x80
336 struct sk_buff
*rx_wbuf
;
337 unsigned long rx_time
; /* system time when received */
338 struct ath_recv_status rx_status
; /* cached rx status */
341 int ath_startrecv(struct ath_softc
*sc
);
342 bool ath_stoprecv(struct ath_softc
*sc
);
343 void ath_flushrecv(struct ath_softc
*sc
);
344 u32
ath_calcrxfilter(struct ath_softc
*sc
);
345 void ath_handle_rx_intr(struct ath_softc
*sc
);
346 int ath_rx_init(struct ath_softc
*sc
, int nbufs
);
347 void ath_rx_cleanup(struct ath_softc
*sc
);
348 int ath_rx_tasklet(struct ath_softc
*sc
, int flush
);
349 int _ath_rx_indicate(struct ath_softc
*sc
,
351 struct ath_recv_status
*status
,
357 #define ATH_TXBUF 512
358 /* max number of transmit attempts (tries) */
359 #define ATH_TXMAXTRY 13
360 /* max number of 11n transmit attempts (tries) */
361 #define ATH_11N_TXMAXTRY 10
362 /* max number of tries for management and control frames */
363 #define ATH_MGT_TXMAXTRY 4
364 #define WME_BA_BMP_SIZE 64
365 #define WME_MAX_BA WME_BA_BMP_SIZE
366 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
367 #define TID_TO_WME_AC(_tid) \
368 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
369 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
370 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
374 /* Wireless Multimedia Extension Defines */
375 #define WME_AC_BE 0 /* best effort */
376 #define WME_AC_BK 1 /* background */
377 #define WME_AC_VI 2 /* video */
378 #define WME_AC_VO 3 /* voice */
382 * Data transmit queue state. One of these exists for each
383 * hardware transmit queue. Packets sent to us from above
384 * are assigned to queues based on their priority. Not all
385 * devices support a complete set of hardware transmit queues.
386 * For those devices the array sc_ac2q will map multiple
387 * priorities to fewer hardware queues (typically all to one
391 u32 axq_qnum
; /* hardware q number */
392 u32
*axq_link
; /* link ptr in last TX desc */
393 struct list_head axq_q
; /* transmit queue */
395 unsigned long axq_lockflags
; /* intr state when must cli */
396 u32 axq_depth
; /* queue depth */
397 u8 axq_aggr_depth
; /* aggregates queued */
398 u32 axq_totalqueued
; /* total ever queued */
400 bool stopped
; /* Is mac80211 queue stopped ? */
401 struct ath_buf
*axq_linkbuf
; /* virtual addr of last buffer*/
403 /* first desc of the last descriptor that contains CTS */
404 struct ath_desc
*axq_lastdsWithCTS
;
406 /* final desc of the gating desc that determines whether
407 lastdsWithCTS has been DMA'ed or not */
408 struct ath_desc
*axq_gatingds
;
410 struct list_head axq_acq
;
413 #define AGGR_CLEANUP BIT(1)
414 #define AGGR_ADDBA_COMPLETE BIT(2)
415 #define AGGR_ADDBA_PROGRESS BIT(3)
417 /* per TID aggregate tx state for a destination */
419 struct list_head list
; /* round-robin tid entry */
420 struct list_head buf_q
; /* pending buffers */
422 struct ath_atx_ac
*ac
;
423 struct ath_buf
*tx_buf
[ATH_TID_MAX_BUFS
]; /* active tx frames */
428 int baw_head
; /* first un-acked tx buffer */
429 int baw_tail
; /* next unused tx buffer slot */
433 int addba_exchangeattempts
;
436 /* per access-category aggregate tx state for a destination */
438 int sched
; /* dest-ac is scheduled */
439 int qnum
; /* H/W queue number associated
441 struct list_head list
; /* round-robin txq entry */
442 struct list_head tid_q
; /* queue of TIDs with buffers */
445 /* per dest tx state */
447 struct ath_atx_tid tid
[WME_NUM_TID
];
448 struct ath_atx_ac ac
[WME_NUM_AC
];
451 /* per-frame tx control block */
452 struct ath_tx_control
{
457 /* per frame tx status block */
458 struct ath_xmit_status
{
459 int retries
; /* number of retries to successufully
460 transmit this frame */
461 int flags
; /* status of transmit */
462 #define ATH_TX_ERROR 0x01
463 #define ATH_TX_XRETRY 0x02
464 #define ATH_TX_BAR 0x04
468 int rssi
; /* RSSI (noise floor ajusted) */
469 int rssictl
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
470 int rssiextn
[ATH_MAX_ANTENNA
]; /* RSSI (noise floor ajusted) */
471 int rateieee
; /* data rate xmitted (IEEE rate code) */
472 int rateKbps
; /* data rate xmitted (Kbps) */
473 int ratecode
; /* phy rate code */
474 int flags
; /* validity flags */
475 /* if any of ctl,extn chain rssis are valid */
476 #define ATH_TX_CHAIN_RSSI_VALID 0x01
477 /* if extn chain rssis are valid */
478 #define ATH_TX_RSSI_EXTN_VALID 0x02
479 u32 airtime
; /* time on air per final tx rate */
482 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
);
483 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
);
484 int ath_tx_setup(struct ath_softc
*sc
, int haltype
);
485 void ath_draintxq(struct ath_softc
*sc
, bool retry_tx
);
486 void ath_tx_draintxq(struct ath_softc
*sc
,
487 struct ath_txq
*txq
, bool retry_tx
);
488 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
);
489 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
);
490 void ath_tx_node_free(struct ath_softc
*sc
, struct ath_node
*an
);
491 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
);
492 int ath_tx_init(struct ath_softc
*sc
, int nbufs
);
493 int ath_tx_cleanup(struct ath_softc
*sc
);
494 int ath_tx_get_qnum(struct ath_softc
*sc
, int qtype
, int haltype
);
495 struct ath_txq
*ath_test_get_txq(struct ath_softc
*sc
, struct sk_buff
*skb
);
496 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
497 struct ath9k_tx_queue_info
*q
);
498 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
,
499 struct ath_tx_control
*txctl
);
500 void ath_tx_tasklet(struct ath_softc
*sc
);
501 u32
ath_txq_depth(struct ath_softc
*sc
, int qnum
);
502 u32
ath_txq_aggr_depth(struct ath_softc
*sc
, int qnum
);
503 void ath_notify_txq_status(struct ath_softc
*sc
, u16 queue_depth
);
504 void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
505 struct ath_xmit_status
*tx_status
);
506 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
);
508 /**********************/
509 /* Node / Aggregation */
510 /**********************/
512 #define ADDBA_EXCHANGE_ATTEMPTS 10
513 #define ATH_AGGR_DELIM_SZ 4 /* delimiter size */
514 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
515 /* number of delimiters for encryption padding */
516 #define ATH_AGGR_ENCRYPTDELIM 10
517 /* minimum h/w qdepth to be sustained to maximize aggregation */
518 #define ATH_AGGR_MIN_QDEPTH 2
519 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
520 #define IEEE80211_SEQ_SEQ_SHIFT 4
521 #define IEEE80211_SEQ_MAX 4096
522 #define IEEE80211_MIN_AMPDU_BUF 0x8
523 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
525 /* return whether a bit at index _n in bitmap _bm is set
526 * _sz is the size of the bitmap */
527 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
528 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
530 /* return block-ack bitmap index given sequence and starting sequence */
531 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
533 /* returns delimiter padding required given the packet length */
534 #define ATH_AGGR_GET_NDELIM(_len) \
535 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
536 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
538 #define BAW_WITHIN(_start, _bawsz, _seqno) \
539 ((((_seqno) - (_start)) & 4095) < (_bawsz))
541 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
542 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
543 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
544 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->an_aggr.tx.tid[(_tidno)])
546 enum ATH_AGGR_STATUS
{
554 struct aggr_rifs_param
{
555 int param_max_frames
;
559 struct ath_rc_series
*param_rcs
;
562 /* Per-node aggregation state */
563 struct ath_node_aggr
{
564 struct ath_atx tx
; /* node transmit state */
567 /* driver-specific node state */
569 struct ath_softc
*an_sc
;
570 struct ath_chainmask_sel an_chainmask_sel
;
571 struct ath_node_aggr an_aggr
;
576 void ath_tx_resume_tid(struct ath_softc
*sc
,
577 struct ath_atx_tid
*tid
);
578 bool ath_tx_aggr_check(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
);
579 void ath_tx_aggr_teardown(struct ath_softc
*sc
,
580 struct ath_node
*an
, u8 tidno
);
581 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
583 int ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
);
584 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
);
585 void ath_newassoc(struct ath_softc
*sc
,
586 struct ath_node
*node
, int isnew
, int isuapsd
);
587 void ath_node_attach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
);
588 void ath_node_detach(struct ath_softc
*sc
, struct ieee80211_sta
*sta
);
590 /*******************/
591 /* Beacon Handling */
592 /*******************/
595 * Regardless of the number of beacons we stagger, (i.e. regardless of the
596 * number of BSSIDs) if a given beacon does not go out even after waiting this
597 * number of beacon intervals, the game's up.
599 #define BSTUCK_THRESH (9 * ATH_BCBUF)
600 #define ATH_BCBUF 4 /* number of beacon buffers */
601 #define ATH_DEFAULT_BINTVAL 100 /* default beacon interval in TU */
602 #define ATH_DEFAULT_BMISS_LIMIT 10
603 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
605 /* beacon configuration */
606 struct ath_beacon_config
{
616 } u
; /* last received beacon/probe response timestamp of this BSS. */
619 void ath9k_beacon_tasklet(unsigned long data
);
620 void ath_beacon_config(struct ath_softc
*sc
, int if_id
);
621 int ath_beaconq_setup(struct ath_hal
*ah
);
622 int ath_beacon_alloc(struct ath_softc
*sc
, int if_id
);
623 void ath_bstuck_process(struct ath_softc
*sc
);
624 void ath_beacon_return(struct ath_softc
*sc
, struct ath_vap
*avp
);
625 void ath_beacon_sync(struct ath_softc
*sc
, int if_id
);
626 void ath_get_beaconconfig(struct ath_softc
*sc
,
628 struct ath_beacon_config
*conf
);
634 * Define the scheme that we select MAC address for multiple
635 * BSS on the same radio. The very first VAP will just use the MAC
636 * address from the EEPROM. For the next 3 VAPs, we set the
637 * U/L bit (bit 1) in MAC address, and use the next two bits as the
641 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
642 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
644 /* VAP configuration (from protocol layer) */
645 struct ath_vap_config
{
646 u32 av_fixed_rateset
;
647 u32 av_fixed_retryset
;
650 /* driver-specific vap state */
652 int av_bslot
; /* beacon slot index */
653 enum ath9k_opmode av_opmode
; /* VAP operational mode */
654 struct ath_buf
*av_bcbuf
; /* beacon buffer */
655 struct ath_tx_control av_btxctl
; /* txctl information for beacon */
656 struct ath_vap_config av_config
;/* vap configuration parameters*/
657 struct ath_rate_node
*rc_node
;
660 /*********************/
661 /* Antenna diversity */
662 /*********************/
664 #define ATH_ANT_DIV_MAX_CFG 2
665 #define ATH_ANT_DIV_MIN_IDLE_US 1000000 /* us */
666 #define ATH_ANT_DIV_MIN_SCAN_US 50000 /* us */
668 enum ATH_ANT_DIV_STATE
{
670 ATH_ANT_DIV_SCAN
, /* evaluating antenna */
674 struct ath_softc
*antdiv_sc
;
676 enum ATH_ANT_DIV_STATE antdiv_state
;
677 u8 antdiv_num_antcfg
;
680 int32_t antdivf_rssitrig
;
681 int32_t antdiv_lastbrssi
[ATH_ANT_DIV_MAX_CFG
];
682 u64 antdiv_lastbtsf
[ATH_ANT_DIV_MAX_CFG
];
683 u64 antdiv_laststatetsf
;
684 u8 antdiv_bssid
[ETH_ALEN
];
687 void ath_slow_ant_div_init(struct ath_antdiv
*antdiv
,
688 struct ath_softc
*sc
, int32_t rssitrig
);
689 void ath_slow_ant_div_start(struct ath_antdiv
*antdiv
,
692 void ath_slow_ant_div_stop(struct ath_antdiv
*antdiv
);
693 void ath_slow_ant_div(struct ath_antdiv
*antdiv
,
694 struct ieee80211_hdr
*wh
,
695 struct ath_rx_status
*rx_stats
);
696 void ath_setdefantenna(void *sc
, u32 antenna
);
702 /* ANI values for STA only.
703 FIXME: Add appropriate values for AP later */
705 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
706 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
707 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
708 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
712 int16_t sc_noise_floor
;
713 unsigned int sc_longcal_timer
;
714 unsigned int sc_shortcal_timer
;
715 unsigned int sc_resetcal_timer
;
716 unsigned int sc_checkani_timer
;
717 struct timer_list timer
;
720 /********************/
722 /********************/
724 #define ATH_LED_PIN 1
734 struct ath_softc
*sc
;
735 struct led_classdev led_cdev
;
736 enum ath_led_type led_type
;
742 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
745 struct rfkill
*rfkill
;
746 struct delayed_work rfkill_poll
;
747 char rfkill_name
[32];
750 /********************/
751 /* Main driver core */
752 /********************/
755 * Default cache line size, in bytes.
756 * Used when PCI device not fully initialized by bootrom/BIOS
758 #define DEFAULT_CACHELINE 32
759 #define ATH_DEFAULT_NOISE_FLOOR -95
760 #define ATH_REGCLASSIDS_MAX 10
761 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
762 #define ATH_MAX_SW_RETRIES 10
763 #define ATH_CHAN_MAX 255
764 #define IEEE80211_WEP_NKID 4 /* number of key ids */
765 #define IEEE80211_RATE_VAL 0x7f
767 * The key cache is used for h/w cipher state and also for
768 * tracking station state such as the current tx antenna.
769 * We also setup a mapping table between key cache slot indices
770 * and station state to short-circuit node lookups on rx.
771 * Different parts have different size key caches. We handle
772 * up to ATH_KEYMAX entries (could dynamically allocate state).
774 #define ATH_KEYMAX 128 /* max key cache size we handle */
776 #define ATH_IF_ID_ANY 0xff
777 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
779 #define RSSI_LPF_THRESHOLD -20
780 #define ATH_RSSI_EP_MULTIPLIER (1<<7) /* pow2 to optimize out * and / */
781 #define ATH_RATE_DUMMY_MARKER 0
782 #define ATH_RSSI_LPF_LEN 10
783 #define ATH_RSSI_DUMMY_MARKER 0x127
785 #define ATH_EP_MUL(x, mul) ((x) * (mul))
786 #define ATH_EP_RND(x, mul) \
787 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
788 #define ATH_RSSI_OUT(x) \
789 (((x) != ATH_RSSI_DUMMY_MARKER) ? \
790 (ATH_EP_RND((x), ATH_RSSI_EP_MULTIPLIER)) : ATH_RSSI_DUMMY_MARKER)
791 #define ATH_RSSI_IN(x) \
792 (ATH_EP_MUL((x), ATH_RSSI_EP_MULTIPLIER))
793 #define ATH_LPF_RSSI(x, y, len) \
794 ((x != ATH_RSSI_DUMMY_MARKER) ? \
795 (((x) * ((len) - 1) + (y)) / (len)) : (y))
796 #define ATH_RSSI_LPF(x, y) do { \
797 if ((y) >= RSSI_LPF_THRESHOLD) \
798 x = ATH_LPF_RSSI((x), \
799 ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
816 enum ath9k_ht_macmode tx_chan_width
;
820 #define SC_OP_INVALID BIT(0)
821 #define SC_OP_BEACONS BIT(1)
822 #define SC_OP_RXAGGR BIT(2)
823 #define SC_OP_TXAGGR BIT(3)
824 #define SC_OP_CHAINMASK_UPDATE BIT(4)
825 #define SC_OP_FULL_RESET BIT(5)
826 #define SC_OP_NO_RESET BIT(6)
827 #define SC_OP_PREAMBLE_SHORT BIT(7)
828 #define SC_OP_PROTECT_ENABLE BIT(8)
829 #define SC_OP_RXFLUSH BIT(9)
830 #define SC_OP_LED_ASSOCIATED BIT(10)
831 #define SC_OP_RFKILL_REGISTERED BIT(11)
832 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
833 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
836 struct ieee80211_hw
*hw
;
837 struct pci_dev
*pdev
;
838 struct tasklet_struct intr_tq
;
839 struct tasklet_struct bcon_tasklet
;
840 struct ath_config sc_config
;
841 struct ath_hal
*sc_ah
;
842 struct ath_rate_softc
*sc_rc
;
845 u8 sc_curbssid
[ETH_ALEN
];
846 u8 sc_myaddr
[ETH_ALEN
];
847 u8 sc_bssidmask
[ETH_ALEN
];
851 u32 sc_flags
; /* SC_OP_* */
852 unsigned int rx_filter
;
856 int sc_slotupdate
; /* slot to next advance fsm */
858 int sc_bslot
[ATH_BCBUF
];
861 enum ath9k_int sc_imask
;
862 enum wireless_mode sc_curmode
; /* current phy mode */
863 enum PROT_MODE sc_protmode
;
865 u8 sc_nbcnvaps
; /* # of vaps sending beacons */
866 u16 sc_nvaps
; /* # of active virtual ap's */
867 struct ieee80211_vif
*sc_vaps
[ATH_BCBUF
];
870 u8 sc_defant
; /* current default antenna */
871 u8 sc_rxotherant
; /* rx's on non-default antenna */
873 struct ath9k_node_stats sc_halstats
; /* station-mode rssi stats */
874 struct ath_ht_info sc_ht_info
;
875 enum ath9k_ht_extprotspacing sc_ht_extprotspacing
;
877 #ifdef CONFIG_SLOW_ANT_DIV
878 struct ath_antdiv sc_antdiv
;
881 OK
, /* no change needed */
882 UPDATE
, /* update pending */
883 COMMIT
/* beacon sent, commit change */
884 } sc_updateslot
; /* slot time update fsm */
887 u32 sc_keymax
; /* size of key cache */
888 DECLARE_BITMAP(sc_keymap
, ATH_KEYMAX
); /* key use bit map */
889 u8 sc_splitmic
; /* split TKIP MIC keys */
892 struct list_head sc_rxbuf
;
893 struct ath_descdma sc_rxdma
;
894 int sc_rxbufsize
; /* rx size based on mtu */
895 u32
*sc_rxlink
; /* link ptr in last RX desc */
898 struct list_head sc_txbuf
;
899 struct ath_txq sc_txq
[ATH9K_NUM_TX_QUEUES
];
900 struct ath_descdma sc_txdma
;
902 int sc_haltype2q
[ATH9K_WME_AC_VO
+1]; /* HAL WME AC -> h/w qnum */
903 u16 seq_no
; /* TX sequence number */
906 struct ath9k_tx_queue_info sc_beacon_qi
;
907 struct ath_descdma sc_bdma
;
908 struct ath_txq
*sc_cabq
;
909 struct list_head sc_bbuf
;
912 u32 ast_be_xmit
; /* beacons transmitted */
916 struct ieee80211_rate rates
[IEEE80211_NUM_BANDS
][ATH_RATE_MAX
];
917 const struct ath9k_rate_table
*sc_currates
;
918 u8 sc_rixmap
[256]; /* IEEE to h/w rate table ix */
919 u8 sc_protrix
; /* protection rate index */
921 u32 rateKbps
; /* transfer rate in kbs */
922 u8 ieeerate
; /* IEEE rate */
923 } sc_hwmap
[256]; /* h/w rate ix mappings */
926 struct ieee80211_channel channels
[IEEE80211_NUM_BANDS
][ATH_CHAN_MAX
];
927 struct ieee80211_supported_band sbands
[IEEE80211_NUM_BANDS
];
930 spinlock_t sc_rxflushlock
;
931 spinlock_t sc_rxbuflock
;
932 spinlock_t sc_txbuflock
;
933 spinlock_t sc_resetlock
;
936 struct ath_led radio_led
;
937 struct ath_led assoc_led
;
938 struct ath_led tx_led
;
939 struct ath_led rx_led
;
942 struct ath_rfkill rf_kill
;
945 struct ath_ani sc_ani
;
948 int ath_init(u16 devid
, struct ath_softc
*sc
);
949 int ath_open(struct ath_softc
*sc
, struct ath9k_channel
*initial_chan
);
950 void ath_stop(struct ath_softc
*sc
);
951 irqreturn_t
ath_isr(int irq
, void *dev
);
952 int ath_reset(struct ath_softc
*sc
, bool retry_tx
);
953 int ath_set_channel(struct ath_softc
*sc
, struct ath9k_channel
*hchan
);
955 /*********************/
956 /* Utility Functions */
957 /*********************/
959 void ath_key_reset(struct ath_softc
*sc
, u16 keyix
, int freeslot
);
960 int ath_keyset(struct ath_softc
*sc
,
962 struct ath9k_keyval
*hk
,
963 const u8 mac
[ETH_ALEN
]);
964 int ath_get_hal_qnum(u16 queue
, struct ath_softc
*sc
);
965 int ath_get_mac80211_qnum(u32 queue
, struct ath_softc
*sc
);
966 void ath_setslottime(struct ath_softc
*sc
);
967 void ath_update_txpow(struct ath_softc
*sc
);
968 int ath_cabq_update(struct ath_softc
*);
969 u64
ath_extend_tsf(struct ath_softc
*sc
, u32 rstamp
);