]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/net/wireless/ath9k/eeprom.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath9k / eeprom.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "ath9k.h"
18
19 static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah,
20 u32 reg, u32 mask,
21 u32 shift, u32 val)
22 {
23 u32 regVal;
24
25 regVal = REG_READ(ah, reg) & ~mask;
26 regVal |= (val << shift) & mask;
27
28 REG_WRITE(ah, reg, regVal);
29
30 if (ah->config.analog_shiftreg)
31 udelay(100);
32
33 return;
34 }
35
36 static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
37 {
38
39 if (fbin == AR5416_BCHAN_UNUSED)
40 return fbin;
41
42 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
43 }
44
45 static inline int16_t ath9k_hw_interpolate(u16 target,
46 u16 srcLeft, u16 srcRight,
47 int16_t targetLeft,
48 int16_t targetRight)
49 {
50 int16_t rv;
51
52 if (srcRight == srcLeft) {
53 rv = targetLeft;
54 } else {
55 rv = (int16_t) (((target - srcLeft) * targetRight +
56 (srcRight - target) * targetLeft) /
57 (srcRight - srcLeft));
58 }
59 return rv;
60 }
61
62 static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList,
63 u16 listSize, u16 *indexL,
64 u16 *indexR)
65 {
66 u16 i;
67
68 if (target <= pList[0]) {
69 *indexL = *indexR = 0;
70 return true;
71 }
72 if (target >= pList[listSize - 1]) {
73 *indexL = *indexR = (u16) (listSize - 1);
74 return true;
75 }
76
77 for (i = 0; i < listSize - 1; i++) {
78 if (pList[i] == target) {
79 *indexL = *indexR = i;
80 return true;
81 }
82 if (target < pList[i + 1]) {
83 *indexL = i;
84 *indexR = (u16) (i + 1);
85 return false;
86 }
87 }
88 return false;
89 }
90
91 static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
92 {
93 struct ath_softc *sc = ah->ah_sc;
94
95 return sc->bus_ops->eeprom_read(ah, off, data);
96 }
97
98 static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
99 u8 *pVpdList, u16 numIntercepts,
100 u8 *pRetVpdList)
101 {
102 u16 i, k;
103 u8 currPwr = pwrMin;
104 u16 idxL = 0, idxR = 0;
105
106 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
107 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
108 numIntercepts, &(idxL),
109 &(idxR));
110 if (idxR < 1)
111 idxR = 1;
112 if (idxL == numIntercepts - 1)
113 idxL = (u16) (numIntercepts - 2);
114 if (pPwrList[idxL] == pPwrList[idxR])
115 k = pVpdList[idxL];
116 else
117 k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
118 (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
119 (pPwrList[idxR] - pPwrList[idxL]));
120 pRetVpdList[i] = (u8) k;
121 currPwr += 2;
122 }
123
124 return true;
125 }
126
127 static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
128 struct ath9k_channel *chan,
129 struct cal_target_power_leg *powInfo,
130 u16 numChannels,
131 struct cal_target_power_leg *pNewPower,
132 u16 numRates, bool isExtTarget)
133 {
134 struct chan_centers centers;
135 u16 clo, chi;
136 int i;
137 int matchIndex = -1, lowIndex = -1;
138 u16 freq;
139
140 ath9k_hw_get_channel_centers(ah, chan, &centers);
141 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
142
143 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
144 IS_CHAN_2GHZ(chan))) {
145 matchIndex = 0;
146 } else {
147 for (i = 0; (i < numChannels) &&
148 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
149 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
150 IS_CHAN_2GHZ(chan))) {
151 matchIndex = i;
152 break;
153 } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
154 IS_CHAN_2GHZ(chan))) &&
155 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
156 IS_CHAN_2GHZ(chan)))) {
157 lowIndex = i - 1;
158 break;
159 }
160 }
161 if ((matchIndex == -1) && (lowIndex == -1))
162 matchIndex = i - 1;
163 }
164
165 if (matchIndex != -1) {
166 *pNewPower = powInfo[matchIndex];
167 } else {
168 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
169 IS_CHAN_2GHZ(chan));
170 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
171 IS_CHAN_2GHZ(chan));
172
173 for (i = 0; i < numRates; i++) {
174 pNewPower->tPow2x[i] =
175 (u8)ath9k_hw_interpolate(freq, clo, chi,
176 powInfo[lowIndex].tPow2x[i],
177 powInfo[lowIndex + 1].tPow2x[i]);
178 }
179 }
180 }
181
182 static void ath9k_get_txgain_index(struct ath_hw *ah,
183 struct ath9k_channel *chan,
184 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
185 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
186 {
187 u8 pcdac, i = 0;
188 u16 idxL = 0, idxR = 0, numPiers;
189 bool match;
190 struct chan_centers centers;
191
192 ath9k_hw_get_channel_centers(ah, chan, &centers);
193
194 for (numPiers = 0; numPiers < availPiers; numPiers++)
195 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
196 break;
197
198 match = ath9k_hw_get_lower_upper_index(
199 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
200 calChans, numPiers, &idxL, &idxR);
201 if (match) {
202 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
203 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
204 } else {
205 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
206 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
207 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
208 }
209
210 while (pcdac > ah->originalGain[i] &&
211 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
212 i++;
213
214 *pcdacIdx = i;
215 return;
216 }
217
218 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
219 u32 initTxGain,
220 int txPower,
221 u8 *pPDADCValues)
222 {
223 u32 i;
224 u32 offset;
225
226 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
227 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
228 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
229 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
230
231 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
232 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
233
234 offset = txPower;
235 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
236 if (i < offset)
237 pPDADCValues[i] = 0x0;
238 else
239 pPDADCValues[i] = 0xFF;
240 }
241
242
243
244
245 static void ath9k_hw_get_target_powers(struct ath_hw *ah,
246 struct ath9k_channel *chan,
247 struct cal_target_power_ht *powInfo,
248 u16 numChannels,
249 struct cal_target_power_ht *pNewPower,
250 u16 numRates, bool isHt40Target)
251 {
252 struct chan_centers centers;
253 u16 clo, chi;
254 int i;
255 int matchIndex = -1, lowIndex = -1;
256 u16 freq;
257
258 ath9k_hw_get_channel_centers(ah, chan, &centers);
259 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
260
261 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
262 matchIndex = 0;
263 } else {
264 for (i = 0; (i < numChannels) &&
265 (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
266 if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
267 IS_CHAN_2GHZ(chan))) {
268 matchIndex = i;
269 break;
270 } else
271 if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
272 IS_CHAN_2GHZ(chan))) &&
273 (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
274 IS_CHAN_2GHZ(chan)))) {
275 lowIndex = i - 1;
276 break;
277 }
278 }
279 if ((matchIndex == -1) && (lowIndex == -1))
280 matchIndex = i - 1;
281 }
282
283 if (matchIndex != -1) {
284 *pNewPower = powInfo[matchIndex];
285 } else {
286 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
287 IS_CHAN_2GHZ(chan));
288 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
289 IS_CHAN_2GHZ(chan));
290
291 for (i = 0; i < numRates; i++) {
292 pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
293 clo, chi,
294 powInfo[lowIndex].tPow2x[i],
295 powInfo[lowIndex + 1].tPow2x[i]);
296 }
297 }
298 }
299
300 static u16 ath9k_hw_get_max_edge_power(u16 freq,
301 struct cal_ctl_edges *pRdEdgesPower,
302 bool is2GHz, int num_band_edges)
303 {
304 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
305 int i;
306
307 for (i = 0; (i < num_band_edges) &&
308 (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
309 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
310 twiceMaxEdgePower = pRdEdgesPower[i].tPower;
311 break;
312 } else if ((i > 0) &&
313 (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
314 is2GHz))) {
315 if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
316 is2GHz) < freq &&
317 pRdEdgesPower[i - 1].flag) {
318 twiceMaxEdgePower =
319 pRdEdgesPower[i - 1].tPower;
320 }
321 break;
322 }
323 }
324
325 return twiceMaxEdgePower;
326 }
327
328 /****************************************/
329 /* EEPROM Operations for 4K sized cards */
330 /****************************************/
331
332 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
333 {
334 return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
335 }
336
337 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
338 {
339 return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
340 }
341
342 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
343 {
344 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
345 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
346 u16 *eep_data;
347 int addr, eep_start_loc = 0;
348
349 eep_start_loc = 64;
350
351 if (!ath9k_hw_use_flash(ah)) {
352 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
353 "Reading from EEPROM, not flash\n");
354 }
355
356 eep_data = (u16 *)eep;
357
358 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
359 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
360 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
361 "Unable to read eeprom region \n");
362 return false;
363 }
364 eep_data++;
365 }
366 return true;
367 #undef SIZE_EEPROM_4K
368 }
369
370 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
371 {
372 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
373 struct ar5416_eeprom_4k *eep =
374 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
375 u16 *eepdata, temp, magic, magic2;
376 u32 sum = 0, el;
377 bool need_swap = false;
378 int i, addr;
379
380
381 if (!ath9k_hw_use_flash(ah)) {
382
383 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
384 &magic)) {
385 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
386 "Reading Magic # failed\n");
387 return false;
388 }
389
390 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
391 "Read Magic = 0x%04X\n", magic);
392
393 if (magic != AR5416_EEPROM_MAGIC) {
394 magic2 = swab16(magic);
395
396 if (magic2 == AR5416_EEPROM_MAGIC) {
397 need_swap = true;
398 eepdata = (u16 *) (&ah->eeprom);
399
400 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
401 temp = swab16(*eepdata);
402 *eepdata = temp;
403 eepdata++;
404
405 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
406 "0x%04X ", *eepdata);
407
408 if (((addr + 1) % 6) == 0)
409 DPRINTF(ah->ah_sc,
410 ATH_DBG_EEPROM, "\n");
411 }
412 } else {
413 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
414 "Invalid EEPROM Magic. "
415 "endianness mismatch.\n");
416 return -EINVAL;
417 }
418 }
419 }
420
421 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
422 need_swap ? "True" : "False");
423
424 if (need_swap)
425 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
426 else
427 el = ah->eeprom.map4k.baseEepHeader.length;
428
429 if (el > sizeof(struct ar5416_eeprom_def))
430 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
431 else
432 el = el / sizeof(u16);
433
434 eepdata = (u16 *)(&ah->eeprom);
435
436 for (i = 0; i < el; i++)
437 sum ^= *eepdata++;
438
439 if (need_swap) {
440 u32 integer;
441 u16 word;
442
443 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
444 "EEPROM Endianness is not native.. Changing \n");
445
446 word = swab16(eep->baseEepHeader.length);
447 eep->baseEepHeader.length = word;
448
449 word = swab16(eep->baseEepHeader.checksum);
450 eep->baseEepHeader.checksum = word;
451
452 word = swab16(eep->baseEepHeader.version);
453 eep->baseEepHeader.version = word;
454
455 word = swab16(eep->baseEepHeader.regDmn[0]);
456 eep->baseEepHeader.regDmn[0] = word;
457
458 word = swab16(eep->baseEepHeader.regDmn[1]);
459 eep->baseEepHeader.regDmn[1] = word;
460
461 word = swab16(eep->baseEepHeader.rfSilent);
462 eep->baseEepHeader.rfSilent = word;
463
464 word = swab16(eep->baseEepHeader.blueToothOptions);
465 eep->baseEepHeader.blueToothOptions = word;
466
467 word = swab16(eep->baseEepHeader.deviceCap);
468 eep->baseEepHeader.deviceCap = word;
469
470 integer = swab32(eep->modalHeader.antCtrlCommon);
471 eep->modalHeader.antCtrlCommon = integer;
472
473 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
474 integer = swab32(eep->modalHeader.antCtrlChain[i]);
475 eep->modalHeader.antCtrlChain[i] = integer;
476 }
477
478 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
479 word = swab16(eep->modalHeader.spurChans[i].spurChan);
480 eep->modalHeader.spurChans[i].spurChan = word;
481 }
482 }
483
484 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
485 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
486 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
487 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
488 sum, ah->eep_ops->get_eeprom_ver(ah));
489 return -EINVAL;
490 }
491
492 return 0;
493 #undef EEPROM_4K_SIZE
494 }
495
496 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
497 enum eeprom_param param)
498 {
499 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
500 struct modal_eep_4k_header *pModal = &eep->modalHeader;
501 struct base_eep_header_4k *pBase = &eep->baseEepHeader;
502
503 switch (param) {
504 case EEP_NFTHRESH_2:
505 return pModal->noiseFloorThreshCh[0];
506 case AR_EEPROM_MAC(0):
507 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
508 case AR_EEPROM_MAC(1):
509 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
510 case AR_EEPROM_MAC(2):
511 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
512 case EEP_REG_0:
513 return pBase->regDmn[0];
514 case EEP_REG_1:
515 return pBase->regDmn[1];
516 case EEP_OP_CAP:
517 return pBase->deviceCap;
518 case EEP_OP_MODE:
519 return pBase->opCapFlags;
520 case EEP_RF_SILENT:
521 return pBase->rfSilent;
522 case EEP_OB_2:
523 return pModal->ob_01;
524 case EEP_DB_2:
525 return pModal->db1_01;
526 case EEP_MINOR_REV:
527 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
528 case EEP_TX_MASK:
529 return pBase->txMask;
530 case EEP_RX_MASK:
531 return pBase->rxMask;
532 case EEP_FRAC_N_5G:
533 return 0;
534 default:
535 return 0;
536 }
537 }
538
539 static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
540 struct ath9k_channel *chan,
541 struct cal_data_per_freq_4k *pRawDataSet,
542 u8 *bChans, u16 availPiers,
543 u16 tPdGainOverlap, int16_t *pMinCalPower,
544 u16 *pPdGainBoundaries, u8 *pPDADCValues,
545 u16 numXpdGains)
546 {
547 #define TMP_VAL_VPD_TABLE \
548 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
549 int i, j, k;
550 int16_t ss;
551 u16 idxL = 0, idxR = 0, numPiers;
552 static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
553 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
554 static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
555 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
556 static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
557 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
558
559 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
560 u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
561 u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
562 int16_t vpdStep;
563 int16_t tmpVal;
564 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
565 bool match;
566 int16_t minDelta = 0;
567 struct chan_centers centers;
568 #define PD_GAIN_BOUNDARY_DEFAULT 58;
569
570 ath9k_hw_get_channel_centers(ah, chan, &centers);
571
572 for (numPiers = 0; numPiers < availPiers; numPiers++) {
573 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
574 break;
575 }
576
577 match = ath9k_hw_get_lower_upper_index(
578 (u8)FREQ2FBIN(centers.synth_center,
579 IS_CHAN_2GHZ(chan)), bChans, numPiers,
580 &idxL, &idxR);
581
582 if (match) {
583 for (i = 0; i < numXpdGains; i++) {
584 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
585 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
586 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
587 pRawDataSet[idxL].pwrPdg[i],
588 pRawDataSet[idxL].vpdPdg[i],
589 AR5416_EEP4K_PD_GAIN_ICEPTS,
590 vpdTableI[i]);
591 }
592 } else {
593 for (i = 0; i < numXpdGains; i++) {
594 pVpdL = pRawDataSet[idxL].vpdPdg[i];
595 pPwrL = pRawDataSet[idxL].pwrPdg[i];
596 pVpdR = pRawDataSet[idxR].vpdPdg[i];
597 pPwrR = pRawDataSet[idxR].pwrPdg[i];
598
599 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
600
601 maxPwrT4[i] =
602 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
603 pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
604
605
606 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
607 pPwrL, pVpdL,
608 AR5416_EEP4K_PD_GAIN_ICEPTS,
609 vpdTableL[i]);
610 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
611 pPwrR, pVpdR,
612 AR5416_EEP4K_PD_GAIN_ICEPTS,
613 vpdTableR[i]);
614
615 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
616 vpdTableI[i][j] =
617 (u8)(ath9k_hw_interpolate((u16)
618 FREQ2FBIN(centers.
619 synth_center,
620 IS_CHAN_2GHZ
621 (chan)),
622 bChans[idxL], bChans[idxR],
623 vpdTableL[i][j], vpdTableR[i][j]));
624 }
625 }
626 }
627
628 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
629
630 k = 0;
631
632 for (i = 0; i < numXpdGains; i++) {
633 if (i == (numXpdGains - 1))
634 pPdGainBoundaries[i] =
635 (u16)(maxPwrT4[i] / 2);
636 else
637 pPdGainBoundaries[i] =
638 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
639
640 pPdGainBoundaries[i] =
641 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
642
643 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
644 minDelta = pPdGainBoundaries[0] - 23;
645 pPdGainBoundaries[0] = 23;
646 } else {
647 minDelta = 0;
648 }
649
650 if (i == 0) {
651 if (AR_SREV_9280_10_OR_LATER(ah))
652 ss = (int16_t)(0 - (minPwrT4[i] / 2));
653 else
654 ss = 0;
655 } else {
656 ss = (int16_t)((pPdGainBoundaries[i - 1] -
657 (minPwrT4[i] / 2)) -
658 tPdGainOverlap + 1 + minDelta);
659 }
660 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
661 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
662
663 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
664 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
665 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
666 ss++;
667 }
668
669 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
670 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
671 (minPwrT4[i] / 2));
672 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
673 tgtIndex : sizeCurrVpdTable;
674
675 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
676 pPDADCValues[k++] = vpdTableI[i][ss++];
677
678 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
679 vpdTableI[i][sizeCurrVpdTable - 2]);
680 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
681
682 if (tgtIndex >= maxIndex) {
683 while ((ss <= tgtIndex) &&
684 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
685 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
686 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
687 255 : tmpVal);
688 ss++;
689 }
690 }
691 }
692
693 while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
694 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
695 i++;
696 }
697
698 while (k < AR5416_NUM_PDADC_VALUES) {
699 pPDADCValues[k] = pPDADCValues[k - 1];
700 k++;
701 }
702
703 return;
704 #undef TMP_VAL_VPD_TABLE
705 }
706
707 static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
708 struct ath9k_channel *chan,
709 int16_t *pTxPowerIndexOffset)
710 {
711 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
712 struct cal_data_per_freq_4k *pRawDataset;
713 u8 *pCalBChans = NULL;
714 u16 pdGainOverlap_t2;
715 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
716 u16 gainBoundaries[AR5416_EEP4K_PD_GAINS_IN_MASK];
717 u16 numPiers, i, j;
718 int16_t tMinCalPower;
719 u16 numXpdGain, xpdMask;
720 u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
721 u32 reg32, regOffset, regChainOffset;
722
723 xpdMask = pEepData->modalHeader.xpdGain;
724
725 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
726 AR5416_EEP_MINOR_VER_2) {
727 pdGainOverlap_t2 =
728 pEepData->modalHeader.pdGainOverlap;
729 } else {
730 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
731 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
732 }
733
734 pCalBChans = pEepData->calFreqPier2G;
735 numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
736
737 numXpdGain = 0;
738
739 for (i = 1; i <= AR5416_EEP4K_PD_GAINS_IN_MASK; i++) {
740 if ((xpdMask >> (AR5416_EEP4K_PD_GAINS_IN_MASK - i)) & 1) {
741 if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
742 break;
743 xpdGainValues[numXpdGain] =
744 (u16)(AR5416_EEP4K_PD_GAINS_IN_MASK - i);
745 numXpdGain++;
746 }
747 }
748
749 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
750 (numXpdGain - 1) & 0x3);
751 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
752 xpdGainValues[0]);
753 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
754 xpdGainValues[1]);
755 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
756
757 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
758 if (AR_SREV_5416_20_OR_LATER(ah) &&
759 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
760 (i != 0)) {
761 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
762 } else
763 regChainOffset = i * 0x1000;
764
765 if (pEepData->baseEepHeader.txMask & (1 << i)) {
766 pRawDataset = pEepData->calPierData2G[i];
767
768 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
769 pRawDataset, pCalBChans,
770 numPiers, pdGainOverlap_t2,
771 &tMinCalPower, gainBoundaries,
772 pdadcValues, numXpdGain);
773
774 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
775 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
776 SM(pdGainOverlap_t2,
777 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
778 | SM(gainBoundaries[0],
779 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
780 | SM(gainBoundaries[1],
781 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
782 | SM(gainBoundaries[2],
783 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
784 | SM(gainBoundaries[3],
785 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
786 }
787
788 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
789 for (j = 0; j < 32; j++) {
790 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
791 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
792 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
793 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
794 REG_WRITE(ah, regOffset, reg32);
795
796 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
797 "PDADC (%d,%4x): %4.4x %8.8x\n",
798 i, regChainOffset, regOffset,
799 reg32);
800 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
801 "PDADC: Chain %d | "
802 "PDADC %3d Value %3d | "
803 "PDADC %3d Value %3d | "
804 "PDADC %3d Value %3d | "
805 "PDADC %3d Value %3d |\n",
806 i, 4 * j, pdadcValues[4 * j],
807 4 * j + 1, pdadcValues[4 * j + 1],
808 4 * j + 2, pdadcValues[4 * j + 2],
809 4 * j + 3,
810 pdadcValues[4 * j + 3]);
811
812 regOffset += 4;
813 }
814 }
815 }
816
817 *pTxPowerIndexOffset = 0;
818
819 return true;
820 }
821
822 static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
823 struct ath9k_channel *chan,
824 int16_t *ratesArray,
825 u16 cfgCtl,
826 u16 AntennaReduction,
827 u16 twiceMaxRegulatoryPower,
828 u16 powerLimit)
829 {
830 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
831 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
832 static const u16 tpScaleReductionTable[5] =
833 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
834
835 int i;
836 int16_t twiceLargestAntenna;
837 struct cal_ctl_data_4k *rep;
838 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
839 0, { 0, 0, 0, 0}
840 };
841 struct cal_target_power_leg targetPowerOfdmExt = {
842 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
843 0, { 0, 0, 0, 0 }
844 };
845 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
846 0, {0, 0, 0, 0}
847 };
848 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
849 u16 ctlModesFor11g[] =
850 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
851 CTL_2GHT40
852 };
853 u16 numCtlModes, *pCtlMode, ctlMode, freq;
854 struct chan_centers centers;
855 int tx_chainmask;
856 u16 twiceMinEdgePower;
857
858 tx_chainmask = ah->txchainmask;
859
860 ath9k_hw_get_channel_centers(ah, chan, &centers);
861
862 twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
863
864 twiceLargestAntenna = (int16_t)min(AntennaReduction -
865 twiceLargestAntenna, 0);
866
867 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
868
869 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
870 maxRegAllowedPower -=
871 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
872 }
873
874 scaledPower = min(powerLimit, maxRegAllowedPower);
875 scaledPower = max((u16)0, scaledPower);
876
877 numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
878 pCtlMode = ctlModesFor11g;
879
880 ath9k_hw_get_legacy_target_powers(ah, chan,
881 pEepData->calTargetPowerCck,
882 AR5416_NUM_2G_CCK_TARGET_POWERS,
883 &targetPowerCck, 4, false);
884 ath9k_hw_get_legacy_target_powers(ah, chan,
885 pEepData->calTargetPower2G,
886 AR5416_NUM_2G_20_TARGET_POWERS,
887 &targetPowerOfdm, 4, false);
888 ath9k_hw_get_target_powers(ah, chan,
889 pEepData->calTargetPower2GHT20,
890 AR5416_NUM_2G_20_TARGET_POWERS,
891 &targetPowerHt20, 8, false);
892
893 if (IS_CHAN_HT40(chan)) {
894 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
895 ath9k_hw_get_target_powers(ah, chan,
896 pEepData->calTargetPower2GHT40,
897 AR5416_NUM_2G_40_TARGET_POWERS,
898 &targetPowerHt40, 8, true);
899 ath9k_hw_get_legacy_target_powers(ah, chan,
900 pEepData->calTargetPowerCck,
901 AR5416_NUM_2G_CCK_TARGET_POWERS,
902 &targetPowerCckExt, 4, true);
903 ath9k_hw_get_legacy_target_powers(ah, chan,
904 pEepData->calTargetPower2G,
905 AR5416_NUM_2G_20_TARGET_POWERS,
906 &targetPowerOfdmExt, 4, true);
907 }
908
909 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
910 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
911 (pCtlMode[ctlMode] == CTL_2GHT40);
912 if (isHt40CtlMode)
913 freq = centers.synth_center;
914 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
915 freq = centers.ext_center;
916 else
917 freq = centers.ctl_center;
918
919 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
920 ah->eep_ops->get_eeprom_rev(ah) <= 2)
921 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
922
923 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
924 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
925 "EXT_ADDITIVE %d\n",
926 ctlMode, numCtlModes, isHt40CtlMode,
927 (pCtlMode[ctlMode] & EXT_ADDITIVE));
928
929 for (i = 0; (i < AR5416_NUM_CTLS) &&
930 pEepData->ctlIndex[i]; i++) {
931 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
932 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
933 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
934 "chan %d\n",
935 i, cfgCtl, pCtlMode[ctlMode],
936 pEepData->ctlIndex[i], chan->channel);
937
938 if ((((cfgCtl & ~CTL_MODE_M) |
939 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
940 pEepData->ctlIndex[i]) ||
941 (((cfgCtl & ~CTL_MODE_M) |
942 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
943 ((pEepData->ctlIndex[i] & CTL_MODE_M) |
944 SD_NO_CTL))) {
945 rep = &(pEepData->ctlData[i]);
946
947 twiceMinEdgePower =
948 ath9k_hw_get_max_edge_power(freq,
949 rep->ctlEdges[ar5416_get_ntxchains
950 (tx_chainmask) - 1],
951 IS_CHAN_2GHZ(chan),
952 AR5416_EEP4K_NUM_BAND_EDGES);
953
954 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
955 " MATCH-EE_IDX %d: ch %d is2 %d "
956 "2xMinEdge %d chainmask %d chains %d\n",
957 i, freq, IS_CHAN_2GHZ(chan),
958 twiceMinEdgePower, tx_chainmask,
959 ar5416_get_ntxchains
960 (tx_chainmask));
961 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
962 twiceMaxEdgePower =
963 min(twiceMaxEdgePower,
964 twiceMinEdgePower);
965 } else {
966 twiceMaxEdgePower = twiceMinEdgePower;
967 break;
968 }
969 }
970 }
971
972 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
973
974 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
975 " SEL-Min ctlMode %d pCtlMode %d "
976 "2xMaxEdge %d sP %d minCtlPwr %d\n",
977 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
978 scaledPower, minCtlPower);
979
980 switch (pCtlMode[ctlMode]) {
981 case CTL_11B:
982 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
983 i++) {
984 targetPowerCck.tPow2x[i] =
985 min((u16)targetPowerCck.tPow2x[i],
986 minCtlPower);
987 }
988 break;
989 case CTL_11G:
990 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
991 i++) {
992 targetPowerOfdm.tPow2x[i] =
993 min((u16)targetPowerOfdm.tPow2x[i],
994 minCtlPower);
995 }
996 break;
997 case CTL_2GHT20:
998 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
999 i++) {
1000 targetPowerHt20.tPow2x[i] =
1001 min((u16)targetPowerHt20.tPow2x[i],
1002 minCtlPower);
1003 }
1004 break;
1005 case CTL_11B_EXT:
1006 targetPowerCckExt.tPow2x[0] = min((u16)
1007 targetPowerCckExt.tPow2x[0],
1008 minCtlPower);
1009 break;
1010 case CTL_11G_EXT:
1011 targetPowerOfdmExt.tPow2x[0] = min((u16)
1012 targetPowerOfdmExt.tPow2x[0],
1013 minCtlPower);
1014 break;
1015 case CTL_2GHT40:
1016 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
1017 i++) {
1018 targetPowerHt40.tPow2x[i] =
1019 min((u16)targetPowerHt40.tPow2x[i],
1020 minCtlPower);
1021 }
1022 break;
1023 default:
1024 break;
1025 }
1026 }
1027
1028 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1029 ratesArray[rate18mb] = ratesArray[rate24mb] =
1030 targetPowerOfdm.tPow2x[0];
1031 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1032 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1033 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1034 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1035
1036 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1037 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1038
1039 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1040 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
1041 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
1042 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
1043
1044 if (IS_CHAN_HT40(chan)) {
1045 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1046 ratesArray[rateHt40_0 + i] =
1047 targetPowerHt40.tPow2x[i];
1048 }
1049 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1050 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1051 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1052 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1053 }
1054 return true;
1055 }
1056
1057 static int ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1058 struct ath9k_channel *chan,
1059 u16 cfgCtl,
1060 u8 twiceAntennaReduction,
1061 u8 twiceMaxRegulatoryPower,
1062 u8 powerLimit)
1063 {
1064 struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
1065 struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
1066 int16_t ratesArray[Ar5416RateSize];
1067 int16_t txPowerIndexOffset = 0;
1068 u8 ht40PowerIncForPdadc = 2;
1069 int i;
1070
1071 memset(ratesArray, 0, sizeof(ratesArray));
1072
1073 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1074 AR5416_EEP_MINOR_VER_2) {
1075 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1076 }
1077
1078 if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1079 &ratesArray[0], cfgCtl,
1080 twiceAntennaReduction,
1081 twiceMaxRegulatoryPower,
1082 powerLimit)) {
1083 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1084 "ath9k_hw_set_txpower: unable to set "
1085 "tx power per rate table\n");
1086 return -EIO;
1087 }
1088
1089 if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) {
1090 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1091 "ath9k_hw_set_txpower: unable to set power table\n");
1092 return -EIO;
1093 }
1094
1095 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1096 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1097 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1098 ratesArray[i] = AR5416_MAX_RATE_POWER;
1099 }
1100
1101 if (AR_SREV_9280_10_OR_LATER(ah)) {
1102 for (i = 0; i < Ar5416RateSize; i++)
1103 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1104 }
1105
1106 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1107 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1108 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1109 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1110 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1111 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1112 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1113 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1114 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1115 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1116
1117 if (IS_CHAN_2GHZ(chan)) {
1118 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1119 ATH9K_POW_SM(ratesArray[rate2s], 24)
1120 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1121 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1122 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1123 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1124 ATH9K_POW_SM(ratesArray[rate11s], 24)
1125 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1126 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1127 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1128 }
1129
1130 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1131 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1132 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1133 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1134 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1135 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1136 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1137 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1138 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1139 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1140
1141 if (IS_CHAN_HT40(chan)) {
1142 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1143 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1144 ht40PowerIncForPdadc, 24)
1145 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1146 ht40PowerIncForPdadc, 16)
1147 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1148 ht40PowerIncForPdadc, 8)
1149 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1150 ht40PowerIncForPdadc, 0));
1151 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1152 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1153 ht40PowerIncForPdadc, 24)
1154 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1155 ht40PowerIncForPdadc, 16)
1156 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1157 ht40PowerIncForPdadc, 8)
1158 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1159 ht40PowerIncForPdadc, 0));
1160
1161 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1162 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1163 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1164 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1165 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1166 }
1167
1168 i = rate6mb;
1169
1170 if (IS_CHAN_HT40(chan))
1171 i = rateHt40_0;
1172 else if (IS_CHAN_HT20(chan))
1173 i = rateHt20_0;
1174
1175 if (AR_SREV_9280_10_OR_LATER(ah))
1176 ah->regulatory.max_power_level =
1177 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1178 else
1179 ah->regulatory.max_power_level = ratesArray[i];
1180
1181 return 0;
1182 }
1183
1184 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1185 struct ath9k_channel *chan)
1186 {
1187 struct modal_eep_4k_header *pModal;
1188 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1189 u8 biaslevel;
1190
1191 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1192 return;
1193
1194 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1195 return;
1196
1197 pModal = &eep->modalHeader;
1198
1199 if (pModal->xpaBiasLvl != 0xff) {
1200 biaslevel = pModal->xpaBiasLvl;
1201 INI_RA(&ah->iniAddac, 7, 1) =
1202 (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
1203 }
1204 }
1205
1206 static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1207 struct ath9k_channel *chan)
1208 {
1209 struct modal_eep_4k_header *pModal;
1210 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1211 int regChainOffset;
1212 u8 txRxAttenLocal;
1213 u8 ob[5], db1[5], db2[5];
1214 u8 ant_div_control1, ant_div_control2;
1215 u32 regVal;
1216
1217
1218 pModal = &eep->modalHeader;
1219
1220 txRxAttenLocal = 23;
1221
1222 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1223 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1224
1225 regChainOffset = 0;
1226 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1227 pModal->antCtrlChain[0]);
1228
1229 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1230 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1231 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1232 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1233 SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1234 SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1235
1236 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1237 AR5416_EEP_MINOR_VER_3) {
1238 txRxAttenLocal = pModal->txRxAttenCh[0];
1239 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1240 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
1241 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1242 AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
1243 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1244 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1245 pModal->xatten2Margin[0]);
1246 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1247 AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
1248 }
1249
1250 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1251 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1252 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1253 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
1254
1255 if (AR_SREV_9285_11(ah))
1256 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
1257
1258 /* Initialize Ant Diversity settings from EEPROM */
1259 if (pModal->version == 3) {
1260 ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf);
1261 ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf);
1262 regVal = REG_READ(ah, 0x99ac);
1263 regVal &= (~(0x7f000000));
1264 regVal |= ((ant_div_control1 & 0x1) << 24);
1265 regVal |= (((ant_div_control1 >> 1) & 0x1) << 29);
1266 regVal |= (((ant_div_control1 >> 2) & 0x1) << 30);
1267 regVal |= ((ant_div_control2 & 0x3) << 25);
1268 regVal |= (((ant_div_control2 >> 2) & 0x3) << 27);
1269 REG_WRITE(ah, 0x99ac, regVal);
1270 regVal = REG_READ(ah, 0x99ac);
1271 regVal = REG_READ(ah, 0xa208);
1272 regVal &= (~(0x1 << 13));
1273 regVal |= (((ant_div_control1 >> 3) & 0x1) << 13);
1274 REG_WRITE(ah, 0xa208, regVal);
1275 regVal = REG_READ(ah, 0xa208);
1276 }
1277
1278 if (pModal->version >= 2) {
1279 ob[0] = (pModal->ob_01 & 0xf);
1280 ob[1] = (pModal->ob_01 >> 4) & 0xf;
1281 ob[2] = (pModal->ob_234 & 0xf);
1282 ob[3] = ((pModal->ob_234 >> 4) & 0xf);
1283 ob[4] = ((pModal->ob_234 >> 8) & 0xf);
1284
1285 db1[0] = (pModal->db1_01 & 0xf);
1286 db1[1] = ((pModal->db1_01 >> 4) & 0xf);
1287 db1[2] = (pModal->db1_234 & 0xf);
1288 db1[3] = ((pModal->db1_234 >> 4) & 0xf);
1289 db1[4] = ((pModal->db1_234 >> 8) & 0xf);
1290
1291 db2[0] = (pModal->db2_01 & 0xf);
1292 db2[1] = ((pModal->db2_01 >> 4) & 0xf);
1293 db2[2] = (pModal->db2_234 & 0xf);
1294 db2[3] = ((pModal->db2_234 >> 4) & 0xf);
1295 db2[4] = ((pModal->db2_234 >> 8) & 0xf);
1296
1297 } else if (pModal->version == 1) {
1298
1299 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1300 "EEPROM Model version is set to 1 \n");
1301 ob[0] = (pModal->ob_01 & 0xf);
1302 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf;
1303 db1[0] = (pModal->db1_01 & 0xf);
1304 db1[1] = db1[2] = db1[3] =
1305 db1[4] = ((pModal->db1_01 >> 4) & 0xf);
1306 db2[0] = (pModal->db2_01 & 0xf);
1307 db2[1] = db2[2] = db2[3] =
1308 db2[4] = ((pModal->db2_01 >> 4) & 0xf);
1309 } else {
1310 int i;
1311 for (i = 0; i < 5; i++) {
1312 ob[i] = pModal->ob_01;
1313 db1[i] = pModal->db1_01;
1314 db2[i] = pModal->db1_01;
1315 }
1316 }
1317
1318 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1319 AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]);
1320 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1321 AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]);
1322 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1323 AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]);
1324 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1325 AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]);
1326 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1327 AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]);
1328
1329 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1330 AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]);
1331 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1332 AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]);
1333 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1334 AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]);
1335 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1336 AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]);
1337 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1338 AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1339
1340 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1341 AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]);
1342 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1343 AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]);
1344 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1345 AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]);
1346 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1347 AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]);
1348 ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1349 AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]);
1350
1351
1352 if (AR_SREV_9285_11(ah))
1353 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1354
1355 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1356 pModal->switchSettling);
1357 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1358 pModal->adcDesiredSize);
1359
1360 REG_WRITE(ah, AR_PHY_RF_CTL4,
1361 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1362 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1363 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) |
1364 SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1365
1366 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1367 pModal->txEndToRxOn);
1368 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1369 pModal->thresh62);
1370 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1371 pModal->thresh62);
1372
1373 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1374 AR5416_EEP_MINOR_VER_2) {
1375 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1376 pModal->txFrameToDataStart);
1377 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1378 pModal->txFrameToPaOn);
1379 }
1380
1381 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1382 AR5416_EEP_MINOR_VER_3) {
1383 if (IS_CHAN_HT40(chan))
1384 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1385 AR_PHY_SETTLING_SWITCH,
1386 pModal->swSettleHt40);
1387 }
1388
1389 return true;
1390 }
1391
1392 static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1393 struct ath9k_channel *chan)
1394 {
1395 struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1396 struct modal_eep_4k_header *pModal = &eep->modalHeader;
1397
1398 return pModal->antCtrlCommon & 0xFFFF;
1399 }
1400
1401 static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1402 enum ieee80211_band freq_band)
1403 {
1404 return 1;
1405 }
1406
1407 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1408 {
1409 #define EEP_MAP4K_SPURCHAN \
1410 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1411
1412 u16 spur_val = AR_NO_SPUR;
1413
1414 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1415 "Getting spur idx %d is2Ghz. %d val %x\n",
1416 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1417
1418 switch (ah->config.spurmode) {
1419 case SPUR_DISABLE:
1420 break;
1421 case SPUR_ENABLE_IOCTL:
1422 spur_val = ah->config.spurchans[i][is2GHz];
1423 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1424 "Getting spur val from new loc. %d\n", spur_val);
1425 break;
1426 case SPUR_ENABLE_EEPROM:
1427 spur_val = EEP_MAP4K_SPURCHAN;
1428 break;
1429 }
1430
1431 return spur_val;
1432
1433 #undef EEP_MAP4K_SPURCHAN
1434 }
1435
1436 static struct eeprom_ops eep_4k_ops = {
1437 .check_eeprom = ath9k_hw_4k_check_eeprom,
1438 .get_eeprom = ath9k_hw_4k_get_eeprom,
1439 .fill_eeprom = ath9k_hw_4k_fill_eeprom,
1440 .get_eeprom_ver = ath9k_hw_4k_get_eeprom_ver,
1441 .get_eeprom_rev = ath9k_hw_4k_get_eeprom_rev,
1442 .get_num_ant_config = ath9k_hw_4k_get_num_ant_config,
1443 .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1444 .set_board_values = ath9k_hw_4k_set_board_values,
1445 .set_addac = ath9k_hw_4k_set_addac,
1446 .set_txpower = ath9k_hw_4k_set_txpower,
1447 .get_spur_channel = ath9k_hw_4k_get_spur_channel
1448 };
1449
1450 /************************************************/
1451 /* EEPROM Operations for non-4K (Default) cards */
1452 /************************************************/
1453
1454 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
1455 {
1456 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
1457 }
1458
1459 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
1460 {
1461 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
1462 }
1463
1464 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
1465 {
1466 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
1467 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1468 u16 *eep_data;
1469 int addr, ar5416_eep_start_loc = 0x100;
1470
1471 eep_data = (u16 *)eep;
1472
1473 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
1474 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
1475 eep_data)) {
1476 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1477 "Unable to read eeprom region\n");
1478 return false;
1479 }
1480 eep_data++;
1481 }
1482 return true;
1483 #undef SIZE_EEPROM_DEF
1484 }
1485
1486 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1487 {
1488 struct ar5416_eeprom_def *eep =
1489 (struct ar5416_eeprom_def *) &ah->eeprom.def;
1490 u16 *eepdata, temp, magic, magic2;
1491 u32 sum = 0, el;
1492 bool need_swap = false;
1493 int i, addr, size;
1494
1495 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
1496 &magic)) {
1497 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1498 "Reading Magic # failed\n");
1499 return false;
1500 }
1501
1502 if (!ath9k_hw_use_flash(ah)) {
1503
1504 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1505 "Read Magic = 0x%04X\n", magic);
1506
1507 if (magic != AR5416_EEPROM_MAGIC) {
1508 magic2 = swab16(magic);
1509
1510 if (magic2 == AR5416_EEPROM_MAGIC) {
1511 size = sizeof(struct ar5416_eeprom_def);
1512 need_swap = true;
1513 eepdata = (u16 *) (&ah->eeprom);
1514
1515 for (addr = 0; addr < size / sizeof(u16); addr++) {
1516 temp = swab16(*eepdata);
1517 *eepdata = temp;
1518 eepdata++;
1519
1520 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1521 "0x%04X ", *eepdata);
1522
1523 if (((addr + 1) % 6) == 0)
1524 DPRINTF(ah->ah_sc,
1525 ATH_DBG_EEPROM, "\n");
1526 }
1527 } else {
1528 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1529 "Invalid EEPROM Magic. "
1530 "endianness mismatch.\n");
1531 return -EINVAL;
1532 }
1533 }
1534 }
1535
1536 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
1537 need_swap ? "True" : "False");
1538
1539 if (need_swap)
1540 el = swab16(ah->eeprom.def.baseEepHeader.length);
1541 else
1542 el = ah->eeprom.def.baseEepHeader.length;
1543
1544 if (el > sizeof(struct ar5416_eeprom_def))
1545 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
1546 else
1547 el = el / sizeof(u16);
1548
1549 eepdata = (u16 *)(&ah->eeprom);
1550
1551 for (i = 0; i < el; i++)
1552 sum ^= *eepdata++;
1553
1554 if (need_swap) {
1555 u32 integer, j;
1556 u16 word;
1557
1558 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1559 "EEPROM Endianness is not native.. Changing \n");
1560
1561 word = swab16(eep->baseEepHeader.length);
1562 eep->baseEepHeader.length = word;
1563
1564 word = swab16(eep->baseEepHeader.checksum);
1565 eep->baseEepHeader.checksum = word;
1566
1567 word = swab16(eep->baseEepHeader.version);
1568 eep->baseEepHeader.version = word;
1569
1570 word = swab16(eep->baseEepHeader.regDmn[0]);
1571 eep->baseEepHeader.regDmn[0] = word;
1572
1573 word = swab16(eep->baseEepHeader.regDmn[1]);
1574 eep->baseEepHeader.regDmn[1] = word;
1575
1576 word = swab16(eep->baseEepHeader.rfSilent);
1577 eep->baseEepHeader.rfSilent = word;
1578
1579 word = swab16(eep->baseEepHeader.blueToothOptions);
1580 eep->baseEepHeader.blueToothOptions = word;
1581
1582 word = swab16(eep->baseEepHeader.deviceCap);
1583 eep->baseEepHeader.deviceCap = word;
1584
1585 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
1586 struct modal_eep_header *pModal =
1587 &eep->modalHeader[j];
1588 integer = swab32(pModal->antCtrlCommon);
1589 pModal->antCtrlCommon = integer;
1590
1591 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1592 integer = swab32(pModal->antCtrlChain[i]);
1593 pModal->antCtrlChain[i] = integer;
1594 }
1595
1596 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
1597 word = swab16(pModal->spurChans[i].spurChan);
1598 pModal->spurChans[i].spurChan = word;
1599 }
1600 }
1601 }
1602
1603 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
1604 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
1605 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1606 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
1607 sum, ah->eep_ops->get_eeprom_ver(ah));
1608 return -EINVAL;
1609 }
1610
1611 return 0;
1612 }
1613
1614 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
1615 enum eeprom_param param)
1616 {
1617 #define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK)
1618 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1619 struct modal_eep_header *pModal = eep->modalHeader;
1620 struct base_eep_header *pBase = &eep->baseEepHeader;
1621
1622 switch (param) {
1623 case EEP_NFTHRESH_5:
1624 return pModal[0].noiseFloorThreshCh[0];
1625 case EEP_NFTHRESH_2:
1626 return pModal[1].noiseFloorThreshCh[0];
1627 case AR_EEPROM_MAC(0):
1628 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1629 case AR_EEPROM_MAC(1):
1630 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1631 case AR_EEPROM_MAC(2):
1632 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1633 case EEP_REG_0:
1634 return pBase->regDmn[0];
1635 case EEP_REG_1:
1636 return pBase->regDmn[1];
1637 case EEP_OP_CAP:
1638 return pBase->deviceCap;
1639 case EEP_OP_MODE:
1640 return pBase->opCapFlags;
1641 case EEP_RF_SILENT:
1642 return pBase->rfSilent;
1643 case EEP_OB_5:
1644 return pModal[0].ob;
1645 case EEP_DB_5:
1646 return pModal[0].db;
1647 case EEP_OB_2:
1648 return pModal[1].ob;
1649 case EEP_DB_2:
1650 return pModal[1].db;
1651 case EEP_MINOR_REV:
1652 return AR5416_VER_MASK;
1653 case EEP_TX_MASK:
1654 return pBase->txMask;
1655 case EEP_RX_MASK:
1656 return pBase->rxMask;
1657 case EEP_RXGAIN_TYPE:
1658 return pBase->rxGainType;
1659 case EEP_TXGAIN_TYPE:
1660 return pBase->txGainType;
1661 case EEP_OL_PWRCTRL:
1662 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1663 return pBase->openLoopPwrCntl ? true : false;
1664 else
1665 return false;
1666 case EEP_RC_CHAIN_MASK:
1667 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1668 return pBase->rcChainMask;
1669 else
1670 return 0;
1671 case EEP_DAC_HPWR_5G:
1672 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
1673 return pBase->dacHiPwrMode_5G;
1674 else
1675 return 0;
1676 case EEP_FRAC_N_5G:
1677 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
1678 return pBase->frac_n_5g;
1679 else
1680 return 0;
1681 default:
1682 return 0;
1683 }
1684 #undef AR5416_VER_MASK
1685 }
1686
1687 /* XXX: Clean me up, make me more legible */
1688 static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1689 struct ath9k_channel *chan)
1690 {
1691 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
1692 struct modal_eep_header *pModal;
1693 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1694 int i, regChainOffset;
1695 u8 txRxAttenLocal;
1696
1697 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1698
1699 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
1700
1701 REG_WRITE(ah, AR_PHY_SWITCH_COM,
1702 ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1703
1704 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1705 if (AR_SREV_9280(ah)) {
1706 if (i >= 2)
1707 break;
1708 }
1709
1710 if (AR_SREV_5416_20_OR_LATER(ah) &&
1711 (ah->rxchainmask == 5 || ah->txchainmask == 5)
1712 && (i != 0))
1713 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1714 else
1715 regChainOffset = i * 0x1000;
1716
1717 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1718 pModal->antCtrlChain[i]);
1719
1720 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1721 (REG_READ(ah,
1722 AR_PHY_TIMING_CTRL4(0) +
1723 regChainOffset) &
1724 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1725 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1726 SM(pModal->iqCalICh[i],
1727 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1728 SM(pModal->iqCalQCh[i],
1729 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1730
1731 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
1732 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1733 txRxAttenLocal = pModal->txRxAttenCh[i];
1734 if (AR_SREV_9280_10_OR_LATER(ah)) {
1735 REG_RMW_FIELD(ah,
1736 AR_PHY_GAIN_2GHZ +
1737 regChainOffset,
1738 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1739 pModal->
1740 bswMargin[i]);
1741 REG_RMW_FIELD(ah,
1742 AR_PHY_GAIN_2GHZ +
1743 regChainOffset,
1744 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1745 pModal->
1746 bswAtten[i]);
1747 REG_RMW_FIELD(ah,
1748 AR_PHY_GAIN_2GHZ +
1749 regChainOffset,
1750 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1751 pModal->
1752 xatten2Margin[i]);
1753 REG_RMW_FIELD(ah,
1754 AR_PHY_GAIN_2GHZ +
1755 regChainOffset,
1756 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1757 pModal->
1758 xatten2Db[i]);
1759 } else {
1760 REG_WRITE(ah,
1761 AR_PHY_GAIN_2GHZ +
1762 regChainOffset,
1763 (REG_READ(ah,
1764 AR_PHY_GAIN_2GHZ +
1765 regChainOffset) &
1766 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
1767 | SM(pModal->
1768 bswMargin[i],
1769 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1770 REG_WRITE(ah,
1771 AR_PHY_GAIN_2GHZ +
1772 regChainOffset,
1773 (REG_READ(ah,
1774 AR_PHY_GAIN_2GHZ +
1775 regChainOffset) &
1776 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
1777 | SM(pModal->bswAtten[i],
1778 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1779 }
1780 }
1781 if (AR_SREV_9280_10_OR_LATER(ah)) {
1782 REG_RMW_FIELD(ah,
1783 AR_PHY_RXGAIN +
1784 regChainOffset,
1785 AR9280_PHY_RXGAIN_TXRX_ATTEN,
1786 txRxAttenLocal);
1787 REG_RMW_FIELD(ah,
1788 AR_PHY_RXGAIN +
1789 regChainOffset,
1790 AR9280_PHY_RXGAIN_TXRX_MARGIN,
1791 pModal->rxTxMarginCh[i]);
1792 } else {
1793 REG_WRITE(ah,
1794 AR_PHY_RXGAIN + regChainOffset,
1795 (REG_READ(ah,
1796 AR_PHY_RXGAIN +
1797 regChainOffset) &
1798 ~AR_PHY_RXGAIN_TXRX_ATTEN) |
1799 SM(txRxAttenLocal,
1800 AR_PHY_RXGAIN_TXRX_ATTEN));
1801 REG_WRITE(ah,
1802 AR_PHY_GAIN_2GHZ +
1803 regChainOffset,
1804 (REG_READ(ah,
1805 AR_PHY_GAIN_2GHZ +
1806 regChainOffset) &
1807 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1808 SM(pModal->rxTxMarginCh[i],
1809 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1810 }
1811 }
1812 }
1813
1814 if (AR_SREV_9280_10_OR_LATER(ah)) {
1815 if (IS_CHAN_2GHZ(chan)) {
1816 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1817 AR_AN_RF2G1_CH0_OB,
1818 AR_AN_RF2G1_CH0_OB_S,
1819 pModal->ob);
1820 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1821 AR_AN_RF2G1_CH0_DB,
1822 AR_AN_RF2G1_CH0_DB_S,
1823 pModal->db);
1824 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1825 AR_AN_RF2G1_CH1_OB,
1826 AR_AN_RF2G1_CH1_OB_S,
1827 pModal->ob_ch1);
1828 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1829 AR_AN_RF2G1_CH1_DB,
1830 AR_AN_RF2G1_CH1_DB_S,
1831 pModal->db_ch1);
1832 } else {
1833 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1834 AR_AN_RF5G1_CH0_OB5,
1835 AR_AN_RF5G1_CH0_OB5_S,
1836 pModal->ob);
1837 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1838 AR_AN_RF5G1_CH0_DB5,
1839 AR_AN_RF5G1_CH0_DB5_S,
1840 pModal->db);
1841 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1842 AR_AN_RF5G1_CH1_OB5,
1843 AR_AN_RF5G1_CH1_OB5_S,
1844 pModal->ob_ch1);
1845 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1846 AR_AN_RF5G1_CH1_DB5,
1847 AR_AN_RF5G1_CH1_DB5_S,
1848 pModal->db_ch1);
1849 }
1850 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1851 AR_AN_TOP2_XPABIAS_LVL,
1852 AR_AN_TOP2_XPABIAS_LVL_S,
1853 pModal->xpaBiasLvl);
1854 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1855 AR_AN_TOP2_LOCALBIAS,
1856 AR_AN_TOP2_LOCALBIAS_S,
1857 pModal->local_bias);
1858 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "ForceXPAon: %d\n",
1859 pModal->force_xpaon);
1860 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
1861 pModal->force_xpaon);
1862 }
1863
1864 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1865 pModal->switchSettling);
1866 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1867 pModal->adcDesiredSize);
1868
1869 if (!AR_SREV_9280_10_OR_LATER(ah))
1870 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1871 AR_PHY_DESIRED_SZ_PGA,
1872 pModal->pgaDesiredSize);
1873
1874 REG_WRITE(ah, AR_PHY_RF_CTL4,
1875 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1876 | SM(pModal->txEndToXpaOff,
1877 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1878 | SM(pModal->txFrameToXpaOn,
1879 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1880 | SM(pModal->txFrameToXpaOn,
1881 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1882
1883 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1884 pModal->txEndToRxOn);
1885 if (AR_SREV_9280_10_OR_LATER(ah)) {
1886 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1887 pModal->thresh62);
1888 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
1889 AR_PHY_EXT_CCA0_THRESH62,
1890 pModal->thresh62);
1891 } else {
1892 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
1893 pModal->thresh62);
1894 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1895 AR_PHY_EXT_CCA_THRESH62,
1896 pModal->thresh62);
1897 }
1898
1899 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
1900 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1901 AR_PHY_TX_END_DATA_START,
1902 pModal->txFrameToDataStart);
1903 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1904 pModal->txFrameToPaOn);
1905 }
1906
1907 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1908 if (IS_CHAN_HT40(chan))
1909 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1910 AR_PHY_SETTLING_SWITCH,
1911 pModal->swSettleHt40);
1912 }
1913
1914 if (AR_SREV_9280_20_OR_LATER(ah) &&
1915 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1916 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
1917 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
1918 pModal->miscBits);
1919
1920
1921 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
1922 if (IS_CHAN_2GHZ(chan))
1923 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
1924 eep->baseEepHeader.dacLpMode);
1925 else if (eep->baseEepHeader.dacHiPwrMode_5G)
1926 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
1927 else
1928 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
1929 eep->baseEepHeader.dacLpMode);
1930
1931 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
1932 pModal->miscBits >> 2);
1933
1934 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
1935 AR_PHY_TX_DESIRED_SCALE_CCK,
1936 eep->baseEepHeader.desiredScaleCCK);
1937 }
1938
1939 return true;
1940 #undef AR5416_VER_MASK
1941 }
1942
1943 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
1944 struct ath9k_channel *chan)
1945 {
1946 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
1947 struct modal_eep_header *pModal;
1948 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1949 u8 biaslevel;
1950
1951 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1952 return;
1953
1954 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1955 return;
1956
1957 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1958
1959 if (pModal->xpaBiasLvl != 0xff) {
1960 biaslevel = pModal->xpaBiasLvl;
1961 } else {
1962 u16 resetFreqBin, freqBin, freqCount = 0;
1963 struct chan_centers centers;
1964
1965 ath9k_hw_get_channel_centers(ah, chan, &centers);
1966
1967 resetFreqBin = FREQ2FBIN(centers.synth_center,
1968 IS_CHAN_2GHZ(chan));
1969 freqBin = XPA_LVL_FREQ(0) & 0xff;
1970 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
1971
1972 freqCount++;
1973
1974 while (freqCount < 3) {
1975 if (XPA_LVL_FREQ(freqCount) == 0x0)
1976 break;
1977
1978 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
1979 if (resetFreqBin >= freqBin)
1980 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
1981 else
1982 break;
1983 freqCount++;
1984 }
1985 }
1986
1987 if (IS_CHAN_2GHZ(chan)) {
1988 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
1989 7, 1) & (~0x18)) | biaslevel << 3;
1990 } else {
1991 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
1992 6, 1) & (~0xc0)) | biaslevel << 6;
1993 }
1994 #undef XPA_LVL_FREQ
1995 }
1996
1997 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
1998 struct ath9k_channel *chan,
1999 struct cal_data_per_freq *pRawDataSet,
2000 u8 *bChans, u16 availPiers,
2001 u16 tPdGainOverlap, int16_t *pMinCalPower,
2002 u16 *pPdGainBoundaries, u8 *pPDADCValues,
2003 u16 numXpdGains)
2004 {
2005 int i, j, k;
2006 int16_t ss;
2007 u16 idxL = 0, idxR = 0, numPiers;
2008 static u8 vpdTableL[AR5416_NUM_PD_GAINS]
2009 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2010 static u8 vpdTableR[AR5416_NUM_PD_GAINS]
2011 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2012 static u8 vpdTableI[AR5416_NUM_PD_GAINS]
2013 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2014
2015 u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
2016 u8 minPwrT4[AR5416_NUM_PD_GAINS];
2017 u8 maxPwrT4[AR5416_NUM_PD_GAINS];
2018 int16_t vpdStep;
2019 int16_t tmpVal;
2020 u16 sizeCurrVpdTable, maxIndex, tgtIndex;
2021 bool match;
2022 int16_t minDelta = 0;
2023 struct chan_centers centers;
2024
2025 ath9k_hw_get_channel_centers(ah, chan, &centers);
2026
2027 for (numPiers = 0; numPiers < availPiers; numPiers++) {
2028 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
2029 break;
2030 }
2031
2032 match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
2033 IS_CHAN_2GHZ(chan)),
2034 bChans, numPiers, &idxL, &idxR);
2035
2036 if (match) {
2037 for (i = 0; i < numXpdGains; i++) {
2038 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
2039 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
2040 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2041 pRawDataSet[idxL].pwrPdg[i],
2042 pRawDataSet[idxL].vpdPdg[i],
2043 AR5416_PD_GAIN_ICEPTS,
2044 vpdTableI[i]);
2045 }
2046 } else {
2047 for (i = 0; i < numXpdGains; i++) {
2048 pVpdL = pRawDataSet[idxL].vpdPdg[i];
2049 pPwrL = pRawDataSet[idxL].pwrPdg[i];
2050 pVpdR = pRawDataSet[idxR].vpdPdg[i];
2051 pPwrR = pRawDataSet[idxR].pwrPdg[i];
2052
2053 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
2054
2055 maxPwrT4[i] =
2056 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
2057 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
2058
2059
2060 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2061 pPwrL, pVpdL,
2062 AR5416_PD_GAIN_ICEPTS,
2063 vpdTableL[i]);
2064 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2065 pPwrR, pVpdR,
2066 AR5416_PD_GAIN_ICEPTS,
2067 vpdTableR[i]);
2068
2069 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
2070 vpdTableI[i][j] =
2071 (u8)(ath9k_hw_interpolate((u16)
2072 FREQ2FBIN(centers.
2073 synth_center,
2074 IS_CHAN_2GHZ
2075 (chan)),
2076 bChans[idxL], bChans[idxR],
2077 vpdTableL[i][j], vpdTableR[i][j]));
2078 }
2079 }
2080 }
2081
2082 *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
2083
2084 k = 0;
2085
2086 for (i = 0; i < numXpdGains; i++) {
2087 if (i == (numXpdGains - 1))
2088 pPdGainBoundaries[i] =
2089 (u16)(maxPwrT4[i] / 2);
2090 else
2091 pPdGainBoundaries[i] =
2092 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
2093
2094 pPdGainBoundaries[i] =
2095 min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
2096
2097 if ((i == 0) && !AR_SREV_5416_20_OR_LATER(ah)) {
2098 minDelta = pPdGainBoundaries[0] - 23;
2099 pPdGainBoundaries[0] = 23;
2100 } else {
2101 minDelta = 0;
2102 }
2103
2104 if (i == 0) {
2105 if (AR_SREV_9280_10_OR_LATER(ah))
2106 ss = (int16_t)(0 - (minPwrT4[i] / 2));
2107 else
2108 ss = 0;
2109 } else {
2110 ss = (int16_t)((pPdGainBoundaries[i - 1] -
2111 (minPwrT4[i] / 2)) -
2112 tPdGainOverlap + 1 + minDelta);
2113 }
2114 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
2115 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2116
2117 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2118 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
2119 pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
2120 ss++;
2121 }
2122
2123 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
2124 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
2125 (minPwrT4[i] / 2));
2126 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
2127 tgtIndex : sizeCurrVpdTable;
2128
2129 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2130 pPDADCValues[k++] = vpdTableI[i][ss++];
2131 }
2132
2133 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
2134 vpdTableI[i][sizeCurrVpdTable - 2]);
2135 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2136
2137 if (tgtIndex > maxIndex) {
2138 while ((ss <= tgtIndex) &&
2139 (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2140 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
2141 (ss - maxIndex + 1) * vpdStep));
2142 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
2143 255 : tmpVal);
2144 ss++;
2145 }
2146 }
2147 }
2148
2149 while (i < AR5416_PD_GAINS_IN_MASK) {
2150 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
2151 i++;
2152 }
2153
2154 while (k < AR5416_NUM_PDADC_VALUES) {
2155 pPDADCValues[k] = pPDADCValues[k - 1];
2156 k++;
2157 }
2158
2159 return;
2160 }
2161
2162 static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2163 struct ath9k_channel *chan,
2164 int16_t *pTxPowerIndexOffset)
2165 {
2166 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
2167 #define SM_PDGAIN_B(x, y) \
2168 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
2169
2170 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2171 struct cal_data_per_freq *pRawDataset;
2172 u8 *pCalBChans = NULL;
2173 u16 pdGainOverlap_t2;
2174 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
2175 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
2176 u16 numPiers, i, j;
2177 int16_t tMinCalPower;
2178 u16 numXpdGain, xpdMask;
2179 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
2180 u32 reg32, regOffset, regChainOffset;
2181 int16_t modalIdx;
2182
2183 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
2184 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
2185
2186 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2187 AR5416_EEP_MINOR_VER_2) {
2188 pdGainOverlap_t2 =
2189 pEepData->modalHeader[modalIdx].pdGainOverlap;
2190 } else {
2191 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
2192 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
2193 }
2194
2195 if (IS_CHAN_2GHZ(chan)) {
2196 pCalBChans = pEepData->calFreqPier2G;
2197 numPiers = AR5416_NUM_2G_CAL_PIERS;
2198 } else {
2199 pCalBChans = pEepData->calFreqPier5G;
2200 numPiers = AR5416_NUM_5G_CAL_PIERS;
2201 }
2202
2203 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
2204 pRawDataset = pEepData->calPierData2G[0];
2205 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
2206 pRawDataset)->vpdPdg[0][0];
2207 }
2208
2209 numXpdGain = 0;
2210
2211 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
2212 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
2213 if (numXpdGain >= AR5416_NUM_PD_GAINS)
2214 break;
2215 xpdGainValues[numXpdGain] =
2216 (u16)(AR5416_PD_GAINS_IN_MASK - i);
2217 numXpdGain++;
2218 }
2219 }
2220
2221 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
2222 (numXpdGain - 1) & 0x3);
2223 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
2224 xpdGainValues[0]);
2225 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
2226 xpdGainValues[1]);
2227 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
2228 xpdGainValues[2]);
2229
2230 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2231 if (AR_SREV_5416_20_OR_LATER(ah) &&
2232 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
2233 (i != 0)) {
2234 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2235 } else
2236 regChainOffset = i * 0x1000;
2237
2238 if (pEepData->baseEepHeader.txMask & (1 << i)) {
2239 if (IS_CHAN_2GHZ(chan))
2240 pRawDataset = pEepData->calPierData2G[i];
2241 else
2242 pRawDataset = pEepData->calPierData5G[i];
2243
2244
2245 if (OLC_FOR_AR9280_20_LATER) {
2246 u8 pcdacIdx;
2247 u8 txPower;
2248
2249 ath9k_get_txgain_index(ah, chan,
2250 (struct calDataPerFreqOpLoop *)pRawDataset,
2251 pCalBChans, numPiers, &txPower, &pcdacIdx);
2252 ath9k_olc_get_pdadcs(ah, pcdacIdx,
2253 txPower/2, pdadcValues);
2254 } else {
2255 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
2256 chan, pRawDataset,
2257 pCalBChans, numPiers,
2258 pdGainOverlap_t2,
2259 &tMinCalPower,
2260 gainBoundaries,
2261 pdadcValues,
2262 numXpdGain);
2263 }
2264
2265 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
2266 if (OLC_FOR_AR9280_20_LATER) {
2267 REG_WRITE(ah,
2268 AR_PHY_TPCRG5 + regChainOffset,
2269 SM(0x6,
2270 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
2271 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
2272 SM_PD_GAIN(3) | SM_PD_GAIN(4));
2273 } else {
2274 REG_WRITE(ah,
2275 AR_PHY_TPCRG5 + regChainOffset,
2276 SM(pdGainOverlap_t2,
2277 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
2278 SM_PDGAIN_B(0, 1) |
2279 SM_PDGAIN_B(1, 2) |
2280 SM_PDGAIN_B(2, 3) |
2281 SM_PDGAIN_B(3, 4));
2282 }
2283 }
2284
2285 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
2286 for (j = 0; j < 32; j++) {
2287 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
2288 ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
2289 ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
2290 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
2291 REG_WRITE(ah, regOffset, reg32);
2292
2293 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2294 "PDADC (%d,%4x): %4.4x %8.8x\n",
2295 i, regChainOffset, regOffset,
2296 reg32);
2297 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2298 "PDADC: Chain %d | PDADC %3d "
2299 "Value %3d | PDADC %3d Value %3d | "
2300 "PDADC %3d Value %3d | PDADC %3d "
2301 "Value %3d |\n",
2302 i, 4 * j, pdadcValues[4 * j],
2303 4 * j + 1, pdadcValues[4 * j + 1],
2304 4 * j + 2, pdadcValues[4 * j + 2],
2305 4 * j + 3,
2306 pdadcValues[4 * j + 3]);
2307
2308 regOffset += 4;
2309 }
2310 }
2311 }
2312
2313 *pTxPowerIndexOffset = 0;
2314
2315 return true;
2316 #undef SM_PD_GAIN
2317 #undef SM_PDGAIN_B
2318 }
2319
2320 static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2321 struct ath9k_channel *chan,
2322 int16_t *ratesArray,
2323 u16 cfgCtl,
2324 u16 AntennaReduction,
2325 u16 twiceMaxRegulatoryPower,
2326 u16 powerLimit)
2327 {
2328 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
2329 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
2330
2331 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2332 u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2333 static const u16 tpScaleReductionTable[5] =
2334 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
2335
2336 int i;
2337 int16_t twiceLargestAntenna;
2338 struct cal_ctl_data *rep;
2339 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
2340 0, { 0, 0, 0, 0}
2341 };
2342 struct cal_target_power_leg targetPowerOfdmExt = {
2343 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
2344 0, { 0, 0, 0, 0 }
2345 };
2346 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
2347 0, {0, 0, 0, 0}
2348 };
2349 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
2350 u16 ctlModesFor11a[] =
2351 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
2352 u16 ctlModesFor11g[] =
2353 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
2354 CTL_2GHT40
2355 };
2356 u16 numCtlModes, *pCtlMode, ctlMode, freq;
2357 struct chan_centers centers;
2358 int tx_chainmask;
2359 u16 twiceMinEdgePower;
2360
2361 tx_chainmask = ah->txchainmask;
2362
2363 ath9k_hw_get_channel_centers(ah, chan, &centers);
2364
2365 twiceLargestAntenna = max(
2366 pEepData->modalHeader
2367 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
2368 pEepData->modalHeader
2369 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
2370
2371 twiceLargestAntenna = max((u8)twiceLargestAntenna,
2372 pEepData->modalHeader
2373 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
2374
2375 twiceLargestAntenna = (int16_t)min(AntennaReduction -
2376 twiceLargestAntenna, 0);
2377
2378 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
2379
2380 if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
2381 maxRegAllowedPower -=
2382 (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
2383 }
2384
2385 scaledPower = min(powerLimit, maxRegAllowedPower);
2386
2387 switch (ar5416_get_ntxchains(tx_chainmask)) {
2388 case 1:
2389 break;
2390 case 2:
2391 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
2392 break;
2393 case 3:
2394 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
2395 break;
2396 }
2397
2398 scaledPower = max((u16)0, scaledPower);
2399
2400 if (IS_CHAN_2GHZ(chan)) {
2401 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
2402 SUB_NUM_CTL_MODES_AT_2G_40;
2403 pCtlMode = ctlModesFor11g;
2404
2405 ath9k_hw_get_legacy_target_powers(ah, chan,
2406 pEepData->calTargetPowerCck,
2407 AR5416_NUM_2G_CCK_TARGET_POWERS,
2408 &targetPowerCck, 4, false);
2409 ath9k_hw_get_legacy_target_powers(ah, chan,
2410 pEepData->calTargetPower2G,
2411 AR5416_NUM_2G_20_TARGET_POWERS,
2412 &targetPowerOfdm, 4, false);
2413 ath9k_hw_get_target_powers(ah, chan,
2414 pEepData->calTargetPower2GHT20,
2415 AR5416_NUM_2G_20_TARGET_POWERS,
2416 &targetPowerHt20, 8, false);
2417
2418 if (IS_CHAN_HT40(chan)) {
2419 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
2420 ath9k_hw_get_target_powers(ah, chan,
2421 pEepData->calTargetPower2GHT40,
2422 AR5416_NUM_2G_40_TARGET_POWERS,
2423 &targetPowerHt40, 8, true);
2424 ath9k_hw_get_legacy_target_powers(ah, chan,
2425 pEepData->calTargetPowerCck,
2426 AR5416_NUM_2G_CCK_TARGET_POWERS,
2427 &targetPowerCckExt, 4, true);
2428 ath9k_hw_get_legacy_target_powers(ah, chan,
2429 pEepData->calTargetPower2G,
2430 AR5416_NUM_2G_20_TARGET_POWERS,
2431 &targetPowerOfdmExt, 4, true);
2432 }
2433 } else {
2434 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
2435 SUB_NUM_CTL_MODES_AT_5G_40;
2436 pCtlMode = ctlModesFor11a;
2437
2438 ath9k_hw_get_legacy_target_powers(ah, chan,
2439 pEepData->calTargetPower5G,
2440 AR5416_NUM_5G_20_TARGET_POWERS,
2441 &targetPowerOfdm, 4, false);
2442 ath9k_hw_get_target_powers(ah, chan,
2443 pEepData->calTargetPower5GHT20,
2444 AR5416_NUM_5G_20_TARGET_POWERS,
2445 &targetPowerHt20, 8, false);
2446
2447 if (IS_CHAN_HT40(chan)) {
2448 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
2449 ath9k_hw_get_target_powers(ah, chan,
2450 pEepData->calTargetPower5GHT40,
2451 AR5416_NUM_5G_40_TARGET_POWERS,
2452 &targetPowerHt40, 8, true);
2453 ath9k_hw_get_legacy_target_powers(ah, chan,
2454 pEepData->calTargetPower5G,
2455 AR5416_NUM_5G_20_TARGET_POWERS,
2456 &targetPowerOfdmExt, 4, true);
2457 }
2458 }
2459
2460 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
2461 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
2462 (pCtlMode[ctlMode] == CTL_2GHT40);
2463 if (isHt40CtlMode)
2464 freq = centers.synth_center;
2465 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
2466 freq = centers.ext_center;
2467 else
2468 freq = centers.ctl_center;
2469
2470 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
2471 ah->eep_ops->get_eeprom_rev(ah) <= 2)
2472 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2473
2474 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2475 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
2476 "EXT_ADDITIVE %d\n",
2477 ctlMode, numCtlModes, isHt40CtlMode,
2478 (pCtlMode[ctlMode] & EXT_ADDITIVE));
2479
2480 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
2481 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2482 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
2483 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
2484 "chan %d\n",
2485 i, cfgCtl, pCtlMode[ctlMode],
2486 pEepData->ctlIndex[i], chan->channel);
2487
2488 if ((((cfgCtl & ~CTL_MODE_M) |
2489 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2490 pEepData->ctlIndex[i]) ||
2491 (((cfgCtl & ~CTL_MODE_M) |
2492 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2493 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
2494 rep = &(pEepData->ctlData[i]);
2495
2496 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
2497 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
2498 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
2499
2500 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2501 " MATCH-EE_IDX %d: ch %d is2 %d "
2502 "2xMinEdge %d chainmask %d chains %d\n",
2503 i, freq, IS_CHAN_2GHZ(chan),
2504 twiceMinEdgePower, tx_chainmask,
2505 ar5416_get_ntxchains
2506 (tx_chainmask));
2507 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
2508 twiceMaxEdgePower = min(twiceMaxEdgePower,
2509 twiceMinEdgePower);
2510 } else {
2511 twiceMaxEdgePower = twiceMinEdgePower;
2512 break;
2513 }
2514 }
2515 }
2516
2517 minCtlPower = min(twiceMaxEdgePower, scaledPower);
2518
2519 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2520 " SEL-Min ctlMode %d pCtlMode %d "
2521 "2xMaxEdge %d sP %d minCtlPwr %d\n",
2522 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
2523 scaledPower, minCtlPower);
2524
2525 switch (pCtlMode[ctlMode]) {
2526 case CTL_11B:
2527 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
2528 targetPowerCck.tPow2x[i] =
2529 min((u16)targetPowerCck.tPow2x[i],
2530 minCtlPower);
2531 }
2532 break;
2533 case CTL_11A:
2534 case CTL_11G:
2535 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
2536 targetPowerOfdm.tPow2x[i] =
2537 min((u16)targetPowerOfdm.tPow2x[i],
2538 minCtlPower);
2539 }
2540 break;
2541 case CTL_5GHT20:
2542 case CTL_2GHT20:
2543 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
2544 targetPowerHt20.tPow2x[i] =
2545 min((u16)targetPowerHt20.tPow2x[i],
2546 minCtlPower);
2547 }
2548 break;
2549 case CTL_11B_EXT:
2550 targetPowerCckExt.tPow2x[0] = min((u16)
2551 targetPowerCckExt.tPow2x[0],
2552 minCtlPower);
2553 break;
2554 case CTL_11A_EXT:
2555 case CTL_11G_EXT:
2556 targetPowerOfdmExt.tPow2x[0] = min((u16)
2557 targetPowerOfdmExt.tPow2x[0],
2558 minCtlPower);
2559 break;
2560 case CTL_5GHT40:
2561 case CTL_2GHT40:
2562 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2563 targetPowerHt40.tPow2x[i] =
2564 min((u16)targetPowerHt40.tPow2x[i],
2565 minCtlPower);
2566 }
2567 break;
2568 default:
2569 break;
2570 }
2571 }
2572
2573 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
2574 ratesArray[rate18mb] = ratesArray[rate24mb] =
2575 targetPowerOfdm.tPow2x[0];
2576 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
2577 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
2578 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
2579 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
2580
2581 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
2582 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
2583
2584 if (IS_CHAN_2GHZ(chan)) {
2585 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
2586 ratesArray[rate2s] = ratesArray[rate2l] =
2587 targetPowerCck.tPow2x[1];
2588 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
2589 targetPowerCck.tPow2x[2];
2590 ;
2591 ratesArray[rate11s] = ratesArray[rate11l] =
2592 targetPowerCck.tPow2x[3];
2593 ;
2594 }
2595 if (IS_CHAN_HT40(chan)) {
2596 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2597 ratesArray[rateHt40_0 + i] =
2598 targetPowerHt40.tPow2x[i];
2599 }
2600 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
2601 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
2602 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
2603 if (IS_CHAN_2GHZ(chan)) {
2604 ratesArray[rateExtCck] =
2605 targetPowerCckExt.tPow2x[0];
2606 }
2607 }
2608 return true;
2609 }
2610
2611 static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
2612 struct ath9k_channel *chan,
2613 u16 cfgCtl,
2614 u8 twiceAntennaReduction,
2615 u8 twiceMaxRegulatoryPower,
2616 u8 powerLimit)
2617 {
2618 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
2619 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2620 struct modal_eep_header *pModal =
2621 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
2622 int16_t ratesArray[Ar5416RateSize];
2623 int16_t txPowerIndexOffset = 0;
2624 u8 ht40PowerIncForPdadc = 2;
2625 int i, cck_ofdm_delta = 0;
2626
2627 memset(ratesArray, 0, sizeof(ratesArray));
2628
2629 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2630 AR5416_EEP_MINOR_VER_2) {
2631 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
2632 }
2633
2634 if (!ath9k_hw_set_def_power_per_rate_table(ah, chan,
2635 &ratesArray[0], cfgCtl,
2636 twiceAntennaReduction,
2637 twiceMaxRegulatoryPower,
2638 powerLimit)) {
2639 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2640 "ath9k_hw_set_txpower: unable to set "
2641 "tx power per rate table\n");
2642 return -EIO;
2643 }
2644
2645 if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) {
2646 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2647 "ath9k_hw_set_txpower: unable to set power table\n");
2648 return -EIO;
2649 }
2650
2651 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
2652 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
2653 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
2654 ratesArray[i] = AR5416_MAX_RATE_POWER;
2655 }
2656
2657 if (AR_SREV_9280_10_OR_LATER(ah)) {
2658 for (i = 0; i < Ar5416RateSize; i++)
2659 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
2660 }
2661
2662 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
2663 ATH9K_POW_SM(ratesArray[rate18mb], 24)
2664 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
2665 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
2666 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
2667 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
2668 ATH9K_POW_SM(ratesArray[rate54mb], 24)
2669 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
2670 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
2671 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
2672
2673 if (IS_CHAN_2GHZ(chan)) {
2674 if (OLC_FOR_AR9280_20_LATER) {
2675 cck_ofdm_delta = 2;
2676 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2677 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
2678 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
2679 | ATH9K_POW_SM(ratesArray[rateXr], 8)
2680 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
2681 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2682 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
2683 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
2684 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
2685 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
2686 } else {
2687 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2688 ATH9K_POW_SM(ratesArray[rate2s], 24)
2689 | ATH9K_POW_SM(ratesArray[rate2l], 16)
2690 | ATH9K_POW_SM(ratesArray[rateXr], 8)
2691 | ATH9K_POW_SM(ratesArray[rate1l], 0));
2692 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2693 ATH9K_POW_SM(ratesArray[rate11s], 24)
2694 | ATH9K_POW_SM(ratesArray[rate11l], 16)
2695 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
2696 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
2697 }
2698 }
2699
2700 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
2701 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
2702 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
2703 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
2704 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
2705 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
2706 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
2707 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
2708 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
2709 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
2710
2711 if (IS_CHAN_HT40(chan)) {
2712 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
2713 ATH9K_POW_SM(ratesArray[rateHt40_3] +
2714 ht40PowerIncForPdadc, 24)
2715 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
2716 ht40PowerIncForPdadc, 16)
2717 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
2718 ht40PowerIncForPdadc, 8)
2719 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
2720 ht40PowerIncForPdadc, 0));
2721 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
2722 ATH9K_POW_SM(ratesArray[rateHt40_7] +
2723 ht40PowerIncForPdadc, 24)
2724 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
2725 ht40PowerIncForPdadc, 16)
2726 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
2727 ht40PowerIncForPdadc, 8)
2728 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
2729 ht40PowerIncForPdadc, 0));
2730 if (OLC_FOR_AR9280_20_LATER) {
2731 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2732 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
2733 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
2734 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
2735 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
2736 } else {
2737 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2738 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
2739 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
2740 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
2741 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
2742 }
2743 }
2744
2745 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2746 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
2747 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
2748
2749 i = rate6mb;
2750
2751 if (IS_CHAN_HT40(chan))
2752 i = rateHt40_0;
2753 else if (IS_CHAN_HT20(chan))
2754 i = rateHt20_0;
2755
2756 if (AR_SREV_9280_10_OR_LATER(ah))
2757 ah->regulatory.max_power_level =
2758 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
2759 else
2760 ah->regulatory.max_power_level = ratesArray[i];
2761
2762 switch(ar5416_get_ntxchains(ah->txchainmask)) {
2763 case 1:
2764 break;
2765 case 2:
2766 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
2767 break;
2768 case 3:
2769 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
2770 break;
2771 default:
2772 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2773 "Invalid chainmask configuration\n");
2774 break;
2775 }
2776
2777 return 0;
2778 }
2779
2780 static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
2781 enum ieee80211_band freq_band)
2782 {
2783 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2784 struct modal_eep_header *pModal =
2785 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
2786 struct base_eep_header *pBase = &eep->baseEepHeader;
2787 u8 num_ant_config;
2788
2789 num_ant_config = 1;
2790
2791 if (pBase->version >= 0x0E0D)
2792 if (pModal->useAnt1)
2793 num_ant_config += 1;
2794
2795 return num_ant_config;
2796 }
2797
2798 static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
2799 struct ath9k_channel *chan)
2800 {
2801 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2802 struct modal_eep_header *pModal =
2803 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2804
2805 return pModal->antCtrlCommon & 0xFFFF;
2806 }
2807
2808 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
2809 {
2810 #define EEP_DEF_SPURCHAN \
2811 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
2812
2813 u16 spur_val = AR_NO_SPUR;
2814
2815 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2816 "Getting spur idx %d is2Ghz. %d val %x\n",
2817 i, is2GHz, ah->config.spurchans[i][is2GHz]);
2818
2819 switch (ah->config.spurmode) {
2820 case SPUR_DISABLE:
2821 break;
2822 case SPUR_ENABLE_IOCTL:
2823 spur_val = ah->config.spurchans[i][is2GHz];
2824 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2825 "Getting spur val from new loc. %d\n", spur_val);
2826 break;
2827 case SPUR_ENABLE_EEPROM:
2828 spur_val = EEP_DEF_SPURCHAN;
2829 break;
2830 }
2831
2832 return spur_val;
2833
2834 #undef EEP_DEF_SPURCHAN
2835 }
2836
2837 static struct eeprom_ops eep_def_ops = {
2838 .check_eeprom = ath9k_hw_def_check_eeprom,
2839 .get_eeprom = ath9k_hw_def_get_eeprom,
2840 .fill_eeprom = ath9k_hw_def_fill_eeprom,
2841 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
2842 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
2843 .get_num_ant_config = ath9k_hw_def_get_num_ant_config,
2844 .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
2845 .set_board_values = ath9k_hw_def_set_board_values,
2846 .set_addac = ath9k_hw_def_set_addac,
2847 .set_txpower = ath9k_hw_def_set_txpower,
2848 .get_spur_channel = ath9k_hw_def_get_spur_channel
2849 };
2850
2851 int ath9k_hw_eeprom_attach(struct ath_hw *ah)
2852 {
2853 int status;
2854
2855 if (AR_SREV_9285(ah)) {
2856 ah->eep_map = EEP_MAP_4KBITS;
2857 ah->eep_ops = &eep_4k_ops;
2858 } else {
2859 ah->eep_map = EEP_MAP_DEFAULT;
2860 ah->eep_ops = &eep_def_ops;
2861 }
2862
2863 if (!ah->eep_ops->fill_eeprom(ah))
2864 return -EIO;
2865
2866 status = ah->eep_ops->check_eeprom(ah);
2867
2868 return status;
2869 }
Ubuntu Artful kernel mirror