2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 static void ath9k_hw_analog_shift_rmw(struct ath_hw
*ah
,
25 regVal
= REG_READ(ah
, reg
) & ~mask
;
26 regVal
|= (val
<< shift
) & mask
;
28 REG_WRITE(ah
, reg
, regVal
);
30 if (ah
->config
.analog_shiftreg
)
36 static inline u16
ath9k_hw_fbin2freq(u8 fbin
, bool is2GHz
)
39 if (fbin
== AR5416_BCHAN_UNUSED
)
42 return (u16
) ((is2GHz
) ? (2300 + fbin
) : (4800 + 5 * fbin
));
45 static inline int16_t ath9k_hw_interpolate(u16 target
,
46 u16 srcLeft
, u16 srcRight
,
52 if (srcRight
== srcLeft
) {
55 rv
= (int16_t) (((target
- srcLeft
) * targetRight
+
56 (srcRight
- target
) * targetLeft
) /
57 (srcRight
- srcLeft
));
62 static inline bool ath9k_hw_get_lower_upper_index(u8 target
, u8
*pList
,
63 u16 listSize
, u16
*indexL
,
68 if (target
<= pList
[0]) {
69 *indexL
= *indexR
= 0;
72 if (target
>= pList
[listSize
- 1]) {
73 *indexL
= *indexR
= (u16
) (listSize
- 1);
77 for (i
= 0; i
< listSize
- 1; i
++) {
78 if (pList
[i
] == target
) {
79 *indexL
= *indexR
= i
;
82 if (target
< pList
[i
+ 1]) {
84 *indexR
= (u16
) (i
+ 1);
91 static inline bool ath9k_hw_nvram_read(struct ath_hw
*ah
, u32 off
, u16
*data
)
93 struct ath_softc
*sc
= ah
->ah_sc
;
95 return sc
->bus_ops
->eeprom_read(ah
, off
, data
);
98 static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin
, u8 pwrMax
, u8
*pPwrList
,
99 u8
*pVpdList
, u16 numIntercepts
,
104 u16 idxL
= 0, idxR
= 0;
106 for (i
= 0; i
<= (pwrMax
- pwrMin
) / 2; i
++) {
107 ath9k_hw_get_lower_upper_index(currPwr
, pPwrList
,
108 numIntercepts
, &(idxL
),
112 if (idxL
== numIntercepts
- 1)
113 idxL
= (u16
) (numIntercepts
- 2);
114 if (pPwrList
[idxL
] == pPwrList
[idxR
])
117 k
= (u16
)(((currPwr
- pPwrList
[idxL
]) * pVpdList
[idxR
] +
118 (pPwrList
[idxR
] - currPwr
) * pVpdList
[idxL
]) /
119 (pPwrList
[idxR
] - pPwrList
[idxL
]));
120 pRetVpdList
[i
] = (u8
) k
;
127 static void ath9k_hw_get_legacy_target_powers(struct ath_hw
*ah
,
128 struct ath9k_channel
*chan
,
129 struct cal_target_power_leg
*powInfo
,
131 struct cal_target_power_leg
*pNewPower
,
132 u16 numRates
, bool isExtTarget
)
134 struct chan_centers centers
;
137 int matchIndex
= -1, lowIndex
= -1;
140 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
141 freq
= (isExtTarget
) ? centers
.ext_center
: centers
.ctl_center
;
143 if (freq
<= ath9k_hw_fbin2freq(powInfo
[0].bChannel
,
144 IS_CHAN_2GHZ(chan
))) {
147 for (i
= 0; (i
< numChannels
) &&
148 (powInfo
[i
].bChannel
!= AR5416_BCHAN_UNUSED
); i
++) {
149 if (freq
== ath9k_hw_fbin2freq(powInfo
[i
].bChannel
,
150 IS_CHAN_2GHZ(chan
))) {
153 } else if ((freq
< ath9k_hw_fbin2freq(powInfo
[i
].bChannel
,
154 IS_CHAN_2GHZ(chan
))) &&
155 (freq
> ath9k_hw_fbin2freq(powInfo
[i
- 1].bChannel
,
156 IS_CHAN_2GHZ(chan
)))) {
161 if ((matchIndex
== -1) && (lowIndex
== -1))
165 if (matchIndex
!= -1) {
166 *pNewPower
= powInfo
[matchIndex
];
168 clo
= ath9k_hw_fbin2freq(powInfo
[lowIndex
].bChannel
,
170 chi
= ath9k_hw_fbin2freq(powInfo
[lowIndex
+ 1].bChannel
,
173 for (i
= 0; i
< numRates
; i
++) {
174 pNewPower
->tPow2x
[i
] =
175 (u8
)ath9k_hw_interpolate(freq
, clo
, chi
,
176 powInfo
[lowIndex
].tPow2x
[i
],
177 powInfo
[lowIndex
+ 1].tPow2x
[i
]);
182 static void ath9k_get_txgain_index(struct ath_hw
*ah
,
183 struct ath9k_channel
*chan
,
184 struct calDataPerFreqOpLoop
*rawDatasetOpLoop
,
185 u8
*calChans
, u16 availPiers
, u8
*pwr
, u8
*pcdacIdx
)
188 u16 idxL
= 0, idxR
= 0, numPiers
;
190 struct chan_centers centers
;
192 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
194 for (numPiers
= 0; numPiers
< availPiers
; numPiers
++)
195 if (calChans
[numPiers
] == AR5416_BCHAN_UNUSED
)
198 match
= ath9k_hw_get_lower_upper_index(
199 (u8
)FREQ2FBIN(centers
.synth_center
, IS_CHAN_2GHZ(chan
)),
200 calChans
, numPiers
, &idxL
, &idxR
);
202 pcdac
= rawDatasetOpLoop
[idxL
].pcdac
[0][0];
203 *pwr
= rawDatasetOpLoop
[idxL
].pwrPdg
[0][0];
205 pcdac
= rawDatasetOpLoop
[idxR
].pcdac
[0][0];
206 *pwr
= (rawDatasetOpLoop
[idxL
].pwrPdg
[0][0] +
207 rawDatasetOpLoop
[idxR
].pwrPdg
[0][0])/2;
210 while (pcdac
> ah
->originalGain
[i
] &&
211 i
< (AR9280_TX_GAIN_TABLE_SIZE
- 1))
218 static void ath9k_olc_get_pdadcs(struct ath_hw
*ah
,
226 REG_RMW_FIELD(ah
, AR_PHY_TX_PWRCTRL6_0
,
227 AR_PHY_TX_PWRCTRL_ERR_EST_MODE
, 3);
228 REG_RMW_FIELD(ah
, AR_PHY_TX_PWRCTRL6_1
,
229 AR_PHY_TX_PWRCTRL_ERR_EST_MODE
, 3);
231 REG_RMW_FIELD(ah
, AR_PHY_TX_PWRCTRL7
,
232 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN
, initTxGain
);
235 for (i
= 0; i
< AR5416_NUM_PDADC_VALUES
; i
++)
237 pPDADCValues
[i
] = 0x0;
239 pPDADCValues
[i
] = 0xFF;
245 static void ath9k_hw_get_target_powers(struct ath_hw
*ah
,
246 struct ath9k_channel
*chan
,
247 struct cal_target_power_ht
*powInfo
,
249 struct cal_target_power_ht
*pNewPower
,
250 u16 numRates
, bool isHt40Target
)
252 struct chan_centers centers
;
255 int matchIndex
= -1, lowIndex
= -1;
258 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
259 freq
= isHt40Target
? centers
.synth_center
: centers
.ctl_center
;
261 if (freq
<= ath9k_hw_fbin2freq(powInfo
[0].bChannel
, IS_CHAN_2GHZ(chan
))) {
264 for (i
= 0; (i
< numChannels
) &&
265 (powInfo
[i
].bChannel
!= AR5416_BCHAN_UNUSED
); i
++) {
266 if (freq
== ath9k_hw_fbin2freq(powInfo
[i
].bChannel
,
267 IS_CHAN_2GHZ(chan
))) {
271 if ((freq
< ath9k_hw_fbin2freq(powInfo
[i
].bChannel
,
272 IS_CHAN_2GHZ(chan
))) &&
273 (freq
> ath9k_hw_fbin2freq(powInfo
[i
- 1].bChannel
,
274 IS_CHAN_2GHZ(chan
)))) {
279 if ((matchIndex
== -1) && (lowIndex
== -1))
283 if (matchIndex
!= -1) {
284 *pNewPower
= powInfo
[matchIndex
];
286 clo
= ath9k_hw_fbin2freq(powInfo
[lowIndex
].bChannel
,
288 chi
= ath9k_hw_fbin2freq(powInfo
[lowIndex
+ 1].bChannel
,
291 for (i
= 0; i
< numRates
; i
++) {
292 pNewPower
->tPow2x
[i
] = (u8
)ath9k_hw_interpolate(freq
,
294 powInfo
[lowIndex
].tPow2x
[i
],
295 powInfo
[lowIndex
+ 1].tPow2x
[i
]);
300 static u16
ath9k_hw_get_max_edge_power(u16 freq
,
301 struct cal_ctl_edges
*pRdEdgesPower
,
302 bool is2GHz
, int num_band_edges
)
304 u16 twiceMaxEdgePower
= AR5416_MAX_RATE_POWER
;
307 for (i
= 0; (i
< num_band_edges
) &&
308 (pRdEdgesPower
[i
].bChannel
!= AR5416_BCHAN_UNUSED
); i
++) {
309 if (freq
== ath9k_hw_fbin2freq(pRdEdgesPower
[i
].bChannel
, is2GHz
)) {
310 twiceMaxEdgePower
= pRdEdgesPower
[i
].tPower
;
312 } else if ((i
> 0) &&
313 (freq
< ath9k_hw_fbin2freq(pRdEdgesPower
[i
].bChannel
,
315 if (ath9k_hw_fbin2freq(pRdEdgesPower
[i
- 1].bChannel
,
317 pRdEdgesPower
[i
- 1].flag
) {
319 pRdEdgesPower
[i
- 1].tPower
;
325 return twiceMaxEdgePower
;
328 /****************************************/
329 /* EEPROM Operations for 4K sized cards */
330 /****************************************/
332 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw
*ah
)
334 return ((ah
->eeprom
.map4k
.baseEepHeader
.version
>> 12) & 0xF);
337 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw
*ah
)
339 return ((ah
->eeprom
.map4k
.baseEepHeader
.version
) & 0xFFF);
342 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw
*ah
)
344 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
345 u16
*eep_data
= (u16
*)&ah
->eeprom
.map4k
;
346 int addr
, eep_start_loc
= 0;
350 if (!ath9k_hw_use_flash(ah
)) {
351 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
352 "Reading from EEPROM, not flash\n");
355 for (addr
= 0; addr
< SIZE_EEPROM_4K
; addr
++) {
356 if (!ath9k_hw_nvram_read(ah
, addr
+ eep_start_loc
, eep_data
)) {
357 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
358 "Unable to read eeprom region \n");
365 #undef SIZE_EEPROM_4K
368 static int ath9k_hw_4k_check_eeprom(struct ath_hw
*ah
)
370 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
371 struct ar5416_eeprom_4k
*eep
=
372 (struct ar5416_eeprom_4k
*) &ah
->eeprom
.map4k
;
373 u16
*eepdata
, temp
, magic
, magic2
;
375 bool need_swap
= false;
379 if (!ath9k_hw_use_flash(ah
)) {
380 if (!ath9k_hw_nvram_read(ah
, AR5416_EEPROM_MAGIC_OFFSET
,
382 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
383 "Reading Magic # failed\n");
387 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
388 "Read Magic = 0x%04X\n", magic
);
390 if (magic
!= AR5416_EEPROM_MAGIC
) {
391 magic2
= swab16(magic
);
393 if (magic2
== AR5416_EEPROM_MAGIC
) {
395 eepdata
= (u16
*) (&ah
->eeprom
);
397 for (addr
= 0; addr
< EEPROM_4K_SIZE
; addr
++) {
398 temp
= swab16(*eepdata
);
403 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
404 "Invalid EEPROM Magic. "
405 "endianness mismatch.\n");
411 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
, "need_swap = %s.\n",
412 need_swap
? "True" : "False");
415 el
= swab16(ah
->eeprom
.map4k
.baseEepHeader
.length
);
417 el
= ah
->eeprom
.map4k
.baseEepHeader
.length
;
419 if (el
> sizeof(struct ar5416_eeprom_4k
))
420 el
= sizeof(struct ar5416_eeprom_4k
) / sizeof(u16
);
422 el
= el
/ sizeof(u16
);
424 eepdata
= (u16
*)(&ah
->eeprom
);
426 for (i
= 0; i
< el
; i
++)
433 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
434 "EEPROM Endianness is not native.. Changing\n");
436 word
= swab16(eep
->baseEepHeader
.length
);
437 eep
->baseEepHeader
.length
= word
;
439 word
= swab16(eep
->baseEepHeader
.checksum
);
440 eep
->baseEepHeader
.checksum
= word
;
442 word
= swab16(eep
->baseEepHeader
.version
);
443 eep
->baseEepHeader
.version
= word
;
445 word
= swab16(eep
->baseEepHeader
.regDmn
[0]);
446 eep
->baseEepHeader
.regDmn
[0] = word
;
448 word
= swab16(eep
->baseEepHeader
.regDmn
[1]);
449 eep
->baseEepHeader
.regDmn
[1] = word
;
451 word
= swab16(eep
->baseEepHeader
.rfSilent
);
452 eep
->baseEepHeader
.rfSilent
= word
;
454 word
= swab16(eep
->baseEepHeader
.blueToothOptions
);
455 eep
->baseEepHeader
.blueToothOptions
= word
;
457 word
= swab16(eep
->baseEepHeader
.deviceCap
);
458 eep
->baseEepHeader
.deviceCap
= word
;
460 integer
= swab32(eep
->modalHeader
.antCtrlCommon
);
461 eep
->modalHeader
.antCtrlCommon
= integer
;
463 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
464 integer
= swab32(eep
->modalHeader
.antCtrlChain
[i
]);
465 eep
->modalHeader
.antCtrlChain
[i
] = integer
;
468 for (i
= 0; i
< AR5416_EEPROM_MODAL_SPURS
; i
++) {
469 word
= swab16(eep
->modalHeader
.spurChans
[i
].spurChan
);
470 eep
->modalHeader
.spurChans
[i
].spurChan
= word
;
474 if (sum
!= 0xffff || ah
->eep_ops
->get_eeprom_ver(ah
) != AR5416_EEP_VER
||
475 ah
->eep_ops
->get_eeprom_rev(ah
) < AR5416_EEP_NO_BACK_VER
) {
476 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
477 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
478 sum
, ah
->eep_ops
->get_eeprom_ver(ah
));
483 #undef EEPROM_4K_SIZE
486 static u32
ath9k_hw_4k_get_eeprom(struct ath_hw
*ah
,
487 enum eeprom_param param
)
489 struct ar5416_eeprom_4k
*eep
= &ah
->eeprom
.map4k
;
490 struct modal_eep_4k_header
*pModal
= &eep
->modalHeader
;
491 struct base_eep_header_4k
*pBase
= &eep
->baseEepHeader
;
495 return pModal
->noiseFloorThreshCh
[0];
496 case AR_EEPROM_MAC(0):
497 return pBase
->macAddr
[0] << 8 | pBase
->macAddr
[1];
498 case AR_EEPROM_MAC(1):
499 return pBase
->macAddr
[2] << 8 | pBase
->macAddr
[3];
500 case AR_EEPROM_MAC(2):
501 return pBase
->macAddr
[4] << 8 | pBase
->macAddr
[5];
503 return pBase
->regDmn
[0];
505 return pBase
->regDmn
[1];
507 return pBase
->deviceCap
;
509 return pBase
->opCapFlags
;
511 return pBase
->rfSilent
;
513 return pModal
->ob_01
;
515 return pModal
->db1_01
;
517 return pBase
->version
& AR5416_EEP_VER_MINOR_MASK
;
519 return pBase
->txMask
;
521 return pBase
->rxMask
;
529 static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw
*ah
,
530 struct ath9k_channel
*chan
,
531 struct cal_data_per_freq_4k
*pRawDataSet
,
532 u8
*bChans
, u16 availPiers
,
533 u16 tPdGainOverlap
, int16_t *pMinCalPower
,
534 u16
*pPdGainBoundaries
, u8
*pPDADCValues
,
537 #define TMP_VAL_VPD_TABLE \
538 ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
541 u16 idxL
= 0, idxR
= 0, numPiers
;
542 static u8 vpdTableL
[AR5416_EEP4K_NUM_PD_GAINS
]
543 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
544 static u8 vpdTableR
[AR5416_EEP4K_NUM_PD_GAINS
]
545 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
546 static u8 vpdTableI
[AR5416_EEP4K_NUM_PD_GAINS
]
547 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
549 u8
*pVpdL
, *pVpdR
, *pPwrL
, *pPwrR
;
550 u8 minPwrT4
[AR5416_EEP4K_NUM_PD_GAINS
];
551 u8 maxPwrT4
[AR5416_EEP4K_NUM_PD_GAINS
];
554 u16 sizeCurrVpdTable
, maxIndex
, tgtIndex
;
556 int16_t minDelta
= 0;
557 struct chan_centers centers
;
558 #define PD_GAIN_BOUNDARY_DEFAULT 58;
560 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
562 for (numPiers
= 0; numPiers
< availPiers
; numPiers
++) {
563 if (bChans
[numPiers
] == AR5416_BCHAN_UNUSED
)
567 match
= ath9k_hw_get_lower_upper_index(
568 (u8
)FREQ2FBIN(centers
.synth_center
,
569 IS_CHAN_2GHZ(chan
)), bChans
, numPiers
,
573 for (i
= 0; i
< numXpdGains
; i
++) {
574 minPwrT4
[i
] = pRawDataSet
[idxL
].pwrPdg
[i
][0];
575 maxPwrT4
[i
] = pRawDataSet
[idxL
].pwrPdg
[i
][4];
576 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
577 pRawDataSet
[idxL
].pwrPdg
[i
],
578 pRawDataSet
[idxL
].vpdPdg
[i
],
579 AR5416_EEP4K_PD_GAIN_ICEPTS
,
583 for (i
= 0; i
< numXpdGains
; i
++) {
584 pVpdL
= pRawDataSet
[idxL
].vpdPdg
[i
];
585 pPwrL
= pRawDataSet
[idxL
].pwrPdg
[i
];
586 pVpdR
= pRawDataSet
[idxR
].vpdPdg
[i
];
587 pPwrR
= pRawDataSet
[idxR
].pwrPdg
[i
];
589 minPwrT4
[i
] = max(pPwrL
[0], pPwrR
[0]);
592 min(pPwrL
[AR5416_EEP4K_PD_GAIN_ICEPTS
- 1],
593 pPwrR
[AR5416_EEP4K_PD_GAIN_ICEPTS
- 1]);
596 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
598 AR5416_EEP4K_PD_GAIN_ICEPTS
,
600 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
602 AR5416_EEP4K_PD_GAIN_ICEPTS
,
605 for (j
= 0; j
<= (maxPwrT4
[i
] - minPwrT4
[i
]) / 2; j
++) {
607 (u8
)(ath9k_hw_interpolate((u16
)
612 bChans
[idxL
], bChans
[idxR
],
613 vpdTableL
[i
][j
], vpdTableR
[i
][j
]));
618 *pMinCalPower
= (int16_t)(minPwrT4
[0] / 2);
622 for (i
= 0; i
< numXpdGains
; i
++) {
623 if (i
== (numXpdGains
- 1))
624 pPdGainBoundaries
[i
] =
625 (u16
)(maxPwrT4
[i
] / 2);
627 pPdGainBoundaries
[i
] =
628 (u16
)((maxPwrT4
[i
] + minPwrT4
[i
+ 1]) / 4);
630 pPdGainBoundaries
[i
] =
631 min((u16
)AR5416_MAX_RATE_POWER
, pPdGainBoundaries
[i
]);
633 if ((i
== 0) && !AR_SREV_5416_20_OR_LATER(ah
)) {
634 minDelta
= pPdGainBoundaries
[0] - 23;
635 pPdGainBoundaries
[0] = 23;
641 if (AR_SREV_9280_10_OR_LATER(ah
))
642 ss
= (int16_t)(0 - (minPwrT4
[i
] / 2));
646 ss
= (int16_t)((pPdGainBoundaries
[i
- 1] -
648 tPdGainOverlap
+ 1 + minDelta
);
650 vpdStep
= (int16_t)(vpdTableI
[i
][1] - vpdTableI
[i
][0]);
651 vpdStep
= (int16_t)((vpdStep
< 1) ? 1 : vpdStep
);
653 while ((ss
< 0) && (k
< (AR5416_NUM_PDADC_VALUES
- 1))) {
654 tmpVal
= (int16_t)(vpdTableI
[i
][0] + ss
* vpdStep
);
655 pPDADCValues
[k
++] = (u8
)((tmpVal
< 0) ? 0 : tmpVal
);
659 sizeCurrVpdTable
= (u8
) ((maxPwrT4
[i
] - minPwrT4
[i
]) / 2 + 1);
660 tgtIndex
= (u8
)(pPdGainBoundaries
[i
] + tPdGainOverlap
-
662 maxIndex
= (tgtIndex
< sizeCurrVpdTable
) ?
663 tgtIndex
: sizeCurrVpdTable
;
665 while ((ss
< maxIndex
) && (k
< (AR5416_NUM_PDADC_VALUES
- 1)))
666 pPDADCValues
[k
++] = vpdTableI
[i
][ss
++];
668 vpdStep
= (int16_t)(vpdTableI
[i
][sizeCurrVpdTable
- 1] -
669 vpdTableI
[i
][sizeCurrVpdTable
- 2]);
670 vpdStep
= (int16_t)((vpdStep
< 1) ? 1 : vpdStep
);
672 if (tgtIndex
>= maxIndex
) {
673 while ((ss
<= tgtIndex
) &&
674 (k
< (AR5416_NUM_PDADC_VALUES
- 1))) {
675 tmpVal
= (int16_t) TMP_VAL_VPD_TABLE
;
676 pPDADCValues
[k
++] = (u8
)((tmpVal
> 255) ?
683 while (i
< AR5416_EEP4K_PD_GAINS_IN_MASK
) {
684 pPdGainBoundaries
[i
] = PD_GAIN_BOUNDARY_DEFAULT
;
688 while (k
< AR5416_NUM_PDADC_VALUES
) {
689 pPDADCValues
[k
] = pPDADCValues
[k
- 1];
694 #undef TMP_VAL_VPD_TABLE
697 static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw
*ah
,
698 struct ath9k_channel
*chan
,
699 int16_t *pTxPowerIndexOffset
)
701 struct ar5416_eeprom_4k
*pEepData
= &ah
->eeprom
.map4k
;
702 struct cal_data_per_freq_4k
*pRawDataset
;
703 u8
*pCalBChans
= NULL
;
704 u16 pdGainOverlap_t2
;
705 static u8 pdadcValues
[AR5416_NUM_PDADC_VALUES
];
706 u16 gainBoundaries
[AR5416_EEP4K_PD_GAINS_IN_MASK
];
708 int16_t tMinCalPower
;
709 u16 numXpdGain
, xpdMask
;
710 u16 xpdGainValues
[AR5416_EEP4K_NUM_PD_GAINS
] = { 0, 0 };
711 u32 reg32
, regOffset
, regChainOffset
;
713 xpdMask
= pEepData
->modalHeader
.xpdGain
;
715 if ((pEepData
->baseEepHeader
.version
& AR5416_EEP_VER_MINOR_MASK
) >=
716 AR5416_EEP_MINOR_VER_2
) {
718 pEepData
->modalHeader
.pdGainOverlap
;
720 pdGainOverlap_t2
= (u16
)(MS(REG_READ(ah
, AR_PHY_TPCRG5
),
721 AR_PHY_TPCRG5_PD_GAIN_OVERLAP
));
724 pCalBChans
= pEepData
->calFreqPier2G
;
725 numPiers
= AR5416_EEP4K_NUM_2G_CAL_PIERS
;
729 for (i
= 1; i
<= AR5416_EEP4K_PD_GAINS_IN_MASK
; i
++) {
730 if ((xpdMask
>> (AR5416_EEP4K_PD_GAINS_IN_MASK
- i
)) & 1) {
731 if (numXpdGain
>= AR5416_EEP4K_NUM_PD_GAINS
)
733 xpdGainValues
[numXpdGain
] =
734 (u16
)(AR5416_EEP4K_PD_GAINS_IN_MASK
- i
);
739 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_NUM_PD_GAIN
,
740 (numXpdGain
- 1) & 0x3);
741 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_1
,
743 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_2
,
745 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_3
, 0);
747 for (i
= 0; i
< AR5416_EEP4K_MAX_CHAINS
; i
++) {
748 if (AR_SREV_5416_20_OR_LATER(ah
) &&
749 (ah
->rxchainmask
== 5 || ah
->txchainmask
== 5) &&
751 regChainOffset
= (i
== 1) ? 0x2000 : 0x1000;
753 regChainOffset
= i
* 0x1000;
755 if (pEepData
->baseEepHeader
.txMask
& (1 << i
)) {
756 pRawDataset
= pEepData
->calPierData2G
[i
];
758 ath9k_hw_get_4k_gain_boundaries_pdadcs(ah
, chan
,
759 pRawDataset
, pCalBChans
,
760 numPiers
, pdGainOverlap_t2
,
761 &tMinCalPower
, gainBoundaries
,
762 pdadcValues
, numXpdGain
);
764 if ((i
== 0) || AR_SREV_5416_20_OR_LATER(ah
)) {
765 REG_WRITE(ah
, AR_PHY_TPCRG5
+ regChainOffset
,
767 AR_PHY_TPCRG5_PD_GAIN_OVERLAP
)
768 | SM(gainBoundaries
[0],
769 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1
)
770 | SM(gainBoundaries
[1],
771 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2
)
772 | SM(gainBoundaries
[2],
773 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3
)
774 | SM(gainBoundaries
[3],
775 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4
));
778 regOffset
= AR_PHY_BASE
+ (672 << 2) + regChainOffset
;
779 for (j
= 0; j
< 32; j
++) {
780 reg32
= ((pdadcValues
[4 * j
+ 0] & 0xFF) << 0) |
781 ((pdadcValues
[4 * j
+ 1] & 0xFF) << 8) |
782 ((pdadcValues
[4 * j
+ 2] & 0xFF) << 16)|
783 ((pdadcValues
[4 * j
+ 3] & 0xFF) << 24);
784 REG_WRITE(ah
, regOffset
, reg32
);
786 DPRINTF(ah
->ah_sc
, ATH_DBG_REG_IO
,
787 "PDADC (%d,%4x): %4.4x %8.8x\n",
788 i
, regChainOffset
, regOffset
,
790 DPRINTF(ah
->ah_sc
, ATH_DBG_REG_IO
,
792 "PDADC %3d Value %3d | "
793 "PDADC %3d Value %3d | "
794 "PDADC %3d Value %3d | "
795 "PDADC %3d Value %3d |\n",
796 i
, 4 * j
, pdadcValues
[4 * j
],
797 4 * j
+ 1, pdadcValues
[4 * j
+ 1],
798 4 * j
+ 2, pdadcValues
[4 * j
+ 2],
800 pdadcValues
[4 * j
+ 3]);
807 *pTxPowerIndexOffset
= 0;
812 static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw
*ah
,
813 struct ath9k_channel
*chan
,
816 u16 AntennaReduction
,
817 u16 twiceMaxRegulatoryPower
,
820 struct ar5416_eeprom_4k
*pEepData
= &ah
->eeprom
.map4k
;
821 u16 twiceMaxEdgePower
= AR5416_MAX_RATE_POWER
;
822 static const u16 tpScaleReductionTable
[5] =
823 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER
};
826 int16_t twiceLargestAntenna
;
827 struct cal_ctl_data_4k
*rep
;
828 struct cal_target_power_leg targetPowerOfdm
, targetPowerCck
= {
831 struct cal_target_power_leg targetPowerOfdmExt
= {
832 0, { 0, 0, 0, 0} }, targetPowerCckExt
= {
835 struct cal_target_power_ht targetPowerHt20
, targetPowerHt40
= {
838 u16 scaledPower
= 0, minCtlPower
, maxRegAllowedPower
;
839 u16 ctlModesFor11g
[] =
840 { CTL_11B
, CTL_11G
, CTL_2GHT20
, CTL_11B_EXT
, CTL_11G_EXT
,
843 u16 numCtlModes
, *pCtlMode
, ctlMode
, freq
;
844 struct chan_centers centers
;
846 u16 twiceMinEdgePower
;
848 tx_chainmask
= ah
->txchainmask
;
850 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
852 twiceLargestAntenna
= pEepData
->modalHeader
.antennaGainCh
[0];
854 twiceLargestAntenna
= (int16_t)min(AntennaReduction
-
855 twiceLargestAntenna
, 0);
857 maxRegAllowedPower
= twiceMaxRegulatoryPower
+ twiceLargestAntenna
;
859 if (ah
->regulatory
.tp_scale
!= ATH9K_TP_SCALE_MAX
) {
860 maxRegAllowedPower
-=
861 (tpScaleReductionTable
[(ah
->regulatory
.tp_scale
)] * 2);
864 scaledPower
= min(powerLimit
, maxRegAllowedPower
);
865 scaledPower
= max((u16
)0, scaledPower
);
867 numCtlModes
= ARRAY_SIZE(ctlModesFor11g
) - SUB_NUM_CTL_MODES_AT_2G_40
;
868 pCtlMode
= ctlModesFor11g
;
870 ath9k_hw_get_legacy_target_powers(ah
, chan
,
871 pEepData
->calTargetPowerCck
,
872 AR5416_NUM_2G_CCK_TARGET_POWERS
,
873 &targetPowerCck
, 4, false);
874 ath9k_hw_get_legacy_target_powers(ah
, chan
,
875 pEepData
->calTargetPower2G
,
876 AR5416_NUM_2G_20_TARGET_POWERS
,
877 &targetPowerOfdm
, 4, false);
878 ath9k_hw_get_target_powers(ah
, chan
,
879 pEepData
->calTargetPower2GHT20
,
880 AR5416_NUM_2G_20_TARGET_POWERS
,
881 &targetPowerHt20
, 8, false);
883 if (IS_CHAN_HT40(chan
)) {
884 numCtlModes
= ARRAY_SIZE(ctlModesFor11g
);
885 ath9k_hw_get_target_powers(ah
, chan
,
886 pEepData
->calTargetPower2GHT40
,
887 AR5416_NUM_2G_40_TARGET_POWERS
,
888 &targetPowerHt40
, 8, true);
889 ath9k_hw_get_legacy_target_powers(ah
, chan
,
890 pEepData
->calTargetPowerCck
,
891 AR5416_NUM_2G_CCK_TARGET_POWERS
,
892 &targetPowerCckExt
, 4, true);
893 ath9k_hw_get_legacy_target_powers(ah
, chan
,
894 pEepData
->calTargetPower2G
,
895 AR5416_NUM_2G_20_TARGET_POWERS
,
896 &targetPowerOfdmExt
, 4, true);
899 for (ctlMode
= 0; ctlMode
< numCtlModes
; ctlMode
++) {
900 bool isHt40CtlMode
= (pCtlMode
[ctlMode
] == CTL_5GHT40
) ||
901 (pCtlMode
[ctlMode
] == CTL_2GHT40
);
903 freq
= centers
.synth_center
;
904 else if (pCtlMode
[ctlMode
] & EXT_ADDITIVE
)
905 freq
= centers
.ext_center
;
907 freq
= centers
.ctl_center
;
909 if (ah
->eep_ops
->get_eeprom_ver(ah
) == 14 &&
910 ah
->eep_ops
->get_eeprom_rev(ah
) <= 2)
911 twiceMaxEdgePower
= AR5416_MAX_RATE_POWER
;
913 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
,
914 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
916 ctlMode
, numCtlModes
, isHt40CtlMode
,
917 (pCtlMode
[ctlMode
] & EXT_ADDITIVE
));
919 for (i
= 0; (i
< AR5416_NUM_CTLS
) &&
920 pEepData
->ctlIndex
[i
]; i
++) {
921 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
,
922 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
923 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
925 i
, cfgCtl
, pCtlMode
[ctlMode
],
926 pEepData
->ctlIndex
[i
], chan
->channel
);
928 if ((((cfgCtl
& ~CTL_MODE_M
) |
929 (pCtlMode
[ctlMode
] & CTL_MODE_M
)) ==
930 pEepData
->ctlIndex
[i
]) ||
931 (((cfgCtl
& ~CTL_MODE_M
) |
932 (pCtlMode
[ctlMode
] & CTL_MODE_M
)) ==
933 ((pEepData
->ctlIndex
[i
] & CTL_MODE_M
) |
935 rep
= &(pEepData
->ctlData
[i
]);
938 ath9k_hw_get_max_edge_power(freq
,
939 rep
->ctlEdges
[ar5416_get_ntxchains
942 AR5416_EEP4K_NUM_BAND_EDGES
);
944 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
,
945 " MATCH-EE_IDX %d: ch %d is2 %d "
946 "2xMinEdge %d chainmask %d chains %d\n",
947 i
, freq
, IS_CHAN_2GHZ(chan
),
948 twiceMinEdgePower
, tx_chainmask
,
951 if ((cfgCtl
& ~CTL_MODE_M
) == SD_NO_CTL
) {
953 min(twiceMaxEdgePower
,
956 twiceMaxEdgePower
= twiceMinEdgePower
;
962 minCtlPower
= (u8
)min(twiceMaxEdgePower
, scaledPower
);
964 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
,
965 " SEL-Min ctlMode %d pCtlMode %d "
966 "2xMaxEdge %d sP %d minCtlPwr %d\n",
967 ctlMode
, pCtlMode
[ctlMode
], twiceMaxEdgePower
,
968 scaledPower
, minCtlPower
);
970 switch (pCtlMode
[ctlMode
]) {
972 for (i
= 0; i
< ARRAY_SIZE(targetPowerCck
.tPow2x
);
974 targetPowerCck
.tPow2x
[i
] =
975 min((u16
)targetPowerCck
.tPow2x
[i
],
980 for (i
= 0; i
< ARRAY_SIZE(targetPowerOfdm
.tPow2x
);
982 targetPowerOfdm
.tPow2x
[i
] =
983 min((u16
)targetPowerOfdm
.tPow2x
[i
],
988 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt20
.tPow2x
);
990 targetPowerHt20
.tPow2x
[i
] =
991 min((u16
)targetPowerHt20
.tPow2x
[i
],
996 targetPowerCckExt
.tPow2x
[0] = min((u16
)
997 targetPowerCckExt
.tPow2x
[0],
1001 targetPowerOfdmExt
.tPow2x
[0] = min((u16
)
1002 targetPowerOfdmExt
.tPow2x
[0],
1006 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt40
.tPow2x
);
1008 targetPowerHt40
.tPow2x
[i
] =
1009 min((u16
)targetPowerHt40
.tPow2x
[i
],
1018 ratesArray
[rate6mb
] = ratesArray
[rate9mb
] = ratesArray
[rate12mb
] =
1019 ratesArray
[rate18mb
] = ratesArray
[rate24mb
] =
1020 targetPowerOfdm
.tPow2x
[0];
1021 ratesArray
[rate36mb
] = targetPowerOfdm
.tPow2x
[1];
1022 ratesArray
[rate48mb
] = targetPowerOfdm
.tPow2x
[2];
1023 ratesArray
[rate54mb
] = targetPowerOfdm
.tPow2x
[3];
1024 ratesArray
[rateXr
] = targetPowerOfdm
.tPow2x
[0];
1026 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt20
.tPow2x
); i
++)
1027 ratesArray
[rateHt20_0
+ i
] = targetPowerHt20
.tPow2x
[i
];
1029 ratesArray
[rate1l
] = targetPowerCck
.tPow2x
[0];
1030 ratesArray
[rate2s
] = ratesArray
[rate2l
] = targetPowerCck
.tPow2x
[1];
1031 ratesArray
[rate5_5s
] = ratesArray
[rate5_5l
] = targetPowerCck
.tPow2x
[2];
1032 ratesArray
[rate11s
] = ratesArray
[rate11l
] = targetPowerCck
.tPow2x
[3];
1034 if (IS_CHAN_HT40(chan
)) {
1035 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt40
.tPow2x
); i
++) {
1036 ratesArray
[rateHt40_0
+ i
] =
1037 targetPowerHt40
.tPow2x
[i
];
1039 ratesArray
[rateDupOfdm
] = targetPowerHt40
.tPow2x
[0];
1040 ratesArray
[rateDupCck
] = targetPowerHt40
.tPow2x
[0];
1041 ratesArray
[rateExtOfdm
] = targetPowerOfdmExt
.tPow2x
[0];
1042 ratesArray
[rateExtCck
] = targetPowerCckExt
.tPow2x
[0];
1047 static int ath9k_hw_4k_set_txpower(struct ath_hw
*ah
,
1048 struct ath9k_channel
*chan
,
1050 u8 twiceAntennaReduction
,
1051 u8 twiceMaxRegulatoryPower
,
1054 struct ar5416_eeprom_4k
*pEepData
= &ah
->eeprom
.map4k
;
1055 struct modal_eep_4k_header
*pModal
= &pEepData
->modalHeader
;
1056 int16_t ratesArray
[Ar5416RateSize
];
1057 int16_t txPowerIndexOffset
= 0;
1058 u8 ht40PowerIncForPdadc
= 2;
1061 memset(ratesArray
, 0, sizeof(ratesArray
));
1063 if ((pEepData
->baseEepHeader
.version
& AR5416_EEP_VER_MINOR_MASK
) >=
1064 AR5416_EEP_MINOR_VER_2
) {
1065 ht40PowerIncForPdadc
= pModal
->ht40PowerIncForPdadc
;
1068 if (!ath9k_hw_set_4k_power_per_rate_table(ah
, chan
,
1069 &ratesArray
[0], cfgCtl
,
1070 twiceAntennaReduction
,
1071 twiceMaxRegulatoryPower
,
1073 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
1074 "ath9k_hw_set_txpower: unable to set "
1075 "tx power per rate table\n");
1079 if (!ath9k_hw_set_4k_power_cal_table(ah
, chan
, &txPowerIndexOffset
)) {
1080 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
1081 "ath9k_hw_set_txpower: unable to set power table\n");
1085 for (i
= 0; i
< ARRAY_SIZE(ratesArray
); i
++) {
1086 ratesArray
[i
] = (int16_t)(txPowerIndexOffset
+ ratesArray
[i
]);
1087 if (ratesArray
[i
] > AR5416_MAX_RATE_POWER
)
1088 ratesArray
[i
] = AR5416_MAX_RATE_POWER
;
1091 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1092 for (i
= 0; i
< Ar5416RateSize
; i
++)
1093 ratesArray
[i
] -= AR5416_PWR_TABLE_OFFSET
* 2;
1096 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE1
,
1097 ATH9K_POW_SM(ratesArray
[rate18mb
], 24)
1098 | ATH9K_POW_SM(ratesArray
[rate12mb
], 16)
1099 | ATH9K_POW_SM(ratesArray
[rate9mb
], 8)
1100 | ATH9K_POW_SM(ratesArray
[rate6mb
], 0));
1101 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE2
,
1102 ATH9K_POW_SM(ratesArray
[rate54mb
], 24)
1103 | ATH9K_POW_SM(ratesArray
[rate48mb
], 16)
1104 | ATH9K_POW_SM(ratesArray
[rate36mb
], 8)
1105 | ATH9K_POW_SM(ratesArray
[rate24mb
], 0));
1107 if (IS_CHAN_2GHZ(chan
)) {
1108 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE3
,
1109 ATH9K_POW_SM(ratesArray
[rate2s
], 24)
1110 | ATH9K_POW_SM(ratesArray
[rate2l
], 16)
1111 | ATH9K_POW_SM(ratesArray
[rateXr
], 8)
1112 | ATH9K_POW_SM(ratesArray
[rate1l
], 0));
1113 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE4
,
1114 ATH9K_POW_SM(ratesArray
[rate11s
], 24)
1115 | ATH9K_POW_SM(ratesArray
[rate11l
], 16)
1116 | ATH9K_POW_SM(ratesArray
[rate5_5s
], 8)
1117 | ATH9K_POW_SM(ratesArray
[rate5_5l
], 0));
1120 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE5
,
1121 ATH9K_POW_SM(ratesArray
[rateHt20_3
], 24)
1122 | ATH9K_POW_SM(ratesArray
[rateHt20_2
], 16)
1123 | ATH9K_POW_SM(ratesArray
[rateHt20_1
], 8)
1124 | ATH9K_POW_SM(ratesArray
[rateHt20_0
], 0));
1125 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE6
,
1126 ATH9K_POW_SM(ratesArray
[rateHt20_7
], 24)
1127 | ATH9K_POW_SM(ratesArray
[rateHt20_6
], 16)
1128 | ATH9K_POW_SM(ratesArray
[rateHt20_5
], 8)
1129 | ATH9K_POW_SM(ratesArray
[rateHt20_4
], 0));
1131 if (IS_CHAN_HT40(chan
)) {
1132 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE7
,
1133 ATH9K_POW_SM(ratesArray
[rateHt40_3
] +
1134 ht40PowerIncForPdadc
, 24)
1135 | ATH9K_POW_SM(ratesArray
[rateHt40_2
] +
1136 ht40PowerIncForPdadc
, 16)
1137 | ATH9K_POW_SM(ratesArray
[rateHt40_1
] +
1138 ht40PowerIncForPdadc
, 8)
1139 | ATH9K_POW_SM(ratesArray
[rateHt40_0
] +
1140 ht40PowerIncForPdadc
, 0));
1141 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE8
,
1142 ATH9K_POW_SM(ratesArray
[rateHt40_7
] +
1143 ht40PowerIncForPdadc
, 24)
1144 | ATH9K_POW_SM(ratesArray
[rateHt40_6
] +
1145 ht40PowerIncForPdadc
, 16)
1146 | ATH9K_POW_SM(ratesArray
[rateHt40_5
] +
1147 ht40PowerIncForPdadc
, 8)
1148 | ATH9K_POW_SM(ratesArray
[rateHt40_4
] +
1149 ht40PowerIncForPdadc
, 0));
1151 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE9
,
1152 ATH9K_POW_SM(ratesArray
[rateExtOfdm
], 24)
1153 | ATH9K_POW_SM(ratesArray
[rateExtCck
], 16)
1154 | ATH9K_POW_SM(ratesArray
[rateDupOfdm
], 8)
1155 | ATH9K_POW_SM(ratesArray
[rateDupCck
], 0));
1160 if (IS_CHAN_HT40(chan
))
1162 else if (IS_CHAN_HT20(chan
))
1165 if (AR_SREV_9280_10_OR_LATER(ah
))
1166 ah
->regulatory
.max_power_level
=
1167 ratesArray
[i
] + AR5416_PWR_TABLE_OFFSET
* 2;
1169 ah
->regulatory
.max_power_level
= ratesArray
[i
];
1174 static void ath9k_hw_4k_set_addac(struct ath_hw
*ah
,
1175 struct ath9k_channel
*chan
)
1177 struct modal_eep_4k_header
*pModal
;
1178 struct ar5416_eeprom_4k
*eep
= &ah
->eeprom
.map4k
;
1181 if (ah
->hw_version
.macVersion
!= AR_SREV_VERSION_9160
)
1184 if (ah
->eep_ops
->get_eeprom_rev(ah
) < AR5416_EEP_MINOR_VER_7
)
1187 pModal
= &eep
->modalHeader
;
1189 if (pModal
->xpaBiasLvl
!= 0xff) {
1190 biaslevel
= pModal
->xpaBiasLvl
;
1191 INI_RA(&ah
->iniAddac
, 7, 1) =
1192 (INI_RA(&ah
->iniAddac
, 7, 1) & (~0x18)) | biaslevel
<< 3;
1196 static void ath9k_hw_4k_set_gain(struct ath_hw
*ah
,
1197 struct modal_eep_4k_header
*pModal
,
1198 struct ar5416_eeprom_4k
*eep
,
1199 u8 txRxAttenLocal
, int regChainOffset
)
1201 REG_WRITE(ah
, AR_PHY_SWITCH_CHAIN_0
+ regChainOffset
,
1202 pModal
->antCtrlChain
[0]);
1204 REG_WRITE(ah
, AR_PHY_TIMING_CTRL4(0) + regChainOffset
,
1205 (REG_READ(ah
, AR_PHY_TIMING_CTRL4(0) + regChainOffset
) &
1206 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
|
1207 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
)) |
1208 SM(pModal
->iqCalICh
[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
) |
1209 SM(pModal
->iqCalQCh
[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
));
1211 if ((eep
->baseEepHeader
.version
& AR5416_EEP_VER_MINOR_MASK
) >=
1212 AR5416_EEP_MINOR_VER_3
) {
1213 txRxAttenLocal
= pModal
->txRxAttenCh
[0];
1215 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1216 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN
, pModal
->bswMargin
[0]);
1217 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1218 AR_PHY_GAIN_2GHZ_XATTEN1_DB
, pModal
->bswAtten
[0]);
1219 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1220 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN
,
1221 pModal
->xatten2Margin
[0]);
1222 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1223 AR_PHY_GAIN_2GHZ_XATTEN2_DB
, pModal
->xatten2Db
[0]);
1226 REG_RMW_FIELD(ah
, AR_PHY_RXGAIN
+ regChainOffset
,
1227 AR9280_PHY_RXGAIN_TXRX_ATTEN
, txRxAttenLocal
);
1228 REG_RMW_FIELD(ah
, AR_PHY_RXGAIN
+ regChainOffset
,
1229 AR9280_PHY_RXGAIN_TXRX_MARGIN
, pModal
->rxTxMarginCh
[0]);
1231 if (AR_SREV_9285_11(ah
))
1232 REG_WRITE(ah
, AR9285_AN_TOP4
, (AR9285_AN_TOP4_DEFAULT
| 0x14));
1235 static void ath9k_hw_4k_set_board_values(struct ath_hw
*ah
,
1236 struct ath9k_channel
*chan
)
1238 struct modal_eep_4k_header
*pModal
;
1239 struct ar5416_eeprom_4k
*eep
= &ah
->eeprom
.map4k
;
1241 u8 ob
[5], db1
[5], db2
[5];
1242 u8 ant_div_control1
, ant_div_control2
;
1245 pModal
= &eep
->modalHeader
;
1246 txRxAttenLocal
= 23;
1248 REG_WRITE(ah
, AR_PHY_SWITCH_COM
,
1249 ah
->eep_ops
->get_eeprom_antenna_cfg(ah
, chan
));
1251 /* Single chain for 4K EEPROM*/
1252 ath9k_hw_4k_set_gain(ah
, pModal
, eep
, txRxAttenLocal
, 0);
1254 /* Initialize Ant Diversity settings from EEPROM */
1255 if (pModal
->version
== 3) {
1256 ant_div_control1
= ((pModal
->ob_234
>> 12) & 0xf);
1257 ant_div_control2
= ((pModal
->db1_234
>> 12) & 0xf);
1258 regVal
= REG_READ(ah
, 0x99ac);
1259 regVal
&= (~(0x7f000000));
1260 regVal
|= ((ant_div_control1
& 0x1) << 24);
1261 regVal
|= (((ant_div_control1
>> 1) & 0x1) << 29);
1262 regVal
|= (((ant_div_control1
>> 2) & 0x1) << 30);
1263 regVal
|= ((ant_div_control2
& 0x3) << 25);
1264 regVal
|= (((ant_div_control2
>> 2) & 0x3) << 27);
1265 REG_WRITE(ah
, 0x99ac, regVal
);
1266 regVal
= REG_READ(ah
, 0x99ac);
1267 regVal
= REG_READ(ah
, 0xa208);
1268 regVal
&= (~(0x1 << 13));
1269 regVal
|= (((ant_div_control1
>> 3) & 0x1) << 13);
1270 REG_WRITE(ah
, 0xa208, regVal
);
1271 regVal
= REG_READ(ah
, 0xa208);
1274 if (pModal
->version
>= 2) {
1275 ob
[0] = (pModal
->ob_01
& 0xf);
1276 ob
[1] = (pModal
->ob_01
>> 4) & 0xf;
1277 ob
[2] = (pModal
->ob_234
& 0xf);
1278 ob
[3] = ((pModal
->ob_234
>> 4) & 0xf);
1279 ob
[4] = ((pModal
->ob_234
>> 8) & 0xf);
1281 db1
[0] = (pModal
->db1_01
& 0xf);
1282 db1
[1] = ((pModal
->db1_01
>> 4) & 0xf);
1283 db1
[2] = (pModal
->db1_234
& 0xf);
1284 db1
[3] = ((pModal
->db1_234
>> 4) & 0xf);
1285 db1
[4] = ((pModal
->db1_234
>> 8) & 0xf);
1287 db2
[0] = (pModal
->db2_01
& 0xf);
1288 db2
[1] = ((pModal
->db2_01
>> 4) & 0xf);
1289 db2
[2] = (pModal
->db2_234
& 0xf);
1290 db2
[3] = ((pModal
->db2_234
>> 4) & 0xf);
1291 db2
[4] = ((pModal
->db2_234
>> 8) & 0xf);
1293 } else if (pModal
->version
== 1) {
1294 ob
[0] = (pModal
->ob_01
& 0xf);
1295 ob
[1] = ob
[2] = ob
[3] = ob
[4] = (pModal
->ob_01
>> 4) & 0xf;
1296 db1
[0] = (pModal
->db1_01
& 0xf);
1297 db1
[1] = db1
[2] = db1
[3] =
1298 db1
[4] = ((pModal
->db1_01
>> 4) & 0xf);
1299 db2
[0] = (pModal
->db2_01
& 0xf);
1300 db2
[1] = db2
[2] = db2
[3] =
1301 db2
[4] = ((pModal
->db2_01
>> 4) & 0xf);
1304 for (i
= 0; i
< 5; i
++) {
1305 ob
[i
] = pModal
->ob_01
;
1306 db1
[i
] = pModal
->db1_01
;
1307 db2
[i
] = pModal
->db1_01
;
1311 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G3
,
1312 AR9285_AN_RF2G3_OB_0
, AR9285_AN_RF2G3_OB_0_S
, ob
[0]);
1313 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G3
,
1314 AR9285_AN_RF2G3_OB_1
, AR9285_AN_RF2G3_OB_1_S
, ob
[1]);
1315 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G3
,
1316 AR9285_AN_RF2G3_OB_2
, AR9285_AN_RF2G3_OB_2_S
, ob
[2]);
1317 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G3
,
1318 AR9285_AN_RF2G3_OB_3
, AR9285_AN_RF2G3_OB_3_S
, ob
[3]);
1319 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G3
,
1320 AR9285_AN_RF2G3_OB_4
, AR9285_AN_RF2G3_OB_4_S
, ob
[4]);
1322 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G3
,
1323 AR9285_AN_RF2G3_DB1_0
, AR9285_AN_RF2G3_DB1_0_S
, db1
[0]);
1324 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G3
,
1325 AR9285_AN_RF2G3_DB1_1
, AR9285_AN_RF2G3_DB1_1_S
, db1
[1]);
1326 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G3
,
1327 AR9285_AN_RF2G3_DB1_2
, AR9285_AN_RF2G3_DB1_2_S
, db1
[2]);
1328 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G4
,
1329 AR9285_AN_RF2G4_DB1_3
, AR9285_AN_RF2G4_DB1_3_S
, db1
[3]);
1330 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G4
,
1331 AR9285_AN_RF2G4_DB1_4
, AR9285_AN_RF2G4_DB1_4_S
, db1
[4]);
1333 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G4
,
1334 AR9285_AN_RF2G4_DB2_0
, AR9285_AN_RF2G4_DB2_0_S
, db2
[0]);
1335 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G4
,
1336 AR9285_AN_RF2G4_DB2_1
, AR9285_AN_RF2G4_DB2_1_S
, db2
[1]);
1337 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G4
,
1338 AR9285_AN_RF2G4_DB2_2
, AR9285_AN_RF2G4_DB2_2_S
, db2
[2]);
1339 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G4
,
1340 AR9285_AN_RF2G4_DB2_3
, AR9285_AN_RF2G4_DB2_3_S
, db2
[3]);
1341 ath9k_hw_analog_shift_rmw(ah
, AR9285_AN_RF2G4
,
1342 AR9285_AN_RF2G4_DB2_4
, AR9285_AN_RF2G4_DB2_4_S
, db2
[4]);
1345 if (AR_SREV_9285_11(ah
))
1346 REG_WRITE(ah
, AR9285_AN_TOP4
, AR9285_AN_TOP4_DEFAULT
);
1348 REG_RMW_FIELD(ah
, AR_PHY_SETTLING
, AR_PHY_SETTLING_SWITCH
,
1349 pModal
->switchSettling
);
1350 REG_RMW_FIELD(ah
, AR_PHY_DESIRED_SZ
, AR_PHY_DESIRED_SZ_ADC
,
1351 pModal
->adcDesiredSize
);
1353 REG_WRITE(ah
, AR_PHY_RF_CTL4
,
1354 SM(pModal
->txEndToXpaOff
, AR_PHY_RF_CTL4_TX_END_XPAA_OFF
) |
1355 SM(pModal
->txEndToXpaOff
, AR_PHY_RF_CTL4_TX_END_XPAB_OFF
) |
1356 SM(pModal
->txFrameToXpaOn
, AR_PHY_RF_CTL4_FRAME_XPAA_ON
) |
1357 SM(pModal
->txFrameToXpaOn
, AR_PHY_RF_CTL4_FRAME_XPAB_ON
));
1359 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL3
, AR_PHY_TX_END_TO_A2_RX_ON
,
1360 pModal
->txEndToRxOn
);
1361 REG_RMW_FIELD(ah
, AR_PHY_CCA
, AR9280_PHY_CCA_THRESH62
,
1363 REG_RMW_FIELD(ah
, AR_PHY_EXT_CCA0
, AR_PHY_EXT_CCA0_THRESH62
,
1366 if ((eep
->baseEepHeader
.version
& AR5416_EEP_VER_MINOR_MASK
) >=
1367 AR5416_EEP_MINOR_VER_2
) {
1368 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL2
, AR_PHY_TX_END_DATA_START
,
1369 pModal
->txFrameToDataStart
);
1370 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL2
, AR_PHY_TX_END_PA_ON
,
1371 pModal
->txFrameToPaOn
);
1374 if ((eep
->baseEepHeader
.version
& AR5416_EEP_VER_MINOR_MASK
) >=
1375 AR5416_EEP_MINOR_VER_3
) {
1376 if (IS_CHAN_HT40(chan
))
1377 REG_RMW_FIELD(ah
, AR_PHY_SETTLING
,
1378 AR_PHY_SETTLING_SWITCH
,
1379 pModal
->swSettleHt40
);
1383 static u16
ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw
*ah
,
1384 struct ath9k_channel
*chan
)
1386 struct ar5416_eeprom_4k
*eep
= &ah
->eeprom
.map4k
;
1387 struct modal_eep_4k_header
*pModal
= &eep
->modalHeader
;
1389 return pModal
->antCtrlCommon
& 0xFFFF;
1392 static u8
ath9k_hw_4k_get_num_ant_config(struct ath_hw
*ah
,
1393 enum ieee80211_band freq_band
)
1398 static u16
ath9k_hw_4k_get_spur_channel(struct ath_hw
*ah
, u16 i
, bool is2GHz
)
1400 #define EEP_MAP4K_SPURCHAN \
1401 (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1403 u16 spur_val
= AR_NO_SPUR
;
1405 DPRINTF(ah
->ah_sc
, ATH_DBG_ANI
,
1406 "Getting spur idx %d is2Ghz. %d val %x\n",
1407 i
, is2GHz
, ah
->config
.spurchans
[i
][is2GHz
]);
1409 switch (ah
->config
.spurmode
) {
1412 case SPUR_ENABLE_IOCTL
:
1413 spur_val
= ah
->config
.spurchans
[i
][is2GHz
];
1414 DPRINTF(ah
->ah_sc
, ATH_DBG_ANI
,
1415 "Getting spur val from new loc. %d\n", spur_val
);
1417 case SPUR_ENABLE_EEPROM
:
1418 spur_val
= EEP_MAP4K_SPURCHAN
;
1424 #undef EEP_MAP4K_SPURCHAN
1427 static struct eeprom_ops eep_4k_ops
= {
1428 .check_eeprom
= ath9k_hw_4k_check_eeprom
,
1429 .get_eeprom
= ath9k_hw_4k_get_eeprom
,
1430 .fill_eeprom
= ath9k_hw_4k_fill_eeprom
,
1431 .get_eeprom_ver
= ath9k_hw_4k_get_eeprom_ver
,
1432 .get_eeprom_rev
= ath9k_hw_4k_get_eeprom_rev
,
1433 .get_num_ant_config
= ath9k_hw_4k_get_num_ant_config
,
1434 .get_eeprom_antenna_cfg
= ath9k_hw_4k_get_eeprom_antenna_cfg
,
1435 .set_board_values
= ath9k_hw_4k_set_board_values
,
1436 .set_addac
= ath9k_hw_4k_set_addac
,
1437 .set_txpower
= ath9k_hw_4k_set_txpower
,
1438 .get_spur_channel
= ath9k_hw_4k_get_spur_channel
1441 /************************************************/
1442 /* EEPROM Operations for non-4K (Default) cards */
1443 /************************************************/
1445 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw
*ah
)
1447 return ((ah
->eeprom
.def
.baseEepHeader
.version
>> 12) & 0xF);
1450 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw
*ah
)
1452 return ((ah
->eeprom
.def
.baseEepHeader
.version
) & 0xFFF);
1455 static bool ath9k_hw_def_fill_eeprom(struct ath_hw
*ah
)
1457 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
1458 u16
*eep_data
= (u16
*)&ah
->eeprom
.def
;
1459 int addr
, ar5416_eep_start_loc
= 0x100;
1461 for (addr
= 0; addr
< SIZE_EEPROM_DEF
; addr
++) {
1462 if (!ath9k_hw_nvram_read(ah
, addr
+ ar5416_eep_start_loc
,
1464 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
1465 "Unable to read eeprom region\n");
1471 #undef SIZE_EEPROM_DEF
1474 static int ath9k_hw_def_check_eeprom(struct ath_hw
*ah
)
1476 struct ar5416_eeprom_def
*eep
=
1477 (struct ar5416_eeprom_def
*) &ah
->eeprom
.def
;
1478 u16
*eepdata
, temp
, magic
, magic2
;
1480 bool need_swap
= false;
1483 if (!ath9k_hw_nvram_read(ah
, AR5416_EEPROM_MAGIC_OFFSET
, &magic
)) {
1484 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
, "Reading Magic # failed\n");
1488 if (!ath9k_hw_use_flash(ah
)) {
1489 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
1490 "Read Magic = 0x%04X\n", magic
);
1492 if (magic
!= AR5416_EEPROM_MAGIC
) {
1493 magic2
= swab16(magic
);
1495 if (magic2
== AR5416_EEPROM_MAGIC
) {
1496 size
= sizeof(struct ar5416_eeprom_def
);
1498 eepdata
= (u16
*) (&ah
->eeprom
);
1500 for (addr
= 0; addr
< size
/ sizeof(u16
); addr
++) {
1501 temp
= swab16(*eepdata
);
1506 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
1507 "Invalid EEPROM Magic. "
1508 "Endianness mismatch.\n");
1514 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
, "need_swap = %s.\n",
1515 need_swap
? "True" : "False");
1518 el
= swab16(ah
->eeprom
.def
.baseEepHeader
.length
);
1520 el
= ah
->eeprom
.def
.baseEepHeader
.length
;
1522 if (el
> sizeof(struct ar5416_eeprom_def
))
1523 el
= sizeof(struct ar5416_eeprom_def
) / sizeof(u16
);
1525 el
= el
/ sizeof(u16
);
1527 eepdata
= (u16
*)(&ah
->eeprom
);
1529 for (i
= 0; i
< el
; i
++)
1536 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
1537 "EEPROM Endianness is not native.. Changing.\n");
1539 word
= swab16(eep
->baseEepHeader
.length
);
1540 eep
->baseEepHeader
.length
= word
;
1542 word
= swab16(eep
->baseEepHeader
.checksum
);
1543 eep
->baseEepHeader
.checksum
= word
;
1545 word
= swab16(eep
->baseEepHeader
.version
);
1546 eep
->baseEepHeader
.version
= word
;
1548 word
= swab16(eep
->baseEepHeader
.regDmn
[0]);
1549 eep
->baseEepHeader
.regDmn
[0] = word
;
1551 word
= swab16(eep
->baseEepHeader
.regDmn
[1]);
1552 eep
->baseEepHeader
.regDmn
[1] = word
;
1554 word
= swab16(eep
->baseEepHeader
.rfSilent
);
1555 eep
->baseEepHeader
.rfSilent
= word
;
1557 word
= swab16(eep
->baseEepHeader
.blueToothOptions
);
1558 eep
->baseEepHeader
.blueToothOptions
= word
;
1560 word
= swab16(eep
->baseEepHeader
.deviceCap
);
1561 eep
->baseEepHeader
.deviceCap
= word
;
1563 for (j
= 0; j
< ARRAY_SIZE(eep
->modalHeader
); j
++) {
1564 struct modal_eep_header
*pModal
=
1565 &eep
->modalHeader
[j
];
1566 integer
= swab32(pModal
->antCtrlCommon
);
1567 pModal
->antCtrlCommon
= integer
;
1569 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
1570 integer
= swab32(pModal
->antCtrlChain
[i
]);
1571 pModal
->antCtrlChain
[i
] = integer
;
1574 for (i
= 0; i
< AR5416_EEPROM_MODAL_SPURS
; i
++) {
1575 word
= swab16(pModal
->spurChans
[i
].spurChan
);
1576 pModal
->spurChans
[i
].spurChan
= word
;
1581 if (sum
!= 0xffff || ah
->eep_ops
->get_eeprom_ver(ah
) != AR5416_EEP_VER
||
1582 ah
->eep_ops
->get_eeprom_rev(ah
) < AR5416_EEP_NO_BACK_VER
) {
1583 DPRINTF(ah
->ah_sc
, ATH_DBG_FATAL
,
1584 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
1585 sum
, ah
->eep_ops
->get_eeprom_ver(ah
));
1592 static u32
ath9k_hw_def_get_eeprom(struct ath_hw
*ah
,
1593 enum eeprom_param param
)
1595 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
1596 struct modal_eep_header
*pModal
= eep
->modalHeader
;
1597 struct base_eep_header
*pBase
= &eep
->baseEepHeader
;
1600 case EEP_NFTHRESH_5
:
1601 return pModal
[0].noiseFloorThreshCh
[0];
1602 case EEP_NFTHRESH_2
:
1603 return pModal
[1].noiseFloorThreshCh
[0];
1604 case AR_EEPROM_MAC(0):
1605 return pBase
->macAddr
[0] << 8 | pBase
->macAddr
[1];
1606 case AR_EEPROM_MAC(1):
1607 return pBase
->macAddr
[2] << 8 | pBase
->macAddr
[3];
1608 case AR_EEPROM_MAC(2):
1609 return pBase
->macAddr
[4] << 8 | pBase
->macAddr
[5];
1611 return pBase
->regDmn
[0];
1613 return pBase
->regDmn
[1];
1615 return pBase
->deviceCap
;
1617 return pBase
->opCapFlags
;
1619 return pBase
->rfSilent
;
1621 return pModal
[0].ob
;
1623 return pModal
[0].db
;
1625 return pModal
[1].ob
;
1627 return pModal
[1].db
;
1629 return AR5416_VER_MASK
;
1631 return pBase
->txMask
;
1633 return pBase
->rxMask
;
1634 case EEP_RXGAIN_TYPE
:
1635 return pBase
->rxGainType
;
1636 case EEP_TXGAIN_TYPE
:
1637 return pBase
->txGainType
;
1638 case EEP_OL_PWRCTRL
:
1639 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_19
)
1640 return pBase
->openLoopPwrCntl
? true : false;
1643 case EEP_RC_CHAIN_MASK
:
1644 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_19
)
1645 return pBase
->rcChainMask
;
1648 case EEP_DAC_HPWR_5G
:
1649 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_20
)
1650 return pBase
->dacHiPwrMode_5G
;
1654 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_22
)
1655 return pBase
->frac_n_5g
;
1663 static void ath9k_hw_def_set_gain(struct ath_hw
*ah
,
1664 struct modal_eep_header
*pModal
,
1665 struct ar5416_eeprom_def
*eep
,
1666 u8 txRxAttenLocal
, int regChainOffset
, int i
)
1668 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_3
) {
1669 txRxAttenLocal
= pModal
->txRxAttenCh
[i
];
1671 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1672 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1673 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN
,
1674 pModal
->bswMargin
[i
]);
1675 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1676 AR_PHY_GAIN_2GHZ_XATTEN1_DB
,
1677 pModal
->bswAtten
[i
]);
1678 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1679 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN
,
1680 pModal
->xatten2Margin
[i
]);
1681 REG_RMW_FIELD(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1682 AR_PHY_GAIN_2GHZ_XATTEN2_DB
,
1683 pModal
->xatten2Db
[i
]);
1685 REG_WRITE(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1686 (REG_READ(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
) &
1687 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN
)
1688 | SM(pModal
-> bswMargin
[i
],
1689 AR_PHY_GAIN_2GHZ_BSW_MARGIN
));
1690 REG_WRITE(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1691 (REG_READ(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
) &
1692 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN
)
1693 | SM(pModal
->bswAtten
[i
],
1694 AR_PHY_GAIN_2GHZ_BSW_ATTEN
));
1698 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1700 AR_PHY_RXGAIN
+ regChainOffset
,
1701 AR9280_PHY_RXGAIN_TXRX_ATTEN
, txRxAttenLocal
);
1703 AR_PHY_RXGAIN
+ regChainOffset
,
1704 AR9280_PHY_RXGAIN_TXRX_MARGIN
, pModal
->rxTxMarginCh
[i
]);
1707 AR_PHY_RXGAIN
+ regChainOffset
,
1708 (REG_READ(ah
, AR_PHY_RXGAIN
+ regChainOffset
) &
1709 ~AR_PHY_RXGAIN_TXRX_ATTEN
)
1710 | SM(txRxAttenLocal
, AR_PHY_RXGAIN_TXRX_ATTEN
));
1712 AR_PHY_GAIN_2GHZ
+ regChainOffset
,
1713 (REG_READ(ah
, AR_PHY_GAIN_2GHZ
+ regChainOffset
) &
1714 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN
) |
1715 SM(pModal
->rxTxMarginCh
[i
], AR_PHY_GAIN_2GHZ_RXTX_MARGIN
));
1719 static void ath9k_hw_def_set_board_values(struct ath_hw
*ah
,
1720 struct ath9k_channel
*chan
)
1722 struct modal_eep_header
*pModal
;
1723 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
1724 int i
, regChainOffset
;
1727 pModal
= &(eep
->modalHeader
[IS_CHAN_2GHZ(chan
)]);
1728 txRxAttenLocal
= IS_CHAN_2GHZ(chan
) ? 23 : 44;
1730 REG_WRITE(ah
, AR_PHY_SWITCH_COM
,
1731 ah
->eep_ops
->get_eeprom_antenna_cfg(ah
, chan
));
1733 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
1734 if (AR_SREV_9280(ah
)) {
1739 if (AR_SREV_5416_20_OR_LATER(ah
) &&
1740 (ah
->rxchainmask
== 5 || ah
->txchainmask
== 5) && (i
!= 0))
1741 regChainOffset
= (i
== 1) ? 0x2000 : 0x1000;
1743 regChainOffset
= i
* 0x1000;
1745 REG_WRITE(ah
, AR_PHY_SWITCH_CHAIN_0
+ regChainOffset
,
1746 pModal
->antCtrlChain
[i
]);
1748 REG_WRITE(ah
, AR_PHY_TIMING_CTRL4(0) + regChainOffset
,
1749 (REG_READ(ah
, AR_PHY_TIMING_CTRL4(0) + regChainOffset
) &
1750 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
|
1751 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
)) |
1752 SM(pModal
->iqCalICh
[i
],
1753 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF
) |
1754 SM(pModal
->iqCalQCh
[i
],
1755 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF
));
1757 if ((i
== 0) || AR_SREV_5416_20_OR_LATER(ah
))
1758 ath9k_hw_def_set_gain(ah
, pModal
, eep
, txRxAttenLocal
,
1762 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1763 if (IS_CHAN_2GHZ(chan
)) {
1764 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF2G1_CH0
,
1766 AR_AN_RF2G1_CH0_OB_S
,
1768 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF2G1_CH0
,
1770 AR_AN_RF2G1_CH0_DB_S
,
1772 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF2G1_CH1
,
1774 AR_AN_RF2G1_CH1_OB_S
,
1776 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF2G1_CH1
,
1778 AR_AN_RF2G1_CH1_DB_S
,
1781 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF5G1_CH0
,
1782 AR_AN_RF5G1_CH0_OB5
,
1783 AR_AN_RF5G1_CH0_OB5_S
,
1785 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF5G1_CH0
,
1786 AR_AN_RF5G1_CH0_DB5
,
1787 AR_AN_RF5G1_CH0_DB5_S
,
1789 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF5G1_CH1
,
1790 AR_AN_RF5G1_CH1_OB5
,
1791 AR_AN_RF5G1_CH1_OB5_S
,
1793 ath9k_hw_analog_shift_rmw(ah
, AR_AN_RF5G1_CH1
,
1794 AR_AN_RF5G1_CH1_DB5
,
1795 AR_AN_RF5G1_CH1_DB5_S
,
1798 ath9k_hw_analog_shift_rmw(ah
, AR_AN_TOP2
,
1799 AR_AN_TOP2_XPABIAS_LVL
,
1800 AR_AN_TOP2_XPABIAS_LVL_S
,
1801 pModal
->xpaBiasLvl
);
1802 ath9k_hw_analog_shift_rmw(ah
, AR_AN_TOP2
,
1803 AR_AN_TOP2_LOCALBIAS
,
1804 AR_AN_TOP2_LOCALBIAS_S
,
1805 pModal
->local_bias
);
1806 REG_RMW_FIELD(ah
, AR_PHY_XPA_CFG
, AR_PHY_FORCE_XPA_CFG
,
1807 pModal
->force_xpaon
);
1810 REG_RMW_FIELD(ah
, AR_PHY_SETTLING
, AR_PHY_SETTLING_SWITCH
,
1811 pModal
->switchSettling
);
1812 REG_RMW_FIELD(ah
, AR_PHY_DESIRED_SZ
, AR_PHY_DESIRED_SZ_ADC
,
1813 pModal
->adcDesiredSize
);
1815 if (!AR_SREV_9280_10_OR_LATER(ah
))
1816 REG_RMW_FIELD(ah
, AR_PHY_DESIRED_SZ
,
1817 AR_PHY_DESIRED_SZ_PGA
,
1818 pModal
->pgaDesiredSize
);
1820 REG_WRITE(ah
, AR_PHY_RF_CTL4
,
1821 SM(pModal
->txEndToXpaOff
, AR_PHY_RF_CTL4_TX_END_XPAA_OFF
)
1822 | SM(pModal
->txEndToXpaOff
,
1823 AR_PHY_RF_CTL4_TX_END_XPAB_OFF
)
1824 | SM(pModal
->txFrameToXpaOn
,
1825 AR_PHY_RF_CTL4_FRAME_XPAA_ON
)
1826 | SM(pModal
->txFrameToXpaOn
,
1827 AR_PHY_RF_CTL4_FRAME_XPAB_ON
));
1829 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL3
, AR_PHY_TX_END_TO_A2_RX_ON
,
1830 pModal
->txEndToRxOn
);
1832 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1833 REG_RMW_FIELD(ah
, AR_PHY_CCA
, AR9280_PHY_CCA_THRESH62
,
1835 REG_RMW_FIELD(ah
, AR_PHY_EXT_CCA0
,
1836 AR_PHY_EXT_CCA0_THRESH62
,
1839 REG_RMW_FIELD(ah
, AR_PHY_CCA
, AR_PHY_CCA_THRESH62
,
1841 REG_RMW_FIELD(ah
, AR_PHY_EXT_CCA
,
1842 AR_PHY_EXT_CCA_THRESH62
,
1846 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_2
) {
1847 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL2
,
1848 AR_PHY_TX_END_DATA_START
,
1849 pModal
->txFrameToDataStart
);
1850 REG_RMW_FIELD(ah
, AR_PHY_RF_CTL2
, AR_PHY_TX_END_PA_ON
,
1851 pModal
->txFrameToPaOn
);
1854 if (AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_3
) {
1855 if (IS_CHAN_HT40(chan
))
1856 REG_RMW_FIELD(ah
, AR_PHY_SETTLING
,
1857 AR_PHY_SETTLING_SWITCH
,
1858 pModal
->swSettleHt40
);
1861 if (AR_SREV_9280_20_OR_LATER(ah
) &&
1862 AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_19
)
1863 REG_RMW_FIELD(ah
, AR_PHY_CCK_TX_CTRL
,
1864 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK
,
1868 if (AR_SREV_9280_20(ah
) && AR5416_VER_MASK
>= AR5416_EEP_MINOR_VER_20
) {
1869 if (IS_CHAN_2GHZ(chan
))
1870 REG_RMW_FIELD(ah
, AR_AN_TOP1
, AR_AN_TOP1_DACIPMODE
,
1871 eep
->baseEepHeader
.dacLpMode
);
1872 else if (eep
->baseEepHeader
.dacHiPwrMode_5G
)
1873 REG_RMW_FIELD(ah
, AR_AN_TOP1
, AR_AN_TOP1_DACIPMODE
, 0);
1875 REG_RMW_FIELD(ah
, AR_AN_TOP1
, AR_AN_TOP1_DACIPMODE
,
1876 eep
->baseEepHeader
.dacLpMode
);
1878 REG_RMW_FIELD(ah
, AR_PHY_FRAME_CTL
, AR_PHY_FRAME_CTL_TX_CLIP
,
1879 pModal
->miscBits
>> 2);
1881 REG_RMW_FIELD(ah
, AR_PHY_TX_PWRCTRL9
,
1882 AR_PHY_TX_DESIRED_SCALE_CCK
,
1883 eep
->baseEepHeader
.desiredScaleCCK
);
1887 static void ath9k_hw_def_set_addac(struct ath_hw
*ah
,
1888 struct ath9k_channel
*chan
)
1890 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
1891 struct modal_eep_header
*pModal
;
1892 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
1895 if (ah
->hw_version
.macVersion
!= AR_SREV_VERSION_9160
)
1898 if (ah
->eep_ops
->get_eeprom_rev(ah
) < AR5416_EEP_MINOR_VER_7
)
1901 pModal
= &(eep
->modalHeader
[IS_CHAN_2GHZ(chan
)]);
1903 if (pModal
->xpaBiasLvl
!= 0xff) {
1904 biaslevel
= pModal
->xpaBiasLvl
;
1906 u16 resetFreqBin
, freqBin
, freqCount
= 0;
1907 struct chan_centers centers
;
1909 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
1911 resetFreqBin
= FREQ2FBIN(centers
.synth_center
,
1912 IS_CHAN_2GHZ(chan
));
1913 freqBin
= XPA_LVL_FREQ(0) & 0xff;
1914 biaslevel
= (u8
) (XPA_LVL_FREQ(0) >> 14);
1918 while (freqCount
< 3) {
1919 if (XPA_LVL_FREQ(freqCount
) == 0x0)
1922 freqBin
= XPA_LVL_FREQ(freqCount
) & 0xff;
1923 if (resetFreqBin
>= freqBin
)
1924 biaslevel
= (u8
)(XPA_LVL_FREQ(freqCount
) >> 14);
1931 if (IS_CHAN_2GHZ(chan
)) {
1932 INI_RA(&ah
->iniAddac
, 7, 1) = (INI_RA(&ah
->iniAddac
,
1933 7, 1) & (~0x18)) | biaslevel
<< 3;
1935 INI_RA(&ah
->iniAddac
, 6, 1) = (INI_RA(&ah
->iniAddac
,
1936 6, 1) & (~0xc0)) | biaslevel
<< 6;
1941 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw
*ah
,
1942 struct ath9k_channel
*chan
,
1943 struct cal_data_per_freq
*pRawDataSet
,
1944 u8
*bChans
, u16 availPiers
,
1945 u16 tPdGainOverlap
, int16_t *pMinCalPower
,
1946 u16
*pPdGainBoundaries
, u8
*pPDADCValues
,
1951 u16 idxL
= 0, idxR
= 0, numPiers
;
1952 static u8 vpdTableL
[AR5416_NUM_PD_GAINS
]
1953 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
1954 static u8 vpdTableR
[AR5416_NUM_PD_GAINS
]
1955 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
1956 static u8 vpdTableI
[AR5416_NUM_PD_GAINS
]
1957 [AR5416_MAX_PWR_RANGE_IN_HALF_DB
];
1959 u8
*pVpdL
, *pVpdR
, *pPwrL
, *pPwrR
;
1960 u8 minPwrT4
[AR5416_NUM_PD_GAINS
];
1961 u8 maxPwrT4
[AR5416_NUM_PD_GAINS
];
1964 u16 sizeCurrVpdTable
, maxIndex
, tgtIndex
;
1966 int16_t minDelta
= 0;
1967 struct chan_centers centers
;
1969 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
1971 for (numPiers
= 0; numPiers
< availPiers
; numPiers
++) {
1972 if (bChans
[numPiers
] == AR5416_BCHAN_UNUSED
)
1976 match
= ath9k_hw_get_lower_upper_index((u8
)FREQ2FBIN(centers
.synth_center
,
1977 IS_CHAN_2GHZ(chan
)),
1978 bChans
, numPiers
, &idxL
, &idxR
);
1981 for (i
= 0; i
< numXpdGains
; i
++) {
1982 minPwrT4
[i
] = pRawDataSet
[idxL
].pwrPdg
[i
][0];
1983 maxPwrT4
[i
] = pRawDataSet
[idxL
].pwrPdg
[i
][4];
1984 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
1985 pRawDataSet
[idxL
].pwrPdg
[i
],
1986 pRawDataSet
[idxL
].vpdPdg
[i
],
1987 AR5416_PD_GAIN_ICEPTS
,
1991 for (i
= 0; i
< numXpdGains
; i
++) {
1992 pVpdL
= pRawDataSet
[idxL
].vpdPdg
[i
];
1993 pPwrL
= pRawDataSet
[idxL
].pwrPdg
[i
];
1994 pVpdR
= pRawDataSet
[idxR
].vpdPdg
[i
];
1995 pPwrR
= pRawDataSet
[idxR
].pwrPdg
[i
];
1997 minPwrT4
[i
] = max(pPwrL
[0], pPwrR
[0]);
2000 min(pPwrL
[AR5416_PD_GAIN_ICEPTS
- 1],
2001 pPwrR
[AR5416_PD_GAIN_ICEPTS
- 1]);
2004 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
2006 AR5416_PD_GAIN_ICEPTS
,
2008 ath9k_hw_fill_vpd_table(minPwrT4
[i
], maxPwrT4
[i
],
2010 AR5416_PD_GAIN_ICEPTS
,
2013 for (j
= 0; j
<= (maxPwrT4
[i
] - minPwrT4
[i
]) / 2; j
++) {
2015 (u8
)(ath9k_hw_interpolate((u16
)
2020 bChans
[idxL
], bChans
[idxR
],
2021 vpdTableL
[i
][j
], vpdTableR
[i
][j
]));
2026 *pMinCalPower
= (int16_t)(minPwrT4
[0] / 2);
2030 for (i
= 0; i
< numXpdGains
; i
++) {
2031 if (i
== (numXpdGains
- 1))
2032 pPdGainBoundaries
[i
] =
2033 (u16
)(maxPwrT4
[i
] / 2);
2035 pPdGainBoundaries
[i
] =
2036 (u16
)((maxPwrT4
[i
] + minPwrT4
[i
+ 1]) / 4);
2038 pPdGainBoundaries
[i
] =
2039 min((u16
)AR5416_MAX_RATE_POWER
, pPdGainBoundaries
[i
]);
2041 if ((i
== 0) && !AR_SREV_5416_20_OR_LATER(ah
)) {
2042 minDelta
= pPdGainBoundaries
[0] - 23;
2043 pPdGainBoundaries
[0] = 23;
2049 if (AR_SREV_9280_10_OR_LATER(ah
))
2050 ss
= (int16_t)(0 - (minPwrT4
[i
] / 2));
2054 ss
= (int16_t)((pPdGainBoundaries
[i
- 1] -
2055 (minPwrT4
[i
] / 2)) -
2056 tPdGainOverlap
+ 1 + minDelta
);
2058 vpdStep
= (int16_t)(vpdTableI
[i
][1] - vpdTableI
[i
][0]);
2059 vpdStep
= (int16_t)((vpdStep
< 1) ? 1 : vpdStep
);
2061 while ((ss
< 0) && (k
< (AR5416_NUM_PDADC_VALUES
- 1))) {
2062 tmpVal
= (int16_t)(vpdTableI
[i
][0] + ss
* vpdStep
);
2063 pPDADCValues
[k
++] = (u8
)((tmpVal
< 0) ? 0 : tmpVal
);
2067 sizeCurrVpdTable
= (u8
) ((maxPwrT4
[i
] - minPwrT4
[i
]) / 2 + 1);
2068 tgtIndex
= (u8
)(pPdGainBoundaries
[i
] + tPdGainOverlap
-
2070 maxIndex
= (tgtIndex
< sizeCurrVpdTable
) ?
2071 tgtIndex
: sizeCurrVpdTable
;
2073 while ((ss
< maxIndex
) && (k
< (AR5416_NUM_PDADC_VALUES
- 1))) {
2074 pPDADCValues
[k
++] = vpdTableI
[i
][ss
++];
2077 vpdStep
= (int16_t)(vpdTableI
[i
][sizeCurrVpdTable
- 1] -
2078 vpdTableI
[i
][sizeCurrVpdTable
- 2]);
2079 vpdStep
= (int16_t)((vpdStep
< 1) ? 1 : vpdStep
);
2081 if (tgtIndex
> maxIndex
) {
2082 while ((ss
<= tgtIndex
) &&
2083 (k
< (AR5416_NUM_PDADC_VALUES
- 1))) {
2084 tmpVal
= (int16_t)((vpdTableI
[i
][sizeCurrVpdTable
- 1] +
2085 (ss
- maxIndex
+ 1) * vpdStep
));
2086 pPDADCValues
[k
++] = (u8
)((tmpVal
> 255) ?
2093 while (i
< AR5416_PD_GAINS_IN_MASK
) {
2094 pPdGainBoundaries
[i
] = pPdGainBoundaries
[i
- 1];
2098 while (k
< AR5416_NUM_PDADC_VALUES
) {
2099 pPDADCValues
[k
] = pPDADCValues
[k
- 1];
2106 static bool ath9k_hw_set_def_power_cal_table(struct ath_hw
*ah
,
2107 struct ath9k_channel
*chan
,
2108 int16_t *pTxPowerIndexOffset
)
2110 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
2111 #define SM_PDGAIN_B(x, y) \
2112 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
2114 struct ar5416_eeprom_def
*pEepData
= &ah
->eeprom
.def
;
2115 struct cal_data_per_freq
*pRawDataset
;
2116 u8
*pCalBChans
= NULL
;
2117 u16 pdGainOverlap_t2
;
2118 static u8 pdadcValues
[AR5416_NUM_PDADC_VALUES
];
2119 u16 gainBoundaries
[AR5416_PD_GAINS_IN_MASK
];
2121 int16_t tMinCalPower
;
2122 u16 numXpdGain
, xpdMask
;
2123 u16 xpdGainValues
[AR5416_NUM_PD_GAINS
] = { 0, 0, 0, 0 };
2124 u32 reg32
, regOffset
, regChainOffset
;
2127 modalIdx
= IS_CHAN_2GHZ(chan
) ? 1 : 0;
2128 xpdMask
= pEepData
->modalHeader
[modalIdx
].xpdGain
;
2130 if ((pEepData
->baseEepHeader
.version
& AR5416_EEP_VER_MINOR_MASK
) >=
2131 AR5416_EEP_MINOR_VER_2
) {
2133 pEepData
->modalHeader
[modalIdx
].pdGainOverlap
;
2135 pdGainOverlap_t2
= (u16
)(MS(REG_READ(ah
, AR_PHY_TPCRG5
),
2136 AR_PHY_TPCRG5_PD_GAIN_OVERLAP
));
2139 if (IS_CHAN_2GHZ(chan
)) {
2140 pCalBChans
= pEepData
->calFreqPier2G
;
2141 numPiers
= AR5416_NUM_2G_CAL_PIERS
;
2143 pCalBChans
= pEepData
->calFreqPier5G
;
2144 numPiers
= AR5416_NUM_5G_CAL_PIERS
;
2147 if (OLC_FOR_AR9280_20_LATER
&& IS_CHAN_2GHZ(chan
)) {
2148 pRawDataset
= pEepData
->calPierData2G
[0];
2149 ah
->initPDADC
= ((struct calDataPerFreqOpLoop
*)
2150 pRawDataset
)->vpdPdg
[0][0];
2155 for (i
= 1; i
<= AR5416_PD_GAINS_IN_MASK
; i
++) {
2156 if ((xpdMask
>> (AR5416_PD_GAINS_IN_MASK
- i
)) & 1) {
2157 if (numXpdGain
>= AR5416_NUM_PD_GAINS
)
2159 xpdGainValues
[numXpdGain
] =
2160 (u16
)(AR5416_PD_GAINS_IN_MASK
- i
);
2165 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_NUM_PD_GAIN
,
2166 (numXpdGain
- 1) & 0x3);
2167 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_1
,
2169 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_2
,
2171 REG_RMW_FIELD(ah
, AR_PHY_TPCRG1
, AR_PHY_TPCRG1_PD_GAIN_3
,
2174 for (i
= 0; i
< AR5416_MAX_CHAINS
; i
++) {
2175 if (AR_SREV_5416_20_OR_LATER(ah
) &&
2176 (ah
->rxchainmask
== 5 || ah
->txchainmask
== 5) &&
2178 regChainOffset
= (i
== 1) ? 0x2000 : 0x1000;
2180 regChainOffset
= i
* 0x1000;
2182 if (pEepData
->baseEepHeader
.txMask
& (1 << i
)) {
2183 if (IS_CHAN_2GHZ(chan
))
2184 pRawDataset
= pEepData
->calPierData2G
[i
];
2186 pRawDataset
= pEepData
->calPierData5G
[i
];
2189 if (OLC_FOR_AR9280_20_LATER
) {
2193 ath9k_get_txgain_index(ah
, chan
,
2194 (struct calDataPerFreqOpLoop
*)pRawDataset
,
2195 pCalBChans
, numPiers
, &txPower
, &pcdacIdx
);
2196 ath9k_olc_get_pdadcs(ah
, pcdacIdx
,
2197 txPower
/2, pdadcValues
);
2199 ath9k_hw_get_def_gain_boundaries_pdadcs(ah
,
2201 pCalBChans
, numPiers
,
2209 if ((i
== 0) || AR_SREV_5416_20_OR_LATER(ah
)) {
2210 if (OLC_FOR_AR9280_20_LATER
) {
2212 AR_PHY_TPCRG5
+ regChainOffset
,
2214 AR_PHY_TPCRG5_PD_GAIN_OVERLAP
) |
2215 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
2216 SM_PD_GAIN(3) | SM_PD_GAIN(4));
2219 AR_PHY_TPCRG5
+ regChainOffset
,
2220 SM(pdGainOverlap_t2
,
2221 AR_PHY_TPCRG5_PD_GAIN_OVERLAP
)|
2229 regOffset
= AR_PHY_BASE
+ (672 << 2) + regChainOffset
;
2230 for (j
= 0; j
< 32; j
++) {
2231 reg32
= ((pdadcValues
[4 * j
+ 0] & 0xFF) << 0) |
2232 ((pdadcValues
[4 * j
+ 1] & 0xFF) << 8) |
2233 ((pdadcValues
[4 * j
+ 2] & 0xFF) << 16)|
2234 ((pdadcValues
[4 * j
+ 3] & 0xFF) << 24);
2235 REG_WRITE(ah
, regOffset
, reg32
);
2237 DPRINTF(ah
->ah_sc
, ATH_DBG_REG_IO
,
2238 "PDADC (%d,%4x): %4.4x %8.8x\n",
2239 i
, regChainOffset
, regOffset
,
2241 DPRINTF(ah
->ah_sc
, ATH_DBG_REG_IO
,
2242 "PDADC: Chain %d | PDADC %3d "
2243 "Value %3d | PDADC %3d Value %3d | "
2244 "PDADC %3d Value %3d | PDADC %3d "
2246 i
, 4 * j
, pdadcValues
[4 * j
],
2247 4 * j
+ 1, pdadcValues
[4 * j
+ 1],
2248 4 * j
+ 2, pdadcValues
[4 * j
+ 2],
2250 pdadcValues
[4 * j
+ 3]);
2257 *pTxPowerIndexOffset
= 0;
2264 static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw
*ah
,
2265 struct ath9k_channel
*chan
,
2266 int16_t *ratesArray
,
2268 u16 AntennaReduction
,
2269 u16 twiceMaxRegulatoryPower
,
2272 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
2273 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
2275 struct ar5416_eeprom_def
*pEepData
= &ah
->eeprom
.def
;
2276 u16 twiceMaxEdgePower
= AR5416_MAX_RATE_POWER
;
2277 static const u16 tpScaleReductionTable
[5] =
2278 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER
};
2281 int16_t twiceLargestAntenna
;
2282 struct cal_ctl_data
*rep
;
2283 struct cal_target_power_leg targetPowerOfdm
, targetPowerCck
= {
2286 struct cal_target_power_leg targetPowerOfdmExt
= {
2287 0, { 0, 0, 0, 0} }, targetPowerCckExt
= {
2290 struct cal_target_power_ht targetPowerHt20
, targetPowerHt40
= {
2293 u16 scaledPower
= 0, minCtlPower
, maxRegAllowedPower
;
2294 u16 ctlModesFor11a
[] =
2295 { CTL_11A
, CTL_5GHT20
, CTL_11A_EXT
, CTL_5GHT40
};
2296 u16 ctlModesFor11g
[] =
2297 { CTL_11B
, CTL_11G
, CTL_2GHT20
, CTL_11B_EXT
, CTL_11G_EXT
,
2300 u16 numCtlModes
, *pCtlMode
, ctlMode
, freq
;
2301 struct chan_centers centers
;
2303 u16 twiceMinEdgePower
;
2305 tx_chainmask
= ah
->txchainmask
;
2307 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
2309 twiceLargestAntenna
= max(
2310 pEepData
->modalHeader
2311 [IS_CHAN_2GHZ(chan
)].antennaGainCh
[0],
2312 pEepData
->modalHeader
2313 [IS_CHAN_2GHZ(chan
)].antennaGainCh
[1]);
2315 twiceLargestAntenna
= max((u8
)twiceLargestAntenna
,
2316 pEepData
->modalHeader
2317 [IS_CHAN_2GHZ(chan
)].antennaGainCh
[2]);
2319 twiceLargestAntenna
= (int16_t)min(AntennaReduction
-
2320 twiceLargestAntenna
, 0);
2322 maxRegAllowedPower
= twiceMaxRegulatoryPower
+ twiceLargestAntenna
;
2324 if (ah
->regulatory
.tp_scale
!= ATH9K_TP_SCALE_MAX
) {
2325 maxRegAllowedPower
-=
2326 (tpScaleReductionTable
[(ah
->regulatory
.tp_scale
)] * 2);
2329 scaledPower
= min(powerLimit
, maxRegAllowedPower
);
2331 switch (ar5416_get_ntxchains(tx_chainmask
)) {
2335 scaledPower
-= REDUCE_SCALED_POWER_BY_TWO_CHAIN
;
2338 scaledPower
-= REDUCE_SCALED_POWER_BY_THREE_CHAIN
;
2342 scaledPower
= max((u16
)0, scaledPower
);
2344 if (IS_CHAN_2GHZ(chan
)) {
2345 numCtlModes
= ARRAY_SIZE(ctlModesFor11g
) -
2346 SUB_NUM_CTL_MODES_AT_2G_40
;
2347 pCtlMode
= ctlModesFor11g
;
2349 ath9k_hw_get_legacy_target_powers(ah
, chan
,
2350 pEepData
->calTargetPowerCck
,
2351 AR5416_NUM_2G_CCK_TARGET_POWERS
,
2352 &targetPowerCck
, 4, false);
2353 ath9k_hw_get_legacy_target_powers(ah
, chan
,
2354 pEepData
->calTargetPower2G
,
2355 AR5416_NUM_2G_20_TARGET_POWERS
,
2356 &targetPowerOfdm
, 4, false);
2357 ath9k_hw_get_target_powers(ah
, chan
,
2358 pEepData
->calTargetPower2GHT20
,
2359 AR5416_NUM_2G_20_TARGET_POWERS
,
2360 &targetPowerHt20
, 8, false);
2362 if (IS_CHAN_HT40(chan
)) {
2363 numCtlModes
= ARRAY_SIZE(ctlModesFor11g
);
2364 ath9k_hw_get_target_powers(ah
, chan
,
2365 pEepData
->calTargetPower2GHT40
,
2366 AR5416_NUM_2G_40_TARGET_POWERS
,
2367 &targetPowerHt40
, 8, true);
2368 ath9k_hw_get_legacy_target_powers(ah
, chan
,
2369 pEepData
->calTargetPowerCck
,
2370 AR5416_NUM_2G_CCK_TARGET_POWERS
,
2371 &targetPowerCckExt
, 4, true);
2372 ath9k_hw_get_legacy_target_powers(ah
, chan
,
2373 pEepData
->calTargetPower2G
,
2374 AR5416_NUM_2G_20_TARGET_POWERS
,
2375 &targetPowerOfdmExt
, 4, true);
2378 numCtlModes
= ARRAY_SIZE(ctlModesFor11a
) -
2379 SUB_NUM_CTL_MODES_AT_5G_40
;
2380 pCtlMode
= ctlModesFor11a
;
2382 ath9k_hw_get_legacy_target_powers(ah
, chan
,
2383 pEepData
->calTargetPower5G
,
2384 AR5416_NUM_5G_20_TARGET_POWERS
,
2385 &targetPowerOfdm
, 4, false);
2386 ath9k_hw_get_target_powers(ah
, chan
,
2387 pEepData
->calTargetPower5GHT20
,
2388 AR5416_NUM_5G_20_TARGET_POWERS
,
2389 &targetPowerHt20
, 8, false);
2391 if (IS_CHAN_HT40(chan
)) {
2392 numCtlModes
= ARRAY_SIZE(ctlModesFor11a
);
2393 ath9k_hw_get_target_powers(ah
, chan
,
2394 pEepData
->calTargetPower5GHT40
,
2395 AR5416_NUM_5G_40_TARGET_POWERS
,
2396 &targetPowerHt40
, 8, true);
2397 ath9k_hw_get_legacy_target_powers(ah
, chan
,
2398 pEepData
->calTargetPower5G
,
2399 AR5416_NUM_5G_20_TARGET_POWERS
,
2400 &targetPowerOfdmExt
, 4, true);
2404 for (ctlMode
= 0; ctlMode
< numCtlModes
; ctlMode
++) {
2405 bool isHt40CtlMode
= (pCtlMode
[ctlMode
] == CTL_5GHT40
) ||
2406 (pCtlMode
[ctlMode
] == CTL_2GHT40
);
2408 freq
= centers
.synth_center
;
2409 else if (pCtlMode
[ctlMode
] & EXT_ADDITIVE
)
2410 freq
= centers
.ext_center
;
2412 freq
= centers
.ctl_center
;
2414 if (ah
->eep_ops
->get_eeprom_ver(ah
) == 14 &&
2415 ah
->eep_ops
->get_eeprom_rev(ah
) <= 2)
2416 twiceMaxEdgePower
= AR5416_MAX_RATE_POWER
;
2418 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
,
2419 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
2420 "EXT_ADDITIVE %d\n",
2421 ctlMode
, numCtlModes
, isHt40CtlMode
,
2422 (pCtlMode
[ctlMode
] & EXT_ADDITIVE
));
2424 for (i
= 0; (i
< AR5416_NUM_CTLS
) && pEepData
->ctlIndex
[i
]; i
++) {
2425 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
,
2426 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
2427 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
2429 i
, cfgCtl
, pCtlMode
[ctlMode
],
2430 pEepData
->ctlIndex
[i
], chan
->channel
);
2432 if ((((cfgCtl
& ~CTL_MODE_M
) |
2433 (pCtlMode
[ctlMode
] & CTL_MODE_M
)) ==
2434 pEepData
->ctlIndex
[i
]) ||
2435 (((cfgCtl
& ~CTL_MODE_M
) |
2436 (pCtlMode
[ctlMode
] & CTL_MODE_M
)) ==
2437 ((pEepData
->ctlIndex
[i
] & CTL_MODE_M
) | SD_NO_CTL
))) {
2438 rep
= &(pEepData
->ctlData
[i
]);
2440 twiceMinEdgePower
= ath9k_hw_get_max_edge_power(freq
,
2441 rep
->ctlEdges
[ar5416_get_ntxchains(tx_chainmask
) - 1],
2442 IS_CHAN_2GHZ(chan
), AR5416_NUM_BAND_EDGES
);
2444 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
,
2445 " MATCH-EE_IDX %d: ch %d is2 %d "
2446 "2xMinEdge %d chainmask %d chains %d\n",
2447 i
, freq
, IS_CHAN_2GHZ(chan
),
2448 twiceMinEdgePower
, tx_chainmask
,
2449 ar5416_get_ntxchains
2451 if ((cfgCtl
& ~CTL_MODE_M
) == SD_NO_CTL
) {
2452 twiceMaxEdgePower
= min(twiceMaxEdgePower
,
2455 twiceMaxEdgePower
= twiceMinEdgePower
;
2461 minCtlPower
= min(twiceMaxEdgePower
, scaledPower
);
2463 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
,
2464 " SEL-Min ctlMode %d pCtlMode %d "
2465 "2xMaxEdge %d sP %d minCtlPwr %d\n",
2466 ctlMode
, pCtlMode
[ctlMode
], twiceMaxEdgePower
,
2467 scaledPower
, minCtlPower
);
2469 switch (pCtlMode
[ctlMode
]) {
2471 for (i
= 0; i
< ARRAY_SIZE(targetPowerCck
.tPow2x
); i
++) {
2472 targetPowerCck
.tPow2x
[i
] =
2473 min((u16
)targetPowerCck
.tPow2x
[i
],
2479 for (i
= 0; i
< ARRAY_SIZE(targetPowerOfdm
.tPow2x
); i
++) {
2480 targetPowerOfdm
.tPow2x
[i
] =
2481 min((u16
)targetPowerOfdm
.tPow2x
[i
],
2487 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt20
.tPow2x
); i
++) {
2488 targetPowerHt20
.tPow2x
[i
] =
2489 min((u16
)targetPowerHt20
.tPow2x
[i
],
2494 targetPowerCckExt
.tPow2x
[0] = min((u16
)
2495 targetPowerCckExt
.tPow2x
[0],
2500 targetPowerOfdmExt
.tPow2x
[0] = min((u16
)
2501 targetPowerOfdmExt
.tPow2x
[0],
2506 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt40
.tPow2x
); i
++) {
2507 targetPowerHt40
.tPow2x
[i
] =
2508 min((u16
)targetPowerHt40
.tPow2x
[i
],
2517 ratesArray
[rate6mb
] = ratesArray
[rate9mb
] = ratesArray
[rate12mb
] =
2518 ratesArray
[rate18mb
] = ratesArray
[rate24mb
] =
2519 targetPowerOfdm
.tPow2x
[0];
2520 ratesArray
[rate36mb
] = targetPowerOfdm
.tPow2x
[1];
2521 ratesArray
[rate48mb
] = targetPowerOfdm
.tPow2x
[2];
2522 ratesArray
[rate54mb
] = targetPowerOfdm
.tPow2x
[3];
2523 ratesArray
[rateXr
] = targetPowerOfdm
.tPow2x
[0];
2525 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt20
.tPow2x
); i
++)
2526 ratesArray
[rateHt20_0
+ i
] = targetPowerHt20
.tPow2x
[i
];
2528 if (IS_CHAN_2GHZ(chan
)) {
2529 ratesArray
[rate1l
] = targetPowerCck
.tPow2x
[0];
2530 ratesArray
[rate2s
] = ratesArray
[rate2l
] =
2531 targetPowerCck
.tPow2x
[1];
2532 ratesArray
[rate5_5s
] = ratesArray
[rate5_5l
] =
2533 targetPowerCck
.tPow2x
[2];
2535 ratesArray
[rate11s
] = ratesArray
[rate11l
] =
2536 targetPowerCck
.tPow2x
[3];
2539 if (IS_CHAN_HT40(chan
)) {
2540 for (i
= 0; i
< ARRAY_SIZE(targetPowerHt40
.tPow2x
); i
++) {
2541 ratesArray
[rateHt40_0
+ i
] =
2542 targetPowerHt40
.tPow2x
[i
];
2544 ratesArray
[rateDupOfdm
] = targetPowerHt40
.tPow2x
[0];
2545 ratesArray
[rateDupCck
] = targetPowerHt40
.tPow2x
[0];
2546 ratesArray
[rateExtOfdm
] = targetPowerOfdmExt
.tPow2x
[0];
2547 if (IS_CHAN_2GHZ(chan
)) {
2548 ratesArray
[rateExtCck
] =
2549 targetPowerCckExt
.tPow2x
[0];
2555 static int ath9k_hw_def_set_txpower(struct ath_hw
*ah
,
2556 struct ath9k_channel
*chan
,
2558 u8 twiceAntennaReduction
,
2559 u8 twiceMaxRegulatoryPower
,
2562 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
2563 struct ar5416_eeprom_def
*pEepData
= &ah
->eeprom
.def
;
2564 struct modal_eep_header
*pModal
=
2565 &(pEepData
->modalHeader
[IS_CHAN_2GHZ(chan
)]);
2566 int16_t ratesArray
[Ar5416RateSize
];
2567 int16_t txPowerIndexOffset
= 0;
2568 u8 ht40PowerIncForPdadc
= 2;
2569 int i
, cck_ofdm_delta
= 0;
2571 memset(ratesArray
, 0, sizeof(ratesArray
));
2573 if ((pEepData
->baseEepHeader
.version
& AR5416_EEP_VER_MINOR_MASK
) >=
2574 AR5416_EEP_MINOR_VER_2
) {
2575 ht40PowerIncForPdadc
= pModal
->ht40PowerIncForPdadc
;
2578 if (!ath9k_hw_set_def_power_per_rate_table(ah
, chan
,
2579 &ratesArray
[0], cfgCtl
,
2580 twiceAntennaReduction
,
2581 twiceMaxRegulatoryPower
,
2583 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
2584 "ath9k_hw_set_txpower: unable to set "
2585 "tx power per rate table\n");
2589 if (!ath9k_hw_set_def_power_cal_table(ah
, chan
, &txPowerIndexOffset
)) {
2590 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
2591 "ath9k_hw_set_txpower: unable to set power table\n");
2595 for (i
= 0; i
< ARRAY_SIZE(ratesArray
); i
++) {
2596 ratesArray
[i
] = (int16_t)(txPowerIndexOffset
+ ratesArray
[i
]);
2597 if (ratesArray
[i
] > AR5416_MAX_RATE_POWER
)
2598 ratesArray
[i
] = AR5416_MAX_RATE_POWER
;
2601 if (AR_SREV_9280_10_OR_LATER(ah
)) {
2602 for (i
= 0; i
< Ar5416RateSize
; i
++)
2603 ratesArray
[i
] -= AR5416_PWR_TABLE_OFFSET
* 2;
2606 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE1
,
2607 ATH9K_POW_SM(ratesArray
[rate18mb
], 24)
2608 | ATH9K_POW_SM(ratesArray
[rate12mb
], 16)
2609 | ATH9K_POW_SM(ratesArray
[rate9mb
], 8)
2610 | ATH9K_POW_SM(ratesArray
[rate6mb
], 0));
2611 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE2
,
2612 ATH9K_POW_SM(ratesArray
[rate54mb
], 24)
2613 | ATH9K_POW_SM(ratesArray
[rate48mb
], 16)
2614 | ATH9K_POW_SM(ratesArray
[rate36mb
], 8)
2615 | ATH9K_POW_SM(ratesArray
[rate24mb
], 0));
2617 if (IS_CHAN_2GHZ(chan
)) {
2618 if (OLC_FOR_AR9280_20_LATER
) {
2620 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE3
,
2621 ATH9K_POW_SM(RT_AR_DELTA(rate2s
), 24)
2622 | ATH9K_POW_SM(RT_AR_DELTA(rate2l
), 16)
2623 | ATH9K_POW_SM(ratesArray
[rateXr
], 8)
2624 | ATH9K_POW_SM(RT_AR_DELTA(rate1l
), 0));
2625 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE4
,
2626 ATH9K_POW_SM(RT_AR_DELTA(rate11s
), 24)
2627 | ATH9K_POW_SM(RT_AR_DELTA(rate11l
), 16)
2628 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s
), 8)
2629 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l
), 0));
2631 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE3
,
2632 ATH9K_POW_SM(ratesArray
[rate2s
], 24)
2633 | ATH9K_POW_SM(ratesArray
[rate2l
], 16)
2634 | ATH9K_POW_SM(ratesArray
[rateXr
], 8)
2635 | ATH9K_POW_SM(ratesArray
[rate1l
], 0));
2636 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE4
,
2637 ATH9K_POW_SM(ratesArray
[rate11s
], 24)
2638 | ATH9K_POW_SM(ratesArray
[rate11l
], 16)
2639 | ATH9K_POW_SM(ratesArray
[rate5_5s
], 8)
2640 | ATH9K_POW_SM(ratesArray
[rate5_5l
], 0));
2644 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE5
,
2645 ATH9K_POW_SM(ratesArray
[rateHt20_3
], 24)
2646 | ATH9K_POW_SM(ratesArray
[rateHt20_2
], 16)
2647 | ATH9K_POW_SM(ratesArray
[rateHt20_1
], 8)
2648 | ATH9K_POW_SM(ratesArray
[rateHt20_0
], 0));
2649 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE6
,
2650 ATH9K_POW_SM(ratesArray
[rateHt20_7
], 24)
2651 | ATH9K_POW_SM(ratesArray
[rateHt20_6
], 16)
2652 | ATH9K_POW_SM(ratesArray
[rateHt20_5
], 8)
2653 | ATH9K_POW_SM(ratesArray
[rateHt20_4
], 0));
2655 if (IS_CHAN_HT40(chan
)) {
2656 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE7
,
2657 ATH9K_POW_SM(ratesArray
[rateHt40_3
] +
2658 ht40PowerIncForPdadc
, 24)
2659 | ATH9K_POW_SM(ratesArray
[rateHt40_2
] +
2660 ht40PowerIncForPdadc
, 16)
2661 | ATH9K_POW_SM(ratesArray
[rateHt40_1
] +
2662 ht40PowerIncForPdadc
, 8)
2663 | ATH9K_POW_SM(ratesArray
[rateHt40_0
] +
2664 ht40PowerIncForPdadc
, 0));
2665 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE8
,
2666 ATH9K_POW_SM(ratesArray
[rateHt40_7
] +
2667 ht40PowerIncForPdadc
, 24)
2668 | ATH9K_POW_SM(ratesArray
[rateHt40_6
] +
2669 ht40PowerIncForPdadc
, 16)
2670 | ATH9K_POW_SM(ratesArray
[rateHt40_5
] +
2671 ht40PowerIncForPdadc
, 8)
2672 | ATH9K_POW_SM(ratesArray
[rateHt40_4
] +
2673 ht40PowerIncForPdadc
, 0));
2674 if (OLC_FOR_AR9280_20_LATER
) {
2675 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE9
,
2676 ATH9K_POW_SM(ratesArray
[rateExtOfdm
], 24)
2677 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck
), 16)
2678 | ATH9K_POW_SM(ratesArray
[rateDupOfdm
], 8)
2679 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck
), 0));
2681 REG_WRITE(ah
, AR_PHY_POWER_TX_RATE9
,
2682 ATH9K_POW_SM(ratesArray
[rateExtOfdm
], 24)
2683 | ATH9K_POW_SM(ratesArray
[rateExtCck
], 16)
2684 | ATH9K_POW_SM(ratesArray
[rateDupOfdm
], 8)
2685 | ATH9K_POW_SM(ratesArray
[rateDupCck
], 0));
2689 REG_WRITE(ah
, AR_PHY_POWER_TX_SUB
,
2690 ATH9K_POW_SM(pModal
->pwrDecreaseFor3Chain
, 6)
2691 | ATH9K_POW_SM(pModal
->pwrDecreaseFor2Chain
, 0));
2695 if (IS_CHAN_HT40(chan
))
2697 else if (IS_CHAN_HT20(chan
))
2700 if (AR_SREV_9280_10_OR_LATER(ah
))
2701 ah
->regulatory
.max_power_level
=
2702 ratesArray
[i
] + AR5416_PWR_TABLE_OFFSET
* 2;
2704 ah
->regulatory
.max_power_level
= ratesArray
[i
];
2706 switch(ar5416_get_ntxchains(ah
->txchainmask
)) {
2710 ah
->regulatory
.max_power_level
+= INCREASE_MAXPOW_BY_TWO_CHAIN
;
2713 ah
->regulatory
.max_power_level
+= INCREASE_MAXPOW_BY_THREE_CHAIN
;
2716 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
2717 "Invalid chainmask configuration\n");
2724 static u8
ath9k_hw_def_get_num_ant_config(struct ath_hw
*ah
,
2725 enum ieee80211_band freq_band
)
2727 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
2728 struct modal_eep_header
*pModal
=
2729 &(eep
->modalHeader
[ATH9K_HAL_FREQ_BAND_2GHZ
== freq_band
]);
2730 struct base_eep_header
*pBase
= &eep
->baseEepHeader
;
2735 if (pBase
->version
>= 0x0E0D)
2736 if (pModal
->useAnt1
)
2737 num_ant_config
+= 1;
2739 return num_ant_config
;
2742 static u16
ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw
*ah
,
2743 struct ath9k_channel
*chan
)
2745 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
2746 struct modal_eep_header
*pModal
=
2747 &(eep
->modalHeader
[IS_CHAN_2GHZ(chan
)]);
2749 return pModal
->antCtrlCommon
& 0xFFFF;
2752 static u16
ath9k_hw_def_get_spur_channel(struct ath_hw
*ah
, u16 i
, bool is2GHz
)
2754 #define EEP_DEF_SPURCHAN \
2755 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
2757 u16 spur_val
= AR_NO_SPUR
;
2759 DPRINTF(ah
->ah_sc
, ATH_DBG_ANI
,
2760 "Getting spur idx %d is2Ghz. %d val %x\n",
2761 i
, is2GHz
, ah
->config
.spurchans
[i
][is2GHz
]);
2763 switch (ah
->config
.spurmode
) {
2766 case SPUR_ENABLE_IOCTL
:
2767 spur_val
= ah
->config
.spurchans
[i
][is2GHz
];
2768 DPRINTF(ah
->ah_sc
, ATH_DBG_ANI
,
2769 "Getting spur val from new loc. %d\n", spur_val
);
2771 case SPUR_ENABLE_EEPROM
:
2772 spur_val
= EEP_DEF_SPURCHAN
;
2778 #undef EEP_DEF_SPURCHAN
2781 static struct eeprom_ops eep_def_ops
= {
2782 .check_eeprom
= ath9k_hw_def_check_eeprom
,
2783 .get_eeprom
= ath9k_hw_def_get_eeprom
,
2784 .fill_eeprom
= ath9k_hw_def_fill_eeprom
,
2785 .get_eeprom_ver
= ath9k_hw_def_get_eeprom_ver
,
2786 .get_eeprom_rev
= ath9k_hw_def_get_eeprom_rev
,
2787 .get_num_ant_config
= ath9k_hw_def_get_num_ant_config
,
2788 .get_eeprom_antenna_cfg
= ath9k_hw_def_get_eeprom_antenna_cfg
,
2789 .set_board_values
= ath9k_hw_def_set_board_values
,
2790 .set_addac
= ath9k_hw_def_set_addac
,
2791 .set_txpower
= ath9k_hw_def_set_txpower
,
2792 .get_spur_channel
= ath9k_hw_def_get_spur_channel
2795 int ath9k_hw_eeprom_attach(struct ath_hw
*ah
)
2799 if (AR_SREV_9285(ah
)) {
2800 ah
->eep_map
= EEP_MAP_4KBITS
;
2801 ah
->eep_ops
= &eep_4k_ops
;
2803 ah
->eep_map
= EEP_MAP_DEFAULT
;
2804 ah
->eep_ops
= &eep_def_ops
;
2807 if (!ah
->eep_ops
->fill_eeprom(ah
))
2810 status
= ah
->eep_ops
->check_eeprom(ah
);