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ath9k: Miscellaneous EEPROM handling cleanup
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath9k / hw.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45 {
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54 }
55
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57 {
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75 }
76
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78 {
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85 }
86
87 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
88 {
89 int i;
90
91 BUG_ON(timeout < AH_TIME_QUANTUM);
92
93 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
94 if ((REG_READ(ah, reg) & mask) == val)
95 return true;
96
97 udelay(AH_TIME_QUANTUM);
98 }
99
100 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
102 timeout, reg, REG_READ(ah, reg), mask, val);
103
104 return false;
105 }
106
107 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
108 {
109 u32 retval;
110 int i;
111
112 for (i = 0, retval = 0; i < n; i++) {
113 retval = (retval << 1) | (val & 1);
114 val >>= 1;
115 }
116 return retval;
117 }
118
119 bool ath9k_get_channel_edges(struct ath_hw *ah,
120 u16 flags, u16 *low,
121 u16 *high)
122 {
123 struct ath9k_hw_capabilities *pCap = &ah->caps;
124
125 if (flags & CHANNEL_5GHZ) {
126 *low = pCap->low_5ghz_chan;
127 *high = pCap->high_5ghz_chan;
128 return true;
129 }
130 if ((flags & CHANNEL_2GHZ)) {
131 *low = pCap->low_2ghz_chan;
132 *high = pCap->high_2ghz_chan;
133 return true;
134 }
135 return false;
136 }
137
138 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
139 struct ath_rate_table *rates,
140 u32 frameLen, u16 rateix,
141 bool shortPreamble)
142 {
143 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
144 u32 kbps;
145
146 kbps = rates->info[rateix].ratekbps;
147
148 if (kbps == 0)
149 return 0;
150
151 switch (rates->info[rateix].phy) {
152 case WLAN_RC_PHY_CCK:
153 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
154 if (shortPreamble && rates->info[rateix].short_preamble)
155 phyTime >>= 1;
156 numBits = frameLen << 3;
157 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
158 break;
159 case WLAN_RC_PHY_OFDM:
160 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
161 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
162 numBits = OFDM_PLCP_BITS + (frameLen << 3);
163 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
164 txTime = OFDM_SIFS_TIME_QUARTER
165 + OFDM_PREAMBLE_TIME_QUARTER
166 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
167 } else if (ah->curchan &&
168 IS_CHAN_HALF_RATE(ah->curchan)) {
169 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
170 numBits = OFDM_PLCP_BITS + (frameLen << 3);
171 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
172 txTime = OFDM_SIFS_TIME_HALF +
173 OFDM_PREAMBLE_TIME_HALF
174 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
175 } else {
176 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
177 numBits = OFDM_PLCP_BITS + (frameLen << 3);
178 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
179 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
180 + (numSymbols * OFDM_SYMBOL_TIME);
181 }
182 break;
183 default:
184 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
185 "Unknown phy %u (rate ix %u)\n",
186 rates->info[rateix].phy, rateix);
187 txTime = 0;
188 break;
189 }
190
191 return txTime;
192 }
193
194 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
195 struct ath9k_channel *chan,
196 struct chan_centers *centers)
197 {
198 int8_t extoff;
199
200 if (!IS_CHAN_HT40(chan)) {
201 centers->ctl_center = centers->ext_center =
202 centers->synth_center = chan->channel;
203 return;
204 }
205
206 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
207 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
208 centers->synth_center =
209 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
210 extoff = 1;
211 } else {
212 centers->synth_center =
213 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
214 extoff = -1;
215 }
216
217 centers->ctl_center =
218 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
219 centers->ext_center =
220 centers->synth_center + (extoff *
221 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
222 HT40_CHANNEL_CENTER_SHIFT : 15));
223 }
224
225 /******************/
226 /* Chip Revisions */
227 /******************/
228
229 static void ath9k_hw_read_revisions(struct ath_hw *ah)
230 {
231 u32 val;
232
233 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
234
235 if (val == 0xFF) {
236 val = REG_READ(ah, AR_SREV);
237 ah->hw_version.macVersion =
238 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
239 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
240 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
241 } else {
242 if (!AR_SREV_9100(ah))
243 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
244
245 ah->hw_version.macRev = val & AR_SREV_REVISION;
246
247 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
248 ah->is_pciexpress = true;
249 }
250 }
251
252 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
253 {
254 u32 val;
255 int i;
256
257 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
258
259 for (i = 0; i < 8; i++)
260 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
261 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
262 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
263
264 return ath9k_hw_reverse_bits(val, 8);
265 }
266
267 /************************************/
268 /* HW Attach, Detach, Init Routines */
269 /************************************/
270
271 static void ath9k_hw_disablepcie(struct ath_hw *ah)
272 {
273 if (AR_SREV_9100(ah))
274 return;
275
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
282 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
283 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
284 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
285
286 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
287 }
288
289 static bool ath9k_hw_chip_test(struct ath_hw *ah)
290 {
291 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
292 u32 regHold[2];
293 u32 patternData[4] = { 0x55555555,
294 0xaaaaaaaa,
295 0x66666666,
296 0x99999999 };
297 int i, j;
298
299 for (i = 0; i < 2; i++) {
300 u32 addr = regAddr[i];
301 u32 wrData, rdData;
302
303 regHold[i] = REG_READ(ah, addr);
304 for (j = 0; j < 0x100; j++) {
305 wrData = (j << 16) | j;
306 REG_WRITE(ah, addr, wrData);
307 rdData = REG_READ(ah, addr);
308 if (rdData != wrData) {
309 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
312 addr, wrData, rdData);
313 return false;
314 }
315 }
316 for (j = 0; j < 4; j++) {
317 wrData = patternData[j];
318 REG_WRITE(ah, addr, wrData);
319 rdData = REG_READ(ah, addr);
320 if (wrData != rdData) {
321 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
322 "address test failed "
323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
324 addr, wrData, rdData);
325 return false;
326 }
327 }
328 REG_WRITE(ah, regAddr[i], regHold[i]);
329 }
330 udelay(100);
331
332 return true;
333 }
334
335 static const char *ath9k_hw_devname(u16 devid)
336 {
337 switch (devid) {
338 case AR5416_DEVID_PCI:
339 return "Atheros 5416";
340 case AR5416_DEVID_PCIE:
341 return "Atheros 5418";
342 case AR9160_DEVID_PCI:
343 return "Atheros 9160";
344 case AR5416_AR9100_DEVID:
345 return "Atheros 9100";
346 case AR9280_DEVID_PCI:
347 case AR9280_DEVID_PCIE:
348 return "Atheros 9280";
349 case AR9285_DEVID_PCIE:
350 return "Atheros 9285";
351 }
352
353 return NULL;
354 }
355
356 static void ath9k_hw_set_defaults(struct ath_hw *ah)
357 {
358 int i;
359
360 ah->config.dma_beacon_response_time = 2;
361 ah->config.sw_beacon_response_time = 10;
362 ah->config.additional_swba_backoff = 0;
363 ah->config.ack_6mb = 0x0;
364 ah->config.cwm_ignore_extcca = 0;
365 ah->config.pcie_powersave_enable = 0;
366 ah->config.pcie_l1skp_enable = 0;
367 ah->config.pcie_clock_req = 0;
368 ah->config.pcie_power_reset = 0x100;
369 ah->config.pcie_restore = 0;
370 ah->config.pcie_waen = 0;
371 ah->config.analog_shiftreg = 1;
372 ah->config.ht_enable = 1;
373 ah->config.ofdm_trig_low = 200;
374 ah->config.ofdm_trig_high = 500;
375 ah->config.cck_trig_high = 200;
376 ah->config.cck_trig_low = 100;
377 ah->config.enable_ani = 1;
378 ah->config.noise_immunity_level = 4;
379 ah->config.ofdm_weaksignal_det = 1;
380 ah->config.cck_weaksignal_thr = 0;
381 ah->config.spur_immunity_level = 2;
382 ah->config.firstep_level = 0;
383 ah->config.rssi_thr_high = 40;
384 ah->config.rssi_thr_low = 7;
385 ah->config.diversity_control = 0;
386 ah->config.antenna_switch_swap = 0;
387
388 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
389 ah->config.spurchans[i][0] = AR_NO_SPUR;
390 ah->config.spurchans[i][1] = AR_NO_SPUR;
391 }
392
393 ah->config.intr_mitigation = 1;
394
395 /*
396 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
397 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
398 * This means we use it for all AR5416 devices, and the few
399 * minor PCI AR9280 devices out there.
400 *
401 * Serialization is required because these devices do not handle
402 * well the case of two concurrent reads/writes due to the latency
403 * involved. During one read/write another read/write can be issued
404 * on another CPU while the previous read/write may still be working
405 * on our hardware, if we hit this case the hardware poops in a loop.
406 * We prevent this by serializing reads and writes.
407 *
408 * This issue is not present on PCI-Express devices or pre-AR5416
409 * devices (legacy, 802.11abg).
410 */
411 if (num_possible_cpus() > 1)
412 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
413 }
414
415 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
416 int *status)
417 {
418 struct ath_hw *ah;
419
420 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
421 if (ah == NULL) {
422 DPRINTF(sc, ATH_DBG_FATAL,
423 "Cannot allocate memory for state block\n");
424 *status = -ENOMEM;
425 return NULL;
426 }
427
428 ah->ah_sc = sc;
429 ah->hw_version.magic = AR5416_MAGIC;
430 ah->regulatory.country_code = CTRY_DEFAULT;
431 ah->hw_version.devid = devid;
432 ah->hw_version.subvendorid = 0;
433
434 ah->ah_flags = 0;
435 if ((devid == AR5416_AR9100_DEVID))
436 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
437 if (!AR_SREV_9100(ah))
438 ah->ah_flags = AH_USE_EEPROM;
439
440 ah->regulatory.power_limit = MAX_RATE_POWER;
441 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
442 ah->atim_window = 0;
443 ah->diversity_control = ah->config.diversity_control;
444 ah->antenna_switch_swap =
445 ah->config.antenna_switch_swap;
446 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
447 ah->beacon_interval = 100;
448 ah->enable_32kHz_clock = DONT_USE_32KHZ;
449 ah->slottime = (u32) -1;
450 ah->acktimeout = (u32) -1;
451 ah->ctstimeout = (u32) -1;
452 ah->globaltxtimeout = (u32) -1;
453
454 ah->gbeacon_rate = 0;
455
456 return ah;
457 }
458
459 static int ath9k_hw_rfattach(struct ath_hw *ah)
460 {
461 bool rfStatus = false;
462 int ecode = 0;
463
464 rfStatus = ath9k_hw_init_rf(ah, &ecode);
465 if (!rfStatus) {
466 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
467 "RF setup failed, status %u\n", ecode);
468 return ecode;
469 }
470
471 return 0;
472 }
473
474 static int ath9k_hw_rf_claim(struct ath_hw *ah)
475 {
476 u32 val;
477
478 REG_WRITE(ah, AR_PHY(0), 0x00000007);
479
480 val = ath9k_hw_get_radiorev(ah);
481 switch (val & AR_RADIO_SREV_MAJOR) {
482 case 0:
483 val = AR_RAD5133_SREV_MAJOR;
484 break;
485 case AR_RAD5133_SREV_MAJOR:
486 case AR_RAD5122_SREV_MAJOR:
487 case AR_RAD2133_SREV_MAJOR:
488 case AR_RAD2122_SREV_MAJOR:
489 break;
490 default:
491 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
492 "5G Radio Chip Rev 0x%02X is not "
493 "supported by this driver\n",
494 ah->hw_version.analog5GhzRev);
495 return -EOPNOTSUPP;
496 }
497
498 ah->hw_version.analog5GhzRev = val;
499
500 return 0;
501 }
502
503 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
504 {
505 u32 sum;
506 int i;
507 u16 eeval;
508
509 sum = 0;
510 for (i = 0; i < 3; i++) {
511 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
512 sum += eeval;
513 ah->macaddr[2 * i] = eeval >> 8;
514 ah->macaddr[2 * i + 1] = eeval & 0xff;
515 }
516 if (sum == 0 || sum == 0xffff * 3) {
517 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
518 "mac address read failed: %pM\n",
519 ah->macaddr);
520 return -EADDRNOTAVAIL;
521 }
522
523 return 0;
524 }
525
526 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
527 {
528 u32 rxgain_type;
529
530 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
531 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
532
533 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
534 INIT_INI_ARRAY(&ah->iniModesRxGain,
535 ar9280Modes_backoff_13db_rxgain_9280_2,
536 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
537 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
538 INIT_INI_ARRAY(&ah->iniModesRxGain,
539 ar9280Modes_backoff_23db_rxgain_9280_2,
540 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
541 else
542 INIT_INI_ARRAY(&ah->iniModesRxGain,
543 ar9280Modes_original_rxgain_9280_2,
544 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
545 } else {
546 INIT_INI_ARRAY(&ah->iniModesRxGain,
547 ar9280Modes_original_rxgain_9280_2,
548 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
549 }
550 }
551
552 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
553 {
554 u32 txgain_type;
555
556 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
557 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
558
559 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
560 INIT_INI_ARRAY(&ah->iniModesTxGain,
561 ar9280Modes_high_power_tx_gain_9280_2,
562 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
563 else
564 INIT_INI_ARRAY(&ah->iniModesTxGain,
565 ar9280Modes_original_tx_gain_9280_2,
566 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
567 } else {
568 INIT_INI_ARRAY(&ah->iniModesTxGain,
569 ar9280Modes_original_tx_gain_9280_2,
570 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
571 }
572 }
573
574 static int ath9k_hw_post_attach(struct ath_hw *ah)
575 {
576 int ecode;
577
578 if (!ath9k_hw_chip_test(ah)) {
579 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
580 "hardware self-test failed\n");
581 return -ENODEV;
582 }
583
584 ecode = ath9k_hw_rf_claim(ah);
585 if (ecode != 0)
586 return ecode;
587
588 ecode = ath9k_hw_eeprom_attach(ah);
589 if (ecode != 0)
590 return ecode;
591
592 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
593 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
594
595 ecode = ath9k_hw_rfattach(ah);
596 if (ecode != 0)
597 return ecode;
598
599 if (!AR_SREV_9100(ah)) {
600 ath9k_hw_ani_setup(ah);
601 ath9k_hw_ani_attach(ah);
602 }
603
604 return 0;
605 }
606
607 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
608 int *status)
609 {
610 struct ath_hw *ah;
611 int ecode;
612 u32 i, j;
613
614 ah = ath9k_hw_newstate(devid, sc, status);
615 if (ah == NULL)
616 return NULL;
617
618 ath9k_hw_set_defaults(ah);
619
620 if (ah->config.intr_mitigation != 0)
621 ah->intr_mitigation = true;
622
623 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
624 DPRINTF(sc, ATH_DBG_RESET, "Couldn't reset chip\n");
625 ecode = -EIO;
626 goto bad;
627 }
628
629 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
630 DPRINTF(sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
631 ecode = -EIO;
632 goto bad;
633 }
634
635 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
636 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
637 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
638 ah->config.serialize_regmode =
639 SER_REG_MODE_ON;
640 } else {
641 ah->config.serialize_regmode =
642 SER_REG_MODE_OFF;
643 }
644 }
645
646 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
647 ah->config.serialize_regmode);
648
649 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
650 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
651 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
652 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
653 DPRINTF(sc, ATH_DBG_RESET,
654 "Mac Chip Rev 0x%02x.%x is not supported by "
655 "this driver\n", ah->hw_version.macVersion,
656 ah->hw_version.macRev);
657 ecode = -EOPNOTSUPP;
658 goto bad;
659 }
660
661 if (AR_SREV_9100(ah)) {
662 ah->iq_caldata.calData = &iq_cal_multi_sample;
663 ah->supp_cals = IQ_MISMATCH_CAL;
664 ah->is_pciexpress = false;
665 }
666 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
667
668 if (AR_SREV_9160_10_OR_LATER(ah)) {
669 if (AR_SREV_9280_10_OR_LATER(ah)) {
670 ah->iq_caldata.calData = &iq_cal_single_sample;
671 ah->adcgain_caldata.calData =
672 &adc_gain_cal_single_sample;
673 ah->adcdc_caldata.calData =
674 &adc_dc_cal_single_sample;
675 ah->adcdc_calinitdata.calData =
676 &adc_init_dc_cal;
677 } else {
678 ah->iq_caldata.calData = &iq_cal_multi_sample;
679 ah->adcgain_caldata.calData =
680 &adc_gain_cal_multi_sample;
681 ah->adcdc_caldata.calData =
682 &adc_dc_cal_multi_sample;
683 ah->adcdc_calinitdata.calData =
684 &adc_init_dc_cal;
685 }
686 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
687 }
688
689 ah->ani_function = ATH9K_ANI_ALL;
690 if (AR_SREV_9280_10_OR_LATER(ah))
691 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
692
693 DPRINTF(sc, ATH_DBG_RESET,
694 "This Mac Chip Rev 0x%02x.%x is \n",
695 ah->hw_version.macVersion, ah->hw_version.macRev);
696
697 if (AR_SREV_9285_12_OR_LATER(ah)) {
698
699 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
700 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
701 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
702 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
703
704 if (ah->config.pcie_clock_req) {
705 INIT_INI_ARRAY(&ah->iniPcieSerdes,
706 ar9285PciePhy_clkreq_off_L1_9285_1_2,
707 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
708 } else {
709 INIT_INI_ARRAY(&ah->iniPcieSerdes,
710 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
711 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
712 2);
713 }
714 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
715 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
716 ARRAY_SIZE(ar9285Modes_9285), 6);
717 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
718 ARRAY_SIZE(ar9285Common_9285), 2);
719
720 if (ah->config.pcie_clock_req) {
721 INIT_INI_ARRAY(&ah->iniPcieSerdes,
722 ar9285PciePhy_clkreq_off_L1_9285,
723 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
724 } else {
725 INIT_INI_ARRAY(&ah->iniPcieSerdes,
726 ar9285PciePhy_clkreq_always_on_L1_9285,
727 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
728 }
729 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
730 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
731 ARRAY_SIZE(ar9280Modes_9280_2), 6);
732 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
733 ARRAY_SIZE(ar9280Common_9280_2), 2);
734
735 if (ah->config.pcie_clock_req) {
736 INIT_INI_ARRAY(&ah->iniPcieSerdes,
737 ar9280PciePhy_clkreq_off_L1_9280,
738 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
739 } else {
740 INIT_INI_ARRAY(&ah->iniPcieSerdes,
741 ar9280PciePhy_clkreq_always_on_L1_9280,
742 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
743 }
744 INIT_INI_ARRAY(&ah->iniModesAdditional,
745 ar9280Modes_fast_clock_9280_2,
746 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
747 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
748 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
749 ARRAY_SIZE(ar9280Modes_9280), 6);
750 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
751 ARRAY_SIZE(ar9280Common_9280), 2);
752 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
753 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
754 ARRAY_SIZE(ar5416Modes_9160), 6);
755 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
756 ARRAY_SIZE(ar5416Common_9160), 2);
757 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
758 ARRAY_SIZE(ar5416Bank0_9160), 2);
759 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
760 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
761 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
762 ARRAY_SIZE(ar5416Bank1_9160), 2);
763 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
764 ARRAY_SIZE(ar5416Bank2_9160), 2);
765 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
766 ARRAY_SIZE(ar5416Bank3_9160), 3);
767 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
768 ARRAY_SIZE(ar5416Bank6_9160), 3);
769 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
770 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
771 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
772 ARRAY_SIZE(ar5416Bank7_9160), 2);
773 if (AR_SREV_9160_11(ah)) {
774 INIT_INI_ARRAY(&ah->iniAddac,
775 ar5416Addac_91601_1,
776 ARRAY_SIZE(ar5416Addac_91601_1), 2);
777 } else {
778 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
779 ARRAY_SIZE(ar5416Addac_9160), 2);
780 }
781 } else if (AR_SREV_9100_OR_LATER(ah)) {
782 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
783 ARRAY_SIZE(ar5416Modes_9100), 6);
784 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
785 ARRAY_SIZE(ar5416Common_9100), 2);
786 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
787 ARRAY_SIZE(ar5416Bank0_9100), 2);
788 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
789 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
790 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
791 ARRAY_SIZE(ar5416Bank1_9100), 2);
792 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
793 ARRAY_SIZE(ar5416Bank2_9100), 2);
794 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
795 ARRAY_SIZE(ar5416Bank3_9100), 3);
796 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
797 ARRAY_SIZE(ar5416Bank6_9100), 3);
798 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
799 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
800 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
801 ARRAY_SIZE(ar5416Bank7_9100), 2);
802 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
803 ARRAY_SIZE(ar5416Addac_9100), 2);
804 } else {
805 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
806 ARRAY_SIZE(ar5416Modes), 6);
807 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
808 ARRAY_SIZE(ar5416Common), 2);
809 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
810 ARRAY_SIZE(ar5416Bank0), 2);
811 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
812 ARRAY_SIZE(ar5416BB_RfGain), 3);
813 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
814 ARRAY_SIZE(ar5416Bank1), 2);
815 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
816 ARRAY_SIZE(ar5416Bank2), 2);
817 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
818 ARRAY_SIZE(ar5416Bank3), 3);
819 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
820 ARRAY_SIZE(ar5416Bank6), 3);
821 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
822 ARRAY_SIZE(ar5416Bank6TPC), 3);
823 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
824 ARRAY_SIZE(ar5416Bank7), 2);
825 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
826 ARRAY_SIZE(ar5416Addac), 2);
827 }
828
829 if (ah->is_pciexpress)
830 ath9k_hw_configpcipowersave(ah, 0);
831 else
832 ath9k_hw_disablepcie(ah);
833
834 ecode = ath9k_hw_post_attach(ah);
835 if (ecode != 0)
836 goto bad;
837
838 if (AR_SREV_9285_12_OR_LATER(ah)) {
839 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
840
841 /* txgain table */
842 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
843 INIT_INI_ARRAY(&ah->iniModesTxGain,
844 ar9285Modes_high_power_tx_gain_9285_1_2,
845 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
846 } else {
847 INIT_INI_ARRAY(&ah->iniModesTxGain,
848 ar9285Modes_original_tx_gain_9285_1_2,
849 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
850 }
851
852 }
853
854 /* rxgain table */
855 if (AR_SREV_9280_20(ah))
856 ath9k_hw_init_rxgain_ini(ah);
857
858 /* txgain table */
859 if (AR_SREV_9280_20(ah))
860 ath9k_hw_init_txgain_ini(ah);
861
862 if (!ath9k_hw_fill_cap_info(ah)) {
863 DPRINTF(sc, ATH_DBG_RESET, "failed ath9k_hw_fill_cap_info\n");
864 ecode = -EINVAL;
865 goto bad;
866 }
867
868 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
869 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
870
871 /* EEPROM Fixup */
872 for (i = 0; i < ah->iniModes.ia_rows; i++) {
873 u32 reg = INI_RA(&ah->iniModes, i, 0);
874
875 for (j = 1; j < ah->iniModes.ia_columns; j++) {
876 u32 val = INI_RA(&ah->iniModes, i, j);
877
878 INI_RA(&ah->iniModes, i, j) =
879 ath9k_hw_ini_fixup(ah,
880 &ah->eeprom.def,
881 reg, val);
882 }
883 }
884 }
885
886 ecode = ath9k_hw_init_macaddr(ah);
887 if (ecode != 0) {
888 DPRINTF(sc, ATH_DBG_RESET,
889 "failed initializing mac address\n");
890 goto bad;
891 }
892
893 if (AR_SREV_9285(ah))
894 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
895 else
896 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
897
898 ath9k_init_nfcal_hist_buffer(ah);
899
900 return ah;
901 bad:
902 if (ah)
903 ath9k_hw_detach(ah);
904 if (status)
905 *status = ecode;
906
907 return NULL;
908 }
909
910 static void ath9k_hw_init_bb(struct ath_hw *ah,
911 struct ath9k_channel *chan)
912 {
913 u32 synthDelay;
914
915 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
916 if (IS_CHAN_B(chan))
917 synthDelay = (4 * synthDelay) / 22;
918 else
919 synthDelay /= 10;
920
921 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
922
923 udelay(synthDelay + BASE_ACTIVATE_DELAY);
924 }
925
926 static void ath9k_hw_init_qos(struct ath_hw *ah)
927 {
928 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
929 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
930
931 REG_WRITE(ah, AR_QOS_NO_ACK,
932 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
933 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
934 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
935
936 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
937 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
938 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
939 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
940 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
941 }
942
943 static void ath9k_hw_init_pll(struct ath_hw *ah,
944 struct ath9k_channel *chan)
945 {
946 u32 pll;
947
948 if (AR_SREV_9100(ah)) {
949 if (chan && IS_CHAN_5GHZ(chan))
950 pll = 0x1450;
951 else
952 pll = 0x1458;
953 } else {
954 if (AR_SREV_9280_10_OR_LATER(ah)) {
955 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
956
957 if (chan && IS_CHAN_HALF_RATE(chan))
958 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
959 else if (chan && IS_CHAN_QUARTER_RATE(chan))
960 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
961
962 if (chan && IS_CHAN_5GHZ(chan)) {
963 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
964
965
966 if (AR_SREV_9280_20(ah)) {
967 if (((chan->channel % 20) == 0)
968 || ((chan->channel % 10) == 0))
969 pll = 0x2850;
970 else
971 pll = 0x142c;
972 }
973 } else {
974 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
975 }
976
977 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
978
979 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
980
981 if (chan && IS_CHAN_HALF_RATE(chan))
982 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
983 else if (chan && IS_CHAN_QUARTER_RATE(chan))
984 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
985
986 if (chan && IS_CHAN_5GHZ(chan))
987 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
988 else
989 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
990 } else {
991 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
992
993 if (chan && IS_CHAN_HALF_RATE(chan))
994 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
995 else if (chan && IS_CHAN_QUARTER_RATE(chan))
996 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
997
998 if (chan && IS_CHAN_5GHZ(chan))
999 pll |= SM(0xa, AR_RTC_PLL_DIV);
1000 else
1001 pll |= SM(0xb, AR_RTC_PLL_DIV);
1002 }
1003 }
1004 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1005
1006 udelay(RTC_PLL_SETTLE_DELAY);
1007
1008 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1009 }
1010
1011 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1012 {
1013 int rx_chainmask, tx_chainmask;
1014
1015 rx_chainmask = ah->rxchainmask;
1016 tx_chainmask = ah->txchainmask;
1017
1018 switch (rx_chainmask) {
1019 case 0x5:
1020 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1021 AR_PHY_SWAP_ALT_CHAIN);
1022 case 0x3:
1023 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1024 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1025 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1026 break;
1027 }
1028 case 0x1:
1029 case 0x2:
1030 case 0x7:
1031 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1032 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1033 break;
1034 default:
1035 break;
1036 }
1037
1038 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1039 if (tx_chainmask == 0x5) {
1040 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1041 AR_PHY_SWAP_ALT_CHAIN);
1042 }
1043 if (AR_SREV_9100(ah))
1044 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1045 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1046 }
1047
1048 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1049 enum nl80211_iftype opmode)
1050 {
1051 ah->mask_reg = AR_IMR_TXERR |
1052 AR_IMR_TXURN |
1053 AR_IMR_RXERR |
1054 AR_IMR_RXORN |
1055 AR_IMR_BCNMISC;
1056
1057 if (ah->intr_mitigation)
1058 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1059 else
1060 ah->mask_reg |= AR_IMR_RXOK;
1061
1062 ah->mask_reg |= AR_IMR_TXOK;
1063
1064 if (opmode == NL80211_IFTYPE_AP)
1065 ah->mask_reg |= AR_IMR_MIB;
1066
1067 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1068 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1069
1070 if (!AR_SREV_9100(ah)) {
1071 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1072 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1073 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1074 }
1075 }
1076
1077 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1078 {
1079 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1080 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1081 ah->acktimeout = (u32) -1;
1082 return false;
1083 } else {
1084 REG_RMW_FIELD(ah, AR_TIME_OUT,
1085 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1086 ah->acktimeout = us;
1087 return true;
1088 }
1089 }
1090
1091 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1092 {
1093 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1094 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1095 ah->ctstimeout = (u32) -1;
1096 return false;
1097 } else {
1098 REG_RMW_FIELD(ah, AR_TIME_OUT,
1099 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1100 ah->ctstimeout = us;
1101 return true;
1102 }
1103 }
1104
1105 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1106 {
1107 if (tu > 0xFFFF) {
1108 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1109 "bad global tx timeout %u\n", tu);
1110 ah->globaltxtimeout = (u32) -1;
1111 return false;
1112 } else {
1113 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1114 ah->globaltxtimeout = tu;
1115 return true;
1116 }
1117 }
1118
1119 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1120 {
1121 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1122 ah->misc_mode);
1123
1124 if (ah->misc_mode != 0)
1125 REG_WRITE(ah, AR_PCU_MISC,
1126 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1127 if (ah->slottime != (u32) -1)
1128 ath9k_hw_setslottime(ah, ah->slottime);
1129 if (ah->acktimeout != (u32) -1)
1130 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1131 if (ah->ctstimeout != (u32) -1)
1132 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1133 if (ah->globaltxtimeout != (u32) -1)
1134 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1135 }
1136
1137 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1138 {
1139 return vendorid == ATHEROS_VENDOR_ID ?
1140 ath9k_hw_devname(devid) : NULL;
1141 }
1142
1143 void ath9k_hw_detach(struct ath_hw *ah)
1144 {
1145 if (!AR_SREV_9100(ah))
1146 ath9k_hw_ani_detach(ah);
1147
1148 ath9k_hw_rfdetach(ah);
1149 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1150 kfree(ah);
1151 }
1152
1153 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1154 {
1155 struct ath_hw *ah = NULL;
1156
1157 switch (devid) {
1158 case AR5416_DEVID_PCI:
1159 case AR5416_DEVID_PCIE:
1160 case AR5416_AR9100_DEVID:
1161 case AR9160_DEVID_PCI:
1162 case AR9280_DEVID_PCI:
1163 case AR9280_DEVID_PCIE:
1164 case AR9285_DEVID_PCIE:
1165 ah = ath9k_hw_do_attach(devid, sc, error);
1166 break;
1167 default:
1168 *error = -ENXIO;
1169 break;
1170 }
1171
1172 return ah;
1173 }
1174
1175 /*******/
1176 /* INI */
1177 /*******/
1178
1179 static void ath9k_hw_override_ini(struct ath_hw *ah,
1180 struct ath9k_channel *chan)
1181 {
1182 /*
1183 * Set the RX_ABORT and RX_DIS and clear if off only after
1184 * RXE is set for MAC. This prevents frames with corrupted
1185 * descriptor status.
1186 */
1187 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1188
1189
1190 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1191 AR_SREV_9280_10_OR_LATER(ah))
1192 return;
1193
1194 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1195 }
1196
1197 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1198 struct ar5416_eeprom_def *pEepData,
1199 u32 reg, u32 value)
1200 {
1201 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1202
1203 switch (ah->hw_version.devid) {
1204 case AR9280_DEVID_PCI:
1205 if (reg == 0x7894) {
1206 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1207 "ini VAL: %x EEPROM: %x\n", value,
1208 (pBase->version & 0xff));
1209
1210 if ((pBase->version & 0xff) > 0x0a) {
1211 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1212 "PWDCLKIND: %d\n",
1213 pBase->pwdclkind);
1214 value &= ~AR_AN_TOP2_PWDCLKIND;
1215 value |= AR_AN_TOP2_PWDCLKIND &
1216 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1217 } else {
1218 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1219 "PWDCLKIND Earlier Rev\n");
1220 }
1221
1222 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1223 "final ini VAL: %x\n", value);
1224 }
1225 break;
1226 }
1227
1228 return value;
1229 }
1230
1231 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1232 struct ar5416_eeprom_def *pEepData,
1233 u32 reg, u32 value)
1234 {
1235 if (ah->eep_map == EEP_MAP_4KBITS)
1236 return value;
1237 else
1238 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1239 }
1240
1241 static void ath9k_olc_init(struct ath_hw *ah)
1242 {
1243 u32 i;
1244
1245 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1246 ah->originalGain[i] =
1247 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1248 AR_PHY_TX_GAIN);
1249 ah->PDADCdelta = 0;
1250 }
1251
1252 static int ath9k_hw_process_ini(struct ath_hw *ah,
1253 struct ath9k_channel *chan,
1254 enum ath9k_ht_macmode macmode)
1255 {
1256 int i, regWrites = 0;
1257 struct ieee80211_channel *channel = chan->chan;
1258 u32 modesIndex, freqIndex;
1259 int status;
1260
1261 switch (chan->chanmode) {
1262 case CHANNEL_A:
1263 case CHANNEL_A_HT20:
1264 modesIndex = 1;
1265 freqIndex = 1;
1266 break;
1267 case CHANNEL_A_HT40PLUS:
1268 case CHANNEL_A_HT40MINUS:
1269 modesIndex = 2;
1270 freqIndex = 1;
1271 break;
1272 case CHANNEL_G:
1273 case CHANNEL_G_HT20:
1274 case CHANNEL_B:
1275 modesIndex = 4;
1276 freqIndex = 2;
1277 break;
1278 case CHANNEL_G_HT40PLUS:
1279 case CHANNEL_G_HT40MINUS:
1280 modesIndex = 3;
1281 freqIndex = 2;
1282 break;
1283
1284 default:
1285 return -EINVAL;
1286 }
1287
1288 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1289 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1290 ah->eep_ops->set_addac(ah, chan);
1291
1292 if (AR_SREV_5416_22_OR_LATER(ah)) {
1293 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1294 } else {
1295 struct ar5416IniArray temp;
1296 u32 addacSize =
1297 sizeof(u32) * ah->iniAddac.ia_rows *
1298 ah->iniAddac.ia_columns;
1299
1300 memcpy(ah->addac5416_21,
1301 ah->iniAddac.ia_array, addacSize);
1302
1303 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1304
1305 temp.ia_array = ah->addac5416_21;
1306 temp.ia_columns = ah->iniAddac.ia_columns;
1307 temp.ia_rows = ah->iniAddac.ia_rows;
1308 REG_WRITE_ARRAY(&temp, 1, regWrites);
1309 }
1310
1311 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1312
1313 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1314 u32 reg = INI_RA(&ah->iniModes, i, 0);
1315 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1316
1317 REG_WRITE(ah, reg, val);
1318
1319 if (reg >= 0x7800 && reg < 0x78a0
1320 && ah->config.analog_shiftreg) {
1321 udelay(100);
1322 }
1323
1324 DO_DELAY(regWrites);
1325 }
1326
1327 if (AR_SREV_9280(ah))
1328 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1329
1330 if (AR_SREV_9280(ah) || (AR_SREV_9285(ah) &&
1331 AR_SREV_9285_12_OR_LATER(ah)))
1332 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1333
1334 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1335 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1336 u32 val = INI_RA(&ah->iniCommon, i, 1);
1337
1338 REG_WRITE(ah, reg, val);
1339
1340 if (reg >= 0x7800 && reg < 0x78a0
1341 && ah->config.analog_shiftreg) {
1342 udelay(100);
1343 }
1344
1345 DO_DELAY(regWrites);
1346 }
1347
1348 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1349
1350 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1351 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1352 regWrites);
1353 }
1354
1355 ath9k_hw_override_ini(ah, chan);
1356 ath9k_hw_set_regs(ah, chan, macmode);
1357 ath9k_hw_init_chain_masks(ah);
1358
1359 if (OLC_FOR_AR9280_20_LATER)
1360 ath9k_olc_init(ah);
1361
1362 status = ah->eep_ops->set_txpower(ah, chan,
1363 ath9k_regd_get_ctl(ah, chan),
1364 channel->max_antenna_gain * 2,
1365 channel->max_power * 2,
1366 min((u32) MAX_RATE_POWER,
1367 (u32) ah->regulatory.power_limit));
1368 if (status != 0) {
1369 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1370 "error init'ing transmit power\n");
1371 return -EIO;
1372 }
1373
1374 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1375 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1376 "ar5416SetRfRegs failed\n");
1377 return -EIO;
1378 }
1379
1380 return 0;
1381 }
1382
1383 /****************************************/
1384 /* Reset and Channel Switching Routines */
1385 /****************************************/
1386
1387 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1388 {
1389 u32 rfMode = 0;
1390
1391 if (chan == NULL)
1392 return;
1393
1394 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1395 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1396
1397 if (!AR_SREV_9280_10_OR_LATER(ah))
1398 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1399 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1400
1401 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1402 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1403
1404 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1405 }
1406
1407 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1408 {
1409 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1410 }
1411
1412 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1413 {
1414 u32 regval;
1415
1416 regval = REG_READ(ah, AR_AHB_MODE);
1417 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1418
1419 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1420 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1421
1422 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1423
1424 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1425 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1426
1427 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1428
1429 if (AR_SREV_9285(ah)) {
1430 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1431 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1432 } else {
1433 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1434 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1435 }
1436 }
1437
1438 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1439 {
1440 u32 val;
1441
1442 val = REG_READ(ah, AR_STA_ID1);
1443 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1444 switch (opmode) {
1445 case NL80211_IFTYPE_AP:
1446 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1447 | AR_STA_ID1_KSRCH_MODE);
1448 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1449 break;
1450 case NL80211_IFTYPE_ADHOC:
1451 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1452 | AR_STA_ID1_KSRCH_MODE);
1453 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1454 break;
1455 case NL80211_IFTYPE_STATION:
1456 case NL80211_IFTYPE_MONITOR:
1457 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1458 break;
1459 }
1460 }
1461
1462 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1463 u32 coef_scaled,
1464 u32 *coef_mantissa,
1465 u32 *coef_exponent)
1466 {
1467 u32 coef_exp, coef_man;
1468
1469 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1470 if ((coef_scaled >> coef_exp) & 0x1)
1471 break;
1472
1473 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1474
1475 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1476
1477 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1478 *coef_exponent = coef_exp - 16;
1479 }
1480
1481 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1482 struct ath9k_channel *chan)
1483 {
1484 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1485 u32 clockMhzScaled = 0x64000000;
1486 struct chan_centers centers;
1487
1488 if (IS_CHAN_HALF_RATE(chan))
1489 clockMhzScaled = clockMhzScaled >> 1;
1490 else if (IS_CHAN_QUARTER_RATE(chan))
1491 clockMhzScaled = clockMhzScaled >> 2;
1492
1493 ath9k_hw_get_channel_centers(ah, chan, &centers);
1494 coef_scaled = clockMhzScaled / centers.synth_center;
1495
1496 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1497 &ds_coef_exp);
1498
1499 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1500 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1501 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1502 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1503
1504 coef_scaled = (9 * coef_scaled) / 10;
1505
1506 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1507 &ds_coef_exp);
1508
1509 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1510 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1511 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1512 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1513 }
1514
1515 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1516 {
1517 u32 rst_flags;
1518 u32 tmpReg;
1519
1520 if (AR_SREV_9100(ah)) {
1521 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1522 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1523 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1524 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1525 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1526 }
1527
1528 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1529 AR_RTC_FORCE_WAKE_ON_INT);
1530
1531 if (AR_SREV_9100(ah)) {
1532 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1533 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1534 } else {
1535 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1536 if (tmpReg &
1537 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1538 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1539 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1540 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1541 } else {
1542 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1543 }
1544
1545 rst_flags = AR_RTC_RC_MAC_WARM;
1546 if (type == ATH9K_RESET_COLD)
1547 rst_flags |= AR_RTC_RC_MAC_COLD;
1548 }
1549
1550 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1551 udelay(50);
1552
1553 REG_WRITE(ah, AR_RTC_RC, 0);
1554 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1555 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1556 "RTC stuck in MAC reset\n");
1557 return false;
1558 }
1559
1560 if (!AR_SREV_9100(ah))
1561 REG_WRITE(ah, AR_RC, 0);
1562
1563 ath9k_hw_init_pll(ah, NULL);
1564
1565 if (AR_SREV_9100(ah))
1566 udelay(50);
1567
1568 return true;
1569 }
1570
1571 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1572 {
1573 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1574 AR_RTC_FORCE_WAKE_ON_INT);
1575
1576 REG_WRITE(ah, AR_RTC_RESET, 0);
1577 udelay(2);
1578 REG_WRITE(ah, AR_RTC_RESET, 1);
1579
1580 if (!ath9k_hw_wait(ah,
1581 AR_RTC_STATUS,
1582 AR_RTC_STATUS_M,
1583 AR_RTC_STATUS_ON,
1584 AH_WAIT_TIMEOUT)) {
1585 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1586 return false;
1587 }
1588
1589 ath9k_hw_read_revisions(ah);
1590
1591 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1592 }
1593
1594 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1595 {
1596 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1597 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1598
1599 switch (type) {
1600 case ATH9K_RESET_POWER_ON:
1601 return ath9k_hw_set_reset_power_on(ah);
1602 break;
1603 case ATH9K_RESET_WARM:
1604 case ATH9K_RESET_COLD:
1605 return ath9k_hw_set_reset(ah, type);
1606 break;
1607 default:
1608 return false;
1609 }
1610 }
1611
1612 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1613 enum ath9k_ht_macmode macmode)
1614 {
1615 u32 phymode;
1616 u32 enableDacFifo = 0;
1617
1618 if (AR_SREV_9285_10_OR_LATER(ah))
1619 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1620 AR_PHY_FC_ENABLE_DAC_FIFO);
1621
1622 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1623 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1624
1625 if (IS_CHAN_HT40(chan)) {
1626 phymode |= AR_PHY_FC_DYN2040_EN;
1627
1628 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1629 (chan->chanmode == CHANNEL_G_HT40PLUS))
1630 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1631
1632 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1633 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1634 }
1635 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1636
1637 ath9k_hw_set11nmac2040(ah, macmode);
1638
1639 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1640 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1641 }
1642
1643 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1644 struct ath9k_channel *chan)
1645 {
1646 if (OLC_FOR_AR9280_20_LATER) {
1647 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1648 return false;
1649 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1650 return false;
1651
1652 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1653 return false;
1654
1655 ah->chip_fullsleep = false;
1656 ath9k_hw_init_pll(ah, chan);
1657 ath9k_hw_set_rfmode(ah, chan);
1658
1659 return true;
1660 }
1661
1662 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1663 struct ath9k_channel *chan,
1664 enum ath9k_ht_macmode macmode)
1665 {
1666 struct ieee80211_channel *channel = chan->chan;
1667 u32 synthDelay, qnum;
1668
1669 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1670 if (ath9k_hw_numtxpending(ah, qnum)) {
1671 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1672 "Transmit frames pending on queue %d\n", qnum);
1673 return false;
1674 }
1675 }
1676
1677 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1678 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1679 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1680 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1681 "Could not kill baseband RX\n");
1682 return false;
1683 }
1684
1685 ath9k_hw_set_regs(ah, chan, macmode);
1686
1687 if (AR_SREV_9280_10_OR_LATER(ah)) {
1688 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1689 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1690 "failed to set channel\n");
1691 return false;
1692 }
1693 } else {
1694 if (!(ath9k_hw_set_channel(ah, chan))) {
1695 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1696 "failed to set channel\n");
1697 return false;
1698 }
1699 }
1700
1701 if (ah->eep_ops->set_txpower(ah, chan,
1702 ath9k_regd_get_ctl(ah, chan),
1703 channel->max_antenna_gain * 2,
1704 channel->max_power * 2,
1705 min((u32) MAX_RATE_POWER,
1706 (u32) ah->regulatory.power_limit)) != 0) {
1707 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1708 "error init'ing transmit power\n");
1709 return false;
1710 }
1711
1712 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1713 if (IS_CHAN_B(chan))
1714 synthDelay = (4 * synthDelay) / 22;
1715 else
1716 synthDelay /= 10;
1717
1718 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1719
1720 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1721
1722 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1723 ath9k_hw_set_delta_slope(ah, chan);
1724
1725 if (AR_SREV_9280_10_OR_LATER(ah))
1726 ath9k_hw_9280_spur_mitigate(ah, chan);
1727 else
1728 ath9k_hw_spur_mitigate(ah, chan);
1729
1730 if (!chan->oneTimeCalsDone)
1731 chan->oneTimeCalsDone = true;
1732
1733 return true;
1734 }
1735
1736 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1737 {
1738 int bb_spur = AR_NO_SPUR;
1739 int freq;
1740 int bin, cur_bin;
1741 int bb_spur_off, spur_subchannel_sd;
1742 int spur_freq_sd;
1743 int spur_delta_phase;
1744 int denominator;
1745 int upper, lower, cur_vit_mask;
1746 int tmp, newVal;
1747 int i;
1748 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1749 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1750 };
1751 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1752 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1753 };
1754 int inc[4] = { 0, 100, 0, 0 };
1755 struct chan_centers centers;
1756
1757 int8_t mask_m[123];
1758 int8_t mask_p[123];
1759 int8_t mask_amt;
1760 int tmp_mask;
1761 int cur_bb_spur;
1762 bool is2GHz = IS_CHAN_2GHZ(chan);
1763
1764 memset(&mask_m, 0, sizeof(int8_t) * 123);
1765 memset(&mask_p, 0, sizeof(int8_t) * 123);
1766
1767 ath9k_hw_get_channel_centers(ah, chan, &centers);
1768 freq = centers.synth_center;
1769
1770 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1771 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1772 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1773
1774 if (is2GHz)
1775 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1776 else
1777 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1778
1779 if (AR_NO_SPUR == cur_bb_spur)
1780 break;
1781 cur_bb_spur = cur_bb_spur - freq;
1782
1783 if (IS_CHAN_HT40(chan)) {
1784 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1785 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1786 bb_spur = cur_bb_spur;
1787 break;
1788 }
1789 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1790 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1791 bb_spur = cur_bb_spur;
1792 break;
1793 }
1794 }
1795
1796 if (AR_NO_SPUR == bb_spur) {
1797 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1798 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1799 return;
1800 } else {
1801 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1802 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1803 }
1804
1805 bin = bb_spur * 320;
1806
1807 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1808
1809 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1810 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1811 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1812 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1813 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1814
1815 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1816 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1817 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1818 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1819 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1820 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1821
1822 if (IS_CHAN_HT40(chan)) {
1823 if (bb_spur < 0) {
1824 spur_subchannel_sd = 1;
1825 bb_spur_off = bb_spur + 10;
1826 } else {
1827 spur_subchannel_sd = 0;
1828 bb_spur_off = bb_spur - 10;
1829 }
1830 } else {
1831 spur_subchannel_sd = 0;
1832 bb_spur_off = bb_spur;
1833 }
1834
1835 if (IS_CHAN_HT40(chan))
1836 spur_delta_phase =
1837 ((bb_spur * 262144) /
1838 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1839 else
1840 spur_delta_phase =
1841 ((bb_spur * 524288) /
1842 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1843
1844 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1845 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1846
1847 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1848 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1849 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1850 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1851
1852 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1853 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1854
1855 cur_bin = -6000;
1856 upper = bin + 100;
1857 lower = bin - 100;
1858
1859 for (i = 0; i < 4; i++) {
1860 int pilot_mask = 0;
1861 int chan_mask = 0;
1862 int bp = 0;
1863 for (bp = 0; bp < 30; bp++) {
1864 if ((cur_bin > lower) && (cur_bin < upper)) {
1865 pilot_mask = pilot_mask | 0x1 << bp;
1866 chan_mask = chan_mask | 0x1 << bp;
1867 }
1868 cur_bin += 100;
1869 }
1870 cur_bin += inc[i];
1871 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1872 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1873 }
1874
1875 cur_vit_mask = 6100;
1876 upper = bin + 120;
1877 lower = bin - 120;
1878
1879 for (i = 0; i < 123; i++) {
1880 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1881
1882 /* workaround for gcc bug #37014 */
1883 volatile int tmp_v = abs(cur_vit_mask - bin);
1884
1885 if (tmp_v < 75)
1886 mask_amt = 1;
1887 else
1888 mask_amt = 0;
1889 if (cur_vit_mask < 0)
1890 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1891 else
1892 mask_p[cur_vit_mask / 100] = mask_amt;
1893 }
1894 cur_vit_mask -= 100;
1895 }
1896
1897 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1898 | (mask_m[48] << 26) | (mask_m[49] << 24)
1899 | (mask_m[50] << 22) | (mask_m[51] << 20)
1900 | (mask_m[52] << 18) | (mask_m[53] << 16)
1901 | (mask_m[54] << 14) | (mask_m[55] << 12)
1902 | (mask_m[56] << 10) | (mask_m[57] << 8)
1903 | (mask_m[58] << 6) | (mask_m[59] << 4)
1904 | (mask_m[60] << 2) | (mask_m[61] << 0);
1905 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1906 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1907
1908 tmp_mask = (mask_m[31] << 28)
1909 | (mask_m[32] << 26) | (mask_m[33] << 24)
1910 | (mask_m[34] << 22) | (mask_m[35] << 20)
1911 | (mask_m[36] << 18) | (mask_m[37] << 16)
1912 | (mask_m[48] << 14) | (mask_m[39] << 12)
1913 | (mask_m[40] << 10) | (mask_m[41] << 8)
1914 | (mask_m[42] << 6) | (mask_m[43] << 4)
1915 | (mask_m[44] << 2) | (mask_m[45] << 0);
1916 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1917 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1918
1919 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1920 | (mask_m[18] << 26) | (mask_m[18] << 24)
1921 | (mask_m[20] << 22) | (mask_m[20] << 20)
1922 | (mask_m[22] << 18) | (mask_m[22] << 16)
1923 | (mask_m[24] << 14) | (mask_m[24] << 12)
1924 | (mask_m[25] << 10) | (mask_m[26] << 8)
1925 | (mask_m[27] << 6) | (mask_m[28] << 4)
1926 | (mask_m[29] << 2) | (mask_m[30] << 0);
1927 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1928 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1929
1930 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1931 | (mask_m[2] << 26) | (mask_m[3] << 24)
1932 | (mask_m[4] << 22) | (mask_m[5] << 20)
1933 | (mask_m[6] << 18) | (mask_m[7] << 16)
1934 | (mask_m[8] << 14) | (mask_m[9] << 12)
1935 | (mask_m[10] << 10) | (mask_m[11] << 8)
1936 | (mask_m[12] << 6) | (mask_m[13] << 4)
1937 | (mask_m[14] << 2) | (mask_m[15] << 0);
1938 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1939 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1940
1941 tmp_mask = (mask_p[15] << 28)
1942 | (mask_p[14] << 26) | (mask_p[13] << 24)
1943 | (mask_p[12] << 22) | (mask_p[11] << 20)
1944 | (mask_p[10] << 18) | (mask_p[9] << 16)
1945 | (mask_p[8] << 14) | (mask_p[7] << 12)
1946 | (mask_p[6] << 10) | (mask_p[5] << 8)
1947 | (mask_p[4] << 6) | (mask_p[3] << 4)
1948 | (mask_p[2] << 2) | (mask_p[1] << 0);
1949 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1950 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1951
1952 tmp_mask = (mask_p[30] << 28)
1953 | (mask_p[29] << 26) | (mask_p[28] << 24)
1954 | (mask_p[27] << 22) | (mask_p[26] << 20)
1955 | (mask_p[25] << 18) | (mask_p[24] << 16)
1956 | (mask_p[23] << 14) | (mask_p[22] << 12)
1957 | (mask_p[21] << 10) | (mask_p[20] << 8)
1958 | (mask_p[19] << 6) | (mask_p[18] << 4)
1959 | (mask_p[17] << 2) | (mask_p[16] << 0);
1960 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1961 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1962
1963 tmp_mask = (mask_p[45] << 28)
1964 | (mask_p[44] << 26) | (mask_p[43] << 24)
1965 | (mask_p[42] << 22) | (mask_p[41] << 20)
1966 | (mask_p[40] << 18) | (mask_p[39] << 16)
1967 | (mask_p[38] << 14) | (mask_p[37] << 12)
1968 | (mask_p[36] << 10) | (mask_p[35] << 8)
1969 | (mask_p[34] << 6) | (mask_p[33] << 4)
1970 | (mask_p[32] << 2) | (mask_p[31] << 0);
1971 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1972 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1973
1974 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1975 | (mask_p[59] << 26) | (mask_p[58] << 24)
1976 | (mask_p[57] << 22) | (mask_p[56] << 20)
1977 | (mask_p[55] << 18) | (mask_p[54] << 16)
1978 | (mask_p[53] << 14) | (mask_p[52] << 12)
1979 | (mask_p[51] << 10) | (mask_p[50] << 8)
1980 | (mask_p[49] << 6) | (mask_p[48] << 4)
1981 | (mask_p[47] << 2) | (mask_p[46] << 0);
1982 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1983 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1984 }
1985
1986 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1987 {
1988 int bb_spur = AR_NO_SPUR;
1989 int bin, cur_bin;
1990 int spur_freq_sd;
1991 int spur_delta_phase;
1992 int denominator;
1993 int upper, lower, cur_vit_mask;
1994 int tmp, new;
1995 int i;
1996 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1997 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1998 };
1999 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2000 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2001 };
2002 int inc[4] = { 0, 100, 0, 0 };
2003
2004 int8_t mask_m[123];
2005 int8_t mask_p[123];
2006 int8_t mask_amt;
2007 int tmp_mask;
2008 int cur_bb_spur;
2009 bool is2GHz = IS_CHAN_2GHZ(chan);
2010
2011 memset(&mask_m, 0, sizeof(int8_t) * 123);
2012 memset(&mask_p, 0, sizeof(int8_t) * 123);
2013
2014 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2015 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2016 if (AR_NO_SPUR == cur_bb_spur)
2017 break;
2018 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2019 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2020 bb_spur = cur_bb_spur;
2021 break;
2022 }
2023 }
2024
2025 if (AR_NO_SPUR == bb_spur)
2026 return;
2027
2028 bin = bb_spur * 32;
2029
2030 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2031 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2032 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2033 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2034 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2035
2036 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2037
2038 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2039 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2040 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2041 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2042 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2043 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2044
2045 spur_delta_phase = ((bb_spur * 524288) / 100) &
2046 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2047
2048 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2049 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2050
2051 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2052 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2053 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2054 REG_WRITE(ah, AR_PHY_TIMING11, new);
2055
2056 cur_bin = -6000;
2057 upper = bin + 100;
2058 lower = bin - 100;
2059
2060 for (i = 0; i < 4; i++) {
2061 int pilot_mask = 0;
2062 int chan_mask = 0;
2063 int bp = 0;
2064 for (bp = 0; bp < 30; bp++) {
2065 if ((cur_bin > lower) && (cur_bin < upper)) {
2066 pilot_mask = pilot_mask | 0x1 << bp;
2067 chan_mask = chan_mask | 0x1 << bp;
2068 }
2069 cur_bin += 100;
2070 }
2071 cur_bin += inc[i];
2072 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2073 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2074 }
2075
2076 cur_vit_mask = 6100;
2077 upper = bin + 120;
2078 lower = bin - 120;
2079
2080 for (i = 0; i < 123; i++) {
2081 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2082
2083 /* workaround for gcc bug #37014 */
2084 volatile int tmp_v = abs(cur_vit_mask - bin);
2085
2086 if (tmp_v < 75)
2087 mask_amt = 1;
2088 else
2089 mask_amt = 0;
2090 if (cur_vit_mask < 0)
2091 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2092 else
2093 mask_p[cur_vit_mask / 100] = mask_amt;
2094 }
2095 cur_vit_mask -= 100;
2096 }
2097
2098 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2099 | (mask_m[48] << 26) | (mask_m[49] << 24)
2100 | (mask_m[50] << 22) | (mask_m[51] << 20)
2101 | (mask_m[52] << 18) | (mask_m[53] << 16)
2102 | (mask_m[54] << 14) | (mask_m[55] << 12)
2103 | (mask_m[56] << 10) | (mask_m[57] << 8)
2104 | (mask_m[58] << 6) | (mask_m[59] << 4)
2105 | (mask_m[60] << 2) | (mask_m[61] << 0);
2106 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2107 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2108
2109 tmp_mask = (mask_m[31] << 28)
2110 | (mask_m[32] << 26) | (mask_m[33] << 24)
2111 | (mask_m[34] << 22) | (mask_m[35] << 20)
2112 | (mask_m[36] << 18) | (mask_m[37] << 16)
2113 | (mask_m[48] << 14) | (mask_m[39] << 12)
2114 | (mask_m[40] << 10) | (mask_m[41] << 8)
2115 | (mask_m[42] << 6) | (mask_m[43] << 4)
2116 | (mask_m[44] << 2) | (mask_m[45] << 0);
2117 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2118 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2119
2120 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2121 | (mask_m[18] << 26) | (mask_m[18] << 24)
2122 | (mask_m[20] << 22) | (mask_m[20] << 20)
2123 | (mask_m[22] << 18) | (mask_m[22] << 16)
2124 | (mask_m[24] << 14) | (mask_m[24] << 12)
2125 | (mask_m[25] << 10) | (mask_m[26] << 8)
2126 | (mask_m[27] << 6) | (mask_m[28] << 4)
2127 | (mask_m[29] << 2) | (mask_m[30] << 0);
2128 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2129 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2130
2131 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2132 | (mask_m[2] << 26) | (mask_m[3] << 24)
2133 | (mask_m[4] << 22) | (mask_m[5] << 20)
2134 | (mask_m[6] << 18) | (mask_m[7] << 16)
2135 | (mask_m[8] << 14) | (mask_m[9] << 12)
2136 | (mask_m[10] << 10) | (mask_m[11] << 8)
2137 | (mask_m[12] << 6) | (mask_m[13] << 4)
2138 | (mask_m[14] << 2) | (mask_m[15] << 0);
2139 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2140 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2141
2142 tmp_mask = (mask_p[15] << 28)
2143 | (mask_p[14] << 26) | (mask_p[13] << 24)
2144 | (mask_p[12] << 22) | (mask_p[11] << 20)
2145 | (mask_p[10] << 18) | (mask_p[9] << 16)
2146 | (mask_p[8] << 14) | (mask_p[7] << 12)
2147 | (mask_p[6] << 10) | (mask_p[5] << 8)
2148 | (mask_p[4] << 6) | (mask_p[3] << 4)
2149 | (mask_p[2] << 2) | (mask_p[1] << 0);
2150 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2151 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2152
2153 tmp_mask = (mask_p[30] << 28)
2154 | (mask_p[29] << 26) | (mask_p[28] << 24)
2155 | (mask_p[27] << 22) | (mask_p[26] << 20)
2156 | (mask_p[25] << 18) | (mask_p[24] << 16)
2157 | (mask_p[23] << 14) | (mask_p[22] << 12)
2158 | (mask_p[21] << 10) | (mask_p[20] << 8)
2159 | (mask_p[19] << 6) | (mask_p[18] << 4)
2160 | (mask_p[17] << 2) | (mask_p[16] << 0);
2161 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2162 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2163
2164 tmp_mask = (mask_p[45] << 28)
2165 | (mask_p[44] << 26) | (mask_p[43] << 24)
2166 | (mask_p[42] << 22) | (mask_p[41] << 20)
2167 | (mask_p[40] << 18) | (mask_p[39] << 16)
2168 | (mask_p[38] << 14) | (mask_p[37] << 12)
2169 | (mask_p[36] << 10) | (mask_p[35] << 8)
2170 | (mask_p[34] << 6) | (mask_p[33] << 4)
2171 | (mask_p[32] << 2) | (mask_p[31] << 0);
2172 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2173 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2174
2175 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2176 | (mask_p[59] << 26) | (mask_p[58] << 24)
2177 | (mask_p[57] << 22) | (mask_p[56] << 20)
2178 | (mask_p[55] << 18) | (mask_p[54] << 16)
2179 | (mask_p[53] << 14) | (mask_p[52] << 12)
2180 | (mask_p[51] << 10) | (mask_p[50] << 8)
2181 | (mask_p[49] << 6) | (mask_p[48] << 4)
2182 | (mask_p[47] << 2) | (mask_p[46] << 0);
2183 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2184 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2185 }
2186
2187 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2188 bool bChannelChange)
2189 {
2190 u32 saveLedState;
2191 struct ath_softc *sc = ah->ah_sc;
2192 struct ath9k_channel *curchan = ah->curchan;
2193 u32 saveDefAntenna;
2194 u32 macStaId1;
2195 int i, rx_chainmask, r;
2196
2197 ah->extprotspacing = sc->ht_extprotspacing;
2198 ah->txchainmask = sc->tx_chainmask;
2199 ah->rxchainmask = sc->rx_chainmask;
2200
2201 if (AR_SREV_9285(ah)) {
2202 ah->txchainmask &= 0x1;
2203 ah->rxchainmask &= 0x1;
2204 } else if (AR_SREV_9280(ah)) {
2205 ah->txchainmask &= 0x3;
2206 ah->rxchainmask &= 0x3;
2207 }
2208
2209 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2210 return -EIO;
2211
2212 if (curchan)
2213 ath9k_hw_getnf(ah, curchan);
2214
2215 if (bChannelChange &&
2216 (ah->chip_fullsleep != true) &&
2217 (ah->curchan != NULL) &&
2218 (chan->channel != ah->curchan->channel) &&
2219 ((chan->channelFlags & CHANNEL_ALL) ==
2220 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2221 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2222 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2223
2224 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2225 ath9k_hw_loadnf(ah, ah->curchan);
2226 ath9k_hw_start_nfcal(ah);
2227 return 0;
2228 }
2229 }
2230
2231 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2232 if (saveDefAntenna == 0)
2233 saveDefAntenna = 1;
2234
2235 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2236
2237 saveLedState = REG_READ(ah, AR_CFG_LED) &
2238 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2239 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2240
2241 ath9k_hw_mark_phy_inactive(ah);
2242
2243 if (!ath9k_hw_chip_reset(ah, chan)) {
2244 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2245 return -EINVAL;
2246 }
2247
2248 if (AR_SREV_9280_10_OR_LATER(ah))
2249 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2250
2251 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2252 if (r)
2253 return r;
2254
2255 /* Setup MFP options for CCMP */
2256 if (AR_SREV_9280_20_OR_LATER(ah)) {
2257 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2258 * frames when constructing CCMP AAD. */
2259 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2260 0xc7ff);
2261 ah->sw_mgmt_crypto = false;
2262 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2263 /* Disable hardware crypto for management frames */
2264 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2265 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2266 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2267 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2268 ah->sw_mgmt_crypto = true;
2269 } else
2270 ah->sw_mgmt_crypto = true;
2271
2272 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2273 ath9k_hw_set_delta_slope(ah, chan);
2274
2275 if (AR_SREV_9280_10_OR_LATER(ah))
2276 ath9k_hw_9280_spur_mitigate(ah, chan);
2277 else
2278 ath9k_hw_spur_mitigate(ah, chan);
2279
2280 if (!ah->eep_ops->set_board_values(ah, chan)) {
2281 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2282 "error setting board options\n");
2283 return -EIO;
2284 }
2285
2286 ath9k_hw_decrease_chain_power(ah, chan);
2287
2288 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2289 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2290 | macStaId1
2291 | AR_STA_ID1_RTS_USE_DEF
2292 | (ah->config.
2293 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2294 | ah->sta_id1_defaults);
2295 ath9k_hw_set_operating_mode(ah, ah->opmode);
2296
2297 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2298 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2299
2300 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2301
2302 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2303 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2304 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2305
2306 REG_WRITE(ah, AR_ISR, ~0);
2307
2308 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2309
2310 if (AR_SREV_9280_10_OR_LATER(ah)) {
2311 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2312 return -EIO;
2313 } else {
2314 if (!(ath9k_hw_set_channel(ah, chan)))
2315 return -EIO;
2316 }
2317
2318 for (i = 0; i < AR_NUM_DCU; i++)
2319 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2320
2321 ah->intr_txqs = 0;
2322 for (i = 0; i < ah->caps.total_queues; i++)
2323 ath9k_hw_resettxqueue(ah, i);
2324
2325 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2326 ath9k_hw_init_qos(ah);
2327
2328 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2329 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2330 ath9k_enable_rfkill(ah);
2331 #endif
2332 ath9k_hw_init_user_settings(ah);
2333
2334 REG_WRITE(ah, AR_STA_ID1,
2335 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2336
2337 ath9k_hw_set_dma(ah);
2338
2339 REG_WRITE(ah, AR_OBS, 8);
2340
2341 if (ah->intr_mitigation) {
2342
2343 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2344 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2345 }
2346
2347 ath9k_hw_init_bb(ah, chan);
2348
2349 if (!ath9k_hw_init_cal(ah, chan))
2350 return -EIO;;
2351
2352 rx_chainmask = ah->rxchainmask;
2353 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2354 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2355 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2356 }
2357
2358 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2359
2360 if (AR_SREV_9100(ah)) {
2361 u32 mask;
2362 mask = REG_READ(ah, AR_CFG);
2363 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2364 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2365 "CFG Byte Swap Set 0x%x\n", mask);
2366 } else {
2367 mask =
2368 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2369 REG_WRITE(ah, AR_CFG, mask);
2370 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2371 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2372 }
2373 } else {
2374 #ifdef __BIG_ENDIAN
2375 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2376 #endif
2377 }
2378
2379 return 0;
2380 }
2381
2382 /************************/
2383 /* Key Cache Management */
2384 /************************/
2385
2386 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2387 {
2388 u32 keyType;
2389
2390 if (entry >= ah->caps.keycache_size) {
2391 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2392 "entry %u out of range\n", entry);
2393 return false;
2394 }
2395
2396 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2397
2398 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2399 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2400 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2401 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2402 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2403 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2404 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2405 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2406
2407 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2408 u16 micentry = entry + 64;
2409
2410 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2411 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2412 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2413 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2414
2415 }
2416
2417 if (ah->curchan == NULL)
2418 return true;
2419
2420 return true;
2421 }
2422
2423 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2424 {
2425 u32 macHi, macLo;
2426
2427 if (entry >= ah->caps.keycache_size) {
2428 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2429 "entry %u out of range\n", entry);
2430 return false;
2431 }
2432
2433 if (mac != NULL) {
2434 macHi = (mac[5] << 8) | mac[4];
2435 macLo = (mac[3] << 24) |
2436 (mac[2] << 16) |
2437 (mac[1] << 8) |
2438 mac[0];
2439 macLo >>= 1;
2440 macLo |= (macHi & 1) << 31;
2441 macHi >>= 1;
2442 } else {
2443 macLo = macHi = 0;
2444 }
2445 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2446 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2447
2448 return true;
2449 }
2450
2451 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2452 const struct ath9k_keyval *k,
2453 const u8 *mac)
2454 {
2455 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2456 u32 key0, key1, key2, key3, key4;
2457 u32 keyType;
2458
2459 if (entry >= pCap->keycache_size) {
2460 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2461 "entry %u out of range\n", entry);
2462 return false;
2463 }
2464
2465 switch (k->kv_type) {
2466 case ATH9K_CIPHER_AES_OCB:
2467 keyType = AR_KEYTABLE_TYPE_AES;
2468 break;
2469 case ATH9K_CIPHER_AES_CCM:
2470 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2471 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2472 "AES-CCM not supported by mac rev 0x%x\n",
2473 ah->hw_version.macRev);
2474 return false;
2475 }
2476 keyType = AR_KEYTABLE_TYPE_CCM;
2477 break;
2478 case ATH9K_CIPHER_TKIP:
2479 keyType = AR_KEYTABLE_TYPE_TKIP;
2480 if (ATH9K_IS_MIC_ENABLED(ah)
2481 && entry + 64 >= pCap->keycache_size) {
2482 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2483 "entry %u inappropriate for TKIP\n", entry);
2484 return false;
2485 }
2486 break;
2487 case ATH9K_CIPHER_WEP:
2488 if (k->kv_len < LEN_WEP40) {
2489 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2490 "WEP key length %u too small\n", k->kv_len);
2491 return false;
2492 }
2493 if (k->kv_len <= LEN_WEP40)
2494 keyType = AR_KEYTABLE_TYPE_40;
2495 else if (k->kv_len <= LEN_WEP104)
2496 keyType = AR_KEYTABLE_TYPE_104;
2497 else
2498 keyType = AR_KEYTABLE_TYPE_128;
2499 break;
2500 case ATH9K_CIPHER_CLR:
2501 keyType = AR_KEYTABLE_TYPE_CLR;
2502 break;
2503 default:
2504 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2505 "cipher %u not supported\n", k->kv_type);
2506 return false;
2507 }
2508
2509 key0 = get_unaligned_le32(k->kv_val + 0);
2510 key1 = get_unaligned_le16(k->kv_val + 4);
2511 key2 = get_unaligned_le32(k->kv_val + 6);
2512 key3 = get_unaligned_le16(k->kv_val + 10);
2513 key4 = get_unaligned_le32(k->kv_val + 12);
2514 if (k->kv_len <= LEN_WEP104)
2515 key4 &= 0xff;
2516
2517 /*
2518 * Note: Key cache registers access special memory area that requires
2519 * two 32-bit writes to actually update the values in the internal
2520 * memory. Consequently, the exact order and pairs used here must be
2521 * maintained.
2522 */
2523
2524 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2525 u16 micentry = entry + 64;
2526
2527 /*
2528 * Write inverted key[47:0] first to avoid Michael MIC errors
2529 * on frames that could be sent or received at the same time.
2530 * The correct key will be written in the end once everything
2531 * else is ready.
2532 */
2533 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2534 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2535
2536 /* Write key[95:48] */
2537 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2538 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2539
2540 /* Write key[127:96] and key type */
2541 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2542 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2543
2544 /* Write MAC address for the entry */
2545 (void) ath9k_hw_keysetmac(ah, entry, mac);
2546
2547 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2548 /*
2549 * TKIP uses two key cache entries:
2550 * Michael MIC TX/RX keys in the same key cache entry
2551 * (idx = main index + 64):
2552 * key0 [31:0] = RX key [31:0]
2553 * key1 [15:0] = TX key [31:16]
2554 * key1 [31:16] = reserved
2555 * key2 [31:0] = RX key [63:32]
2556 * key3 [15:0] = TX key [15:0]
2557 * key3 [31:16] = reserved
2558 * key4 [31:0] = TX key [63:32]
2559 */
2560 u32 mic0, mic1, mic2, mic3, mic4;
2561
2562 mic0 = get_unaligned_le32(k->kv_mic + 0);
2563 mic2 = get_unaligned_le32(k->kv_mic + 4);
2564 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2565 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2566 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2567
2568 /* Write RX[31:0] and TX[31:16] */
2569 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2570 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2571
2572 /* Write RX[63:32] and TX[15:0] */
2573 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2574 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2575
2576 /* Write TX[63:32] and keyType(reserved) */
2577 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2578 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2579 AR_KEYTABLE_TYPE_CLR);
2580
2581 } else {
2582 /*
2583 * TKIP uses four key cache entries (two for group
2584 * keys):
2585 * Michael MIC TX/RX keys are in different key cache
2586 * entries (idx = main index + 64 for TX and
2587 * main index + 32 + 96 for RX):
2588 * key0 [31:0] = TX/RX MIC key [31:0]
2589 * key1 [31:0] = reserved
2590 * key2 [31:0] = TX/RX MIC key [63:32]
2591 * key3 [31:0] = reserved
2592 * key4 [31:0] = reserved
2593 *
2594 * Upper layer code will call this function separately
2595 * for TX and RX keys when these registers offsets are
2596 * used.
2597 */
2598 u32 mic0, mic2;
2599
2600 mic0 = get_unaligned_le32(k->kv_mic + 0);
2601 mic2 = get_unaligned_le32(k->kv_mic + 4);
2602
2603 /* Write MIC key[31:0] */
2604 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2605 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2606
2607 /* Write MIC key[63:32] */
2608 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2609 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2610
2611 /* Write TX[63:32] and keyType(reserved) */
2612 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2613 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2614 AR_KEYTABLE_TYPE_CLR);
2615 }
2616
2617 /* MAC address registers are reserved for the MIC entry */
2618 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2619 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2620
2621 /*
2622 * Write the correct (un-inverted) key[47:0] last to enable
2623 * TKIP now that all other registers are set with correct
2624 * values.
2625 */
2626 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2627 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2628 } else {
2629 /* Write key[47:0] */
2630 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2631 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2632
2633 /* Write key[95:48] */
2634 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2635 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2636
2637 /* Write key[127:96] and key type */
2638 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2639 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2640
2641 /* Write MAC address for the entry */
2642 (void) ath9k_hw_keysetmac(ah, entry, mac);
2643 }
2644
2645 return true;
2646 }
2647
2648 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2649 {
2650 if (entry < ah->caps.keycache_size) {
2651 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2652 if (val & AR_KEYTABLE_VALID)
2653 return true;
2654 }
2655 return false;
2656 }
2657
2658 /******************************/
2659 /* Power Management (Chipset) */
2660 /******************************/
2661
2662 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2663 {
2664 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2665 if (setChip) {
2666 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2667 AR_RTC_FORCE_WAKE_EN);
2668 if (!AR_SREV_9100(ah))
2669 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2670
2671 REG_CLR_BIT(ah, (AR_RTC_RESET),
2672 AR_RTC_RESET_EN);
2673 }
2674 }
2675
2676 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2677 {
2678 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2679 if (setChip) {
2680 struct ath9k_hw_capabilities *pCap = &ah->caps;
2681
2682 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2683 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2684 AR_RTC_FORCE_WAKE_ON_INT);
2685 } else {
2686 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2687 AR_RTC_FORCE_WAKE_EN);
2688 }
2689 }
2690 }
2691
2692 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2693 {
2694 u32 val;
2695 int i;
2696
2697 if (setChip) {
2698 if ((REG_READ(ah, AR_RTC_STATUS) &
2699 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2700 if (ath9k_hw_set_reset_reg(ah,
2701 ATH9K_RESET_POWER_ON) != true) {
2702 return false;
2703 }
2704 }
2705 if (AR_SREV_9100(ah))
2706 REG_SET_BIT(ah, AR_RTC_RESET,
2707 AR_RTC_RESET_EN);
2708
2709 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2710 AR_RTC_FORCE_WAKE_EN);
2711 udelay(50);
2712
2713 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2714 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2715 if (val == AR_RTC_STATUS_ON)
2716 break;
2717 udelay(50);
2718 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2719 AR_RTC_FORCE_WAKE_EN);
2720 }
2721 if (i == 0) {
2722 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2723 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2724 return false;
2725 }
2726 }
2727
2728 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2729
2730 return true;
2731 }
2732
2733 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2734 {
2735 int status = true, setChip = true;
2736 static const char *modes[] = {
2737 "AWAKE",
2738 "FULL-SLEEP",
2739 "NETWORK SLEEP",
2740 "UNDEFINED"
2741 };
2742
2743 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2744 modes[ah->power_mode], modes[mode],
2745 setChip ? "set chip " : "");
2746
2747 switch (mode) {
2748 case ATH9K_PM_AWAKE:
2749 status = ath9k_hw_set_power_awake(ah, setChip);
2750 break;
2751 case ATH9K_PM_FULL_SLEEP:
2752 ath9k_set_power_sleep(ah, setChip);
2753 ah->chip_fullsleep = true;
2754 break;
2755 case ATH9K_PM_NETWORK_SLEEP:
2756 ath9k_set_power_network_sleep(ah, setChip);
2757 break;
2758 default:
2759 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2760 "Unknown power mode %u\n", mode);
2761 return false;
2762 }
2763 ah->power_mode = mode;
2764
2765 return status;
2766 }
2767
2768 /*
2769 * Helper for ASPM support.
2770 *
2771 * Disable PLL when in L0s as well as receiver clock when in L1.
2772 * This power saving option must be enabled through the SerDes.
2773 *
2774 * Programming the SerDes must go through the same 288 bit serial shift
2775 * register as the other analog registers. Hence the 9 writes.
2776 */
2777 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2778 {
2779 u8 i;
2780
2781 if (ah->is_pciexpress != true)
2782 return;
2783
2784 /* Do not touch SerDes registers */
2785 if (ah->config.pcie_powersave_enable == 2)
2786 return;
2787
2788 /* Nothing to do on restore for 11N */
2789 if (restore)
2790 return;
2791
2792 if (AR_SREV_9280_20_OR_LATER(ah)) {
2793 /*
2794 * AR9280 2.0 or later chips use SerDes values from the
2795 * initvals.h initialized depending on chipset during
2796 * ath9k_hw_do_attach()
2797 */
2798 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2799 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2800 INI_RA(&ah->iniPcieSerdes, i, 1));
2801 }
2802 } else if (AR_SREV_9280(ah) &&
2803 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2804 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2805 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2806
2807 /* RX shut off when elecidle is asserted */
2808 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2809 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2810 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2811
2812 /* Shut off CLKREQ active in L1 */
2813 if (ah->config.pcie_clock_req)
2814 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2815 else
2816 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2817
2818 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2819 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2820 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2821
2822 /* Load the new settings */
2823 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2824
2825 } else {
2826 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2827 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2828
2829 /* RX shut off when elecidle is asserted */
2830 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2831 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2832 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2833
2834 /*
2835 * Ignore ah->ah_config.pcie_clock_req setting for
2836 * pre-AR9280 11n
2837 */
2838 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2839
2840 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2841 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2842 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2843
2844 /* Load the new settings */
2845 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2846 }
2847
2848 udelay(1000);
2849
2850 /* set bit 19 to allow forcing of pcie core into L1 state */
2851 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2852
2853 /* Several PCIe massages to ensure proper behaviour */
2854 if (ah->config.pcie_waen) {
2855 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2856 } else {
2857 if (AR_SREV_9285(ah))
2858 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2859 /*
2860 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2861 * otherwise card may disappear.
2862 */
2863 else if (AR_SREV_9280(ah))
2864 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2865 else
2866 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2867 }
2868 }
2869
2870 /**********************/
2871 /* Interrupt Handling */
2872 /**********************/
2873
2874 bool ath9k_hw_intrpend(struct ath_hw *ah)
2875 {
2876 u32 host_isr;
2877
2878 if (AR_SREV_9100(ah))
2879 return true;
2880
2881 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2882 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2883 return true;
2884
2885 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2886 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2887 && (host_isr != AR_INTR_SPURIOUS))
2888 return true;
2889
2890 return false;
2891 }
2892
2893 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2894 {
2895 u32 isr = 0;
2896 u32 mask2 = 0;
2897 struct ath9k_hw_capabilities *pCap = &ah->caps;
2898 u32 sync_cause = 0;
2899 bool fatal_int = false;
2900
2901 if (!AR_SREV_9100(ah)) {
2902 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2903 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2904 == AR_RTC_STATUS_ON) {
2905 isr = REG_READ(ah, AR_ISR);
2906 }
2907 }
2908
2909 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2910 AR_INTR_SYNC_DEFAULT;
2911
2912 *masked = 0;
2913
2914 if (!isr && !sync_cause)
2915 return false;
2916 } else {
2917 *masked = 0;
2918 isr = REG_READ(ah, AR_ISR);
2919 }
2920
2921 if (isr) {
2922 if (isr & AR_ISR_BCNMISC) {
2923 u32 isr2;
2924 isr2 = REG_READ(ah, AR_ISR_S2);
2925 if (isr2 & AR_ISR_S2_TIM)
2926 mask2 |= ATH9K_INT_TIM;
2927 if (isr2 & AR_ISR_S2_DTIM)
2928 mask2 |= ATH9K_INT_DTIM;
2929 if (isr2 & AR_ISR_S2_DTIMSYNC)
2930 mask2 |= ATH9K_INT_DTIMSYNC;
2931 if (isr2 & (AR_ISR_S2_CABEND))
2932 mask2 |= ATH9K_INT_CABEND;
2933 if (isr2 & AR_ISR_S2_GTT)
2934 mask2 |= ATH9K_INT_GTT;
2935 if (isr2 & AR_ISR_S2_CST)
2936 mask2 |= ATH9K_INT_CST;
2937 if (isr2 & AR_ISR_S2_TSFOOR)
2938 mask2 |= ATH9K_INT_TSFOOR;
2939 }
2940
2941 isr = REG_READ(ah, AR_ISR_RAC);
2942 if (isr == 0xffffffff) {
2943 *masked = 0;
2944 return false;
2945 }
2946
2947 *masked = isr & ATH9K_INT_COMMON;
2948
2949 if (ah->intr_mitigation) {
2950 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2951 *masked |= ATH9K_INT_RX;
2952 }
2953
2954 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2955 *masked |= ATH9K_INT_RX;
2956 if (isr &
2957 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2958 AR_ISR_TXEOL)) {
2959 u32 s0_s, s1_s;
2960
2961 *masked |= ATH9K_INT_TX;
2962
2963 s0_s = REG_READ(ah, AR_ISR_S0_S);
2964 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2965 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2966
2967 s1_s = REG_READ(ah, AR_ISR_S1_S);
2968 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2969 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2970 }
2971
2972 if (isr & AR_ISR_RXORN) {
2973 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2974 "receive FIFO overrun interrupt\n");
2975 }
2976
2977 if (!AR_SREV_9100(ah)) {
2978 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2979 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2980 if (isr5 & AR_ISR_S5_TIM_TIMER)
2981 *masked |= ATH9K_INT_TIM_TIMER;
2982 }
2983 }
2984
2985 *masked |= mask2;
2986 }
2987
2988 if (AR_SREV_9100(ah))
2989 return true;
2990
2991 if (sync_cause) {
2992 fatal_int =
2993 (sync_cause &
2994 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2995 ? true : false;
2996
2997 if (fatal_int) {
2998 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2999 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3000 "received PCI FATAL interrupt\n");
3001 }
3002 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3003 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3004 "received PCI PERR interrupt\n");
3005 }
3006 }
3007 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3008 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3009 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3010 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3011 REG_WRITE(ah, AR_RC, 0);
3012 *masked |= ATH9K_INT_FATAL;
3013 }
3014 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3015 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3016 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3017 }
3018
3019 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3020 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3021 }
3022
3023 return true;
3024 }
3025
3026 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3027 {
3028 return ah->mask_reg;
3029 }
3030
3031 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3032 {
3033 u32 omask = ah->mask_reg;
3034 u32 mask, mask2;
3035 struct ath9k_hw_capabilities *pCap = &ah->caps;
3036
3037 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3038
3039 if (omask & ATH9K_INT_GLOBAL) {
3040 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3041 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3042 (void) REG_READ(ah, AR_IER);
3043 if (!AR_SREV_9100(ah)) {
3044 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3045 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3046
3047 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3048 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3049 }
3050 }
3051
3052 mask = ints & ATH9K_INT_COMMON;
3053 mask2 = 0;
3054
3055 if (ints & ATH9K_INT_TX) {
3056 if (ah->txok_interrupt_mask)
3057 mask |= AR_IMR_TXOK;
3058 if (ah->txdesc_interrupt_mask)
3059 mask |= AR_IMR_TXDESC;
3060 if (ah->txerr_interrupt_mask)
3061 mask |= AR_IMR_TXERR;
3062 if (ah->txeol_interrupt_mask)
3063 mask |= AR_IMR_TXEOL;
3064 }
3065 if (ints & ATH9K_INT_RX) {
3066 mask |= AR_IMR_RXERR;
3067 if (ah->intr_mitigation)
3068 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3069 else
3070 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3071 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3072 mask |= AR_IMR_GENTMR;
3073 }
3074
3075 if (ints & (ATH9K_INT_BMISC)) {
3076 mask |= AR_IMR_BCNMISC;
3077 if (ints & ATH9K_INT_TIM)
3078 mask2 |= AR_IMR_S2_TIM;
3079 if (ints & ATH9K_INT_DTIM)
3080 mask2 |= AR_IMR_S2_DTIM;
3081 if (ints & ATH9K_INT_DTIMSYNC)
3082 mask2 |= AR_IMR_S2_DTIMSYNC;
3083 if (ints & ATH9K_INT_CABEND)
3084 mask2 |= AR_IMR_S2_CABEND;
3085 if (ints & ATH9K_INT_TSFOOR)
3086 mask2 |= AR_IMR_S2_TSFOOR;
3087 }
3088
3089 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3090 mask |= AR_IMR_BCNMISC;
3091 if (ints & ATH9K_INT_GTT)
3092 mask2 |= AR_IMR_S2_GTT;
3093 if (ints & ATH9K_INT_CST)
3094 mask2 |= AR_IMR_S2_CST;
3095 }
3096
3097 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3098 REG_WRITE(ah, AR_IMR, mask);
3099 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3100 AR_IMR_S2_DTIM |
3101 AR_IMR_S2_DTIMSYNC |
3102 AR_IMR_S2_CABEND |
3103 AR_IMR_S2_CABTO |
3104 AR_IMR_S2_TSFOOR |
3105 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3106 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3107 ah->mask_reg = ints;
3108
3109 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3110 if (ints & ATH9K_INT_TIM_TIMER)
3111 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3112 else
3113 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3114 }
3115
3116 if (ints & ATH9K_INT_GLOBAL) {
3117 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3118 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3119 if (!AR_SREV_9100(ah)) {
3120 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3121 AR_INTR_MAC_IRQ);
3122 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3123
3124
3125 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3126 AR_INTR_SYNC_DEFAULT);
3127 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3128 AR_INTR_SYNC_DEFAULT);
3129 }
3130 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3131 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3132 }
3133
3134 return omask;
3135 }
3136
3137 /*******************/
3138 /* Beacon Handling */
3139 /*******************/
3140
3141 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3142 {
3143 int flags = 0;
3144
3145 ah->beacon_interval = beacon_period;
3146
3147 switch (ah->opmode) {
3148 case NL80211_IFTYPE_STATION:
3149 case NL80211_IFTYPE_MONITOR:
3150 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3151 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3152 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3153 flags |= AR_TBTT_TIMER_EN;
3154 break;
3155 case NL80211_IFTYPE_ADHOC:
3156 REG_SET_BIT(ah, AR_TXCFG,
3157 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3158 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3159 TU_TO_USEC(next_beacon +
3160 (ah->atim_window ? ah->
3161 atim_window : 1)));
3162 flags |= AR_NDP_TIMER_EN;
3163 case NL80211_IFTYPE_AP:
3164 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3165 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3166 TU_TO_USEC(next_beacon -
3167 ah->config.
3168 dma_beacon_response_time));
3169 REG_WRITE(ah, AR_NEXT_SWBA,
3170 TU_TO_USEC(next_beacon -
3171 ah->config.
3172 sw_beacon_response_time));
3173 flags |=
3174 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3175 break;
3176 default:
3177 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3178 "%s: unsupported opmode: %d\n",
3179 __func__, ah->opmode);
3180 return;
3181 break;
3182 }
3183
3184 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3185 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3186 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3187 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3188
3189 beacon_period &= ~ATH9K_BEACON_ENA;
3190 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3191 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3192 ath9k_hw_reset_tsf(ah);
3193 }
3194
3195 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3196 }
3197
3198 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3199 const struct ath9k_beacon_state *bs)
3200 {
3201 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3202 struct ath9k_hw_capabilities *pCap = &ah->caps;
3203
3204 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3205
3206 REG_WRITE(ah, AR_BEACON_PERIOD,
3207 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3208 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3209 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3210
3211 REG_RMW_FIELD(ah, AR_RSSI_THR,
3212 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3213
3214 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3215
3216 if (bs->bs_sleepduration > beaconintval)
3217 beaconintval = bs->bs_sleepduration;
3218
3219 dtimperiod = bs->bs_dtimperiod;
3220 if (bs->bs_sleepduration > dtimperiod)
3221 dtimperiod = bs->bs_sleepduration;
3222
3223 if (beaconintval == dtimperiod)
3224 nextTbtt = bs->bs_nextdtim;
3225 else
3226 nextTbtt = bs->bs_nexttbtt;
3227
3228 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3229 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3230 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3231 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3232
3233 REG_WRITE(ah, AR_NEXT_DTIM,
3234 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3235 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3236
3237 REG_WRITE(ah, AR_SLEEP1,
3238 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3239 | AR_SLEEP1_ASSUME_DTIM);
3240
3241 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3242 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3243 else
3244 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3245
3246 REG_WRITE(ah, AR_SLEEP2,
3247 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3248
3249 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3250 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3251
3252 REG_SET_BIT(ah, AR_TIMER_MODE,
3253 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3254 AR_DTIM_TIMER_EN);
3255
3256 /* TSF Out of Range Threshold */
3257 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3258 }
3259
3260 /*******************/
3261 /* HW Capabilities */
3262 /*******************/
3263
3264 bool ath9k_hw_fill_cap_info(struct ath_hw *ah)
3265 {
3266 struct ath9k_hw_capabilities *pCap = &ah->caps;
3267 u16 capField = 0, eeval;
3268
3269 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3270 ah->regulatory.current_rd = eeval;
3271
3272 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3273 if (AR_SREV_9285_10_OR_LATER(ah))
3274 eeval |= AR9285_RDEXT_DEFAULT;
3275 ah->regulatory.current_rd_ext = eeval;
3276
3277 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3278
3279 if (ah->opmode != NL80211_IFTYPE_AP &&
3280 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3281 if (ah->regulatory.current_rd == 0x64 ||
3282 ah->regulatory.current_rd == 0x65)
3283 ah->regulatory.current_rd += 5;
3284 else if (ah->regulatory.current_rd == 0x41)
3285 ah->regulatory.current_rd = 0x43;
3286 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3287 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3288 }
3289
3290 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3291 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3292
3293 if (eeval & AR5416_OPFLAGS_11A) {
3294 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3295 if (ah->config.ht_enable) {
3296 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3297 set_bit(ATH9K_MODE_11NA_HT20,
3298 pCap->wireless_modes);
3299 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3300 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3301 pCap->wireless_modes);
3302 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3303 pCap->wireless_modes);
3304 }
3305 }
3306 }
3307
3308 if (eeval & AR5416_OPFLAGS_11G) {
3309 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3310 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3311 if (ah->config.ht_enable) {
3312 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3313 set_bit(ATH9K_MODE_11NG_HT20,
3314 pCap->wireless_modes);
3315 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3316 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3317 pCap->wireless_modes);
3318 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3319 pCap->wireless_modes);
3320 }
3321 }
3322 }
3323
3324 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3325 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3326 !(eeval & AR5416_OPFLAGS_11A))
3327 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3328 else
3329 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3330
3331 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3332 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3333
3334 pCap->low_2ghz_chan = 2312;
3335 pCap->high_2ghz_chan = 2732;
3336
3337 pCap->low_5ghz_chan = 4920;
3338 pCap->high_5ghz_chan = 6100;
3339
3340 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3341 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3342 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3343
3344 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3345 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3346 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3347
3348 pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3349
3350 if (ah->config.ht_enable)
3351 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3352 else
3353 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3354
3355 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3356 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3357 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3358 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3359
3360 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3361 pCap->total_queues =
3362 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3363 else
3364 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3365
3366 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3367 pCap->keycache_size =
3368 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3369 else
3370 pCap->keycache_size = AR_KEYTABLE_SIZE;
3371
3372 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3373 pCap->num_mr_retries = 4;
3374 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3375
3376 if (AR_SREV_9285_10_OR_LATER(ah))
3377 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3378 else if (AR_SREV_9280_10_OR_LATER(ah))
3379 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3380 else
3381 pCap->num_gpio_pins = AR_NUM_GPIO;
3382
3383 if (AR_SREV_9280_10_OR_LATER(ah)) {
3384 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3385 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3386 } else {
3387 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3388 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3389 }
3390
3391 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3392 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3393 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3394 } else {
3395 pCap->rts_aggr_limit = (8 * 1024);
3396 }
3397
3398 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3399
3400 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3401 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3402 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3403 ah->rfkill_gpio =
3404 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3405 ah->rfkill_polarity =
3406 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3407
3408 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3409 }
3410 #endif
3411
3412 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3413 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3414 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3415 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3416 (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3417 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3418 else
3419 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3420
3421 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3422 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3423 else
3424 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3425
3426 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3427 pCap->reg_cap =
3428 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3429 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3430 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3431 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3432 } else {
3433 pCap->reg_cap =
3434 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3435 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3436 }
3437
3438 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3439
3440 pCap->num_antcfg_5ghz =
3441 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3442 pCap->num_antcfg_2ghz =
3443 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3444
3445 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3446 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3447 ah->btactive_gpio = 6;
3448 ah->wlanactive_gpio = 5;
3449 }
3450
3451 return true;
3452 }
3453
3454 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3455 u32 capability, u32 *result)
3456 {
3457 switch (type) {
3458 case ATH9K_CAP_CIPHER:
3459 switch (capability) {
3460 case ATH9K_CIPHER_AES_CCM:
3461 case ATH9K_CIPHER_AES_OCB:
3462 case ATH9K_CIPHER_TKIP:
3463 case ATH9K_CIPHER_WEP:
3464 case ATH9K_CIPHER_MIC:
3465 case ATH9K_CIPHER_CLR:
3466 return true;
3467 default:
3468 return false;
3469 }
3470 case ATH9K_CAP_TKIP_MIC:
3471 switch (capability) {
3472 case 0:
3473 return true;
3474 case 1:
3475 return (ah->sta_id1_defaults &
3476 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3477 false;
3478 }
3479 case ATH9K_CAP_TKIP_SPLIT:
3480 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3481 false : true;
3482 case ATH9K_CAP_DIVERSITY:
3483 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3484 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3485 true : false;
3486 case ATH9K_CAP_MCAST_KEYSRCH:
3487 switch (capability) {
3488 case 0:
3489 return true;
3490 case 1:
3491 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3492 return false;
3493 } else {
3494 return (ah->sta_id1_defaults &
3495 AR_STA_ID1_MCAST_KSRCH) ? true :
3496 false;
3497 }
3498 }
3499 return false;
3500 case ATH9K_CAP_TXPOW:
3501 switch (capability) {
3502 case 0:
3503 return 0;
3504 case 1:
3505 *result = ah->regulatory.power_limit;
3506 return 0;
3507 case 2:
3508 *result = ah->regulatory.max_power_level;
3509 return 0;
3510 case 3:
3511 *result = ah->regulatory.tp_scale;
3512 return 0;
3513 }
3514 return false;
3515 case ATH9K_CAP_DS:
3516 return (AR_SREV_9280_20_OR_LATER(ah) &&
3517 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3518 ? false : true;
3519 default:
3520 return false;
3521 }
3522 }
3523
3524 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3525 u32 capability, u32 setting, int *status)
3526 {
3527 u32 v;
3528
3529 switch (type) {
3530 case ATH9K_CAP_TKIP_MIC:
3531 if (setting)
3532 ah->sta_id1_defaults |=
3533 AR_STA_ID1_CRPT_MIC_ENABLE;
3534 else
3535 ah->sta_id1_defaults &=
3536 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3537 return true;
3538 case ATH9K_CAP_DIVERSITY:
3539 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3540 if (setting)
3541 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3542 else
3543 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3544 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3545 return true;
3546 case ATH9K_CAP_MCAST_KEYSRCH:
3547 if (setting)
3548 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3549 else
3550 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3551 return true;
3552 default:
3553 return false;
3554 }
3555 }
3556
3557 /****************************/
3558 /* GPIO / RFKILL / Antennae */
3559 /****************************/
3560
3561 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3562 u32 gpio, u32 type)
3563 {
3564 int addr;
3565 u32 gpio_shift, tmp;
3566
3567 if (gpio > 11)
3568 addr = AR_GPIO_OUTPUT_MUX3;
3569 else if (gpio > 5)
3570 addr = AR_GPIO_OUTPUT_MUX2;
3571 else
3572 addr = AR_GPIO_OUTPUT_MUX1;
3573
3574 gpio_shift = (gpio % 6) * 5;
3575
3576 if (AR_SREV_9280_20_OR_LATER(ah)
3577 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3578 REG_RMW(ah, addr, (type << gpio_shift),
3579 (0x1f << gpio_shift));
3580 } else {
3581 tmp = REG_READ(ah, addr);
3582 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3583 tmp &= ~(0x1f << gpio_shift);
3584 tmp |= (type << gpio_shift);
3585 REG_WRITE(ah, addr, tmp);
3586 }
3587 }
3588
3589 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3590 {
3591 u32 gpio_shift;
3592
3593 ASSERT(gpio < ah->caps.num_gpio_pins);
3594
3595 gpio_shift = gpio << 1;
3596
3597 REG_RMW(ah,
3598 AR_GPIO_OE_OUT,
3599 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3600 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3601 }
3602
3603 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3604 {
3605 #define MS_REG_READ(x, y) \
3606 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3607
3608 if (gpio >= ah->caps.num_gpio_pins)
3609 return 0xffffffff;
3610
3611 if (AR_SREV_9285_10_OR_LATER(ah))
3612 return MS_REG_READ(AR9285, gpio) != 0;
3613 else if (AR_SREV_9280_10_OR_LATER(ah))
3614 return MS_REG_READ(AR928X, gpio) != 0;
3615 else
3616 return MS_REG_READ(AR, gpio) != 0;
3617 }
3618
3619 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3620 u32 ah_signal_type)
3621 {
3622 u32 gpio_shift;
3623
3624 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3625
3626 gpio_shift = 2 * gpio;
3627
3628 REG_RMW(ah,
3629 AR_GPIO_OE_OUT,
3630 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3631 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3632 }
3633
3634 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3635 {
3636 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3637 AR_GPIO_BIT(gpio));
3638 }
3639
3640 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3641 void ath9k_enable_rfkill(struct ath_hw *ah)
3642 {
3643 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3644 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3645
3646 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3647 AR_GPIO_INPUT_MUX2_RFSILENT);
3648
3649 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
3650 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3651 }
3652 #endif
3653
3654 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3655 {
3656 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3657 }
3658
3659 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3660 {
3661 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3662 }
3663
3664 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3665 enum ath9k_ant_setting settings,
3666 struct ath9k_channel *chan,
3667 u8 *tx_chainmask,
3668 u8 *rx_chainmask,
3669 u8 *antenna_cfgd)
3670 {
3671 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3672
3673 if (AR_SREV_9280(ah)) {
3674 if (!tx_chainmask_cfg) {
3675
3676 tx_chainmask_cfg = *tx_chainmask;
3677 rx_chainmask_cfg = *rx_chainmask;
3678 }
3679
3680 switch (settings) {
3681 case ATH9K_ANT_FIXED_A:
3682 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3683 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3684 *antenna_cfgd = true;
3685 break;
3686 case ATH9K_ANT_FIXED_B:
3687 if (ah->caps.tx_chainmask >
3688 ATH9K_ANTENNA1_CHAINMASK) {
3689 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3690 }
3691 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3692 *antenna_cfgd = true;
3693 break;
3694 case ATH9K_ANT_VARIABLE:
3695 *tx_chainmask = tx_chainmask_cfg;
3696 *rx_chainmask = rx_chainmask_cfg;
3697 *antenna_cfgd = true;
3698 break;
3699 default:
3700 break;
3701 }
3702 } else {
3703 ah->diversity_control = settings;
3704 }
3705
3706 return true;
3707 }
3708
3709 /*********************/
3710 /* General Operation */
3711 /*********************/
3712
3713 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3714 {
3715 u32 bits = REG_READ(ah, AR_RX_FILTER);
3716 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3717
3718 if (phybits & AR_PHY_ERR_RADAR)
3719 bits |= ATH9K_RX_FILTER_PHYRADAR;
3720 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3721 bits |= ATH9K_RX_FILTER_PHYERR;
3722
3723 return bits;
3724 }
3725
3726 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3727 {
3728 u32 phybits;
3729
3730 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3731 phybits = 0;
3732 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3733 phybits |= AR_PHY_ERR_RADAR;
3734 if (bits & ATH9K_RX_FILTER_PHYERR)
3735 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3736 REG_WRITE(ah, AR_PHY_ERR, phybits);
3737
3738 if (phybits)
3739 REG_WRITE(ah, AR_RXCFG,
3740 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3741 else
3742 REG_WRITE(ah, AR_RXCFG,
3743 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3744 }
3745
3746 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3747 {
3748 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3749 }
3750
3751 bool ath9k_hw_disable(struct ath_hw *ah)
3752 {
3753 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3754 return false;
3755
3756 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3757 }
3758
3759 bool ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3760 {
3761 struct ath9k_channel *chan = ah->curchan;
3762 struct ieee80211_channel *channel = chan->chan;
3763
3764 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3765
3766 if (ah->eep_ops->set_txpower(ah, chan,
3767 ath9k_regd_get_ctl(ah, chan),
3768 channel->max_antenna_gain * 2,
3769 channel->max_power * 2,
3770 min((u32) MAX_RATE_POWER,
3771 (u32) ah->regulatory.power_limit)) != 0)
3772 return false;
3773
3774 return true;
3775 }
3776
3777 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3778 {
3779 memcpy(ah->macaddr, mac, ETH_ALEN);
3780 }
3781
3782 void ath9k_hw_setopmode(struct ath_hw *ah)
3783 {
3784 ath9k_hw_set_operating_mode(ah, ah->opmode);
3785 }
3786
3787 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3788 {
3789 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3790 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3791 }
3792
3793 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3794 {
3795 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3796 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3797 }
3798
3799 void ath9k_hw_write_associd(struct ath_softc *sc)
3800 {
3801 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3802 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3803 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3804 }
3805
3806 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3807 {
3808 u64 tsf;
3809
3810 tsf = REG_READ(ah, AR_TSF_U32);
3811 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3812
3813 return tsf;
3814 }
3815
3816 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3817 {
3818 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3819 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3820 }
3821
3822 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3823 {
3824 int count;
3825
3826 count = 0;
3827 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3828 count++;
3829 if (count > 10) {
3830 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3831 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3832 break;
3833 }
3834 udelay(10);
3835 }
3836 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3837 }
3838
3839 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3840 {
3841 if (setting)
3842 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3843 else
3844 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3845
3846 return true;
3847 }
3848
3849 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3850 {
3851 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3852 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3853 ah->slottime = (u32) -1;
3854 return false;
3855 } else {
3856 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3857 ah->slottime = us;
3858 return true;
3859 }
3860 }
3861
3862 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3863 {
3864 u32 macmode;
3865
3866 if (mode == ATH9K_HT_MACMODE_2040 &&
3867 !ah->config.cwm_ignore_extcca)
3868 macmode = AR_2040_JOINED_RX_CLEAR;
3869 else
3870 macmode = 0;
3871
3872 REG_WRITE(ah, AR_2040_MODE, macmode);
3873 }
3874
3875 /***************************/
3876 /* Bluetooth Coexistence */
3877 /***************************/
3878
3879 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3880 {
3881 /* connect bt_active to baseband */
3882 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3883 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3884 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3885
3886 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3887 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3888
3889 /* Set input mux for bt_active to gpio pin */
3890 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3891 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3892 ah->btactive_gpio);
3893
3894 /* Configure the desired gpio port for input */
3895 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3896
3897 /* Configure the desired GPIO port for TX_FRAME output */
3898 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3899 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3900 }
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