2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
23 static int btcoex_enable
;
24 module_param(btcoex_enable
, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable
, "Enable Bluetooth coexistence support");
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
31 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
32 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
33 enum ath9k_ht_macmode macmode
);
34 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
35 struct ar5416_eeprom_def
*pEepData
,
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
38 static void ath9k_hw_spur_mitigate(struct ath_hw
*ah
, struct ath9k_channel
*chan
);
40 /********************/
41 /* Helper Functions */
42 /********************/
44 static u32
ath9k_hw_mac_usec(struct ath_hw
*ah
, u32 clks
)
46 struct ieee80211_conf
*conf
= &ah
->ah_sc
->hw
->conf
;
48 if (!ah
->curchan
) /* should really check for CCK instead */
49 return clks
/ ATH9K_CLOCK_RATE_CCK
;
50 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
51 return clks
/ ATH9K_CLOCK_RATE_2GHZ_OFDM
;
53 return clks
/ ATH9K_CLOCK_RATE_5GHZ_OFDM
;
56 static u32
ath9k_hw_mac_to_usec(struct ath_hw
*ah
, u32 clks
)
58 struct ieee80211_conf
*conf
= &ah
->ah_sc
->hw
->conf
;
60 if (conf_is_ht40(conf
))
61 return ath9k_hw_mac_usec(ah
, clks
) / 2;
63 return ath9k_hw_mac_usec(ah
, clks
);
66 static u32
ath9k_hw_mac_clks(struct ath_hw
*ah
, u32 usecs
)
68 struct ieee80211_conf
*conf
= &ah
->ah_sc
->hw
->conf
;
70 if (!ah
->curchan
) /* should really check for CCK instead */
71 return usecs
*ATH9K_CLOCK_RATE_CCK
;
72 if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
73 return usecs
*ATH9K_CLOCK_RATE_2GHZ_OFDM
;
74 return usecs
*ATH9K_CLOCK_RATE_5GHZ_OFDM
;
77 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
79 struct ieee80211_conf
*conf
= &ah
->ah_sc
->hw
->conf
;
81 if (conf_is_ht40(conf
))
82 return ath9k_hw_mac_clks(ah
, usecs
) * 2;
84 return ath9k_hw_mac_clks(ah
, usecs
);
87 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
91 BUG_ON(timeout
< AH_TIME_QUANTUM
);
93 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
94 if ((REG_READ(ah
, reg
) & mask
) == val
)
97 udelay(AH_TIME_QUANTUM
);
100 DPRINTF(ah
->ah_sc
, ATH_DBG_REG_IO
,
101 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
102 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
107 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
112 for (i
= 0, retval
= 0; i
< n
; i
++) {
113 retval
= (retval
<< 1) | (val
& 1);
119 bool ath9k_get_channel_edges(struct ath_hw
*ah
,
123 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
125 if (flags
& CHANNEL_5GHZ
) {
126 *low
= pCap
->low_5ghz_chan
;
127 *high
= pCap
->high_5ghz_chan
;
130 if ((flags
& CHANNEL_2GHZ
)) {
131 *low
= pCap
->low_2ghz_chan
;
132 *high
= pCap
->high_2ghz_chan
;
138 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
139 struct ath_rate_table
*rates
,
140 u32 frameLen
, u16 rateix
,
143 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
146 kbps
= rates
->info
[rateix
].ratekbps
;
151 switch (rates
->info
[rateix
].phy
) {
152 case WLAN_RC_PHY_CCK
:
153 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
154 if (shortPreamble
&& rates
->info
[rateix
].short_preamble
)
156 numBits
= frameLen
<< 3;
157 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
159 case WLAN_RC_PHY_OFDM
:
160 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
161 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
162 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
163 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
164 txTime
= OFDM_SIFS_TIME_QUARTER
165 + OFDM_PREAMBLE_TIME_QUARTER
166 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
167 } else if (ah
->curchan
&&
168 IS_CHAN_HALF_RATE(ah
->curchan
)) {
169 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
170 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
171 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
172 txTime
= OFDM_SIFS_TIME_HALF
+
173 OFDM_PREAMBLE_TIME_HALF
174 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
176 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
177 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
178 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
179 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
180 + (numSymbols
* OFDM_SYMBOL_TIME
);
184 DPRINTF(ah
->ah_sc
, ATH_DBG_REG_IO
,
185 "Unknown phy %u (rate ix %u)\n",
186 rates
->info
[rateix
].phy
, rateix
);
194 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
195 struct ath9k_channel
*chan
,
196 struct chan_centers
*centers
)
200 if (!IS_CHAN_HT40(chan
)) {
201 centers
->ctl_center
= centers
->ext_center
=
202 centers
->synth_center
= chan
->channel
;
206 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
207 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
208 centers
->synth_center
=
209 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
212 centers
->synth_center
=
213 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
217 centers
->ctl_center
=
218 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
219 centers
->ext_center
=
220 centers
->synth_center
+ (extoff
*
221 ((ah
->extprotspacing
== ATH9K_HT_EXTPROTSPACING_20
) ?
222 HT40_CHANNEL_CENTER_SHIFT
: 15));
229 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
233 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
236 val
= REG_READ(ah
, AR_SREV
);
237 ah
->hw_version
.macVersion
=
238 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
239 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
240 ah
->is_pciexpress
= (val
& AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
242 if (!AR_SREV_9100(ah
))
243 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
245 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
247 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
248 ah
->is_pciexpress
= true;
252 static int ath9k_hw_get_radiorev(struct ath_hw
*ah
)
257 REG_WRITE(ah
, AR_PHY(0x36), 0x00007058);
259 for (i
= 0; i
< 8; i
++)
260 REG_WRITE(ah
, AR_PHY(0x20), 0x00010000);
261 val
= (REG_READ(ah
, AR_PHY(256)) >> 24) & 0xff;
262 val
= ((val
& 0xf0) >> 4) | ((val
& 0x0f) << 4);
264 return ath9k_hw_reverse_bits(val
, 8);
267 /************************************/
268 /* HW Attach, Detach, Init Routines */
269 /************************************/
271 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
273 if (AR_SREV_9100(ah
))
276 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
277 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
278 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
279 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
280 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
281 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
282 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
283 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
284 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
286 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
289 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
291 u32 regAddr
[2] = { AR_STA_ID0
, AR_PHY_BASE
+ (8 << 2) };
293 u32 patternData
[4] = { 0x55555555,
299 for (i
= 0; i
< 2; i
++) {
300 u32 addr
= regAddr
[i
];
303 regHold
[i
] = REG_READ(ah
, addr
);
304 for (j
= 0; j
< 0x100; j
++) {
305 wrData
= (j
<< 16) | j
;
306 REG_WRITE(ah
, addr
, wrData
);
307 rdData
= REG_READ(ah
, addr
);
308 if (rdData
!= wrData
) {
309 DPRINTF(ah
->ah_sc
, ATH_DBG_REG_IO
,
310 "address test failed "
311 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
312 addr
, wrData
, rdData
);
316 for (j
= 0; j
< 4; j
++) {
317 wrData
= patternData
[j
];
318 REG_WRITE(ah
, addr
, wrData
);
319 rdData
= REG_READ(ah
, addr
);
320 if (wrData
!= rdData
) {
321 DPRINTF(ah
->ah_sc
, ATH_DBG_REG_IO
,
322 "address test failed "
323 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
324 addr
, wrData
, rdData
);
328 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
335 static const char *ath9k_hw_devname(u16 devid
)
338 case AR5416_DEVID_PCI
:
339 return "Atheros 5416";
340 case AR5416_DEVID_PCIE
:
341 return "Atheros 5418";
342 case AR9160_DEVID_PCI
:
343 return "Atheros 9160";
344 case AR5416_AR9100_DEVID
:
345 return "Atheros 9100";
346 case AR9280_DEVID_PCI
:
347 case AR9280_DEVID_PCIE
:
348 return "Atheros 9280";
349 case AR9285_DEVID_PCIE
:
350 return "Atheros 9285";
356 static void ath9k_hw_set_defaults(struct ath_hw
*ah
)
360 ah
->config
.dma_beacon_response_time
= 2;
361 ah
->config
.sw_beacon_response_time
= 10;
362 ah
->config
.additional_swba_backoff
= 0;
363 ah
->config
.ack_6mb
= 0x0;
364 ah
->config
.cwm_ignore_extcca
= 0;
365 ah
->config
.pcie_powersave_enable
= 0;
366 ah
->config
.pcie_l1skp_enable
= 0;
367 ah
->config
.pcie_clock_req
= 0;
368 ah
->config
.pcie_power_reset
= 0x100;
369 ah
->config
.pcie_restore
= 0;
370 ah
->config
.pcie_waen
= 0;
371 ah
->config
.analog_shiftreg
= 1;
372 ah
->config
.ht_enable
= 1;
373 ah
->config
.ofdm_trig_low
= 200;
374 ah
->config
.ofdm_trig_high
= 500;
375 ah
->config
.cck_trig_high
= 200;
376 ah
->config
.cck_trig_low
= 100;
377 ah
->config
.enable_ani
= 1;
378 ah
->config
.noise_immunity_level
= 4;
379 ah
->config
.ofdm_weaksignal_det
= 1;
380 ah
->config
.cck_weaksignal_thr
= 0;
381 ah
->config
.spur_immunity_level
= 2;
382 ah
->config
.firstep_level
= 0;
383 ah
->config
.rssi_thr_high
= 40;
384 ah
->config
.rssi_thr_low
= 7;
385 ah
->config
.diversity_control
= 0;
386 ah
->config
.antenna_switch_swap
= 0;
388 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
389 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
390 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
393 ah
->config
.intr_mitigation
= 1;
396 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
397 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
398 * This means we use it for all AR5416 devices, and the few
399 * minor PCI AR9280 devices out there.
401 * Serialization is required because these devices do not handle
402 * well the case of two concurrent reads/writes due to the latency
403 * involved. During one read/write another read/write can be issued
404 * on another CPU while the previous read/write may still be working
405 * on our hardware, if we hit this case the hardware poops in a loop.
406 * We prevent this by serializing reads and writes.
408 * This issue is not present on PCI-Express devices or pre-AR5416
409 * devices (legacy, 802.11abg).
411 if (num_possible_cpus() > 1)
412 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
415 static struct ath_hw
*ath9k_hw_newstate(u16 devid
, struct ath_softc
*sc
,
420 ah
= kzalloc(sizeof(struct ath_hw
), GFP_KERNEL
);
422 DPRINTF(sc
, ATH_DBG_FATAL
,
423 "Cannot allocate memory for state block\n");
429 ah
->hw_version
.magic
= AR5416_MAGIC
;
430 ah
->regulatory
.country_code
= CTRY_DEFAULT
;
431 ah
->hw_version
.devid
= devid
;
432 ah
->hw_version
.subvendorid
= 0;
435 if ((devid
== AR5416_AR9100_DEVID
))
436 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
437 if (!AR_SREV_9100(ah
))
438 ah
->ah_flags
= AH_USE_EEPROM
;
440 ah
->regulatory
.power_limit
= MAX_RATE_POWER
;
441 ah
->regulatory
.tp_scale
= ATH9K_TP_SCALE_MAX
;
443 ah
->diversity_control
= ah
->config
.diversity_control
;
444 ah
->antenna_switch_swap
=
445 ah
->config
.antenna_switch_swap
;
446 ah
->sta_id1_defaults
= AR_STA_ID1_CRPT_MIC_ENABLE
;
447 ah
->beacon_interval
= 100;
448 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
449 ah
->slottime
= (u32
) -1;
450 ah
->acktimeout
= (u32
) -1;
451 ah
->ctstimeout
= (u32
) -1;
452 ah
->globaltxtimeout
= (u32
) -1;
454 ah
->gbeacon_rate
= 0;
459 static int ath9k_hw_rfattach(struct ath_hw
*ah
)
461 bool rfStatus
= false;
464 rfStatus
= ath9k_hw_init_rf(ah
, &ecode
);
466 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
,
467 "RF setup failed, status %u\n", ecode
);
474 static int ath9k_hw_rf_claim(struct ath_hw
*ah
)
478 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
480 val
= ath9k_hw_get_radiorev(ah
);
481 switch (val
& AR_RADIO_SREV_MAJOR
) {
483 val
= AR_RAD5133_SREV_MAJOR
;
485 case AR_RAD5133_SREV_MAJOR
:
486 case AR_RAD5122_SREV_MAJOR
:
487 case AR_RAD2133_SREV_MAJOR
:
488 case AR_RAD2122_SREV_MAJOR
:
491 DPRINTF(ah
->ah_sc
, ATH_DBG_CHANNEL
,
492 "5G Radio Chip Rev 0x%02X is not "
493 "supported by this driver\n",
494 ah
->hw_version
.analog5GhzRev
);
498 ah
->hw_version
.analog5GhzRev
= val
;
503 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
510 for (i
= 0; i
< 3; i
++) {
511 eeval
= ah
->eep_ops
->get_eeprom(ah
, AR_EEPROM_MAC(i
));
513 ah
->macaddr
[2 * i
] = eeval
>> 8;
514 ah
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
516 if (sum
== 0 || sum
== 0xffff * 3) {
517 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
518 "mac address read failed: %pM\n",
520 return -EADDRNOTAVAIL
;
526 static void ath9k_hw_init_rxgain_ini(struct ath_hw
*ah
)
530 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_17
) {
531 rxgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_RXGAIN_TYPE
);
533 if (rxgain_type
== AR5416_EEP_RXGAIN_13DB_BACKOFF
)
534 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
535 ar9280Modes_backoff_13db_rxgain_9280_2
,
536 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2
), 6);
537 else if (rxgain_type
== AR5416_EEP_RXGAIN_23DB_BACKOFF
)
538 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
539 ar9280Modes_backoff_23db_rxgain_9280_2
,
540 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2
), 6);
542 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
543 ar9280Modes_original_rxgain_9280_2
,
544 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
546 INIT_INI_ARRAY(&ah
->iniModesRxGain
,
547 ar9280Modes_original_rxgain_9280_2
,
548 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2
), 6);
552 static void ath9k_hw_init_txgain_ini(struct ath_hw
*ah
)
556 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MINOR_REV
) >= AR5416_EEP_MINOR_VER_19
) {
557 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
559 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
)
560 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
561 ar9280Modes_high_power_tx_gain_9280_2
,
562 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2
), 6);
564 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
565 ar9280Modes_original_tx_gain_9280_2
,
566 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
568 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
569 ar9280Modes_original_tx_gain_9280_2
,
570 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2
), 6);
574 static int ath9k_hw_post_attach(struct ath_hw
*ah
)
578 if (!ath9k_hw_chip_test(ah
)) {
579 DPRINTF(ah
->ah_sc
, ATH_DBG_REG_IO
,
580 "hardware self-test failed\n");
584 ecode
= ath9k_hw_rf_claim(ah
);
588 ecode
= ath9k_hw_eeprom_attach(ah
);
592 DPRINTF(ah
->ah_sc
, ATH_DBG_CONFIG
, "Eeprom VER: %d, REV: %d\n",
593 ah
->eep_ops
->get_eeprom_ver(ah
), ah
->eep_ops
->get_eeprom_rev(ah
));
595 ecode
= ath9k_hw_rfattach(ah
);
599 if (!AR_SREV_9100(ah
)) {
600 ath9k_hw_ani_setup(ah
);
601 ath9k_hw_ani_attach(ah
);
607 static struct ath_hw
*ath9k_hw_do_attach(u16 devid
, struct ath_softc
*sc
,
614 ah
= ath9k_hw_newstate(devid
, sc
, status
);
618 ath9k_hw_set_defaults(ah
);
620 if (ah
->config
.intr_mitigation
!= 0)
621 ah
->intr_mitigation
= true;
623 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
624 DPRINTF(sc
, ATH_DBG_RESET
, "Couldn't reset chip\n");
629 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
630 DPRINTF(sc
, ATH_DBG_RESET
, "Couldn't wakeup chip\n");
635 if (ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
636 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
637 (AR_SREV_9280(ah
) && !ah
->is_pciexpress
)) {
638 ah
->config
.serialize_regmode
=
641 ah
->config
.serialize_regmode
=
646 DPRINTF(sc
, ATH_DBG_RESET
, "serialize_regmode is %d\n",
647 ah
->config
.serialize_regmode
);
649 if ((ah
->hw_version
.macVersion
!= AR_SREV_VERSION_5416_PCI
) &&
650 (ah
->hw_version
.macVersion
!= AR_SREV_VERSION_5416_PCIE
) &&
651 (ah
->hw_version
.macVersion
!= AR_SREV_VERSION_9160
) &&
652 (!AR_SREV_9100(ah
)) && (!AR_SREV_9280(ah
)) && (!AR_SREV_9285(ah
))) {
653 DPRINTF(sc
, ATH_DBG_RESET
,
654 "Mac Chip Rev 0x%02x.%x is not supported by "
655 "this driver\n", ah
->hw_version
.macVersion
,
656 ah
->hw_version
.macRev
);
661 if (AR_SREV_9100(ah
)) {
662 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
663 ah
->supp_cals
= IQ_MISMATCH_CAL
;
664 ah
->is_pciexpress
= false;
666 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
668 if (AR_SREV_9160_10_OR_LATER(ah
)) {
669 if (AR_SREV_9280_10_OR_LATER(ah
)) {
670 ah
->iq_caldata
.calData
= &iq_cal_single_sample
;
671 ah
->adcgain_caldata
.calData
=
672 &adc_gain_cal_single_sample
;
673 ah
->adcdc_caldata
.calData
=
674 &adc_dc_cal_single_sample
;
675 ah
->adcdc_calinitdata
.calData
=
678 ah
->iq_caldata
.calData
= &iq_cal_multi_sample
;
679 ah
->adcgain_caldata
.calData
=
680 &adc_gain_cal_multi_sample
;
681 ah
->adcdc_caldata
.calData
=
682 &adc_dc_cal_multi_sample
;
683 ah
->adcdc_calinitdata
.calData
=
686 ah
->supp_cals
= ADC_GAIN_CAL
| ADC_DC_CAL
| IQ_MISMATCH_CAL
;
689 ah
->ani_function
= ATH9K_ANI_ALL
;
690 if (AR_SREV_9280_10_OR_LATER(ah
))
691 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
693 DPRINTF(sc
, ATH_DBG_RESET
,
694 "This Mac Chip Rev 0x%02x.%x is \n",
695 ah
->hw_version
.macVersion
, ah
->hw_version
.macRev
);
697 if (AR_SREV_9285_12_OR_LATER(ah
)) {
699 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285_1_2
,
700 ARRAY_SIZE(ar9285Modes_9285_1_2
), 6);
701 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285_1_2
,
702 ARRAY_SIZE(ar9285Common_9285_1_2
), 2);
704 if (ah
->config
.pcie_clock_req
) {
705 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
706 ar9285PciePhy_clkreq_off_L1_9285_1_2
,
707 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2
), 2);
709 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
710 ar9285PciePhy_clkreq_always_on_L1_9285_1_2
,
711 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2
),
714 } else if (AR_SREV_9285_10_OR_LATER(ah
)) {
715 INIT_INI_ARRAY(&ah
->iniModes
, ar9285Modes_9285
,
716 ARRAY_SIZE(ar9285Modes_9285
), 6);
717 INIT_INI_ARRAY(&ah
->iniCommon
, ar9285Common_9285
,
718 ARRAY_SIZE(ar9285Common_9285
), 2);
720 if (ah
->config
.pcie_clock_req
) {
721 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
722 ar9285PciePhy_clkreq_off_L1_9285
,
723 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285
), 2);
725 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
726 ar9285PciePhy_clkreq_always_on_L1_9285
,
727 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285
), 2);
729 } else if (AR_SREV_9280_20_OR_LATER(ah
)) {
730 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280_2
,
731 ARRAY_SIZE(ar9280Modes_9280_2
), 6);
732 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280_2
,
733 ARRAY_SIZE(ar9280Common_9280_2
), 2);
735 if (ah
->config
.pcie_clock_req
) {
736 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
737 ar9280PciePhy_clkreq_off_L1_9280
,
738 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280
),2);
740 INIT_INI_ARRAY(&ah
->iniPcieSerdes
,
741 ar9280PciePhy_clkreq_always_on_L1_9280
,
742 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280
), 2);
744 INIT_INI_ARRAY(&ah
->iniModesAdditional
,
745 ar9280Modes_fast_clock_9280_2
,
746 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2
), 3);
747 } else if (AR_SREV_9280_10_OR_LATER(ah
)) {
748 INIT_INI_ARRAY(&ah
->iniModes
, ar9280Modes_9280
,
749 ARRAY_SIZE(ar9280Modes_9280
), 6);
750 INIT_INI_ARRAY(&ah
->iniCommon
, ar9280Common_9280
,
751 ARRAY_SIZE(ar9280Common_9280
), 2);
752 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
753 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9160
,
754 ARRAY_SIZE(ar5416Modes_9160
), 6);
755 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9160
,
756 ARRAY_SIZE(ar5416Common_9160
), 2);
757 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9160
,
758 ARRAY_SIZE(ar5416Bank0_9160
), 2);
759 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9160
,
760 ARRAY_SIZE(ar5416BB_RfGain_9160
), 3);
761 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9160
,
762 ARRAY_SIZE(ar5416Bank1_9160
), 2);
763 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9160
,
764 ARRAY_SIZE(ar5416Bank2_9160
), 2);
765 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9160
,
766 ARRAY_SIZE(ar5416Bank3_9160
), 3);
767 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9160
,
768 ARRAY_SIZE(ar5416Bank6_9160
), 3);
769 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9160
,
770 ARRAY_SIZE(ar5416Bank6TPC_9160
), 3);
771 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9160
,
772 ARRAY_SIZE(ar5416Bank7_9160
), 2);
773 if (AR_SREV_9160_11(ah
)) {
774 INIT_INI_ARRAY(&ah
->iniAddac
,
776 ARRAY_SIZE(ar5416Addac_91601_1
), 2);
778 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9160
,
779 ARRAY_SIZE(ar5416Addac_9160
), 2);
781 } else if (AR_SREV_9100_OR_LATER(ah
)) {
782 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes_9100
,
783 ARRAY_SIZE(ar5416Modes_9100
), 6);
784 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common_9100
,
785 ARRAY_SIZE(ar5416Common_9100
), 2);
786 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0_9100
,
787 ARRAY_SIZE(ar5416Bank0_9100
), 2);
788 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain_9100
,
789 ARRAY_SIZE(ar5416BB_RfGain_9100
), 3);
790 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1_9100
,
791 ARRAY_SIZE(ar5416Bank1_9100
), 2);
792 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2_9100
,
793 ARRAY_SIZE(ar5416Bank2_9100
), 2);
794 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3_9100
,
795 ARRAY_SIZE(ar5416Bank3_9100
), 3);
796 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6_9100
,
797 ARRAY_SIZE(ar5416Bank6_9100
), 3);
798 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC_9100
,
799 ARRAY_SIZE(ar5416Bank6TPC_9100
), 3);
800 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7_9100
,
801 ARRAY_SIZE(ar5416Bank7_9100
), 2);
802 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac_9100
,
803 ARRAY_SIZE(ar5416Addac_9100
), 2);
805 INIT_INI_ARRAY(&ah
->iniModes
, ar5416Modes
,
806 ARRAY_SIZE(ar5416Modes
), 6);
807 INIT_INI_ARRAY(&ah
->iniCommon
, ar5416Common
,
808 ARRAY_SIZE(ar5416Common
), 2);
809 INIT_INI_ARRAY(&ah
->iniBank0
, ar5416Bank0
,
810 ARRAY_SIZE(ar5416Bank0
), 2);
811 INIT_INI_ARRAY(&ah
->iniBB_RfGain
, ar5416BB_RfGain
,
812 ARRAY_SIZE(ar5416BB_RfGain
), 3);
813 INIT_INI_ARRAY(&ah
->iniBank1
, ar5416Bank1
,
814 ARRAY_SIZE(ar5416Bank1
), 2);
815 INIT_INI_ARRAY(&ah
->iniBank2
, ar5416Bank2
,
816 ARRAY_SIZE(ar5416Bank2
), 2);
817 INIT_INI_ARRAY(&ah
->iniBank3
, ar5416Bank3
,
818 ARRAY_SIZE(ar5416Bank3
), 3);
819 INIT_INI_ARRAY(&ah
->iniBank6
, ar5416Bank6
,
820 ARRAY_SIZE(ar5416Bank6
), 3);
821 INIT_INI_ARRAY(&ah
->iniBank6TPC
, ar5416Bank6TPC
,
822 ARRAY_SIZE(ar5416Bank6TPC
), 3);
823 INIT_INI_ARRAY(&ah
->iniBank7
, ar5416Bank7
,
824 ARRAY_SIZE(ar5416Bank7
), 2);
825 INIT_INI_ARRAY(&ah
->iniAddac
, ar5416Addac
,
826 ARRAY_SIZE(ar5416Addac
), 2);
829 if (ah
->is_pciexpress
)
830 ath9k_hw_configpcipowersave(ah
, 0);
832 ath9k_hw_disablepcie(ah
);
834 ecode
= ath9k_hw_post_attach(ah
);
838 if (AR_SREV_9285_12_OR_LATER(ah
)) {
839 u32 txgain_type
= ah
->eep_ops
->get_eeprom(ah
, EEP_TXGAIN_TYPE
);
842 if (txgain_type
== AR5416_EEP_TXGAIN_HIGH_POWER
) {
843 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
844 ar9285Modes_high_power_tx_gain_9285_1_2
,
845 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2
), 6);
847 INIT_INI_ARRAY(&ah
->iniModesTxGain
,
848 ar9285Modes_original_tx_gain_9285_1_2
,
849 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2
), 6);
855 if (AR_SREV_9280_20(ah
))
856 ath9k_hw_init_rxgain_ini(ah
);
859 if (AR_SREV_9280_20(ah
))
860 ath9k_hw_init_txgain_ini(ah
);
862 if (!ath9k_hw_fill_cap_info(ah
)) {
863 DPRINTF(sc
, ATH_DBG_RESET
, "failed ath9k_hw_fill_cap_info\n");
868 if ((ah
->hw_version
.devid
== AR9280_DEVID_PCI
) &&
869 test_bit(ATH9K_MODE_11A
, ah
->caps
.wireless_modes
)) {
872 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
873 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
875 for (j
= 1; j
< ah
->iniModes
.ia_columns
; j
++) {
876 u32 val
= INI_RA(&ah
->iniModes
, i
, j
);
878 INI_RA(&ah
->iniModes
, i
, j
) =
879 ath9k_hw_ini_fixup(ah
,
886 ecode
= ath9k_hw_init_macaddr(ah
);
888 DPRINTF(sc
, ATH_DBG_RESET
,
889 "failed initializing mac address\n");
893 if (AR_SREV_9285(ah
))
894 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
896 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
898 ath9k_init_nfcal_hist_buffer(ah
);
910 static void ath9k_hw_init_bb(struct ath_hw
*ah
,
911 struct ath9k_channel
*chan
)
915 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
917 synthDelay
= (4 * synthDelay
) / 22;
921 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_EN
);
923 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
926 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
928 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
929 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
931 REG_WRITE(ah
, AR_QOS_NO_ACK
,
932 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
933 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
934 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
936 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
937 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
938 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
939 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
940 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
943 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
944 struct ath9k_channel
*chan
)
948 if (AR_SREV_9100(ah
)) {
949 if (chan
&& IS_CHAN_5GHZ(chan
))
954 if (AR_SREV_9280_10_OR_LATER(ah
)) {
955 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
957 if (chan
&& IS_CHAN_HALF_RATE(chan
))
958 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
959 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
960 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
962 if (chan
&& IS_CHAN_5GHZ(chan
)) {
963 pll
|= SM(0x28, AR_RTC_9160_PLL_DIV
);
966 if (AR_SREV_9280_20(ah
)) {
967 if (((chan
->channel
% 20) == 0)
968 || ((chan
->channel
% 10) == 0))
974 pll
|= SM(0x2c, AR_RTC_9160_PLL_DIV
);
977 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
979 pll
= SM(0x5, AR_RTC_9160_PLL_REFDIV
);
981 if (chan
&& IS_CHAN_HALF_RATE(chan
))
982 pll
|= SM(0x1, AR_RTC_9160_PLL_CLKSEL
);
983 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
984 pll
|= SM(0x2, AR_RTC_9160_PLL_CLKSEL
);
986 if (chan
&& IS_CHAN_5GHZ(chan
))
987 pll
|= SM(0x50, AR_RTC_9160_PLL_DIV
);
989 pll
|= SM(0x58, AR_RTC_9160_PLL_DIV
);
991 pll
= AR_RTC_PLL_REFDIV_5
| AR_RTC_PLL_DIV2
;
993 if (chan
&& IS_CHAN_HALF_RATE(chan
))
994 pll
|= SM(0x1, AR_RTC_PLL_CLKSEL
);
995 else if (chan
&& IS_CHAN_QUARTER_RATE(chan
))
996 pll
|= SM(0x2, AR_RTC_PLL_CLKSEL
);
998 if (chan
&& IS_CHAN_5GHZ(chan
))
999 pll
|= SM(0xa, AR_RTC_PLL_DIV
);
1001 pll
|= SM(0xb, AR_RTC_PLL_DIV
);
1004 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
1006 udelay(RTC_PLL_SETTLE_DELAY
);
1008 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
1011 static void ath9k_hw_init_chain_masks(struct ath_hw
*ah
)
1013 int rx_chainmask
, tx_chainmask
;
1015 rx_chainmask
= ah
->rxchainmask
;
1016 tx_chainmask
= ah
->txchainmask
;
1018 switch (rx_chainmask
) {
1020 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1021 AR_PHY_SWAP_ALT_CHAIN
);
1023 if (((ah
)->hw_version
.macVersion
<= AR_SREV_VERSION_9160
)) {
1024 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, 0x7);
1025 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, 0x7);
1031 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
1032 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
1038 REG_WRITE(ah
, AR_SELFGEN_MASK
, tx_chainmask
);
1039 if (tx_chainmask
== 0x5) {
1040 REG_SET_BIT(ah
, AR_PHY_ANALOG_SWAP
,
1041 AR_PHY_SWAP_ALT_CHAIN
);
1043 if (AR_SREV_9100(ah
))
1044 REG_WRITE(ah
, AR_PHY_ANALOG_SWAP
,
1045 REG_READ(ah
, AR_PHY_ANALOG_SWAP
) | 0x00000001);
1048 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
1049 enum nl80211_iftype opmode
)
1051 ah
->mask_reg
= AR_IMR_TXERR
|
1057 if (ah
->intr_mitigation
)
1058 ah
->mask_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
1060 ah
->mask_reg
|= AR_IMR_RXOK
;
1062 ah
->mask_reg
|= AR_IMR_TXOK
;
1064 if (opmode
== NL80211_IFTYPE_AP
)
1065 ah
->mask_reg
|= AR_IMR_MIB
;
1067 REG_WRITE(ah
, AR_IMR
, ah
->mask_reg
);
1068 REG_WRITE(ah
, AR_IMR_S2
, REG_READ(ah
, AR_IMR_S2
) | AR_IMR_S2_GTT
);
1070 if (!AR_SREV_9100(ah
)) {
1071 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
1072 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, AR_INTR_SYNC_DEFAULT
);
1073 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
1077 static bool ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
1079 if (us
> ath9k_hw_mac_to_usec(ah
, MS(0xffffffff, AR_TIME_OUT_ACK
))) {
1080 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "bad ack timeout %u\n", us
);
1081 ah
->acktimeout
= (u32
) -1;
1084 REG_RMW_FIELD(ah
, AR_TIME_OUT
,
1085 AR_TIME_OUT_ACK
, ath9k_hw_mac_to_clks(ah
, us
));
1086 ah
->acktimeout
= us
;
1091 static bool ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
1093 if (us
> ath9k_hw_mac_to_usec(ah
, MS(0xffffffff, AR_TIME_OUT_CTS
))) {
1094 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "bad cts timeout %u\n", us
);
1095 ah
->ctstimeout
= (u32
) -1;
1098 REG_RMW_FIELD(ah
, AR_TIME_OUT
,
1099 AR_TIME_OUT_CTS
, ath9k_hw_mac_to_clks(ah
, us
));
1100 ah
->ctstimeout
= us
;
1105 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
1108 DPRINTF(ah
->ah_sc
, ATH_DBG_XMIT
,
1109 "bad global tx timeout %u\n", tu
);
1110 ah
->globaltxtimeout
= (u32
) -1;
1113 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
1114 ah
->globaltxtimeout
= tu
;
1119 static void ath9k_hw_init_user_settings(struct ath_hw
*ah
)
1121 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "ah->misc_mode 0x%x\n",
1124 if (ah
->misc_mode
!= 0)
1125 REG_WRITE(ah
, AR_PCU_MISC
,
1126 REG_READ(ah
, AR_PCU_MISC
) | ah
->misc_mode
);
1127 if (ah
->slottime
!= (u32
) -1)
1128 ath9k_hw_setslottime(ah
, ah
->slottime
);
1129 if (ah
->acktimeout
!= (u32
) -1)
1130 ath9k_hw_set_ack_timeout(ah
, ah
->acktimeout
);
1131 if (ah
->ctstimeout
!= (u32
) -1)
1132 ath9k_hw_set_cts_timeout(ah
, ah
->ctstimeout
);
1133 if (ah
->globaltxtimeout
!= (u32
) -1)
1134 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
1137 const char *ath9k_hw_probe(u16 vendorid
, u16 devid
)
1139 return vendorid
== ATHEROS_VENDOR_ID
?
1140 ath9k_hw_devname(devid
) : NULL
;
1143 void ath9k_hw_detach(struct ath_hw
*ah
)
1145 if (!AR_SREV_9100(ah
))
1146 ath9k_hw_ani_detach(ah
);
1148 ath9k_hw_rfdetach(ah
);
1149 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1153 struct ath_hw
*ath9k_hw_attach(u16 devid
, struct ath_softc
*sc
, int *error
)
1155 struct ath_hw
*ah
= NULL
;
1158 case AR5416_DEVID_PCI
:
1159 case AR5416_DEVID_PCIE
:
1160 case AR5416_AR9100_DEVID
:
1161 case AR9160_DEVID_PCI
:
1162 case AR9280_DEVID_PCI
:
1163 case AR9280_DEVID_PCIE
:
1164 case AR9285_DEVID_PCIE
:
1165 ah
= ath9k_hw_do_attach(devid
, sc
, error
);
1179 static void ath9k_hw_override_ini(struct ath_hw
*ah
,
1180 struct ath9k_channel
*chan
)
1183 * Set the RX_ABORT and RX_DIS and clear if off only after
1184 * RXE is set for MAC. This prevents frames with corrupted
1185 * descriptor status.
1187 REG_SET_BIT(ah
, AR_DIAG_SW
, (AR_DIAG_RX_DIS
| AR_DIAG_RX_ABORT
));
1190 if (!AR_SREV_5416_20_OR_LATER(ah
) ||
1191 AR_SREV_9280_10_OR_LATER(ah
))
1194 REG_WRITE(ah
, 0x9800 + (651 << 2), 0x11);
1197 static u32
ath9k_hw_def_ini_fixup(struct ath_hw
*ah
,
1198 struct ar5416_eeprom_def
*pEepData
,
1201 struct base_eep_header
*pBase
= &(pEepData
->baseEepHeader
);
1203 switch (ah
->hw_version
.devid
) {
1204 case AR9280_DEVID_PCI
:
1205 if (reg
== 0x7894) {
1206 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
1207 "ini VAL: %x EEPROM: %x\n", value
,
1208 (pBase
->version
& 0xff));
1210 if ((pBase
->version
& 0xff) > 0x0a) {
1211 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
1214 value
&= ~AR_AN_TOP2_PWDCLKIND
;
1215 value
|= AR_AN_TOP2_PWDCLKIND
&
1216 (pBase
->pwdclkind
<< AR_AN_TOP2_PWDCLKIND_S
);
1218 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
1219 "PWDCLKIND Earlier Rev\n");
1222 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
1223 "final ini VAL: %x\n", value
);
1231 static u32
ath9k_hw_ini_fixup(struct ath_hw
*ah
,
1232 struct ar5416_eeprom_def
*pEepData
,
1235 if (ah
->eep_map
== EEP_MAP_4KBITS
)
1238 return ath9k_hw_def_ini_fixup(ah
, pEepData
, reg
, value
);
1241 static void ath9k_olc_init(struct ath_hw
*ah
)
1245 for (i
= 0; i
< AR9280_TX_GAIN_TABLE_SIZE
; i
++)
1246 ah
->originalGain
[i
] =
1247 MS(REG_READ(ah
, AR_PHY_TX_GAIN_TBL1
+ i
* 4),
1252 static int ath9k_hw_process_ini(struct ath_hw
*ah
,
1253 struct ath9k_channel
*chan
,
1254 enum ath9k_ht_macmode macmode
)
1256 int i
, regWrites
= 0;
1257 struct ieee80211_channel
*channel
= chan
->chan
;
1258 u32 modesIndex
, freqIndex
;
1261 switch (chan
->chanmode
) {
1263 case CHANNEL_A_HT20
:
1267 case CHANNEL_A_HT40PLUS
:
1268 case CHANNEL_A_HT40MINUS
:
1273 case CHANNEL_G_HT20
:
1278 case CHANNEL_G_HT40PLUS
:
1279 case CHANNEL_G_HT40MINUS
:
1288 REG_WRITE(ah
, AR_PHY(0), 0x00000007);
1289 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_EXTERNAL_RADIO
);
1290 ah
->eep_ops
->set_addac(ah
, chan
);
1292 if (AR_SREV_5416_22_OR_LATER(ah
)) {
1293 REG_WRITE_ARRAY(&ah
->iniAddac
, 1, regWrites
);
1295 struct ar5416IniArray temp
;
1297 sizeof(u32
) * ah
->iniAddac
.ia_rows
*
1298 ah
->iniAddac
.ia_columns
;
1300 memcpy(ah
->addac5416_21
,
1301 ah
->iniAddac
.ia_array
, addacSize
);
1303 (ah
->addac5416_21
)[31 * ah
->iniAddac
.ia_columns
+ 1] = 0;
1305 temp
.ia_array
= ah
->addac5416_21
;
1306 temp
.ia_columns
= ah
->iniAddac
.ia_columns
;
1307 temp
.ia_rows
= ah
->iniAddac
.ia_rows
;
1308 REG_WRITE_ARRAY(&temp
, 1, regWrites
);
1311 REG_WRITE(ah
, AR_PHY_ADC_SERIAL_CTL
, AR_PHY_SEL_INTERNAL_ADDAC
);
1313 for (i
= 0; i
< ah
->iniModes
.ia_rows
; i
++) {
1314 u32 reg
= INI_RA(&ah
->iniModes
, i
, 0);
1315 u32 val
= INI_RA(&ah
->iniModes
, i
, modesIndex
);
1317 REG_WRITE(ah
, reg
, val
);
1319 if (reg
>= 0x7800 && reg
< 0x78a0
1320 && ah
->config
.analog_shiftreg
) {
1324 DO_DELAY(regWrites
);
1327 if (AR_SREV_9280(ah
))
1328 REG_WRITE_ARRAY(&ah
->iniModesRxGain
, modesIndex
, regWrites
);
1330 if (AR_SREV_9280(ah
) || (AR_SREV_9285(ah
) &&
1331 AR_SREV_9285_12_OR_LATER(ah
)))
1332 REG_WRITE_ARRAY(&ah
->iniModesTxGain
, modesIndex
, regWrites
);
1334 for (i
= 0; i
< ah
->iniCommon
.ia_rows
; i
++) {
1335 u32 reg
= INI_RA(&ah
->iniCommon
, i
, 0);
1336 u32 val
= INI_RA(&ah
->iniCommon
, i
, 1);
1338 REG_WRITE(ah
, reg
, val
);
1340 if (reg
>= 0x7800 && reg
< 0x78a0
1341 && ah
->config
.analog_shiftreg
) {
1345 DO_DELAY(regWrites
);
1348 ath9k_hw_write_regs(ah
, modesIndex
, freqIndex
, regWrites
);
1350 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
)) {
1351 REG_WRITE_ARRAY(&ah
->iniModesAdditional
, modesIndex
,
1355 ath9k_hw_override_ini(ah
, chan
);
1356 ath9k_hw_set_regs(ah
, chan
, macmode
);
1357 ath9k_hw_init_chain_masks(ah
);
1359 if (OLC_FOR_AR9280_20_LATER
)
1362 status
= ah
->eep_ops
->set_txpower(ah
, chan
,
1363 ath9k_regd_get_ctl(ah
, chan
),
1364 channel
->max_antenna_gain
* 2,
1365 channel
->max_power
* 2,
1366 min((u32
) MAX_RATE_POWER
,
1367 (u32
) ah
->regulatory
.power_limit
));
1369 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
,
1370 "error init'ing transmit power\n");
1374 if (!ath9k_hw_set_rf_regs(ah
, chan
, freqIndex
)) {
1375 DPRINTF(ah
->ah_sc
, ATH_DBG_REG_IO
,
1376 "ar5416SetRfRegs failed\n");
1383 /****************************************/
1384 /* Reset and Channel Switching Routines */
1385 /****************************************/
1387 static void ath9k_hw_set_rfmode(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1394 rfMode
|= (IS_CHAN_B(chan
) || IS_CHAN_G(chan
))
1395 ? AR_PHY_MODE_DYNAMIC
: AR_PHY_MODE_OFDM
;
1397 if (!AR_SREV_9280_10_OR_LATER(ah
))
1398 rfMode
|= (IS_CHAN_5GHZ(chan
)) ?
1399 AR_PHY_MODE_RF5GHZ
: AR_PHY_MODE_RF2GHZ
;
1401 if (AR_SREV_9280_20(ah
) && IS_CHAN_A_5MHZ_SPACED(chan
))
1402 rfMode
|= (AR_PHY_MODE_DYNAMIC
| AR_PHY_MODE_DYN_CCK_DISABLE
);
1404 REG_WRITE(ah
, AR_PHY_MODE
, rfMode
);
1407 static void ath9k_hw_mark_phy_inactive(struct ath_hw
*ah
)
1409 REG_WRITE(ah
, AR_PHY_ACTIVE
, AR_PHY_ACTIVE_DIS
);
1412 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
1416 regval
= REG_READ(ah
, AR_AHB_MODE
);
1417 REG_WRITE(ah
, AR_AHB_MODE
, regval
| AR_AHB_PREFETCH_RD_EN
);
1419 regval
= REG_READ(ah
, AR_TXCFG
) & ~AR_TXCFG_DMASZ_MASK
;
1420 REG_WRITE(ah
, AR_TXCFG
, regval
| AR_TXCFG_DMASZ_128B
);
1422 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
1424 regval
= REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_DMASZ_MASK
;
1425 REG_WRITE(ah
, AR_RXCFG
, regval
| AR_RXCFG_DMASZ_128B
);
1427 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
1429 if (AR_SREV_9285(ah
)) {
1430 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1431 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
1433 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1434 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
1438 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
1442 val
= REG_READ(ah
, AR_STA_ID1
);
1443 val
&= ~(AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
);
1445 case NL80211_IFTYPE_AP
:
1446 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_STA_AP
1447 | AR_STA_ID1_KSRCH_MODE
);
1448 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1450 case NL80211_IFTYPE_ADHOC
:
1451 case NL80211_IFTYPE_MESH_POINT
:
1452 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_ADHOC
1453 | AR_STA_ID1_KSRCH_MODE
);
1454 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1456 case NL80211_IFTYPE_STATION
:
1457 case NL80211_IFTYPE_MONITOR
:
1458 REG_WRITE(ah
, AR_STA_ID1
, val
| AR_STA_ID1_KSRCH_MODE
);
1463 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
,
1468 u32 coef_exp
, coef_man
;
1470 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
1471 if ((coef_scaled
>> coef_exp
) & 0x1)
1474 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
1476 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
1478 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
1479 *coef_exponent
= coef_exp
- 16;
1482 static void ath9k_hw_set_delta_slope(struct ath_hw
*ah
,
1483 struct ath9k_channel
*chan
)
1485 u32 coef_scaled
, ds_coef_exp
, ds_coef_man
;
1486 u32 clockMhzScaled
= 0x64000000;
1487 struct chan_centers centers
;
1489 if (IS_CHAN_HALF_RATE(chan
))
1490 clockMhzScaled
= clockMhzScaled
>> 1;
1491 else if (IS_CHAN_QUARTER_RATE(chan
))
1492 clockMhzScaled
= clockMhzScaled
>> 2;
1494 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
1495 coef_scaled
= clockMhzScaled
/ centers
.synth_center
;
1497 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1500 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1501 AR_PHY_TIMING3_DSC_MAN
, ds_coef_man
);
1502 REG_RMW_FIELD(ah
, AR_PHY_TIMING3
,
1503 AR_PHY_TIMING3_DSC_EXP
, ds_coef_exp
);
1505 coef_scaled
= (9 * coef_scaled
) / 10;
1507 ath9k_hw_get_delta_slope_vals(ah
, coef_scaled
, &ds_coef_man
,
1510 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1511 AR_PHY_HALFGI_DSC_MAN
, ds_coef_man
);
1512 REG_RMW_FIELD(ah
, AR_PHY_HALFGI
,
1513 AR_PHY_HALFGI_DSC_EXP
, ds_coef_exp
);
1516 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
1521 if (AR_SREV_9100(ah
)) {
1522 u32 val
= REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1523 val
&= ~AR_RTC_DERIVED_CLK_PERIOD
;
1524 val
|= SM(1, AR_RTC_DERIVED_CLK_PERIOD
);
1525 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, val
);
1526 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1529 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1530 AR_RTC_FORCE_WAKE_ON_INT
);
1532 if (AR_SREV_9100(ah
)) {
1533 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1534 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1536 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1538 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
1539 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
1540 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1541 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1543 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1546 rst_flags
= AR_RTC_RC_MAC_WARM
;
1547 if (type
== ATH9K_RESET_COLD
)
1548 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1551 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1554 REG_WRITE(ah
, AR_RTC_RC
, 0);
1555 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1556 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
,
1557 "RTC stuck in MAC reset\n");
1561 if (!AR_SREV_9100(ah
))
1562 REG_WRITE(ah
, AR_RC
, 0);
1564 ath9k_hw_init_pll(ah
, NULL
);
1566 if (AR_SREV_9100(ah
))
1572 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1574 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1575 AR_RTC_FORCE_WAKE_ON_INT
);
1577 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1579 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1581 if (!ath9k_hw_wait(ah
,
1586 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "RTC not waking up\n");
1590 ath9k_hw_read_revisions(ah
);
1592 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1595 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1597 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1598 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1601 case ATH9K_RESET_POWER_ON
:
1602 return ath9k_hw_set_reset_power_on(ah
);
1604 case ATH9K_RESET_WARM
:
1605 case ATH9K_RESET_COLD
:
1606 return ath9k_hw_set_reset(ah
, type
);
1613 static void ath9k_hw_set_regs(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1614 enum ath9k_ht_macmode macmode
)
1617 u32 enableDacFifo
= 0;
1619 if (AR_SREV_9285_10_OR_LATER(ah
))
1620 enableDacFifo
= (REG_READ(ah
, AR_PHY_TURBO
) &
1621 AR_PHY_FC_ENABLE_DAC_FIFO
);
1623 phymode
= AR_PHY_FC_HT_EN
| AR_PHY_FC_SHORT_GI_40
1624 | AR_PHY_FC_SINGLE_HT_LTF1
| AR_PHY_FC_WALSH
| enableDacFifo
;
1626 if (IS_CHAN_HT40(chan
)) {
1627 phymode
|= AR_PHY_FC_DYN2040_EN
;
1629 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
1630 (chan
->chanmode
== CHANNEL_G_HT40PLUS
))
1631 phymode
|= AR_PHY_FC_DYN2040_PRI_CH
;
1633 if (ah
->extprotspacing
== ATH9K_HT_EXTPROTSPACING_25
)
1634 phymode
|= AR_PHY_FC_DYN2040_EXT_CH
;
1636 REG_WRITE(ah
, AR_PHY_TURBO
, phymode
);
1638 ath9k_hw_set11nmac2040(ah
, macmode
);
1640 REG_WRITE(ah
, AR_GTXTO
, 25 << AR_GTXTO_TIMEOUT_LIMIT_S
);
1641 REG_WRITE(ah
, AR_CST
, 0xF << AR_CST_TIMEOUT_LIMIT_S
);
1644 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1645 struct ath9k_channel
*chan
)
1647 if (OLC_FOR_AR9280_20_LATER
) {
1648 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
))
1650 } else if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
1653 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1656 ah
->chip_fullsleep
= false;
1657 ath9k_hw_init_pll(ah
, chan
);
1658 ath9k_hw_set_rfmode(ah
, chan
);
1663 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1664 struct ath9k_channel
*chan
,
1665 enum ath9k_ht_macmode macmode
)
1667 struct ieee80211_channel
*channel
= chan
->chan
;
1668 u32 synthDelay
, qnum
;
1670 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1671 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1672 DPRINTF(ah
->ah_sc
, ATH_DBG_QUEUE
,
1673 "Transmit frames pending on queue %d\n", qnum
);
1678 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, AR_PHY_RFBUS_REQ_EN
);
1679 if (!ath9k_hw_wait(ah
, AR_PHY_RFBUS_GRANT
, AR_PHY_RFBUS_GRANT_EN
,
1680 AR_PHY_RFBUS_GRANT_EN
, AH_WAIT_TIMEOUT
)) {
1681 DPRINTF(ah
->ah_sc
, ATH_DBG_REG_IO
,
1682 "Could not kill baseband RX\n");
1686 ath9k_hw_set_regs(ah
, chan
, macmode
);
1688 if (AR_SREV_9280_10_OR_LATER(ah
)) {
1689 if (!(ath9k_hw_ar9280_set_channel(ah
, chan
))) {
1690 DPRINTF(ah
->ah_sc
, ATH_DBG_CHANNEL
,
1691 "failed to set channel\n");
1695 if (!(ath9k_hw_set_channel(ah
, chan
))) {
1696 DPRINTF(ah
->ah_sc
, ATH_DBG_CHANNEL
,
1697 "failed to set channel\n");
1702 if (ah
->eep_ops
->set_txpower(ah
, chan
,
1703 ath9k_regd_get_ctl(ah
, chan
),
1704 channel
->max_antenna_gain
* 2,
1705 channel
->max_power
* 2,
1706 min((u32
) MAX_RATE_POWER
,
1707 (u32
) ah
->regulatory
.power_limit
)) != 0) {
1708 DPRINTF(ah
->ah_sc
, ATH_DBG_EEPROM
,
1709 "error init'ing transmit power\n");
1713 synthDelay
= REG_READ(ah
, AR_PHY_RX_DELAY
) & AR_PHY_RX_DELAY_DELAY
;
1714 if (IS_CHAN_B(chan
))
1715 synthDelay
= (4 * synthDelay
) / 22;
1719 udelay(synthDelay
+ BASE_ACTIVATE_DELAY
);
1721 REG_WRITE(ah
, AR_PHY_RFBUS_REQ
, 0);
1723 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1724 ath9k_hw_set_delta_slope(ah
, chan
);
1726 if (AR_SREV_9280_10_OR_LATER(ah
))
1727 ath9k_hw_9280_spur_mitigate(ah
, chan
);
1729 ath9k_hw_spur_mitigate(ah
, chan
);
1731 if (!chan
->oneTimeCalsDone
)
1732 chan
->oneTimeCalsDone
= true;
1737 static void ath9k_hw_9280_spur_mitigate(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1739 int bb_spur
= AR_NO_SPUR
;
1742 int bb_spur_off
, spur_subchannel_sd
;
1744 int spur_delta_phase
;
1746 int upper
, lower
, cur_vit_mask
;
1749 int pilot_mask_reg
[4] = { AR_PHY_TIMING7
, AR_PHY_TIMING8
,
1750 AR_PHY_PILOT_MASK_01_30
, AR_PHY_PILOT_MASK_31_60
1752 int chan_mask_reg
[4] = { AR_PHY_TIMING9
, AR_PHY_TIMING10
,
1753 AR_PHY_CHANNEL_MASK_01_30
, AR_PHY_CHANNEL_MASK_31_60
1755 int inc
[4] = { 0, 100, 0, 0 };
1756 struct chan_centers centers
;
1763 bool is2GHz
= IS_CHAN_2GHZ(chan
);
1765 memset(&mask_m
, 0, sizeof(int8_t) * 123);
1766 memset(&mask_p
, 0, sizeof(int8_t) * 123);
1768 ath9k_hw_get_channel_centers(ah
, chan
, ¢ers
);
1769 freq
= centers
.synth_center
;
1771 ah
->config
.spurmode
= SPUR_ENABLE_EEPROM
;
1772 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
1773 cur_bb_spur
= ah
->eep_ops
->get_spur_channel(ah
, i
, is2GHz
);
1776 cur_bb_spur
= (cur_bb_spur
/ 10) + AR_BASE_FREQ_2GHZ
;
1778 cur_bb_spur
= (cur_bb_spur
/ 10) + AR_BASE_FREQ_5GHZ
;
1780 if (AR_NO_SPUR
== cur_bb_spur
)
1782 cur_bb_spur
= cur_bb_spur
- freq
;
1784 if (IS_CHAN_HT40(chan
)) {
1785 if ((cur_bb_spur
> -AR_SPUR_FEEQ_BOUND_HT40
) &&
1786 (cur_bb_spur
< AR_SPUR_FEEQ_BOUND_HT40
)) {
1787 bb_spur
= cur_bb_spur
;
1790 } else if ((cur_bb_spur
> -AR_SPUR_FEEQ_BOUND_HT20
) &&
1791 (cur_bb_spur
< AR_SPUR_FEEQ_BOUND_HT20
)) {
1792 bb_spur
= cur_bb_spur
;
1797 if (AR_NO_SPUR
== bb_spur
) {
1798 REG_CLR_BIT(ah
, AR_PHY_FORCE_CLKEN_CCK
,
1799 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX
);
1802 REG_CLR_BIT(ah
, AR_PHY_FORCE_CLKEN_CCK
,
1803 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX
);
1806 bin
= bb_spur
* 320;
1808 tmp
= REG_READ(ah
, AR_PHY_TIMING_CTRL4(0));
1810 newVal
= tmp
| (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
|
1811 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
|
1812 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
|
1813 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
);
1814 REG_WRITE(ah
, AR_PHY_TIMING_CTRL4(0), newVal
);
1816 newVal
= (AR_PHY_SPUR_REG_MASK_RATE_CNTL
|
1817 AR_PHY_SPUR_REG_ENABLE_MASK_PPM
|
1818 AR_PHY_SPUR_REG_MASK_RATE_SELECT
|
1819 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
|
1820 SM(SPUR_RSSI_THRESH
, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
));
1821 REG_WRITE(ah
, AR_PHY_SPUR_REG
, newVal
);
1823 if (IS_CHAN_HT40(chan
)) {
1825 spur_subchannel_sd
= 1;
1826 bb_spur_off
= bb_spur
+ 10;
1828 spur_subchannel_sd
= 0;
1829 bb_spur_off
= bb_spur
- 10;
1832 spur_subchannel_sd
= 0;
1833 bb_spur_off
= bb_spur
;
1836 if (IS_CHAN_HT40(chan
))
1838 ((bb_spur
* 262144) /
1839 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE
;
1842 ((bb_spur
* 524288) /
1843 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE
;
1845 denominator
= IS_CHAN_2GHZ(chan
) ? 44 : 40;
1846 spur_freq_sd
= ((bb_spur_off
* 2048) / denominator
) & 0x3ff;
1848 newVal
= (AR_PHY_TIMING11_USE_SPUR_IN_AGC
|
1849 SM(spur_freq_sd
, AR_PHY_TIMING11_SPUR_FREQ_SD
) |
1850 SM(spur_delta_phase
, AR_PHY_TIMING11_SPUR_DELTA_PHASE
));
1851 REG_WRITE(ah
, AR_PHY_TIMING11
, newVal
);
1853 newVal
= spur_subchannel_sd
<< AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S
;
1854 REG_WRITE(ah
, AR_PHY_SFCORR_EXT
, newVal
);
1860 for (i
= 0; i
< 4; i
++) {
1864 for (bp
= 0; bp
< 30; bp
++) {
1865 if ((cur_bin
> lower
) && (cur_bin
< upper
)) {
1866 pilot_mask
= pilot_mask
| 0x1 << bp
;
1867 chan_mask
= chan_mask
| 0x1 << bp
;
1872 REG_WRITE(ah
, pilot_mask_reg
[i
], pilot_mask
);
1873 REG_WRITE(ah
, chan_mask_reg
[i
], chan_mask
);
1876 cur_vit_mask
= 6100;
1880 for (i
= 0; i
< 123; i
++) {
1881 if ((cur_vit_mask
> lower
) && (cur_vit_mask
< upper
)) {
1883 /* workaround for gcc bug #37014 */
1884 volatile int tmp_v
= abs(cur_vit_mask
- bin
);
1890 if (cur_vit_mask
< 0)
1891 mask_m
[abs(cur_vit_mask
/ 100)] = mask_amt
;
1893 mask_p
[cur_vit_mask
/ 100] = mask_amt
;
1895 cur_vit_mask
-= 100;
1898 tmp_mask
= (mask_m
[46] << 30) | (mask_m
[47] << 28)
1899 | (mask_m
[48] << 26) | (mask_m
[49] << 24)
1900 | (mask_m
[50] << 22) | (mask_m
[51] << 20)
1901 | (mask_m
[52] << 18) | (mask_m
[53] << 16)
1902 | (mask_m
[54] << 14) | (mask_m
[55] << 12)
1903 | (mask_m
[56] << 10) | (mask_m
[57] << 8)
1904 | (mask_m
[58] << 6) | (mask_m
[59] << 4)
1905 | (mask_m
[60] << 2) | (mask_m
[61] << 0);
1906 REG_WRITE(ah
, AR_PHY_BIN_MASK_1
, tmp_mask
);
1907 REG_WRITE(ah
, AR_PHY_VIT_MASK2_M_46_61
, tmp_mask
);
1909 tmp_mask
= (mask_m
[31] << 28)
1910 | (mask_m
[32] << 26) | (mask_m
[33] << 24)
1911 | (mask_m
[34] << 22) | (mask_m
[35] << 20)
1912 | (mask_m
[36] << 18) | (mask_m
[37] << 16)
1913 | (mask_m
[48] << 14) | (mask_m
[39] << 12)
1914 | (mask_m
[40] << 10) | (mask_m
[41] << 8)
1915 | (mask_m
[42] << 6) | (mask_m
[43] << 4)
1916 | (mask_m
[44] << 2) | (mask_m
[45] << 0);
1917 REG_WRITE(ah
, AR_PHY_BIN_MASK_2
, tmp_mask
);
1918 REG_WRITE(ah
, AR_PHY_MASK2_M_31_45
, tmp_mask
);
1920 tmp_mask
= (mask_m
[16] << 30) | (mask_m
[16] << 28)
1921 | (mask_m
[18] << 26) | (mask_m
[18] << 24)
1922 | (mask_m
[20] << 22) | (mask_m
[20] << 20)
1923 | (mask_m
[22] << 18) | (mask_m
[22] << 16)
1924 | (mask_m
[24] << 14) | (mask_m
[24] << 12)
1925 | (mask_m
[25] << 10) | (mask_m
[26] << 8)
1926 | (mask_m
[27] << 6) | (mask_m
[28] << 4)
1927 | (mask_m
[29] << 2) | (mask_m
[30] << 0);
1928 REG_WRITE(ah
, AR_PHY_BIN_MASK_3
, tmp_mask
);
1929 REG_WRITE(ah
, AR_PHY_MASK2_M_16_30
, tmp_mask
);
1931 tmp_mask
= (mask_m
[0] << 30) | (mask_m
[1] << 28)
1932 | (mask_m
[2] << 26) | (mask_m
[3] << 24)
1933 | (mask_m
[4] << 22) | (mask_m
[5] << 20)
1934 | (mask_m
[6] << 18) | (mask_m
[7] << 16)
1935 | (mask_m
[8] << 14) | (mask_m
[9] << 12)
1936 | (mask_m
[10] << 10) | (mask_m
[11] << 8)
1937 | (mask_m
[12] << 6) | (mask_m
[13] << 4)
1938 | (mask_m
[14] << 2) | (mask_m
[15] << 0);
1939 REG_WRITE(ah
, AR_PHY_MASK_CTL
, tmp_mask
);
1940 REG_WRITE(ah
, AR_PHY_MASK2_M_00_15
, tmp_mask
);
1942 tmp_mask
= (mask_p
[15] << 28)
1943 | (mask_p
[14] << 26) | (mask_p
[13] << 24)
1944 | (mask_p
[12] << 22) | (mask_p
[11] << 20)
1945 | (mask_p
[10] << 18) | (mask_p
[9] << 16)
1946 | (mask_p
[8] << 14) | (mask_p
[7] << 12)
1947 | (mask_p
[6] << 10) | (mask_p
[5] << 8)
1948 | (mask_p
[4] << 6) | (mask_p
[3] << 4)
1949 | (mask_p
[2] << 2) | (mask_p
[1] << 0);
1950 REG_WRITE(ah
, AR_PHY_BIN_MASK2_1
, tmp_mask
);
1951 REG_WRITE(ah
, AR_PHY_MASK2_P_15_01
, tmp_mask
);
1953 tmp_mask
= (mask_p
[30] << 28)
1954 | (mask_p
[29] << 26) | (mask_p
[28] << 24)
1955 | (mask_p
[27] << 22) | (mask_p
[26] << 20)
1956 | (mask_p
[25] << 18) | (mask_p
[24] << 16)
1957 | (mask_p
[23] << 14) | (mask_p
[22] << 12)
1958 | (mask_p
[21] << 10) | (mask_p
[20] << 8)
1959 | (mask_p
[19] << 6) | (mask_p
[18] << 4)
1960 | (mask_p
[17] << 2) | (mask_p
[16] << 0);
1961 REG_WRITE(ah
, AR_PHY_BIN_MASK2_2
, tmp_mask
);
1962 REG_WRITE(ah
, AR_PHY_MASK2_P_30_16
, tmp_mask
);
1964 tmp_mask
= (mask_p
[45] << 28)
1965 | (mask_p
[44] << 26) | (mask_p
[43] << 24)
1966 | (mask_p
[42] << 22) | (mask_p
[41] << 20)
1967 | (mask_p
[40] << 18) | (mask_p
[39] << 16)
1968 | (mask_p
[38] << 14) | (mask_p
[37] << 12)
1969 | (mask_p
[36] << 10) | (mask_p
[35] << 8)
1970 | (mask_p
[34] << 6) | (mask_p
[33] << 4)
1971 | (mask_p
[32] << 2) | (mask_p
[31] << 0);
1972 REG_WRITE(ah
, AR_PHY_BIN_MASK2_3
, tmp_mask
);
1973 REG_WRITE(ah
, AR_PHY_MASK2_P_45_31
, tmp_mask
);
1975 tmp_mask
= (mask_p
[61] << 30) | (mask_p
[60] << 28)
1976 | (mask_p
[59] << 26) | (mask_p
[58] << 24)
1977 | (mask_p
[57] << 22) | (mask_p
[56] << 20)
1978 | (mask_p
[55] << 18) | (mask_p
[54] << 16)
1979 | (mask_p
[53] << 14) | (mask_p
[52] << 12)
1980 | (mask_p
[51] << 10) | (mask_p
[50] << 8)
1981 | (mask_p
[49] << 6) | (mask_p
[48] << 4)
1982 | (mask_p
[47] << 2) | (mask_p
[46] << 0);
1983 REG_WRITE(ah
, AR_PHY_BIN_MASK2_4
, tmp_mask
);
1984 REG_WRITE(ah
, AR_PHY_MASK2_P_61_45
, tmp_mask
);
1987 static void ath9k_hw_spur_mitigate(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
1989 int bb_spur
= AR_NO_SPUR
;
1992 int spur_delta_phase
;
1994 int upper
, lower
, cur_vit_mask
;
1997 int pilot_mask_reg
[4] = { AR_PHY_TIMING7
, AR_PHY_TIMING8
,
1998 AR_PHY_PILOT_MASK_01_30
, AR_PHY_PILOT_MASK_31_60
2000 int chan_mask_reg
[4] = { AR_PHY_TIMING9
, AR_PHY_TIMING10
,
2001 AR_PHY_CHANNEL_MASK_01_30
, AR_PHY_CHANNEL_MASK_31_60
2003 int inc
[4] = { 0, 100, 0, 0 };
2010 bool is2GHz
= IS_CHAN_2GHZ(chan
);
2012 memset(&mask_m
, 0, sizeof(int8_t) * 123);
2013 memset(&mask_p
, 0, sizeof(int8_t) * 123);
2015 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
2016 cur_bb_spur
= ah
->eep_ops
->get_spur_channel(ah
, i
, is2GHz
);
2017 if (AR_NO_SPUR
== cur_bb_spur
)
2019 cur_bb_spur
= cur_bb_spur
- (chan
->channel
* 10);
2020 if ((cur_bb_spur
> -95) && (cur_bb_spur
< 95)) {
2021 bb_spur
= cur_bb_spur
;
2026 if (AR_NO_SPUR
== bb_spur
)
2031 tmp
= REG_READ(ah
, AR_PHY_TIMING_CTRL4(0));
2032 new = tmp
| (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI
|
2033 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER
|
2034 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK
|
2035 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK
);
2037 REG_WRITE(ah
, AR_PHY_TIMING_CTRL4(0), new);
2039 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL
|
2040 AR_PHY_SPUR_REG_ENABLE_MASK_PPM
|
2041 AR_PHY_SPUR_REG_MASK_RATE_SELECT
|
2042 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI
|
2043 SM(SPUR_RSSI_THRESH
, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH
));
2044 REG_WRITE(ah
, AR_PHY_SPUR_REG
, new);
2046 spur_delta_phase
= ((bb_spur
* 524288) / 100) &
2047 AR_PHY_TIMING11_SPUR_DELTA_PHASE
;
2049 denominator
= IS_CHAN_2GHZ(chan
) ? 440 : 400;
2050 spur_freq_sd
= ((bb_spur
* 2048) / denominator
) & 0x3ff;
2052 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC
|
2053 SM(spur_freq_sd
, AR_PHY_TIMING11_SPUR_FREQ_SD
) |
2054 SM(spur_delta_phase
, AR_PHY_TIMING11_SPUR_DELTA_PHASE
));
2055 REG_WRITE(ah
, AR_PHY_TIMING11
, new);
2061 for (i
= 0; i
< 4; i
++) {
2065 for (bp
= 0; bp
< 30; bp
++) {
2066 if ((cur_bin
> lower
) && (cur_bin
< upper
)) {
2067 pilot_mask
= pilot_mask
| 0x1 << bp
;
2068 chan_mask
= chan_mask
| 0x1 << bp
;
2073 REG_WRITE(ah
, pilot_mask_reg
[i
], pilot_mask
);
2074 REG_WRITE(ah
, chan_mask_reg
[i
], chan_mask
);
2077 cur_vit_mask
= 6100;
2081 for (i
= 0; i
< 123; i
++) {
2082 if ((cur_vit_mask
> lower
) && (cur_vit_mask
< upper
)) {
2084 /* workaround for gcc bug #37014 */
2085 volatile int tmp_v
= abs(cur_vit_mask
- bin
);
2091 if (cur_vit_mask
< 0)
2092 mask_m
[abs(cur_vit_mask
/ 100)] = mask_amt
;
2094 mask_p
[cur_vit_mask
/ 100] = mask_amt
;
2096 cur_vit_mask
-= 100;
2099 tmp_mask
= (mask_m
[46] << 30) | (mask_m
[47] << 28)
2100 | (mask_m
[48] << 26) | (mask_m
[49] << 24)
2101 | (mask_m
[50] << 22) | (mask_m
[51] << 20)
2102 | (mask_m
[52] << 18) | (mask_m
[53] << 16)
2103 | (mask_m
[54] << 14) | (mask_m
[55] << 12)
2104 | (mask_m
[56] << 10) | (mask_m
[57] << 8)
2105 | (mask_m
[58] << 6) | (mask_m
[59] << 4)
2106 | (mask_m
[60] << 2) | (mask_m
[61] << 0);
2107 REG_WRITE(ah
, AR_PHY_BIN_MASK_1
, tmp_mask
);
2108 REG_WRITE(ah
, AR_PHY_VIT_MASK2_M_46_61
, tmp_mask
);
2110 tmp_mask
= (mask_m
[31] << 28)
2111 | (mask_m
[32] << 26) | (mask_m
[33] << 24)
2112 | (mask_m
[34] << 22) | (mask_m
[35] << 20)
2113 | (mask_m
[36] << 18) | (mask_m
[37] << 16)
2114 | (mask_m
[48] << 14) | (mask_m
[39] << 12)
2115 | (mask_m
[40] << 10) | (mask_m
[41] << 8)
2116 | (mask_m
[42] << 6) | (mask_m
[43] << 4)
2117 | (mask_m
[44] << 2) | (mask_m
[45] << 0);
2118 REG_WRITE(ah
, AR_PHY_BIN_MASK_2
, tmp_mask
);
2119 REG_WRITE(ah
, AR_PHY_MASK2_M_31_45
, tmp_mask
);
2121 tmp_mask
= (mask_m
[16] << 30) | (mask_m
[16] << 28)
2122 | (mask_m
[18] << 26) | (mask_m
[18] << 24)
2123 | (mask_m
[20] << 22) | (mask_m
[20] << 20)
2124 | (mask_m
[22] << 18) | (mask_m
[22] << 16)
2125 | (mask_m
[24] << 14) | (mask_m
[24] << 12)
2126 | (mask_m
[25] << 10) | (mask_m
[26] << 8)
2127 | (mask_m
[27] << 6) | (mask_m
[28] << 4)
2128 | (mask_m
[29] << 2) | (mask_m
[30] << 0);
2129 REG_WRITE(ah
, AR_PHY_BIN_MASK_3
, tmp_mask
);
2130 REG_WRITE(ah
, AR_PHY_MASK2_M_16_30
, tmp_mask
);
2132 tmp_mask
= (mask_m
[0] << 30) | (mask_m
[1] << 28)
2133 | (mask_m
[2] << 26) | (mask_m
[3] << 24)
2134 | (mask_m
[4] << 22) | (mask_m
[5] << 20)
2135 | (mask_m
[6] << 18) | (mask_m
[7] << 16)
2136 | (mask_m
[8] << 14) | (mask_m
[9] << 12)
2137 | (mask_m
[10] << 10) | (mask_m
[11] << 8)
2138 | (mask_m
[12] << 6) | (mask_m
[13] << 4)
2139 | (mask_m
[14] << 2) | (mask_m
[15] << 0);
2140 REG_WRITE(ah
, AR_PHY_MASK_CTL
, tmp_mask
);
2141 REG_WRITE(ah
, AR_PHY_MASK2_M_00_15
, tmp_mask
);
2143 tmp_mask
= (mask_p
[15] << 28)
2144 | (mask_p
[14] << 26) | (mask_p
[13] << 24)
2145 | (mask_p
[12] << 22) | (mask_p
[11] << 20)
2146 | (mask_p
[10] << 18) | (mask_p
[9] << 16)
2147 | (mask_p
[8] << 14) | (mask_p
[7] << 12)
2148 | (mask_p
[6] << 10) | (mask_p
[5] << 8)
2149 | (mask_p
[4] << 6) | (mask_p
[3] << 4)
2150 | (mask_p
[2] << 2) | (mask_p
[1] << 0);
2151 REG_WRITE(ah
, AR_PHY_BIN_MASK2_1
, tmp_mask
);
2152 REG_WRITE(ah
, AR_PHY_MASK2_P_15_01
, tmp_mask
);
2154 tmp_mask
= (mask_p
[30] << 28)
2155 | (mask_p
[29] << 26) | (mask_p
[28] << 24)
2156 | (mask_p
[27] << 22) | (mask_p
[26] << 20)
2157 | (mask_p
[25] << 18) | (mask_p
[24] << 16)
2158 | (mask_p
[23] << 14) | (mask_p
[22] << 12)
2159 | (mask_p
[21] << 10) | (mask_p
[20] << 8)
2160 | (mask_p
[19] << 6) | (mask_p
[18] << 4)
2161 | (mask_p
[17] << 2) | (mask_p
[16] << 0);
2162 REG_WRITE(ah
, AR_PHY_BIN_MASK2_2
, tmp_mask
);
2163 REG_WRITE(ah
, AR_PHY_MASK2_P_30_16
, tmp_mask
);
2165 tmp_mask
= (mask_p
[45] << 28)
2166 | (mask_p
[44] << 26) | (mask_p
[43] << 24)
2167 | (mask_p
[42] << 22) | (mask_p
[41] << 20)
2168 | (mask_p
[40] << 18) | (mask_p
[39] << 16)
2169 | (mask_p
[38] << 14) | (mask_p
[37] << 12)
2170 | (mask_p
[36] << 10) | (mask_p
[35] << 8)
2171 | (mask_p
[34] << 6) | (mask_p
[33] << 4)
2172 | (mask_p
[32] << 2) | (mask_p
[31] << 0);
2173 REG_WRITE(ah
, AR_PHY_BIN_MASK2_3
, tmp_mask
);
2174 REG_WRITE(ah
, AR_PHY_MASK2_P_45_31
, tmp_mask
);
2176 tmp_mask
= (mask_p
[61] << 30) | (mask_p
[60] << 28)
2177 | (mask_p
[59] << 26) | (mask_p
[58] << 24)
2178 | (mask_p
[57] << 22) | (mask_p
[56] << 20)
2179 | (mask_p
[55] << 18) | (mask_p
[54] << 16)
2180 | (mask_p
[53] << 14) | (mask_p
[52] << 12)
2181 | (mask_p
[51] << 10) | (mask_p
[50] << 8)
2182 | (mask_p
[49] << 6) | (mask_p
[48] << 4)
2183 | (mask_p
[47] << 2) | (mask_p
[46] << 0);
2184 REG_WRITE(ah
, AR_PHY_BIN_MASK2_4
, tmp_mask
);
2185 REG_WRITE(ah
, AR_PHY_MASK2_P_61_45
, tmp_mask
);
2188 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
2189 bool bChannelChange
)
2192 struct ath_softc
*sc
= ah
->ah_sc
;
2193 struct ath9k_channel
*curchan
= ah
->curchan
;
2196 int i
, rx_chainmask
, r
;
2198 ah
->extprotspacing
= sc
->ht_extprotspacing
;
2199 ah
->txchainmask
= sc
->tx_chainmask
;
2200 ah
->rxchainmask
= sc
->rx_chainmask
;
2202 if (AR_SREV_9285(ah
)) {
2203 ah
->txchainmask
&= 0x1;
2204 ah
->rxchainmask
&= 0x1;
2205 } else if (AR_SREV_9280(ah
)) {
2206 ah
->txchainmask
&= 0x3;
2207 ah
->rxchainmask
&= 0x3;
2210 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
2214 ath9k_hw_getnf(ah
, curchan
);
2216 if (bChannelChange
&&
2217 (ah
->chip_fullsleep
!= true) &&
2218 (ah
->curchan
!= NULL
) &&
2219 (chan
->channel
!= ah
->curchan
->channel
) &&
2220 ((chan
->channelFlags
& CHANNEL_ALL
) ==
2221 (ah
->curchan
->channelFlags
& CHANNEL_ALL
)) &&
2222 (!AR_SREV_9280(ah
) || (!IS_CHAN_A_5MHZ_SPACED(chan
) &&
2223 !IS_CHAN_A_5MHZ_SPACED(ah
->curchan
)))) {
2225 if (ath9k_hw_channel_change(ah
, chan
, sc
->tx_chan_width
)) {
2226 ath9k_hw_loadnf(ah
, ah
->curchan
);
2227 ath9k_hw_start_nfcal(ah
);
2232 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
2233 if (saveDefAntenna
== 0)
2236 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
2238 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
2239 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
2240 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
2242 ath9k_hw_mark_phy_inactive(ah
);
2244 if (!ath9k_hw_chip_reset(ah
, chan
)) {
2245 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "chip reset failed\n");
2249 if (AR_SREV_9280_10_OR_LATER(ah
))
2250 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
2252 r
= ath9k_hw_process_ini(ah
, chan
, sc
->tx_chan_width
);
2256 /* Setup MFP options for CCMP */
2257 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2258 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2259 * frames when constructing CCMP AAD. */
2260 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
2262 ah
->sw_mgmt_crypto
= false;
2263 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
2264 /* Disable hardware crypto for management frames */
2265 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
2266 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
2267 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
2268 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
2269 ah
->sw_mgmt_crypto
= true;
2271 ah
->sw_mgmt_crypto
= true;
2273 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
2274 ath9k_hw_set_delta_slope(ah
, chan
);
2276 if (AR_SREV_9280_10_OR_LATER(ah
))
2277 ath9k_hw_9280_spur_mitigate(ah
, chan
);
2279 ath9k_hw_spur_mitigate(ah
, chan
);
2281 ah
->eep_ops
->set_board_values(ah
, chan
);
2283 ath9k_hw_decrease_chain_power(ah
, chan
);
2285 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(ah
->macaddr
));
2286 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(ah
->macaddr
+ 4)
2288 | AR_STA_ID1_RTS_USE_DEF
2290 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
2291 | ah
->sta_id1_defaults
);
2292 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2294 REG_WRITE(ah
, AR_BSSMSKL
, get_unaligned_le32(sc
->bssidmask
));
2295 REG_WRITE(ah
, AR_BSSMSKU
, get_unaligned_le16(sc
->bssidmask
+ 4));
2297 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
2299 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(sc
->curbssid
));
2300 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(sc
->curbssid
+ 4) |
2301 ((sc
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
2303 REG_WRITE(ah
, AR_ISR
, ~0);
2305 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
2307 if (AR_SREV_9280_10_OR_LATER(ah
)) {
2308 if (!(ath9k_hw_ar9280_set_channel(ah
, chan
)))
2311 if (!(ath9k_hw_set_channel(ah
, chan
)))
2315 for (i
= 0; i
< AR_NUM_DCU
; i
++)
2316 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
2319 for (i
= 0; i
< ah
->caps
.total_queues
; i
++)
2320 ath9k_hw_resettxqueue(ah
, i
);
2322 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
2323 ath9k_hw_init_qos(ah
);
2325 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2326 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
2327 ath9k_enable_rfkill(ah
);
2329 ath9k_hw_init_user_settings(ah
);
2331 REG_WRITE(ah
, AR_STA_ID1
,
2332 REG_READ(ah
, AR_STA_ID1
) | AR_STA_ID1_PRESERVE_SEQNUM
);
2334 ath9k_hw_set_dma(ah
);
2336 REG_WRITE(ah
, AR_OBS
, 8);
2338 if (ah
->intr_mitigation
) {
2340 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
2341 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
2344 ath9k_hw_init_bb(ah
, chan
);
2346 if (!ath9k_hw_init_cal(ah
, chan
))
2349 rx_chainmask
= ah
->rxchainmask
;
2350 if ((rx_chainmask
== 0x5) || (rx_chainmask
== 0x3)) {
2351 REG_WRITE(ah
, AR_PHY_RX_CHAINMASK
, rx_chainmask
);
2352 REG_WRITE(ah
, AR_PHY_CAL_CHAINMASK
, rx_chainmask
);
2355 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
2357 if (AR_SREV_9100(ah
)) {
2359 mask
= REG_READ(ah
, AR_CFG
);
2360 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
2361 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
,
2362 "CFG Byte Swap Set 0x%x\n", mask
);
2365 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
2366 REG_WRITE(ah
, AR_CFG
, mask
);
2367 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
,
2368 "Setting CFG 0x%x\n", REG_READ(ah
, AR_CFG
));
2372 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
2379 /************************/
2380 /* Key Cache Management */
2381 /************************/
2383 bool ath9k_hw_keyreset(struct ath_hw
*ah
, u16 entry
)
2387 if (entry
>= ah
->caps
.keycache_size
) {
2388 DPRINTF(ah
->ah_sc
, ATH_DBG_KEYCACHE
,
2389 "entry %u out of range\n", entry
);
2393 keyType
= REG_READ(ah
, AR_KEYTABLE_TYPE(entry
));
2395 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), 0);
2396 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), 0);
2397 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), 0);
2398 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), 0);
2399 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), 0);
2400 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), AR_KEYTABLE_TYPE_CLR
);
2401 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), 0);
2402 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), 0);
2404 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2405 u16 micentry
= entry
+ 64;
2407 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), 0);
2408 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2409 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), 0);
2410 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2414 if (ah
->curchan
== NULL
)
2420 bool ath9k_hw_keysetmac(struct ath_hw
*ah
, u16 entry
, const u8
*mac
)
2424 if (entry
>= ah
->caps
.keycache_size
) {
2425 DPRINTF(ah
->ah_sc
, ATH_DBG_KEYCACHE
,
2426 "entry %u out of range\n", entry
);
2431 macHi
= (mac
[5] << 8) | mac
[4];
2432 macLo
= (mac
[3] << 24) |
2437 macLo
|= (macHi
& 1) << 31;
2442 REG_WRITE(ah
, AR_KEYTABLE_MAC0(entry
), macLo
);
2443 REG_WRITE(ah
, AR_KEYTABLE_MAC1(entry
), macHi
| AR_KEYTABLE_VALID
);
2448 bool ath9k_hw_set_keycache_entry(struct ath_hw
*ah
, u16 entry
,
2449 const struct ath9k_keyval
*k
,
2452 const struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2453 u32 key0
, key1
, key2
, key3
, key4
;
2456 if (entry
>= pCap
->keycache_size
) {
2457 DPRINTF(ah
->ah_sc
, ATH_DBG_KEYCACHE
,
2458 "entry %u out of range\n", entry
);
2462 switch (k
->kv_type
) {
2463 case ATH9K_CIPHER_AES_OCB
:
2464 keyType
= AR_KEYTABLE_TYPE_AES
;
2466 case ATH9K_CIPHER_AES_CCM
:
2467 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_CIPHER_AESCCM
)) {
2468 DPRINTF(ah
->ah_sc
, ATH_DBG_KEYCACHE
,
2469 "AES-CCM not supported by mac rev 0x%x\n",
2470 ah
->hw_version
.macRev
);
2473 keyType
= AR_KEYTABLE_TYPE_CCM
;
2475 case ATH9K_CIPHER_TKIP
:
2476 keyType
= AR_KEYTABLE_TYPE_TKIP
;
2477 if (ATH9K_IS_MIC_ENABLED(ah
)
2478 && entry
+ 64 >= pCap
->keycache_size
) {
2479 DPRINTF(ah
->ah_sc
, ATH_DBG_KEYCACHE
,
2480 "entry %u inappropriate for TKIP\n", entry
);
2484 case ATH9K_CIPHER_WEP
:
2485 if (k
->kv_len
< LEN_WEP40
) {
2486 DPRINTF(ah
->ah_sc
, ATH_DBG_KEYCACHE
,
2487 "WEP key length %u too small\n", k
->kv_len
);
2490 if (k
->kv_len
<= LEN_WEP40
)
2491 keyType
= AR_KEYTABLE_TYPE_40
;
2492 else if (k
->kv_len
<= LEN_WEP104
)
2493 keyType
= AR_KEYTABLE_TYPE_104
;
2495 keyType
= AR_KEYTABLE_TYPE_128
;
2497 case ATH9K_CIPHER_CLR
:
2498 keyType
= AR_KEYTABLE_TYPE_CLR
;
2501 DPRINTF(ah
->ah_sc
, ATH_DBG_KEYCACHE
,
2502 "cipher %u not supported\n", k
->kv_type
);
2506 key0
= get_unaligned_le32(k
->kv_val
+ 0);
2507 key1
= get_unaligned_le16(k
->kv_val
+ 4);
2508 key2
= get_unaligned_le32(k
->kv_val
+ 6);
2509 key3
= get_unaligned_le16(k
->kv_val
+ 10);
2510 key4
= get_unaligned_le32(k
->kv_val
+ 12);
2511 if (k
->kv_len
<= LEN_WEP104
)
2515 * Note: Key cache registers access special memory area that requires
2516 * two 32-bit writes to actually update the values in the internal
2517 * memory. Consequently, the exact order and pairs used here must be
2521 if (keyType
== AR_KEYTABLE_TYPE_TKIP
&& ATH9K_IS_MIC_ENABLED(ah
)) {
2522 u16 micentry
= entry
+ 64;
2525 * Write inverted key[47:0] first to avoid Michael MIC errors
2526 * on frames that could be sent or received at the same time.
2527 * The correct key will be written in the end once everything
2530 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), ~key0
);
2531 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), ~key1
);
2533 /* Write key[95:48] */
2534 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2535 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2537 /* Write key[127:96] and key type */
2538 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2539 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2541 /* Write MAC address for the entry */
2542 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2544 if (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) {
2546 * TKIP uses two key cache entries:
2547 * Michael MIC TX/RX keys in the same key cache entry
2548 * (idx = main index + 64):
2549 * key0 [31:0] = RX key [31:0]
2550 * key1 [15:0] = TX key [31:16]
2551 * key1 [31:16] = reserved
2552 * key2 [31:0] = RX key [63:32]
2553 * key3 [15:0] = TX key [15:0]
2554 * key3 [31:16] = reserved
2555 * key4 [31:0] = TX key [63:32]
2557 u32 mic0
, mic1
, mic2
, mic3
, mic4
;
2559 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2560 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2561 mic1
= get_unaligned_le16(k
->kv_txmic
+ 2) & 0xffff;
2562 mic3
= get_unaligned_le16(k
->kv_txmic
+ 0) & 0xffff;
2563 mic4
= get_unaligned_le32(k
->kv_txmic
+ 4);
2565 /* Write RX[31:0] and TX[31:16] */
2566 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2567 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), mic1
);
2569 /* Write RX[63:32] and TX[15:0] */
2570 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2571 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), mic3
);
2573 /* Write TX[63:32] and keyType(reserved) */
2574 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), mic4
);
2575 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2576 AR_KEYTABLE_TYPE_CLR
);
2580 * TKIP uses four key cache entries (two for group
2582 * Michael MIC TX/RX keys are in different key cache
2583 * entries (idx = main index + 64 for TX and
2584 * main index + 32 + 96 for RX):
2585 * key0 [31:0] = TX/RX MIC key [31:0]
2586 * key1 [31:0] = reserved
2587 * key2 [31:0] = TX/RX MIC key [63:32]
2588 * key3 [31:0] = reserved
2589 * key4 [31:0] = reserved
2591 * Upper layer code will call this function separately
2592 * for TX and RX keys when these registers offsets are
2597 mic0
= get_unaligned_le32(k
->kv_mic
+ 0);
2598 mic2
= get_unaligned_le32(k
->kv_mic
+ 4);
2600 /* Write MIC key[31:0] */
2601 REG_WRITE(ah
, AR_KEYTABLE_KEY0(micentry
), mic0
);
2602 REG_WRITE(ah
, AR_KEYTABLE_KEY1(micentry
), 0);
2604 /* Write MIC key[63:32] */
2605 REG_WRITE(ah
, AR_KEYTABLE_KEY2(micentry
), mic2
);
2606 REG_WRITE(ah
, AR_KEYTABLE_KEY3(micentry
), 0);
2608 /* Write TX[63:32] and keyType(reserved) */
2609 REG_WRITE(ah
, AR_KEYTABLE_KEY4(micentry
), 0);
2610 REG_WRITE(ah
, AR_KEYTABLE_TYPE(micentry
),
2611 AR_KEYTABLE_TYPE_CLR
);
2614 /* MAC address registers are reserved for the MIC entry */
2615 REG_WRITE(ah
, AR_KEYTABLE_MAC0(micentry
), 0);
2616 REG_WRITE(ah
, AR_KEYTABLE_MAC1(micentry
), 0);
2619 * Write the correct (un-inverted) key[47:0] last to enable
2620 * TKIP now that all other registers are set with correct
2623 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2624 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2626 /* Write key[47:0] */
2627 REG_WRITE(ah
, AR_KEYTABLE_KEY0(entry
), key0
);
2628 REG_WRITE(ah
, AR_KEYTABLE_KEY1(entry
), key1
);
2630 /* Write key[95:48] */
2631 REG_WRITE(ah
, AR_KEYTABLE_KEY2(entry
), key2
);
2632 REG_WRITE(ah
, AR_KEYTABLE_KEY3(entry
), key3
);
2634 /* Write key[127:96] and key type */
2635 REG_WRITE(ah
, AR_KEYTABLE_KEY4(entry
), key4
);
2636 REG_WRITE(ah
, AR_KEYTABLE_TYPE(entry
), keyType
);
2638 /* Write MAC address for the entry */
2639 (void) ath9k_hw_keysetmac(ah
, entry
, mac
);
2645 bool ath9k_hw_keyisvalid(struct ath_hw
*ah
, u16 entry
)
2647 if (entry
< ah
->caps
.keycache_size
) {
2648 u32 val
= REG_READ(ah
, AR_KEYTABLE_MAC1(entry
));
2649 if (val
& AR_KEYTABLE_VALID
)
2655 /******************************/
2656 /* Power Management (Chipset) */
2657 /******************************/
2659 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
2661 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2663 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2664 AR_RTC_FORCE_WAKE_EN
);
2665 if (!AR_SREV_9100(ah
))
2666 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
2668 REG_CLR_BIT(ah
, (AR_RTC_RESET
),
2673 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
2675 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2677 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2679 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2680 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
2681 AR_RTC_FORCE_WAKE_ON_INT
);
2683 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
2684 AR_RTC_FORCE_WAKE_EN
);
2689 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
2695 if ((REG_READ(ah
, AR_RTC_STATUS
) &
2696 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
2697 if (ath9k_hw_set_reset_reg(ah
,
2698 ATH9K_RESET_POWER_ON
) != true) {
2702 if (AR_SREV_9100(ah
))
2703 REG_SET_BIT(ah
, AR_RTC_RESET
,
2706 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2707 AR_RTC_FORCE_WAKE_EN
);
2710 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
2711 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
2712 if (val
== AR_RTC_STATUS_ON
)
2715 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
2716 AR_RTC_FORCE_WAKE_EN
);
2719 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
,
2720 "Failed to wakeup in %uus\n", POWER_UP_TIME
/ 20);
2725 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
2730 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
2732 int status
= true, setChip
= true;
2733 static const char *modes
[] = {
2740 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
, "%s -> %s (%s)\n",
2741 modes
[ah
->power_mode
], modes
[mode
],
2742 setChip
? "set chip " : "");
2745 case ATH9K_PM_AWAKE
:
2746 status
= ath9k_hw_set_power_awake(ah
, setChip
);
2748 case ATH9K_PM_FULL_SLEEP
:
2749 ath9k_set_power_sleep(ah
, setChip
);
2750 ah
->chip_fullsleep
= true;
2752 case ATH9K_PM_NETWORK_SLEEP
:
2753 ath9k_set_power_network_sleep(ah
, setChip
);
2756 DPRINTF(ah
->ah_sc
, ATH_DBG_POWER_MGMT
,
2757 "Unknown power mode %u\n", mode
);
2760 ah
->power_mode
= mode
;
2766 * Helper for ASPM support.
2768 * Disable PLL when in L0s as well as receiver clock when in L1.
2769 * This power saving option must be enabled through the SerDes.
2771 * Programming the SerDes must go through the same 288 bit serial shift
2772 * register as the other analog registers. Hence the 9 writes.
2774 void ath9k_hw_configpcipowersave(struct ath_hw
*ah
, int restore
)
2778 if (ah
->is_pciexpress
!= true)
2781 /* Do not touch SerDes registers */
2782 if (ah
->config
.pcie_powersave_enable
== 2)
2785 /* Nothing to do on restore for 11N */
2789 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2791 * AR9280 2.0 or later chips use SerDes values from the
2792 * initvals.h initialized depending on chipset during
2793 * ath9k_hw_do_attach()
2795 for (i
= 0; i
< ah
->iniPcieSerdes
.ia_rows
; i
++) {
2796 REG_WRITE(ah
, INI_RA(&ah
->iniPcieSerdes
, i
, 0),
2797 INI_RA(&ah
->iniPcieSerdes
, i
, 1));
2799 } else if (AR_SREV_9280(ah
) &&
2800 (ah
->hw_version
.macRev
== AR_SREV_REVISION_9280_10
)) {
2801 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fd00);
2802 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2804 /* RX shut off when elecidle is asserted */
2805 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xa8000019);
2806 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x13160820);
2807 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980560);
2809 /* Shut off CLKREQ active in L1 */
2810 if (ah
->config
.pcie_clock_req
)
2811 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffc);
2813 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x401deffd);
2815 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2816 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2817 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00043007);
2819 /* Load the new settings */
2820 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2823 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
2824 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
2826 /* RX shut off when elecidle is asserted */
2827 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000039);
2828 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x53160824);
2829 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xe5980579);
2832 * Ignore ah->ah_config.pcie_clock_req setting for
2835 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x001defff);
2837 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
2838 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
2839 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e3007);
2841 /* Load the new settings */
2842 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
2847 /* set bit 19 to allow forcing of pcie core into L1 state */
2848 REG_SET_BIT(ah
, AR_PCIE_PM_CTRL
, AR_PCIE_PM_CTRL_ENA
);
2850 /* Several PCIe massages to ensure proper behaviour */
2851 if (ah
->config
.pcie_waen
) {
2852 REG_WRITE(ah
, AR_WA
, ah
->config
.pcie_waen
);
2854 if (AR_SREV_9285(ah
))
2855 REG_WRITE(ah
, AR_WA
, AR9285_WA_DEFAULT
);
2857 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2858 * otherwise card may disappear.
2860 else if (AR_SREV_9280(ah
))
2861 REG_WRITE(ah
, AR_WA
, AR9280_WA_DEFAULT
);
2863 REG_WRITE(ah
, AR_WA
, AR_WA_DEFAULT
);
2867 /**********************/
2868 /* Interrupt Handling */
2869 /**********************/
2871 bool ath9k_hw_intrpend(struct ath_hw
*ah
)
2875 if (AR_SREV_9100(ah
))
2878 host_isr
= REG_READ(ah
, AR_INTR_ASYNC_CAUSE
);
2879 if ((host_isr
& AR_INTR_MAC_IRQ
) && (host_isr
!= AR_INTR_SPURIOUS
))
2882 host_isr
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
2883 if ((host_isr
& AR_INTR_SYNC_DEFAULT
)
2884 && (host_isr
!= AR_INTR_SPURIOUS
))
2890 bool ath9k_hw_getisr(struct ath_hw
*ah
, enum ath9k_int
*masked
)
2894 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2896 bool fatal_int
= false;
2898 if (!AR_SREV_9100(ah
)) {
2899 if (REG_READ(ah
, AR_INTR_ASYNC_CAUSE
) & AR_INTR_MAC_IRQ
) {
2900 if ((REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
)
2901 == AR_RTC_STATUS_ON
) {
2902 isr
= REG_READ(ah
, AR_ISR
);
2906 sync_cause
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
) &
2907 AR_INTR_SYNC_DEFAULT
;
2911 if (!isr
&& !sync_cause
)
2915 isr
= REG_READ(ah
, AR_ISR
);
2919 if (isr
& AR_ISR_BCNMISC
) {
2921 isr2
= REG_READ(ah
, AR_ISR_S2
);
2922 if (isr2
& AR_ISR_S2_TIM
)
2923 mask2
|= ATH9K_INT_TIM
;
2924 if (isr2
& AR_ISR_S2_DTIM
)
2925 mask2
|= ATH9K_INT_DTIM
;
2926 if (isr2
& AR_ISR_S2_DTIMSYNC
)
2927 mask2
|= ATH9K_INT_DTIMSYNC
;
2928 if (isr2
& (AR_ISR_S2_CABEND
))
2929 mask2
|= ATH9K_INT_CABEND
;
2930 if (isr2
& AR_ISR_S2_GTT
)
2931 mask2
|= ATH9K_INT_GTT
;
2932 if (isr2
& AR_ISR_S2_CST
)
2933 mask2
|= ATH9K_INT_CST
;
2934 if (isr2
& AR_ISR_S2_TSFOOR
)
2935 mask2
|= ATH9K_INT_TSFOOR
;
2938 isr
= REG_READ(ah
, AR_ISR_RAC
);
2939 if (isr
== 0xffffffff) {
2944 *masked
= isr
& ATH9K_INT_COMMON
;
2946 if (ah
->intr_mitigation
) {
2947 if (isr
& (AR_ISR_RXMINTR
| AR_ISR_RXINTM
))
2948 *masked
|= ATH9K_INT_RX
;
2951 if (isr
& (AR_ISR_RXOK
| AR_ISR_RXERR
))
2952 *masked
|= ATH9K_INT_RX
;
2954 (AR_ISR_TXOK
| AR_ISR_TXDESC
| AR_ISR_TXERR
|
2958 *masked
|= ATH9K_INT_TX
;
2960 s0_s
= REG_READ(ah
, AR_ISR_S0_S
);
2961 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXOK
);
2962 ah
->intr_txqs
|= MS(s0_s
, AR_ISR_S0_QCU_TXDESC
);
2964 s1_s
= REG_READ(ah
, AR_ISR_S1_S
);
2965 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXERR
);
2966 ah
->intr_txqs
|= MS(s1_s
, AR_ISR_S1_QCU_TXEOL
);
2969 if (isr
& AR_ISR_RXORN
) {
2970 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
,
2971 "receive FIFO overrun interrupt\n");
2974 if (!AR_SREV_9100(ah
)) {
2975 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
2976 u32 isr5
= REG_READ(ah
, AR_ISR_S5_S
);
2977 if (isr5
& AR_ISR_S5_TIM_TIMER
)
2978 *masked
|= ATH9K_INT_TIM_TIMER
;
2985 if (AR_SREV_9100(ah
))
2991 (AR_INTR_SYNC_HOST1_FATAL
| AR_INTR_SYNC_HOST1_PERR
))
2995 if (sync_cause
& AR_INTR_SYNC_HOST1_FATAL
) {
2996 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
2997 "received PCI FATAL interrupt\n");
2999 if (sync_cause
& AR_INTR_SYNC_HOST1_PERR
) {
3000 DPRINTF(ah
->ah_sc
, ATH_DBG_ANY
,
3001 "received PCI PERR interrupt\n");
3004 if (sync_cause
& AR_INTR_SYNC_RADM_CPL_TIMEOUT
) {
3005 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
,
3006 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3007 REG_WRITE(ah
, AR_RC
, AR_RC_HOSTIF
);
3008 REG_WRITE(ah
, AR_RC
, 0);
3009 *masked
|= ATH9K_INT_FATAL
;
3011 if (sync_cause
& AR_INTR_SYNC_LOCAL_TIMEOUT
) {
3012 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
,
3013 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3016 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE_CLR
, sync_cause
);
3017 (void) REG_READ(ah
, AR_INTR_SYNC_CAUSE_CLR
);
3023 enum ath9k_int
ath9k_hw_intrget(struct ath_hw
*ah
)
3025 return ah
->mask_reg
;
3028 enum ath9k_int
ath9k_hw_set_interrupts(struct ath_hw
*ah
, enum ath9k_int ints
)
3030 u32 omask
= ah
->mask_reg
;
3032 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3034 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
, "0x%x => 0x%x\n", omask
, ints
);
3036 if (omask
& ATH9K_INT_GLOBAL
) {
3037 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
, "disable IER\n");
3038 REG_WRITE(ah
, AR_IER
, AR_IER_DISABLE
);
3039 (void) REG_READ(ah
, AR_IER
);
3040 if (!AR_SREV_9100(ah
)) {
3041 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
, 0);
3042 (void) REG_READ(ah
, AR_INTR_ASYNC_ENABLE
);
3044 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
3045 (void) REG_READ(ah
, AR_INTR_SYNC_ENABLE
);
3049 mask
= ints
& ATH9K_INT_COMMON
;
3052 if (ints
& ATH9K_INT_TX
) {
3053 if (ah
->txok_interrupt_mask
)
3054 mask
|= AR_IMR_TXOK
;
3055 if (ah
->txdesc_interrupt_mask
)
3056 mask
|= AR_IMR_TXDESC
;
3057 if (ah
->txerr_interrupt_mask
)
3058 mask
|= AR_IMR_TXERR
;
3059 if (ah
->txeol_interrupt_mask
)
3060 mask
|= AR_IMR_TXEOL
;
3062 if (ints
& ATH9K_INT_RX
) {
3063 mask
|= AR_IMR_RXERR
;
3064 if (ah
->intr_mitigation
)
3065 mask
|= AR_IMR_RXMINTR
| AR_IMR_RXINTM
;
3067 mask
|= AR_IMR_RXOK
| AR_IMR_RXDESC
;
3068 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
))
3069 mask
|= AR_IMR_GENTMR
;
3072 if (ints
& (ATH9K_INT_BMISC
)) {
3073 mask
|= AR_IMR_BCNMISC
;
3074 if (ints
& ATH9K_INT_TIM
)
3075 mask2
|= AR_IMR_S2_TIM
;
3076 if (ints
& ATH9K_INT_DTIM
)
3077 mask2
|= AR_IMR_S2_DTIM
;
3078 if (ints
& ATH9K_INT_DTIMSYNC
)
3079 mask2
|= AR_IMR_S2_DTIMSYNC
;
3080 if (ints
& ATH9K_INT_CABEND
)
3081 mask2
|= AR_IMR_S2_CABEND
;
3082 if (ints
& ATH9K_INT_TSFOOR
)
3083 mask2
|= AR_IMR_S2_TSFOOR
;
3086 if (ints
& (ATH9K_INT_GTT
| ATH9K_INT_CST
)) {
3087 mask
|= AR_IMR_BCNMISC
;
3088 if (ints
& ATH9K_INT_GTT
)
3089 mask2
|= AR_IMR_S2_GTT
;
3090 if (ints
& ATH9K_INT_CST
)
3091 mask2
|= AR_IMR_S2_CST
;
3094 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
, "new IMR 0x%x\n", mask
);
3095 REG_WRITE(ah
, AR_IMR
, mask
);
3096 mask
= REG_READ(ah
, AR_IMR_S2
) & ~(AR_IMR_S2_TIM
|
3098 AR_IMR_S2_DTIMSYNC
|
3102 AR_IMR_S2_GTT
| AR_IMR_S2_CST
);
3103 REG_WRITE(ah
, AR_IMR_S2
, mask
| mask2
);
3104 ah
->mask_reg
= ints
;
3106 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
3107 if (ints
& ATH9K_INT_TIM_TIMER
)
3108 REG_SET_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
3110 REG_CLR_BIT(ah
, AR_IMR_S5
, AR_IMR_S5_TIM_TIMER
);
3113 if (ints
& ATH9K_INT_GLOBAL
) {
3114 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
, "enable IER\n");
3115 REG_WRITE(ah
, AR_IER
, AR_IER_ENABLE
);
3116 if (!AR_SREV_9100(ah
)) {
3117 REG_WRITE(ah
, AR_INTR_ASYNC_ENABLE
,
3119 REG_WRITE(ah
, AR_INTR_ASYNC_MASK
, AR_INTR_MAC_IRQ
);
3122 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
,
3123 AR_INTR_SYNC_DEFAULT
);
3124 REG_WRITE(ah
, AR_INTR_SYNC_MASK
,
3125 AR_INTR_SYNC_DEFAULT
);
3127 DPRINTF(ah
->ah_sc
, ATH_DBG_INTERRUPT
, "AR_IMR 0x%x IER 0x%x\n",
3128 REG_READ(ah
, AR_IMR
), REG_READ(ah
, AR_IER
));
3134 /*******************/
3135 /* Beacon Handling */
3136 /*******************/
3138 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
3142 ah
->beacon_interval
= beacon_period
;
3144 switch (ah
->opmode
) {
3145 case NL80211_IFTYPE_STATION
:
3146 case NL80211_IFTYPE_MONITOR
:
3147 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
3148 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, 0xffff);
3149 REG_WRITE(ah
, AR_NEXT_SWBA
, 0x7ffff);
3150 flags
|= AR_TBTT_TIMER_EN
;
3152 case NL80211_IFTYPE_ADHOC
:
3153 case NL80211_IFTYPE_MESH_POINT
:
3154 REG_SET_BIT(ah
, AR_TXCFG
,
3155 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
3156 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
,
3157 TU_TO_USEC(next_beacon
+
3158 (ah
->atim_window
? ah
->
3160 flags
|= AR_NDP_TIMER_EN
;
3161 case NL80211_IFTYPE_AP
:
3162 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(next_beacon
));
3163 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
,
3164 TU_TO_USEC(next_beacon
-
3166 dma_beacon_response_time
));
3167 REG_WRITE(ah
, AR_NEXT_SWBA
,
3168 TU_TO_USEC(next_beacon
-
3170 sw_beacon_response_time
));
3172 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
3175 DPRINTF(ah
->ah_sc
, ATH_DBG_BEACON
,
3176 "%s: unsupported opmode: %d\n",
3177 __func__
, ah
->opmode
);
3182 REG_WRITE(ah
, AR_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
3183 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, TU_TO_USEC(beacon_period
));
3184 REG_WRITE(ah
, AR_SWBA_PERIOD
, TU_TO_USEC(beacon_period
));
3185 REG_WRITE(ah
, AR_NDP_PERIOD
, TU_TO_USEC(beacon_period
));
3187 beacon_period
&= ~ATH9K_BEACON_ENA
;
3188 if (beacon_period
& ATH9K_BEACON_RESET_TSF
) {
3189 beacon_period
&= ~ATH9K_BEACON_RESET_TSF
;
3190 ath9k_hw_reset_tsf(ah
);
3193 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
3196 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
3197 const struct ath9k_beacon_state
*bs
)
3199 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
3200 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3202 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
3204 REG_WRITE(ah
, AR_BEACON_PERIOD
,
3205 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3206 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
3207 TU_TO_USEC(bs
->bs_intval
& ATH9K_BEACON_PERIOD
));
3209 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
3210 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
3212 beaconintval
= bs
->bs_intval
& ATH9K_BEACON_PERIOD
;
3214 if (bs
->bs_sleepduration
> beaconintval
)
3215 beaconintval
= bs
->bs_sleepduration
;
3217 dtimperiod
= bs
->bs_dtimperiod
;
3218 if (bs
->bs_sleepduration
> dtimperiod
)
3219 dtimperiod
= bs
->bs_sleepduration
;
3221 if (beaconintval
== dtimperiod
)
3222 nextTbtt
= bs
->bs_nextdtim
;
3224 nextTbtt
= bs
->bs_nexttbtt
;
3226 DPRINTF(ah
->ah_sc
, ATH_DBG_BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
3227 DPRINTF(ah
->ah_sc
, ATH_DBG_BEACON
, "next beacon %d\n", nextTbtt
);
3228 DPRINTF(ah
->ah_sc
, ATH_DBG_BEACON
, "beacon period %d\n", beaconintval
);
3229 DPRINTF(ah
->ah_sc
, ATH_DBG_BEACON
, "DTIM period %d\n", dtimperiod
);
3231 REG_WRITE(ah
, AR_NEXT_DTIM
,
3232 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
3233 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
3235 REG_WRITE(ah
, AR_SLEEP1
,
3236 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
3237 | AR_SLEEP1_ASSUME_DTIM
);
3239 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
3240 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
3242 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
3244 REG_WRITE(ah
, AR_SLEEP2
,
3245 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
3247 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
3248 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
3250 REG_SET_BIT(ah
, AR_TIMER_MODE
,
3251 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
3254 /* TSF Out of Range Threshold */
3255 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
3258 /*******************/
3259 /* HW Capabilities */
3260 /*******************/
3262 bool ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
3264 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
3265 u16 capField
= 0, eeval
;
3267 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
3268 ah
->regulatory
.current_rd
= eeval
;
3270 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_1
);
3271 if (AR_SREV_9285_10_OR_LATER(ah
))
3272 eeval
|= AR9285_RDEXT_DEFAULT
;
3273 ah
->regulatory
.current_rd_ext
= eeval
;
3275 capField
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_CAP
);
3277 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
3278 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
3279 if (ah
->regulatory
.current_rd
== 0x64 ||
3280 ah
->regulatory
.current_rd
== 0x65)
3281 ah
->regulatory
.current_rd
+= 5;
3282 else if (ah
->regulatory
.current_rd
== 0x41)
3283 ah
->regulatory
.current_rd
= 0x43;
3284 DPRINTF(ah
->ah_sc
, ATH_DBG_REGULATORY
,
3285 "regdomain mapped to 0x%x\n", ah
->regulatory
.current_rd
);
3288 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
3289 bitmap_zero(pCap
->wireless_modes
, ATH9K_MODE_MAX
);
3291 if (eeval
& AR5416_OPFLAGS_11A
) {
3292 set_bit(ATH9K_MODE_11A
, pCap
->wireless_modes
);
3293 if (ah
->config
.ht_enable
) {
3294 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT20
))
3295 set_bit(ATH9K_MODE_11NA_HT20
,
3296 pCap
->wireless_modes
);
3297 if (!(eeval
& AR5416_OPFLAGS_N_5G_HT40
)) {
3298 set_bit(ATH9K_MODE_11NA_HT40PLUS
,
3299 pCap
->wireless_modes
);
3300 set_bit(ATH9K_MODE_11NA_HT40MINUS
,
3301 pCap
->wireless_modes
);
3306 if (eeval
& AR5416_OPFLAGS_11G
) {
3307 set_bit(ATH9K_MODE_11B
, pCap
->wireless_modes
);
3308 set_bit(ATH9K_MODE_11G
, pCap
->wireless_modes
);
3309 if (ah
->config
.ht_enable
) {
3310 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT20
))
3311 set_bit(ATH9K_MODE_11NG_HT20
,
3312 pCap
->wireless_modes
);
3313 if (!(eeval
& AR5416_OPFLAGS_N_2G_HT40
)) {
3314 set_bit(ATH9K_MODE_11NG_HT40PLUS
,
3315 pCap
->wireless_modes
);
3316 set_bit(ATH9K_MODE_11NG_HT40MINUS
,
3317 pCap
->wireless_modes
);
3322 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
3323 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
3324 !(eeval
& AR5416_OPFLAGS_11A
))
3325 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
3327 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
3329 if (!(AR_SREV_9280(ah
) && (ah
->hw_version
.macRev
== 0)))
3330 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
3332 pCap
->low_2ghz_chan
= 2312;
3333 pCap
->high_2ghz_chan
= 2732;
3335 pCap
->low_5ghz_chan
= 4920;
3336 pCap
->high_5ghz_chan
= 6100;
3338 pCap
->hw_caps
&= ~ATH9K_HW_CAP_CIPHER_CKIP
;
3339 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_TKIP
;
3340 pCap
->hw_caps
|= ATH9K_HW_CAP_CIPHER_AESCCM
;
3342 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MIC_CKIP
;
3343 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_TKIP
;
3344 pCap
->hw_caps
|= ATH9K_HW_CAP_MIC_AESCCM
;
3346 pCap
->hw_caps
|= ATH9K_HW_CAP_CHAN_SPREAD
;
3348 if (ah
->config
.ht_enable
)
3349 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
3351 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
3353 pCap
->hw_caps
|= ATH9K_HW_CAP_GTT
;
3354 pCap
->hw_caps
|= ATH9K_HW_CAP_VEOL
;
3355 pCap
->hw_caps
|= ATH9K_HW_CAP_BSSIDMASK
;
3356 pCap
->hw_caps
&= ~ATH9K_HW_CAP_MCAST_KEYSEARCH
;
3358 if (capField
& AR_EEPROM_EEPCAP_MAXQCU
)
3359 pCap
->total_queues
=
3360 MS(capField
, AR_EEPROM_EEPCAP_MAXQCU
);
3362 pCap
->total_queues
= ATH9K_NUM_TX_QUEUES
;
3364 if (capField
& AR_EEPROM_EEPCAP_KC_ENTRIES
)
3365 pCap
->keycache_size
=
3366 1 << MS(capField
, AR_EEPROM_EEPCAP_KC_ENTRIES
);
3368 pCap
->keycache_size
= AR_KEYTABLE_SIZE
;
3370 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCC
;
3371 pCap
->num_mr_retries
= 4;
3372 pCap
->tx_triglevel_max
= MAX_TX_FIFO_THRESHOLD
;
3374 if (AR_SREV_9285_10_OR_LATER(ah
))
3375 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
3376 else if (AR_SREV_9280_10_OR_LATER(ah
))
3377 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
3379 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
3381 if (AR_SREV_9280_10_OR_LATER(ah
)) {
3382 pCap
->hw_caps
|= ATH9K_HW_CAP_WOW
;
3383 pCap
->hw_caps
|= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT
;
3385 pCap
->hw_caps
&= ~ATH9K_HW_CAP_WOW
;
3386 pCap
->hw_caps
&= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT
;
3389 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
)) {
3390 pCap
->hw_caps
|= ATH9K_HW_CAP_CST
;
3391 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
3393 pCap
->rts_aggr_limit
= (8 * 1024);
3396 pCap
->hw_caps
|= ATH9K_HW_CAP_ENHANCEDPM
;
3398 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3399 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
3400 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
3402 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
3403 ah
->rfkill_polarity
=
3404 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
3406 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
3410 if ((ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
) ||
3411 (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
) ||
3412 (ah
->hw_version
.macVersion
== AR_SREV_VERSION_9160
) ||
3413 (ah
->hw_version
.macVersion
== AR_SREV_VERSION_9100
) ||
3414 (ah
->hw_version
.macVersion
== AR_SREV_VERSION_9280
))
3415 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
3417 pCap
->hw_caps
|= ATH9K_HW_CAP_AUTOSLEEP
;
3419 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
3420 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
3422 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
3424 if (ah
->regulatory
.current_rd_ext
& (1 << REG_EXT_JAPAN_MIDBAND
)) {
3426 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3427 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
|
3428 AR_EEPROM_EEREGCAP_EN_KK_U2
|
3429 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND
;
3432 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A
|
3433 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN
;
3436 pCap
->reg_cap
|= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND
;
3438 pCap
->num_antcfg_5ghz
=
3439 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_5GHZ
);
3440 pCap
->num_antcfg_2ghz
=
3441 ah
->eep_ops
->get_num_ant_config(ah
, ATH9K_HAL_FREQ_BAND_2GHZ
);
3443 if (AR_SREV_9280_10_OR_LATER(ah
) && btcoex_enable
) {
3444 pCap
->hw_caps
|= ATH9K_HW_CAP_BT_COEX
;
3445 ah
->btactive_gpio
= 6;
3446 ah
->wlanactive_gpio
= 5;
3452 bool ath9k_hw_getcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3453 u32 capability
, u32
*result
)
3456 case ATH9K_CAP_CIPHER
:
3457 switch (capability
) {
3458 case ATH9K_CIPHER_AES_CCM
:
3459 case ATH9K_CIPHER_AES_OCB
:
3460 case ATH9K_CIPHER_TKIP
:
3461 case ATH9K_CIPHER_WEP
:
3462 case ATH9K_CIPHER_MIC
:
3463 case ATH9K_CIPHER_CLR
:
3468 case ATH9K_CAP_TKIP_MIC
:
3469 switch (capability
) {
3473 return (ah
->sta_id1_defaults
&
3474 AR_STA_ID1_CRPT_MIC_ENABLE
) ? true :
3477 case ATH9K_CAP_TKIP_SPLIT
:
3478 return (ah
->misc_mode
& AR_PCU_MIC_NEW_LOC_ENA
) ?
3480 case ATH9K_CAP_DIVERSITY
:
3481 return (REG_READ(ah
, AR_PHY_CCK_DETECT
) &
3482 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
) ?
3484 case ATH9K_CAP_MCAST_KEYSRCH
:
3485 switch (capability
) {
3489 if (REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_ADHOC
) {
3492 return (ah
->sta_id1_defaults
&
3493 AR_STA_ID1_MCAST_KSRCH
) ? true :
3498 case ATH9K_CAP_TXPOW
:
3499 switch (capability
) {
3503 *result
= ah
->regulatory
.power_limit
;
3506 *result
= ah
->regulatory
.max_power_level
;
3509 *result
= ah
->regulatory
.tp_scale
;
3514 return (AR_SREV_9280_20_OR_LATER(ah
) &&
3515 (ah
->eep_ops
->get_eeprom(ah
, EEP_RC_CHAIN_MASK
) == 1))
3522 bool ath9k_hw_setcapability(struct ath_hw
*ah
, enum ath9k_capability_type type
,
3523 u32 capability
, u32 setting
, int *status
)
3528 case ATH9K_CAP_TKIP_MIC
:
3530 ah
->sta_id1_defaults
|=
3531 AR_STA_ID1_CRPT_MIC_ENABLE
;
3533 ah
->sta_id1_defaults
&=
3534 ~AR_STA_ID1_CRPT_MIC_ENABLE
;
3536 case ATH9K_CAP_DIVERSITY
:
3537 v
= REG_READ(ah
, AR_PHY_CCK_DETECT
);
3539 v
|= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3541 v
&= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV
;
3542 REG_WRITE(ah
, AR_PHY_CCK_DETECT
, v
);
3544 case ATH9K_CAP_MCAST_KEYSRCH
:
3546 ah
->sta_id1_defaults
|= AR_STA_ID1_MCAST_KSRCH
;
3548 ah
->sta_id1_defaults
&= ~AR_STA_ID1_MCAST_KSRCH
;
3555 /****************************/
3556 /* GPIO / RFKILL / Antennae */
3557 /****************************/
3559 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
3563 u32 gpio_shift
, tmp
;
3566 addr
= AR_GPIO_OUTPUT_MUX3
;
3568 addr
= AR_GPIO_OUTPUT_MUX2
;
3570 addr
= AR_GPIO_OUTPUT_MUX1
;
3572 gpio_shift
= (gpio
% 6) * 5;
3574 if (AR_SREV_9280_20_OR_LATER(ah
)
3575 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
3576 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
3577 (0x1f << gpio_shift
));
3579 tmp
= REG_READ(ah
, addr
);
3580 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
3581 tmp
&= ~(0x1f << gpio_shift
);
3582 tmp
|= (type
<< gpio_shift
);
3583 REG_WRITE(ah
, addr
, tmp
);
3587 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
3591 ASSERT(gpio
< ah
->caps
.num_gpio_pins
);
3593 gpio_shift
= gpio
<< 1;
3597 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
3598 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3601 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
3603 #define MS_REG_READ(x, y) \
3604 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3606 if (gpio
>= ah
->caps
.num_gpio_pins
)
3609 if (AR_SREV_9285_10_OR_LATER(ah
))
3610 return MS_REG_READ(AR9285
, gpio
) != 0;
3611 else if (AR_SREV_9280_10_OR_LATER(ah
))
3612 return MS_REG_READ(AR928X
, gpio
) != 0;
3614 return MS_REG_READ(AR
, gpio
) != 0;
3617 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
3622 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
3624 gpio_shift
= 2 * gpio
;
3628 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
3629 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
3632 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
3634 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
3638 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3639 void ath9k_enable_rfkill(struct ath_hw
*ah
)
3641 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
,
3642 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB
);
3644 REG_CLR_BIT(ah
, AR_GPIO_INPUT_MUX2
,
3645 AR_GPIO_INPUT_MUX2_RFSILENT
);
3647 ath9k_hw_cfg_gpio_input(ah
, ah
->rfkill_gpio
);
3648 REG_SET_BIT(ah
, AR_PHY_TEST
, RFSILENT_BB
);
3652 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
)
3654 return REG_READ(ah
, AR_DEF_ANTENNA
) & 0x7;
3657 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
3659 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
3662 bool ath9k_hw_setantennaswitch(struct ath_hw
*ah
,
3663 enum ath9k_ant_setting settings
,
3664 struct ath9k_channel
*chan
,
3669 static u8 tx_chainmask_cfg
, rx_chainmask_cfg
;
3671 if (AR_SREV_9280(ah
)) {
3672 if (!tx_chainmask_cfg
) {
3674 tx_chainmask_cfg
= *tx_chainmask
;
3675 rx_chainmask_cfg
= *rx_chainmask
;
3679 case ATH9K_ANT_FIXED_A
:
3680 *tx_chainmask
= ATH9K_ANTENNA0_CHAINMASK
;
3681 *rx_chainmask
= ATH9K_ANTENNA0_CHAINMASK
;
3682 *antenna_cfgd
= true;
3684 case ATH9K_ANT_FIXED_B
:
3685 if (ah
->caps
.tx_chainmask
>
3686 ATH9K_ANTENNA1_CHAINMASK
) {
3687 *tx_chainmask
= ATH9K_ANTENNA1_CHAINMASK
;
3689 *rx_chainmask
= ATH9K_ANTENNA1_CHAINMASK
;
3690 *antenna_cfgd
= true;
3692 case ATH9K_ANT_VARIABLE
:
3693 *tx_chainmask
= tx_chainmask_cfg
;
3694 *rx_chainmask
= rx_chainmask_cfg
;
3695 *antenna_cfgd
= true;
3701 ah
->diversity_control
= settings
;
3707 /*********************/
3708 /* General Operation */
3709 /*********************/
3711 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
3713 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
3714 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
3716 if (phybits
& AR_PHY_ERR_RADAR
)
3717 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
3718 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
3719 bits
|= ATH9K_RX_FILTER_PHYERR
;
3724 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
3728 REG_WRITE(ah
, AR_RX_FILTER
, (bits
& 0xffff) | AR_RX_COMPR_BAR
);
3730 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
3731 phybits
|= AR_PHY_ERR_RADAR
;
3732 if (bits
& ATH9K_RX_FILTER_PHYERR
)
3733 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
3734 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
3737 REG_WRITE(ah
, AR_RXCFG
,
3738 REG_READ(ah
, AR_RXCFG
) | AR_RXCFG_ZLFDMA
);
3740 REG_WRITE(ah
, AR_RXCFG
,
3741 REG_READ(ah
, AR_RXCFG
) & ~AR_RXCFG_ZLFDMA
);
3744 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
3746 return ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
);
3749 bool ath9k_hw_disable(struct ath_hw
*ah
)
3751 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
3754 return ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
);
3757 bool ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
)
3759 struct ath9k_channel
*chan
= ah
->curchan
;
3760 struct ieee80211_channel
*channel
= chan
->chan
;
3762 ah
->regulatory
.power_limit
= min(limit
, (u32
) MAX_RATE_POWER
);
3764 if (ah
->eep_ops
->set_txpower(ah
, chan
,
3765 ath9k_regd_get_ctl(ah
, chan
),
3766 channel
->max_antenna_gain
* 2,
3767 channel
->max_power
* 2,
3768 min((u32
) MAX_RATE_POWER
,
3769 (u32
) ah
->regulatory
.power_limit
)) != 0)
3775 void ath9k_hw_setmac(struct ath_hw
*ah
, const u8
*mac
)
3777 memcpy(ah
->macaddr
, mac
, ETH_ALEN
);
3780 void ath9k_hw_setopmode(struct ath_hw
*ah
)
3782 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
3785 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
3787 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
3788 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
3791 void ath9k_hw_setbssidmask(struct ath_softc
*sc
)
3793 REG_WRITE(sc
->sc_ah
, AR_BSSMSKL
, get_unaligned_le32(sc
->bssidmask
));
3794 REG_WRITE(sc
->sc_ah
, AR_BSSMSKU
, get_unaligned_le16(sc
->bssidmask
+ 4));
3797 void ath9k_hw_write_associd(struct ath_softc
*sc
)
3799 REG_WRITE(sc
->sc_ah
, AR_BSS_ID0
, get_unaligned_le32(sc
->curbssid
));
3800 REG_WRITE(sc
->sc_ah
, AR_BSS_ID1
, get_unaligned_le16(sc
->curbssid
+ 4) |
3801 ((sc
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
3804 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
3808 tsf
= REG_READ(ah
, AR_TSF_U32
);
3809 tsf
= (tsf
<< 32) | REG_READ(ah
, AR_TSF_L32
);
3814 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
3816 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
3817 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
3820 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
3825 while (REG_READ(ah
, AR_SLP32_MODE
) & AR_SLP32_TSF_WRITE_STATUS
) {
3828 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
,
3829 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3834 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
3837 bool ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
3840 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
3842 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
3847 bool ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
3849 if (us
< ATH9K_SLOT_TIME_9
|| us
> ath9k_hw_mac_to_usec(ah
, 0xffff)) {
3850 DPRINTF(ah
->ah_sc
, ATH_DBG_RESET
, "bad slot time %u\n", us
);
3851 ah
->slottime
= (u32
) -1;
3854 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, ath9k_hw_mac_to_clks(ah
, us
));
3860 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
, enum ath9k_ht_macmode mode
)
3864 if (mode
== ATH9K_HT_MACMODE_2040
&&
3865 !ah
->config
.cwm_ignore_extcca
)
3866 macmode
= AR_2040_JOINED_RX_CLEAR
;
3870 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
3873 /***************************/
3874 /* Bluetooth Coexistence */
3875 /***************************/
3877 void ath9k_hw_btcoex_enable(struct ath_hw
*ah
)
3879 /* connect bt_active to baseband */
3880 REG_CLR_BIT(ah
, AR_GPIO_INPUT_EN_VAL
,
3881 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF
|
3882 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF
));
3884 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
,
3885 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB
);
3887 /* Set input mux for bt_active to gpio pin */
3888 REG_RMW_FIELD(ah
, AR_GPIO_INPUT_MUX1
,
3889 AR_GPIO_INPUT_MUX1_BT_ACTIVE
,
3892 /* Configure the desired gpio port for input */
3893 ath9k_hw_cfg_gpio_input(ah
, ah
->btactive_gpio
);
3895 /* Configure the desired GPIO port for TX_FRAME output */
3896 ath9k_hw_cfg_output(ah
, ah
->wlanactive_gpio
,
3897 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME
);