drivers/net/wireless/ath9k/pci.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include <linux/pci.h>
  19 #include "core.h"
  20 #include "reg.h"
  21 #include "hw.h"
  22
  23 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  24         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  25         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  26         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  27         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  28         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  29         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  30         { 0 }
  31 };
  32
  33 /* return bus cachesize in 4B word units */
  34 static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
  35 {
  36         u8 u8tmp;
  37
  38         pci_read_config_byte(to_pci_dev(sc->dev), PCI_CACHE_LINE_SIZE,
  39                              (u8 *)&u8tmp);
  40         *csz = (int)u8tmp;
  41
  42         /*
  43          * This check was put in to avoid "unplesant" consequences if
  44          * the bootrom has not fully initialized all PCI devices.
  45          * Sometimes the cache line size register is not set
  46          */
  47
  48         if (*csz == 0)
  49                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  50 }
  51
  52 static void ath_pci_cleanup(struct ath_softc *sc)
  53 {
  54         struct pci_dev *pdev = to_pci_dev(sc->dev);
  55
  56         pci_iounmap(pdev, sc->mem);
  57         pci_release_region(pdev, 0);
  58         pci_disable_device(pdev);
  59 }
  60
  61 static bool ath_pci_eeprom_read(struct ath_hal *ah, u32 off, u16 *data)
  62 {
  63         (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
  64
  65         if (!ath9k_hw_wait(ah,
  66                            AR_EEPROM_STATUS_DATA,
  67                            AR_EEPROM_STATUS_DATA_BUSY |
  68                            AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
  69                 return false;
  70         }
  71
  72         *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
  73                    AR_EEPROM_STATUS_DATA_VAL);
  74
  75         return true;
  76 }
  77
  78 static struct ath_bus_ops ath_pci_bus_ops = {
  79         .read_cachesize = ath_pci_read_cachesize,
  80         .cleanup = ath_pci_cleanup,
  81         .eeprom_read = ath_pci_eeprom_read,
  82 };
  83
  84 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  85 {
  86         void __iomem *mem;
  87         struct ath_softc *sc;
  88         struct ieee80211_hw *hw;
  89         u8 csz;
  90         u32 val;
  91         int ret = 0;
  92         struct ath_hal *ah;
  93
  94         if (pci_enable_device(pdev))
  95                 return -EIO;
  96
  97         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  98
  99         if (ret) {
 100                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
 101                 goto bad;
 102         }
 103
 104         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 105
 106         if (ret) {
 107                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
 108                         "DMA enable failed\n");
 109                 goto bad;
 110         }
 111
 112         /*
 113          * Cache line size is used to size and align various
 114          * structures used to communicate with the hardware.
 115          */
 116         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 117         if (csz == 0) {
 118                 /*
 119                  * Linux 2.4.18 (at least) writes the cache line size
 120                  * register as a 16-bit wide register which is wrong.
 121                  * We must have this setup properly for rx buffer
 122                  * DMA to work so force a reasonable value here if it
 123                  * comes up zero.
 124                  */
 125                 csz = L1_CACHE_BYTES / sizeof(u32);
 126                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 127         }
 128         /*
 129          * The default setting of latency timer yields poor results,
 130          * set it to the value used by other systems. It may be worth
 131          * tweaking this setting more.
 132          */
 133         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 134
 135         pci_set_master(pdev);
 136
 137         /*
 138          * Disable the RETRY_TIMEOUT register (0x41) to keep
 139          * PCI Tx retries from interfering with C3 CPU state.
 140          */
 141         pci_read_config_dword(pdev, 0x40, &val);
 142         if ((val & 0x0000ff00) != 0)
 143                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 144
 145         ret = pci_request_region(pdev, 0, "ath9k");
 146         if (ret) {
 147                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
 148                 ret = -ENODEV;
 149                 goto bad;
 150         }
 151
 152         mem = pci_iomap(pdev, 0, 0);
 153         if (!mem) {
 154                 printk(KERN_ERR "PCI memory map error\n") ;
 155                 ret = -EIO;
 156                 goto bad1;
 157         }
 158
 159         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
 160         if (hw == NULL) {
 161                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
 162                 goto bad2;
 163         }
 164
 165         SET_IEEE80211_DEV(hw, &pdev->dev);
 166         pci_set_drvdata(pdev, hw);
 167
 168         sc = hw->priv;
 169         sc->hw = hw;
 170         sc->dev = &pdev->dev;
 171         sc->mem = mem;
 172         sc->bus_ops = &ath_pci_bus_ops;
 173
 174         if (ath_attach(id->device, sc) != 0) {
 175                 ret = -ENODEV;
 176                 goto bad3;
 177         }
 178
 179         /* setup interrupt service routine */
 180
 181         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
 182                 printk(KERN_ERR "%s: request_irq failed\n",
 183                         wiphy_name(hw->wiphy));
 184                 ret = -EIO;
 185                 goto bad4;
 186         }
 187
 188         sc->irq = pdev->irq;
 189
 190         ah = sc->sc_ah;
 191         printk(KERN_INFO
 192                "%s: Atheros AR%s MAC/BB Rev:%x "
 193                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
 194                wiphy_name(hw->wiphy),
 195                ath_mac_bb_name(ah->ah_macVersion),
 196                ah->ah_macRev,
 197                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
 198                ah->ah_phyRev,
 199                (unsigned long)mem, pdev->irq);
 200
 201         return 0;
 202 bad4:
 203         ath_detach(sc);
 204 bad3:
 205         ieee80211_free_hw(hw);
 206 bad2:
 207         pci_iounmap(pdev, mem);
 208 bad1:
 209         pci_release_region(pdev, 0);
 210 bad:
 211         pci_disable_device(pdev);
 212         return ret;
 213 }
 214
 215 static void ath_pci_remove(struct pci_dev *pdev)
 216 {
 217         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 218         struct ath_softc *sc = hw->priv;
 219
 220         ath_cleanup(sc);
 221 }
 222
 223 #ifdef CONFIG_PM
 224
 225 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 226 {
 227         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 228         struct ath_softc *sc = hw->priv;
 229
 230         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 231
 232 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
 233         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
 234                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
 235 #endif
 236
 237         pci_save_state(pdev);
 238         pci_disable_device(pdev);
 239         pci_set_power_state(pdev, PCI_D3hot);
 240
 241         return 0;
 242 }
 243
 244 static int ath_pci_resume(struct pci_dev *pdev)
 245 {
 246         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 247         struct ath_softc *sc = hw->priv;
 248         u32 val;
 249         int err;
 250
 251         err = pci_enable_device(pdev);
 252         if (err)
 253                 return err;
 254         pci_restore_state(pdev);
 255         /*
 256          * Suspend/Resume resets the PCI configuration space, so we have to
 257          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 258          * PCI Tx retries from interfering with C3 CPU state
 259          */
 260         pci_read_config_dword(pdev, 0x40, &val);
 261         if ((val & 0x0000ff00) != 0)
 262                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
 263
 264         /* Enable LED */
 265         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
 266                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 267         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 268
 269 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
 270         /*
 271          * check the h/w rfkill state on resume
 272          * and start the rfkill poll timer
 273          */
 274         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
 275                 queue_delayed_work(sc->hw->workqueue,
 276                                    &sc->rf_kill.rfkill_poll, 0);
 277 #endif
 278
 279         return 0;
 280 }
 281
 282 #endif /* CONFIG_PM */
 283
 284 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
 285
 286 static struct pci_driver ath_pci_driver = {
 287         .name       = "ath9k",
 288         .id_table   = ath_pci_id_table,
 289         .probe      = ath_pci_probe,
 290         .remove     = ath_pci_remove,
 291 #ifdef CONFIG_PM
 292         .suspend    = ath_pci_suspend,
 293         .resume     = ath_pci_resume,
 294 #endif /* CONFIG_PM */
 295 };
 296
 297 int __init ath_pci_init(void)
 298 {
 299         return pci_register_driver(&ath_pci_driver);
 300 }
 301
 302 void ath_pci_exit(void)
 303 {
 304         pci_unregister_driver(&ath_pci_driver);
 305 }