2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * Implementation of receive path.
24 * Setup and link descriptors.
26 * 11N: we can no longer afford to self link the last descriptor.
27 * MAC acknowledges BA status as long as it copies frames to host
28 * buffer (or rx fifo). This can incorrectly acknowledge packets
29 * to a sender if last desc is self-linked.
31 * NOTE: Caller should hold the rxbuf lock.
34 static void ath_rx_buf_link(struct ath_softc
*sc
, struct ath_buf
*bf
)
36 struct ath_hal
*ah
= sc
->sc_ah
;
43 ds
->ds_link
= 0; /* link to null */
44 ds
->ds_data
= bf
->bf_buf_addr
;
47 * virtual addr of the beginning of the buffer. */
50 ds
->ds_vdata
= skb
->data
;
52 /* setup rx descriptors */
53 ath9k_hw_setuprxdesc(ah
,
55 skb_tailroom(skb
), /* buffer size */
58 if (sc
->sc_rxlink
== NULL
)
59 ath9k_hw_putrxbuf(ah
, bf
->bf_daddr
);
61 *sc
->sc_rxlink
= bf
->bf_daddr
;
63 sc
->sc_rxlink
= &ds
->ds_link
;
67 /* Process received BAR frame */
69 static int ath_bar_rx(struct ath_softc
*sc
,
73 struct ieee80211_bar
*bar
;
74 struct ath_arx_tid
*rxtid
;
76 struct ath_recv_status
*rx_status
;
77 int tidno
, index
, cindex
;
80 /* look at BAR contents */
82 bar
= (struct ieee80211_bar
*)skb
->data
;
83 tidno
= (le16_to_cpu(bar
->control
) & IEEE80211_BAR_CTL_TID_M
)
84 >> IEEE80211_BAR_CTL_TID_S
;
85 seqno
= le16_to_cpu(bar
->start_seq_num
) >> IEEE80211_SEQ_SEQ_SHIFT
;
87 /* process BAR - indicate all pending RX frames till the BAR seqno */
89 rxtid
= &an
->an_aggr
.rx
.tid
[tidno
];
91 spin_lock_bh(&rxtid
->tidlock
);
93 /* get relative index */
95 index
= ATH_BA_INDEX(rxtid
->seq_next
, seqno
);
97 /* drop BAR if old sequence (index is too large) */
99 if ((index
> rxtid
->baw_size
) &&
100 (index
> (IEEE80211_SEQ_MAX
- (rxtid
->baw_size
<< 2))))
101 /* discard frame, ieee layer may not treat frame as a dup */
102 goto unlock_and_free
;
104 /* complete receive processing for all pending frames upto BAR seqno */
106 cindex
= (rxtid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
107 while ((rxtid
->baw_head
!= rxtid
->baw_tail
) &&
108 (rxtid
->baw_head
!= cindex
)) {
109 tskb
= rxtid
->rxbuf
[rxtid
->baw_head
].rx_wbuf
;
110 rx_status
= &rxtid
->rxbuf
[rxtid
->baw_head
].rx_status
;
111 rxtid
->rxbuf
[rxtid
->baw_head
].rx_wbuf
= NULL
;
114 ath_rx_subframe(an
, tskb
, rx_status
);
116 INCR(rxtid
->baw_head
, ATH_TID_MAX_BUFS
);
117 INCR(rxtid
->seq_next
, IEEE80211_SEQ_MAX
);
120 /* ... and indicate rest of the frames in-order */
122 while (rxtid
->baw_head
!= rxtid
->baw_tail
&&
123 rxtid
->rxbuf
[rxtid
->baw_head
].rx_wbuf
!= NULL
) {
124 tskb
= rxtid
->rxbuf
[rxtid
->baw_head
].rx_wbuf
;
125 rx_status
= &rxtid
->rxbuf
[rxtid
->baw_head
].rx_status
;
126 rxtid
->rxbuf
[rxtid
->baw_head
].rx_wbuf
= NULL
;
128 ath_rx_subframe(an
, tskb
, rx_status
);
130 INCR(rxtid
->baw_head
, ATH_TID_MAX_BUFS
);
131 INCR(rxtid
->seq_next
, IEEE80211_SEQ_MAX
);
135 spin_unlock_bh(&rxtid
->tidlock
);
136 /* free bar itself */
138 return IEEE80211_FTYPE_CTL
;
141 /* Function to handle a subframe of aggregation when HT is enabled */
143 static int ath_ampdu_input(struct ath_softc
*sc
,
146 struct ath_recv_status
*rx_status
)
148 struct ieee80211_hdr
*hdr
;
149 struct ath_arx_tid
*rxtid
;
150 struct ath_rxbuf
*rxbuf
;
153 int tid
= 0, index
, cindex
, rxdiff
;
157 hdr
= (struct ieee80211_hdr
*)skb
->data
;
158 fc
= hdr
->frame_control
;
160 /* collect stats of frames with non-zero version */
162 if ((le16_to_cpu(hdr
->frame_control
) & IEEE80211_FCTL_VERS
) != 0) {
167 type
= le16_to_cpu(hdr
->frame_control
) & IEEE80211_FCTL_FTYPE
;
168 subtype
= le16_to_cpu(hdr
->frame_control
) & IEEE80211_FCTL_STYPE
;
170 if (ieee80211_is_back_req(fc
))
171 return ath_bar_rx(sc
, an
, skb
);
173 /* special aggregate processing only for qos unicast data frames */
175 if (!ieee80211_is_data(fc
) ||
176 !ieee80211_is_data_qos(fc
) ||
177 is_multicast_ether_addr(hdr
->addr1
))
178 return ath_rx_subframe(an
, skb
, rx_status
);
180 /* lookup rx tid state */
182 if (ieee80211_is_data_qos(fc
)) {
183 qc
= ieee80211_get_qos_ctl(hdr
);
187 if (sc
->sc_ah
->ah_opmode
== ATH9K_M_STA
) {
188 /* Drop the frame not belonging to me. */
189 if (memcmp(hdr
->addr1
, sc
->sc_myaddr
, ETH_ALEN
)) {
195 rxtid
= &an
->an_aggr
.rx
.tid
[tid
];
197 spin_lock(&rxtid
->tidlock
);
199 rxdiff
= (rxtid
->baw_tail
- rxtid
->baw_head
) &
200 (ATH_TID_MAX_BUFS
- 1);
203 * If the ADDBA exchange has not been completed by the source,
204 * process via legacy path (i.e. no reordering buffer is needed)
206 if (!rxtid
->addba_exchangecomplete
) {
207 spin_unlock(&rxtid
->tidlock
);
208 return ath_rx_subframe(an
, skb
, rx_status
);
211 /* extract sequence number from recvd frame */
213 rxseq
= le16_to_cpu(hdr
->seq_ctrl
) >> IEEE80211_SEQ_SEQ_SHIFT
;
215 if (rxtid
->seq_reset
) {
216 rxtid
->seq_reset
= 0;
217 rxtid
->seq_next
= rxseq
;
220 index
= ATH_BA_INDEX(rxtid
->seq_next
, rxseq
);
222 /* drop frame if old sequence (index is too large) */
224 if (index
> (IEEE80211_SEQ_MAX
- (rxtid
->baw_size
<< 2))) {
225 /* discard frame, ieee layer may not treat frame as a dup */
226 spin_unlock(&rxtid
->tidlock
);
228 return IEEE80211_FTYPE_DATA
;
231 /* sequence number is beyond block-ack window */
233 if (index
>= rxtid
->baw_size
) {
235 /* complete receive processing for all pending frames */
237 while (index
>= rxtid
->baw_size
) {
239 rxbuf
= rxtid
->rxbuf
+ rxtid
->baw_head
;
241 if (rxbuf
->rx_wbuf
!= NULL
) {
242 ath_rx_subframe(an
, rxbuf
->rx_wbuf
,
244 rxbuf
->rx_wbuf
= NULL
;
247 INCR(rxtid
->baw_head
, ATH_TID_MAX_BUFS
);
248 INCR(rxtid
->seq_next
, IEEE80211_SEQ_MAX
);
254 /* add buffer to the recv ba window */
256 cindex
= (rxtid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
257 rxbuf
= rxtid
->rxbuf
+ cindex
;
259 if (rxbuf
->rx_wbuf
!= NULL
) {
260 spin_unlock(&rxtid
->tidlock
);
261 /* duplicate frame */
263 return IEEE80211_FTYPE_DATA
;
266 rxbuf
->rx_wbuf
= skb
;
267 rxbuf
->rx_time
= get_timestamp();
268 rxbuf
->rx_status
= *rx_status
;
270 /* advance tail if sequence received is newer
271 * than any received so far */
273 if (index
>= rxdiff
) {
274 rxtid
->baw_tail
= cindex
;
275 INCR(rxtid
->baw_tail
, ATH_TID_MAX_BUFS
);
278 /* indicate all in-order received frames */
280 while (rxtid
->baw_head
!= rxtid
->baw_tail
) {
281 rxbuf
= rxtid
->rxbuf
+ rxtid
->baw_head
;
285 ath_rx_subframe(an
, rxbuf
->rx_wbuf
, &rxbuf
->rx_status
);
286 rxbuf
->rx_wbuf
= NULL
;
288 INCR(rxtid
->baw_head
, ATH_TID_MAX_BUFS
);
289 INCR(rxtid
->seq_next
, IEEE80211_SEQ_MAX
);
293 * start a timer to flush all received frames if there are pending
296 if (rxtid
->baw_head
!= rxtid
->baw_tail
)
297 mod_timer(&rxtid
->timer
, ATH_RX_TIMEOUT
);
299 del_timer_sync(&rxtid
->timer
);
301 spin_unlock(&rxtid
->tidlock
);
302 return IEEE80211_FTYPE_DATA
;
305 /* Timer to flush all received sub-frames */
307 static void ath_rx_timer(unsigned long data
)
309 struct ath_arx_tid
*rxtid
= (struct ath_arx_tid
*)data
;
310 struct ath_node
*an
= rxtid
->an
;
311 struct ath_rxbuf
*rxbuf
;
314 spin_lock_bh(&rxtid
->tidlock
);
315 while (rxtid
->baw_head
!= rxtid
->baw_tail
) {
316 rxbuf
= rxtid
->rxbuf
+ rxtid
->baw_head
;
317 if (!rxbuf
->rx_wbuf
) {
318 INCR(rxtid
->baw_head
, ATH_TID_MAX_BUFS
);
319 INCR(rxtid
->seq_next
, IEEE80211_SEQ_MAX
);
324 * Stop if the next one is a very recent frame.
326 * Call get_timestamp in every iteration to protect against the
327 * case in which a new frame is received while we are executing
328 * this function. Using a timestamp obtained before entering
329 * the loop could lead to a very large time interval
330 * (a negative value typecast to unsigned), breaking the
333 if ((get_timestamp() - rxbuf
->rx_time
) <
334 (ATH_RX_TIMEOUT
* HZ
/ 1000))
337 ath_rx_subframe(an
, rxbuf
->rx_wbuf
,
339 rxbuf
->rx_wbuf
= NULL
;
341 INCR(rxtid
->baw_head
, ATH_TID_MAX_BUFS
);
342 INCR(rxtid
->seq_next
, IEEE80211_SEQ_MAX
);
346 * start a timer to flush all received frames if there are pending
349 if (rxtid
->baw_head
!= rxtid
->baw_tail
)
352 nosched
= 1; /* no need to re-arm the timer again */
354 spin_unlock_bh(&rxtid
->tidlock
);
357 /* Free all pending sub-frames in the re-ordering buffer */
359 static void ath_rx_flush_tid(struct ath_softc
*sc
,
360 struct ath_arx_tid
*rxtid
, int drop
)
362 struct ath_rxbuf
*rxbuf
;
365 spin_lock_irqsave(&rxtid
->tidlock
, flag
);
366 while (rxtid
->baw_head
!= rxtid
->baw_tail
) {
367 rxbuf
= rxtid
->rxbuf
+ rxtid
->baw_head
;
368 if (!rxbuf
->rx_wbuf
) {
369 INCR(rxtid
->baw_head
, ATH_TID_MAX_BUFS
);
370 INCR(rxtid
->seq_next
, IEEE80211_SEQ_MAX
);
375 dev_kfree_skb(rxbuf
->rx_wbuf
);
377 ath_rx_subframe(rxtid
->an
,
381 rxbuf
->rx_wbuf
= NULL
;
383 INCR(rxtid
->baw_head
, ATH_TID_MAX_BUFS
);
384 INCR(rxtid
->seq_next
, IEEE80211_SEQ_MAX
);
386 spin_unlock_irqrestore(&rxtid
->tidlock
, flag
);
389 static struct sk_buff
*ath_rxbuf_alloc(struct ath_softc
*sc
,
396 * Cache-line-align. This is important (for the
397 * 5210 at least) as not doing so causes bogus data
401 skb
= dev_alloc_skb(len
+ sc
->sc_cachelsz
- 1);
403 off
= ((unsigned long) skb
->data
) % sc
->sc_cachelsz
;
405 skb_reserve(skb
, sc
->sc_cachelsz
- off
);
407 DPRINTF(sc
, ATH_DBG_FATAL
,
408 "%s: skbuff alloc of size %u failed\n",
416 static void ath_rx_requeue(struct ath_softc
*sc
, struct sk_buff
*skb
)
418 struct ath_buf
*bf
= ATH_RX_CONTEXT(skb
)->ctx_rxbuf
;
422 spin_lock_bh(&sc
->sc_rxbuflock
);
423 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
425 * This buffer is still held for hw acess.
426 * Mark it as free to be re-queued it later.
428 bf
->bf_status
|= ATH_BUFSTATUS_FREE
;
430 /* XXX: we probably never enter here, remove after
432 list_add_tail(&bf
->list
, &sc
->sc_rxbuf
);
433 ath_rx_buf_link(sc
, bf
);
435 spin_unlock_bh(&sc
->sc_rxbuflock
);
439 * The skb indicated to upper stack won't be returned to us.
440 * So we have to allocate a new one and queue it by ourselves.
442 static int ath_rx_indicate(struct ath_softc
*sc
,
444 struct ath_recv_status
*status
,
447 struct ath_buf
*bf
= ATH_RX_CONTEXT(skb
)->ctx_rxbuf
;
448 struct sk_buff
*nskb
;
451 /* indicate frame to the stack, which will free the old skb. */
452 type
= _ath_rx_indicate(sc
, skb
, status
, keyix
);
454 /* allocate a new skb and queue it to for H/W processing */
455 nskb
= ath_rxbuf_alloc(sc
, sc
->sc_rxbufsize
);
458 bf
->bf_buf_addr
= pci_map_single(sc
->pdev
, nskb
->data
,
459 skb_end_pointer(nskb
) - nskb
->head
,
461 bf
->bf_dmacontext
= bf
->bf_buf_addr
;
462 ATH_RX_CONTEXT(nskb
)->ctx_rxbuf
= bf
;
464 /* queue the new wbuf to H/W */
465 ath_rx_requeue(sc
, nskb
);
471 static void ath_opmode_init(struct ath_softc
*sc
)
473 struct ath_hal
*ah
= sc
->sc_ah
;
476 /* configure rx filter */
477 rfilt
= ath_calcrxfilter(sc
);
478 ath9k_hw_setrxfilter(ah
, rfilt
);
480 /* configure bssid mask */
481 if (ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_BSSIDMASK
)
482 ath9k_hw_setbssidmask(ah
, sc
->sc_bssidmask
);
484 /* configure operational mode */
485 ath9k_hw_setopmode(ah
);
487 /* Handle any link-level address change. */
488 ath9k_hw_setmac(ah
, sc
->sc_myaddr
);
490 /* calculate and install multicast filter */
491 mfilt
[0] = mfilt
[1] = ~0;
493 ath9k_hw_setmcastfilter(ah
, mfilt
[0], mfilt
[1]);
494 DPRINTF(sc
, ATH_DBG_CONFIG
,
495 "%s: RX filter 0x%x, MC filter %08x:%08x\n",
496 __func__
, rfilt
, mfilt
[0], mfilt
[1]);
499 int ath_rx_init(struct ath_softc
*sc
, int nbufs
)
506 spin_lock_init(&sc
->sc_rxflushlock
);
507 sc
->sc_flags
&= ~SC_OP_RXFLUSH
;
508 spin_lock_init(&sc
->sc_rxbuflock
);
511 * Cisco's VPN software requires that drivers be able to
512 * receive encapsulated frames that are larger than the MTU.
513 * Since we can't be sure how large a frame we'll get, setup
514 * to handle the larges on possible.
516 sc
->sc_rxbufsize
= roundup(IEEE80211_MAX_MPDU_LEN
,
520 DPRINTF(sc
, ATH_DBG_CONFIG
, "%s: cachelsz %u rxbufsize %u\n",
521 __func__
, sc
->sc_cachelsz
, sc
->sc_rxbufsize
);
523 /* Initialize rx descriptors */
525 error
= ath_descdma_setup(sc
, &sc
->sc_rxdma
, &sc
->sc_rxbuf
,
528 DPRINTF(sc
, ATH_DBG_FATAL
,
529 "%s: failed to allocate rx descriptors: %d\n",
534 /* Pre-allocate a wbuf for each rx buffer */
536 list_for_each_entry(bf
, &sc
->sc_rxbuf
, list
) {
537 skb
= ath_rxbuf_alloc(sc
, sc
->sc_rxbufsize
);
544 bf
->bf_buf_addr
= pci_map_single(sc
->pdev
, skb
->data
,
545 skb_end_pointer(skb
) - skb
->head
,
547 bf
->bf_dmacontext
= bf
->bf_buf_addr
;
548 ATH_RX_CONTEXT(skb
)->ctx_rxbuf
= bf
;
550 sc
->sc_rxlink
= NULL
;
560 /* Reclaim all rx queue resources */
562 void ath_rx_cleanup(struct ath_softc
*sc
)
567 list_for_each_entry(bf
, &sc
->sc_rxbuf
, list
) {
573 /* cleanup rx descriptors */
575 if (sc
->sc_rxdma
.dd_desc_len
!= 0)
576 ath_descdma_cleanup(sc
, &sc
->sc_rxdma
, &sc
->sc_rxbuf
);
580 * Calculate the receive filter according to the
581 * operating mode and state:
583 * o always accept unicast, broadcast, and multicast traffic
584 * o maintain current state of phy error reception (the hal
585 * may enable phy error frames for noise immunity work)
586 * o probe request frames are accepted only when operating in
587 * hostap, adhoc, or monitor modes
588 * o enable promiscuous mode according to the interface state
590 * - when operating in adhoc mode so the 802.11 layer creates
591 * node table entries for peers,
592 * - when operating in station mode for collecting rssi data when
593 * the station is otherwise quiet, or
594 * - when operating as a repeater so we see repeater-sta beacons
598 u32
ath_calcrxfilter(struct ath_softc
*sc
)
600 #define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
604 rfilt
= (ath9k_hw_getrxfilter(sc
->sc_ah
) & RX_FILTER_PRESERVE
)
605 | ATH9K_RX_FILTER_UCAST
| ATH9K_RX_FILTER_BCAST
606 | ATH9K_RX_FILTER_MCAST
;
608 /* If not a STA, enable processing of Probe Requests */
609 if (sc
->sc_ah
->ah_opmode
!= ATH9K_M_STA
)
610 rfilt
|= ATH9K_RX_FILTER_PROBEREQ
;
612 /* Can't set HOSTAP into promiscous mode */
613 if (((sc
->sc_ah
->ah_opmode
!= ATH9K_M_HOSTAP
) &&
614 (sc
->rx_filter
& FIF_PROMISC_IN_BSS
)) ||
615 (sc
->sc_ah
->ah_opmode
== ATH9K_M_MONITOR
)) {
616 rfilt
|= ATH9K_RX_FILTER_PROM
;
617 /* ??? To prevent from sending ACK */
618 rfilt
&= ~ATH9K_RX_FILTER_UCAST
;
621 if (((sc
->sc_ah
->ah_opmode
== ATH9K_M_STA
) &&
622 (sc
->rx_filter
& FIF_BCN_PRBRESP_PROMISC
)) ||
623 (sc
->sc_ah
->ah_opmode
== ATH9K_M_IBSS
))
624 rfilt
|= ATH9K_RX_FILTER_BEACON
;
626 /* If in HOSTAP mode, want to enable reception of PSPOLL frames
628 if (sc
->sc_ah
->ah_opmode
== ATH9K_M_HOSTAP
)
629 rfilt
|= (ATH9K_RX_FILTER_BEACON
| ATH9K_RX_FILTER_PSPOLL
);
632 #undef RX_FILTER_PRESERVE
635 /* Enable the receive h/w following a reset. */
637 int ath_startrecv(struct ath_softc
*sc
)
639 struct ath_hal
*ah
= sc
->sc_ah
;
640 struct ath_buf
*bf
, *tbf
;
642 spin_lock_bh(&sc
->sc_rxbuflock
);
643 if (list_empty(&sc
->sc_rxbuf
))
646 sc
->sc_rxlink
= NULL
;
647 list_for_each_entry_safe(bf
, tbf
, &sc
->sc_rxbuf
, list
) {
648 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
649 /* restarting h/w, no need for holding descriptors */
650 bf
->bf_status
&= ~ATH_BUFSTATUS_STALE
;
652 * Upper layer may not be done with the frame yet so
653 * we can't just re-queue it to hardware. Remove it
654 * from h/w queue. It'll be re-queued when upper layer
655 * returns the frame and ath_rx_requeue_mpdu is called.
657 if (!(bf
->bf_status
& ATH_BUFSTATUS_FREE
)) {
662 /* chain descriptors */
663 ath_rx_buf_link(sc
, bf
);
666 /* We could have deleted elements so the list may be empty now */
667 if (list_empty(&sc
->sc_rxbuf
))
670 bf
= list_first_entry(&sc
->sc_rxbuf
, struct ath_buf
, list
);
671 ath9k_hw_putrxbuf(ah
, bf
->bf_daddr
);
672 ath9k_hw_rxena(ah
); /* enable recv descriptors */
675 spin_unlock_bh(&sc
->sc_rxbuflock
);
676 ath_opmode_init(sc
); /* set filters, etc. */
677 ath9k_hw_startpcureceive(ah
); /* re-enable PCU/DMA engine */
681 /* Disable the receive h/w in preparation for a reset. */
683 bool ath_stoprecv(struct ath_softc
*sc
)
685 struct ath_hal
*ah
= sc
->sc_ah
;
689 ath9k_hw_stoppcurecv(ah
); /* disable PCU */
690 ath9k_hw_setrxfilter(ah
, 0); /* clear recv filter */
691 stopped
= ath9k_hw_stopdmarecv(ah
); /* disable DMA engine */
692 mdelay(3); /* 3ms is long enough for 1 frame */
693 tsf
= ath9k_hw_gettsf64(ah
);
694 sc
->sc_rxlink
= NULL
; /* just in case */
698 /* Flush receive queue */
700 void ath_flushrecv(struct ath_softc
*sc
)
703 * ath_rx_tasklet may be used to handle rx interrupt and flush receive
704 * queue at the same time. Use a lock to serialize the access of rx
706 * ath_rx_tasklet cannot hold the spinlock while indicating packets.
707 * Instead, do not claim the spinlock but check for a flush in
708 * progress (see references to sc_rxflush)
710 spin_lock_bh(&sc
->sc_rxflushlock
);
711 sc
->sc_flags
|= SC_OP_RXFLUSH
;
713 ath_rx_tasklet(sc
, 1);
715 sc
->sc_flags
&= ~SC_OP_RXFLUSH
;
716 spin_unlock_bh(&sc
->sc_rxflushlock
);
719 /* Process an individual frame */
721 int ath_rx_input(struct ath_softc
*sc
,
725 struct ath_recv_status
*rx_status
,
726 enum ATH_RX_TYPE
*status
)
728 if (is_ampdu
&& (sc
->sc_flags
& SC_OP_RXAGGR
)) {
729 *status
= ATH_RX_CONSUMED
;
730 return ath_ampdu_input(sc
, an
, skb
, rx_status
);
732 *status
= ATH_RX_NON_CONSUMED
;
737 /* Process receive queue, as well as LED, etc. */
739 int ath_rx_tasklet(struct ath_softc
*sc
, int flush
)
741 #define PA2DESC(_sc, _pa) \
742 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
743 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
745 struct ath_buf
*bf
, *bf_held
= NULL
;
747 struct ieee80211_hdr
*hdr
;
748 struct sk_buff
*skb
= NULL
;
749 struct ath_recv_status rx_status
;
750 struct ath_hal
*ah
= sc
->sc_ah
;
751 int type
, rx_processed
= 0;
758 /* If handling rx interrupt and flush is in progress => exit */
759 if ((sc
->sc_flags
& SC_OP_RXFLUSH
) && (flush
== 0))
762 spin_lock_bh(&sc
->sc_rxbuflock
);
763 if (list_empty(&sc
->sc_rxbuf
)) {
764 sc
->sc_rxlink
= NULL
;
765 spin_unlock_bh(&sc
->sc_rxbuflock
);
769 bf
= list_first_entry(&sc
->sc_rxbuf
, struct ath_buf
, list
);
772 * There is a race condition that BH gets scheduled after sw
773 * writes RxE and before hw re-load the last descriptor to get
774 * the newly chained one. Software must keep the last DONE
775 * descriptor as a holding descriptor - software does so by
776 * marking it with the STALE flag.
778 if (bf
->bf_status
& ATH_BUFSTATUS_STALE
) {
780 if (list_is_last(&bf_held
->list
, &sc
->sc_rxbuf
)) {
782 * The holding descriptor is the last
783 * descriptor in queue. It's safe to
784 * remove the last holding descriptor
787 list_del(&bf_held
->list
);
788 bf_held
->bf_status
&= ~ATH_BUFSTATUS_STALE
;
789 sc
->sc_rxlink
= NULL
;
791 if (bf_held
->bf_status
& ATH_BUFSTATUS_FREE
) {
792 list_add_tail(&bf_held
->list
,
794 ath_rx_buf_link(sc
, bf_held
);
796 spin_unlock_bh(&sc
->sc_rxbuflock
);
799 bf
= list_entry(bf
->list
.next
, struct ath_buf
, list
);
806 * Must provide the virtual address of the current
807 * descriptor, the physical address, and the virtual
808 * address of the next descriptor in the h/w chain.
809 * This allows the HAL to look ahead to see if the
810 * hardware is done with a descriptor by checking the
811 * done bit in the following descriptor and the address
812 * of the current descriptor the DMA engine is working
813 * on. All this is necessary because of our use of
814 * a self-linked list to avoid rx overruns.
816 retval
= ath9k_hw_rxprocdesc(ah
,
819 PA2DESC(sc
, ds
->ds_link
),
821 if (retval
== -EINPROGRESS
) {
823 struct ath_desc
*tds
;
825 if (list_is_last(&bf
->list
, &sc
->sc_rxbuf
)) {
826 spin_unlock_bh(&sc
->sc_rxbuflock
);
830 tbf
= list_entry(bf
->list
.next
, struct ath_buf
, list
);
833 * On some hardware the descriptor status words could
834 * get corrupted, including the done bit. Because of
835 * this, check if the next descriptor's done bit is
838 * If the next descriptor's done bit is set, the current
839 * descriptor has been corrupted. Force s/w to discard
840 * this descriptor and continue...
844 retval
= ath9k_hw_rxprocdesc(ah
,
846 PA2DESC(sc
, tds
->ds_link
), 0);
847 if (retval
== -EINPROGRESS
) {
848 spin_unlock_bh(&sc
->sc_rxbuflock
);
853 /* XXX: we do not support frames spanning
854 * multiple descriptors */
855 bf
->bf_status
|= ATH_BUFSTATUS_DONE
;
858 if (skb
== NULL
) { /* XXX ??? can this happen */
859 spin_unlock_bh(&sc
->sc_rxbuflock
);
863 * Now we know it's a completed frame, we can indicate the
864 * frame. Remove the previous holding descriptor and leave
865 * this one in the queue as the new holding descriptor.
868 list_del(&bf_held
->list
);
869 bf_held
->bf_status
&= ~ATH_BUFSTATUS_STALE
;
870 if (bf_held
->bf_status
& ATH_BUFSTATUS_FREE
) {
871 list_add_tail(&bf_held
->list
, &sc
->sc_rxbuf
);
872 /* try to requeue this descriptor */
873 ath_rx_buf_link(sc
, bf_held
);
877 bf
->bf_status
|= ATH_BUFSTATUS_STALE
;
880 * Release the lock here in case ieee80211_input() return
881 * the frame immediately by calling ath_rx_mpdu_requeue().
883 spin_unlock_bh(&sc
->sc_rxbuflock
);
887 * If we're asked to flush receive queue, directly
888 * chain it back at the queue without processing it.
893 hdr
= (struct ieee80211_hdr
*)skb
->data
;
894 fc
= hdr
->frame_control
;
895 memset(&rx_status
, 0, sizeof(struct ath_recv_status
));
897 if (ds
->ds_rxstat
.rs_more
) {
899 * Frame spans multiple descriptors; this
900 * cannot happen yet as we don't support
901 * jumbograms. If not in monitor mode,
906 * Enable this if you want to see
907 * error frames in Monitor mode.
909 if (sc
->sc_ah
->ah_opmode
!= ATH9K_M_MONITOR
)
912 /* fall thru for monitor mode handling... */
913 } else if (ds
->ds_rxstat
.rs_status
!= 0) {
914 if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_CRC
)
915 rx_status
.flags
|= ATH_RX_FCS_ERROR
;
916 if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_PHY
) {
917 phyerr
= ds
->ds_rxstat
.rs_phyerr
& 0x1f;
921 if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_DECRYPT
) {
923 * Decrypt error. We only mark packet status
924 * here and always push up the frame up to let
925 * mac80211 handle the actual error case, be
926 * it no decryption key or real decryption
927 * error. This let us keep statistics there.
929 rx_status
.flags
|= ATH_RX_DECRYPT_ERROR
;
930 } else if (ds
->ds_rxstat
.rs_status
& ATH9K_RXERR_MIC
) {
932 * Demic error. We only mark frame status here
933 * and always push up the frame up to let
934 * mac80211 handle the actual error case. This
935 * let us keep statistics there. Hardware may
936 * post a false-positive MIC error.
938 if (ieee80211_is_ctl(fc
))
940 * Sometimes, we get invalid
941 * MIC failures on valid control frames.
942 * Remove these mic errors.
944 ds
->ds_rxstat
.rs_status
&=
947 rx_status
.flags
|= ATH_RX_MIC_ERROR
;
950 * Reject error frames with the exception of
951 * decryption and MIC failures. For monitor mode,
952 * we also ignore the CRC error.
954 if (sc
->sc_ah
->ah_opmode
== ATH9K_M_MONITOR
) {
955 if (ds
->ds_rxstat
.rs_status
&
956 ~(ATH9K_RXERR_DECRYPT
| ATH9K_RXERR_MIC
|
960 if (ds
->ds_rxstat
.rs_status
&
961 ~(ATH9K_RXERR_DECRYPT
| ATH9K_RXERR_MIC
)) {
967 * The status portion of the descriptor could get corrupted.
969 if (sc
->sc_rxbufsize
< ds
->ds_rxstat
.rs_datalen
)
972 * Sync and unmap the frame. At this point we're
973 * committed to passing the sk_buff somewhere so
974 * clear buf_skb; this means a new sk_buff must be
975 * allocated when the rx descriptor is setup again
976 * to receive another frame.
978 skb_put(skb
, ds
->ds_rxstat
.rs_datalen
);
979 skb
->protocol
= cpu_to_be16(ETH_P_CONTROL
);
980 rx_status
.tsf
= ath_extend_tsf(sc
, ds
->ds_rxstat
.rs_tstamp
);
982 sc
->sc_hwmap
[ds
->ds_rxstat
.rs_rate
].ieeerate
;
984 sc
->sc_hwmap
[ds
->ds_rxstat
.rs_rate
].rateKbps
;
985 rx_status
.ratecode
= ds
->ds_rxstat
.rs_rate
;
988 if (rx_status
.ratecode
& 0x80) {
989 /* TODO - add table to avoid division */
990 if (ds
->ds_rxstat
.rs_flags
& ATH9K_RX_2040
) {
991 rx_status
.flags
|= ATH_RX_40MHZ
;
993 (rx_status
.rateKbps
* 27) / 13;
995 if (ds
->ds_rxstat
.rs_flags
& ATH9K_RX_GI
)
997 (rx_status
.rateKbps
* 10) / 9;
999 rx_status
.flags
|= ATH_RX_SHORT_GI
;
1002 /* sc_noise_floor is only available when the station
1003 attaches to an AP, so we use a default value
1004 if we are not yet attached. */
1005 rx_status
.abs_rssi
=
1006 ds
->ds_rxstat
.rs_rssi
+ sc
->sc_ani
.sc_noise_floor
;
1008 pci_dma_sync_single_for_cpu(sc
->pdev
,
1011 PCI_DMA_FROMDEVICE
);
1012 pci_unmap_single(sc
->pdev
,
1015 PCI_DMA_FROMDEVICE
);
1017 /* XXX: Ah! make me more readable, use a helper */
1018 if (ah
->ah_caps
.hw_caps
& ATH9K_HW_CAP_HT
) {
1019 if (ds
->ds_rxstat
.rs_moreaggr
== 0) {
1020 rx_status
.rssictl
[0] =
1021 ds
->ds_rxstat
.rs_rssi_ctl0
;
1022 rx_status
.rssictl
[1] =
1023 ds
->ds_rxstat
.rs_rssi_ctl1
;
1024 rx_status
.rssictl
[2] =
1025 ds
->ds_rxstat
.rs_rssi_ctl2
;
1026 rx_status
.rssi
= ds
->ds_rxstat
.rs_rssi
;
1027 if (ds
->ds_rxstat
.rs_flags
& ATH9K_RX_2040
) {
1028 rx_status
.rssiextn
[0] =
1029 ds
->ds_rxstat
.rs_rssi_ext0
;
1030 rx_status
.rssiextn
[1] =
1031 ds
->ds_rxstat
.rs_rssi_ext1
;
1032 rx_status
.rssiextn
[2] =
1033 ds
->ds_rxstat
.rs_rssi_ext2
;
1035 ATH_RX_RSSI_EXTN_VALID
;
1037 rx_status
.flags
|= ATH_RX_RSSI_VALID
|
1038 ATH_RX_CHAIN_RSSI_VALID
;
1042 * Need to insert the "combined" rssi into the
1043 * status structure for upper layer processing
1045 rx_status
.rssi
= ds
->ds_rxstat
.rs_rssi
;
1046 rx_status
.flags
|= ATH_RX_RSSI_VALID
;
1049 /* Pass frames up to the stack. */
1051 type
= ath_rx_indicate(sc
, skb
,
1052 &rx_status
, ds
->ds_rxstat
.rs_keyix
);
1055 * change the default rx antenna if rx diversity chooses the
1056 * other antenna 3 times in a row.
1058 if (sc
->sc_defant
!= ds
->ds_rxstat
.rs_antenna
) {
1059 if (++sc
->sc_rxotherant
>= 3)
1060 ath_setdefantenna(sc
,
1061 ds
->ds_rxstat
.rs_antenna
);
1063 sc
->sc_rxotherant
= 0;
1066 #ifdef CONFIG_SLOW_ANT_DIV
1067 if ((rx_status
.flags
& ATH_RX_RSSI_VALID
) &&
1068 ieee80211_is_beacon(fc
)) {
1069 ath_slow_ant_div(&sc
->sc_antdiv
, hdr
, &ds
->ds_rxstat
);
1073 * For frames successfully indicated, the buffer will be
1074 * returned to us by upper layers by calling
1075 * ath_rx_mpdu_requeue, either synchronusly or asynchronously.
1076 * So we don't want to do it here in this loop.
1081 bf
->bf_status
|= ATH_BUFSTATUS_FREE
;
1085 DPRINTF(sc
, ATH_DBG_CONFIG
,
1086 "%s: Reset rx chain mask. "
1087 "Do internal reset\n", __func__
);
1089 ath_reset(sc
, false);
1096 /* Process ADDBA request in per-TID data structure */
1098 int ath_rx_aggr_start(struct ath_softc
*sc
,
1103 struct ath_arx_tid
*rxtid
;
1104 struct ath_node
*an
;
1105 struct ieee80211_hw
*hw
= sc
->hw
;
1106 struct ieee80211_supported_band
*sband
;
1109 spin_lock_bh(&sc
->node_lock
);
1110 an
= ath_node_find(sc
, (u8
*) addr
);
1111 spin_unlock_bh(&sc
->node_lock
);
1114 DPRINTF(sc
, ATH_DBG_AGGR
,
1115 "%s: Node not found to initialize RX aggregation\n",
1120 sband
= hw
->wiphy
->bands
[hw
->conf
.channel
->band
];
1121 buffersize
= IEEE80211_MIN_AMPDU_BUF
<<
1122 sband
->ht_info
.ampdu_factor
; /* FIXME */
1124 rxtid
= &an
->an_aggr
.rx
.tid
[tid
];
1126 spin_lock_bh(&rxtid
->tidlock
);
1127 if (sc
->sc_flags
& SC_OP_RXAGGR
) {
1128 /* Allow aggregation reception
1129 * Adjust rx BA window size. Peer might indicate a
1130 * zero buffer size for a _dont_care_ condition.
1133 rxtid
->baw_size
= min(buffersize
, rxtid
->baw_size
);
1135 /* set rx sequence number */
1136 rxtid
->seq_next
= *ssn
;
1138 /* Allocate the receive buffers for this TID */
1139 DPRINTF(sc
, ATH_DBG_AGGR
,
1140 "%s: Allcating rxbuffer for TID %d\n", __func__
, tid
);
1142 if (rxtid
->rxbuf
== NULL
) {
1144 * If the rxbuff is not NULL at this point, we *probably*
1145 * already allocated the buffer on a previous ADDBA,
1146 * and this is a subsequent ADDBA that got through.
1147 * Don't allocate, but use the value in the pointer,
1148 * we zero it out when we de-allocate.
1150 rxtid
->rxbuf
= kmalloc(ATH_TID_MAX_BUFS
*
1151 sizeof(struct ath_rxbuf
), GFP_ATOMIC
);
1153 if (rxtid
->rxbuf
== NULL
) {
1154 DPRINTF(sc
, ATH_DBG_AGGR
,
1155 "%s: Unable to allocate RX buffer, "
1156 "refusing ADDBA\n", __func__
);
1158 /* Ensure the memory is zeroed out (all internal
1159 * pointers are null) */
1160 memset(rxtid
->rxbuf
, 0, ATH_TID_MAX_BUFS
*
1161 sizeof(struct ath_rxbuf
));
1162 DPRINTF(sc
, ATH_DBG_AGGR
,
1163 "%s: Allocated @%p\n", __func__
, rxtid
->rxbuf
);
1165 /* Allow aggregation reception */
1166 rxtid
->addba_exchangecomplete
= 1;
1169 spin_unlock_bh(&rxtid
->tidlock
);
1176 int ath_rx_aggr_stop(struct ath_softc
*sc
,
1180 struct ath_node
*an
;
1182 spin_lock_bh(&sc
->node_lock
);
1183 an
= ath_node_find(sc
, (u8
*) addr
);
1184 spin_unlock_bh(&sc
->node_lock
);
1187 DPRINTF(sc
, ATH_DBG_AGGR
,
1188 "%s: RX aggr stop for non-existent node\n", __func__
);
1192 ath_rx_aggr_teardown(sc
, an
, tid
);
1196 /* Rx aggregation tear down */
1198 void ath_rx_aggr_teardown(struct ath_softc
*sc
,
1199 struct ath_node
*an
, u8 tid
)
1201 struct ath_arx_tid
*rxtid
= &an
->an_aggr
.rx
.tid
[tid
];
1203 if (!rxtid
->addba_exchangecomplete
)
1206 del_timer_sync(&rxtid
->timer
);
1207 ath_rx_flush_tid(sc
, rxtid
, 0);
1208 rxtid
->addba_exchangecomplete
= 0;
1210 /* De-allocate the receive buffer array allocated when addba started */
1213 DPRINTF(sc
, ATH_DBG_AGGR
,
1214 "%s: Deallocating TID %d rxbuff @%p\n",
1215 __func__
, tid
, rxtid
->rxbuf
);
1216 kfree(rxtid
->rxbuf
);
1218 /* Set pointer to null to avoid reuse*/
1219 rxtid
->rxbuf
= NULL
;
1223 /* Initialize per-node receive state */
1225 void ath_rx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
1227 if (sc
->sc_flags
& SC_OP_RXAGGR
) {
1228 struct ath_arx_tid
*rxtid
;
1231 /* Init per tid rx state */
1232 for (tidno
= 0, rxtid
= &an
->an_aggr
.rx
.tid
[tidno
];
1233 tidno
< WME_NUM_TID
;
1236 rxtid
->seq_reset
= 1;
1237 rxtid
->seq_next
= 0;
1238 rxtid
->baw_size
= WME_MAX_BA
;
1239 rxtid
->baw_head
= rxtid
->baw_tail
= 0;
1242 * Ensure the buffer pointer is null at this point
1243 * (needs to be allocated when addba is received)
1246 rxtid
->rxbuf
= NULL
;
1247 setup_timer(&rxtid
->timer
, ath_rx_timer
,
1248 (unsigned long)rxtid
);
1249 spin_lock_init(&rxtid
->tidlock
);
1252 rxtid
->addba_exchangecomplete
= 0;
1257 void ath_rx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
1259 if (sc
->sc_flags
& SC_OP_RXAGGR
) {
1260 struct ath_arx_tid
*rxtid
;
1263 /* Init per tid rx state */
1264 for (tidno
= 0, rxtid
= &an
->an_aggr
.rx
.tid
[tidno
];
1265 tidno
< WME_NUM_TID
;
1268 if (!rxtid
->addba_exchangecomplete
)
1271 /* must cancel timer first */
1272 del_timer_sync(&rxtid
->timer
);
1274 /* drop any pending sub-frames */
1275 ath_rx_flush_tid(sc
, rxtid
, 1);
1277 for (i
= 0; i
< ATH_TID_MAX_BUFS
; i
++)
1278 ASSERT(rxtid
->rxbuf
[i
].rx_wbuf
== NULL
);
1280 rxtid
->addba_exchangecomplete
= 0;
1286 /* Cleanup per-node receive state */
1288 void ath_rx_node_free(struct ath_softc
*sc
, struct ath_node
*an
)
1290 ath_rx_node_cleanup(sc
, an
);