3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 Copyright (c) 2009 Albert Herranz <albert_herranz@yahoo.es>
14 Some parts of the code in this file are derived from the ipw2200
15 driver Copyright(c) 2003 - 2004 Intel Corporation.
17 This program is free software; you can redistribute it and/or modify
18 it under the terms of the GNU General Public License as published by
19 the Free Software Foundation; either version 2 of the License, or
20 (at your option) any later version.
22 This program is distributed in the hope that it will be useful,
23 but WITHOUT ANY WARRANTY; without even the implied warranty of
24 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 GNU General Public License for more details.
27 You should have received a copy of the GNU General Public License
28 along with this program; see the file COPYING. If not, write to
29 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
30 Boston, MA 02110-1301, USA.
34 #include <linux/delay.h>
35 #include <linux/init.h>
36 #include <linux/moduleparam.h>
37 #include <linux/if_arp.h>
38 #include <linux/etherdevice.h>
39 #include <linux/firmware.h>
40 #include <linux/wireless.h>
41 #include <linux/workqueue.h>
42 #include <linux/skbuff.h>
44 #include <linux/dma-mapping.h>
45 #include <asm/unaligned.h>
50 #include "phy_common.h"
60 #include <linux/mmc/sdio_func.h>
62 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
63 MODULE_AUTHOR("Martin Langer");
64 MODULE_AUTHOR("Stefano Brivio");
65 MODULE_AUTHOR("Michael Buesch");
66 MODULE_AUTHOR("Gábor Stefanik");
67 MODULE_LICENSE("GPL");
69 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID
);
72 static int modparam_bad_frames_preempt
;
73 module_param_named(bad_frames_preempt
, modparam_bad_frames_preempt
, int, 0444);
74 MODULE_PARM_DESC(bad_frames_preempt
,
75 "enable(1) / disable(0) Bad Frames Preemption");
77 static char modparam_fwpostfix
[16];
78 module_param_string(fwpostfix
, modparam_fwpostfix
, 16, 0444);
79 MODULE_PARM_DESC(fwpostfix
, "Postfix for the .fw files to load.");
81 static int modparam_hwpctl
;
82 module_param_named(hwpctl
, modparam_hwpctl
, int, 0444);
83 MODULE_PARM_DESC(hwpctl
, "Enable hardware-side power control (default off)");
85 static int modparam_nohwcrypt
;
86 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
87 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
89 static int modparam_hwtkip
;
90 module_param_named(hwtkip
, modparam_hwtkip
, int, 0444);
91 MODULE_PARM_DESC(hwtkip
, "Enable hardware tkip.");
93 static int modparam_qos
= 1;
94 module_param_named(qos
, modparam_qos
, int, 0444);
95 MODULE_PARM_DESC(qos
, "Enable QOS support (default on)");
97 static int modparam_btcoex
= 1;
98 module_param_named(btcoex
, modparam_btcoex
, int, 0444);
99 MODULE_PARM_DESC(btcoex
, "Enable Bluetooth coexistence (default on)");
101 int b43_modparam_verbose
= B43_VERBOSITY_DEFAULT
;
102 module_param_named(verbose
, b43_modparam_verbose
, int, 0644);
103 MODULE_PARM_DESC(verbose
, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
105 static int modparam_pio
;
106 module_param_named(pio
, modparam_pio
, int, 0444);
107 MODULE_PARM_DESC(pio
, "enable(1) / disable(0) PIO mode");
109 static const struct ssb_device_id b43_ssb_tbl
[] = {
110 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 5),
111 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 6),
112 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 7),
113 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 9),
114 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 10),
115 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 11),
116 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 13),
117 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 15),
118 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 16),
122 MODULE_DEVICE_TABLE(ssb
, b43_ssb_tbl
);
124 /* Channel and ratetables are shared for all devices.
125 * They can't be const, because ieee80211 puts some precalculated
126 * data in there. This data is the same for all devices, so we don't
127 * get concurrency issues */
128 #define RATETAB_ENT(_rateid, _flags) \
130 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
131 .hw_value = (_rateid), \
136 * NOTE: When changing this, sync with xmit.c's
137 * b43_plcp_get_bitrate_idx_* functions!
139 static struct ieee80211_rate __b43_ratetable
[] = {
140 RATETAB_ENT(B43_CCK_RATE_1MB
, 0),
141 RATETAB_ENT(B43_CCK_RATE_2MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
142 RATETAB_ENT(B43_CCK_RATE_5MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
143 RATETAB_ENT(B43_CCK_RATE_11MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
144 RATETAB_ENT(B43_OFDM_RATE_6MB
, 0),
145 RATETAB_ENT(B43_OFDM_RATE_9MB
, 0),
146 RATETAB_ENT(B43_OFDM_RATE_12MB
, 0),
147 RATETAB_ENT(B43_OFDM_RATE_18MB
, 0),
148 RATETAB_ENT(B43_OFDM_RATE_24MB
, 0),
149 RATETAB_ENT(B43_OFDM_RATE_36MB
, 0),
150 RATETAB_ENT(B43_OFDM_RATE_48MB
, 0),
151 RATETAB_ENT(B43_OFDM_RATE_54MB
, 0),
154 #define b43_a_ratetable (__b43_ratetable + 4)
155 #define b43_a_ratetable_size 8
156 #define b43_b_ratetable (__b43_ratetable + 0)
157 #define b43_b_ratetable_size 4
158 #define b43_g_ratetable (__b43_ratetable + 0)
159 #define b43_g_ratetable_size 12
161 #define CHAN4G(_channel, _freq, _flags) { \
162 .band = IEEE80211_BAND_2GHZ, \
163 .center_freq = (_freq), \
164 .hw_value = (_channel), \
166 .max_antenna_gain = 0, \
169 static struct ieee80211_channel b43_2ghz_chantable
[] = {
187 #define CHAN5G(_channel, _flags) { \
188 .band = IEEE80211_BAND_5GHZ, \
189 .center_freq = 5000 + (5 * (_channel)), \
190 .hw_value = (_channel), \
192 .max_antenna_gain = 0, \
195 static struct ieee80211_channel b43_5ghz_nphy_chantable
[] = {
196 CHAN5G(32, 0), CHAN5G(34, 0),
197 CHAN5G(36, 0), CHAN5G(38, 0),
198 CHAN5G(40, 0), CHAN5G(42, 0),
199 CHAN5G(44, 0), CHAN5G(46, 0),
200 CHAN5G(48, 0), CHAN5G(50, 0),
201 CHAN5G(52, 0), CHAN5G(54, 0),
202 CHAN5G(56, 0), CHAN5G(58, 0),
203 CHAN5G(60, 0), CHAN5G(62, 0),
204 CHAN5G(64, 0), CHAN5G(66, 0),
205 CHAN5G(68, 0), CHAN5G(70, 0),
206 CHAN5G(72, 0), CHAN5G(74, 0),
207 CHAN5G(76, 0), CHAN5G(78, 0),
208 CHAN5G(80, 0), CHAN5G(82, 0),
209 CHAN5G(84, 0), CHAN5G(86, 0),
210 CHAN5G(88, 0), CHAN5G(90, 0),
211 CHAN5G(92, 0), CHAN5G(94, 0),
212 CHAN5G(96, 0), CHAN5G(98, 0),
213 CHAN5G(100, 0), CHAN5G(102, 0),
214 CHAN5G(104, 0), CHAN5G(106, 0),
215 CHAN5G(108, 0), CHAN5G(110, 0),
216 CHAN5G(112, 0), CHAN5G(114, 0),
217 CHAN5G(116, 0), CHAN5G(118, 0),
218 CHAN5G(120, 0), CHAN5G(122, 0),
219 CHAN5G(124, 0), CHAN5G(126, 0),
220 CHAN5G(128, 0), CHAN5G(130, 0),
221 CHAN5G(132, 0), CHAN5G(134, 0),
222 CHAN5G(136, 0), CHAN5G(138, 0),
223 CHAN5G(140, 0), CHAN5G(142, 0),
224 CHAN5G(144, 0), CHAN5G(145, 0),
225 CHAN5G(146, 0), CHAN5G(147, 0),
226 CHAN5G(148, 0), CHAN5G(149, 0),
227 CHAN5G(150, 0), CHAN5G(151, 0),
228 CHAN5G(152, 0), CHAN5G(153, 0),
229 CHAN5G(154, 0), CHAN5G(155, 0),
230 CHAN5G(156, 0), CHAN5G(157, 0),
231 CHAN5G(158, 0), CHAN5G(159, 0),
232 CHAN5G(160, 0), CHAN5G(161, 0),
233 CHAN5G(162, 0), CHAN5G(163, 0),
234 CHAN5G(164, 0), CHAN5G(165, 0),
235 CHAN5G(166, 0), CHAN5G(168, 0),
236 CHAN5G(170, 0), CHAN5G(172, 0),
237 CHAN5G(174, 0), CHAN5G(176, 0),
238 CHAN5G(178, 0), CHAN5G(180, 0),
239 CHAN5G(182, 0), CHAN5G(184, 0),
240 CHAN5G(186, 0), CHAN5G(188, 0),
241 CHAN5G(190, 0), CHAN5G(192, 0),
242 CHAN5G(194, 0), CHAN5G(196, 0),
243 CHAN5G(198, 0), CHAN5G(200, 0),
244 CHAN5G(202, 0), CHAN5G(204, 0),
245 CHAN5G(206, 0), CHAN5G(208, 0),
246 CHAN5G(210, 0), CHAN5G(212, 0),
247 CHAN5G(214, 0), CHAN5G(216, 0),
248 CHAN5G(218, 0), CHAN5G(220, 0),
249 CHAN5G(222, 0), CHAN5G(224, 0),
250 CHAN5G(226, 0), CHAN5G(228, 0),
253 static struct ieee80211_channel b43_5ghz_aphy_chantable
[] = {
254 CHAN5G(34, 0), CHAN5G(36, 0),
255 CHAN5G(38, 0), CHAN5G(40, 0),
256 CHAN5G(42, 0), CHAN5G(44, 0),
257 CHAN5G(46, 0), CHAN5G(48, 0),
258 CHAN5G(52, 0), CHAN5G(56, 0),
259 CHAN5G(60, 0), CHAN5G(64, 0),
260 CHAN5G(100, 0), CHAN5G(104, 0),
261 CHAN5G(108, 0), CHAN5G(112, 0),
262 CHAN5G(116, 0), CHAN5G(120, 0),
263 CHAN5G(124, 0), CHAN5G(128, 0),
264 CHAN5G(132, 0), CHAN5G(136, 0),
265 CHAN5G(140, 0), CHAN5G(149, 0),
266 CHAN5G(153, 0), CHAN5G(157, 0),
267 CHAN5G(161, 0), CHAN5G(165, 0),
268 CHAN5G(184, 0), CHAN5G(188, 0),
269 CHAN5G(192, 0), CHAN5G(196, 0),
270 CHAN5G(200, 0), CHAN5G(204, 0),
271 CHAN5G(208, 0), CHAN5G(212, 0),
276 static struct ieee80211_supported_band b43_band_5GHz_nphy
= {
277 .band
= IEEE80211_BAND_5GHZ
,
278 .channels
= b43_5ghz_nphy_chantable
,
279 .n_channels
= ARRAY_SIZE(b43_5ghz_nphy_chantable
),
280 .bitrates
= b43_a_ratetable
,
281 .n_bitrates
= b43_a_ratetable_size
,
284 static struct ieee80211_supported_band b43_band_5GHz_aphy
= {
285 .band
= IEEE80211_BAND_5GHZ
,
286 .channels
= b43_5ghz_aphy_chantable
,
287 .n_channels
= ARRAY_SIZE(b43_5ghz_aphy_chantable
),
288 .bitrates
= b43_a_ratetable
,
289 .n_bitrates
= b43_a_ratetable_size
,
292 static struct ieee80211_supported_band b43_band_2GHz
= {
293 .band
= IEEE80211_BAND_2GHZ
,
294 .channels
= b43_2ghz_chantable
,
295 .n_channels
= ARRAY_SIZE(b43_2ghz_chantable
),
296 .bitrates
= b43_g_ratetable
,
297 .n_bitrates
= b43_g_ratetable_size
,
300 static void b43_wireless_core_exit(struct b43_wldev
*dev
);
301 static int b43_wireless_core_init(struct b43_wldev
*dev
);
302 static struct b43_wldev
* b43_wireless_core_stop(struct b43_wldev
*dev
);
303 static int b43_wireless_core_start(struct b43_wldev
*dev
);
305 static int b43_ratelimit(struct b43_wl
*wl
)
307 if (!wl
|| !wl
->current_dev
)
309 if (b43_status(wl
->current_dev
) < B43_STAT_STARTED
)
311 /* We are up and running.
312 * Ratelimit the messages to avoid DoS over the net. */
313 return net_ratelimit();
316 void b43info(struct b43_wl
*wl
, const char *fmt
, ...)
320 if (b43_modparam_verbose
< B43_VERBOSITY_INFO
)
322 if (!b43_ratelimit(wl
))
325 printk(KERN_INFO
"b43-%s: ",
326 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
331 void b43err(struct b43_wl
*wl
, const char *fmt
, ...)
335 if (b43_modparam_verbose
< B43_VERBOSITY_ERROR
)
337 if (!b43_ratelimit(wl
))
340 printk(KERN_ERR
"b43-%s ERROR: ",
341 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
346 void b43warn(struct b43_wl
*wl
, const char *fmt
, ...)
350 if (b43_modparam_verbose
< B43_VERBOSITY_WARN
)
352 if (!b43_ratelimit(wl
))
355 printk(KERN_WARNING
"b43-%s warning: ",
356 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
361 void b43dbg(struct b43_wl
*wl
, const char *fmt
, ...)
365 if (b43_modparam_verbose
< B43_VERBOSITY_DEBUG
)
368 printk(KERN_DEBUG
"b43-%s debug: ",
369 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
374 static void b43_ram_write(struct b43_wldev
*dev
, u16 offset
, u32 val
)
378 B43_WARN_ON(offset
% 4 != 0);
380 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
381 if (macctl
& B43_MACCTL_BE
)
384 b43_write32(dev
, B43_MMIO_RAM_CONTROL
, offset
);
386 b43_write32(dev
, B43_MMIO_RAM_DATA
, val
);
389 static inline void b43_shm_control_word(struct b43_wldev
*dev
,
390 u16 routing
, u16 offset
)
394 /* "offset" is the WORD offset. */
398 b43_write32(dev
, B43_MMIO_SHM_CONTROL
, control
);
401 u32
b43_shm_read32(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
405 if (routing
== B43_SHM_SHARED
) {
406 B43_WARN_ON(offset
& 0x0001);
407 if (offset
& 0x0003) {
408 /* Unaligned access */
409 b43_shm_control_word(dev
, routing
, offset
>> 2);
410 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
411 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
412 ret
|= ((u32
)b43_read16(dev
, B43_MMIO_SHM_DATA
)) << 16;
418 b43_shm_control_word(dev
, routing
, offset
);
419 ret
= b43_read32(dev
, B43_MMIO_SHM_DATA
);
424 u16
b43_shm_read16(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
428 if (routing
== B43_SHM_SHARED
) {
429 B43_WARN_ON(offset
& 0x0001);
430 if (offset
& 0x0003) {
431 /* Unaligned access */
432 b43_shm_control_word(dev
, routing
, offset
>> 2);
433 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
439 b43_shm_control_word(dev
, routing
, offset
);
440 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA
);
445 void b43_shm_write32(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u32 value
)
447 if (routing
== B43_SHM_SHARED
) {
448 B43_WARN_ON(offset
& 0x0001);
449 if (offset
& 0x0003) {
450 /* Unaligned access */
451 b43_shm_control_word(dev
, routing
, offset
>> 2);
452 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
,
454 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
455 b43_write16(dev
, B43_MMIO_SHM_DATA
,
456 (value
>> 16) & 0xFFFF);
461 b43_shm_control_word(dev
, routing
, offset
);
462 b43_write32(dev
, B43_MMIO_SHM_DATA
, value
);
465 void b43_shm_write16(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u16 value
)
467 if (routing
== B43_SHM_SHARED
) {
468 B43_WARN_ON(offset
& 0x0001);
469 if (offset
& 0x0003) {
470 /* Unaligned access */
471 b43_shm_control_word(dev
, routing
, offset
>> 2);
472 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
, value
);
477 b43_shm_control_word(dev
, routing
, offset
);
478 b43_write16(dev
, B43_MMIO_SHM_DATA
, value
);
482 u64
b43_hf_read(struct b43_wldev
*dev
)
486 ret
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFHI
);
488 ret
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFMI
);
490 ret
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFLO
);
495 /* Write HostFlags */
496 void b43_hf_write(struct b43_wldev
*dev
, u64 value
)
500 lo
= (value
& 0x00000000FFFFULL
);
501 mi
= (value
& 0x0000FFFF0000ULL
) >> 16;
502 hi
= (value
& 0xFFFF00000000ULL
) >> 32;
503 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFLO
, lo
);
504 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFMI
, mi
);
505 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFHI
, hi
);
508 /* Read the firmware capabilities bitmask (Opensource firmware only) */
509 static u16
b43_fwcapa_read(struct b43_wldev
*dev
)
511 B43_WARN_ON(!dev
->fw
.opensource
);
512 return b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_FWCAPA
);
515 void b43_tsf_read(struct b43_wldev
*dev
, u64
*tsf
)
519 B43_WARN_ON(dev
->dev
->id
.revision
< 3);
521 /* The hardware guarantees us an atomic read, if we
522 * read the low register first. */
523 low
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
);
524 high
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
);
531 static void b43_time_lock(struct b43_wldev
*dev
)
535 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
536 macctl
|= B43_MACCTL_TBTTHOLD
;
537 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
538 /* Commit the write */
539 b43_read32(dev
, B43_MMIO_MACCTL
);
542 static void b43_time_unlock(struct b43_wldev
*dev
)
546 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
547 macctl
&= ~B43_MACCTL_TBTTHOLD
;
548 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
549 /* Commit the write */
550 b43_read32(dev
, B43_MMIO_MACCTL
);
553 static void b43_tsf_write_locked(struct b43_wldev
*dev
, u64 tsf
)
557 B43_WARN_ON(dev
->dev
->id
.revision
< 3);
561 /* The hardware guarantees us an atomic write, if we
562 * write the low register first. */
563 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
, low
);
565 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
, high
);
569 void b43_tsf_write(struct b43_wldev
*dev
, u64 tsf
)
572 b43_tsf_write_locked(dev
, tsf
);
573 b43_time_unlock(dev
);
577 void b43_macfilter_set(struct b43_wldev
*dev
, u16 offset
, const u8
*mac
)
579 static const u8 zero_addr
[ETH_ALEN
] = { 0 };
586 b43_write16(dev
, B43_MMIO_MACFILTER_CONTROL
, offset
);
590 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
593 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
596 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
599 static void b43_write_mac_bssid_templates(struct b43_wldev
*dev
)
603 u8 mac_bssid
[ETH_ALEN
* 2];
607 bssid
= dev
->wl
->bssid
;
608 mac
= dev
->wl
->mac_addr
;
610 b43_macfilter_set(dev
, B43_MACFILTER_BSSID
, bssid
);
612 memcpy(mac_bssid
, mac
, ETH_ALEN
);
613 memcpy(mac_bssid
+ ETH_ALEN
, bssid
, ETH_ALEN
);
615 /* Write our MAC address and BSSID to template ram */
616 for (i
= 0; i
< ARRAY_SIZE(mac_bssid
); i
+= sizeof(u32
)) {
617 tmp
= (u32
) (mac_bssid
[i
+ 0]);
618 tmp
|= (u32
) (mac_bssid
[i
+ 1]) << 8;
619 tmp
|= (u32
) (mac_bssid
[i
+ 2]) << 16;
620 tmp
|= (u32
) (mac_bssid
[i
+ 3]) << 24;
621 b43_ram_write(dev
, 0x20 + i
, tmp
);
625 static void b43_upload_card_macaddress(struct b43_wldev
*dev
)
627 b43_write_mac_bssid_templates(dev
);
628 b43_macfilter_set(dev
, B43_MACFILTER_SELF
, dev
->wl
->mac_addr
);
631 static void b43_set_slot_time(struct b43_wldev
*dev
, u16 slot_time
)
633 /* slot_time is in usec. */
634 if (dev
->phy
.type
!= B43_PHYTYPE_G
)
636 b43_write16(dev
, 0x684, 510 + slot_time
);
637 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0010, slot_time
);
640 static void b43_short_slot_timing_enable(struct b43_wldev
*dev
)
642 b43_set_slot_time(dev
, 9);
645 static void b43_short_slot_timing_disable(struct b43_wldev
*dev
)
647 b43_set_slot_time(dev
, 20);
650 /* DummyTransmission function, as documented on
651 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
653 void b43_dummy_transmission(struct b43_wldev
*dev
, bool ofdm
, bool pa_on
)
655 struct b43_phy
*phy
= &dev
->phy
;
656 unsigned int i
, max_loop
;
668 buffer
[0] = 0x000201CC;
671 buffer
[0] = 0x000B846E;
674 for (i
= 0; i
< 5; i
++)
675 b43_ram_write(dev
, i
* 4, buffer
[i
]);
677 b43_write16(dev
, 0x0568, 0x0000);
678 if (dev
->dev
->id
.revision
< 11)
679 b43_write16(dev
, 0x07C0, 0x0000);
681 b43_write16(dev
, 0x07C0, 0x0100);
682 value
= (ofdm
? 0x41 : 0x40);
683 b43_write16(dev
, 0x050C, value
);
684 if ((phy
->type
== B43_PHYTYPE_N
) || (phy
->type
== B43_PHYTYPE_LP
))
685 b43_write16(dev
, 0x0514, 0x1A02);
686 b43_write16(dev
, 0x0508, 0x0000);
687 b43_write16(dev
, 0x050A, 0x0000);
688 b43_write16(dev
, 0x054C, 0x0000);
689 b43_write16(dev
, 0x056A, 0x0014);
690 b43_write16(dev
, 0x0568, 0x0826);
691 b43_write16(dev
, 0x0500, 0x0000);
692 if (!pa_on
&& (phy
->type
== B43_PHYTYPE_N
)) {
698 b43_write16(dev
, 0x0502, 0x00D0);
701 b43_write16(dev
, 0x0502, 0x0050);
704 b43_write16(dev
, 0x0502, 0x0030);
707 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
708 b43_radio_write16(dev
, 0x0051, 0x0017);
709 for (i
= 0x00; i
< max_loop
; i
++) {
710 value
= b43_read16(dev
, 0x050E);
715 for (i
= 0x00; i
< 0x0A; i
++) {
716 value
= b43_read16(dev
, 0x050E);
721 for (i
= 0x00; i
< 0x19; i
++) {
722 value
= b43_read16(dev
, 0x0690);
723 if (!(value
& 0x0100))
727 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
728 b43_radio_write16(dev
, 0x0051, 0x0037);
731 static void key_write(struct b43_wldev
*dev
,
732 u8 index
, u8 algorithm
, const u8
*key
)
739 /* Key index/algo block */
740 kidx
= b43_kidx_to_fw(dev
, index
);
741 value
= ((kidx
<< 4) | algorithm
);
742 b43_shm_write16(dev
, B43_SHM_SHARED
,
743 B43_SHM_SH_KEYIDXBLOCK
+ (kidx
* 2), value
);
745 /* Write the key to the Key Table Pointer offset */
746 offset
= dev
->ktp
+ (index
* B43_SEC_KEYSIZE
);
747 for (i
= 0; i
< B43_SEC_KEYSIZE
; i
+= 2) {
749 value
|= (u16
) (key
[i
+ 1]) << 8;
750 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
, value
);
754 static void keymac_write(struct b43_wldev
*dev
, u8 index
, const u8
*addr
)
756 u32 addrtmp
[2] = { 0, 0, };
757 u8 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
759 if (b43_new_kidx_api(dev
))
760 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
762 B43_WARN_ON(index
< pairwise_keys_start
);
763 /* We have four default TX keys and possibly four default RX keys.
764 * Physical mac 0 is mapped to physical key 4 or 8, depending
765 * on the firmware version.
766 * So we must adjust the index here.
768 index
-= pairwise_keys_start
;
769 B43_WARN_ON(index
>= B43_NR_PAIRWISE_KEYS
);
772 addrtmp
[0] = addr
[0];
773 addrtmp
[0] |= ((u32
) (addr
[1]) << 8);
774 addrtmp
[0] |= ((u32
) (addr
[2]) << 16);
775 addrtmp
[0] |= ((u32
) (addr
[3]) << 24);
776 addrtmp
[1] = addr
[4];
777 addrtmp
[1] |= ((u32
) (addr
[5]) << 8);
780 /* Receive match transmitter address (RCMTA) mechanism */
781 b43_shm_write32(dev
, B43_SHM_RCMTA
,
782 (index
* 2) + 0, addrtmp
[0]);
783 b43_shm_write16(dev
, B43_SHM_RCMTA
,
784 (index
* 2) + 1, addrtmp
[1]);
787 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
788 * When a packet is received, the iv32 is checked.
789 * - if it doesn't the packet is returned without modification (and software
790 * decryption can be done). That's what happen when iv16 wrap.
791 * - if it does, the rc4 key is computed, and decryption is tried.
792 * Either it will success and B43_RX_MAC_DEC is returned,
793 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
794 * and the packet is not usable (it got modified by the ucode).
795 * So in order to never have B43_RX_MAC_DECERR, we should provide
796 * a iv32 and phase1key that match. Because we drop packets in case of
797 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
798 * packets will be lost without higher layer knowing (ie no resync possible
801 * NOTE : this should support 50 key like RCMTA because
802 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
804 static void rx_tkip_phase1_write(struct b43_wldev
*dev
, u8 index
, u32 iv32
,
809 u8 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
811 if (!modparam_hwtkip
)
814 if (b43_new_kidx_api(dev
))
815 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
817 B43_WARN_ON(index
< pairwise_keys_start
);
818 /* We have four default TX keys and possibly four default RX keys.
819 * Physical mac 0 is mapped to physical key 4 or 8, depending
820 * on the firmware version.
821 * So we must adjust the index here.
823 index
-= pairwise_keys_start
;
824 B43_WARN_ON(index
>= B43_NR_PAIRWISE_KEYS
);
826 if (b43_debug(dev
, B43_DBG_KEYS
)) {
827 b43dbg(dev
->wl
, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
830 /* Write the key to the RX tkip shared mem */
831 offset
= B43_SHM_SH_TKIPTSCTTAK
+ index
* (10 + 4);
832 for (i
= 0; i
< 10; i
+= 2) {
833 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
,
834 phase1key
? phase1key
[i
/ 2] : 0);
836 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
, iv32
);
837 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
+ 2, iv32
>> 16);
840 static void b43_op_update_tkip_key(struct ieee80211_hw
*hw
,
841 struct ieee80211_key_conf
*keyconf
, const u8
*addr
,
842 u32 iv32
, u16
*phase1key
)
844 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
845 struct b43_wldev
*dev
;
846 int index
= keyconf
->hw_key_idx
;
848 if (B43_WARN_ON(!modparam_hwtkip
))
851 mutex_lock(&wl
->mutex
);
853 dev
= wl
->current_dev
;
854 if (!dev
|| b43_status(dev
) < B43_STAT_INITIALIZED
)
857 keymac_write(dev
, index
, NULL
); /* First zero out mac to avoid race */
859 rx_tkip_phase1_write(dev
, index
, iv32
, phase1key
);
860 keymac_write(dev
, index
, addr
);
863 mutex_unlock(&wl
->mutex
);
866 static void do_key_write(struct b43_wldev
*dev
,
867 u8 index
, u8 algorithm
,
868 const u8
*key
, size_t key_len
, const u8
*mac_addr
)
870 u8 buf
[B43_SEC_KEYSIZE
] = { 0, };
871 u8 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
873 if (b43_new_kidx_api(dev
))
874 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
876 B43_WARN_ON(index
>= ARRAY_SIZE(dev
->key
));
877 B43_WARN_ON(key_len
> B43_SEC_KEYSIZE
);
879 if (index
>= pairwise_keys_start
)
880 keymac_write(dev
, index
, NULL
); /* First zero out mac. */
881 if (algorithm
== B43_SEC_ALGO_TKIP
) {
883 * We should provide an initial iv32, phase1key pair.
884 * We could start with iv32=0 and compute the corresponding
885 * phase1key, but this means calling ieee80211_get_tkip_key
886 * with a fake skb (or export other tkip function).
887 * Because we are lazy we hope iv32 won't start with
888 * 0xffffffff and let's b43_op_update_tkip_key provide a
891 rx_tkip_phase1_write(dev
, index
, 0xffffffff, (u16
*)buf
);
892 } else if (index
>= pairwise_keys_start
) /* clear it */
893 rx_tkip_phase1_write(dev
, index
, 0, NULL
);
895 memcpy(buf
, key
, key_len
);
896 key_write(dev
, index
, algorithm
, buf
);
897 if (index
>= pairwise_keys_start
)
898 keymac_write(dev
, index
, mac_addr
);
900 dev
->key
[index
].algorithm
= algorithm
;
903 static int b43_key_write(struct b43_wldev
*dev
,
904 int index
, u8 algorithm
,
905 const u8
*key
, size_t key_len
,
907 struct ieee80211_key_conf
*keyconf
)
910 int pairwise_keys_start
;
912 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
913 * - Temporal Encryption Key (128 bits)
914 * - Temporal Authenticator Tx MIC Key (64 bits)
915 * - Temporal Authenticator Rx MIC Key (64 bits)
917 * Hardware only store TEK
919 if (algorithm
== B43_SEC_ALGO_TKIP
&& key_len
== 32)
921 if (key_len
> B43_SEC_KEYSIZE
)
923 for (i
= 0; i
< ARRAY_SIZE(dev
->key
); i
++) {
924 /* Check that we don't already have this key. */
925 B43_WARN_ON(dev
->key
[i
].keyconf
== keyconf
);
928 /* Pairwise key. Get an empty slot for the key. */
929 if (b43_new_kidx_api(dev
))
930 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
932 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
933 for (i
= pairwise_keys_start
;
934 i
< pairwise_keys_start
+ B43_NR_PAIRWISE_KEYS
;
936 B43_WARN_ON(i
>= ARRAY_SIZE(dev
->key
));
937 if (!dev
->key
[i
].keyconf
) {
944 b43warn(dev
->wl
, "Out of hardware key memory\n");
948 B43_WARN_ON(index
> 3);
950 do_key_write(dev
, index
, algorithm
, key
, key_len
, mac_addr
);
951 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
953 B43_WARN_ON(mac_addr
);
954 do_key_write(dev
, index
+ 4, algorithm
, key
, key_len
, NULL
);
956 keyconf
->hw_key_idx
= index
;
957 dev
->key
[index
].keyconf
= keyconf
;
962 static int b43_key_clear(struct b43_wldev
*dev
, int index
)
964 if (B43_WARN_ON((index
< 0) || (index
>= ARRAY_SIZE(dev
->key
))))
966 do_key_write(dev
, index
, B43_SEC_ALGO_NONE
,
967 NULL
, B43_SEC_KEYSIZE
, NULL
);
968 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
969 do_key_write(dev
, index
+ 4, B43_SEC_ALGO_NONE
,
970 NULL
, B43_SEC_KEYSIZE
, NULL
);
972 dev
->key
[index
].keyconf
= NULL
;
977 static void b43_clear_keys(struct b43_wldev
*dev
)
981 if (b43_new_kidx_api(dev
))
982 count
= B43_NR_GROUP_KEYS
+ B43_NR_PAIRWISE_KEYS
;
984 count
= B43_NR_GROUP_KEYS
* 2 + B43_NR_PAIRWISE_KEYS
;
985 for (i
= 0; i
< count
; i
++)
986 b43_key_clear(dev
, i
);
989 static void b43_dump_keymemory(struct b43_wldev
*dev
)
991 unsigned int i
, index
, count
, offset
, pairwise_keys_start
;
999 if (!b43_debug(dev
, B43_DBG_KEYS
))
1002 hf
= b43_hf_read(dev
);
1003 b43dbg(dev
->wl
, "Hardware key memory dump: USEDEFKEYS=%u\n",
1004 !!(hf
& B43_HF_USEDEFKEYS
));
1005 if (b43_new_kidx_api(dev
)) {
1006 pairwise_keys_start
= B43_NR_GROUP_KEYS
;
1007 count
= B43_NR_GROUP_KEYS
+ B43_NR_PAIRWISE_KEYS
;
1009 pairwise_keys_start
= B43_NR_GROUP_KEYS
* 2;
1010 count
= B43_NR_GROUP_KEYS
* 2 + B43_NR_PAIRWISE_KEYS
;
1012 for (index
= 0; index
< count
; index
++) {
1013 key
= &(dev
->key
[index
]);
1014 printk(KERN_DEBUG
"Key slot %02u: %s",
1015 index
, (key
->keyconf
== NULL
) ? " " : "*");
1016 offset
= dev
->ktp
+ (index
* B43_SEC_KEYSIZE
);
1017 for (i
= 0; i
< B43_SEC_KEYSIZE
; i
+= 2) {
1018 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, offset
+ i
);
1019 printk("%02X%02X", (tmp
& 0xFF), ((tmp
>> 8) & 0xFF));
1022 algo
= b43_shm_read16(dev
, B43_SHM_SHARED
,
1023 B43_SHM_SH_KEYIDXBLOCK
+ (index
* 2));
1024 printk(" Algo: %04X/%02X", algo
, key
->algorithm
);
1026 if (index
>= pairwise_keys_start
) {
1027 if (key
->algorithm
== B43_SEC_ALGO_TKIP
) {
1029 offset
= B43_SHM_SH_TKIPTSCTTAK
+ (index
- 4) * (10 + 4);
1030 for (i
= 0; i
< 14; i
+= 2) {
1031 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, offset
+ i
);
1032 printk("%02X%02X", (tmp
& 0xFF), ((tmp
>> 8) & 0xFF));
1035 rcmta0
= b43_shm_read32(dev
, B43_SHM_RCMTA
,
1036 ((index
- pairwise_keys_start
) * 2) + 0);
1037 rcmta1
= b43_shm_read16(dev
, B43_SHM_RCMTA
,
1038 ((index
- pairwise_keys_start
) * 2) + 1);
1039 *((__le32
*)(&mac
[0])) = cpu_to_le32(rcmta0
);
1040 *((__le16
*)(&mac
[4])) = cpu_to_le16(rcmta1
);
1041 printk(" MAC: %pM", mac
);
1043 printk(" DEFAULT KEY");
1048 void b43_power_saving_ctl_bits(struct b43_wldev
*dev
, unsigned int ps_flags
)
1056 B43_WARN_ON((ps_flags
& B43_PS_ENABLED
) &&
1057 (ps_flags
& B43_PS_DISABLED
));
1058 B43_WARN_ON((ps_flags
& B43_PS_AWAKE
) && (ps_flags
& B43_PS_ASLEEP
));
1060 if (ps_flags
& B43_PS_ENABLED
) {
1062 } else if (ps_flags
& B43_PS_DISABLED
) {
1065 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1066 // and thus is not an AP and we are associated, set bit 25
1068 if (ps_flags
& B43_PS_AWAKE
) {
1070 } else if (ps_flags
& B43_PS_ASLEEP
) {
1073 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1074 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1075 // successful, set bit26
1078 /* FIXME: For now we force awake-on and hwps-off */
1082 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
1084 macctl
|= B43_MACCTL_HWPS
;
1086 macctl
&= ~B43_MACCTL_HWPS
;
1088 macctl
|= B43_MACCTL_AWAKE
;
1090 macctl
&= ~B43_MACCTL_AWAKE
;
1091 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
1093 b43_read32(dev
, B43_MMIO_MACCTL
);
1094 if (awake
&& dev
->dev
->id
.revision
>= 5) {
1095 /* Wait for the microcode to wake up. */
1096 for (i
= 0; i
< 100; i
++) {
1097 ucstat
= b43_shm_read16(dev
, B43_SHM_SHARED
,
1098 B43_SHM_SH_UCODESTAT
);
1099 if (ucstat
!= B43_SHM_SH_UCODESTAT_SLEEP
)
1106 void b43_wireless_core_reset(struct b43_wldev
*dev
, u32 flags
)
1111 flags
|= B43_TMSLOW_PHYCLKEN
;
1112 flags
|= B43_TMSLOW_PHYRESET
;
1113 ssb_device_enable(dev
->dev
, flags
);
1114 msleep(2); /* Wait for the PLL to turn on. */
1116 /* Now take the PHY out of Reset again */
1117 tmslow
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
1118 tmslow
|= SSB_TMSLOW_FGC
;
1119 tmslow
&= ~B43_TMSLOW_PHYRESET
;
1120 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
1121 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
1123 tmslow
&= ~SSB_TMSLOW_FGC
;
1124 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
1125 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
1128 /* Turn Analog ON, but only if we already know the PHY-type.
1129 * This protects against very early setup where we don't know the
1130 * PHY-type, yet. wireless_core_reset will be called once again later,
1131 * when we know the PHY-type. */
1133 dev
->phy
.ops
->switch_analog(dev
, 1);
1135 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
1136 macctl
&= ~B43_MACCTL_GMODE
;
1137 if (flags
& B43_TMSLOW_GMODE
)
1138 macctl
|= B43_MACCTL_GMODE
;
1139 macctl
|= B43_MACCTL_IHR_ENABLED
;
1140 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
1143 static void handle_irq_transmit_status(struct b43_wldev
*dev
)
1147 struct b43_txstatus stat
;
1150 v0
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
1151 if (!(v0
& 0x00000001))
1153 v1
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
1155 stat
.cookie
= (v0
>> 16);
1156 stat
.seq
= (v1
& 0x0000FFFF);
1157 stat
.phy_stat
= ((v1
& 0x00FF0000) >> 16);
1158 tmp
= (v0
& 0x0000FFFF);
1159 stat
.frame_count
= ((tmp
& 0xF000) >> 12);
1160 stat
.rts_count
= ((tmp
& 0x0F00) >> 8);
1161 stat
.supp_reason
= ((tmp
& 0x001C) >> 2);
1162 stat
.pm_indicated
= !!(tmp
& 0x0080);
1163 stat
.intermediate
= !!(tmp
& 0x0040);
1164 stat
.for_ampdu
= !!(tmp
& 0x0020);
1165 stat
.acked
= !!(tmp
& 0x0002);
1167 b43_handle_txstatus(dev
, &stat
);
1171 static void drain_txstatus_queue(struct b43_wldev
*dev
)
1175 if (dev
->dev
->id
.revision
< 5)
1177 /* Read all entries from the microcode TXstatus FIFO
1178 * and throw them away.
1181 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
1182 if (!(dummy
& 0x00000001))
1184 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
1188 static u32
b43_jssi_read(struct b43_wldev
*dev
)
1192 val
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x08A);
1194 val
|= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x088);
1199 static void b43_jssi_write(struct b43_wldev
*dev
, u32 jssi
)
1201 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x088, (jssi
& 0x0000FFFF));
1202 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x08A, (jssi
& 0xFFFF0000) >> 16);
1205 static void b43_generate_noise_sample(struct b43_wldev
*dev
)
1207 b43_jssi_write(dev
, 0x7F7F7F7F);
1208 b43_write32(dev
, B43_MMIO_MACCMD
,
1209 b43_read32(dev
, B43_MMIO_MACCMD
) | B43_MACCMD_BGNOISE
);
1212 static void b43_calculate_link_quality(struct b43_wldev
*dev
)
1214 /* Top half of Link Quality calculation. */
1216 if (dev
->phy
.type
!= B43_PHYTYPE_G
)
1218 if (dev
->noisecalc
.calculation_running
)
1220 dev
->noisecalc
.calculation_running
= 1;
1221 dev
->noisecalc
.nr_samples
= 0;
1223 b43_generate_noise_sample(dev
);
1226 static void handle_irq_noise(struct b43_wldev
*dev
)
1228 struct b43_phy_g
*phy
= dev
->phy
.g
;
1234 /* Bottom half of Link Quality calculation. */
1236 if (dev
->phy
.type
!= B43_PHYTYPE_G
)
1239 /* Possible race condition: It might be possible that the user
1240 * changed to a different channel in the meantime since we
1241 * started the calculation. We ignore that fact, since it's
1242 * not really that much of a problem. The background noise is
1243 * an estimation only anyway. Slightly wrong results will get damped
1244 * by the averaging of the 8 sample rounds. Additionally the
1245 * value is shortlived. So it will be replaced by the next noise
1246 * calculation round soon. */
1248 B43_WARN_ON(!dev
->noisecalc
.calculation_running
);
1249 *((__le32
*)noise
) = cpu_to_le32(b43_jssi_read(dev
));
1250 if (noise
[0] == 0x7F || noise
[1] == 0x7F ||
1251 noise
[2] == 0x7F || noise
[3] == 0x7F)
1254 /* Get the noise samples. */
1255 B43_WARN_ON(dev
->noisecalc
.nr_samples
>= 8);
1256 i
= dev
->noisecalc
.nr_samples
;
1257 noise
[0] = clamp_val(noise
[0], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1258 noise
[1] = clamp_val(noise
[1], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1259 noise
[2] = clamp_val(noise
[2], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1260 noise
[3] = clamp_val(noise
[3], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1261 dev
->noisecalc
.samples
[i
][0] = phy
->nrssi_lt
[noise
[0]];
1262 dev
->noisecalc
.samples
[i
][1] = phy
->nrssi_lt
[noise
[1]];
1263 dev
->noisecalc
.samples
[i
][2] = phy
->nrssi_lt
[noise
[2]];
1264 dev
->noisecalc
.samples
[i
][3] = phy
->nrssi_lt
[noise
[3]];
1265 dev
->noisecalc
.nr_samples
++;
1266 if (dev
->noisecalc
.nr_samples
== 8) {
1267 /* Calculate the Link Quality by the noise samples. */
1269 for (i
= 0; i
< 8; i
++) {
1270 for (j
= 0; j
< 4; j
++)
1271 average
+= dev
->noisecalc
.samples
[i
][j
];
1277 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x40C);
1278 tmp
= (tmp
/ 128) & 0x1F;
1288 dev
->stats
.link_noise
= average
;
1289 dev
->noisecalc
.calculation_running
= 0;
1293 b43_generate_noise_sample(dev
);
1296 static void handle_irq_tbtt_indication(struct b43_wldev
*dev
)
1298 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_AP
)) {
1301 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1302 b43_power_saving_ctl_bits(dev
, 0);
1304 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_ADHOC
))
1308 static void handle_irq_atim_end(struct b43_wldev
*dev
)
1310 if (dev
->dfq_valid
) {
1311 b43_write32(dev
, B43_MMIO_MACCMD
,
1312 b43_read32(dev
, B43_MMIO_MACCMD
)
1313 | B43_MACCMD_DFQ_VALID
);
1318 static void handle_irq_pmq(struct b43_wldev
*dev
)
1325 tmp
= b43_read32(dev
, B43_MMIO_PS_STATUS
);
1326 if (!(tmp
& 0x00000008))
1329 /* 16bit write is odd, but correct. */
1330 b43_write16(dev
, B43_MMIO_PS_STATUS
, 0x0002);
1333 static void b43_write_template_common(struct b43_wldev
*dev
,
1334 const u8
*data
, u16 size
,
1336 u16 shm_size_offset
, u8 rate
)
1339 struct b43_plcp_hdr4 plcp
;
1342 b43_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1343 b43_ram_write(dev
, ram_offset
, le32_to_cpu(plcp
.data
));
1344 ram_offset
+= sizeof(u32
);
1345 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1346 * So leave the first two bytes of the next write blank.
1348 tmp
= (u32
) (data
[0]) << 16;
1349 tmp
|= (u32
) (data
[1]) << 24;
1350 b43_ram_write(dev
, ram_offset
, tmp
);
1351 ram_offset
+= sizeof(u32
);
1352 for (i
= 2; i
< size
; i
+= sizeof(u32
)) {
1353 tmp
= (u32
) (data
[i
+ 0]);
1355 tmp
|= (u32
) (data
[i
+ 1]) << 8;
1357 tmp
|= (u32
) (data
[i
+ 2]) << 16;
1359 tmp
|= (u32
) (data
[i
+ 3]) << 24;
1360 b43_ram_write(dev
, ram_offset
+ i
- 2, tmp
);
1362 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_size_offset
,
1363 size
+ sizeof(struct b43_plcp_hdr6
));
1366 /* Check if the use of the antenna that ieee80211 told us to
1367 * use is possible. This will fall back to DEFAULT.
1368 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1369 u8
b43_ieee80211_antenna_sanitize(struct b43_wldev
*dev
,
1374 if (antenna_nr
== 0) {
1375 /* Zero means "use default antenna". That's always OK. */
1379 /* Get the mask of available antennas. */
1381 antenna_mask
= dev
->dev
->bus
->sprom
.ant_available_bg
;
1383 antenna_mask
= dev
->dev
->bus
->sprom
.ant_available_a
;
1385 if (!(antenna_mask
& (1 << (antenna_nr
- 1)))) {
1386 /* This antenna is not available. Fall back to default. */
1393 /* Convert a b43 antenna number value to the PHY TX control value. */
1394 static u16
b43_antenna_to_phyctl(int antenna
)
1398 return B43_TXH_PHY_ANT0
;
1400 return B43_TXH_PHY_ANT1
;
1402 return B43_TXH_PHY_ANT2
;
1404 return B43_TXH_PHY_ANT3
;
1405 case B43_ANTENNA_AUTO0
:
1406 case B43_ANTENNA_AUTO1
:
1407 return B43_TXH_PHY_ANT01AUTO
;
1413 static void b43_write_beacon_template(struct b43_wldev
*dev
,
1415 u16 shm_size_offset
)
1417 unsigned int i
, len
, variable_len
;
1418 const struct ieee80211_mgmt
*bcn
;
1424 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(dev
->wl
->current_beacon
);
1426 bcn
= (const struct ieee80211_mgmt
*)(dev
->wl
->current_beacon
->data
);
1427 len
= min((size_t) dev
->wl
->current_beacon
->len
,
1428 0x200 - sizeof(struct b43_plcp_hdr6
));
1429 rate
= ieee80211_get_tx_rate(dev
->wl
->hw
, info
)->hw_value
;
1431 b43_write_template_common(dev
, (const u8
*)bcn
,
1432 len
, ram_offset
, shm_size_offset
, rate
);
1434 /* Write the PHY TX control parameters. */
1435 antenna
= B43_ANTENNA_DEFAULT
;
1436 antenna
= b43_antenna_to_phyctl(antenna
);
1437 ctl
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
);
1438 /* We can't send beacons with short preamble. Would get PHY errors. */
1439 ctl
&= ~B43_TXH_PHY_SHORTPRMBL
;
1440 ctl
&= ~B43_TXH_PHY_ANT
;
1441 ctl
&= ~B43_TXH_PHY_ENC
;
1443 if (b43_is_cck_rate(rate
))
1444 ctl
|= B43_TXH_PHY_ENC_CCK
;
1446 ctl
|= B43_TXH_PHY_ENC_OFDM
;
1447 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
, ctl
);
1449 /* Find the position of the TIM and the DTIM_period value
1450 * and write them to SHM. */
1451 ie
= bcn
->u
.beacon
.variable
;
1452 variable_len
= len
- offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
);
1453 for (i
= 0; i
< variable_len
- 2; ) {
1454 uint8_t ie_id
, ie_len
;
1461 /* This is the TIM Information Element */
1463 /* Check whether the ie_len is in the beacon data range. */
1464 if (variable_len
< ie_len
+ 2 + i
)
1466 /* A valid TIM is at least 4 bytes long. */
1471 tim_position
= sizeof(struct b43_plcp_hdr6
);
1472 tim_position
+= offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
);
1475 dtim_period
= ie
[i
+ 3];
1477 b43_shm_write16(dev
, B43_SHM_SHARED
,
1478 B43_SHM_SH_TIMBPOS
, tim_position
);
1479 b43_shm_write16(dev
, B43_SHM_SHARED
,
1480 B43_SHM_SH_DTIMPER
, dtim_period
);
1487 * If ucode wants to modify TIM do it behind the beacon, this
1488 * will happen, for example, when doing mesh networking.
1490 b43_shm_write16(dev
, B43_SHM_SHARED
,
1492 len
+ sizeof(struct b43_plcp_hdr6
));
1493 b43_shm_write16(dev
, B43_SHM_SHARED
,
1494 B43_SHM_SH_DTIMPER
, 0);
1496 b43dbg(dev
->wl
, "Updated beacon template at 0x%x\n", ram_offset
);
1499 static void b43_upload_beacon0(struct b43_wldev
*dev
)
1501 struct b43_wl
*wl
= dev
->wl
;
1503 if (wl
->beacon0_uploaded
)
1505 b43_write_beacon_template(dev
, 0x68, 0x18);
1506 wl
->beacon0_uploaded
= 1;
1509 static void b43_upload_beacon1(struct b43_wldev
*dev
)
1511 struct b43_wl
*wl
= dev
->wl
;
1513 if (wl
->beacon1_uploaded
)
1515 b43_write_beacon_template(dev
, 0x468, 0x1A);
1516 wl
->beacon1_uploaded
= 1;
1519 static void handle_irq_beacon(struct b43_wldev
*dev
)
1521 struct b43_wl
*wl
= dev
->wl
;
1522 u32 cmd
, beacon0_valid
, beacon1_valid
;
1524 if (!b43_is_mode(wl
, NL80211_IFTYPE_AP
) &&
1525 !b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
))
1528 /* This is the bottom half of the asynchronous beacon update. */
1530 /* Ignore interrupt in the future. */
1531 dev
->irq_mask
&= ~B43_IRQ_BEACON
;
1533 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1534 beacon0_valid
= (cmd
& B43_MACCMD_BEACON0_VALID
);
1535 beacon1_valid
= (cmd
& B43_MACCMD_BEACON1_VALID
);
1537 /* Schedule interrupt manually, if busy. */
1538 if (beacon0_valid
&& beacon1_valid
) {
1539 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_BEACON
);
1540 dev
->irq_mask
|= B43_IRQ_BEACON
;
1544 if (unlikely(wl
->beacon_templates_virgin
)) {
1545 /* We never uploaded a beacon before.
1546 * Upload both templates now, but only mark one valid. */
1547 wl
->beacon_templates_virgin
= 0;
1548 b43_upload_beacon0(dev
);
1549 b43_upload_beacon1(dev
);
1550 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1551 cmd
|= B43_MACCMD_BEACON0_VALID
;
1552 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1554 if (!beacon0_valid
) {
1555 b43_upload_beacon0(dev
);
1556 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1557 cmd
|= B43_MACCMD_BEACON0_VALID
;
1558 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1559 } else if (!beacon1_valid
) {
1560 b43_upload_beacon1(dev
);
1561 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1562 cmd
|= B43_MACCMD_BEACON1_VALID
;
1563 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1568 static void b43_do_beacon_update_trigger_work(struct b43_wldev
*dev
)
1570 u32 old_irq_mask
= dev
->irq_mask
;
1572 /* update beacon right away or defer to irq */
1573 handle_irq_beacon(dev
);
1574 if (old_irq_mask
!= dev
->irq_mask
) {
1575 /* The handler updated the IRQ mask. */
1576 B43_WARN_ON(!dev
->irq_mask
);
1577 if (b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
)) {
1578 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, dev
->irq_mask
);
1580 /* Device interrupts are currently disabled. That means
1581 * we just ran the hardirq handler and scheduled the
1582 * IRQ thread. The thread will write the IRQ mask when
1583 * it finished, so there's nothing to do here. Writing
1584 * the mask _here_ would incorrectly re-enable IRQs. */
1589 static void b43_beacon_update_trigger_work(struct work_struct
*work
)
1591 struct b43_wl
*wl
= container_of(work
, struct b43_wl
,
1592 beacon_update_trigger
);
1593 struct b43_wldev
*dev
;
1595 mutex_lock(&wl
->mutex
);
1596 dev
= wl
->current_dev
;
1597 if (likely(dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
))) {
1598 if (dev
->dev
->bus
->bustype
== SSB_BUSTYPE_SDIO
) {
1599 /* wl->mutex is enough. */
1600 b43_do_beacon_update_trigger_work(dev
);
1603 spin_lock_irq(&wl
->hardirq_lock
);
1604 b43_do_beacon_update_trigger_work(dev
);
1606 spin_unlock_irq(&wl
->hardirq_lock
);
1609 mutex_unlock(&wl
->mutex
);
1612 /* Asynchronously update the packet templates in template RAM.
1613 * Locking: Requires wl->mutex to be locked. */
1614 static void b43_update_templates(struct b43_wl
*wl
)
1616 struct sk_buff
*beacon
;
1618 /* This is the top half of the ansynchronous beacon update.
1619 * The bottom half is the beacon IRQ.
1620 * Beacon update must be asynchronous to avoid sending an
1621 * invalid beacon. This can happen for example, if the firmware
1622 * transmits a beacon while we are updating it. */
1624 /* We could modify the existing beacon and set the aid bit in
1625 * the TIM field, but that would probably require resizing and
1626 * moving of data within the beacon template.
1627 * Simply request a new beacon and let mac80211 do the hard work. */
1628 beacon
= ieee80211_beacon_get(wl
->hw
, wl
->vif
);
1629 if (unlikely(!beacon
))
1632 if (wl
->current_beacon
)
1633 dev_kfree_skb_any(wl
->current_beacon
);
1634 wl
->current_beacon
= beacon
;
1635 wl
->beacon0_uploaded
= 0;
1636 wl
->beacon1_uploaded
= 0;
1637 ieee80211_queue_work(wl
->hw
, &wl
->beacon_update_trigger
);
1640 static void b43_set_beacon_int(struct b43_wldev
*dev
, u16 beacon_int
)
1643 if (dev
->dev
->id
.revision
>= 3) {
1644 b43_write32(dev
, B43_MMIO_TSF_CFP_REP
, (beacon_int
<< 16));
1645 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, (beacon_int
<< 10));
1647 b43_write16(dev
, 0x606, (beacon_int
>> 6));
1648 b43_write16(dev
, 0x610, beacon_int
);
1650 b43_time_unlock(dev
);
1651 b43dbg(dev
->wl
, "Set beacon interval to %u\n", beacon_int
);
1654 static void b43_handle_firmware_panic(struct b43_wldev
*dev
)
1658 /* Read the register that contains the reason code for the panic. */
1659 reason
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, B43_FWPANIC_REASON_REG
);
1660 b43err(dev
->wl
, "Whoopsy, firmware panic! Reason: %u\n", reason
);
1664 b43dbg(dev
->wl
, "The panic reason is unknown.\n");
1666 case B43_FWPANIC_DIE
:
1667 /* Do not restart the controller or firmware.
1668 * The device is nonfunctional from now on.
1669 * Restarting would result in this panic to trigger again,
1670 * so we avoid that recursion. */
1672 case B43_FWPANIC_RESTART
:
1673 b43_controller_restart(dev
, "Microcode panic");
1678 static void handle_irq_ucode_debug(struct b43_wldev
*dev
)
1680 unsigned int i
, cnt
;
1681 u16 reason
, marker_id
, marker_line
;
1684 /* The proprietary firmware doesn't have this IRQ. */
1685 if (!dev
->fw
.opensource
)
1688 /* Read the register that contains the reason code for this IRQ. */
1689 reason
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, B43_DEBUGIRQ_REASON_REG
);
1692 case B43_DEBUGIRQ_PANIC
:
1693 b43_handle_firmware_panic(dev
);
1695 case B43_DEBUGIRQ_DUMP_SHM
:
1697 break; /* Only with driver debugging enabled. */
1698 buf
= kmalloc(4096, GFP_ATOMIC
);
1700 b43dbg(dev
->wl
, "SHM-dump: Failed to allocate memory\n");
1703 for (i
= 0; i
< 4096; i
+= 2) {
1704 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, i
);
1705 buf
[i
/ 2] = cpu_to_le16(tmp
);
1707 b43info(dev
->wl
, "Shared memory dump:\n");
1708 print_hex_dump(KERN_INFO
, "", DUMP_PREFIX_OFFSET
,
1709 16, 2, buf
, 4096, 1);
1712 case B43_DEBUGIRQ_DUMP_REGS
:
1714 break; /* Only with driver debugging enabled. */
1715 b43info(dev
->wl
, "Microcode register dump:\n");
1716 for (i
= 0, cnt
= 0; i
< 64; i
++) {
1717 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, i
);
1720 printk("r%02u: 0x%04X ", i
, tmp
);
1729 case B43_DEBUGIRQ_MARKER
:
1731 break; /* Only with driver debugging enabled. */
1732 marker_id
= b43_shm_read16(dev
, B43_SHM_SCRATCH
,
1734 marker_line
= b43_shm_read16(dev
, B43_SHM_SCRATCH
,
1735 B43_MARKER_LINE_REG
);
1736 b43info(dev
->wl
, "The firmware just executed the MARKER(%u) "
1737 "at line number %u\n",
1738 marker_id
, marker_line
);
1741 b43dbg(dev
->wl
, "Debug-IRQ triggered for unknown reason: %u\n",
1745 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1746 b43_shm_write16(dev
, B43_SHM_SCRATCH
,
1747 B43_DEBUGIRQ_REASON_REG
, B43_DEBUGIRQ_ACK
);
1750 static void b43_do_interrupt_thread(struct b43_wldev
*dev
)
1753 u32 dma_reason
[ARRAY_SIZE(dev
->dma_reason
)];
1754 u32 merged_dma_reason
= 0;
1757 if (unlikely(b43_status(dev
) != B43_STAT_STARTED
))
1760 reason
= dev
->irq_reason
;
1761 for (i
= 0; i
< ARRAY_SIZE(dma_reason
); i
++) {
1762 dma_reason
[i
] = dev
->dma_reason
[i
];
1763 merged_dma_reason
|= dma_reason
[i
];
1766 if (unlikely(reason
& B43_IRQ_MAC_TXERR
))
1767 b43err(dev
->wl
, "MAC transmission error\n");
1769 if (unlikely(reason
& B43_IRQ_PHY_TXERR
)) {
1770 b43err(dev
->wl
, "PHY transmission error\n");
1772 if (unlikely(atomic_dec_and_test(&dev
->phy
.txerr_cnt
))) {
1773 atomic_set(&dev
->phy
.txerr_cnt
,
1774 B43_PHY_TX_BADNESS_LIMIT
);
1775 b43err(dev
->wl
, "Too many PHY TX errors, "
1776 "restarting the controller\n");
1777 b43_controller_restart(dev
, "PHY TX errors");
1781 if (unlikely(merged_dma_reason
& (B43_DMAIRQ_FATALMASK
|
1782 B43_DMAIRQ_NONFATALMASK
))) {
1783 if (merged_dma_reason
& B43_DMAIRQ_FATALMASK
) {
1784 b43err(dev
->wl
, "Fatal DMA error: "
1785 "0x%08X, 0x%08X, 0x%08X, "
1786 "0x%08X, 0x%08X, 0x%08X\n",
1787 dma_reason
[0], dma_reason
[1],
1788 dma_reason
[2], dma_reason
[3],
1789 dma_reason
[4], dma_reason
[5]);
1790 b43err(dev
->wl
, "This device does not support DMA "
1791 "on your system. Please use PIO instead.\n");
1792 b43err(dev
->wl
, "Unload the b43 module and reload "
1796 if (merged_dma_reason
& B43_DMAIRQ_NONFATALMASK
) {
1797 b43err(dev
->wl
, "DMA error: "
1798 "0x%08X, 0x%08X, 0x%08X, "
1799 "0x%08X, 0x%08X, 0x%08X\n",
1800 dma_reason
[0], dma_reason
[1],
1801 dma_reason
[2], dma_reason
[3],
1802 dma_reason
[4], dma_reason
[5]);
1806 if (unlikely(reason
& B43_IRQ_UCODE_DEBUG
))
1807 handle_irq_ucode_debug(dev
);
1808 if (reason
& B43_IRQ_TBTT_INDI
)
1809 handle_irq_tbtt_indication(dev
);
1810 if (reason
& B43_IRQ_ATIM_END
)
1811 handle_irq_atim_end(dev
);
1812 if (reason
& B43_IRQ_BEACON
)
1813 handle_irq_beacon(dev
);
1814 if (reason
& B43_IRQ_PMQ
)
1815 handle_irq_pmq(dev
);
1816 if (reason
& B43_IRQ_TXFIFO_FLUSH_OK
)
1818 if (reason
& B43_IRQ_NOISESAMPLE_OK
)
1819 handle_irq_noise(dev
);
1821 /* Check the DMA reason registers for received data. */
1822 if (dma_reason
[0] & B43_DMAIRQ_RX_DONE
) {
1823 if (b43_using_pio_transfers(dev
))
1824 b43_pio_rx(dev
->pio
.rx_queue
);
1826 b43_dma_rx(dev
->dma
.rx_ring
);
1828 B43_WARN_ON(dma_reason
[1] & B43_DMAIRQ_RX_DONE
);
1829 B43_WARN_ON(dma_reason
[2] & B43_DMAIRQ_RX_DONE
);
1830 B43_WARN_ON(dma_reason
[3] & B43_DMAIRQ_RX_DONE
);
1831 B43_WARN_ON(dma_reason
[4] & B43_DMAIRQ_RX_DONE
);
1832 B43_WARN_ON(dma_reason
[5] & B43_DMAIRQ_RX_DONE
);
1834 if (reason
& B43_IRQ_TX_OK
)
1835 handle_irq_transmit_status(dev
);
1837 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1838 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, dev
->irq_mask
);
1841 if (b43_debug(dev
, B43_DBG_VERBOSESTATS
)) {
1843 for (i
= 0; i
< ARRAY_SIZE(dev
->irq_bit_count
); i
++) {
1844 if (reason
& (1 << i
))
1845 dev
->irq_bit_count
[i
]++;
1851 /* Interrupt thread handler. Handles device interrupts in thread context. */
1852 static irqreturn_t
b43_interrupt_thread_handler(int irq
, void *dev_id
)
1854 struct b43_wldev
*dev
= dev_id
;
1856 mutex_lock(&dev
->wl
->mutex
);
1857 b43_do_interrupt_thread(dev
);
1859 mutex_unlock(&dev
->wl
->mutex
);
1864 static irqreturn_t
b43_do_interrupt(struct b43_wldev
*dev
)
1868 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1869 * On SDIO, this runs under wl->mutex. */
1871 reason
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
1872 if (reason
== 0xffffffff) /* shared IRQ */
1874 reason
&= dev
->irq_mask
;
1878 dev
->dma_reason
[0] = b43_read32(dev
, B43_MMIO_DMA0_REASON
)
1880 dev
->dma_reason
[1] = b43_read32(dev
, B43_MMIO_DMA1_REASON
)
1882 dev
->dma_reason
[2] = b43_read32(dev
, B43_MMIO_DMA2_REASON
)
1884 dev
->dma_reason
[3] = b43_read32(dev
, B43_MMIO_DMA3_REASON
)
1886 dev
->dma_reason
[4] = b43_read32(dev
, B43_MMIO_DMA4_REASON
)
1889 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1893 /* ACK the interrupt. */
1894 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, reason
);
1895 b43_write32(dev
, B43_MMIO_DMA0_REASON
, dev
->dma_reason
[0]);
1896 b43_write32(dev
, B43_MMIO_DMA1_REASON
, dev
->dma_reason
[1]);
1897 b43_write32(dev
, B43_MMIO_DMA2_REASON
, dev
->dma_reason
[2]);
1898 b43_write32(dev
, B43_MMIO_DMA3_REASON
, dev
->dma_reason
[3]);
1899 b43_write32(dev
, B43_MMIO_DMA4_REASON
, dev
->dma_reason
[4]);
1901 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1904 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
1905 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, 0);
1906 /* Save the reason bitmasks for the IRQ thread handler. */
1907 dev
->irq_reason
= reason
;
1909 return IRQ_WAKE_THREAD
;
1912 /* Interrupt handler top-half. This runs with interrupts disabled. */
1913 static irqreturn_t
b43_interrupt_handler(int irq
, void *dev_id
)
1915 struct b43_wldev
*dev
= dev_id
;
1918 if (unlikely(b43_status(dev
) < B43_STAT_STARTED
))
1921 spin_lock(&dev
->wl
->hardirq_lock
);
1922 ret
= b43_do_interrupt(dev
);
1924 spin_unlock(&dev
->wl
->hardirq_lock
);
1929 /* SDIO interrupt handler. This runs in process context. */
1930 static void b43_sdio_interrupt_handler(struct b43_wldev
*dev
)
1932 struct b43_wl
*wl
= dev
->wl
;
1935 mutex_lock(&wl
->mutex
);
1937 ret
= b43_do_interrupt(dev
);
1938 if (ret
== IRQ_WAKE_THREAD
)
1939 b43_do_interrupt_thread(dev
);
1941 mutex_unlock(&wl
->mutex
);
1944 void b43_do_release_fw(struct b43_firmware_file
*fw
)
1946 release_firmware(fw
->data
);
1948 fw
->filename
= NULL
;
1951 static void b43_release_firmware(struct b43_wldev
*dev
)
1953 b43_do_release_fw(&dev
->fw
.ucode
);
1954 b43_do_release_fw(&dev
->fw
.pcm
);
1955 b43_do_release_fw(&dev
->fw
.initvals
);
1956 b43_do_release_fw(&dev
->fw
.initvals_band
);
1959 static void b43_print_fw_helptext(struct b43_wl
*wl
, bool error
)
1963 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1964 "and download the correct firmware for this driver version. " \
1965 "Please carefully read all instructions on this website.\n";
1973 int b43_do_request_fw(struct b43_request_fw_context
*ctx
,
1975 struct b43_firmware_file
*fw
)
1977 const struct firmware
*blob
;
1978 struct b43_fw_header
*hdr
;
1983 /* Don't fetch anything. Free possibly cached firmware. */
1984 /* FIXME: We should probably keep it anyway, to save some headache
1985 * on suspend/resume with multiband devices. */
1986 b43_do_release_fw(fw
);
1990 if ((fw
->type
== ctx
->req_type
) &&
1991 (strcmp(fw
->filename
, name
) == 0))
1992 return 0; /* Already have this fw. */
1993 /* Free the cached firmware first. */
1994 /* FIXME: We should probably do this later after we successfully
1995 * got the new fw. This could reduce headache with multiband devices.
1996 * We could also redesign this to cache the firmware for all possible
1997 * bands all the time. */
1998 b43_do_release_fw(fw
);
2001 switch (ctx
->req_type
) {
2002 case B43_FWTYPE_PROPRIETARY
:
2003 snprintf(ctx
->fwname
, sizeof(ctx
->fwname
),
2005 modparam_fwpostfix
, name
);
2007 case B43_FWTYPE_OPENSOURCE
:
2008 snprintf(ctx
->fwname
, sizeof(ctx
->fwname
),
2010 modparam_fwpostfix
, name
);
2016 err
= request_firmware(&blob
, ctx
->fwname
, ctx
->dev
->dev
->dev
);
2017 if (err
== -ENOENT
) {
2018 snprintf(ctx
->errors
[ctx
->req_type
],
2019 sizeof(ctx
->errors
[ctx
->req_type
]),
2020 "Firmware file \"%s\" not found\n", ctx
->fwname
);
2023 snprintf(ctx
->errors
[ctx
->req_type
],
2024 sizeof(ctx
->errors
[ctx
->req_type
]),
2025 "Firmware file \"%s\" request failed (err=%d)\n",
2029 if (blob
->size
< sizeof(struct b43_fw_header
))
2031 hdr
= (struct b43_fw_header
*)(blob
->data
);
2032 switch (hdr
->type
) {
2033 case B43_FW_TYPE_UCODE
:
2034 case B43_FW_TYPE_PCM
:
2035 size
= be32_to_cpu(hdr
->size
);
2036 if (size
!= blob
->size
- sizeof(struct b43_fw_header
))
2039 case B43_FW_TYPE_IV
:
2048 fw
->filename
= name
;
2049 fw
->type
= ctx
->req_type
;
2054 snprintf(ctx
->errors
[ctx
->req_type
],
2055 sizeof(ctx
->errors
[ctx
->req_type
]),
2056 "Firmware file \"%s\" format error.\n", ctx
->fwname
);
2057 release_firmware(blob
);
2062 static int b43_try_request_fw(struct b43_request_fw_context
*ctx
)
2064 struct b43_wldev
*dev
= ctx
->dev
;
2065 struct b43_firmware
*fw
= &ctx
->dev
->fw
;
2066 const u8 rev
= ctx
->dev
->dev
->id
.revision
;
2067 const char *filename
;
2072 tmshigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
2073 if ((rev
>= 5) && (rev
<= 10))
2074 filename
= "ucode5";
2075 else if ((rev
>= 11) && (rev
<= 12))
2076 filename
= "ucode11";
2078 filename
= "ucode13";
2080 filename
= "ucode14";
2082 filename
= "ucode15";
2085 err
= b43_do_request_fw(ctx
, filename
, &fw
->ucode
);
2090 if ((rev
>= 5) && (rev
<= 10))
2096 fw
->pcm_request_failed
= 0;
2097 err
= b43_do_request_fw(ctx
, filename
, &fw
->pcm
);
2098 if (err
== -ENOENT
) {
2099 /* We did not find a PCM file? Not fatal, but
2100 * core rev <= 10 must do without hwcrypto then. */
2101 fw
->pcm_request_failed
= 1;
2106 switch (dev
->phy
.type
) {
2108 if ((rev
>= 5) && (rev
<= 10)) {
2109 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
2110 filename
= "a0g1initvals5";
2112 filename
= "a0g0initvals5";
2114 goto err_no_initvals
;
2117 if ((rev
>= 5) && (rev
<= 10))
2118 filename
= "b0g0initvals5";
2120 filename
= "b0g0initvals13";
2122 goto err_no_initvals
;
2125 if ((rev
>= 11) && (rev
<= 12))
2126 filename
= "n0initvals11";
2128 goto err_no_initvals
;
2130 case B43_PHYTYPE_LP
:
2132 filename
= "lp0initvals13";
2134 filename
= "lp0initvals14";
2136 filename
= "lp0initvals15";
2138 goto err_no_initvals
;
2141 goto err_no_initvals
;
2143 err
= b43_do_request_fw(ctx
, filename
, &fw
->initvals
);
2147 /* Get bandswitch initvals */
2148 switch (dev
->phy
.type
) {
2150 if ((rev
>= 5) && (rev
<= 10)) {
2151 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
2152 filename
= "a0g1bsinitvals5";
2154 filename
= "a0g0bsinitvals5";
2155 } else if (rev
>= 11)
2158 goto err_no_initvals
;
2161 if ((rev
>= 5) && (rev
<= 10))
2162 filename
= "b0g0bsinitvals5";
2166 goto err_no_initvals
;
2169 if ((rev
>= 11) && (rev
<= 12))
2170 filename
= "n0bsinitvals11";
2172 goto err_no_initvals
;
2174 case B43_PHYTYPE_LP
:
2176 filename
= "lp0bsinitvals13";
2178 filename
= "lp0bsinitvals14";
2180 filename
= "lp0bsinitvals15";
2182 goto err_no_initvals
;
2185 goto err_no_initvals
;
2187 err
= b43_do_request_fw(ctx
, filename
, &fw
->initvals_band
);
2194 err
= ctx
->fatal_failure
= -EOPNOTSUPP
;
2195 b43err(dev
->wl
, "The driver does not know which firmware (ucode) "
2196 "is required for your device (wl-core rev %u)\n", rev
);
2200 err
= ctx
->fatal_failure
= -EOPNOTSUPP
;
2201 b43err(dev
->wl
, "The driver does not know which firmware (PCM) "
2202 "is required for your device (wl-core rev %u)\n", rev
);
2206 err
= ctx
->fatal_failure
= -EOPNOTSUPP
;
2207 b43err(dev
->wl
, "The driver does not know which firmware (initvals) "
2208 "is required for your device (wl-core rev %u)\n", rev
);
2212 /* We failed to load this firmware image. The error message
2213 * already is in ctx->errors. Return and let our caller decide
2218 b43_release_firmware(dev
);
2222 static int b43_request_firmware(struct b43_wldev
*dev
)
2224 struct b43_request_fw_context
*ctx
;
2229 ctx
= kzalloc(sizeof(*ctx
), GFP_KERNEL
);
2234 ctx
->req_type
= B43_FWTYPE_PROPRIETARY
;
2235 err
= b43_try_request_fw(ctx
);
2237 goto out
; /* Successfully loaded it. */
2238 err
= ctx
->fatal_failure
;
2242 ctx
->req_type
= B43_FWTYPE_OPENSOURCE
;
2243 err
= b43_try_request_fw(ctx
);
2245 goto out
; /* Successfully loaded it. */
2246 err
= ctx
->fatal_failure
;
2250 /* Could not find a usable firmware. Print the errors. */
2251 for (i
= 0; i
< B43_NR_FWTYPES
; i
++) {
2252 errmsg
= ctx
->errors
[i
];
2254 b43err(dev
->wl
, errmsg
);
2256 b43_print_fw_helptext(dev
->wl
, 1);
2264 static int b43_upload_microcode(struct b43_wldev
*dev
)
2266 const size_t hdr_len
= sizeof(struct b43_fw_header
);
2268 unsigned int i
, len
;
2269 u16 fwrev
, fwpatch
, fwdate
, fwtime
;
2273 /* Jump the microcode PSM to offset 0 */
2274 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2275 B43_WARN_ON(macctl
& B43_MACCTL_PSM_RUN
);
2276 macctl
|= B43_MACCTL_PSM_JMP0
;
2277 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2278 /* Zero out all microcode PSM registers and shared memory. */
2279 for (i
= 0; i
< 64; i
++)
2280 b43_shm_write16(dev
, B43_SHM_SCRATCH
, i
, 0);
2281 for (i
= 0; i
< 4096; i
+= 2)
2282 b43_shm_write16(dev
, B43_SHM_SHARED
, i
, 0);
2284 /* Upload Microcode. */
2285 data
= (__be32
*) (dev
->fw
.ucode
.data
->data
+ hdr_len
);
2286 len
= (dev
->fw
.ucode
.data
->size
- hdr_len
) / sizeof(__be32
);
2287 b43_shm_control_word(dev
, B43_SHM_UCODE
| B43_SHM_AUTOINC_W
, 0x0000);
2288 for (i
= 0; i
< len
; i
++) {
2289 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
2293 if (dev
->fw
.pcm
.data
) {
2294 /* Upload PCM data. */
2295 data
= (__be32
*) (dev
->fw
.pcm
.data
->data
+ hdr_len
);
2296 len
= (dev
->fw
.pcm
.data
->size
- hdr_len
) / sizeof(__be32
);
2297 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EA);
2298 b43_write32(dev
, B43_MMIO_SHM_DATA
, 0x00004000);
2299 /* No need for autoinc bit in SHM_HW */
2300 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EB);
2301 for (i
= 0; i
< len
; i
++) {
2302 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
2307 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_ALL
);
2309 /* Start the microcode PSM */
2310 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2311 macctl
&= ~B43_MACCTL_PSM_JMP0
;
2312 macctl
|= B43_MACCTL_PSM_RUN
;
2313 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2315 /* Wait for the microcode to load and respond */
2318 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2319 if (tmp
== B43_IRQ_MAC_SUSPENDED
)
2323 b43err(dev
->wl
, "Microcode not responding\n");
2324 b43_print_fw_helptext(dev
->wl
, 1);
2330 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
); /* dummy read */
2332 /* Get and check the revisions. */
2333 fwrev
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEREV
);
2334 fwpatch
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEPATCH
);
2335 fwdate
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEDATE
);
2336 fwtime
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODETIME
);
2338 if (fwrev
<= 0x128) {
2339 b43err(dev
->wl
, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2340 "binary drivers older than version 4.x is unsupported. "
2341 "You must upgrade your firmware files.\n");
2342 b43_print_fw_helptext(dev
->wl
, 1);
2346 dev
->fw
.rev
= fwrev
;
2347 dev
->fw
.patch
= fwpatch
;
2348 dev
->fw
.opensource
= (fwdate
== 0xFFFF);
2350 /* Default to use-all-queues. */
2351 dev
->wl
->hw
->queues
= dev
->wl
->mac80211_initially_registered_queues
;
2352 dev
->qos_enabled
= !!modparam_qos
;
2353 /* Default to firmware/hardware crypto acceleration. */
2354 dev
->hwcrypto_enabled
= 1;
2356 if (dev
->fw
.opensource
) {
2359 /* Patchlevel info is encoded in the "time" field. */
2360 dev
->fw
.patch
= fwtime
;
2361 b43info(dev
->wl
, "Loading OpenSource firmware version %u.%u\n",
2362 dev
->fw
.rev
, dev
->fw
.patch
);
2364 fwcapa
= b43_fwcapa_read(dev
);
2365 if (!(fwcapa
& B43_FWCAPA_HWCRYPTO
) || dev
->fw
.pcm_request_failed
) {
2366 b43info(dev
->wl
, "Hardware crypto acceleration not supported by firmware\n");
2367 /* Disable hardware crypto and fall back to software crypto. */
2368 dev
->hwcrypto_enabled
= 0;
2370 if (!(fwcapa
& B43_FWCAPA_QOS
)) {
2371 b43info(dev
->wl
, "QoS not supported by firmware\n");
2372 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2373 * ieee80211_unregister to make sure the networking core can
2374 * properly free possible resources. */
2375 dev
->wl
->hw
->queues
= 1;
2376 dev
->qos_enabled
= 0;
2379 b43info(dev
->wl
, "Loading firmware version %u.%u "
2380 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2382 (fwdate
>> 12) & 0xF, (fwdate
>> 8) & 0xF, fwdate
& 0xFF,
2383 (fwtime
>> 11) & 0x1F, (fwtime
>> 5) & 0x3F, fwtime
& 0x1F);
2384 if (dev
->fw
.pcm_request_failed
) {
2385 b43warn(dev
->wl
, "No \"pcm5.fw\" firmware file found. "
2386 "Hardware accelerated cryptography is disabled.\n");
2387 b43_print_fw_helptext(dev
->wl
, 0);
2391 if (b43_is_old_txhdr_format(dev
)) {
2392 /* We're over the deadline, but we keep support for old fw
2393 * until it turns out to be in major conflict with something new. */
2394 b43warn(dev
->wl
, "You are using an old firmware image. "
2395 "Support for old firmware will be removed soon "
2396 "(official deadline was July 2008).\n");
2397 b43_print_fw_helptext(dev
->wl
, 0);
2403 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2404 macctl
&= ~B43_MACCTL_PSM_RUN
;
2405 macctl
|= B43_MACCTL_PSM_JMP0
;
2406 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2411 static int b43_write_initvals(struct b43_wldev
*dev
,
2412 const struct b43_iv
*ivals
,
2416 const struct b43_iv
*iv
;
2421 BUILD_BUG_ON(sizeof(struct b43_iv
) != 6);
2423 for (i
= 0; i
< count
; i
++) {
2424 if (array_size
< sizeof(iv
->offset_size
))
2426 array_size
-= sizeof(iv
->offset_size
);
2427 offset
= be16_to_cpu(iv
->offset_size
);
2428 bit32
= !!(offset
& B43_IV_32BIT
);
2429 offset
&= B43_IV_OFFSET_MASK
;
2430 if (offset
>= 0x1000)
2435 if (array_size
< sizeof(iv
->data
.d32
))
2437 array_size
-= sizeof(iv
->data
.d32
);
2439 value
= get_unaligned_be32(&iv
->data
.d32
);
2440 b43_write32(dev
, offset
, value
);
2442 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
2448 if (array_size
< sizeof(iv
->data
.d16
))
2450 array_size
-= sizeof(iv
->data
.d16
);
2452 value
= be16_to_cpu(iv
->data
.d16
);
2453 b43_write16(dev
, offset
, value
);
2455 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
2466 b43err(dev
->wl
, "Initial Values Firmware file-format error.\n");
2467 b43_print_fw_helptext(dev
->wl
, 1);
2472 static int b43_upload_initvals(struct b43_wldev
*dev
)
2474 const size_t hdr_len
= sizeof(struct b43_fw_header
);
2475 const struct b43_fw_header
*hdr
;
2476 struct b43_firmware
*fw
= &dev
->fw
;
2477 const struct b43_iv
*ivals
;
2481 hdr
= (const struct b43_fw_header
*)(fw
->initvals
.data
->data
);
2482 ivals
= (const struct b43_iv
*)(fw
->initvals
.data
->data
+ hdr_len
);
2483 count
= be32_to_cpu(hdr
->size
);
2484 err
= b43_write_initvals(dev
, ivals
, count
,
2485 fw
->initvals
.data
->size
- hdr_len
);
2488 if (fw
->initvals_band
.data
) {
2489 hdr
= (const struct b43_fw_header
*)(fw
->initvals_band
.data
->data
);
2490 ivals
= (const struct b43_iv
*)(fw
->initvals_band
.data
->data
+ hdr_len
);
2491 count
= be32_to_cpu(hdr
->size
);
2492 err
= b43_write_initvals(dev
, ivals
, count
,
2493 fw
->initvals_band
.data
->size
- hdr_len
);
2502 /* Initialize the GPIOs
2503 * http://bcm-specs.sipsolutions.net/GPIO
2505 static int b43_gpio_init(struct b43_wldev
*dev
)
2507 struct ssb_bus
*bus
= dev
->dev
->bus
;
2508 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
2511 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2512 & ~B43_MACCTL_GPOUTSMSK
);
2514 b43_write16(dev
, B43_MMIO_GPIO_MASK
, b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2519 if (dev
->dev
->bus
->chip_id
== 0x4301) {
2523 if (0 /* FIXME: conditional unknown */ ) {
2524 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
2525 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2530 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_PACTRL
) {
2531 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
2532 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2537 if (dev
->dev
->id
.revision
>= 2)
2538 mask
|= 0x0010; /* FIXME: This is redundant. */
2540 #ifdef CONFIG_SSB_DRIVER_PCICORE
2541 pcidev
= bus
->pcicore
.dev
;
2543 gpiodev
= bus
->chipco
.dev
? : pcidev
;
2546 ssb_write32(gpiodev
, B43_GPIO_CONTROL
,
2547 (ssb_read32(gpiodev
, B43_GPIO_CONTROL
)
2553 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2554 static void b43_gpio_cleanup(struct b43_wldev
*dev
)
2556 struct ssb_bus
*bus
= dev
->dev
->bus
;
2557 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
2559 #ifdef CONFIG_SSB_DRIVER_PCICORE
2560 pcidev
= bus
->pcicore
.dev
;
2562 gpiodev
= bus
->chipco
.dev
? : pcidev
;
2565 ssb_write32(gpiodev
, B43_GPIO_CONTROL
, 0);
2568 /* http://bcm-specs.sipsolutions.net/EnableMac */
2569 void b43_mac_enable(struct b43_wldev
*dev
)
2571 if (b43_debug(dev
, B43_DBG_FIRMWARE
)) {
2574 fwstate
= b43_shm_read16(dev
, B43_SHM_SHARED
,
2575 B43_SHM_SH_UCODESTAT
);
2576 if ((fwstate
!= B43_SHM_SH_UCODESTAT_SUSP
) &&
2577 (fwstate
!= B43_SHM_SH_UCODESTAT_SLEEP
)) {
2578 b43err(dev
->wl
, "b43_mac_enable(): The firmware "
2579 "should be suspended, but current state is %u\n",
2584 dev
->mac_suspended
--;
2585 B43_WARN_ON(dev
->mac_suspended
< 0);
2586 if (dev
->mac_suspended
== 0) {
2587 b43_write32(dev
, B43_MMIO_MACCTL
,
2588 b43_read32(dev
, B43_MMIO_MACCTL
)
2589 | B43_MACCTL_ENABLED
);
2590 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
,
2591 B43_IRQ_MAC_SUSPENDED
);
2593 b43_read32(dev
, B43_MMIO_MACCTL
);
2594 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2595 b43_power_saving_ctl_bits(dev
, 0);
2599 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2600 void b43_mac_suspend(struct b43_wldev
*dev
)
2606 B43_WARN_ON(dev
->mac_suspended
< 0);
2608 if (dev
->mac_suspended
== 0) {
2609 b43_power_saving_ctl_bits(dev
, B43_PS_AWAKE
);
2610 b43_write32(dev
, B43_MMIO_MACCTL
,
2611 b43_read32(dev
, B43_MMIO_MACCTL
)
2612 & ~B43_MACCTL_ENABLED
);
2613 /* force pci to flush the write */
2614 b43_read32(dev
, B43_MMIO_MACCTL
);
2615 for (i
= 35; i
; i
--) {
2616 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2617 if (tmp
& B43_IRQ_MAC_SUSPENDED
)
2621 /* Hm, it seems this will take some time. Use msleep(). */
2622 for (i
= 40; i
; i
--) {
2623 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2624 if (tmp
& B43_IRQ_MAC_SUSPENDED
)
2628 b43err(dev
->wl
, "MAC suspend failed\n");
2631 dev
->mac_suspended
++;
2634 static void b43_adjust_opmode(struct b43_wldev
*dev
)
2636 struct b43_wl
*wl
= dev
->wl
;
2640 ctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2641 /* Reset status to STA infrastructure mode. */
2642 ctl
&= ~B43_MACCTL_AP
;
2643 ctl
&= ~B43_MACCTL_KEEP_CTL
;
2644 ctl
&= ~B43_MACCTL_KEEP_BADPLCP
;
2645 ctl
&= ~B43_MACCTL_KEEP_BAD
;
2646 ctl
&= ~B43_MACCTL_PROMISC
;
2647 ctl
&= ~B43_MACCTL_BEACPROMISC
;
2648 ctl
|= B43_MACCTL_INFRA
;
2650 if (b43_is_mode(wl
, NL80211_IFTYPE_AP
) ||
2651 b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
))
2652 ctl
|= B43_MACCTL_AP
;
2653 else if (b43_is_mode(wl
, NL80211_IFTYPE_ADHOC
))
2654 ctl
&= ~B43_MACCTL_INFRA
;
2656 if (wl
->filter_flags
& FIF_CONTROL
)
2657 ctl
|= B43_MACCTL_KEEP_CTL
;
2658 if (wl
->filter_flags
& FIF_FCSFAIL
)
2659 ctl
|= B43_MACCTL_KEEP_BAD
;
2660 if (wl
->filter_flags
& FIF_PLCPFAIL
)
2661 ctl
|= B43_MACCTL_KEEP_BADPLCP
;
2662 if (wl
->filter_flags
& FIF_PROMISC_IN_BSS
)
2663 ctl
|= B43_MACCTL_PROMISC
;
2664 if (wl
->filter_flags
& FIF_BCN_PRBRESP_PROMISC
)
2665 ctl
|= B43_MACCTL_BEACPROMISC
;
2667 /* Workaround: On old hardware the HW-MAC-address-filter
2668 * doesn't work properly, so always run promisc in filter
2669 * it in software. */
2670 if (dev
->dev
->id
.revision
<= 4)
2671 ctl
|= B43_MACCTL_PROMISC
;
2673 b43_write32(dev
, B43_MMIO_MACCTL
, ctl
);
2676 if ((ctl
& B43_MACCTL_INFRA
) && !(ctl
& B43_MACCTL_AP
)) {
2677 if (dev
->dev
->bus
->chip_id
== 0x4306 &&
2678 dev
->dev
->bus
->chip_rev
== 3)
2683 b43_write16(dev
, 0x612, cfp_pretbtt
);
2685 /* FIXME: We don't currently implement the PMQ mechanism,
2686 * so always disable it. If we want to implement PMQ,
2687 * we need to enable it here (clear DISCPMQ) in AP mode.
2689 if (0 /* ctl & B43_MACCTL_AP */) {
2690 b43_write32(dev
, B43_MMIO_MACCTL
,
2691 b43_read32(dev
, B43_MMIO_MACCTL
)
2692 & ~B43_MACCTL_DISCPMQ
);
2694 b43_write32(dev
, B43_MMIO_MACCTL
,
2695 b43_read32(dev
, B43_MMIO_MACCTL
)
2696 | B43_MACCTL_DISCPMQ
);
2700 static void b43_rate_memory_write(struct b43_wldev
*dev
, u16 rate
, int is_ofdm
)
2706 offset
+= (b43_plcp_get_ratecode_ofdm(rate
) & 0x000F) * 2;
2709 offset
+= (b43_plcp_get_ratecode_cck(rate
) & 0x000F) * 2;
2711 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ 0x20,
2712 b43_shm_read16(dev
, B43_SHM_SHARED
, offset
));
2715 static void b43_rate_memory_init(struct b43_wldev
*dev
)
2717 switch (dev
->phy
.type
) {
2721 case B43_PHYTYPE_LP
:
2722 b43_rate_memory_write(dev
, B43_OFDM_RATE_6MB
, 1);
2723 b43_rate_memory_write(dev
, B43_OFDM_RATE_12MB
, 1);
2724 b43_rate_memory_write(dev
, B43_OFDM_RATE_18MB
, 1);
2725 b43_rate_memory_write(dev
, B43_OFDM_RATE_24MB
, 1);
2726 b43_rate_memory_write(dev
, B43_OFDM_RATE_36MB
, 1);
2727 b43_rate_memory_write(dev
, B43_OFDM_RATE_48MB
, 1);
2728 b43_rate_memory_write(dev
, B43_OFDM_RATE_54MB
, 1);
2729 if (dev
->phy
.type
== B43_PHYTYPE_A
)
2733 b43_rate_memory_write(dev
, B43_CCK_RATE_1MB
, 0);
2734 b43_rate_memory_write(dev
, B43_CCK_RATE_2MB
, 0);
2735 b43_rate_memory_write(dev
, B43_CCK_RATE_5MB
, 0);
2736 b43_rate_memory_write(dev
, B43_CCK_RATE_11MB
, 0);
2743 /* Set the default values for the PHY TX Control Words. */
2744 static void b43_set_phytxctl_defaults(struct b43_wldev
*dev
)
2748 ctl
|= B43_TXH_PHY_ENC_CCK
;
2749 ctl
|= B43_TXH_PHY_ANT01AUTO
;
2750 ctl
|= B43_TXH_PHY_TXPWR
;
2752 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
, ctl
);
2753 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
, ctl
);
2754 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
, ctl
);
2757 /* Set the TX-Antenna for management frames sent by firmware. */
2758 static void b43_mgmtframe_txantenna(struct b43_wldev
*dev
, int antenna
)
2763 ant
= b43_antenna_to_phyctl(antenna
);
2766 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
);
2767 tmp
= (tmp
& ~B43_TXH_PHY_ANT
) | ant
;
2768 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
, tmp
);
2769 /* For Probe Resposes */
2770 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
);
2771 tmp
= (tmp
& ~B43_TXH_PHY_ANT
) | ant
;
2772 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
, tmp
);
2775 /* This is the opposite of b43_chip_init() */
2776 static void b43_chip_exit(struct b43_wldev
*dev
)
2779 b43_gpio_cleanup(dev
);
2780 /* firmware is released later */
2783 /* Initialize the chip
2784 * http://bcm-specs.sipsolutions.net/ChipInit
2786 static int b43_chip_init(struct b43_wldev
*dev
)
2788 struct b43_phy
*phy
= &dev
->phy
;
2790 u32 value32
, macctl
;
2793 /* Initialize the MAC control */
2794 macctl
= B43_MACCTL_IHR_ENABLED
| B43_MACCTL_SHM_ENABLED
;
2796 macctl
|= B43_MACCTL_GMODE
;
2797 macctl
|= B43_MACCTL_INFRA
;
2798 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2800 err
= b43_request_firmware(dev
);
2803 err
= b43_upload_microcode(dev
);
2805 goto out
; /* firmware is released later */
2807 err
= b43_gpio_init(dev
);
2809 goto out
; /* firmware is released later */
2811 err
= b43_upload_initvals(dev
);
2813 goto err_gpio_clean
;
2815 /* Turn the Analog on and initialize the PHY. */
2816 phy
->ops
->switch_analog(dev
, 1);
2817 err
= b43_phy_init(dev
);
2819 goto err_gpio_clean
;
2821 /* Disable Interference Mitigation. */
2822 if (phy
->ops
->interf_mitigation
)
2823 phy
->ops
->interf_mitigation(dev
, B43_INTERFMODE_NONE
);
2825 /* Select the antennae */
2826 if (phy
->ops
->set_rx_antenna
)
2827 phy
->ops
->set_rx_antenna(dev
, B43_ANTENNA_DEFAULT
);
2828 b43_mgmtframe_txantenna(dev
, B43_ANTENNA_DEFAULT
);
2830 if (phy
->type
== B43_PHYTYPE_B
) {
2831 value16
= b43_read16(dev
, 0x005E);
2833 b43_write16(dev
, 0x005E, value16
);
2835 b43_write32(dev
, 0x0100, 0x01000000);
2836 if (dev
->dev
->id
.revision
< 5)
2837 b43_write32(dev
, 0x010C, 0x01000000);
2839 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2840 & ~B43_MACCTL_INFRA
);
2841 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2842 | B43_MACCTL_INFRA
);
2844 /* Probe Response Timeout value */
2845 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2846 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0074, 0x0000);
2848 /* Initially set the wireless operation mode. */
2849 b43_adjust_opmode(dev
);
2851 if (dev
->dev
->id
.revision
< 3) {
2852 b43_write16(dev
, 0x060E, 0x0000);
2853 b43_write16(dev
, 0x0610, 0x8000);
2854 b43_write16(dev
, 0x0604, 0x0000);
2855 b43_write16(dev
, 0x0606, 0x0200);
2857 b43_write32(dev
, 0x0188, 0x80000000);
2858 b43_write32(dev
, 0x018C, 0x02000000);
2860 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, 0x00004000);
2861 b43_write32(dev
, B43_MMIO_DMA0_IRQ_MASK
, 0x0001DC00);
2862 b43_write32(dev
, B43_MMIO_DMA1_IRQ_MASK
, 0x0000DC00);
2863 b43_write32(dev
, B43_MMIO_DMA2_IRQ_MASK
, 0x0000DC00);
2864 b43_write32(dev
, B43_MMIO_DMA3_IRQ_MASK
, 0x0001DC00);
2865 b43_write32(dev
, B43_MMIO_DMA4_IRQ_MASK
, 0x0000DC00);
2866 b43_write32(dev
, B43_MMIO_DMA5_IRQ_MASK
, 0x0000DC00);
2868 value32
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
2869 value32
|= 0x00100000;
2870 ssb_write32(dev
->dev
, SSB_TMSLOW
, value32
);
2872 b43_write16(dev
, B43_MMIO_POWERUP_DELAY
,
2873 dev
->dev
->bus
->chipco
.fast_pwrup_delay
);
2876 b43dbg(dev
->wl
, "Chip initialized\n");
2881 b43_gpio_cleanup(dev
);
2885 static void b43_periodic_every60sec(struct b43_wldev
*dev
)
2887 const struct b43_phy_operations
*ops
= dev
->phy
.ops
;
2889 if (ops
->pwork_60sec
)
2890 ops
->pwork_60sec(dev
);
2892 /* Force check the TX power emission now. */
2893 b43_phy_txpower_check(dev
, B43_TXPWR_IGNORE_TIME
);
2896 static void b43_periodic_every30sec(struct b43_wldev
*dev
)
2898 /* Update device statistics. */
2899 b43_calculate_link_quality(dev
);
2902 static void b43_periodic_every15sec(struct b43_wldev
*dev
)
2904 struct b43_phy
*phy
= &dev
->phy
;
2907 if (dev
->fw
.opensource
) {
2908 /* Check if the firmware is still alive.
2909 * It will reset the watchdog counter to 0 in its idle loop. */
2910 wdr
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, B43_WATCHDOG_REG
);
2911 if (unlikely(wdr
)) {
2912 b43err(dev
->wl
, "Firmware watchdog: The firmware died!\n");
2913 b43_controller_restart(dev
, "Firmware watchdog");
2916 b43_shm_write16(dev
, B43_SHM_SCRATCH
,
2917 B43_WATCHDOG_REG
, 1);
2921 if (phy
->ops
->pwork_15sec
)
2922 phy
->ops
->pwork_15sec(dev
);
2924 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
2928 if (b43_debug(dev
, B43_DBG_VERBOSESTATS
)) {
2931 b43dbg(dev
->wl
, "Stats: %7u IRQs/sec, %7u TX/sec, %7u RX/sec\n",
2932 dev
->irq_count
/ 15,
2934 dev
->rx_count
/ 15);
2938 for (i
= 0; i
< ARRAY_SIZE(dev
->irq_bit_count
); i
++) {
2939 if (dev
->irq_bit_count
[i
]) {
2940 b43dbg(dev
->wl
, "Stats: %7u IRQ-%02u/sec (0x%08X)\n",
2941 dev
->irq_bit_count
[i
] / 15, i
, (1 << i
));
2942 dev
->irq_bit_count
[i
] = 0;
2949 static void do_periodic_work(struct b43_wldev
*dev
)
2953 state
= dev
->periodic_state
;
2955 b43_periodic_every60sec(dev
);
2957 b43_periodic_every30sec(dev
);
2958 b43_periodic_every15sec(dev
);
2961 /* Periodic work locking policy:
2962 * The whole periodic work handler is protected by
2963 * wl->mutex. If another lock is needed somewhere in the
2964 * pwork callchain, it's aquired in-place, where it's needed.
2966 static void b43_periodic_work_handler(struct work_struct
*work
)
2968 struct b43_wldev
*dev
= container_of(work
, struct b43_wldev
,
2969 periodic_work
.work
);
2970 struct b43_wl
*wl
= dev
->wl
;
2971 unsigned long delay
;
2973 mutex_lock(&wl
->mutex
);
2975 if (unlikely(b43_status(dev
) != B43_STAT_STARTED
))
2977 if (b43_debug(dev
, B43_DBG_PWORK_STOP
))
2980 do_periodic_work(dev
);
2982 dev
->periodic_state
++;
2984 if (b43_debug(dev
, B43_DBG_PWORK_FAST
))
2985 delay
= msecs_to_jiffies(50);
2987 delay
= round_jiffies_relative(HZ
* 15);
2988 ieee80211_queue_delayed_work(wl
->hw
, &dev
->periodic_work
, delay
);
2990 mutex_unlock(&wl
->mutex
);
2993 static void b43_periodic_tasks_setup(struct b43_wldev
*dev
)
2995 struct delayed_work
*work
= &dev
->periodic_work
;
2997 dev
->periodic_state
= 0;
2998 INIT_DELAYED_WORK(work
, b43_periodic_work_handler
);
2999 ieee80211_queue_delayed_work(dev
->wl
->hw
, work
, 0);
3002 /* Check if communication with the device works correctly. */
3003 static int b43_validate_chipaccess(struct b43_wldev
*dev
)
3005 u32 v
, backup0
, backup4
;
3007 backup0
= b43_shm_read32(dev
, B43_SHM_SHARED
, 0);
3008 backup4
= b43_shm_read32(dev
, B43_SHM_SHARED
, 4);
3010 /* Check for read/write and endianness problems. */
3011 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0x55AAAA55);
3012 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0x55AAAA55)
3014 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0xAA5555AA);
3015 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0xAA5555AA)
3018 /* Check if unaligned 32bit SHM_SHARED access works properly.
3019 * However, don't bail out on failure, because it's noncritical. */
3020 b43_shm_write16(dev
, B43_SHM_SHARED
, 0, 0x1122);
3021 b43_shm_write16(dev
, B43_SHM_SHARED
, 2, 0x3344);
3022 b43_shm_write16(dev
, B43_SHM_SHARED
, 4, 0x5566);
3023 b43_shm_write16(dev
, B43_SHM_SHARED
, 6, 0x7788);
3024 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 2) != 0x55663344)
3025 b43warn(dev
->wl
, "Unaligned 32bit SHM read access is broken\n");
3026 b43_shm_write32(dev
, B43_SHM_SHARED
, 2, 0xAABBCCDD);
3027 if (b43_shm_read16(dev
, B43_SHM_SHARED
, 0) != 0x1122 ||
3028 b43_shm_read16(dev
, B43_SHM_SHARED
, 2) != 0xCCDD ||
3029 b43_shm_read16(dev
, B43_SHM_SHARED
, 4) != 0xAABB ||
3030 b43_shm_read16(dev
, B43_SHM_SHARED
, 6) != 0x7788)
3031 b43warn(dev
->wl
, "Unaligned 32bit SHM write access is broken\n");
3033 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, backup0
);
3034 b43_shm_write32(dev
, B43_SHM_SHARED
, 4, backup4
);
3036 if ((dev
->dev
->id
.revision
>= 3) && (dev
->dev
->id
.revision
<= 10)) {
3037 /* The 32bit register shadows the two 16bit registers
3038 * with update sideeffects. Validate this. */
3039 b43_write16(dev
, B43_MMIO_TSF_CFP_START
, 0xAAAA);
3040 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0xCCCCBBBB);
3041 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_LOW
) != 0xBBBB)
3043 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_HIGH
) != 0xCCCC)
3046 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0);
3048 v
= b43_read32(dev
, B43_MMIO_MACCTL
);
3049 v
|= B43_MACCTL_GMODE
;
3050 if (v
!= (B43_MACCTL_GMODE
| B43_MACCTL_IHR_ENABLED
))
3055 b43err(dev
->wl
, "Failed to validate the chipaccess\n");
3059 static void b43_security_init(struct b43_wldev
*dev
)
3061 dev
->ktp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_KTP
);
3062 /* KTP is a word address, but we address SHM bytewise.
3063 * So multiply by two.
3066 /* Number of RCMTA address slots */
3067 b43_write16(dev
, B43_MMIO_RCMTA_COUNT
, B43_NR_PAIRWISE_KEYS
);
3068 /* Clear the key memory. */
3069 b43_clear_keys(dev
);
3072 #ifdef CONFIG_B43_HWRNG
3073 static int b43_rng_read(struct hwrng
*rng
, u32
*data
)
3075 struct b43_wl
*wl
= (struct b43_wl
*)rng
->priv
;
3076 struct b43_wldev
*dev
;
3077 int count
= -ENODEV
;
3079 mutex_lock(&wl
->mutex
);
3080 dev
= wl
->current_dev
;
3081 if (likely(dev
&& b43_status(dev
) >= B43_STAT_INITIALIZED
)) {
3082 *data
= b43_read16(dev
, B43_MMIO_RNG
);
3083 count
= sizeof(u16
);
3085 mutex_unlock(&wl
->mutex
);
3089 #endif /* CONFIG_B43_HWRNG */
3091 static void b43_rng_exit(struct b43_wl
*wl
)
3093 #ifdef CONFIG_B43_HWRNG
3094 if (wl
->rng_initialized
)
3095 hwrng_unregister(&wl
->rng
);
3096 #endif /* CONFIG_B43_HWRNG */
3099 static int b43_rng_init(struct b43_wl
*wl
)
3103 #ifdef CONFIG_B43_HWRNG
3104 snprintf(wl
->rng_name
, ARRAY_SIZE(wl
->rng_name
),
3105 "%s_%s", KBUILD_MODNAME
, wiphy_name(wl
->hw
->wiphy
));
3106 wl
->rng
.name
= wl
->rng_name
;
3107 wl
->rng
.data_read
= b43_rng_read
;
3108 wl
->rng
.priv
= (unsigned long)wl
;
3109 wl
->rng_initialized
= 1;
3110 err
= hwrng_register(&wl
->rng
);
3112 wl
->rng_initialized
= 0;
3113 b43err(wl
, "Failed to register the random "
3114 "number generator (%d)\n", err
);
3116 #endif /* CONFIG_B43_HWRNG */
3121 static void b43_tx_work(struct work_struct
*work
)
3123 struct b43_wl
*wl
= container_of(work
, struct b43_wl
, tx_work
);
3124 struct b43_wldev
*dev
;
3125 struct sk_buff
*skb
;
3128 mutex_lock(&wl
->mutex
);
3129 dev
= wl
->current_dev
;
3130 if (unlikely(!dev
|| b43_status(dev
) < B43_STAT_STARTED
)) {
3131 mutex_unlock(&wl
->mutex
);
3135 while (skb_queue_len(&wl
->tx_queue
)) {
3136 skb
= skb_dequeue(&wl
->tx_queue
);
3138 if (b43_using_pio_transfers(dev
))
3139 err
= b43_pio_tx(dev
, skb
);
3141 err
= b43_dma_tx(dev
, skb
);
3143 dev_kfree_skb(skb
); /* Drop it */
3149 mutex_unlock(&wl
->mutex
);
3152 static int b43_op_tx(struct ieee80211_hw
*hw
,
3153 struct sk_buff
*skb
)
3155 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3157 if (unlikely(skb
->len
< 2 + 2 + 6)) {
3158 /* Too short, this can't be a valid frame. */
3159 dev_kfree_skb_any(skb
);
3160 return NETDEV_TX_OK
;
3162 B43_WARN_ON(skb_shinfo(skb
)->nr_frags
);
3164 skb_queue_tail(&wl
->tx_queue
, skb
);
3165 ieee80211_queue_work(wl
->hw
, &wl
->tx_work
);
3167 return NETDEV_TX_OK
;
3170 static void b43_qos_params_upload(struct b43_wldev
*dev
,
3171 const struct ieee80211_tx_queue_params
*p
,
3174 u16 params
[B43_NR_QOSPARAMS
];
3178 if (!dev
->qos_enabled
)
3181 bslots
= b43_read16(dev
, B43_MMIO_RNG
) & p
->cw_min
;
3183 memset(¶ms
, 0, sizeof(params
));
3185 params
[B43_QOSPARAM_TXOP
] = p
->txop
* 32;
3186 params
[B43_QOSPARAM_CWMIN
] = p
->cw_min
;
3187 params
[B43_QOSPARAM_CWMAX
] = p
->cw_max
;
3188 params
[B43_QOSPARAM_CWCUR
] = p
->cw_min
;
3189 params
[B43_QOSPARAM_AIFS
] = p
->aifs
;
3190 params
[B43_QOSPARAM_BSLOTS
] = bslots
;
3191 params
[B43_QOSPARAM_REGGAP
] = bslots
+ p
->aifs
;
3193 for (i
= 0; i
< ARRAY_SIZE(params
); i
++) {
3194 if (i
== B43_QOSPARAM_STATUS
) {
3195 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
,
3196 shm_offset
+ (i
* 2));
3197 /* Mark the parameters as updated. */
3199 b43_shm_write16(dev
, B43_SHM_SHARED
,
3200 shm_offset
+ (i
* 2),
3203 b43_shm_write16(dev
, B43_SHM_SHARED
,
3204 shm_offset
+ (i
* 2),
3210 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3211 static const u16 b43_qos_shm_offsets
[] = {
3212 /* [mac80211-queue-nr] = SHM_OFFSET, */
3213 [0] = B43_QOS_VOICE
,
3214 [1] = B43_QOS_VIDEO
,
3215 [2] = B43_QOS_BESTEFFORT
,
3216 [3] = B43_QOS_BACKGROUND
,
3219 /* Update all QOS parameters in hardware. */
3220 static void b43_qos_upload_all(struct b43_wldev
*dev
)
3222 struct b43_wl
*wl
= dev
->wl
;
3223 struct b43_qos_params
*params
;
3226 if (!dev
->qos_enabled
)
3229 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets
) !=
3230 ARRAY_SIZE(wl
->qos_params
));
3232 b43_mac_suspend(dev
);
3233 for (i
= 0; i
< ARRAY_SIZE(wl
->qos_params
); i
++) {
3234 params
= &(wl
->qos_params
[i
]);
3235 b43_qos_params_upload(dev
, &(params
->p
),
3236 b43_qos_shm_offsets
[i
]);
3238 b43_mac_enable(dev
);
3241 static void b43_qos_clear(struct b43_wl
*wl
)
3243 struct b43_qos_params
*params
;
3246 /* Initialize QoS parameters to sane defaults. */
3248 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets
) !=
3249 ARRAY_SIZE(wl
->qos_params
));
3251 for (i
= 0; i
< ARRAY_SIZE(wl
->qos_params
); i
++) {
3252 params
= &(wl
->qos_params
[i
]);
3254 switch (b43_qos_shm_offsets
[i
]) {
3258 params
->p
.cw_min
= 0x0001;
3259 params
->p
.cw_max
= 0x0001;
3264 params
->p
.cw_min
= 0x0001;
3265 params
->p
.cw_max
= 0x0001;
3267 case B43_QOS_BESTEFFORT
:
3270 params
->p
.cw_min
= 0x0001;
3271 params
->p
.cw_max
= 0x03FF;
3273 case B43_QOS_BACKGROUND
:
3276 params
->p
.cw_min
= 0x0001;
3277 params
->p
.cw_max
= 0x03FF;
3285 /* Initialize the core's QOS capabilities */
3286 static void b43_qos_init(struct b43_wldev
*dev
)
3288 if (!dev
->qos_enabled
) {
3289 /* Disable QOS support. */
3290 b43_hf_write(dev
, b43_hf_read(dev
) & ~B43_HF_EDCF
);
3291 b43_write16(dev
, B43_MMIO_IFSCTL
,
3292 b43_read16(dev
, B43_MMIO_IFSCTL
)
3293 & ~B43_MMIO_IFSCTL_USE_EDCF
);
3294 b43dbg(dev
->wl
, "QoS disabled\n");
3298 /* Upload the current QOS parameters. */
3299 b43_qos_upload_all(dev
);
3301 /* Enable QOS support. */
3302 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_EDCF
);
3303 b43_write16(dev
, B43_MMIO_IFSCTL
,
3304 b43_read16(dev
, B43_MMIO_IFSCTL
)
3305 | B43_MMIO_IFSCTL_USE_EDCF
);
3306 b43dbg(dev
->wl
, "QoS enabled\n");
3309 static int b43_op_conf_tx(struct ieee80211_hw
*hw
, u16 _queue
,
3310 const struct ieee80211_tx_queue_params
*params
)
3312 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3313 struct b43_wldev
*dev
;
3314 unsigned int queue
= (unsigned int)_queue
;
3317 if (queue
>= ARRAY_SIZE(wl
->qos_params
)) {
3318 /* Queue not available or don't support setting
3319 * params on this queue. Return success to not
3320 * confuse mac80211. */
3323 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets
) !=
3324 ARRAY_SIZE(wl
->qos_params
));
3326 mutex_lock(&wl
->mutex
);
3327 dev
= wl
->current_dev
;
3328 if (unlikely(!dev
|| (b43_status(dev
) < B43_STAT_INITIALIZED
)))
3331 memcpy(&(wl
->qos_params
[queue
].p
), params
, sizeof(*params
));
3332 b43_mac_suspend(dev
);
3333 b43_qos_params_upload(dev
, &(wl
->qos_params
[queue
].p
),
3334 b43_qos_shm_offsets
[queue
]);
3335 b43_mac_enable(dev
);
3339 mutex_unlock(&wl
->mutex
);
3344 static int b43_op_get_tx_stats(struct ieee80211_hw
*hw
,
3345 struct ieee80211_tx_queue_stats
*stats
)
3347 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3348 struct b43_wldev
*dev
;
3351 mutex_lock(&wl
->mutex
);
3352 dev
= wl
->current_dev
;
3353 if (dev
&& b43_status(dev
) >= B43_STAT_STARTED
) {
3354 if (b43_using_pio_transfers(dev
))
3355 b43_pio_get_tx_stats(dev
, stats
);
3357 b43_dma_get_tx_stats(dev
, stats
);
3360 mutex_unlock(&wl
->mutex
);
3365 static int b43_op_get_stats(struct ieee80211_hw
*hw
,
3366 struct ieee80211_low_level_stats
*stats
)
3368 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3370 mutex_lock(&wl
->mutex
);
3371 memcpy(stats
, &wl
->ieee_stats
, sizeof(*stats
));
3372 mutex_unlock(&wl
->mutex
);
3377 static u64
b43_op_get_tsf(struct ieee80211_hw
*hw
)
3379 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3380 struct b43_wldev
*dev
;
3383 mutex_lock(&wl
->mutex
);
3384 dev
= wl
->current_dev
;
3386 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
))
3387 b43_tsf_read(dev
, &tsf
);
3391 mutex_unlock(&wl
->mutex
);
3396 static void b43_op_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
3398 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3399 struct b43_wldev
*dev
;
3401 mutex_lock(&wl
->mutex
);
3402 dev
= wl
->current_dev
;
3404 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
))
3405 b43_tsf_write(dev
, tsf
);
3407 mutex_unlock(&wl
->mutex
);
3410 static void b43_put_phy_into_reset(struct b43_wldev
*dev
)
3412 struct ssb_device
*sdev
= dev
->dev
;
3415 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
3416 tmslow
&= ~B43_TMSLOW_GMODE
;
3417 tmslow
|= B43_TMSLOW_PHYRESET
;
3418 tmslow
|= SSB_TMSLOW_FGC
;
3419 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
3422 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
3423 tmslow
&= ~SSB_TMSLOW_FGC
;
3424 tmslow
|= B43_TMSLOW_PHYRESET
;
3425 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
3429 static const char *band_to_string(enum ieee80211_band band
)
3432 case IEEE80211_BAND_5GHZ
:
3434 case IEEE80211_BAND_2GHZ
:
3443 /* Expects wl->mutex locked */
3444 static int b43_switch_band(struct b43_wl
*wl
, struct ieee80211_channel
*chan
)
3446 struct b43_wldev
*up_dev
= NULL
;
3447 struct b43_wldev
*down_dev
;
3448 struct b43_wldev
*d
;
3450 bool uninitialized_var(gmode
);
3453 /* Find a device and PHY which supports the band. */
3454 list_for_each_entry(d
, &wl
->devlist
, list
) {
3455 switch (chan
->band
) {
3456 case IEEE80211_BAND_5GHZ
:
3457 if (d
->phy
.supports_5ghz
) {
3462 case IEEE80211_BAND_2GHZ
:
3463 if (d
->phy
.supports_2ghz
) {
3476 b43err(wl
, "Could not find a device for %s-GHz band operation\n",
3477 band_to_string(chan
->band
));
3480 if ((up_dev
== wl
->current_dev
) &&
3481 (!!wl
->current_dev
->phy
.gmode
== !!gmode
)) {
3482 /* This device is already running. */
3485 b43dbg(wl
, "Switching to %s-GHz band\n",
3486 band_to_string(chan
->band
));
3487 down_dev
= wl
->current_dev
;
3489 prev_status
= b43_status(down_dev
);
3490 /* Shutdown the currently running core. */
3491 if (prev_status
>= B43_STAT_STARTED
)
3492 down_dev
= b43_wireless_core_stop(down_dev
);
3493 if (prev_status
>= B43_STAT_INITIALIZED
)
3494 b43_wireless_core_exit(down_dev
);
3496 if (down_dev
!= up_dev
) {
3497 /* We switch to a different core, so we put PHY into
3498 * RESET on the old core. */
3499 b43_put_phy_into_reset(down_dev
);
3502 /* Now start the new core. */
3503 up_dev
->phy
.gmode
= gmode
;
3504 if (prev_status
>= B43_STAT_INITIALIZED
) {
3505 err
= b43_wireless_core_init(up_dev
);
3507 b43err(wl
, "Fatal: Could not initialize device for "
3508 "selected %s-GHz band\n",
3509 band_to_string(chan
->band
));
3513 if (prev_status
>= B43_STAT_STARTED
) {
3514 err
= b43_wireless_core_start(up_dev
);
3516 b43err(wl
, "Fatal: Coult not start device for "
3517 "selected %s-GHz band\n",
3518 band_to_string(chan
->band
));
3519 b43_wireless_core_exit(up_dev
);
3523 B43_WARN_ON(b43_status(up_dev
) != prev_status
);
3525 wl
->current_dev
= up_dev
;
3529 /* Whoops, failed to init the new core. No core is operating now. */
3530 wl
->current_dev
= NULL
;
3534 /* Write the short and long frame retry limit values. */
3535 static void b43_set_retry_limits(struct b43_wldev
*dev
,
3536 unsigned int short_retry
,
3537 unsigned int long_retry
)
3539 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3540 * the chip-internal counter. */
3541 short_retry
= min(short_retry
, (unsigned int)0xF);
3542 long_retry
= min(long_retry
, (unsigned int)0xF);
3544 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_SRLIMIT
,
3546 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_LRLIMIT
,
3550 static int b43_op_config(struct ieee80211_hw
*hw
, u32 changed
)
3552 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3553 struct b43_wldev
*dev
;
3554 struct b43_phy
*phy
;
3555 struct ieee80211_conf
*conf
= &hw
->conf
;
3559 mutex_lock(&wl
->mutex
);
3561 /* Switch the band (if necessary). This might change the active core. */
3562 err
= b43_switch_band(wl
, conf
->channel
);
3564 goto out_unlock_mutex
;
3565 dev
= wl
->current_dev
;
3568 b43_mac_suspend(dev
);
3570 if (changed
& IEEE80211_CONF_CHANGE_RETRY_LIMITS
)
3571 b43_set_retry_limits(dev
, conf
->short_frame_max_tx_count
,
3572 conf
->long_frame_max_tx_count
);
3573 changed
&= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS
;
3575 goto out_mac_enable
;
3577 /* Switch to the requested channel.
3578 * The firmware takes care of races with the TX handler. */
3579 if (conf
->channel
->hw_value
!= phy
->channel
)
3580 b43_switch_channel(dev
, conf
->channel
->hw_value
);
3582 dev
->wl
->radiotap_enabled
= !!(conf
->flags
& IEEE80211_CONF_MONITOR
);
3584 /* Adjust the desired TX power level. */
3585 if (conf
->power_level
!= 0) {
3586 if (conf
->power_level
!= phy
->desired_txpower
) {
3587 phy
->desired_txpower
= conf
->power_level
;
3588 b43_phy_txpower_check(dev
, B43_TXPWR_IGNORE_TIME
|
3589 B43_TXPWR_IGNORE_TSSI
);
3593 /* Antennas for RX and management frame TX. */
3594 antenna
= B43_ANTENNA_DEFAULT
;
3595 b43_mgmtframe_txantenna(dev
, antenna
);
3596 antenna
= B43_ANTENNA_DEFAULT
;
3597 if (phy
->ops
->set_rx_antenna
)
3598 phy
->ops
->set_rx_antenna(dev
, antenna
);
3600 if (wl
->radio_enabled
!= phy
->radio_on
) {
3601 if (wl
->radio_enabled
) {
3602 b43_software_rfkill(dev
, false);
3603 b43info(dev
->wl
, "Radio turned on by software\n");
3604 if (!dev
->radio_hw_enable
) {
3605 b43info(dev
->wl
, "The hardware RF-kill button "
3606 "still turns the radio physically off. "
3607 "Press the button to turn it on.\n");
3610 b43_software_rfkill(dev
, true);
3611 b43info(dev
->wl
, "Radio turned off by software\n");
3616 b43_mac_enable(dev
);
3618 mutex_unlock(&wl
->mutex
);
3623 static void b43_update_basic_rates(struct b43_wldev
*dev
, u32 brates
)
3625 struct ieee80211_supported_band
*sband
=
3626 dev
->wl
->hw
->wiphy
->bands
[b43_current_band(dev
->wl
)];
3627 struct ieee80211_rate
*rate
;
3629 u16 basic
, direct
, offset
, basic_offset
, rateptr
;
3631 for (i
= 0; i
< sband
->n_bitrates
; i
++) {
3632 rate
= &sband
->bitrates
[i
];
3634 if (b43_is_cck_rate(rate
->hw_value
)) {
3635 direct
= B43_SHM_SH_CCKDIRECT
;
3636 basic
= B43_SHM_SH_CCKBASIC
;
3637 offset
= b43_plcp_get_ratecode_cck(rate
->hw_value
);
3640 direct
= B43_SHM_SH_OFDMDIRECT
;
3641 basic
= B43_SHM_SH_OFDMBASIC
;
3642 offset
= b43_plcp_get_ratecode_ofdm(rate
->hw_value
);
3646 rate
= ieee80211_get_response_rate(sband
, brates
, rate
->bitrate
);
3648 if (b43_is_cck_rate(rate
->hw_value
)) {
3649 basic_offset
= b43_plcp_get_ratecode_cck(rate
->hw_value
);
3650 basic_offset
&= 0xF;
3652 basic_offset
= b43_plcp_get_ratecode_ofdm(rate
->hw_value
);
3653 basic_offset
&= 0xF;
3657 * Get the pointer that we need to point to
3658 * from the direct map
3660 rateptr
= b43_shm_read16(dev
, B43_SHM_SHARED
,
3661 direct
+ 2 * basic_offset
);
3662 /* and write it to the basic map */
3663 b43_shm_write16(dev
, B43_SHM_SHARED
, basic
+ 2 * offset
,
3668 static void b43_op_bss_info_changed(struct ieee80211_hw
*hw
,
3669 struct ieee80211_vif
*vif
,
3670 struct ieee80211_bss_conf
*conf
,
3673 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3674 struct b43_wldev
*dev
;
3676 mutex_lock(&wl
->mutex
);
3678 dev
= wl
->current_dev
;
3679 if (!dev
|| b43_status(dev
) < B43_STAT_STARTED
)
3680 goto out_unlock_mutex
;
3682 B43_WARN_ON(wl
->vif
!= vif
);
3684 if (changed
& BSS_CHANGED_BSSID
) {
3686 memcpy(wl
->bssid
, conf
->bssid
, ETH_ALEN
);
3688 memset(wl
->bssid
, 0, ETH_ALEN
);
3691 if (b43_status(dev
) >= B43_STAT_INITIALIZED
) {
3692 if (changed
& BSS_CHANGED_BEACON
&&
3693 (b43_is_mode(wl
, NL80211_IFTYPE_AP
) ||
3694 b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
) ||
3695 b43_is_mode(wl
, NL80211_IFTYPE_ADHOC
)))
3696 b43_update_templates(wl
);
3698 if (changed
& BSS_CHANGED_BSSID
)
3699 b43_write_mac_bssid_templates(dev
);
3702 b43_mac_suspend(dev
);
3704 /* Update templates for AP/mesh mode. */
3705 if (changed
& BSS_CHANGED_BEACON_INT
&&
3706 (b43_is_mode(wl
, NL80211_IFTYPE_AP
) ||
3707 b43_is_mode(wl
, NL80211_IFTYPE_MESH_POINT
) ||
3708 b43_is_mode(wl
, NL80211_IFTYPE_ADHOC
)))
3709 b43_set_beacon_int(dev
, conf
->beacon_int
);
3711 if (changed
& BSS_CHANGED_BASIC_RATES
)
3712 b43_update_basic_rates(dev
, conf
->basic_rates
);
3714 if (changed
& BSS_CHANGED_ERP_SLOT
) {
3715 if (conf
->use_short_slot
)
3716 b43_short_slot_timing_enable(dev
);
3718 b43_short_slot_timing_disable(dev
);
3721 b43_mac_enable(dev
);
3723 mutex_unlock(&wl
->mutex
);
3726 static int b43_op_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3727 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
3728 struct ieee80211_key_conf
*key
)
3730 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3731 struct b43_wldev
*dev
;
3735 static const u8 bcast_addr
[ETH_ALEN
] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3737 if (modparam_nohwcrypt
)
3738 return -ENOSPC
; /* User disabled HW-crypto */
3740 mutex_lock(&wl
->mutex
);
3742 dev
= wl
->current_dev
;
3744 if (!dev
|| b43_status(dev
) < B43_STAT_INITIALIZED
)
3747 if (dev
->fw
.pcm_request_failed
|| !dev
->hwcrypto_enabled
) {
3748 /* We don't have firmware for the crypto engine.
3749 * Must use software-crypto. */
3757 if (key
->keylen
== WLAN_KEY_LEN_WEP40
)
3758 algorithm
= B43_SEC_ALGO_WEP40
;
3760 algorithm
= B43_SEC_ALGO_WEP104
;
3763 algorithm
= B43_SEC_ALGO_TKIP
;
3766 algorithm
= B43_SEC_ALGO_AES
;
3772 index
= (u8
) (key
->keyidx
);
3778 if (algorithm
== B43_SEC_ALGO_TKIP
&&
3779 (!(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
) ||
3780 !modparam_hwtkip
)) {
3781 /* We support only pairwise key */
3786 if (key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
) {
3787 if (WARN_ON(!sta
)) {
3791 /* Pairwise key with an assigned MAC address. */
3792 err
= b43_key_write(dev
, -1, algorithm
,
3793 key
->key
, key
->keylen
,
3797 err
= b43_key_write(dev
, index
, algorithm
,
3798 key
->key
, key
->keylen
, NULL
, key
);
3803 if (algorithm
== B43_SEC_ALGO_WEP40
||
3804 algorithm
== B43_SEC_ALGO_WEP104
) {
3805 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_USEDEFKEYS
);
3808 b43_hf_read(dev
) & ~B43_HF_USEDEFKEYS
);
3810 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
3811 if (algorithm
== B43_SEC_ALGO_TKIP
)
3812 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_MMIC
;
3815 err
= b43_key_clear(dev
, key
->hw_key_idx
);
3826 b43dbg(wl
, "%s hardware based encryption for keyidx: %d, "
3828 cmd
== SET_KEY
? "Using" : "Disabling", key
->keyidx
,
3829 sta
? sta
->addr
: bcast_addr
);
3830 b43_dump_keymemory(dev
);
3832 mutex_unlock(&wl
->mutex
);
3837 static void b43_op_configure_filter(struct ieee80211_hw
*hw
,
3838 unsigned int changed
, unsigned int *fflags
,
3841 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3842 struct b43_wldev
*dev
;
3844 mutex_lock(&wl
->mutex
);
3845 dev
= wl
->current_dev
;
3851 *fflags
&= FIF_PROMISC_IN_BSS
|
3857 FIF_BCN_PRBRESP_PROMISC
;
3859 changed
&= FIF_PROMISC_IN_BSS
|
3865 FIF_BCN_PRBRESP_PROMISC
;
3867 wl
->filter_flags
= *fflags
;
3869 if (changed
&& b43_status(dev
) >= B43_STAT_INITIALIZED
)
3870 b43_adjust_opmode(dev
);
3873 mutex_unlock(&wl
->mutex
);
3876 /* Locking: wl->mutex
3877 * Returns the current dev. This might be different from the passed in dev,
3878 * because the core might be gone away while we unlocked the mutex. */
3879 static struct b43_wldev
* b43_wireless_core_stop(struct b43_wldev
*dev
)
3881 struct b43_wl
*wl
= dev
->wl
;
3882 struct b43_wldev
*orig_dev
;
3886 if (!dev
|| b43_status(dev
) < B43_STAT_STARTED
)
3889 /* Cancel work. Unlock to avoid deadlocks. */
3890 mutex_unlock(&wl
->mutex
);
3891 cancel_delayed_work_sync(&dev
->periodic_work
);
3892 cancel_work_sync(&wl
->tx_work
);
3893 mutex_lock(&wl
->mutex
);
3894 dev
= wl
->current_dev
;
3895 if (!dev
|| b43_status(dev
) < B43_STAT_STARTED
) {
3896 /* Whoops, aliens ate up the device while we were unlocked. */
3900 /* Disable interrupts on the device. */
3901 b43_set_status(dev
, B43_STAT_INITIALIZED
);
3902 if (dev
->dev
->bus
->bustype
== SSB_BUSTYPE_SDIO
) {
3903 /* wl->mutex is locked. That is enough. */
3904 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, 0);
3905 b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
); /* Flush */
3907 spin_lock_irq(&wl
->hardirq_lock
);
3908 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, 0);
3909 b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
); /* Flush */
3910 spin_unlock_irq(&wl
->hardirq_lock
);
3912 /* Synchronize and free the interrupt handlers. Unlock to avoid deadlocks. */
3914 mutex_unlock(&wl
->mutex
);
3915 if (dev
->dev
->bus
->bustype
== SSB_BUSTYPE_SDIO
) {
3916 b43_sdio_free_irq(dev
);
3918 synchronize_irq(dev
->dev
->irq
);
3919 free_irq(dev
->dev
->irq
, dev
);
3921 mutex_lock(&wl
->mutex
);
3922 dev
= wl
->current_dev
;
3925 if (dev
!= orig_dev
) {
3926 if (b43_status(dev
) >= B43_STAT_STARTED
)
3930 mask
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
3931 B43_WARN_ON(mask
!= 0xFFFFFFFF && mask
);
3933 /* Drain the TX queue */
3934 while (skb_queue_len(&wl
->tx_queue
))
3935 dev_kfree_skb(skb_dequeue(&wl
->tx_queue
));
3937 b43_mac_suspend(dev
);
3939 b43dbg(wl
, "Wireless interface stopped\n");
3944 /* Locking: wl->mutex */
3945 static int b43_wireless_core_start(struct b43_wldev
*dev
)
3949 B43_WARN_ON(b43_status(dev
) != B43_STAT_INITIALIZED
);
3951 drain_txstatus_queue(dev
);
3952 if (dev
->dev
->bus
->bustype
== SSB_BUSTYPE_SDIO
) {
3953 err
= b43_sdio_request_irq(dev
, b43_sdio_interrupt_handler
);
3955 b43err(dev
->wl
, "Cannot request SDIO IRQ\n");
3959 err
= request_threaded_irq(dev
->dev
->irq
, b43_interrupt_handler
,
3960 b43_interrupt_thread_handler
,
3961 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
3963 b43err(dev
->wl
, "Cannot request IRQ-%d\n", dev
->dev
->irq
);
3968 /* We are ready to run. */
3969 b43_set_status(dev
, B43_STAT_STARTED
);
3971 /* Start data flow (TX/RX). */
3972 b43_mac_enable(dev
);
3973 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, dev
->irq_mask
);
3975 /* Start maintainance work */
3976 b43_periodic_tasks_setup(dev
);
3980 b43dbg(dev
->wl
, "Wireless interface started\n");
3985 /* Get PHY and RADIO versioning numbers */
3986 static int b43_phy_versioning(struct b43_wldev
*dev
)
3988 struct b43_phy
*phy
= &dev
->phy
;
3996 int unsupported
= 0;
3998 /* Get PHY versioning */
3999 tmp
= b43_read16(dev
, B43_MMIO_PHY_VER
);
4000 analog_type
= (tmp
& B43_PHYVER_ANALOG
) >> B43_PHYVER_ANALOG_SHIFT
;
4001 phy_type
= (tmp
& B43_PHYVER_TYPE
) >> B43_PHYVER_TYPE_SHIFT
;
4002 phy_rev
= (tmp
& B43_PHYVER_VERSION
);
4009 if (phy_rev
!= 2 && phy_rev
!= 4 && phy_rev
!= 6
4017 #ifdef CONFIG_B43_NPHY
4023 #ifdef CONFIG_B43_PHY_LP
4024 case B43_PHYTYPE_LP
:
4033 b43err(dev
->wl
, "FOUND UNSUPPORTED PHY "
4034 "(Analog %u, Type %u, Revision %u)\n",
4035 analog_type
, phy_type
, phy_rev
);
4038 b43dbg(dev
->wl
, "Found PHY: Analog %u, Type %u, Revision %u\n",
4039 analog_type
, phy_type
, phy_rev
);
4041 /* Get RADIO versioning */
4042 if (dev
->dev
->bus
->chip_id
== 0x4317) {
4043 if (dev
->dev
->bus
->chip_rev
== 0)
4045 else if (dev
->dev
->bus
->chip_rev
== 1)
4050 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, B43_RADIOCTL_ID
);
4051 tmp
= b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
4052 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, B43_RADIOCTL_ID
);
4053 tmp
|= (u32
)b43_read16(dev
, B43_MMIO_RADIO_DATA_HIGH
) << 16;
4055 radio_manuf
= (tmp
& 0x00000FFF);
4056 radio_ver
= (tmp
& 0x0FFFF000) >> 12;
4057 radio_rev
= (tmp
& 0xF0000000) >> 28;
4058 if (radio_manuf
!= 0x17F /* Broadcom */)
4062 if (radio_ver
!= 0x2060)
4066 if (radio_manuf
!= 0x17F)
4070 if ((radio_ver
& 0xFFF0) != 0x2050)
4074 if (radio_ver
!= 0x2050)
4078 if (radio_ver
!= 0x2055 && radio_ver
!= 0x2056)
4081 case B43_PHYTYPE_LP
:
4082 if (radio_ver
!= 0x2062 && radio_ver
!= 0x2063)
4089 b43err(dev
->wl
, "FOUND UNSUPPORTED RADIO "
4090 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4091 radio_manuf
, radio_ver
, radio_rev
);
4094 b43dbg(dev
->wl
, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4095 radio_manuf
, radio_ver
, radio_rev
);
4097 phy
->radio_manuf
= radio_manuf
;
4098 phy
->radio_ver
= radio_ver
;
4099 phy
->radio_rev
= radio_rev
;
4101 phy
->analog
= analog_type
;
4102 phy
->type
= phy_type
;
4108 static void setup_struct_phy_for_init(struct b43_wldev
*dev
,
4109 struct b43_phy
*phy
)
4111 phy
->hardware_power_control
= !!modparam_hwpctl
;
4112 phy
->next_txpwr_check_time
= jiffies
;
4113 /* PHY TX errors counter. */
4114 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
4117 phy
->phy_locked
= 0;
4118 phy
->radio_locked
= 0;
4122 static void setup_struct_wldev_for_init(struct b43_wldev
*dev
)
4126 /* Assume the radio is enabled. If it's not enabled, the state will
4127 * immediately get fixed on the first periodic work run. */
4128 dev
->radio_hw_enable
= 1;
4131 memset(&dev
->stats
, 0, sizeof(dev
->stats
));
4133 setup_struct_phy_for_init(dev
, &dev
->phy
);
4135 /* IRQ related flags */
4136 dev
->irq_reason
= 0;
4137 memset(dev
->dma_reason
, 0, sizeof(dev
->dma_reason
));
4138 dev
->irq_mask
= B43_IRQ_MASKTEMPLATE
;
4139 if (b43_modparam_verbose
< B43_VERBOSITY_DEBUG
)
4140 dev
->irq_mask
&= ~B43_IRQ_PHY_TXERR
;
4142 dev
->mac_suspended
= 1;
4144 /* Noise calculation context */
4145 memset(&dev
->noisecalc
, 0, sizeof(dev
->noisecalc
));
4148 static void b43_bluetooth_coext_enable(struct b43_wldev
*dev
)
4150 struct ssb_sprom
*sprom
= &dev
->dev
->bus
->sprom
;
4153 if (!modparam_btcoex
)
4155 if (!(sprom
->boardflags_lo
& B43_BFL_BTCOEXIST
))
4157 if (dev
->phy
.type
!= B43_PHYTYPE_B
&& !dev
->phy
.gmode
)
4160 hf
= b43_hf_read(dev
);
4161 if (sprom
->boardflags_lo
& B43_BFL_BTCMOD
)
4162 hf
|= B43_HF_BTCOEXALT
;
4164 hf
|= B43_HF_BTCOEX
;
4165 b43_hf_write(dev
, hf
);
4168 static void b43_bluetooth_coext_disable(struct b43_wldev
*dev
)
4170 if (!modparam_btcoex
)
4175 static void b43_imcfglo_timeouts_workaround(struct b43_wldev
*dev
)
4177 #ifdef CONFIG_SSB_DRIVER_PCICORE
4178 struct ssb_bus
*bus
= dev
->dev
->bus
;
4181 if (bus
->pcicore
.dev
&&
4182 bus
->pcicore
.dev
->id
.coreid
== SSB_DEV_PCI
&&
4183 bus
->pcicore
.dev
->id
.revision
<= 5) {
4184 /* IMCFGLO timeouts workaround. */
4185 tmp
= ssb_read32(dev
->dev
, SSB_IMCFGLO
);
4186 switch (bus
->bustype
) {
4187 case SSB_BUSTYPE_PCI
:
4188 case SSB_BUSTYPE_PCMCIA
:
4189 tmp
&= ~SSB_IMCFGLO_REQTO
;
4190 tmp
&= ~SSB_IMCFGLO_SERTO
;
4193 case SSB_BUSTYPE_SSB
:
4194 tmp
&= ~SSB_IMCFGLO_REQTO
;
4195 tmp
&= ~SSB_IMCFGLO_SERTO
;
4201 ssb_write32(dev
->dev
, SSB_IMCFGLO
, tmp
);
4203 #endif /* CONFIG_SSB_DRIVER_PCICORE */
4206 static void b43_set_synth_pu_delay(struct b43_wldev
*dev
, bool idle
)
4210 /* The time value is in microseconds. */
4211 if (dev
->phy
.type
== B43_PHYTYPE_A
)
4215 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_ADHOC
) || idle
)
4217 if ((dev
->phy
.radio_ver
== 0x2050) && (dev
->phy
.radio_rev
== 8))
4218 pu_delay
= max(pu_delay
, (u16
)2400);
4220 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_SPUWKUP
, pu_delay
);
4223 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4224 static void b43_set_pretbtt(struct b43_wldev
*dev
)
4228 /* The time value is in microseconds. */
4229 if (b43_is_mode(dev
->wl
, NL80211_IFTYPE_ADHOC
)) {
4232 if (dev
->phy
.type
== B43_PHYTYPE_A
)
4237 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRETBTT
, pretbtt
);
4238 b43_write16(dev
, B43_MMIO_TSF_CFP_PRETBTT
, pretbtt
);
4241 /* Shutdown a wireless core */
4242 /* Locking: wl->mutex */
4243 static void b43_wireless_core_exit(struct b43_wldev
*dev
)
4247 B43_WARN_ON(dev
&& b43_status(dev
) > B43_STAT_INITIALIZED
);
4248 if (!dev
|| b43_status(dev
) != B43_STAT_INITIALIZED
)
4250 b43_set_status(dev
, B43_STAT_UNINIT
);
4252 /* Stop the microcode PSM. */
4253 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
4254 macctl
&= ~B43_MACCTL_PSM_RUN
;
4255 macctl
|= B43_MACCTL_PSM_JMP0
;
4256 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
4261 dev
->phy
.ops
->switch_analog(dev
, 0);
4262 if (dev
->wl
->current_beacon
) {
4263 dev_kfree_skb_any(dev
->wl
->current_beacon
);
4264 dev
->wl
->current_beacon
= NULL
;
4267 ssb_device_disable(dev
->dev
, 0);
4268 ssb_bus_may_powerdown(dev
->dev
->bus
);
4271 /* Initialize a wireless core */
4272 static int b43_wireless_core_init(struct b43_wldev
*dev
)
4274 struct ssb_bus
*bus
= dev
->dev
->bus
;
4275 struct ssb_sprom
*sprom
= &bus
->sprom
;
4276 struct b43_phy
*phy
= &dev
->phy
;
4281 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
4283 err
= ssb_bus_powerup(bus
, 0);
4286 if (!ssb_device_is_enabled(dev
->dev
)) {
4287 tmp
= phy
->gmode
? B43_TMSLOW_GMODE
: 0;
4288 b43_wireless_core_reset(dev
, tmp
);
4291 /* Reset all data structures. */
4292 setup_struct_wldev_for_init(dev
);
4293 phy
->ops
->prepare_structs(dev
);
4295 /* Enable IRQ routing to this device. */
4296 ssb_pcicore_dev_irqvecs_enable(&bus
->pcicore
, dev
->dev
);
4298 b43_imcfglo_timeouts_workaround(dev
);
4299 b43_bluetooth_coext_disable(dev
);
4300 if (phy
->ops
->prepare_hardware
) {
4301 err
= phy
->ops
->prepare_hardware(dev
);
4305 err
= b43_chip_init(dev
);
4308 b43_shm_write16(dev
, B43_SHM_SHARED
,
4309 B43_SHM_SH_WLCOREREV
, dev
->dev
->id
.revision
);
4310 hf
= b43_hf_read(dev
);
4311 if (phy
->type
== B43_PHYTYPE_G
) {
4315 if (sprom
->boardflags_lo
& B43_BFL_PACTRL
)
4316 hf
|= B43_HF_OFDMPABOOST
;
4318 if (phy
->radio_ver
== 0x2050) {
4319 if (phy
->radio_rev
== 6)
4320 hf
|= B43_HF_4318TSSI
;
4321 if (phy
->radio_rev
< 6)
4322 hf
|= B43_HF_VCORECALC
;
4324 if (sprom
->boardflags_lo
& B43_BFL_XTAL_NOSLOW
)
4325 hf
|= B43_HF_DSCRQ
; /* Disable slowclock requests from ucode. */
4326 #ifdef CONFIG_SSB_DRIVER_PCICORE
4327 if ((bus
->bustype
== SSB_BUSTYPE_PCI
) &&
4328 (bus
->pcicore
.dev
->id
.revision
<= 10))
4329 hf
|= B43_HF_PCISCW
; /* PCI slow clock workaround. */
4331 hf
&= ~B43_HF_SKCFPUP
;
4332 b43_hf_write(dev
, hf
);
4334 b43_set_retry_limits(dev
, B43_DEFAULT_SHORT_RETRY_LIMIT
,
4335 B43_DEFAULT_LONG_RETRY_LIMIT
);
4336 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_SFFBLIM
, 3);
4337 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_LFFBLIM
, 2);
4339 /* Disable sending probe responses from firmware.
4340 * Setting the MaxTime to one usec will always trigger
4341 * a timeout, so we never send any probe resp.
4342 * A timeout of zero is infinite. */
4343 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRMAXTIME
, 1);
4345 b43_rate_memory_init(dev
);
4346 b43_set_phytxctl_defaults(dev
);
4348 /* Minimum Contention Window */
4349 if (phy
->type
== B43_PHYTYPE_B
) {
4350 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0x1F);
4352 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0xF);
4354 /* Maximum Contention Window */
4355 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MAXCONT
, 0x3FF);
4357 if ((dev
->dev
->bus
->bustype
== SSB_BUSTYPE_PCMCIA
) ||
4358 (dev
->dev
->bus
->bustype
== SSB_BUSTYPE_SDIO
) ||
4360 dev
->__using_pio_transfers
= 1;
4361 err
= b43_pio_init(dev
);
4363 dev
->__using_pio_transfers
= 0;
4364 err
= b43_dma_init(dev
);
4369 b43_set_synth_pu_delay(dev
, 1);
4370 b43_bluetooth_coext_enable(dev
);
4372 ssb_bus_powerup(bus
, !(sprom
->boardflags_lo
& B43_BFL_XTAL_NOSLOW
));
4373 b43_upload_card_macaddress(dev
);
4374 b43_security_init(dev
);
4376 ieee80211_wake_queues(dev
->wl
->hw
);
4378 ieee80211_wake_queues(dev
->wl
->hw
);
4380 b43_set_status(dev
, B43_STAT_INITIALIZED
);
4388 ssb_bus_may_powerdown(bus
);
4389 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
4393 static int b43_op_add_interface(struct ieee80211_hw
*hw
,
4394 struct ieee80211_vif
*vif
)
4396 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4397 struct b43_wldev
*dev
;
4398 int err
= -EOPNOTSUPP
;
4400 /* TODO: allow WDS/AP devices to coexist */
4402 if (vif
->type
!= NL80211_IFTYPE_AP
&&
4403 vif
->type
!= NL80211_IFTYPE_MESH_POINT
&&
4404 vif
->type
!= NL80211_IFTYPE_STATION
&&
4405 vif
->type
!= NL80211_IFTYPE_WDS
&&
4406 vif
->type
!= NL80211_IFTYPE_ADHOC
)
4409 mutex_lock(&wl
->mutex
);
4411 goto out_mutex_unlock
;
4413 b43dbg(wl
, "Adding Interface type %d\n", vif
->type
);
4415 dev
= wl
->current_dev
;
4418 wl
->if_type
= vif
->type
;
4419 memcpy(wl
->mac_addr
, vif
->addr
, ETH_ALEN
);
4421 b43_adjust_opmode(dev
);
4422 b43_set_pretbtt(dev
);
4423 b43_set_synth_pu_delay(dev
, 0);
4424 b43_upload_card_macaddress(dev
);
4428 mutex_unlock(&wl
->mutex
);
4433 static void b43_op_remove_interface(struct ieee80211_hw
*hw
,
4434 struct ieee80211_vif
*vif
)
4436 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4437 struct b43_wldev
*dev
= wl
->current_dev
;
4439 b43dbg(wl
, "Removing Interface type %d\n", vif
->type
);
4441 mutex_lock(&wl
->mutex
);
4443 B43_WARN_ON(!wl
->operating
);
4444 B43_WARN_ON(wl
->vif
!= vif
);
4449 b43_adjust_opmode(dev
);
4450 memset(wl
->mac_addr
, 0, ETH_ALEN
);
4451 b43_upload_card_macaddress(dev
);
4453 mutex_unlock(&wl
->mutex
);
4456 static int b43_op_start(struct ieee80211_hw
*hw
)
4458 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4459 struct b43_wldev
*dev
= wl
->current_dev
;
4463 /* Kill all old instance specific information to make sure
4464 * the card won't use it in the short timeframe between start
4465 * and mac80211 reconfiguring it. */
4466 memset(wl
->bssid
, 0, ETH_ALEN
);
4467 memset(wl
->mac_addr
, 0, ETH_ALEN
);
4468 wl
->filter_flags
= 0;
4469 wl
->radiotap_enabled
= 0;
4471 wl
->beacon0_uploaded
= 0;
4472 wl
->beacon1_uploaded
= 0;
4473 wl
->beacon_templates_virgin
= 1;
4474 wl
->radio_enabled
= 1;
4476 mutex_lock(&wl
->mutex
);
4478 if (b43_status(dev
) < B43_STAT_INITIALIZED
) {
4479 err
= b43_wireless_core_init(dev
);
4481 goto out_mutex_unlock
;
4485 if (b43_status(dev
) < B43_STAT_STARTED
) {
4486 err
= b43_wireless_core_start(dev
);
4489 b43_wireless_core_exit(dev
);
4490 goto out_mutex_unlock
;
4494 /* XXX: only do if device doesn't support rfkill irq */
4495 wiphy_rfkill_start_polling(hw
->wiphy
);
4498 mutex_unlock(&wl
->mutex
);
4503 static void b43_op_stop(struct ieee80211_hw
*hw
)
4505 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4506 struct b43_wldev
*dev
= wl
->current_dev
;
4508 cancel_work_sync(&(wl
->beacon_update_trigger
));
4510 mutex_lock(&wl
->mutex
);
4511 if (b43_status(dev
) >= B43_STAT_STARTED
) {
4512 dev
= b43_wireless_core_stop(dev
);
4516 b43_wireless_core_exit(dev
);
4517 wl
->radio_enabled
= 0;
4520 mutex_unlock(&wl
->mutex
);
4522 cancel_work_sync(&(wl
->txpower_adjust_work
));
4525 static int b43_op_beacon_set_tim(struct ieee80211_hw
*hw
,
4526 struct ieee80211_sta
*sta
, bool set
)
4528 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4530 /* FIXME: add locking */
4531 b43_update_templates(wl
);
4536 static void b43_op_sta_notify(struct ieee80211_hw
*hw
,
4537 struct ieee80211_vif
*vif
,
4538 enum sta_notify_cmd notify_cmd
,
4539 struct ieee80211_sta
*sta
)
4541 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4543 B43_WARN_ON(!vif
|| wl
->vif
!= vif
);
4546 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw
*hw
)
4548 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4549 struct b43_wldev
*dev
;
4551 mutex_lock(&wl
->mutex
);
4552 dev
= wl
->current_dev
;
4553 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
)) {
4554 /* Disable CFP update during scan on other channels. */
4555 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_SKCFPUP
);
4557 mutex_unlock(&wl
->mutex
);
4560 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw
*hw
)
4562 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4563 struct b43_wldev
*dev
;
4565 mutex_lock(&wl
->mutex
);
4566 dev
= wl
->current_dev
;
4567 if (dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
)) {
4568 /* Re-enable CFP update. */
4569 b43_hf_write(dev
, b43_hf_read(dev
) & ~B43_HF_SKCFPUP
);
4571 mutex_unlock(&wl
->mutex
);
4574 static const struct ieee80211_ops b43_hw_ops
= {
4576 .conf_tx
= b43_op_conf_tx
,
4577 .add_interface
= b43_op_add_interface
,
4578 .remove_interface
= b43_op_remove_interface
,
4579 .config
= b43_op_config
,
4580 .bss_info_changed
= b43_op_bss_info_changed
,
4581 .configure_filter
= b43_op_configure_filter
,
4582 .set_key
= b43_op_set_key
,
4583 .update_tkip_key
= b43_op_update_tkip_key
,
4584 .get_stats
= b43_op_get_stats
,
4585 .get_tx_stats
= b43_op_get_tx_stats
,
4586 .get_tsf
= b43_op_get_tsf
,
4587 .set_tsf
= b43_op_set_tsf
,
4588 .start
= b43_op_start
,
4589 .stop
= b43_op_stop
,
4590 .set_tim
= b43_op_beacon_set_tim
,
4591 .sta_notify
= b43_op_sta_notify
,
4592 .sw_scan_start
= b43_op_sw_scan_start_notifier
,
4593 .sw_scan_complete
= b43_op_sw_scan_complete_notifier
,
4594 .rfkill_poll
= b43_rfkill_poll
,
4597 /* Hard-reset the chip. Do not call this directly.
4598 * Use b43_controller_restart()
4600 static void b43_chip_reset(struct work_struct
*work
)
4602 struct b43_wldev
*dev
=
4603 container_of(work
, struct b43_wldev
, restart_work
);
4604 struct b43_wl
*wl
= dev
->wl
;
4608 mutex_lock(&wl
->mutex
);
4610 prev_status
= b43_status(dev
);
4611 /* Bring the device down... */
4612 if (prev_status
>= B43_STAT_STARTED
) {
4613 dev
= b43_wireless_core_stop(dev
);
4619 if (prev_status
>= B43_STAT_INITIALIZED
)
4620 b43_wireless_core_exit(dev
);
4622 /* ...and up again. */
4623 if (prev_status
>= B43_STAT_INITIALIZED
) {
4624 err
= b43_wireless_core_init(dev
);
4628 if (prev_status
>= B43_STAT_STARTED
) {
4629 err
= b43_wireless_core_start(dev
);
4631 b43_wireless_core_exit(dev
);
4637 wl
->current_dev
= NULL
; /* Failed to init the dev. */
4638 mutex_unlock(&wl
->mutex
);
4640 b43err(wl
, "Controller restart FAILED\n");
4642 b43info(wl
, "Controller restarted\n");
4645 static int b43_setup_bands(struct b43_wldev
*dev
,
4646 bool have_2ghz_phy
, bool have_5ghz_phy
)
4648 struct ieee80211_hw
*hw
= dev
->wl
->hw
;
4651 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = &b43_band_2GHz
;
4652 if (dev
->phy
.type
== B43_PHYTYPE_N
) {
4654 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = &b43_band_5GHz_nphy
;
4657 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = &b43_band_5GHz_aphy
;
4660 dev
->phy
.supports_2ghz
= have_2ghz_phy
;
4661 dev
->phy
.supports_5ghz
= have_5ghz_phy
;
4666 static void b43_wireless_core_detach(struct b43_wldev
*dev
)
4668 /* We release firmware that late to not be required to re-request
4669 * is all the time when we reinit the core. */
4670 b43_release_firmware(dev
);
4674 static int b43_wireless_core_attach(struct b43_wldev
*dev
)
4676 struct b43_wl
*wl
= dev
->wl
;
4677 struct ssb_bus
*bus
= dev
->dev
->bus
;
4678 struct pci_dev
*pdev
= (bus
->bustype
== SSB_BUSTYPE_PCI
) ? bus
->host_pci
: NULL
;
4680 bool have_2ghz_phy
= 0, have_5ghz_phy
= 0;
4683 /* Do NOT do any device initialization here.
4684 * Do it in wireless_core_init() instead.
4685 * This function is for gathering basic information about the HW, only.
4686 * Also some structs may be set up here. But most likely you want to have
4687 * that in core_init(), too.
4690 err
= ssb_bus_powerup(bus
, 0);
4692 b43err(wl
, "Bus powerup failed\n");
4695 /* Get the PHY type. */
4696 if (dev
->dev
->id
.revision
>= 5) {
4699 tmshigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
4700 have_2ghz_phy
= !!(tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
);
4701 have_5ghz_phy
= !!(tmshigh
& B43_TMSHIGH_HAVE_5GHZ_PHY
);
4705 dev
->phy
.gmode
= have_2ghz_phy
;
4706 dev
->phy
.radio_on
= 1;
4707 tmp
= dev
->phy
.gmode
? B43_TMSLOW_GMODE
: 0;
4708 b43_wireless_core_reset(dev
, tmp
);
4710 err
= b43_phy_versioning(dev
);
4713 /* Check if this device supports multiband. */
4715 (pdev
->device
!= 0x4312 &&
4716 pdev
->device
!= 0x4319 && pdev
->device
!= 0x4324)) {
4717 /* No multiband support. */
4720 switch (dev
->phy
.type
) {
4724 case B43_PHYTYPE_LP
: //FIXME not always!
4725 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
4736 if (dev
->phy
.type
== B43_PHYTYPE_A
) {
4738 b43err(wl
, "IEEE 802.11a devices are unsupported\n");
4742 if (1 /* disable A-PHY */) {
4743 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4744 if (dev
->phy
.type
!= B43_PHYTYPE_N
&&
4745 dev
->phy
.type
!= B43_PHYTYPE_LP
) {
4751 err
= b43_phy_allocate(dev
);
4755 dev
->phy
.gmode
= have_2ghz_phy
;
4756 tmp
= dev
->phy
.gmode
? B43_TMSLOW_GMODE
: 0;
4757 b43_wireless_core_reset(dev
, tmp
);
4759 err
= b43_validate_chipaccess(dev
);
4762 err
= b43_setup_bands(dev
, have_2ghz_phy
, have_5ghz_phy
);
4766 /* Now set some default "current_dev" */
4767 if (!wl
->current_dev
)
4768 wl
->current_dev
= dev
;
4769 INIT_WORK(&dev
->restart_work
, b43_chip_reset
);
4771 dev
->phy
.ops
->switch_analog(dev
, 0);
4772 ssb_device_disable(dev
->dev
, 0);
4773 ssb_bus_may_powerdown(bus
);
4781 ssb_bus_may_powerdown(bus
);
4785 static void b43_one_core_detach(struct ssb_device
*dev
)
4787 struct b43_wldev
*wldev
;
4790 /* Do not cancel ieee80211-workqueue based work here.
4791 * See comment in b43_remove(). */
4793 wldev
= ssb_get_drvdata(dev
);
4795 b43_debugfs_remove_device(wldev
);
4796 b43_wireless_core_detach(wldev
);
4797 list_del(&wldev
->list
);
4799 ssb_set_drvdata(dev
, NULL
);
4803 static int b43_one_core_attach(struct ssb_device
*dev
, struct b43_wl
*wl
)
4805 struct b43_wldev
*wldev
;
4806 struct pci_dev
*pdev
;
4809 if (!list_empty(&wl
->devlist
)) {
4810 /* We are not the first core on this chip. */
4811 pdev
= (dev
->bus
->bustype
== SSB_BUSTYPE_PCI
) ? dev
->bus
->host_pci
: NULL
;
4812 /* Only special chips support more than one wireless
4813 * core, although some of the other chips have more than
4814 * one wireless core as well. Check for this and
4818 ((pdev
->device
!= 0x4321) &&
4819 (pdev
->device
!= 0x4313) && (pdev
->device
!= 0x431A))) {
4820 b43dbg(wl
, "Ignoring unconnected 802.11 core\n");
4825 wldev
= kzalloc(sizeof(*wldev
), GFP_KERNEL
);
4831 b43_set_status(wldev
, B43_STAT_UNINIT
);
4832 wldev
->bad_frames_preempt
= modparam_bad_frames_preempt
;
4833 INIT_LIST_HEAD(&wldev
->list
);
4835 err
= b43_wireless_core_attach(wldev
);
4837 goto err_kfree_wldev
;
4839 list_add(&wldev
->list
, &wl
->devlist
);
4841 ssb_set_drvdata(dev
, wldev
);
4842 b43_debugfs_add_device(wldev
);
4852 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4853 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4854 (pdev->device == _device) && \
4855 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4856 (pdev->subsystem_device == _subdevice) )
4858 static void b43_sprom_fixup(struct ssb_bus
*bus
)
4860 struct pci_dev
*pdev
;
4862 /* boardflags workarounds */
4863 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_DELL
&&
4864 bus
->chip_id
== 0x4301 && bus
->boardinfo
.rev
== 0x74)
4865 bus
->sprom
.boardflags_lo
|= B43_BFL_BTCOEXIST
;
4866 if (bus
->boardinfo
.vendor
== PCI_VENDOR_ID_APPLE
&&
4867 bus
->boardinfo
.type
== 0x4E && bus
->boardinfo
.rev
> 0x40)
4868 bus
->sprom
.boardflags_lo
|= B43_BFL_PACTRL
;
4869 if (bus
->bustype
== SSB_BUSTYPE_PCI
) {
4870 pdev
= bus
->host_pci
;
4871 if (IS_PDEV(pdev
, BROADCOM
, 0x4318, ASUSTEK
, 0x100F) ||
4872 IS_PDEV(pdev
, BROADCOM
, 0x4320, DELL
, 0x0003) ||
4873 IS_PDEV(pdev
, BROADCOM
, 0x4320, HP
, 0x12f8) ||
4874 IS_PDEV(pdev
, BROADCOM
, 0x4320, LINKSYS
, 0x0015) ||
4875 IS_PDEV(pdev
, BROADCOM
, 0x4320, LINKSYS
, 0x0014) ||
4876 IS_PDEV(pdev
, BROADCOM
, 0x4320, LINKSYS
, 0x0013) ||
4877 IS_PDEV(pdev
, BROADCOM
, 0x4320, MOTOROLA
, 0x7010))
4878 bus
->sprom
.boardflags_lo
&= ~B43_BFL_BTCOEXIST
;
4882 static void b43_wireless_exit(struct ssb_device
*dev
, struct b43_wl
*wl
)
4884 struct ieee80211_hw
*hw
= wl
->hw
;
4886 ssb_set_devtypedata(dev
, NULL
);
4887 ieee80211_free_hw(hw
);
4890 static int b43_wireless_init(struct ssb_device
*dev
)
4892 struct ssb_sprom
*sprom
= &dev
->bus
->sprom
;
4893 struct ieee80211_hw
*hw
;
4897 b43_sprom_fixup(dev
->bus
);
4899 hw
= ieee80211_alloc_hw(sizeof(*wl
), &b43_hw_ops
);
4901 b43err(NULL
, "Could not allocate ieee80211 device\n");
4904 wl
= hw_to_b43_wl(hw
);
4907 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
4908 IEEE80211_HW_SIGNAL_DBM
|
4909 IEEE80211_HW_NOISE_DBM
;
4911 hw
->wiphy
->interface_modes
=
4912 BIT(NL80211_IFTYPE_AP
) |
4913 BIT(NL80211_IFTYPE_MESH_POINT
) |
4914 BIT(NL80211_IFTYPE_STATION
) |
4915 BIT(NL80211_IFTYPE_WDS
) |
4916 BIT(NL80211_IFTYPE_ADHOC
);
4918 hw
->queues
= modparam_qos
? 4 : 1;
4919 wl
->mac80211_initially_registered_queues
= hw
->queues
;
4921 SET_IEEE80211_DEV(hw
, dev
->dev
);
4922 if (is_valid_ether_addr(sprom
->et1mac
))
4923 SET_IEEE80211_PERM_ADDR(hw
, sprom
->et1mac
);
4925 SET_IEEE80211_PERM_ADDR(hw
, sprom
->il0mac
);
4927 /* Initialize struct b43_wl */
4929 mutex_init(&wl
->mutex
);
4930 spin_lock_init(&wl
->hardirq_lock
);
4931 INIT_LIST_HEAD(&wl
->devlist
);
4932 INIT_WORK(&wl
->beacon_update_trigger
, b43_beacon_update_trigger_work
);
4933 INIT_WORK(&wl
->txpower_adjust_work
, b43_phy_txpower_adjust_work
);
4934 INIT_WORK(&wl
->tx_work
, b43_tx_work
);
4935 skb_queue_head_init(&wl
->tx_queue
);
4937 ssb_set_devtypedata(dev
, wl
);
4938 b43info(wl
, "Broadcom %04X WLAN found (core revision %u)\n",
4939 dev
->bus
->chip_id
, dev
->id
.revision
);
4945 static int b43_probe(struct ssb_device
*dev
, const struct ssb_device_id
*id
)
4951 wl
= ssb_get_devtypedata(dev
);
4953 /* Probing the first core. Must setup common struct b43_wl */
4955 err
= b43_wireless_init(dev
);
4958 wl
= ssb_get_devtypedata(dev
);
4961 err
= b43_one_core_attach(dev
, wl
);
4963 goto err_wireless_exit
;
4966 err
= ieee80211_register_hw(wl
->hw
);
4968 goto err_one_core_detach
;
4969 b43_leds_register(wl
->current_dev
);
4976 err_one_core_detach
:
4977 b43_one_core_detach(dev
);
4980 b43_wireless_exit(dev
, wl
);
4984 static void b43_remove(struct ssb_device
*dev
)
4986 struct b43_wl
*wl
= ssb_get_devtypedata(dev
);
4987 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
4989 /* We must cancel any work here before unregistering from ieee80211,
4990 * as the ieee80211 unreg will destroy the workqueue. */
4991 cancel_work_sync(&wldev
->restart_work
);
4994 if (wl
->current_dev
== wldev
) {
4995 /* Restore the queues count before unregistering, because firmware detect
4996 * might have modified it. Restoring is important, so the networking
4997 * stack can properly free resources. */
4998 wl
->hw
->queues
= wl
->mac80211_initially_registered_queues
;
4999 b43_leds_stop(wldev
);
5000 ieee80211_unregister_hw(wl
->hw
);
5003 b43_one_core_detach(dev
);
5005 if (list_empty(&wl
->devlist
)) {
5007 b43_leds_unregister(wl
);
5008 /* Last core on the chip unregistered.
5009 * We can destroy common struct b43_wl.
5011 b43_wireless_exit(dev
, wl
);
5015 /* Perform a hardware reset. This can be called from any context. */
5016 void b43_controller_restart(struct b43_wldev
*dev
, const char *reason
)
5018 /* Must avoid requeueing, if we are in shutdown. */
5019 if (b43_status(dev
) < B43_STAT_INITIALIZED
)
5021 b43info(dev
->wl
, "Controller RESET (%s) ...\n", reason
);
5022 ieee80211_queue_work(dev
->wl
->hw
, &dev
->restart_work
);
5025 static struct ssb_driver b43_ssb_driver
= {
5026 .name
= KBUILD_MODNAME
,
5027 .id_table
= b43_ssb_tbl
,
5029 .remove
= b43_remove
,
5032 static void b43_print_driverinfo(void)
5034 const char *feat_pci
= "", *feat_pcmcia
= "", *feat_nphy
= "",
5035 *feat_leds
= "", *feat_sdio
= "";
5037 #ifdef CONFIG_B43_PCI_AUTOSELECT
5040 #ifdef CONFIG_B43_PCMCIA
5043 #ifdef CONFIG_B43_NPHY
5046 #ifdef CONFIG_B43_LEDS
5049 #ifdef CONFIG_B43_SDIO
5052 printk(KERN_INFO
"Broadcom 43xx driver loaded "
5053 "[ Features: %s%s%s%s%s, Firmware-ID: "
5054 B43_SUPPORTED_FIRMWARE_ID
" ]\n",
5055 feat_pci
, feat_pcmcia
, feat_nphy
,
5056 feat_leds
, feat_sdio
);
5059 static int __init
b43_init(void)
5064 err
= b43_pcmcia_init();
5067 err
= b43_sdio_init();
5069 goto err_pcmcia_exit
;
5070 err
= ssb_driver_register(&b43_ssb_driver
);
5073 b43_print_driverinfo();
5086 static void __exit
b43_exit(void)
5088 ssb_driver_unregister(&b43_ssb_driver
);
5094 module_init(b43_init
)
5095 module_exit(b43_exit
)