3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
54 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
55 MODULE_AUTHOR("Martin Langer");
56 MODULE_AUTHOR("Stefano Brivio");
57 MODULE_AUTHOR("Michael Buesch");
58 MODULE_LICENSE("GPL");
61 static int modparam_bad_frames_preempt
;
62 module_param_named(bad_frames_preempt
, modparam_bad_frames_preempt
, int, 0444);
63 MODULE_PARM_DESC(bad_frames_preempt
,
64 "enable(1) / disable(0) Bad Frames Preemption");
66 static char modparam_fwpostfix
[16];
67 module_param_string(fwpostfix
, modparam_fwpostfix
, 16, 0444);
68 MODULE_PARM_DESC(fwpostfix
, "Postfix for the .fw files to load.");
70 static int modparam_hwpctl
;
71 module_param_named(hwpctl
, modparam_hwpctl
, int, 0444);
72 MODULE_PARM_DESC(hwpctl
, "Enable hardware-side power control (default off)");
74 static int modparam_nohwcrypt
;
75 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
76 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
78 static const struct ssb_device_id b43_ssb_tbl
[] = {
79 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 5),
80 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 6),
81 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 7),
82 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 9),
83 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 10),
84 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 11),
85 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 13),
89 MODULE_DEVICE_TABLE(ssb
, b43_ssb_tbl
);
91 /* Channel and ratetables are shared for all devices.
92 * They can't be const, because ieee80211 puts some precalculated
93 * data in there. This data is the same for all devices, so we don't
94 * get concurrency issues */
95 #define RATETAB_ENT(_rateid, _flags) \
97 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
102 static struct ieee80211_rate __b43_ratetable
[] = {
103 RATETAB_ENT(B43_CCK_RATE_1MB
, IEEE80211_RATE_CCK
),
104 RATETAB_ENT(B43_CCK_RATE_2MB
, IEEE80211_RATE_CCK_2
),
105 RATETAB_ENT(B43_CCK_RATE_5MB
, IEEE80211_RATE_CCK_2
),
106 RATETAB_ENT(B43_CCK_RATE_11MB
, IEEE80211_RATE_CCK_2
),
107 RATETAB_ENT(B43_OFDM_RATE_6MB
, IEEE80211_RATE_OFDM
),
108 RATETAB_ENT(B43_OFDM_RATE_9MB
, IEEE80211_RATE_OFDM
),
109 RATETAB_ENT(B43_OFDM_RATE_12MB
, IEEE80211_RATE_OFDM
),
110 RATETAB_ENT(B43_OFDM_RATE_18MB
, IEEE80211_RATE_OFDM
),
111 RATETAB_ENT(B43_OFDM_RATE_24MB
, IEEE80211_RATE_OFDM
),
112 RATETAB_ENT(B43_OFDM_RATE_36MB
, IEEE80211_RATE_OFDM
),
113 RATETAB_ENT(B43_OFDM_RATE_48MB
, IEEE80211_RATE_OFDM
),
114 RATETAB_ENT(B43_OFDM_RATE_54MB
, IEEE80211_RATE_OFDM
),
117 #define b43_a_ratetable (__b43_ratetable + 4)
118 #define b43_a_ratetable_size 8
119 #define b43_b_ratetable (__b43_ratetable + 0)
120 #define b43_b_ratetable_size 4
121 #define b43_g_ratetable (__b43_ratetable + 0)
122 #define b43_g_ratetable_size 12
124 #define CHANTAB_ENT(_chanid, _freq) \
129 .flag = IEEE80211_CHAN_W_SCAN | \
130 IEEE80211_CHAN_W_ACTIVE_SCAN | \
131 IEEE80211_CHAN_W_IBSS, \
132 .power_level = 0xFF, \
133 .antenna_max = 0xFF, \
135 static struct ieee80211_channel b43_2ghz_chantable
[] = {
136 CHANTAB_ENT(1, 2412),
137 CHANTAB_ENT(2, 2417),
138 CHANTAB_ENT(3, 2422),
139 CHANTAB_ENT(4, 2427),
140 CHANTAB_ENT(5, 2432),
141 CHANTAB_ENT(6, 2437),
142 CHANTAB_ENT(7, 2442),
143 CHANTAB_ENT(8, 2447),
144 CHANTAB_ENT(9, 2452),
145 CHANTAB_ENT(10, 2457),
146 CHANTAB_ENT(11, 2462),
147 CHANTAB_ENT(12, 2467),
148 CHANTAB_ENT(13, 2472),
149 CHANTAB_ENT(14, 2484),
151 #define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
154 static struct ieee80211_channel b43_5ghz_chantable
[] = {
155 CHANTAB_ENT(36, 5180),
156 CHANTAB_ENT(40, 5200),
157 CHANTAB_ENT(44, 5220),
158 CHANTAB_ENT(48, 5240),
159 CHANTAB_ENT(52, 5260),
160 CHANTAB_ENT(56, 5280),
161 CHANTAB_ENT(60, 5300),
162 CHANTAB_ENT(64, 5320),
163 CHANTAB_ENT(149, 5745),
164 CHANTAB_ENT(153, 5765),
165 CHANTAB_ENT(157, 5785),
166 CHANTAB_ENT(161, 5805),
167 CHANTAB_ENT(165, 5825),
169 #define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
172 static void b43_wireless_core_exit(struct b43_wldev
*dev
);
173 static int b43_wireless_core_init(struct b43_wldev
*dev
);
174 static void b43_wireless_core_stop(struct b43_wldev
*dev
);
175 static int b43_wireless_core_start(struct b43_wldev
*dev
);
177 static int b43_ratelimit(struct b43_wl
*wl
)
179 if (!wl
|| !wl
->current_dev
)
181 if (b43_status(wl
->current_dev
) < B43_STAT_STARTED
)
183 /* We are up and running.
184 * Ratelimit the messages to avoid DoS over the net. */
185 return net_ratelimit();
188 void b43info(struct b43_wl
*wl
, const char *fmt
, ...)
192 if (!b43_ratelimit(wl
))
195 printk(KERN_INFO
"b43-%s: ",
196 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
201 void b43err(struct b43_wl
*wl
, const char *fmt
, ...)
205 if (!b43_ratelimit(wl
))
208 printk(KERN_ERR
"b43-%s ERROR: ",
209 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
214 void b43warn(struct b43_wl
*wl
, const char *fmt
, ...)
218 if (!b43_ratelimit(wl
))
221 printk(KERN_WARNING
"b43-%s warning: ",
222 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
228 void b43dbg(struct b43_wl
*wl
, const char *fmt
, ...)
233 printk(KERN_DEBUG
"b43-%s debug: ",
234 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
240 static void b43_ram_write(struct b43_wldev
*dev
, u16 offset
, u32 val
)
244 B43_WARN_ON(offset
% 4 != 0);
246 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
247 if (macctl
& B43_MACCTL_BE
)
250 b43_write32(dev
, B43_MMIO_RAM_CONTROL
, offset
);
252 b43_write32(dev
, B43_MMIO_RAM_DATA
, val
);
255 static inline void b43_shm_control_word(struct b43_wldev
*dev
,
256 u16 routing
, u16 offset
)
260 /* "offset" is the WORD offset. */
264 b43_write32(dev
, B43_MMIO_SHM_CONTROL
, control
);
267 u32
b43_shm_read32(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
269 struct b43_wl
*wl
= dev
->wl
;
273 spin_lock_irqsave(&wl
->shm_lock
, flags
);
274 if (routing
== B43_SHM_SHARED
) {
275 B43_WARN_ON(offset
& 0x0001);
276 if (offset
& 0x0003) {
277 /* Unaligned access */
278 b43_shm_control_word(dev
, routing
, offset
>> 2);
279 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
281 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
282 ret
|= b43_read16(dev
, B43_MMIO_SHM_DATA
);
288 b43_shm_control_word(dev
, routing
, offset
);
289 ret
= b43_read32(dev
, B43_MMIO_SHM_DATA
);
291 spin_unlock_irqrestore(&wl
->shm_lock
, flags
);
296 u16
b43_shm_read16(struct b43_wldev
* dev
, u16 routing
, u16 offset
)
298 struct b43_wl
*wl
= dev
->wl
;
302 spin_lock_irqsave(&wl
->shm_lock
, flags
);
303 if (routing
== B43_SHM_SHARED
) {
304 B43_WARN_ON(offset
& 0x0001);
305 if (offset
& 0x0003) {
306 /* Unaligned access */
307 b43_shm_control_word(dev
, routing
, offset
>> 2);
308 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
314 b43_shm_control_word(dev
, routing
, offset
);
315 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA
);
317 spin_unlock_irqrestore(&wl
->shm_lock
, flags
);
322 void b43_shm_write32(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u32 value
)
324 struct b43_wl
*wl
= dev
->wl
;
327 spin_lock_irqsave(&wl
->shm_lock
, flags
);
328 if (routing
== B43_SHM_SHARED
) {
329 B43_WARN_ON(offset
& 0x0001);
330 if (offset
& 0x0003) {
331 /* Unaligned access */
332 b43_shm_control_word(dev
, routing
, offset
>> 2);
333 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
,
334 (value
>> 16) & 0xffff);
335 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
336 b43_write16(dev
, B43_MMIO_SHM_DATA
, value
& 0xffff);
341 b43_shm_control_word(dev
, routing
, offset
);
342 b43_write32(dev
, B43_MMIO_SHM_DATA
, value
);
344 spin_unlock_irqrestore(&wl
->shm_lock
, flags
);
347 void b43_shm_write16(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u16 value
)
349 struct b43_wl
*wl
= dev
->wl
;
352 spin_lock_irqsave(&wl
->shm_lock
, flags
);
353 if (routing
== B43_SHM_SHARED
) {
354 B43_WARN_ON(offset
& 0x0001);
355 if (offset
& 0x0003) {
356 /* Unaligned access */
357 b43_shm_control_word(dev
, routing
, offset
>> 2);
358 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
, value
);
363 b43_shm_control_word(dev
, routing
, offset
);
364 b43_write16(dev
, B43_MMIO_SHM_DATA
, value
);
366 spin_unlock_irqrestore(&wl
->shm_lock
, flags
);
370 u32
b43_hf_read(struct b43_wldev
* dev
)
374 ret
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFHI
);
376 ret
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFLO
);
381 /* Write HostFlags */
382 void b43_hf_write(struct b43_wldev
*dev
, u32 value
)
384 b43_shm_write16(dev
, B43_SHM_SHARED
,
385 B43_SHM_SH_HOSTFLO
, (value
& 0x0000FFFF));
386 b43_shm_write16(dev
, B43_SHM_SHARED
,
387 B43_SHM_SH_HOSTFHI
, ((value
& 0xFFFF0000) >> 16));
390 void b43_tsf_read(struct b43_wldev
*dev
, u64
* tsf
)
392 /* We need to be careful. As we read the TSF from multiple
393 * registers, we should take care of register overflows.
394 * In theory, the whole tsf read process should be atomic.
395 * We try to be atomic here, by restaring the read process,
396 * if any of the high registers changed (overflew).
398 if (dev
->dev
->id
.revision
>= 3) {
399 u32 low
, high
, high2
;
402 high
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
);
403 low
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
);
404 high2
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
);
405 } while (unlikely(high
!= high2
));
413 u16 test1
, test2
, test3
;
416 v3
= b43_read16(dev
, B43_MMIO_TSF_3
);
417 v2
= b43_read16(dev
, B43_MMIO_TSF_2
);
418 v1
= b43_read16(dev
, B43_MMIO_TSF_1
);
419 v0
= b43_read16(dev
, B43_MMIO_TSF_0
);
421 test3
= b43_read16(dev
, B43_MMIO_TSF_3
);
422 test2
= b43_read16(dev
, B43_MMIO_TSF_2
);
423 test1
= b43_read16(dev
, B43_MMIO_TSF_1
);
424 } while (v3
!= test3
|| v2
!= test2
|| v1
!= test1
);
438 static void b43_time_lock(struct b43_wldev
*dev
)
442 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
443 macctl
|= B43_MACCTL_TBTTHOLD
;
444 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
445 /* Commit the write */
446 b43_read32(dev
, B43_MMIO_MACCTL
);
449 static void b43_time_unlock(struct b43_wldev
*dev
)
453 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
454 macctl
&= ~B43_MACCTL_TBTTHOLD
;
455 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
456 /* Commit the write */
457 b43_read32(dev
, B43_MMIO_MACCTL
);
460 static void b43_tsf_write_locked(struct b43_wldev
*dev
, u64 tsf
)
462 /* Be careful with the in-progress timer.
463 * First zero out the low register, so we have a full
464 * register-overflow duration to complete the operation.
466 if (dev
->dev
->id
.revision
>= 3) {
467 u32 lo
= (tsf
& 0x00000000FFFFFFFFULL
);
468 u32 hi
= (tsf
& 0xFFFFFFFF00000000ULL
) >> 32;
470 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
, 0);
472 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
, hi
);
474 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
, lo
);
476 u16 v0
= (tsf
& 0x000000000000FFFFULL
);
477 u16 v1
= (tsf
& 0x00000000FFFF0000ULL
) >> 16;
478 u16 v2
= (tsf
& 0x0000FFFF00000000ULL
) >> 32;
479 u16 v3
= (tsf
& 0xFFFF000000000000ULL
) >> 48;
481 b43_write16(dev
, B43_MMIO_TSF_0
, 0);
483 b43_write16(dev
, B43_MMIO_TSF_3
, v3
);
485 b43_write16(dev
, B43_MMIO_TSF_2
, v2
);
487 b43_write16(dev
, B43_MMIO_TSF_1
, v1
);
489 b43_write16(dev
, B43_MMIO_TSF_0
, v0
);
493 void b43_tsf_write(struct b43_wldev
*dev
, u64 tsf
)
496 b43_tsf_write_locked(dev
, tsf
);
497 b43_time_unlock(dev
);
501 void b43_macfilter_set(struct b43_wldev
*dev
, u16 offset
, const u8
* mac
)
503 static const u8 zero_addr
[ETH_ALEN
] = { 0 };
510 b43_write16(dev
, B43_MMIO_MACFILTER_CONTROL
, offset
);
514 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
517 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
520 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
523 static void b43_write_mac_bssid_templates(struct b43_wldev
*dev
)
527 u8 mac_bssid
[ETH_ALEN
* 2];
531 bssid
= dev
->wl
->bssid
;
532 mac
= dev
->wl
->mac_addr
;
534 b43_macfilter_set(dev
, B43_MACFILTER_BSSID
, bssid
);
536 memcpy(mac_bssid
, mac
, ETH_ALEN
);
537 memcpy(mac_bssid
+ ETH_ALEN
, bssid
, ETH_ALEN
);
539 /* Write our MAC address and BSSID to template ram */
540 for (i
= 0; i
< ARRAY_SIZE(mac_bssid
); i
+= sizeof(u32
)) {
541 tmp
= (u32
) (mac_bssid
[i
+ 0]);
542 tmp
|= (u32
) (mac_bssid
[i
+ 1]) << 8;
543 tmp
|= (u32
) (mac_bssid
[i
+ 2]) << 16;
544 tmp
|= (u32
) (mac_bssid
[i
+ 3]) << 24;
545 b43_ram_write(dev
, 0x20 + i
, tmp
);
549 static void b43_upload_card_macaddress(struct b43_wldev
*dev
)
551 b43_write_mac_bssid_templates(dev
);
552 b43_macfilter_set(dev
, B43_MACFILTER_SELF
, dev
->wl
->mac_addr
);
555 static void b43_set_slot_time(struct b43_wldev
*dev
, u16 slot_time
)
557 /* slot_time is in usec. */
558 if (dev
->phy
.type
!= B43_PHYTYPE_G
)
560 b43_write16(dev
, 0x684, 510 + slot_time
);
561 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0010, slot_time
);
564 static void b43_short_slot_timing_enable(struct b43_wldev
*dev
)
566 b43_set_slot_time(dev
, 9);
570 static void b43_short_slot_timing_disable(struct b43_wldev
*dev
)
572 b43_set_slot_time(dev
, 20);
576 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
577 * Returns the _previously_ enabled IRQ mask.
579 static inline u32
b43_interrupt_enable(struct b43_wldev
*dev
, u32 mask
)
583 old_mask
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
584 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, old_mask
| mask
);
589 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
590 * Returns the _previously_ enabled IRQ mask.
592 static inline u32
b43_interrupt_disable(struct b43_wldev
*dev
, u32 mask
)
596 old_mask
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
597 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, old_mask
& ~mask
);
602 /* Synchronize IRQ top- and bottom-half.
603 * IRQs must be masked before calling this.
604 * This must not be called with the irq_lock held.
606 static void b43_synchronize_irq(struct b43_wldev
*dev
)
608 synchronize_irq(dev
->dev
->irq
);
609 tasklet_kill(&dev
->isr_tasklet
);
612 /* DummyTransmission function, as documented on
613 * http://bcm-specs.sipsolutions.net/DummyTransmission
615 void b43_dummy_transmission(struct b43_wldev
*dev
)
617 struct b43_phy
*phy
= &dev
->phy
;
618 unsigned int i
, max_loop
;
631 buffer
[0] = 0x000201CC;
636 buffer
[0] = 0x000B846E;
643 for (i
= 0; i
< 5; i
++)
644 b43_ram_write(dev
, i
* 4, buffer
[i
]);
647 b43_read32(dev
, B43_MMIO_MACCTL
);
649 b43_write16(dev
, 0x0568, 0x0000);
650 b43_write16(dev
, 0x07C0, 0x0000);
651 value
= ((phy
->type
== B43_PHYTYPE_A
) ? 1 : 0);
652 b43_write16(dev
, 0x050C, value
);
653 b43_write16(dev
, 0x0508, 0x0000);
654 b43_write16(dev
, 0x050A, 0x0000);
655 b43_write16(dev
, 0x054C, 0x0000);
656 b43_write16(dev
, 0x056A, 0x0014);
657 b43_write16(dev
, 0x0568, 0x0826);
658 b43_write16(dev
, 0x0500, 0x0000);
659 b43_write16(dev
, 0x0502, 0x0030);
661 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
662 b43_radio_write16(dev
, 0x0051, 0x0017);
663 for (i
= 0x00; i
< max_loop
; i
++) {
664 value
= b43_read16(dev
, 0x050E);
669 for (i
= 0x00; i
< 0x0A; i
++) {
670 value
= b43_read16(dev
, 0x050E);
675 for (i
= 0x00; i
< 0x0A; i
++) {
676 value
= b43_read16(dev
, 0x0690);
677 if (!(value
& 0x0100))
681 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
682 b43_radio_write16(dev
, 0x0051, 0x0037);
685 static void key_write(struct b43_wldev
*dev
,
686 u8 index
, u8 algorithm
, const u8
* key
)
693 /* Key index/algo block */
694 kidx
= b43_kidx_to_fw(dev
, index
);
695 value
= ((kidx
<< 4) | algorithm
);
696 b43_shm_write16(dev
, B43_SHM_SHARED
,
697 B43_SHM_SH_KEYIDXBLOCK
+ (kidx
* 2), value
);
699 /* Write the key to the Key Table Pointer offset */
700 offset
= dev
->ktp
+ (index
* B43_SEC_KEYSIZE
);
701 for (i
= 0; i
< B43_SEC_KEYSIZE
; i
+= 2) {
703 value
|= (u16
) (key
[i
+ 1]) << 8;
704 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
, value
);
708 static void keymac_write(struct b43_wldev
*dev
, u8 index
, const u8
* addr
)
710 u32 addrtmp
[2] = { 0, 0, };
711 u8 per_sta_keys_start
= 8;
713 if (b43_new_kidx_api(dev
))
714 per_sta_keys_start
= 4;
716 B43_WARN_ON(index
< per_sta_keys_start
);
717 /* We have two default TX keys and possibly two default RX keys.
718 * Physical mac 0 is mapped to physical key 4 or 8, depending
719 * on the firmware version.
720 * So we must adjust the index here.
722 index
-= per_sta_keys_start
;
725 addrtmp
[0] = addr
[0];
726 addrtmp
[0] |= ((u32
) (addr
[1]) << 8);
727 addrtmp
[0] |= ((u32
) (addr
[2]) << 16);
728 addrtmp
[0] |= ((u32
) (addr
[3]) << 24);
729 addrtmp
[1] = addr
[4];
730 addrtmp
[1] |= ((u32
) (addr
[5]) << 8);
733 if (dev
->dev
->id
.revision
>= 5) {
734 /* Receive match transmitter address mechanism */
735 b43_shm_write32(dev
, B43_SHM_RCMTA
,
736 (index
* 2) + 0, addrtmp
[0]);
737 b43_shm_write16(dev
, B43_SHM_RCMTA
,
738 (index
* 2) + 1, addrtmp
[1]);
740 /* RXE (Receive Engine) and
741 * PSM (Programmable State Machine) mechanism
744 /* TODO write to RCM 16, 19, 22 and 25 */
746 b43_shm_write32(dev
, B43_SHM_SHARED
,
747 B43_SHM_SH_PSM
+ (index
* 6) + 0,
749 b43_shm_write16(dev
, B43_SHM_SHARED
,
750 B43_SHM_SH_PSM
+ (index
* 6) + 4,
756 static void do_key_write(struct b43_wldev
*dev
,
757 u8 index
, u8 algorithm
,
758 const u8
* key
, size_t key_len
, const u8
* mac_addr
)
760 u8 buf
[B43_SEC_KEYSIZE
] = { 0, };
761 u8 per_sta_keys_start
= 8;
763 if (b43_new_kidx_api(dev
))
764 per_sta_keys_start
= 4;
766 B43_WARN_ON(index
>= dev
->max_nr_keys
);
767 B43_WARN_ON(key_len
> B43_SEC_KEYSIZE
);
769 if (index
>= per_sta_keys_start
)
770 keymac_write(dev
, index
, NULL
); /* First zero out mac. */
772 memcpy(buf
, key
, key_len
);
773 key_write(dev
, index
, algorithm
, buf
);
774 if (index
>= per_sta_keys_start
)
775 keymac_write(dev
, index
, mac_addr
);
777 dev
->key
[index
].algorithm
= algorithm
;
780 static int b43_key_write(struct b43_wldev
*dev
,
781 int index
, u8 algorithm
,
782 const u8
* key
, size_t key_len
,
784 struct ieee80211_key_conf
*keyconf
)
789 if (key_len
> B43_SEC_KEYSIZE
)
791 for (i
= 0; i
< dev
->max_nr_keys
; i
++) {
792 /* Check that we don't already have this key. */
793 B43_WARN_ON(dev
->key
[i
].keyconf
== keyconf
);
796 /* Either pairwise key or address is 00:00:00:00:00:00
797 * for transmit-only keys. Search the index. */
798 if (b43_new_kidx_api(dev
))
802 for (i
= sta_keys_start
; i
< dev
->max_nr_keys
; i
++) {
803 if (!dev
->key
[i
].keyconf
) {
810 b43err(dev
->wl
, "Out of hardware key memory\n");
814 B43_WARN_ON(index
> 3);
816 do_key_write(dev
, index
, algorithm
, key
, key_len
, mac_addr
);
817 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
819 B43_WARN_ON(mac_addr
);
820 do_key_write(dev
, index
+ 4, algorithm
, key
, key_len
, NULL
);
822 keyconf
->hw_key_idx
= index
;
823 dev
->key
[index
].keyconf
= keyconf
;
828 static int b43_key_clear(struct b43_wldev
*dev
, int index
)
830 if (B43_WARN_ON((index
< 0) || (index
>= dev
->max_nr_keys
)))
832 do_key_write(dev
, index
, B43_SEC_ALGO_NONE
,
833 NULL
, B43_SEC_KEYSIZE
, NULL
);
834 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
835 do_key_write(dev
, index
+ 4, B43_SEC_ALGO_NONE
,
836 NULL
, B43_SEC_KEYSIZE
, NULL
);
838 dev
->key
[index
].keyconf
= NULL
;
843 static void b43_clear_keys(struct b43_wldev
*dev
)
847 for (i
= 0; i
< dev
->max_nr_keys
; i
++)
848 b43_key_clear(dev
, i
);
851 void b43_power_saving_ctl_bits(struct b43_wldev
*dev
, unsigned int ps_flags
)
859 B43_WARN_ON((ps_flags
& B43_PS_ENABLED
) &&
860 (ps_flags
& B43_PS_DISABLED
));
861 B43_WARN_ON((ps_flags
& B43_PS_AWAKE
) && (ps_flags
& B43_PS_ASLEEP
));
863 if (ps_flags
& B43_PS_ENABLED
) {
865 } else if (ps_flags
& B43_PS_DISABLED
) {
868 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
869 // and thus is not an AP and we are associated, set bit 25
871 if (ps_flags
& B43_PS_AWAKE
) {
873 } else if (ps_flags
& B43_PS_ASLEEP
) {
876 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
877 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
878 // successful, set bit26
881 /* FIXME: For now we force awake-on and hwps-off */
885 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
887 macctl
|= B43_MACCTL_HWPS
;
889 macctl
&= ~B43_MACCTL_HWPS
;
891 macctl
|= B43_MACCTL_AWAKE
;
893 macctl
&= ~B43_MACCTL_AWAKE
;
894 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
896 b43_read32(dev
, B43_MMIO_MACCTL
);
897 if (awake
&& dev
->dev
->id
.revision
>= 5) {
898 /* Wait for the microcode to wake up. */
899 for (i
= 0; i
< 100; i
++) {
900 ucstat
= b43_shm_read16(dev
, B43_SHM_SHARED
,
901 B43_SHM_SH_UCODESTAT
);
902 if (ucstat
!= B43_SHM_SH_UCODESTAT_SLEEP
)
909 /* Turn the Analog ON/OFF */
910 static void b43_switch_analog(struct b43_wldev
*dev
, int on
)
912 b43_write16(dev
, B43_MMIO_PHY0
, on
? 0 : 0xF4);
915 void b43_wireless_core_reset(struct b43_wldev
*dev
, u32 flags
)
920 flags
|= B43_TMSLOW_PHYCLKEN
;
921 flags
|= B43_TMSLOW_PHYRESET
;
922 ssb_device_enable(dev
->dev
, flags
);
923 msleep(2); /* Wait for the PLL to turn on. */
925 /* Now take the PHY out of Reset again */
926 tmslow
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
927 tmslow
|= SSB_TMSLOW_FGC
;
928 tmslow
&= ~B43_TMSLOW_PHYRESET
;
929 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
930 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
932 tmslow
&= ~SSB_TMSLOW_FGC
;
933 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
934 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
938 b43_switch_analog(dev
, 1);
940 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
941 macctl
&= ~B43_MACCTL_GMODE
;
942 if (flags
& B43_TMSLOW_GMODE
)
943 macctl
|= B43_MACCTL_GMODE
;
944 macctl
|= B43_MACCTL_IHR_ENABLED
;
945 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
948 static void handle_irq_transmit_status(struct b43_wldev
*dev
)
952 struct b43_txstatus stat
;
955 v0
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
956 if (!(v0
& 0x00000001))
958 v1
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
960 stat
.cookie
= (v0
>> 16);
961 stat
.seq
= (v1
& 0x0000FFFF);
962 stat
.phy_stat
= ((v1
& 0x00FF0000) >> 16);
963 tmp
= (v0
& 0x0000FFFF);
964 stat
.frame_count
= ((tmp
& 0xF000) >> 12);
965 stat
.rts_count
= ((tmp
& 0x0F00) >> 8);
966 stat
.supp_reason
= ((tmp
& 0x001C) >> 2);
967 stat
.pm_indicated
= !!(tmp
& 0x0080);
968 stat
.intermediate
= !!(tmp
& 0x0040);
969 stat
.for_ampdu
= !!(tmp
& 0x0020);
970 stat
.acked
= !!(tmp
& 0x0002);
972 b43_handle_txstatus(dev
, &stat
);
976 static void drain_txstatus_queue(struct b43_wldev
*dev
)
980 if (dev
->dev
->id
.revision
< 5)
982 /* Read all entries from the microcode TXstatus FIFO
983 * and throw them away.
986 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
987 if (!(dummy
& 0x00000001))
989 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
993 static u32
b43_jssi_read(struct b43_wldev
*dev
)
997 val
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x08A);
999 val
|= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x088);
1004 static void b43_jssi_write(struct b43_wldev
*dev
, u32 jssi
)
1006 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x088, (jssi
& 0x0000FFFF));
1007 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x08A, (jssi
& 0xFFFF0000) >> 16);
1010 static void b43_generate_noise_sample(struct b43_wldev
*dev
)
1012 b43_jssi_write(dev
, 0x7F7F7F7F);
1013 b43_write32(dev
, B43_MMIO_MACCMD
,
1014 b43_read32(dev
, B43_MMIO_MACCMD
) | B43_MACCMD_BGNOISE
);
1015 B43_WARN_ON(dev
->noisecalc
.channel_at_start
!= dev
->phy
.channel
);
1018 static void b43_calculate_link_quality(struct b43_wldev
*dev
)
1020 /* Top half of Link Quality calculation. */
1022 if (dev
->noisecalc
.calculation_running
)
1024 dev
->noisecalc
.channel_at_start
= dev
->phy
.channel
;
1025 dev
->noisecalc
.calculation_running
= 1;
1026 dev
->noisecalc
.nr_samples
= 0;
1028 b43_generate_noise_sample(dev
);
1031 static void handle_irq_noise(struct b43_wldev
*dev
)
1033 struct b43_phy
*phy
= &dev
->phy
;
1039 /* Bottom half of Link Quality calculation. */
1041 B43_WARN_ON(!dev
->noisecalc
.calculation_running
);
1042 if (dev
->noisecalc
.channel_at_start
!= phy
->channel
)
1043 goto drop_calculation
;
1044 *((__le32
*)noise
) = cpu_to_le32(b43_jssi_read(dev
));
1045 if (noise
[0] == 0x7F || noise
[1] == 0x7F ||
1046 noise
[2] == 0x7F || noise
[3] == 0x7F)
1049 /* Get the noise samples. */
1050 B43_WARN_ON(dev
->noisecalc
.nr_samples
>= 8);
1051 i
= dev
->noisecalc
.nr_samples
;
1052 noise
[0] = limit_value(noise
[0], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1053 noise
[1] = limit_value(noise
[1], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1054 noise
[2] = limit_value(noise
[2], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1055 noise
[3] = limit_value(noise
[3], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1056 dev
->noisecalc
.samples
[i
][0] = phy
->nrssi_lt
[noise
[0]];
1057 dev
->noisecalc
.samples
[i
][1] = phy
->nrssi_lt
[noise
[1]];
1058 dev
->noisecalc
.samples
[i
][2] = phy
->nrssi_lt
[noise
[2]];
1059 dev
->noisecalc
.samples
[i
][3] = phy
->nrssi_lt
[noise
[3]];
1060 dev
->noisecalc
.nr_samples
++;
1061 if (dev
->noisecalc
.nr_samples
== 8) {
1062 /* Calculate the Link Quality by the noise samples. */
1064 for (i
= 0; i
< 8; i
++) {
1065 for (j
= 0; j
< 4; j
++)
1066 average
+= dev
->noisecalc
.samples
[i
][j
];
1072 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x40C);
1073 tmp
= (tmp
/ 128) & 0x1F;
1083 dev
->stats
.link_noise
= average
;
1085 dev
->noisecalc
.calculation_running
= 0;
1089 b43_generate_noise_sample(dev
);
1092 static void handle_irq_tbtt_indication(struct b43_wldev
*dev
)
1094 if (b43_is_mode(dev
->wl
, IEEE80211_IF_TYPE_AP
)) {
1097 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1098 b43_power_saving_ctl_bits(dev
, 0);
1100 if (b43_is_mode(dev
->wl
, IEEE80211_IF_TYPE_IBSS
))
1104 static void handle_irq_atim_end(struct b43_wldev
*dev
)
1106 if (dev
->dfq_valid
) {
1107 b43_write32(dev
, B43_MMIO_MACCMD
,
1108 b43_read32(dev
, B43_MMIO_MACCMD
)
1109 | B43_MACCMD_DFQ_VALID
);
1114 static void handle_irq_pmq(struct b43_wldev
*dev
)
1121 tmp
= b43_read32(dev
, B43_MMIO_PS_STATUS
);
1122 if (!(tmp
& 0x00000008))
1125 /* 16bit write is odd, but correct. */
1126 b43_write16(dev
, B43_MMIO_PS_STATUS
, 0x0002);
1129 static void b43_write_template_common(struct b43_wldev
*dev
,
1130 const u8
* data
, u16 size
,
1132 u16 shm_size_offset
, u8 rate
)
1135 struct b43_plcp_hdr4 plcp
;
1138 b43_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1139 b43_ram_write(dev
, ram_offset
, le32_to_cpu(plcp
.data
));
1140 ram_offset
+= sizeof(u32
);
1141 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1142 * So leave the first two bytes of the next write blank.
1144 tmp
= (u32
) (data
[0]) << 16;
1145 tmp
|= (u32
) (data
[1]) << 24;
1146 b43_ram_write(dev
, ram_offset
, tmp
);
1147 ram_offset
+= sizeof(u32
);
1148 for (i
= 2; i
< size
; i
+= sizeof(u32
)) {
1149 tmp
= (u32
) (data
[i
+ 0]);
1151 tmp
|= (u32
) (data
[i
+ 1]) << 8;
1153 tmp
|= (u32
) (data
[i
+ 2]) << 16;
1155 tmp
|= (u32
) (data
[i
+ 3]) << 24;
1156 b43_ram_write(dev
, ram_offset
+ i
- 2, tmp
);
1158 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_size_offset
,
1159 size
+ sizeof(struct b43_plcp_hdr6
));
1162 static void b43_write_beacon_template(struct b43_wldev
*dev
,
1164 u16 shm_size_offset
, u8 rate
)
1166 unsigned int i
, len
, variable_len
;
1167 const struct ieee80211_mgmt
*bcn
;
1171 bcn
= (const struct ieee80211_mgmt
*)(dev
->wl
->current_beacon
->data
);
1172 len
= min((size_t) dev
->wl
->current_beacon
->len
,
1173 0x200 - sizeof(struct b43_plcp_hdr6
));
1175 b43_write_template_common(dev
, (const u8
*)bcn
,
1176 len
, ram_offset
, shm_size_offset
, rate
);
1178 /* Find the position of the TIM and the DTIM_period value
1179 * and write them to SHM. */
1180 ie
= bcn
->u
.beacon
.variable
;
1181 variable_len
= len
- offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
);
1182 for (i
= 0; i
< variable_len
- 2; ) {
1183 uint8_t ie_id
, ie_len
;
1190 /* This is the TIM Information Element */
1192 /* Check whether the ie_len is in the beacon data range. */
1193 if (variable_len
< ie_len
+ 2 + i
)
1195 /* A valid TIM is at least 4 bytes long. */
1200 tim_position
= sizeof(struct b43_plcp_hdr6
);
1201 tim_position
+= offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
);
1204 dtim_period
= ie
[i
+ 3];
1206 b43_shm_write16(dev
, B43_SHM_SHARED
,
1207 B43_SHM_SH_TIMBPOS
, tim_position
);
1208 b43_shm_write16(dev
, B43_SHM_SHARED
,
1209 B43_SHM_SH_DTIMPER
, dtim_period
);
1215 b43warn(dev
->wl
, "Did not find a valid TIM IE in "
1216 "the beacon template packet. AP or IBSS operation "
1217 "may be broken.\n");
1221 static void b43_write_probe_resp_plcp(struct b43_wldev
*dev
,
1222 u16 shm_offset
, u16 size
, u8 rate
)
1224 struct b43_plcp_hdr4 plcp
;
1229 b43_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1230 dur
= ieee80211_generic_frame_duration(dev
->wl
->hw
,
1232 B43_RATE_TO_BASE100KBPS(rate
));
1233 /* Write PLCP in two parts and timing for packet transfer */
1234 tmp
= le32_to_cpu(plcp
.data
);
1235 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
, tmp
& 0xFFFF);
1236 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
+ 2, tmp
>> 16);
1237 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
+ 6, le16_to_cpu(dur
));
1240 /* Instead of using custom probe response template, this function
1241 * just patches custom beacon template by:
1242 * 1) Changing packet type
1243 * 2) Patching duration field
1246 static const u8
* b43_generate_probe_resp(struct b43_wldev
*dev
,
1247 u16
*dest_size
, u8 rate
)
1251 u16 src_size
, elem_size
, src_pos
, dest_pos
;
1253 struct ieee80211_hdr
*hdr
;
1256 src_size
= dev
->wl
->current_beacon
->len
;
1257 src_data
= (const u8
*)dev
->wl
->current_beacon
->data
;
1259 /* Get the start offset of the variable IEs in the packet. */
1260 ie_start
= offsetof(struct ieee80211_mgmt
, u
.probe_resp
.variable
);
1261 B43_WARN_ON(ie_start
!= offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
));
1263 if (B43_WARN_ON(src_size
< ie_start
))
1266 dest_data
= kmalloc(src_size
, GFP_ATOMIC
);
1267 if (unlikely(!dest_data
))
1270 /* Copy the static data and all Information Elements, except the TIM. */
1271 memcpy(dest_data
, src_data
, ie_start
);
1273 dest_pos
= ie_start
;
1274 for ( ; src_pos
< src_size
- 2; src_pos
+= elem_size
) {
1275 elem_size
= src_data
[src_pos
+ 1] + 2;
1276 if (src_data
[src_pos
] == 5) {
1277 /* This is the TIM. */
1280 memcpy(dest_data
+ dest_pos
, src_data
+ src_pos
,
1282 dest_pos
+= elem_size
;
1284 *dest_size
= dest_pos
;
1285 hdr
= (struct ieee80211_hdr
*)dest_data
;
1287 /* Set the frame control. */
1288 hdr
->frame_control
= cpu_to_le16(IEEE80211_FTYPE_MGMT
|
1289 IEEE80211_STYPE_PROBE_RESP
);
1290 dur
= ieee80211_generic_frame_duration(dev
->wl
->hw
,
1291 dev
->wl
->vif
, *dest_size
,
1292 B43_RATE_TO_BASE100KBPS(rate
));
1293 hdr
->duration_id
= dur
;
1298 static void b43_write_probe_resp_template(struct b43_wldev
*dev
,
1300 u16 shm_size_offset
, u8 rate
)
1302 const u8
*probe_resp_data
;
1305 size
= dev
->wl
->current_beacon
->len
;
1306 probe_resp_data
= b43_generate_probe_resp(dev
, &size
, rate
);
1307 if (unlikely(!probe_resp_data
))
1310 /* Looks like PLCP headers plus packet timings are stored for
1311 * all possible basic rates
1313 b43_write_probe_resp_plcp(dev
, 0x31A, size
, B43_CCK_RATE_1MB
);
1314 b43_write_probe_resp_plcp(dev
, 0x32C, size
, B43_CCK_RATE_2MB
);
1315 b43_write_probe_resp_plcp(dev
, 0x33E, size
, B43_CCK_RATE_5MB
);
1316 b43_write_probe_resp_plcp(dev
, 0x350, size
, B43_CCK_RATE_11MB
);
1318 size
= min((size_t) size
, 0x200 - sizeof(struct b43_plcp_hdr6
));
1319 b43_write_template_common(dev
, probe_resp_data
,
1320 size
, ram_offset
, shm_size_offset
, rate
);
1321 kfree(probe_resp_data
);
1324 /* Asynchronously update the packet templates in template RAM.
1325 * Locking: Requires wl->irq_lock to be locked. */
1326 static void b43_update_templates(struct b43_wl
*wl
, struct sk_buff
*beacon
)
1328 /* This is the top half of the ansynchronous beacon update.
1329 * The bottom half is the beacon IRQ.
1330 * Beacon update must be asynchronous to avoid sending an
1331 * invalid beacon. This can happen for example, if the firmware
1332 * transmits a beacon while we are updating it. */
1334 if (wl
->current_beacon
)
1335 dev_kfree_skb_any(wl
->current_beacon
);
1336 wl
->current_beacon
= beacon
;
1337 wl
->beacon0_uploaded
= 0;
1338 wl
->beacon1_uploaded
= 0;
1341 static void b43_set_ssid(struct b43_wldev
*dev
, const u8
* ssid
, u8 ssid_len
)
1346 len
= min((u16
) ssid_len
, (u16
) 0x100);
1347 for (i
= 0; i
< len
; i
+= sizeof(u32
)) {
1348 tmp
= (u32
) (ssid
[i
+ 0]);
1350 tmp
|= (u32
) (ssid
[i
+ 1]) << 8;
1352 tmp
|= (u32
) (ssid
[i
+ 2]) << 16;
1354 tmp
|= (u32
) (ssid
[i
+ 3]) << 24;
1355 b43_shm_write32(dev
, B43_SHM_SHARED
, 0x380 + i
, tmp
);
1357 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x48, len
);
1360 static void b43_set_beacon_int(struct b43_wldev
*dev
, u16 beacon_int
)
1363 if (dev
->dev
->id
.revision
>= 3) {
1364 b43_write32(dev
, 0x188, (beacon_int
<< 16));
1366 b43_write16(dev
, 0x606, (beacon_int
>> 6));
1367 b43_write16(dev
, 0x610, beacon_int
);
1369 b43_time_unlock(dev
);
1372 static void handle_irq_beacon(struct b43_wldev
*dev
)
1374 struct b43_wl
*wl
= dev
->wl
;
1377 if (!b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
))
1380 /* This is the bottom half of the asynchronous beacon update. */
1382 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1383 if (!(cmd
& B43_MACCMD_BEACON0_VALID
)) {
1384 if (!wl
->beacon0_uploaded
) {
1385 b43_write_beacon_template(dev
, 0x68, 0x18,
1387 b43_write_probe_resp_template(dev
, 0x268, 0x4A,
1389 wl
->beacon0_uploaded
= 1;
1391 cmd
|= B43_MACCMD_BEACON0_VALID
;
1393 if (!(cmd
& B43_MACCMD_BEACON1_VALID
)) {
1394 if (!wl
->beacon1_uploaded
) {
1395 b43_write_beacon_template(dev
, 0x468, 0x1A,
1397 wl
->beacon1_uploaded
= 1;
1399 cmd
|= B43_MACCMD_BEACON1_VALID
;
1401 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1404 static void handle_irq_ucode_debug(struct b43_wldev
*dev
)
1409 /* Interrupt handler bottom-half */
1410 static void b43_interrupt_tasklet(struct b43_wldev
*dev
)
1413 u32 dma_reason
[ARRAY_SIZE(dev
->dma_reason
)];
1414 u32 merged_dma_reason
= 0;
1416 unsigned long flags
;
1418 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
1420 B43_WARN_ON(b43_status(dev
) != B43_STAT_STARTED
);
1422 reason
= dev
->irq_reason
;
1423 for (i
= 0; i
< ARRAY_SIZE(dma_reason
); i
++) {
1424 dma_reason
[i
] = dev
->dma_reason
[i
];
1425 merged_dma_reason
|= dma_reason
[i
];
1428 if (unlikely(reason
& B43_IRQ_MAC_TXERR
))
1429 b43err(dev
->wl
, "MAC transmission error\n");
1431 if (unlikely(reason
& B43_IRQ_PHY_TXERR
)) {
1432 b43err(dev
->wl
, "PHY transmission error\n");
1434 if (unlikely(atomic_dec_and_test(&dev
->phy
.txerr_cnt
))) {
1435 atomic_set(&dev
->phy
.txerr_cnt
,
1436 B43_PHY_TX_BADNESS_LIMIT
);
1437 b43err(dev
->wl
, "Too many PHY TX errors, "
1438 "restarting the controller\n");
1439 b43_controller_restart(dev
, "PHY TX errors");
1443 if (unlikely(merged_dma_reason
& (B43_DMAIRQ_FATALMASK
|
1444 B43_DMAIRQ_NONFATALMASK
))) {
1445 if (merged_dma_reason
& B43_DMAIRQ_FATALMASK
) {
1446 b43err(dev
->wl
, "Fatal DMA error: "
1447 "0x%08X, 0x%08X, 0x%08X, "
1448 "0x%08X, 0x%08X, 0x%08X\n",
1449 dma_reason
[0], dma_reason
[1],
1450 dma_reason
[2], dma_reason
[3],
1451 dma_reason
[4], dma_reason
[5]);
1452 b43_controller_restart(dev
, "DMA error");
1454 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
1457 if (merged_dma_reason
& B43_DMAIRQ_NONFATALMASK
) {
1458 b43err(dev
->wl
, "DMA error: "
1459 "0x%08X, 0x%08X, 0x%08X, "
1460 "0x%08X, 0x%08X, 0x%08X\n",
1461 dma_reason
[0], dma_reason
[1],
1462 dma_reason
[2], dma_reason
[3],
1463 dma_reason
[4], dma_reason
[5]);
1467 if (unlikely(reason
& B43_IRQ_UCODE_DEBUG
))
1468 handle_irq_ucode_debug(dev
);
1469 if (reason
& B43_IRQ_TBTT_INDI
)
1470 handle_irq_tbtt_indication(dev
);
1471 if (reason
& B43_IRQ_ATIM_END
)
1472 handle_irq_atim_end(dev
);
1473 if (reason
& B43_IRQ_BEACON
)
1474 handle_irq_beacon(dev
);
1475 if (reason
& B43_IRQ_PMQ
)
1476 handle_irq_pmq(dev
);
1477 if (reason
& B43_IRQ_TXFIFO_FLUSH_OK
)
1479 if (reason
& B43_IRQ_NOISESAMPLE_OK
)
1480 handle_irq_noise(dev
);
1482 /* Check the DMA reason registers for received data. */
1483 if (dma_reason
[0] & B43_DMAIRQ_RX_DONE
)
1484 b43_dma_rx(dev
->dma
.rx_ring0
);
1485 if (dma_reason
[3] & B43_DMAIRQ_RX_DONE
)
1486 b43_dma_rx(dev
->dma
.rx_ring3
);
1487 B43_WARN_ON(dma_reason
[1] & B43_DMAIRQ_RX_DONE
);
1488 B43_WARN_ON(dma_reason
[2] & B43_DMAIRQ_RX_DONE
);
1489 B43_WARN_ON(dma_reason
[4] & B43_DMAIRQ_RX_DONE
);
1490 B43_WARN_ON(dma_reason
[5] & B43_DMAIRQ_RX_DONE
);
1492 if (reason
& B43_IRQ_TX_OK
)
1493 handle_irq_transmit_status(dev
);
1495 b43_interrupt_enable(dev
, dev
->irq_savedstate
);
1497 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
1500 static void b43_interrupt_ack(struct b43_wldev
*dev
, u32 reason
)
1502 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, reason
);
1504 b43_write32(dev
, B43_MMIO_DMA0_REASON
, dev
->dma_reason
[0]);
1505 b43_write32(dev
, B43_MMIO_DMA1_REASON
, dev
->dma_reason
[1]);
1506 b43_write32(dev
, B43_MMIO_DMA2_REASON
, dev
->dma_reason
[2]);
1507 b43_write32(dev
, B43_MMIO_DMA3_REASON
, dev
->dma_reason
[3]);
1508 b43_write32(dev
, B43_MMIO_DMA4_REASON
, dev
->dma_reason
[4]);
1509 b43_write32(dev
, B43_MMIO_DMA5_REASON
, dev
->dma_reason
[5]);
1512 /* Interrupt handler top-half */
1513 static irqreturn_t
b43_interrupt_handler(int irq
, void *dev_id
)
1515 irqreturn_t ret
= IRQ_NONE
;
1516 struct b43_wldev
*dev
= dev_id
;
1522 spin_lock(&dev
->wl
->irq_lock
);
1524 if (b43_status(dev
) < B43_STAT_STARTED
)
1526 reason
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
1527 if (reason
== 0xffffffff) /* shared IRQ */
1530 reason
&= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
1534 dev
->dma_reason
[0] = b43_read32(dev
, B43_MMIO_DMA0_REASON
)
1536 dev
->dma_reason
[1] = b43_read32(dev
, B43_MMIO_DMA1_REASON
)
1538 dev
->dma_reason
[2] = b43_read32(dev
, B43_MMIO_DMA2_REASON
)
1540 dev
->dma_reason
[3] = b43_read32(dev
, B43_MMIO_DMA3_REASON
)
1542 dev
->dma_reason
[4] = b43_read32(dev
, B43_MMIO_DMA4_REASON
)
1544 dev
->dma_reason
[5] = b43_read32(dev
, B43_MMIO_DMA5_REASON
)
1547 b43_interrupt_ack(dev
, reason
);
1548 /* disable all IRQs. They are enabled again in the bottom half. */
1549 dev
->irq_savedstate
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
1550 /* save the reason code and call our bottom half. */
1551 dev
->irq_reason
= reason
;
1552 tasklet_schedule(&dev
->isr_tasklet
);
1555 spin_unlock(&dev
->wl
->irq_lock
);
1560 static void do_release_fw(struct b43_firmware_file
*fw
)
1562 release_firmware(fw
->data
);
1564 fw
->filename
= NULL
;
1567 static void b43_release_firmware(struct b43_wldev
*dev
)
1569 do_release_fw(&dev
->fw
.ucode
);
1570 do_release_fw(&dev
->fw
.pcm
);
1571 do_release_fw(&dev
->fw
.initvals
);
1572 do_release_fw(&dev
->fw
.initvals_band
);
1575 static void b43_print_fw_helptext(struct b43_wl
*wl
, bool error
)
1579 text
= "You must go to "
1580 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1581 "and download the latest firmware (version 4).\n";
1588 static int do_request_fw(struct b43_wldev
*dev
,
1590 struct b43_firmware_file
*fw
)
1592 char path
[sizeof(modparam_fwpostfix
) + 32];
1593 const struct firmware
*blob
;
1594 struct b43_fw_header
*hdr
;
1599 /* Don't fetch anything. Free possibly cached firmware. */
1604 if (strcmp(fw
->filename
, name
) == 0)
1605 return 0; /* Already have this fw. */
1606 /* Free the cached firmware first. */
1610 snprintf(path
, ARRAY_SIZE(path
),
1612 modparam_fwpostfix
, name
);
1613 err
= request_firmware(&blob
, path
, dev
->dev
->dev
);
1615 b43err(dev
->wl
, "Firmware file \"%s\" not found "
1616 "or load failed.\n", path
);
1619 if (blob
->size
< sizeof(struct b43_fw_header
))
1621 hdr
= (struct b43_fw_header
*)(blob
->data
);
1622 switch (hdr
->type
) {
1623 case B43_FW_TYPE_UCODE
:
1624 case B43_FW_TYPE_PCM
:
1625 size
= be32_to_cpu(hdr
->size
);
1626 if (size
!= blob
->size
- sizeof(struct b43_fw_header
))
1629 case B43_FW_TYPE_IV
:
1638 fw
->filename
= name
;
1643 b43err(dev
->wl
, "Firmware file \"%s\" format error.\n", path
);
1644 release_firmware(blob
);
1649 static int b43_request_firmware(struct b43_wldev
*dev
)
1651 struct b43_firmware
*fw
= &dev
->fw
;
1652 const u8 rev
= dev
->dev
->id
.revision
;
1653 const char *filename
;
1658 tmshigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
1659 if ((rev
>= 5) && (rev
<= 10))
1660 filename
= "ucode5";
1661 else if ((rev
>= 11) && (rev
<= 12))
1662 filename
= "ucode11";
1664 filename
= "ucode13";
1667 err
= do_request_fw(dev
, filename
, &fw
->ucode
);
1672 if ((rev
>= 5) && (rev
<= 10))
1678 err
= do_request_fw(dev
, filename
, &fw
->pcm
);
1683 switch (dev
->phy
.type
) {
1685 if ((rev
>= 5) && (rev
<= 10)) {
1686 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
1687 filename
= "a0g1initvals5";
1689 filename
= "a0g0initvals5";
1691 goto err_no_initvals
;
1694 if ((rev
>= 5) && (rev
<= 10))
1695 filename
= "b0g0initvals5";
1697 filename
= "lp0initvals13";
1699 goto err_no_initvals
;
1702 if ((rev
>= 11) && (rev
<= 12))
1703 filename
= "n0initvals11";
1705 goto err_no_initvals
;
1708 goto err_no_initvals
;
1710 err
= do_request_fw(dev
, filename
, &fw
->initvals
);
1714 /* Get bandswitch initvals */
1715 switch (dev
->phy
.type
) {
1717 if ((rev
>= 5) && (rev
<= 10)) {
1718 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
1719 filename
= "a0g1bsinitvals5";
1721 filename
= "a0g0bsinitvals5";
1722 } else if (rev
>= 11)
1725 goto err_no_initvals
;
1728 if ((rev
>= 5) && (rev
<= 10))
1729 filename
= "b0g0bsinitvals5";
1733 goto err_no_initvals
;
1736 if ((rev
>= 11) && (rev
<= 12))
1737 filename
= "n0bsinitvals11";
1739 goto err_no_initvals
;
1742 goto err_no_initvals
;
1744 err
= do_request_fw(dev
, filename
, &fw
->initvals_band
);
1751 b43_print_fw_helptext(dev
->wl
, 1);
1756 b43err(dev
->wl
, "No microcode available for core rev %u\n", rev
);
1761 b43err(dev
->wl
, "No PCM available for core rev %u\n", rev
);
1766 b43err(dev
->wl
, "No Initial Values firmware file for PHY %u, "
1767 "core rev %u\n", dev
->phy
.type
, rev
);
1771 b43_release_firmware(dev
);
1775 static int b43_upload_microcode(struct b43_wldev
*dev
)
1777 const size_t hdr_len
= sizeof(struct b43_fw_header
);
1779 unsigned int i
, len
;
1780 u16 fwrev
, fwpatch
, fwdate
, fwtime
;
1784 /* Jump the microcode PSM to offset 0 */
1785 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
1786 B43_WARN_ON(macctl
& B43_MACCTL_PSM_RUN
);
1787 macctl
|= B43_MACCTL_PSM_JMP0
;
1788 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
1789 /* Zero out all microcode PSM registers and shared memory. */
1790 for (i
= 0; i
< 64; i
++)
1791 b43_shm_write16(dev
, B43_SHM_SCRATCH
, i
, 0);
1792 for (i
= 0; i
< 4096; i
+= 2)
1793 b43_shm_write16(dev
, B43_SHM_SHARED
, i
, 0);
1795 /* Upload Microcode. */
1796 data
= (__be32
*) (dev
->fw
.ucode
.data
->data
+ hdr_len
);
1797 len
= (dev
->fw
.ucode
.data
->size
- hdr_len
) / sizeof(__be32
);
1798 b43_shm_control_word(dev
, B43_SHM_UCODE
| B43_SHM_AUTOINC_W
, 0x0000);
1799 for (i
= 0; i
< len
; i
++) {
1800 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
1804 if (dev
->fw
.pcm
.data
) {
1805 /* Upload PCM data. */
1806 data
= (__be32
*) (dev
->fw
.pcm
.data
->data
+ hdr_len
);
1807 len
= (dev
->fw
.pcm
.data
->size
- hdr_len
) / sizeof(__be32
);
1808 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EA);
1809 b43_write32(dev
, B43_MMIO_SHM_DATA
, 0x00004000);
1810 /* No need for autoinc bit in SHM_HW */
1811 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EB);
1812 for (i
= 0; i
< len
; i
++) {
1813 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
1818 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_ALL
);
1820 /* Start the microcode PSM */
1821 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
1822 macctl
&= ~B43_MACCTL_PSM_JMP0
;
1823 macctl
|= B43_MACCTL_PSM_RUN
;
1824 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
1826 /* Wait for the microcode to load and respond */
1829 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
1830 if (tmp
== B43_IRQ_MAC_SUSPENDED
)
1834 b43err(dev
->wl
, "Microcode not responding\n");
1835 b43_print_fw_helptext(dev
->wl
, 1);
1839 msleep_interruptible(50);
1840 if (signal_pending(current
)) {
1845 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
); /* dummy read */
1847 /* Get and check the revisions. */
1848 fwrev
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEREV
);
1849 fwpatch
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEPATCH
);
1850 fwdate
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEDATE
);
1851 fwtime
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODETIME
);
1853 if (fwrev
<= 0x128) {
1854 b43err(dev
->wl
, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1855 "binary drivers older than version 4.x is unsupported. "
1856 "You must upgrade your firmware files.\n");
1857 b43_print_fw_helptext(dev
->wl
, 1);
1861 b43dbg(dev
->wl
, "Loading firmware version %u.%u "
1862 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1864 (fwdate
>> 12) & 0xF, (fwdate
>> 8) & 0xF, fwdate
& 0xFF,
1865 (fwtime
>> 11) & 0x1F, (fwtime
>> 5) & 0x3F, fwtime
& 0x1F);
1867 dev
->fw
.rev
= fwrev
;
1868 dev
->fw
.patch
= fwpatch
;
1870 if (b43_is_old_txhdr_format(dev
)) {
1871 b43warn(dev
->wl
, "You are using an old firmware image. "
1872 "Support for old firmware will be removed in July 2008.\n");
1873 b43_print_fw_helptext(dev
->wl
, 0);
1879 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
1880 macctl
&= ~B43_MACCTL_PSM_RUN
;
1881 macctl
|= B43_MACCTL_PSM_JMP0
;
1882 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
1887 static int b43_write_initvals(struct b43_wldev
*dev
,
1888 const struct b43_iv
*ivals
,
1892 const struct b43_iv
*iv
;
1897 BUILD_BUG_ON(sizeof(struct b43_iv
) != 6);
1899 for (i
= 0; i
< count
; i
++) {
1900 if (array_size
< sizeof(iv
->offset_size
))
1902 array_size
-= sizeof(iv
->offset_size
);
1903 offset
= be16_to_cpu(iv
->offset_size
);
1904 bit32
= !!(offset
& B43_IV_32BIT
);
1905 offset
&= B43_IV_OFFSET_MASK
;
1906 if (offset
>= 0x1000)
1911 if (array_size
< sizeof(iv
->data
.d32
))
1913 array_size
-= sizeof(iv
->data
.d32
);
1915 value
= be32_to_cpu(get_unaligned(&iv
->data
.d32
));
1916 b43_write32(dev
, offset
, value
);
1918 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
1924 if (array_size
< sizeof(iv
->data
.d16
))
1926 array_size
-= sizeof(iv
->data
.d16
);
1928 value
= be16_to_cpu(iv
->data
.d16
);
1929 b43_write16(dev
, offset
, value
);
1931 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
1942 b43err(dev
->wl
, "Initial Values Firmware file-format error.\n");
1943 b43_print_fw_helptext(dev
->wl
, 1);
1948 static int b43_upload_initvals(struct b43_wldev
*dev
)
1950 const size_t hdr_len
= sizeof(struct b43_fw_header
);
1951 const struct b43_fw_header
*hdr
;
1952 struct b43_firmware
*fw
= &dev
->fw
;
1953 const struct b43_iv
*ivals
;
1957 hdr
= (const struct b43_fw_header
*)(fw
->initvals
.data
->data
);
1958 ivals
= (const struct b43_iv
*)(fw
->initvals
.data
->data
+ hdr_len
);
1959 count
= be32_to_cpu(hdr
->size
);
1960 err
= b43_write_initvals(dev
, ivals
, count
,
1961 fw
->initvals
.data
->size
- hdr_len
);
1964 if (fw
->initvals_band
.data
) {
1965 hdr
= (const struct b43_fw_header
*)(fw
->initvals_band
.data
->data
);
1966 ivals
= (const struct b43_iv
*)(fw
->initvals_band
.data
->data
+ hdr_len
);
1967 count
= be32_to_cpu(hdr
->size
);
1968 err
= b43_write_initvals(dev
, ivals
, count
,
1969 fw
->initvals_band
.data
->size
- hdr_len
);
1978 /* Initialize the GPIOs
1979 * http://bcm-specs.sipsolutions.net/GPIO
1981 static int b43_gpio_init(struct b43_wldev
*dev
)
1983 struct ssb_bus
*bus
= dev
->dev
->bus
;
1984 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
1987 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
1988 & ~B43_MACCTL_GPOUTSMSK
);
1990 b43_write16(dev
, B43_MMIO_GPIO_MASK
, b43_read16(dev
, B43_MMIO_GPIO_MASK
)
1995 if (dev
->dev
->bus
->chip_id
== 0x4301) {
1999 if (0 /* FIXME: conditional unknown */ ) {
2000 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
2001 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2006 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_PACTRL
) {
2007 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
2008 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2013 if (dev
->dev
->id
.revision
>= 2)
2014 mask
|= 0x0010; /* FIXME: This is redundant. */
2016 #ifdef CONFIG_SSB_DRIVER_PCICORE
2017 pcidev
= bus
->pcicore
.dev
;
2019 gpiodev
= bus
->chipco
.dev
? : pcidev
;
2022 ssb_write32(gpiodev
, B43_GPIO_CONTROL
,
2023 (ssb_read32(gpiodev
, B43_GPIO_CONTROL
)
2029 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2030 static void b43_gpio_cleanup(struct b43_wldev
*dev
)
2032 struct ssb_bus
*bus
= dev
->dev
->bus
;
2033 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
2035 #ifdef CONFIG_SSB_DRIVER_PCICORE
2036 pcidev
= bus
->pcicore
.dev
;
2038 gpiodev
= bus
->chipco
.dev
? : pcidev
;
2041 ssb_write32(gpiodev
, B43_GPIO_CONTROL
, 0);
2044 /* http://bcm-specs.sipsolutions.net/EnableMac */
2045 void b43_mac_enable(struct b43_wldev
*dev
)
2047 dev
->mac_suspended
--;
2048 B43_WARN_ON(dev
->mac_suspended
< 0);
2049 B43_WARN_ON(irqs_disabled());
2050 if (dev
->mac_suspended
== 0) {
2051 b43_write32(dev
, B43_MMIO_MACCTL
,
2052 b43_read32(dev
, B43_MMIO_MACCTL
)
2053 | B43_MACCTL_ENABLED
);
2054 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
,
2055 B43_IRQ_MAC_SUSPENDED
);
2057 b43_read32(dev
, B43_MMIO_MACCTL
);
2058 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2059 b43_power_saving_ctl_bits(dev
, 0);
2061 /* Re-enable IRQs. */
2062 spin_lock_irq(&dev
->wl
->irq_lock
);
2063 b43_interrupt_enable(dev
, dev
->irq_savedstate
);
2064 spin_unlock_irq(&dev
->wl
->irq_lock
);
2068 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2069 void b43_mac_suspend(struct b43_wldev
*dev
)
2075 B43_WARN_ON(irqs_disabled());
2076 B43_WARN_ON(dev
->mac_suspended
< 0);
2078 if (dev
->mac_suspended
== 0) {
2079 /* Mask IRQs before suspending MAC. Otherwise
2080 * the MAC stays busy and won't suspend. */
2081 spin_lock_irq(&dev
->wl
->irq_lock
);
2082 tmp
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
2083 spin_unlock_irq(&dev
->wl
->irq_lock
);
2084 b43_synchronize_irq(dev
);
2085 dev
->irq_savedstate
= tmp
;
2087 b43_power_saving_ctl_bits(dev
, B43_PS_AWAKE
);
2088 b43_write32(dev
, B43_MMIO_MACCTL
,
2089 b43_read32(dev
, B43_MMIO_MACCTL
)
2090 & ~B43_MACCTL_ENABLED
);
2091 /* force pci to flush the write */
2092 b43_read32(dev
, B43_MMIO_MACCTL
);
2093 for (i
= 40; i
; i
--) {
2094 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2095 if (tmp
& B43_IRQ_MAC_SUSPENDED
)
2099 b43err(dev
->wl
, "MAC suspend failed\n");
2102 dev
->mac_suspended
++;
2105 static void b43_adjust_opmode(struct b43_wldev
*dev
)
2107 struct b43_wl
*wl
= dev
->wl
;
2111 ctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2112 /* Reset status to STA infrastructure mode. */
2113 ctl
&= ~B43_MACCTL_AP
;
2114 ctl
&= ~B43_MACCTL_KEEP_CTL
;
2115 ctl
&= ~B43_MACCTL_KEEP_BADPLCP
;
2116 ctl
&= ~B43_MACCTL_KEEP_BAD
;
2117 ctl
&= ~B43_MACCTL_PROMISC
;
2118 ctl
&= ~B43_MACCTL_BEACPROMISC
;
2119 ctl
|= B43_MACCTL_INFRA
;
2121 if (b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
))
2122 ctl
|= B43_MACCTL_AP
;
2123 else if (b43_is_mode(wl
, IEEE80211_IF_TYPE_IBSS
))
2124 ctl
&= ~B43_MACCTL_INFRA
;
2126 if (wl
->filter_flags
& FIF_CONTROL
)
2127 ctl
|= B43_MACCTL_KEEP_CTL
;
2128 if (wl
->filter_flags
& FIF_FCSFAIL
)
2129 ctl
|= B43_MACCTL_KEEP_BAD
;
2130 if (wl
->filter_flags
& FIF_PLCPFAIL
)
2131 ctl
|= B43_MACCTL_KEEP_BADPLCP
;
2132 if (wl
->filter_flags
& FIF_PROMISC_IN_BSS
)
2133 ctl
|= B43_MACCTL_PROMISC
;
2134 if (wl
->filter_flags
& FIF_BCN_PRBRESP_PROMISC
)
2135 ctl
|= B43_MACCTL_BEACPROMISC
;
2137 /* Workaround: On old hardware the HW-MAC-address-filter
2138 * doesn't work properly, so always run promisc in filter
2139 * it in software. */
2140 if (dev
->dev
->id
.revision
<= 4)
2141 ctl
|= B43_MACCTL_PROMISC
;
2143 b43_write32(dev
, B43_MMIO_MACCTL
, ctl
);
2146 if ((ctl
& B43_MACCTL_INFRA
) && !(ctl
& B43_MACCTL_AP
)) {
2147 if (dev
->dev
->bus
->chip_id
== 0x4306 &&
2148 dev
->dev
->bus
->chip_rev
== 3)
2153 b43_write16(dev
, 0x612, cfp_pretbtt
);
2156 static void b43_rate_memory_write(struct b43_wldev
*dev
, u16 rate
, int is_ofdm
)
2162 offset
+= (b43_plcp_get_ratecode_ofdm(rate
) & 0x000F) * 2;
2165 offset
+= (b43_plcp_get_ratecode_cck(rate
) & 0x000F) * 2;
2167 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ 0x20,
2168 b43_shm_read16(dev
, B43_SHM_SHARED
, offset
));
2171 static void b43_rate_memory_init(struct b43_wldev
*dev
)
2173 switch (dev
->phy
.type
) {
2177 b43_rate_memory_write(dev
, B43_OFDM_RATE_6MB
, 1);
2178 b43_rate_memory_write(dev
, B43_OFDM_RATE_12MB
, 1);
2179 b43_rate_memory_write(dev
, B43_OFDM_RATE_18MB
, 1);
2180 b43_rate_memory_write(dev
, B43_OFDM_RATE_24MB
, 1);
2181 b43_rate_memory_write(dev
, B43_OFDM_RATE_36MB
, 1);
2182 b43_rate_memory_write(dev
, B43_OFDM_RATE_48MB
, 1);
2183 b43_rate_memory_write(dev
, B43_OFDM_RATE_54MB
, 1);
2184 if (dev
->phy
.type
== B43_PHYTYPE_A
)
2188 b43_rate_memory_write(dev
, B43_CCK_RATE_1MB
, 0);
2189 b43_rate_memory_write(dev
, B43_CCK_RATE_2MB
, 0);
2190 b43_rate_memory_write(dev
, B43_CCK_RATE_5MB
, 0);
2191 b43_rate_memory_write(dev
, B43_CCK_RATE_11MB
, 0);
2198 /* Set the TX-Antenna for management frames sent by firmware. */
2199 static void b43_mgmtframe_txantenna(struct b43_wldev
*dev
, int antenna
)
2206 ant
|= B43_TXH_PHY_ANT0
;
2209 ant
|= B43_TXH_PHY_ANT1
;
2212 ant
|= B43_TXH_PHY_ANT2
;
2215 ant
|= B43_TXH_PHY_ANT3
;
2217 case B43_ANTENNA_AUTO
:
2218 ant
|= B43_TXH_PHY_ANT01AUTO
;
2224 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2227 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
);
2228 tmp
= (tmp
& ~B43_TXH_PHY_ANT
) | ant
;
2229 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
, tmp
);
2231 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
);
2232 tmp
= (tmp
& ~B43_TXH_PHY_ANT
) | ant
;
2233 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
, tmp
);
2234 /* For Probe Resposes */
2235 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
);
2236 tmp
= (tmp
& ~B43_TXH_PHY_ANT
) | ant
;
2237 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
, tmp
);
2240 /* This is the opposite of b43_chip_init() */
2241 static void b43_chip_exit(struct b43_wldev
*dev
)
2243 b43_radio_turn_off(dev
, 1);
2244 b43_gpio_cleanup(dev
);
2245 /* firmware is released later */
2248 /* Initialize the chip
2249 * http://bcm-specs.sipsolutions.net/ChipInit
2251 static int b43_chip_init(struct b43_wldev
*dev
)
2253 struct b43_phy
*phy
= &dev
->phy
;
2255 u32 value32
, macctl
;
2258 /* Initialize the MAC control */
2259 macctl
= B43_MACCTL_IHR_ENABLED
| B43_MACCTL_SHM_ENABLED
;
2261 macctl
|= B43_MACCTL_GMODE
;
2262 macctl
|= B43_MACCTL_INFRA
;
2263 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2265 err
= b43_request_firmware(dev
);
2268 err
= b43_upload_microcode(dev
);
2270 goto out
; /* firmware is released later */
2272 err
= b43_gpio_init(dev
);
2274 goto out
; /* firmware is released later */
2276 err
= b43_upload_initvals(dev
);
2278 goto err_gpio_clean
;
2279 b43_radio_turn_on(dev
);
2281 b43_write16(dev
, 0x03E6, 0x0000);
2282 err
= b43_phy_init(dev
);
2286 /* Select initial Interference Mitigation. */
2287 tmp
= phy
->interfmode
;
2288 phy
->interfmode
= B43_INTERFMODE_NONE
;
2289 b43_radio_set_interference_mitigation(dev
, tmp
);
2291 b43_set_rx_antenna(dev
, B43_ANTENNA_DEFAULT
);
2292 b43_mgmtframe_txantenna(dev
, B43_ANTENNA_DEFAULT
);
2294 if (phy
->type
== B43_PHYTYPE_B
) {
2295 value16
= b43_read16(dev
, 0x005E);
2297 b43_write16(dev
, 0x005E, value16
);
2299 b43_write32(dev
, 0x0100, 0x01000000);
2300 if (dev
->dev
->id
.revision
< 5)
2301 b43_write32(dev
, 0x010C, 0x01000000);
2303 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2304 & ~B43_MACCTL_INFRA
);
2305 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2306 | B43_MACCTL_INFRA
);
2308 /* Probe Response Timeout value */
2309 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2310 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0074, 0x0000);
2312 /* Initially set the wireless operation mode. */
2313 b43_adjust_opmode(dev
);
2315 if (dev
->dev
->id
.revision
< 3) {
2316 b43_write16(dev
, 0x060E, 0x0000);
2317 b43_write16(dev
, 0x0610, 0x8000);
2318 b43_write16(dev
, 0x0604, 0x0000);
2319 b43_write16(dev
, 0x0606, 0x0200);
2321 b43_write32(dev
, 0x0188, 0x80000000);
2322 b43_write32(dev
, 0x018C, 0x02000000);
2324 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, 0x00004000);
2325 b43_write32(dev
, B43_MMIO_DMA0_IRQ_MASK
, 0x0001DC00);
2326 b43_write32(dev
, B43_MMIO_DMA1_IRQ_MASK
, 0x0000DC00);
2327 b43_write32(dev
, B43_MMIO_DMA2_IRQ_MASK
, 0x0000DC00);
2328 b43_write32(dev
, B43_MMIO_DMA3_IRQ_MASK
, 0x0001DC00);
2329 b43_write32(dev
, B43_MMIO_DMA4_IRQ_MASK
, 0x0000DC00);
2330 b43_write32(dev
, B43_MMIO_DMA5_IRQ_MASK
, 0x0000DC00);
2332 value32
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
2333 value32
|= 0x00100000;
2334 ssb_write32(dev
->dev
, SSB_TMSLOW
, value32
);
2336 b43_write16(dev
, B43_MMIO_POWERUP_DELAY
,
2337 dev
->dev
->bus
->chipco
.fast_pwrup_delay
);
2340 b43dbg(dev
->wl
, "Chip initialized\n");
2345 b43_radio_turn_off(dev
, 1);
2347 b43_gpio_cleanup(dev
);
2351 static void b43_periodic_every120sec(struct b43_wldev
*dev
)
2353 struct b43_phy
*phy
= &dev
->phy
;
2355 if (phy
->type
!= B43_PHYTYPE_G
|| phy
->rev
< 2)
2358 b43_mac_suspend(dev
);
2359 b43_lo_g_measure(dev
);
2360 b43_mac_enable(dev
);
2361 if (b43_has_hardware_pctl(phy
))
2362 b43_lo_g_ctl_mark_all_unused(dev
);
2365 static void b43_periodic_every60sec(struct b43_wldev
*dev
)
2367 struct b43_phy
*phy
= &dev
->phy
;
2369 if (phy
->type
!= B43_PHYTYPE_G
)
2371 if (!b43_has_hardware_pctl(phy
))
2372 b43_lo_g_ctl_mark_all_unused(dev
);
2373 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_RSSI
) {
2374 b43_mac_suspend(dev
);
2375 b43_calc_nrssi_slope(dev
);
2376 if ((phy
->radio_ver
== 0x2050) && (phy
->radio_rev
== 8)) {
2377 u8 old_chan
= phy
->channel
;
2379 /* VCO Calibration */
2381 b43_radio_selectchannel(dev
, 1, 0);
2383 b43_radio_selectchannel(dev
, 13, 0);
2384 b43_radio_selectchannel(dev
, old_chan
, 0);
2386 b43_mac_enable(dev
);
2390 static void b43_periodic_every30sec(struct b43_wldev
*dev
)
2392 /* Update device statistics. */
2393 b43_calculate_link_quality(dev
);
2396 static void b43_periodic_every15sec(struct b43_wldev
*dev
)
2398 struct b43_phy
*phy
= &dev
->phy
;
2400 if (phy
->type
== B43_PHYTYPE_G
) {
2401 //TODO: update_aci_moving_average
2402 if (phy
->aci_enable
&& phy
->aci_wlan_automatic
) {
2403 b43_mac_suspend(dev
);
2404 if (!phy
->aci_enable
&& 1 /*TODO: not scanning? */ ) {
2405 if (0 /*TODO: bunch of conditions */ ) {
2406 b43_radio_set_interference_mitigation
2407 (dev
, B43_INTERFMODE_MANUALWLAN
);
2409 } else if (1 /*TODO*/) {
2411 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2412 b43_radio_set_interference_mitigation(dev,
2413 B43_INTERFMODE_NONE);
2417 b43_mac_enable(dev
);
2418 } else if (phy
->interfmode
== B43_INTERFMODE_NONWLAN
&&
2420 //TODO: implement rev1 workaround
2423 b43_phy_xmitpower(dev
); //FIXME: unless scanning?
2424 //TODO for APHY (temperature?)
2426 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
2430 static void do_periodic_work(struct b43_wldev
*dev
)
2434 state
= dev
->periodic_state
;
2436 b43_periodic_every120sec(dev
);
2438 b43_periodic_every60sec(dev
);
2440 b43_periodic_every30sec(dev
);
2441 b43_periodic_every15sec(dev
);
2444 /* Periodic work locking policy:
2445 * The whole periodic work handler is protected by
2446 * wl->mutex. If another lock is needed somewhere in the
2447 * pwork callchain, it's aquired in-place, where it's needed.
2449 static void b43_periodic_work_handler(struct work_struct
*work
)
2451 struct b43_wldev
*dev
= container_of(work
, struct b43_wldev
,
2452 periodic_work
.work
);
2453 struct b43_wl
*wl
= dev
->wl
;
2454 unsigned long delay
;
2456 mutex_lock(&wl
->mutex
);
2458 if (unlikely(b43_status(dev
) != B43_STAT_STARTED
))
2460 if (b43_debug(dev
, B43_DBG_PWORK_STOP
))
2463 do_periodic_work(dev
);
2465 dev
->periodic_state
++;
2467 if (b43_debug(dev
, B43_DBG_PWORK_FAST
))
2468 delay
= msecs_to_jiffies(50);
2470 delay
= round_jiffies_relative(HZ
* 15);
2471 queue_delayed_work(wl
->hw
->workqueue
, &dev
->periodic_work
, delay
);
2473 mutex_unlock(&wl
->mutex
);
2476 static void b43_periodic_tasks_setup(struct b43_wldev
*dev
)
2478 struct delayed_work
*work
= &dev
->periodic_work
;
2480 dev
->periodic_state
= 0;
2481 INIT_DELAYED_WORK(work
, b43_periodic_work_handler
);
2482 queue_delayed_work(dev
->wl
->hw
->workqueue
, work
, 0);
2485 /* Check if communication with the device works correctly. */
2486 static int b43_validate_chipaccess(struct b43_wldev
*dev
)
2490 backup
= b43_shm_read32(dev
, B43_SHM_SHARED
, 0);
2492 /* Check for read/write and endianness problems. */
2493 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0x55AAAA55);
2494 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0x55AAAA55)
2496 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0xAA5555AA);
2497 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0xAA5555AA)
2500 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, backup
);
2502 if ((dev
->dev
->id
.revision
>= 3) && (dev
->dev
->id
.revision
<= 10)) {
2503 /* The 32bit register shadows the two 16bit registers
2504 * with update sideeffects. Validate this. */
2505 b43_write16(dev
, B43_MMIO_TSF_CFP_START
, 0xAAAA);
2506 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0xCCCCBBBB);
2507 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_LOW
) != 0xBBBB)
2509 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_HIGH
) != 0xCCCC)
2512 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0);
2514 v
= b43_read32(dev
, B43_MMIO_MACCTL
);
2515 v
|= B43_MACCTL_GMODE
;
2516 if (v
!= (B43_MACCTL_GMODE
| B43_MACCTL_IHR_ENABLED
))
2521 b43err(dev
->wl
, "Failed to validate the chipaccess\n");
2525 static void b43_security_init(struct b43_wldev
*dev
)
2527 dev
->max_nr_keys
= (dev
->dev
->id
.revision
>= 5) ? 58 : 20;
2528 B43_WARN_ON(dev
->max_nr_keys
> ARRAY_SIZE(dev
->key
));
2529 dev
->ktp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_KTP
);
2530 /* KTP is a word address, but we address SHM bytewise.
2531 * So multiply by two.
2534 if (dev
->dev
->id
.revision
>= 5) {
2535 /* Number of RCMTA address slots */
2536 b43_write16(dev
, B43_MMIO_RCMTA_COUNT
, dev
->max_nr_keys
- 8);
2538 b43_clear_keys(dev
);
2541 static int b43_rng_read(struct hwrng
*rng
, u32
* data
)
2543 struct b43_wl
*wl
= (struct b43_wl
*)rng
->priv
;
2544 unsigned long flags
;
2546 /* Don't take wl->mutex here, as it could deadlock with
2547 * hwrng internal locking. It's not needed to take
2548 * wl->mutex here, anyway. */
2550 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2551 *data
= b43_read16(wl
->current_dev
, B43_MMIO_RNG
);
2552 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2554 return (sizeof(u16
));
2557 static void b43_rng_exit(struct b43_wl
*wl
)
2559 if (wl
->rng_initialized
)
2560 hwrng_unregister(&wl
->rng
);
2563 static int b43_rng_init(struct b43_wl
*wl
)
2567 snprintf(wl
->rng_name
, ARRAY_SIZE(wl
->rng_name
),
2568 "%s_%s", KBUILD_MODNAME
, wiphy_name(wl
->hw
->wiphy
));
2569 wl
->rng
.name
= wl
->rng_name
;
2570 wl
->rng
.data_read
= b43_rng_read
;
2571 wl
->rng
.priv
= (unsigned long)wl
;
2572 wl
->rng_initialized
= 1;
2573 err
= hwrng_register(&wl
->rng
);
2575 wl
->rng_initialized
= 0;
2576 b43err(wl
, "Failed to register the random "
2577 "number generator (%d)\n", err
);
2583 static int b43_op_tx(struct ieee80211_hw
*hw
,
2584 struct sk_buff
*skb
,
2585 struct ieee80211_tx_control
*ctl
)
2587 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2588 struct b43_wldev
*dev
= wl
->current_dev
;
2593 if (unlikely(b43_status(dev
) < B43_STAT_STARTED
))
2595 /* DMA-TX is done without a global lock. */
2596 err
= b43_dma_tx(dev
, skb
, ctl
);
2599 return NETDEV_TX_BUSY
;
2600 return NETDEV_TX_OK
;
2603 static int b43_op_conf_tx(struct ieee80211_hw
*hw
,
2605 const struct ieee80211_tx_queue_params
*params
)
2610 static int b43_op_get_tx_stats(struct ieee80211_hw
*hw
,
2611 struct ieee80211_tx_queue_stats
*stats
)
2613 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2614 struct b43_wldev
*dev
= wl
->current_dev
;
2615 unsigned long flags
;
2620 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2621 if (likely(b43_status(dev
) >= B43_STAT_STARTED
)) {
2622 b43_dma_get_tx_stats(dev
, stats
);
2625 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2630 static int b43_op_get_stats(struct ieee80211_hw
*hw
,
2631 struct ieee80211_low_level_stats
*stats
)
2633 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2634 unsigned long flags
;
2636 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2637 memcpy(stats
, &wl
->ieee_stats
, sizeof(*stats
));
2638 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2643 static const char *phymode_to_string(unsigned int phymode
)
2658 static int find_wldev_for_phymode(struct b43_wl
*wl
,
2659 unsigned int phymode
,
2660 struct b43_wldev
**dev
, bool * gmode
)
2662 struct b43_wldev
*d
;
2664 list_for_each_entry(d
, &wl
->devlist
, list
) {
2665 if (d
->phy
.possible_phymodes
& phymode
) {
2666 /* Ok, this device supports the PHY-mode.
2667 * Now figure out how the gmode bit has to be
2668 * set to support it. */
2669 if (phymode
== B43_PHYMODE_A
)
2682 static void b43_put_phy_into_reset(struct b43_wldev
*dev
)
2684 struct ssb_device
*sdev
= dev
->dev
;
2687 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
2688 tmslow
&= ~B43_TMSLOW_GMODE
;
2689 tmslow
|= B43_TMSLOW_PHYRESET
;
2690 tmslow
|= SSB_TMSLOW_FGC
;
2691 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
2694 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
2695 tmslow
&= ~SSB_TMSLOW_FGC
;
2696 tmslow
|= B43_TMSLOW_PHYRESET
;
2697 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
2701 /* Expects wl->mutex locked */
2702 static int b43_switch_phymode(struct b43_wl
*wl
, unsigned int new_mode
)
2704 struct b43_wldev
*up_dev
;
2705 struct b43_wldev
*down_dev
;
2710 err
= find_wldev_for_phymode(wl
, new_mode
, &up_dev
, &gmode
);
2712 b43err(wl
, "Could not find a device for %s-PHY mode\n",
2713 phymode_to_string(new_mode
));
2716 if ((up_dev
== wl
->current_dev
) &&
2717 (!!wl
->current_dev
->phy
.gmode
== !!gmode
)) {
2718 /* This device is already running. */
2721 b43dbg(wl
, "Reconfiguring PHYmode to %s-PHY\n",
2722 phymode_to_string(new_mode
));
2723 down_dev
= wl
->current_dev
;
2725 prev_status
= b43_status(down_dev
);
2726 /* Shutdown the currently running core. */
2727 if (prev_status
>= B43_STAT_STARTED
)
2728 b43_wireless_core_stop(down_dev
);
2729 if (prev_status
>= B43_STAT_INITIALIZED
)
2730 b43_wireless_core_exit(down_dev
);
2732 if (down_dev
!= up_dev
) {
2733 /* We switch to a different core, so we put PHY into
2734 * RESET on the old core. */
2735 b43_put_phy_into_reset(down_dev
);
2738 /* Now start the new core. */
2739 up_dev
->phy
.gmode
= gmode
;
2740 if (prev_status
>= B43_STAT_INITIALIZED
) {
2741 err
= b43_wireless_core_init(up_dev
);
2743 b43err(wl
, "Fatal: Could not initialize device for "
2744 "newly selected %s-PHY mode\n",
2745 phymode_to_string(new_mode
));
2749 if (prev_status
>= B43_STAT_STARTED
) {
2750 err
= b43_wireless_core_start(up_dev
);
2752 b43err(wl
, "Fatal: Coult not start device for "
2753 "newly selected %s-PHY mode\n",
2754 phymode_to_string(new_mode
));
2755 b43_wireless_core_exit(up_dev
);
2759 B43_WARN_ON(b43_status(up_dev
) != prev_status
);
2761 wl
->current_dev
= up_dev
;
2765 /* Whoops, failed to init the new core. No core is operating now. */
2766 wl
->current_dev
= NULL
;
2770 /* Check if the use of the antenna that ieee80211 told us to
2771 * use is possible. This will fall back to DEFAULT.
2772 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2773 u8
b43_ieee80211_antenna_sanitize(struct b43_wldev
*dev
,
2778 if (antenna_nr
== 0) {
2779 /* Zero means "use default antenna". That's always OK. */
2783 /* Get the mask of available antennas. */
2785 antenna_mask
= dev
->dev
->bus
->sprom
.ant_available_bg
;
2787 antenna_mask
= dev
->dev
->bus
->sprom
.ant_available_a
;
2789 if (!(antenna_mask
& (1 << (antenna_nr
- 1)))) {
2790 /* This antenna is not available. Fall back to default. */
2797 static int b43_antenna_from_ieee80211(struct b43_wldev
*dev
, u8 antenna
)
2799 antenna
= b43_ieee80211_antenna_sanitize(dev
, antenna
);
2801 case 0: /* default/diversity */
2802 return B43_ANTENNA_DEFAULT
;
2803 case 1: /* Antenna 0 */
2804 return B43_ANTENNA0
;
2805 case 2: /* Antenna 1 */
2806 return B43_ANTENNA1
;
2807 case 3: /* Antenna 2 */
2808 return B43_ANTENNA2
;
2809 case 4: /* Antenna 3 */
2810 return B43_ANTENNA3
;
2812 return B43_ANTENNA_DEFAULT
;
2816 static int b43_op_config(struct ieee80211_hw
*hw
, struct ieee80211_conf
*conf
)
2818 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2819 struct b43_wldev
*dev
;
2820 struct b43_phy
*phy
;
2821 unsigned long flags
;
2822 unsigned int new_phymode
= 0xFFFF;
2827 mutex_lock(&wl
->mutex
);
2829 /* Switch the PHY mode (if necessary). */
2830 switch (conf
->phymode
) {
2831 case MODE_IEEE80211A
:
2832 new_phymode
= B43_PHYMODE_A
;
2834 case MODE_IEEE80211B
:
2835 new_phymode
= B43_PHYMODE_B
;
2837 case MODE_IEEE80211G
:
2838 new_phymode
= B43_PHYMODE_G
;
2843 err
= b43_switch_phymode(wl
, new_phymode
);
2845 goto out_unlock_mutex
;
2846 dev
= wl
->current_dev
;
2849 /* Disable IRQs while reconfiguring the device.
2850 * This makes it possible to drop the spinlock throughout
2851 * the reconfiguration process. */
2852 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2853 if (b43_status(dev
) < B43_STAT_STARTED
) {
2854 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2855 goto out_unlock_mutex
;
2857 savedirqs
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
2858 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2859 b43_synchronize_irq(dev
);
2861 /* Switch to the requested channel.
2862 * The firmware takes care of races with the TX handler. */
2863 if (conf
->channel_val
!= phy
->channel
)
2864 b43_radio_selectchannel(dev
, conf
->channel_val
, 0);
2866 /* Enable/Disable ShortSlot timing. */
2867 if ((!!(conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
)) !=
2869 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
2870 if (conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
)
2871 b43_short_slot_timing_enable(dev
);
2873 b43_short_slot_timing_disable(dev
);
2876 dev
->wl
->radiotap_enabled
= !!(conf
->flags
& IEEE80211_CONF_RADIOTAP
);
2878 /* Adjust the desired TX power level. */
2879 if (conf
->power_level
!= 0) {
2880 if (conf
->power_level
!= phy
->power_level
) {
2881 phy
->power_level
= conf
->power_level
;
2882 b43_phy_xmitpower(dev
);
2886 /* Antennas for RX and management frame TX. */
2887 antenna
= b43_antenna_from_ieee80211(dev
, conf
->antenna_sel_tx
);
2888 b43_mgmtframe_txantenna(dev
, antenna
);
2889 antenna
= b43_antenna_from_ieee80211(dev
, conf
->antenna_sel_rx
);
2890 b43_set_rx_antenna(dev
, antenna
);
2892 /* Update templates for AP mode. */
2893 if (b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
))
2894 b43_set_beacon_int(dev
, conf
->beacon_int
);
2896 if (!!conf
->radio_enabled
!= phy
->radio_on
) {
2897 if (conf
->radio_enabled
) {
2898 b43_radio_turn_on(dev
);
2899 b43info(dev
->wl
, "Radio turned on by software\n");
2900 if (!dev
->radio_hw_enable
) {
2901 b43info(dev
->wl
, "The hardware RF-kill button "
2902 "still turns the radio physically off. "
2903 "Press the button to turn it on.\n");
2906 b43_radio_turn_off(dev
, 0);
2907 b43info(dev
->wl
, "Radio turned off by software\n");
2911 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2912 b43_interrupt_enable(dev
, savedirqs
);
2914 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2916 mutex_unlock(&wl
->mutex
);
2921 static int b43_op_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
2922 const u8
*local_addr
, const u8
*addr
,
2923 struct ieee80211_key_conf
*key
)
2925 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2926 struct b43_wldev
*dev
;
2927 unsigned long flags
;
2931 DECLARE_MAC_BUF(mac
);
2933 if (modparam_nohwcrypt
)
2934 return -ENOSPC
; /* User disabled HW-crypto */
2936 mutex_lock(&wl
->mutex
);
2937 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2939 dev
= wl
->current_dev
;
2941 if (!dev
|| b43_status(dev
) < B43_STAT_INITIALIZED
)
2947 if (key
->keylen
== 5)
2948 algorithm
= B43_SEC_ALGO_WEP40
;
2950 algorithm
= B43_SEC_ALGO_WEP104
;
2953 algorithm
= B43_SEC_ALGO_TKIP
;
2956 algorithm
= B43_SEC_ALGO_AES
;
2962 index
= (u8
) (key
->keyidx
);
2968 if (algorithm
== B43_SEC_ALGO_TKIP
) {
2969 /* FIXME: No TKIP hardware encryption for now. */
2974 if (is_broadcast_ether_addr(addr
)) {
2975 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2976 err
= b43_key_write(dev
, index
, algorithm
,
2977 key
->key
, key
->keylen
, NULL
, key
);
2980 * either pairwise key or address is 00:00:00:00:00:00
2981 * for transmit-only keys
2983 err
= b43_key_write(dev
, -1, algorithm
,
2984 key
->key
, key
->keylen
, addr
, key
);
2989 if (algorithm
== B43_SEC_ALGO_WEP40
||
2990 algorithm
== B43_SEC_ALGO_WEP104
) {
2991 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_USEDEFKEYS
);
2994 b43_hf_read(dev
) & ~B43_HF_USEDEFKEYS
);
2996 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
2999 err
= b43_key_clear(dev
, key
->hw_key_idx
);
3008 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3009 mutex_unlock(&wl
->mutex
);
3011 b43dbg(wl
, "%s hardware based encryption for keyidx: %d, "
3013 cmd
== SET_KEY
? "Using" : "Disabling", key
->keyidx
,
3014 print_mac(mac
, addr
));
3019 static void b43_op_configure_filter(struct ieee80211_hw
*hw
,
3020 unsigned int changed
, unsigned int *fflags
,
3021 int mc_count
, struct dev_addr_list
*mc_list
)
3023 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3024 struct b43_wldev
*dev
= wl
->current_dev
;
3025 unsigned long flags
;
3032 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3033 *fflags
&= FIF_PROMISC_IN_BSS
|
3039 FIF_BCN_PRBRESP_PROMISC
;
3041 changed
&= FIF_PROMISC_IN_BSS
|
3047 FIF_BCN_PRBRESP_PROMISC
;
3049 wl
->filter_flags
= *fflags
;
3051 if (changed
&& b43_status(dev
) >= B43_STAT_INITIALIZED
)
3052 b43_adjust_opmode(dev
);
3053 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3056 static int b43_op_config_interface(struct ieee80211_hw
*hw
,
3057 struct ieee80211_vif
*vif
,
3058 struct ieee80211_if_conf
*conf
)
3060 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3061 struct b43_wldev
*dev
= wl
->current_dev
;
3062 unsigned long flags
;
3066 mutex_lock(&wl
->mutex
);
3067 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3068 B43_WARN_ON(wl
->vif
!= vif
);
3070 memcpy(wl
->bssid
, conf
->bssid
, ETH_ALEN
);
3072 memset(wl
->bssid
, 0, ETH_ALEN
);
3073 if (b43_status(dev
) >= B43_STAT_INITIALIZED
) {
3074 if (b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
)) {
3075 B43_WARN_ON(conf
->type
!= IEEE80211_IF_TYPE_AP
);
3076 b43_set_ssid(dev
, conf
->ssid
, conf
->ssid_len
);
3078 b43_update_templates(wl
, conf
->beacon
);
3080 b43_write_mac_bssid_templates(dev
);
3082 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3083 mutex_unlock(&wl
->mutex
);
3088 /* Locking: wl->mutex */
3089 static void b43_wireless_core_stop(struct b43_wldev
*dev
)
3091 struct b43_wl
*wl
= dev
->wl
;
3092 unsigned long flags
;
3094 if (b43_status(dev
) < B43_STAT_STARTED
)
3097 /* Disable and sync interrupts. We must do this before than
3098 * setting the status to INITIALIZED, as the interrupt handler
3099 * won't care about IRQs then. */
3100 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3101 dev
->irq_savedstate
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
3102 b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
); /* flush */
3103 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3104 b43_synchronize_irq(dev
);
3106 b43_set_status(dev
, B43_STAT_INITIALIZED
);
3108 mutex_unlock(&wl
->mutex
);
3109 /* Must unlock as it would otherwise deadlock. No races here.
3110 * Cancel the possibly running self-rearming periodic work. */
3111 cancel_delayed_work_sync(&dev
->periodic_work
);
3112 mutex_lock(&wl
->mutex
);
3114 ieee80211_stop_queues(wl
->hw
); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3116 b43_mac_suspend(dev
);
3117 free_irq(dev
->dev
->irq
, dev
);
3118 b43dbg(wl
, "Wireless interface stopped\n");
3121 /* Locking: wl->mutex */
3122 static int b43_wireless_core_start(struct b43_wldev
*dev
)
3126 B43_WARN_ON(b43_status(dev
) != B43_STAT_INITIALIZED
);
3128 drain_txstatus_queue(dev
);
3129 err
= request_irq(dev
->dev
->irq
, b43_interrupt_handler
,
3130 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
3132 b43err(dev
->wl
, "Cannot request IRQ-%d\n", dev
->dev
->irq
);
3136 /* We are ready to run. */
3137 b43_set_status(dev
, B43_STAT_STARTED
);
3139 /* Start data flow (TX/RX). */
3140 b43_mac_enable(dev
);
3141 b43_interrupt_enable(dev
, dev
->irq_savedstate
);
3142 ieee80211_start_queues(dev
->wl
->hw
);
3144 /* Start maintainance work */
3145 b43_periodic_tasks_setup(dev
);
3147 b43dbg(dev
->wl
, "Wireless interface started\n");
3152 /* Get PHY and RADIO versioning numbers */
3153 static int b43_phy_versioning(struct b43_wldev
*dev
)
3155 struct b43_phy
*phy
= &dev
->phy
;
3163 int unsupported
= 0;
3165 /* Get PHY versioning */
3166 tmp
= b43_read16(dev
, B43_MMIO_PHY_VER
);
3167 analog_type
= (tmp
& B43_PHYVER_ANALOG
) >> B43_PHYVER_ANALOG_SHIFT
;
3168 phy_type
= (tmp
& B43_PHYVER_TYPE
) >> B43_PHYVER_TYPE_SHIFT
;
3169 phy_rev
= (tmp
& B43_PHYVER_VERSION
);
3176 if (phy_rev
!= 2 && phy_rev
!= 4 && phy_rev
!= 6
3184 #ifdef CONFIG_B43_NPHY
3194 b43err(dev
->wl
, "FOUND UNSUPPORTED PHY "
3195 "(Analog %u, Type %u, Revision %u)\n",
3196 analog_type
, phy_type
, phy_rev
);
3199 b43dbg(dev
->wl
, "Found PHY: Analog %u, Type %u, Revision %u\n",
3200 analog_type
, phy_type
, phy_rev
);
3202 /* Get RADIO versioning */
3203 if (dev
->dev
->bus
->chip_id
== 0x4317) {
3204 if (dev
->dev
->bus
->chip_rev
== 0)
3206 else if (dev
->dev
->bus
->chip_rev
== 1)
3211 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, B43_RADIOCTL_ID
);
3212 tmp
= b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
3213 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, B43_RADIOCTL_ID
);
3214 tmp
|= (u32
)b43_read16(dev
, B43_MMIO_RADIO_DATA_HIGH
) << 16;
3216 radio_manuf
= (tmp
& 0x00000FFF);
3217 radio_ver
= (tmp
& 0x0FFFF000) >> 12;
3218 radio_rev
= (tmp
& 0xF0000000) >> 28;
3219 if (radio_manuf
!= 0x17F /* Broadcom */)
3223 if (radio_ver
!= 0x2060)
3227 if (radio_manuf
!= 0x17F)
3231 if ((radio_ver
& 0xFFF0) != 0x2050)
3235 if (radio_ver
!= 0x2050)
3239 if (radio_ver
!= 0x2055)
3246 b43err(dev
->wl
, "FOUND UNSUPPORTED RADIO "
3247 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3248 radio_manuf
, radio_ver
, radio_rev
);
3251 b43dbg(dev
->wl
, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3252 radio_manuf
, radio_ver
, radio_rev
);
3254 phy
->radio_manuf
= radio_manuf
;
3255 phy
->radio_ver
= radio_ver
;
3256 phy
->radio_rev
= radio_rev
;
3258 phy
->analog
= analog_type
;
3259 phy
->type
= phy_type
;
3265 static void setup_struct_phy_for_init(struct b43_wldev
*dev
,
3266 struct b43_phy
*phy
)
3268 struct b43_txpower_lo_control
*lo
;
3271 memset(phy
->minlowsig
, 0xFF, sizeof(phy
->minlowsig
));
3272 memset(phy
->minlowsigpos
, 0, sizeof(phy
->minlowsigpos
));
3274 phy
->aci_enable
= 0;
3275 phy
->aci_wlan_automatic
= 0;
3276 phy
->aci_hw_rssi
= 0;
3278 phy
->radio_off_context
.valid
= 0;
3280 lo
= phy
->lo_control
;
3282 memset(lo
, 0, sizeof(*(phy
->lo_control
)));
3286 phy
->max_lb_gain
= 0;
3287 phy
->trsw_rx_gain
= 0;
3288 phy
->txpwr_offset
= 0;
3291 phy
->nrssislope
= 0;
3292 for (i
= 0; i
< ARRAY_SIZE(phy
->nrssi
); i
++)
3293 phy
->nrssi
[i
] = -1000;
3294 for (i
= 0; i
< ARRAY_SIZE(phy
->nrssi_lt
); i
++)
3295 phy
->nrssi_lt
[i
] = i
;
3297 phy
->lofcal
= 0xFFFF;
3298 phy
->initval
= 0xFFFF;
3300 phy
->interfmode
= B43_INTERFMODE_NONE
;
3301 phy
->channel
= 0xFF;
3303 phy
->hardware_power_control
= !!modparam_hwpctl
;
3305 /* PHY TX errors counter. */
3306 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
3308 /* OFDM-table address caching. */
3309 phy
->ofdmtab_addr_direction
= B43_OFDMTAB_DIRECTION_UNKNOWN
;
3312 static void setup_struct_wldev_for_init(struct b43_wldev
*dev
)
3316 /* Assume the radio is enabled. If it's not enabled, the state will
3317 * immediately get fixed on the first periodic work run. */
3318 dev
->radio_hw_enable
= 1;
3321 memset(&dev
->stats
, 0, sizeof(dev
->stats
));
3323 setup_struct_phy_for_init(dev
, &dev
->phy
);
3325 /* IRQ related flags */
3326 dev
->irq_reason
= 0;
3327 memset(dev
->dma_reason
, 0, sizeof(dev
->dma_reason
));
3328 dev
->irq_savedstate
= B43_IRQ_MASKTEMPLATE
;
3330 dev
->mac_suspended
= 1;
3332 /* Noise calculation context */
3333 memset(&dev
->noisecalc
, 0, sizeof(dev
->noisecalc
));
3336 static void b43_bluetooth_coext_enable(struct b43_wldev
*dev
)
3338 struct ssb_sprom
*sprom
= &dev
->dev
->bus
->sprom
;
3341 if (!(sprom
->boardflags_lo
& B43_BFL_BTCOEXIST
))
3343 if (dev
->phy
.type
!= B43_PHYTYPE_B
&& !dev
->phy
.gmode
)
3346 hf
= b43_hf_read(dev
);
3347 if (sprom
->boardflags_lo
& B43_BFL_BTCMOD
)
3348 hf
|= B43_HF_BTCOEXALT
;
3350 hf
|= B43_HF_BTCOEX
;
3351 b43_hf_write(dev
, hf
);
3355 static void b43_bluetooth_coext_disable(struct b43_wldev
*dev
)
3359 static void b43_imcfglo_timeouts_workaround(struct b43_wldev
*dev
)
3361 #ifdef CONFIG_SSB_DRIVER_PCICORE
3362 struct ssb_bus
*bus
= dev
->dev
->bus
;
3365 if (bus
->pcicore
.dev
&&
3366 bus
->pcicore
.dev
->id
.coreid
== SSB_DEV_PCI
&&
3367 bus
->pcicore
.dev
->id
.revision
<= 5) {
3368 /* IMCFGLO timeouts workaround. */
3369 tmp
= ssb_read32(dev
->dev
, SSB_IMCFGLO
);
3370 tmp
&= ~SSB_IMCFGLO_REQTO
;
3371 tmp
&= ~SSB_IMCFGLO_SERTO
;
3372 switch (bus
->bustype
) {
3373 case SSB_BUSTYPE_PCI
:
3374 case SSB_BUSTYPE_PCMCIA
:
3377 case SSB_BUSTYPE_SSB
:
3381 ssb_write32(dev
->dev
, SSB_IMCFGLO
, tmp
);
3383 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3386 /* Write the short and long frame retry limit values. */
3387 static void b43_set_retry_limits(struct b43_wldev
*dev
,
3388 unsigned int short_retry
,
3389 unsigned int long_retry
)
3391 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3392 * the chip-internal counter. */
3393 short_retry
= min(short_retry
, (unsigned int)0xF);
3394 long_retry
= min(long_retry
, (unsigned int)0xF);
3396 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_SRLIMIT
,
3398 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_LRLIMIT
,
3402 /* Shutdown a wireless core */
3403 /* Locking: wl->mutex */
3404 static void b43_wireless_core_exit(struct b43_wldev
*dev
)
3406 struct b43_phy
*phy
= &dev
->phy
;
3409 B43_WARN_ON(b43_status(dev
) > B43_STAT_INITIALIZED
);
3410 if (b43_status(dev
) != B43_STAT_INITIALIZED
)
3412 b43_set_status(dev
, B43_STAT_UNINIT
);
3414 /* Stop the microcode PSM. */
3415 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
3416 macctl
&= ~B43_MACCTL_PSM_RUN
;
3417 macctl
|= B43_MACCTL_PSM_JMP0
;
3418 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
3421 b43_rng_exit(dev
->wl
);
3424 b43_radio_turn_off(dev
, 1);
3425 b43_switch_analog(dev
, 0);
3426 if (phy
->dyn_tssi_tbl
)
3427 kfree(phy
->tssi2dbm
);
3428 kfree(phy
->lo_control
);
3429 phy
->lo_control
= NULL
;
3430 if (dev
->wl
->current_beacon
) {
3431 dev_kfree_skb_any(dev
->wl
->current_beacon
);
3432 dev
->wl
->current_beacon
= NULL
;
3435 ssb_device_disable(dev
->dev
, 0);
3436 ssb_bus_may_powerdown(dev
->dev
->bus
);
3439 /* Initialize a wireless core */
3440 static int b43_wireless_core_init(struct b43_wldev
*dev
)
3442 struct b43_wl
*wl
= dev
->wl
;
3443 struct ssb_bus
*bus
= dev
->dev
->bus
;
3444 struct ssb_sprom
*sprom
= &bus
->sprom
;
3445 struct b43_phy
*phy
= &dev
->phy
;
3449 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
3451 err
= ssb_bus_powerup(bus
, 0);
3454 if (!ssb_device_is_enabled(dev
->dev
)) {
3455 tmp
= phy
->gmode
? B43_TMSLOW_GMODE
: 0;
3456 b43_wireless_core_reset(dev
, tmp
);
3459 if ((phy
->type
== B43_PHYTYPE_B
) || (phy
->type
== B43_PHYTYPE_G
)) {
3461 kzalloc(sizeof(*(phy
->lo_control
)), GFP_KERNEL
);
3462 if (!phy
->lo_control
) {
3467 setup_struct_wldev_for_init(dev
);
3469 err
= b43_phy_init_tssi2dbm_table(dev
);
3471 goto err_kfree_lo_control
;
3473 /* Enable IRQ routing to this device. */
3474 ssb_pcicore_dev_irqvecs_enable(&bus
->pcicore
, dev
->dev
);
3476 b43_imcfglo_timeouts_workaround(dev
);
3477 b43_bluetooth_coext_disable(dev
);
3478 b43_phy_early_init(dev
);
3479 err
= b43_chip_init(dev
);
3481 goto err_kfree_tssitbl
;
3482 b43_shm_write16(dev
, B43_SHM_SHARED
,
3483 B43_SHM_SH_WLCOREREV
, dev
->dev
->id
.revision
);
3484 hf
= b43_hf_read(dev
);
3485 if (phy
->type
== B43_PHYTYPE_G
) {
3489 if (sprom
->boardflags_lo
& B43_BFL_PACTRL
)
3490 hf
|= B43_HF_OFDMPABOOST
;
3491 } else if (phy
->type
== B43_PHYTYPE_B
) {
3493 if (phy
->rev
>= 2 && phy
->radio_ver
== 0x2050)
3496 b43_hf_write(dev
, hf
);
3498 b43_set_retry_limits(dev
, B43_DEFAULT_SHORT_RETRY_LIMIT
,
3499 B43_DEFAULT_LONG_RETRY_LIMIT
);
3500 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_SFFBLIM
, 3);
3501 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_LFFBLIM
, 2);
3503 /* Disable sending probe responses from firmware.
3504 * Setting the MaxTime to one usec will always trigger
3505 * a timeout, so we never send any probe resp.
3506 * A timeout of zero is infinite. */
3507 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRMAXTIME
, 1);
3509 b43_rate_memory_init(dev
);
3511 /* Minimum Contention Window */
3512 if (phy
->type
== B43_PHYTYPE_B
) {
3513 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0x1F);
3515 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0xF);
3517 /* Maximum Contention Window */
3518 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MAXCONT
, 0x3FF);
3520 err
= b43_dma_init(dev
);
3527 b43_write16(dev
, 0x0612, 0x0050);
3528 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0416, 0x0050);
3529 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0414, 0x01F4);
3532 b43_bluetooth_coext_enable(dev
);
3534 ssb_bus_powerup(bus
, 1); /* Enable dynamic PCTL */
3535 memset(wl
->bssid
, 0, ETH_ALEN
);
3536 memset(wl
->mac_addr
, 0, ETH_ALEN
);
3537 b43_upload_card_macaddress(dev
);
3538 b43_security_init(dev
);
3541 b43_set_status(dev
, B43_STAT_INITIALIZED
);
3550 if (phy
->dyn_tssi_tbl
)
3551 kfree(phy
->tssi2dbm
);
3552 err_kfree_lo_control
:
3553 kfree(phy
->lo_control
);
3554 phy
->lo_control
= NULL
;
3556 ssb_bus_may_powerdown(bus
);
3557 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
3561 static int b43_op_add_interface(struct ieee80211_hw
*hw
,
3562 struct ieee80211_if_init_conf
*conf
)
3564 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3565 struct b43_wldev
*dev
;
3566 unsigned long flags
;
3567 int err
= -EOPNOTSUPP
;
3569 /* TODO: allow WDS/AP devices to coexist */
3571 if (conf
->type
!= IEEE80211_IF_TYPE_AP
&&
3572 conf
->type
!= IEEE80211_IF_TYPE_STA
&&
3573 conf
->type
!= IEEE80211_IF_TYPE_WDS
&&
3574 conf
->type
!= IEEE80211_IF_TYPE_IBSS
)
3577 mutex_lock(&wl
->mutex
);
3579 goto out_mutex_unlock
;
3581 b43dbg(wl
, "Adding Interface type %d\n", conf
->type
);
3583 dev
= wl
->current_dev
;
3585 wl
->vif
= conf
->vif
;
3586 wl
->if_type
= conf
->type
;
3587 memcpy(wl
->mac_addr
, conf
->mac_addr
, ETH_ALEN
);
3589 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3590 b43_adjust_opmode(dev
);
3591 b43_upload_card_macaddress(dev
);
3592 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3596 mutex_unlock(&wl
->mutex
);
3601 static void b43_op_remove_interface(struct ieee80211_hw
*hw
,
3602 struct ieee80211_if_init_conf
*conf
)
3604 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3605 struct b43_wldev
*dev
= wl
->current_dev
;
3606 unsigned long flags
;
3608 b43dbg(wl
, "Removing Interface type %d\n", conf
->type
);
3610 mutex_lock(&wl
->mutex
);
3612 B43_WARN_ON(!wl
->operating
);
3613 B43_WARN_ON(wl
->vif
!= conf
->vif
);
3618 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3619 b43_adjust_opmode(dev
);
3620 memset(wl
->mac_addr
, 0, ETH_ALEN
);
3621 b43_upload_card_macaddress(dev
);
3622 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3624 mutex_unlock(&wl
->mutex
);
3627 static int b43_op_start(struct ieee80211_hw
*hw
)
3629 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3630 struct b43_wldev
*dev
= wl
->current_dev
;
3633 bool do_rfkill_exit
= 0;
3635 /* First register RFkill.
3636 * LEDs that are registered later depend on it. */
3637 b43_rfkill_init(dev
);
3639 mutex_lock(&wl
->mutex
);
3641 if (b43_status(dev
) < B43_STAT_INITIALIZED
) {
3642 err
= b43_wireless_core_init(dev
);
3645 goto out_mutex_unlock
;
3650 if (b43_status(dev
) < B43_STAT_STARTED
) {
3651 err
= b43_wireless_core_start(dev
);
3654 b43_wireless_core_exit(dev
);
3656 goto out_mutex_unlock
;
3661 mutex_unlock(&wl
->mutex
);
3664 b43_rfkill_exit(dev
);
3669 static void b43_op_stop(struct ieee80211_hw
*hw
)
3671 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3672 struct b43_wldev
*dev
= wl
->current_dev
;
3674 b43_rfkill_exit(dev
);
3676 mutex_lock(&wl
->mutex
);
3677 if (b43_status(dev
) >= B43_STAT_STARTED
)
3678 b43_wireless_core_stop(dev
);
3679 b43_wireless_core_exit(dev
);
3680 mutex_unlock(&wl
->mutex
);
3683 static int b43_op_set_retry_limit(struct ieee80211_hw
*hw
,
3684 u32 short_retry_limit
, u32 long_retry_limit
)
3686 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3687 struct b43_wldev
*dev
;
3690 mutex_lock(&wl
->mutex
);
3691 dev
= wl
->current_dev
;
3692 if (unlikely(!dev
|| (b43_status(dev
) < B43_STAT_INITIALIZED
))) {
3696 b43_set_retry_limits(dev
, short_retry_limit
, long_retry_limit
);
3698 mutex_unlock(&wl
->mutex
);
3703 static int b43_op_beacon_set_tim(struct ieee80211_hw
*hw
, int aid
, int set
)
3705 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3706 struct sk_buff
*beacon
;
3707 unsigned long flags
;
3709 /* We could modify the existing beacon and set the aid bit in
3710 * the TIM field, but that would probably require resizing and
3711 * moving of data within the beacon template.
3712 * Simply request a new beacon and let mac80211 do the hard work. */
3713 beacon
= ieee80211_beacon_get(hw
, wl
->vif
, NULL
);
3714 if (unlikely(!beacon
))
3716 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3717 b43_update_templates(wl
, beacon
);
3718 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3723 static int b43_op_ibss_beacon_update(struct ieee80211_hw
*hw
,
3724 struct sk_buff
*beacon
,
3725 struct ieee80211_tx_control
*ctl
)
3727 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3728 unsigned long flags
;
3730 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3731 b43_update_templates(wl
, beacon
);
3732 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3737 static const struct ieee80211_ops b43_hw_ops
= {
3739 .conf_tx
= b43_op_conf_tx
,
3740 .add_interface
= b43_op_add_interface
,
3741 .remove_interface
= b43_op_remove_interface
,
3742 .config
= b43_op_config
,
3743 .config_interface
= b43_op_config_interface
,
3744 .configure_filter
= b43_op_configure_filter
,
3745 .set_key
= b43_op_set_key
,
3746 .get_stats
= b43_op_get_stats
,
3747 .get_tx_stats
= b43_op_get_tx_stats
,
3748 .start
= b43_op_start
,
3749 .stop
= b43_op_stop
,
3750 .set_retry_limit
= b43_op_set_retry_limit
,
3751 .set_tim
= b43_op_beacon_set_tim
,
3752 .beacon_update
= b43_op_ibss_beacon_update
,
3755 /* Hard-reset the chip. Do not call this directly.
3756 * Use b43_controller_restart()
3758 static void b43_chip_reset(struct work_struct
*work
)
3760 struct b43_wldev
*dev
=
3761 container_of(work
, struct b43_wldev
, restart_work
);
3762 struct b43_wl
*wl
= dev
->wl
;
3766 mutex_lock(&wl
->mutex
);
3768 prev_status
= b43_status(dev
);
3769 /* Bring the device down... */
3770 if (prev_status
>= B43_STAT_STARTED
)
3771 b43_wireless_core_stop(dev
);
3772 if (prev_status
>= B43_STAT_INITIALIZED
)
3773 b43_wireless_core_exit(dev
);
3775 /* ...and up again. */
3776 if (prev_status
>= B43_STAT_INITIALIZED
) {
3777 err
= b43_wireless_core_init(dev
);
3781 if (prev_status
>= B43_STAT_STARTED
) {
3782 err
= b43_wireless_core_start(dev
);
3784 b43_wireless_core_exit(dev
);
3789 mutex_unlock(&wl
->mutex
);
3791 b43err(wl
, "Controller restart FAILED\n");
3793 b43info(wl
, "Controller restarted\n");
3796 static int b43_setup_modes(struct b43_wldev
*dev
,
3797 bool have_2ghz_phy
, bool have_5ghz_phy
)
3799 struct ieee80211_hw
*hw
= dev
->wl
->hw
;
3800 struct ieee80211_hw_mode
*mode
;
3801 struct b43_phy
*phy
= &dev
->phy
;
3804 /* XXX: This function will go away soon, when mac80211
3805 * band stuff is rewritten. So this is just a hack.
3806 * For now we always claim GPHY mode, as there is no
3807 * support for NPHY and APHY in the device, yet.
3808 * This assumption is OK, as any B, N or A PHY will already
3809 * have died a horrible sanity check death earlier. */
3811 mode
= &phy
->hwmodes
[0];
3812 mode
->mode
= MODE_IEEE80211G
;
3813 mode
->num_channels
= b43_2ghz_chantable_size
;
3814 mode
->channels
= b43_2ghz_chantable
;
3815 mode
->num_rates
= b43_g_ratetable_size
;
3816 mode
->rates
= b43_g_ratetable
;
3817 err
= ieee80211_register_hwmode(hw
, mode
);
3820 phy
->possible_phymodes
|= B43_PHYMODE_G
;
3825 static void b43_wireless_core_detach(struct b43_wldev
*dev
)
3827 /* We release firmware that late to not be required to re-request
3828 * is all the time when we reinit the core. */
3829 b43_release_firmware(dev
);
3832 static int b43_wireless_core_attach(struct b43_wldev
*dev
)
3834 struct b43_wl
*wl
= dev
->wl
;
3835 struct ssb_bus
*bus
= dev
->dev
->bus
;
3836 struct pci_dev
*pdev
= bus
->host_pci
;
3838 bool have_2ghz_phy
= 0, have_5ghz_phy
= 0;
3841 /* Do NOT do any device initialization here.
3842 * Do it in wireless_core_init() instead.
3843 * This function is for gathering basic information about the HW, only.
3844 * Also some structs may be set up here. But most likely you want to have
3845 * that in core_init(), too.
3848 err
= ssb_bus_powerup(bus
, 0);
3850 b43err(wl
, "Bus powerup failed\n");
3853 /* Get the PHY type. */
3854 if (dev
->dev
->id
.revision
>= 5) {
3857 tmshigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
3858 have_2ghz_phy
= !!(tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
);
3859 have_5ghz_phy
= !!(tmshigh
& B43_TMSHIGH_HAVE_5GHZ_PHY
);
3863 dev
->phy
.gmode
= have_2ghz_phy
;
3864 tmp
= dev
->phy
.gmode
? B43_TMSLOW_GMODE
: 0;
3865 b43_wireless_core_reset(dev
, tmp
);
3867 err
= b43_phy_versioning(dev
);
3870 /* Check if this device supports multiband. */
3872 (pdev
->device
!= 0x4312 &&
3873 pdev
->device
!= 0x4319 && pdev
->device
!= 0x4324)) {
3874 /* No multiband support. */
3877 switch (dev
->phy
.type
) {
3889 if (dev
->phy
.type
== B43_PHYTYPE_A
) {
3891 b43err(wl
, "IEEE 802.11a devices are unsupported\n");
3895 dev
->phy
.gmode
= have_2ghz_phy
;
3896 tmp
= dev
->phy
.gmode
? B43_TMSLOW_GMODE
: 0;
3897 b43_wireless_core_reset(dev
, tmp
);
3899 err
= b43_validate_chipaccess(dev
);
3902 err
= b43_setup_modes(dev
, have_2ghz_phy
, have_5ghz_phy
);
3906 /* Now set some default "current_dev" */
3907 if (!wl
->current_dev
)
3908 wl
->current_dev
= dev
;
3909 INIT_WORK(&dev
->restart_work
, b43_chip_reset
);
3911 b43_radio_turn_off(dev
, 1);
3912 b43_switch_analog(dev
, 0);
3913 ssb_device_disable(dev
->dev
, 0);
3914 ssb_bus_may_powerdown(bus
);
3920 ssb_bus_may_powerdown(bus
);
3924 static void b43_one_core_detach(struct ssb_device
*dev
)
3926 struct b43_wldev
*wldev
;
3929 wldev
= ssb_get_drvdata(dev
);
3931 cancel_work_sync(&wldev
->restart_work
);
3932 b43_debugfs_remove_device(wldev
);
3933 b43_wireless_core_detach(wldev
);
3934 list_del(&wldev
->list
);
3936 ssb_set_drvdata(dev
, NULL
);
3940 static int b43_one_core_attach(struct ssb_device
*dev
, struct b43_wl
*wl
)
3942 struct b43_wldev
*wldev
;
3943 struct pci_dev
*pdev
;
3946 if (!list_empty(&wl
->devlist
)) {
3947 /* We are not the first core on this chip. */
3948 pdev
= dev
->bus
->host_pci
;
3949 /* Only special chips support more than one wireless
3950 * core, although some of the other chips have more than
3951 * one wireless core as well. Check for this and
3955 ((pdev
->device
!= 0x4321) &&
3956 (pdev
->device
!= 0x4313) && (pdev
->device
!= 0x431A))) {
3957 b43dbg(wl
, "Ignoring unconnected 802.11 core\n");
3962 wldev
= kzalloc(sizeof(*wldev
), GFP_KERNEL
);
3968 b43_set_status(wldev
, B43_STAT_UNINIT
);
3969 wldev
->bad_frames_preempt
= modparam_bad_frames_preempt
;
3970 tasklet_init(&wldev
->isr_tasklet
,
3971 (void (*)(unsigned long))b43_interrupt_tasklet
,
3972 (unsigned long)wldev
);
3973 INIT_LIST_HEAD(&wldev
->list
);
3975 err
= b43_wireless_core_attach(wldev
);
3977 goto err_kfree_wldev
;
3979 list_add(&wldev
->list
, &wl
->devlist
);
3981 ssb_set_drvdata(dev
, wldev
);
3982 b43_debugfs_add_device(wldev
);
3992 static void b43_sprom_fixup(struct ssb_bus
*bus
)
3994 /* boardflags workarounds */
3995 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_DELL
&&
3996 bus
->chip_id
== 0x4301 && bus
->boardinfo
.rev
== 0x74)
3997 bus
->sprom
.boardflags_lo
|= B43_BFL_BTCOEXIST
;
3998 if (bus
->boardinfo
.vendor
== PCI_VENDOR_ID_APPLE
&&
3999 bus
->boardinfo
.type
== 0x4E && bus
->boardinfo
.rev
> 0x40)
4000 bus
->sprom
.boardflags_lo
|= B43_BFL_PACTRL
;
4003 static void b43_wireless_exit(struct ssb_device
*dev
, struct b43_wl
*wl
)
4005 struct ieee80211_hw
*hw
= wl
->hw
;
4007 ssb_set_devtypedata(dev
, NULL
);
4008 ieee80211_free_hw(hw
);
4011 static int b43_wireless_init(struct ssb_device
*dev
)
4013 struct ssb_sprom
*sprom
= &dev
->bus
->sprom
;
4014 struct ieee80211_hw
*hw
;
4018 b43_sprom_fixup(dev
->bus
);
4020 hw
= ieee80211_alloc_hw(sizeof(*wl
), &b43_hw_ops
);
4022 b43err(NULL
, "Could not allocate ieee80211 device\n");
4027 hw
->flags
= IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE
|
4028 IEEE80211_HW_RX_INCLUDES_FCS
;
4029 hw
->max_signal
= 100;
4030 hw
->max_rssi
= -110;
4031 hw
->max_noise
= -110;
4032 hw
->queues
= 1; /* FIXME: hardware has more queues */
4033 SET_IEEE80211_DEV(hw
, dev
->dev
);
4034 if (is_valid_ether_addr(sprom
->et1mac
))
4035 SET_IEEE80211_PERM_ADDR(hw
, sprom
->et1mac
);
4037 SET_IEEE80211_PERM_ADDR(hw
, sprom
->il0mac
);
4039 /* Get and initialize struct b43_wl */
4040 wl
= hw_to_b43_wl(hw
);
4041 memset(wl
, 0, sizeof(*wl
));
4043 spin_lock_init(&wl
->irq_lock
);
4044 spin_lock_init(&wl
->leds_lock
);
4045 spin_lock_init(&wl
->shm_lock
);
4046 mutex_init(&wl
->mutex
);
4047 INIT_LIST_HEAD(&wl
->devlist
);
4049 ssb_set_devtypedata(dev
, wl
);
4050 b43info(wl
, "Broadcom %04X WLAN found\n", dev
->bus
->chip_id
);
4056 static int b43_probe(struct ssb_device
*dev
, const struct ssb_device_id
*id
)
4062 wl
= ssb_get_devtypedata(dev
);
4064 /* Probing the first core. Must setup common struct b43_wl */
4066 err
= b43_wireless_init(dev
);
4069 wl
= ssb_get_devtypedata(dev
);
4072 err
= b43_one_core_attach(dev
, wl
);
4074 goto err_wireless_exit
;
4077 err
= ieee80211_register_hw(wl
->hw
);
4079 goto err_one_core_detach
;
4085 err_one_core_detach
:
4086 b43_one_core_detach(dev
);
4089 b43_wireless_exit(dev
, wl
);
4093 static void b43_remove(struct ssb_device
*dev
)
4095 struct b43_wl
*wl
= ssb_get_devtypedata(dev
);
4096 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
4099 if (wl
->current_dev
== wldev
)
4100 ieee80211_unregister_hw(wl
->hw
);
4102 b43_one_core_detach(dev
);
4104 if (list_empty(&wl
->devlist
)) {
4105 /* Last core on the chip unregistered.
4106 * We can destroy common struct b43_wl.
4108 b43_wireless_exit(dev
, wl
);
4112 /* Perform a hardware reset. This can be called from any context. */
4113 void b43_controller_restart(struct b43_wldev
*dev
, const char *reason
)
4115 /* Must avoid requeueing, if we are in shutdown. */
4116 if (b43_status(dev
) < B43_STAT_INITIALIZED
)
4118 b43info(dev
->wl
, "Controller RESET (%s) ...\n", reason
);
4119 queue_work(dev
->wl
->hw
->workqueue
, &dev
->restart_work
);
4124 static int b43_suspend(struct ssb_device
*dev
, pm_message_t state
)
4126 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
4127 struct b43_wl
*wl
= wldev
->wl
;
4129 b43dbg(wl
, "Suspending...\n");
4131 mutex_lock(&wl
->mutex
);
4132 wldev
->suspend_init_status
= b43_status(wldev
);
4133 if (wldev
->suspend_init_status
>= B43_STAT_STARTED
)
4134 b43_wireless_core_stop(wldev
);
4135 if (wldev
->suspend_init_status
>= B43_STAT_INITIALIZED
)
4136 b43_wireless_core_exit(wldev
);
4137 mutex_unlock(&wl
->mutex
);
4139 b43dbg(wl
, "Device suspended.\n");
4144 static int b43_resume(struct ssb_device
*dev
)
4146 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
4147 struct b43_wl
*wl
= wldev
->wl
;
4150 b43dbg(wl
, "Resuming...\n");
4152 mutex_lock(&wl
->mutex
);
4153 if (wldev
->suspend_init_status
>= B43_STAT_INITIALIZED
) {
4154 err
= b43_wireless_core_init(wldev
);
4156 b43err(wl
, "Resume failed at core init\n");
4160 if (wldev
->suspend_init_status
>= B43_STAT_STARTED
) {
4161 err
= b43_wireless_core_start(wldev
);
4163 b43_wireless_core_exit(wldev
);
4164 b43err(wl
, "Resume failed at core start\n");
4168 mutex_unlock(&wl
->mutex
);
4170 b43dbg(wl
, "Device resumed.\n");
4175 #else /* CONFIG_PM */
4176 # define b43_suspend NULL
4177 # define b43_resume NULL
4178 #endif /* CONFIG_PM */
4180 static struct ssb_driver b43_ssb_driver
= {
4181 .name
= KBUILD_MODNAME
,
4182 .id_table
= b43_ssb_tbl
,
4184 .remove
= b43_remove
,
4185 .suspend
= b43_suspend
,
4186 .resume
= b43_resume
,
4189 static int __init
b43_init(void)
4194 err
= b43_pcmcia_init();
4197 err
= ssb_driver_register(&b43_ssb_driver
);
4199 goto err_pcmcia_exit
;
4210 static void __exit
b43_exit(void)
4212 ssb_driver_unregister(&b43_ssb_driver
);
4217 module_init(b43_init
)
4218 module_exit(b43_exit
)