3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
54 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
55 MODULE_AUTHOR("Martin Langer");
56 MODULE_AUTHOR("Stefano Brivio");
57 MODULE_AUTHOR("Michael Buesch");
58 MODULE_LICENSE("GPL");
61 static int modparam_bad_frames_preempt
;
62 module_param_named(bad_frames_preempt
, modparam_bad_frames_preempt
, int, 0444);
63 MODULE_PARM_DESC(bad_frames_preempt
,
64 "enable(1) / disable(0) Bad Frames Preemption");
66 static char modparam_fwpostfix
[16];
67 module_param_string(fwpostfix
, modparam_fwpostfix
, 16, 0444);
68 MODULE_PARM_DESC(fwpostfix
, "Postfix for the .fw files to load.");
70 static int modparam_hwpctl
;
71 module_param_named(hwpctl
, modparam_hwpctl
, int, 0444);
72 MODULE_PARM_DESC(hwpctl
, "Enable hardware-side power control (default off)");
74 static int modparam_nohwcrypt
;
75 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
76 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
78 static const struct ssb_device_id b43_ssb_tbl
[] = {
79 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 5),
80 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 6),
81 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 7),
82 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 9),
83 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 10),
84 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 11),
85 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 13),
89 MODULE_DEVICE_TABLE(ssb
, b43_ssb_tbl
);
91 /* Channel and ratetables are shared for all devices.
92 * They can't be const, because ieee80211 puts some precalculated
93 * data in there. This data is the same for all devices, so we don't
94 * get concurrency issues */
95 #define RATETAB_ENT(_rateid, _flags) \
97 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
102 static struct ieee80211_rate __b43_ratetable
[] = {
103 RATETAB_ENT(B43_CCK_RATE_1MB
, IEEE80211_RATE_CCK
),
104 RATETAB_ENT(B43_CCK_RATE_2MB
, IEEE80211_RATE_CCK_2
),
105 RATETAB_ENT(B43_CCK_RATE_5MB
, IEEE80211_RATE_CCK_2
),
106 RATETAB_ENT(B43_CCK_RATE_11MB
, IEEE80211_RATE_CCK_2
),
107 RATETAB_ENT(B43_OFDM_RATE_6MB
, IEEE80211_RATE_OFDM
),
108 RATETAB_ENT(B43_OFDM_RATE_9MB
, IEEE80211_RATE_OFDM
),
109 RATETAB_ENT(B43_OFDM_RATE_12MB
, IEEE80211_RATE_OFDM
),
110 RATETAB_ENT(B43_OFDM_RATE_18MB
, IEEE80211_RATE_OFDM
),
111 RATETAB_ENT(B43_OFDM_RATE_24MB
, IEEE80211_RATE_OFDM
),
112 RATETAB_ENT(B43_OFDM_RATE_36MB
, IEEE80211_RATE_OFDM
),
113 RATETAB_ENT(B43_OFDM_RATE_48MB
, IEEE80211_RATE_OFDM
),
114 RATETAB_ENT(B43_OFDM_RATE_54MB
, IEEE80211_RATE_OFDM
),
117 #define b43_a_ratetable (__b43_ratetable + 4)
118 #define b43_a_ratetable_size 8
119 #define b43_b_ratetable (__b43_ratetable + 0)
120 #define b43_b_ratetable_size 4
121 #define b43_g_ratetable (__b43_ratetable + 0)
122 #define b43_g_ratetable_size 12
124 #define CHANTAB_ENT(_chanid, _freq) \
129 .flag = IEEE80211_CHAN_W_SCAN | \
130 IEEE80211_CHAN_W_ACTIVE_SCAN | \
131 IEEE80211_CHAN_W_IBSS, \
132 .power_level = 0xFF, \
133 .antenna_max = 0xFF, \
135 static struct ieee80211_channel b43_2ghz_chantable
[] = {
136 CHANTAB_ENT(1, 2412),
137 CHANTAB_ENT(2, 2417),
138 CHANTAB_ENT(3, 2422),
139 CHANTAB_ENT(4, 2427),
140 CHANTAB_ENT(5, 2432),
141 CHANTAB_ENT(6, 2437),
142 CHANTAB_ENT(7, 2442),
143 CHANTAB_ENT(8, 2447),
144 CHANTAB_ENT(9, 2452),
145 CHANTAB_ENT(10, 2457),
146 CHANTAB_ENT(11, 2462),
147 CHANTAB_ENT(12, 2467),
148 CHANTAB_ENT(13, 2472),
149 CHANTAB_ENT(14, 2484),
151 #define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
154 static struct ieee80211_channel b43_5ghz_chantable
[] = {
155 CHANTAB_ENT(36, 5180),
156 CHANTAB_ENT(40, 5200),
157 CHANTAB_ENT(44, 5220),
158 CHANTAB_ENT(48, 5240),
159 CHANTAB_ENT(52, 5260),
160 CHANTAB_ENT(56, 5280),
161 CHANTAB_ENT(60, 5300),
162 CHANTAB_ENT(64, 5320),
163 CHANTAB_ENT(149, 5745),
164 CHANTAB_ENT(153, 5765),
165 CHANTAB_ENT(157, 5785),
166 CHANTAB_ENT(161, 5805),
167 CHANTAB_ENT(165, 5825),
169 #define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
172 static void b43_wireless_core_exit(struct b43_wldev
*dev
);
173 static int b43_wireless_core_init(struct b43_wldev
*dev
);
174 static void b43_wireless_core_stop(struct b43_wldev
*dev
);
175 static int b43_wireless_core_start(struct b43_wldev
*dev
);
177 static int b43_ratelimit(struct b43_wl
*wl
)
179 if (!wl
|| !wl
->current_dev
)
181 if (b43_status(wl
->current_dev
) < B43_STAT_STARTED
)
183 /* We are up and running.
184 * Ratelimit the messages to avoid DoS over the net. */
185 return net_ratelimit();
188 void b43info(struct b43_wl
*wl
, const char *fmt
, ...)
192 if (!b43_ratelimit(wl
))
195 printk(KERN_INFO
"b43-%s: ",
196 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
201 void b43err(struct b43_wl
*wl
, const char *fmt
, ...)
205 if (!b43_ratelimit(wl
))
208 printk(KERN_ERR
"b43-%s ERROR: ",
209 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
214 void b43warn(struct b43_wl
*wl
, const char *fmt
, ...)
218 if (!b43_ratelimit(wl
))
221 printk(KERN_WARNING
"b43-%s warning: ",
222 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
228 void b43dbg(struct b43_wl
*wl
, const char *fmt
, ...)
233 printk(KERN_DEBUG
"b43-%s debug: ",
234 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
240 static void b43_ram_write(struct b43_wldev
*dev
, u16 offset
, u32 val
)
244 B43_WARN_ON(offset
% 4 != 0);
246 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
247 if (macctl
& B43_MACCTL_BE
)
250 b43_write32(dev
, B43_MMIO_RAM_CONTROL
, offset
);
252 b43_write32(dev
, B43_MMIO_RAM_DATA
, val
);
256 void b43_shm_control_word(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
260 /* "offset" is the WORD offset. */
265 b43_write32(dev
, B43_MMIO_SHM_CONTROL
, control
);
268 u32
b43_shm_read32(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
272 if (routing
== B43_SHM_SHARED
) {
273 B43_WARN_ON(offset
& 0x0001);
274 if (offset
& 0x0003) {
275 /* Unaligned access */
276 b43_shm_control_word(dev
, routing
, offset
>> 2);
277 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
279 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
280 ret
|= b43_read16(dev
, B43_MMIO_SHM_DATA
);
286 b43_shm_control_word(dev
, routing
, offset
);
287 ret
= b43_read32(dev
, B43_MMIO_SHM_DATA
);
292 u16
b43_shm_read16(struct b43_wldev
* dev
, u16 routing
, u16 offset
)
296 if (routing
== B43_SHM_SHARED
) {
297 B43_WARN_ON(offset
& 0x0001);
298 if (offset
& 0x0003) {
299 /* Unaligned access */
300 b43_shm_control_word(dev
, routing
, offset
>> 2);
301 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
307 b43_shm_control_word(dev
, routing
, offset
);
308 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA
);
313 void b43_shm_write32(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u32 value
)
315 if (routing
== B43_SHM_SHARED
) {
316 B43_WARN_ON(offset
& 0x0001);
317 if (offset
& 0x0003) {
318 /* Unaligned access */
319 b43_shm_control_word(dev
, routing
, offset
>> 2);
321 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
,
322 (value
>> 16) & 0xffff);
324 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
326 b43_write16(dev
, B43_MMIO_SHM_DATA
, value
& 0xffff);
331 b43_shm_control_word(dev
, routing
, offset
);
333 b43_write32(dev
, B43_MMIO_SHM_DATA
, value
);
336 void b43_shm_write16(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u16 value
)
338 if (routing
== B43_SHM_SHARED
) {
339 B43_WARN_ON(offset
& 0x0001);
340 if (offset
& 0x0003) {
341 /* Unaligned access */
342 b43_shm_control_word(dev
, routing
, offset
>> 2);
344 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
, value
);
349 b43_shm_control_word(dev
, routing
, offset
);
351 b43_write16(dev
, B43_MMIO_SHM_DATA
, value
);
355 u32
b43_hf_read(struct b43_wldev
* dev
)
359 ret
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFHI
);
361 ret
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFLO
);
366 /* Write HostFlags */
367 void b43_hf_write(struct b43_wldev
*dev
, u32 value
)
369 b43_shm_write16(dev
, B43_SHM_SHARED
,
370 B43_SHM_SH_HOSTFLO
, (value
& 0x0000FFFF));
371 b43_shm_write16(dev
, B43_SHM_SHARED
,
372 B43_SHM_SH_HOSTFHI
, ((value
& 0xFFFF0000) >> 16));
375 void b43_tsf_read(struct b43_wldev
*dev
, u64
* tsf
)
377 /* We need to be careful. As we read the TSF from multiple
378 * registers, we should take care of register overflows.
379 * In theory, the whole tsf read process should be atomic.
380 * We try to be atomic here, by restaring the read process,
381 * if any of the high registers changed (overflew).
383 if (dev
->dev
->id
.revision
>= 3) {
384 u32 low
, high
, high2
;
387 high
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
);
388 low
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
);
389 high2
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
);
390 } while (unlikely(high
!= high2
));
398 u16 test1
, test2
, test3
;
401 v3
= b43_read16(dev
, B43_MMIO_TSF_3
);
402 v2
= b43_read16(dev
, B43_MMIO_TSF_2
);
403 v1
= b43_read16(dev
, B43_MMIO_TSF_1
);
404 v0
= b43_read16(dev
, B43_MMIO_TSF_0
);
406 test3
= b43_read16(dev
, B43_MMIO_TSF_3
);
407 test2
= b43_read16(dev
, B43_MMIO_TSF_2
);
408 test1
= b43_read16(dev
, B43_MMIO_TSF_1
);
409 } while (v3
!= test3
|| v2
!= test2
|| v1
!= test1
);
423 static void b43_time_lock(struct b43_wldev
*dev
)
427 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
428 macctl
|= B43_MACCTL_TBTTHOLD
;
429 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
430 /* Commit the write */
431 b43_read32(dev
, B43_MMIO_MACCTL
);
434 static void b43_time_unlock(struct b43_wldev
*dev
)
438 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
439 macctl
&= ~B43_MACCTL_TBTTHOLD
;
440 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
441 /* Commit the write */
442 b43_read32(dev
, B43_MMIO_MACCTL
);
445 static void b43_tsf_write_locked(struct b43_wldev
*dev
, u64 tsf
)
447 /* Be careful with the in-progress timer.
448 * First zero out the low register, so we have a full
449 * register-overflow duration to complete the operation.
451 if (dev
->dev
->id
.revision
>= 3) {
452 u32 lo
= (tsf
& 0x00000000FFFFFFFFULL
);
453 u32 hi
= (tsf
& 0xFFFFFFFF00000000ULL
) >> 32;
455 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
, 0);
457 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
, hi
);
459 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
, lo
);
461 u16 v0
= (tsf
& 0x000000000000FFFFULL
);
462 u16 v1
= (tsf
& 0x00000000FFFF0000ULL
) >> 16;
463 u16 v2
= (tsf
& 0x0000FFFF00000000ULL
) >> 32;
464 u16 v3
= (tsf
& 0xFFFF000000000000ULL
) >> 48;
466 b43_write16(dev
, B43_MMIO_TSF_0
, 0);
468 b43_write16(dev
, B43_MMIO_TSF_3
, v3
);
470 b43_write16(dev
, B43_MMIO_TSF_2
, v2
);
472 b43_write16(dev
, B43_MMIO_TSF_1
, v1
);
474 b43_write16(dev
, B43_MMIO_TSF_0
, v0
);
478 void b43_tsf_write(struct b43_wldev
*dev
, u64 tsf
)
481 b43_tsf_write_locked(dev
, tsf
);
482 b43_time_unlock(dev
);
486 void b43_macfilter_set(struct b43_wldev
*dev
, u16 offset
, const u8
* mac
)
488 static const u8 zero_addr
[ETH_ALEN
] = { 0 };
495 b43_write16(dev
, B43_MMIO_MACFILTER_CONTROL
, offset
);
499 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
502 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
505 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
508 static void b43_write_mac_bssid_templates(struct b43_wldev
*dev
)
512 u8 mac_bssid
[ETH_ALEN
* 2];
516 bssid
= dev
->wl
->bssid
;
517 mac
= dev
->wl
->mac_addr
;
519 b43_macfilter_set(dev
, B43_MACFILTER_BSSID
, bssid
);
521 memcpy(mac_bssid
, mac
, ETH_ALEN
);
522 memcpy(mac_bssid
+ ETH_ALEN
, bssid
, ETH_ALEN
);
524 /* Write our MAC address and BSSID to template ram */
525 for (i
= 0; i
< ARRAY_SIZE(mac_bssid
); i
+= sizeof(u32
)) {
526 tmp
= (u32
) (mac_bssid
[i
+ 0]);
527 tmp
|= (u32
) (mac_bssid
[i
+ 1]) << 8;
528 tmp
|= (u32
) (mac_bssid
[i
+ 2]) << 16;
529 tmp
|= (u32
) (mac_bssid
[i
+ 3]) << 24;
530 b43_ram_write(dev
, 0x20 + i
, tmp
);
534 static void b43_upload_card_macaddress(struct b43_wldev
*dev
)
536 b43_write_mac_bssid_templates(dev
);
537 b43_macfilter_set(dev
, B43_MACFILTER_SELF
, dev
->wl
->mac_addr
);
540 static void b43_set_slot_time(struct b43_wldev
*dev
, u16 slot_time
)
542 /* slot_time is in usec. */
543 if (dev
->phy
.type
!= B43_PHYTYPE_G
)
545 b43_write16(dev
, 0x684, 510 + slot_time
);
546 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0010, slot_time
);
549 static void b43_short_slot_timing_enable(struct b43_wldev
*dev
)
551 b43_set_slot_time(dev
, 9);
555 static void b43_short_slot_timing_disable(struct b43_wldev
*dev
)
557 b43_set_slot_time(dev
, 20);
561 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
562 * Returns the _previously_ enabled IRQ mask.
564 static inline u32
b43_interrupt_enable(struct b43_wldev
*dev
, u32 mask
)
568 old_mask
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
569 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, old_mask
| mask
);
574 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
575 * Returns the _previously_ enabled IRQ mask.
577 static inline u32
b43_interrupt_disable(struct b43_wldev
*dev
, u32 mask
)
581 old_mask
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
582 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, old_mask
& ~mask
);
587 /* Synchronize IRQ top- and bottom-half.
588 * IRQs must be masked before calling this.
589 * This must not be called with the irq_lock held.
591 static void b43_synchronize_irq(struct b43_wldev
*dev
)
593 synchronize_irq(dev
->dev
->irq
);
594 tasklet_kill(&dev
->isr_tasklet
);
597 /* DummyTransmission function, as documented on
598 * http://bcm-specs.sipsolutions.net/DummyTransmission
600 void b43_dummy_transmission(struct b43_wldev
*dev
)
602 struct b43_phy
*phy
= &dev
->phy
;
603 unsigned int i
, max_loop
;
616 buffer
[0] = 0x000201CC;
621 buffer
[0] = 0x000B846E;
628 for (i
= 0; i
< 5; i
++)
629 b43_ram_write(dev
, i
* 4, buffer
[i
]);
632 b43_read32(dev
, B43_MMIO_MACCTL
);
634 b43_write16(dev
, 0x0568, 0x0000);
635 b43_write16(dev
, 0x07C0, 0x0000);
636 value
= ((phy
->type
== B43_PHYTYPE_A
) ? 1 : 0);
637 b43_write16(dev
, 0x050C, value
);
638 b43_write16(dev
, 0x0508, 0x0000);
639 b43_write16(dev
, 0x050A, 0x0000);
640 b43_write16(dev
, 0x054C, 0x0000);
641 b43_write16(dev
, 0x056A, 0x0014);
642 b43_write16(dev
, 0x0568, 0x0826);
643 b43_write16(dev
, 0x0500, 0x0000);
644 b43_write16(dev
, 0x0502, 0x0030);
646 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
647 b43_radio_write16(dev
, 0x0051, 0x0017);
648 for (i
= 0x00; i
< max_loop
; i
++) {
649 value
= b43_read16(dev
, 0x050E);
654 for (i
= 0x00; i
< 0x0A; i
++) {
655 value
= b43_read16(dev
, 0x050E);
660 for (i
= 0x00; i
< 0x0A; i
++) {
661 value
= b43_read16(dev
, 0x0690);
662 if (!(value
& 0x0100))
666 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
667 b43_radio_write16(dev
, 0x0051, 0x0037);
670 static void key_write(struct b43_wldev
*dev
,
671 u8 index
, u8 algorithm
, const u8
* key
)
678 /* Key index/algo block */
679 kidx
= b43_kidx_to_fw(dev
, index
);
680 value
= ((kidx
<< 4) | algorithm
);
681 b43_shm_write16(dev
, B43_SHM_SHARED
,
682 B43_SHM_SH_KEYIDXBLOCK
+ (kidx
* 2), value
);
684 /* Write the key to the Key Table Pointer offset */
685 offset
= dev
->ktp
+ (index
* B43_SEC_KEYSIZE
);
686 for (i
= 0; i
< B43_SEC_KEYSIZE
; i
+= 2) {
688 value
|= (u16
) (key
[i
+ 1]) << 8;
689 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
, value
);
693 static void keymac_write(struct b43_wldev
*dev
, u8 index
, const u8
* addr
)
695 u32 addrtmp
[2] = { 0, 0, };
696 u8 per_sta_keys_start
= 8;
698 if (b43_new_kidx_api(dev
))
699 per_sta_keys_start
= 4;
701 B43_WARN_ON(index
< per_sta_keys_start
);
702 /* We have two default TX keys and possibly two default RX keys.
703 * Physical mac 0 is mapped to physical key 4 or 8, depending
704 * on the firmware version.
705 * So we must adjust the index here.
707 index
-= per_sta_keys_start
;
710 addrtmp
[0] = addr
[0];
711 addrtmp
[0] |= ((u32
) (addr
[1]) << 8);
712 addrtmp
[0] |= ((u32
) (addr
[2]) << 16);
713 addrtmp
[0] |= ((u32
) (addr
[3]) << 24);
714 addrtmp
[1] = addr
[4];
715 addrtmp
[1] |= ((u32
) (addr
[5]) << 8);
718 if (dev
->dev
->id
.revision
>= 5) {
719 /* Receive match transmitter address mechanism */
720 b43_shm_write32(dev
, B43_SHM_RCMTA
,
721 (index
* 2) + 0, addrtmp
[0]);
722 b43_shm_write16(dev
, B43_SHM_RCMTA
,
723 (index
* 2) + 1, addrtmp
[1]);
725 /* RXE (Receive Engine) and
726 * PSM (Programmable State Machine) mechanism
729 /* TODO write to RCM 16, 19, 22 and 25 */
731 b43_shm_write32(dev
, B43_SHM_SHARED
,
732 B43_SHM_SH_PSM
+ (index
* 6) + 0,
734 b43_shm_write16(dev
, B43_SHM_SHARED
,
735 B43_SHM_SH_PSM
+ (index
* 6) + 4,
741 static void do_key_write(struct b43_wldev
*dev
,
742 u8 index
, u8 algorithm
,
743 const u8
* key
, size_t key_len
, const u8
* mac_addr
)
745 u8 buf
[B43_SEC_KEYSIZE
] = { 0, };
746 u8 per_sta_keys_start
= 8;
748 if (b43_new_kidx_api(dev
))
749 per_sta_keys_start
= 4;
751 B43_WARN_ON(index
>= dev
->max_nr_keys
);
752 B43_WARN_ON(key_len
> B43_SEC_KEYSIZE
);
754 if (index
>= per_sta_keys_start
)
755 keymac_write(dev
, index
, NULL
); /* First zero out mac. */
757 memcpy(buf
, key
, key_len
);
758 key_write(dev
, index
, algorithm
, buf
);
759 if (index
>= per_sta_keys_start
)
760 keymac_write(dev
, index
, mac_addr
);
762 dev
->key
[index
].algorithm
= algorithm
;
765 static int b43_key_write(struct b43_wldev
*dev
,
766 int index
, u8 algorithm
,
767 const u8
* key
, size_t key_len
,
769 struct ieee80211_key_conf
*keyconf
)
774 if (key_len
> B43_SEC_KEYSIZE
)
776 for (i
= 0; i
< dev
->max_nr_keys
; i
++) {
777 /* Check that we don't already have this key. */
778 B43_WARN_ON(dev
->key
[i
].keyconf
== keyconf
);
781 /* Either pairwise key or address is 00:00:00:00:00:00
782 * for transmit-only keys. Search the index. */
783 if (b43_new_kidx_api(dev
))
787 for (i
= sta_keys_start
; i
< dev
->max_nr_keys
; i
++) {
788 if (!dev
->key
[i
].keyconf
) {
795 b43err(dev
->wl
, "Out of hardware key memory\n");
799 B43_WARN_ON(index
> 3);
801 do_key_write(dev
, index
, algorithm
, key
, key_len
, mac_addr
);
802 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
804 B43_WARN_ON(mac_addr
);
805 do_key_write(dev
, index
+ 4, algorithm
, key
, key_len
, NULL
);
807 keyconf
->hw_key_idx
= index
;
808 dev
->key
[index
].keyconf
= keyconf
;
813 static int b43_key_clear(struct b43_wldev
*dev
, int index
)
815 if (B43_WARN_ON((index
< 0) || (index
>= dev
->max_nr_keys
)))
817 do_key_write(dev
, index
, B43_SEC_ALGO_NONE
,
818 NULL
, B43_SEC_KEYSIZE
, NULL
);
819 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
820 do_key_write(dev
, index
+ 4, B43_SEC_ALGO_NONE
,
821 NULL
, B43_SEC_KEYSIZE
, NULL
);
823 dev
->key
[index
].keyconf
= NULL
;
828 static void b43_clear_keys(struct b43_wldev
*dev
)
832 for (i
= 0; i
< dev
->max_nr_keys
; i
++)
833 b43_key_clear(dev
, i
);
836 void b43_power_saving_ctl_bits(struct b43_wldev
*dev
, unsigned int ps_flags
)
844 B43_WARN_ON((ps_flags
& B43_PS_ENABLED
) &&
845 (ps_flags
& B43_PS_DISABLED
));
846 B43_WARN_ON((ps_flags
& B43_PS_AWAKE
) && (ps_flags
& B43_PS_ASLEEP
));
848 if (ps_flags
& B43_PS_ENABLED
) {
850 } else if (ps_flags
& B43_PS_DISABLED
) {
853 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
854 // and thus is not an AP and we are associated, set bit 25
856 if (ps_flags
& B43_PS_AWAKE
) {
858 } else if (ps_flags
& B43_PS_ASLEEP
) {
861 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
862 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
863 // successful, set bit26
866 /* FIXME: For now we force awake-on and hwps-off */
870 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
872 macctl
|= B43_MACCTL_HWPS
;
874 macctl
&= ~B43_MACCTL_HWPS
;
876 macctl
|= B43_MACCTL_AWAKE
;
878 macctl
&= ~B43_MACCTL_AWAKE
;
879 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
881 b43_read32(dev
, B43_MMIO_MACCTL
);
882 if (awake
&& dev
->dev
->id
.revision
>= 5) {
883 /* Wait for the microcode to wake up. */
884 for (i
= 0; i
< 100; i
++) {
885 ucstat
= b43_shm_read16(dev
, B43_SHM_SHARED
,
886 B43_SHM_SH_UCODESTAT
);
887 if (ucstat
!= B43_SHM_SH_UCODESTAT_SLEEP
)
894 /* Turn the Analog ON/OFF */
895 static void b43_switch_analog(struct b43_wldev
*dev
, int on
)
897 b43_write16(dev
, B43_MMIO_PHY0
, on
? 0 : 0xF4);
900 void b43_wireless_core_reset(struct b43_wldev
*dev
, u32 flags
)
905 flags
|= B43_TMSLOW_PHYCLKEN
;
906 flags
|= B43_TMSLOW_PHYRESET
;
907 ssb_device_enable(dev
->dev
, flags
);
908 msleep(2); /* Wait for the PLL to turn on. */
910 /* Now take the PHY out of Reset again */
911 tmslow
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
912 tmslow
|= SSB_TMSLOW_FGC
;
913 tmslow
&= ~B43_TMSLOW_PHYRESET
;
914 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
915 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
917 tmslow
&= ~SSB_TMSLOW_FGC
;
918 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
919 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
923 b43_switch_analog(dev
, 1);
925 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
926 macctl
&= ~B43_MACCTL_GMODE
;
927 if (flags
& B43_TMSLOW_GMODE
)
928 macctl
|= B43_MACCTL_GMODE
;
929 macctl
|= B43_MACCTL_IHR_ENABLED
;
930 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
933 static void handle_irq_transmit_status(struct b43_wldev
*dev
)
937 struct b43_txstatus stat
;
940 v0
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
941 if (!(v0
& 0x00000001))
943 v1
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
945 stat
.cookie
= (v0
>> 16);
946 stat
.seq
= (v1
& 0x0000FFFF);
947 stat
.phy_stat
= ((v1
& 0x00FF0000) >> 16);
948 tmp
= (v0
& 0x0000FFFF);
949 stat
.frame_count
= ((tmp
& 0xF000) >> 12);
950 stat
.rts_count
= ((tmp
& 0x0F00) >> 8);
951 stat
.supp_reason
= ((tmp
& 0x001C) >> 2);
952 stat
.pm_indicated
= !!(tmp
& 0x0080);
953 stat
.intermediate
= !!(tmp
& 0x0040);
954 stat
.for_ampdu
= !!(tmp
& 0x0020);
955 stat
.acked
= !!(tmp
& 0x0002);
957 b43_handle_txstatus(dev
, &stat
);
961 static void drain_txstatus_queue(struct b43_wldev
*dev
)
965 if (dev
->dev
->id
.revision
< 5)
967 /* Read all entries from the microcode TXstatus FIFO
968 * and throw them away.
971 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
972 if (!(dummy
& 0x00000001))
974 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
978 static u32
b43_jssi_read(struct b43_wldev
*dev
)
982 val
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x08A);
984 val
|= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x088);
989 static void b43_jssi_write(struct b43_wldev
*dev
, u32 jssi
)
991 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x088, (jssi
& 0x0000FFFF));
992 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x08A, (jssi
& 0xFFFF0000) >> 16);
995 static void b43_generate_noise_sample(struct b43_wldev
*dev
)
997 b43_jssi_write(dev
, 0x7F7F7F7F);
998 b43_write32(dev
, B43_MMIO_MACCMD
,
999 b43_read32(dev
, B43_MMIO_MACCMD
) | B43_MACCMD_BGNOISE
);
1000 B43_WARN_ON(dev
->noisecalc
.channel_at_start
!= dev
->phy
.channel
);
1003 static void b43_calculate_link_quality(struct b43_wldev
*dev
)
1005 /* Top half of Link Quality calculation. */
1007 if (dev
->noisecalc
.calculation_running
)
1009 dev
->noisecalc
.channel_at_start
= dev
->phy
.channel
;
1010 dev
->noisecalc
.calculation_running
= 1;
1011 dev
->noisecalc
.nr_samples
= 0;
1013 b43_generate_noise_sample(dev
);
1016 static void handle_irq_noise(struct b43_wldev
*dev
)
1018 struct b43_phy
*phy
= &dev
->phy
;
1024 /* Bottom half of Link Quality calculation. */
1026 B43_WARN_ON(!dev
->noisecalc
.calculation_running
);
1027 if (dev
->noisecalc
.channel_at_start
!= phy
->channel
)
1028 goto drop_calculation
;
1029 *((__le32
*)noise
) = cpu_to_le32(b43_jssi_read(dev
));
1030 if (noise
[0] == 0x7F || noise
[1] == 0x7F ||
1031 noise
[2] == 0x7F || noise
[3] == 0x7F)
1034 /* Get the noise samples. */
1035 B43_WARN_ON(dev
->noisecalc
.nr_samples
>= 8);
1036 i
= dev
->noisecalc
.nr_samples
;
1037 noise
[0] = limit_value(noise
[0], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1038 noise
[1] = limit_value(noise
[1], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1039 noise
[2] = limit_value(noise
[2], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1040 noise
[3] = limit_value(noise
[3], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1041 dev
->noisecalc
.samples
[i
][0] = phy
->nrssi_lt
[noise
[0]];
1042 dev
->noisecalc
.samples
[i
][1] = phy
->nrssi_lt
[noise
[1]];
1043 dev
->noisecalc
.samples
[i
][2] = phy
->nrssi_lt
[noise
[2]];
1044 dev
->noisecalc
.samples
[i
][3] = phy
->nrssi_lt
[noise
[3]];
1045 dev
->noisecalc
.nr_samples
++;
1046 if (dev
->noisecalc
.nr_samples
== 8) {
1047 /* Calculate the Link Quality by the noise samples. */
1049 for (i
= 0; i
< 8; i
++) {
1050 for (j
= 0; j
< 4; j
++)
1051 average
+= dev
->noisecalc
.samples
[i
][j
];
1057 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x40C);
1058 tmp
= (tmp
/ 128) & 0x1F;
1068 dev
->stats
.link_noise
= average
;
1070 dev
->noisecalc
.calculation_running
= 0;
1074 b43_generate_noise_sample(dev
);
1077 static void handle_irq_tbtt_indication(struct b43_wldev
*dev
)
1079 if (b43_is_mode(dev
->wl
, IEEE80211_IF_TYPE_AP
)) {
1082 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1083 b43_power_saving_ctl_bits(dev
, 0);
1085 if (b43_is_mode(dev
->wl
, IEEE80211_IF_TYPE_IBSS
))
1089 static void handle_irq_atim_end(struct b43_wldev
*dev
)
1091 if (dev
->dfq_valid
) {
1092 b43_write32(dev
, B43_MMIO_MACCMD
,
1093 b43_read32(dev
, B43_MMIO_MACCMD
)
1094 | B43_MACCMD_DFQ_VALID
);
1099 static void handle_irq_pmq(struct b43_wldev
*dev
)
1106 tmp
= b43_read32(dev
, B43_MMIO_PS_STATUS
);
1107 if (!(tmp
& 0x00000008))
1110 /* 16bit write is odd, but correct. */
1111 b43_write16(dev
, B43_MMIO_PS_STATUS
, 0x0002);
1114 static void b43_write_template_common(struct b43_wldev
*dev
,
1115 const u8
* data
, u16 size
,
1117 u16 shm_size_offset
, u8 rate
)
1120 struct b43_plcp_hdr4 plcp
;
1123 b43_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1124 b43_ram_write(dev
, ram_offset
, le32_to_cpu(plcp
.data
));
1125 ram_offset
+= sizeof(u32
);
1126 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1127 * So leave the first two bytes of the next write blank.
1129 tmp
= (u32
) (data
[0]) << 16;
1130 tmp
|= (u32
) (data
[1]) << 24;
1131 b43_ram_write(dev
, ram_offset
, tmp
);
1132 ram_offset
+= sizeof(u32
);
1133 for (i
= 2; i
< size
; i
+= sizeof(u32
)) {
1134 tmp
= (u32
) (data
[i
+ 0]);
1136 tmp
|= (u32
) (data
[i
+ 1]) << 8;
1138 tmp
|= (u32
) (data
[i
+ 2]) << 16;
1140 tmp
|= (u32
) (data
[i
+ 3]) << 24;
1141 b43_ram_write(dev
, ram_offset
+ i
- 2, tmp
);
1143 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_size_offset
,
1144 size
+ sizeof(struct b43_plcp_hdr6
));
1147 static void b43_write_beacon_template(struct b43_wldev
*dev
,
1149 u16 shm_size_offset
, u8 rate
)
1152 const struct ieee80211_mgmt
*bcn
;
1156 bcn
= (const struct ieee80211_mgmt
*)(dev
->wl
->current_beacon
->data
);
1157 len
= min((size_t) dev
->wl
->current_beacon
->len
,
1158 0x200 - sizeof(struct b43_plcp_hdr6
));
1160 b43_write_template_common(dev
, (const u8
*)bcn
,
1161 len
, ram_offset
, shm_size_offset
, rate
);
1163 /* Find the position of the TIM and the DTIM_period value
1164 * and write them to SHM. */
1165 ie
= bcn
->u
.beacon
.variable
;
1166 for (i
= 0; i
< len
- 2; ) {
1167 uint8_t ie_id
, ie_len
;
1174 /* This is the TIM Information Element */
1176 /* Check whether the ie_len is in the beacon data range. */
1177 if (len
< ie_len
+ 2 + i
)
1179 /* A valid TIM is at least 4 bytes long. */
1184 tim_position
= sizeof(struct b43_plcp_hdr6
);
1185 tim_position
+= offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
);
1188 dtim_period
= ie
[i
+ 3];
1190 b43_shm_write16(dev
, B43_SHM_SHARED
,
1191 B43_SHM_SH_TIMBPOS
, tim_position
);
1192 b43_shm_write16(dev
, B43_SHM_SHARED
,
1193 B43_SHM_SH_DTIMPER
, dtim_period
);
1199 b43warn(dev
->wl
, "Did not find a valid TIM IE in "
1200 "the beacon template packet. AP or IBSS operation "
1201 "may be broken.\n");
1205 static void b43_write_probe_resp_plcp(struct b43_wldev
*dev
,
1206 u16 shm_offset
, u16 size
, u8 rate
)
1208 struct b43_plcp_hdr4 plcp
;
1213 b43_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1214 dur
= ieee80211_generic_frame_duration(dev
->wl
->hw
,
1216 B43_RATE_TO_BASE100KBPS(rate
));
1217 /* Write PLCP in two parts and timing for packet transfer */
1218 tmp
= le32_to_cpu(plcp
.data
);
1219 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
, tmp
& 0xFFFF);
1220 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
+ 2, tmp
>> 16);
1221 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
+ 6, le16_to_cpu(dur
));
1224 /* Instead of using custom probe response template, this function
1225 * just patches custom beacon template by:
1226 * 1) Changing packet type
1227 * 2) Patching duration field
1230 static const u8
* b43_generate_probe_resp(struct b43_wldev
*dev
,
1231 u16
*dest_size
, u8 rate
)
1235 u16 src_size
, elem_size
, src_pos
, dest_pos
;
1237 struct ieee80211_hdr
*hdr
;
1240 src_size
= dev
->wl
->current_beacon
->len
;
1241 src_data
= (const u8
*)dev
->wl
->current_beacon
->data
;
1243 /* Get the start offset of the variable IEs in the packet. */
1244 ie_start
= offsetof(struct ieee80211_mgmt
, u
.probe_resp
.variable
);
1245 B43_WARN_ON(ie_start
!= offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
));
1247 if (B43_WARN_ON(src_size
< ie_start
))
1250 dest_data
= kmalloc(src_size
, GFP_ATOMIC
);
1251 if (unlikely(!dest_data
))
1254 /* Copy the static data and all Information Elements, except the TIM. */
1255 memcpy(dest_data
, src_data
, ie_start
);
1257 dest_pos
= ie_start
;
1258 for ( ; src_pos
< src_size
- 2; src_pos
+= elem_size
) {
1259 elem_size
= src_data
[src_pos
+ 1] + 2;
1260 if (src_data
[src_pos
] == 5) {
1261 /* This is the TIM. */
1264 memcpy(dest_data
+ dest_pos
, src_data
+ src_pos
,
1266 dest_pos
+= elem_size
;
1268 *dest_size
= dest_pos
;
1269 hdr
= (struct ieee80211_hdr
*)dest_data
;
1271 /* Set the frame control. */
1272 hdr
->frame_control
= cpu_to_le16(IEEE80211_FTYPE_MGMT
|
1273 IEEE80211_STYPE_PROBE_RESP
);
1274 dur
= ieee80211_generic_frame_duration(dev
->wl
->hw
,
1275 dev
->wl
->vif
, *dest_size
,
1276 B43_RATE_TO_BASE100KBPS(rate
));
1277 hdr
->duration_id
= dur
;
1282 static void b43_write_probe_resp_template(struct b43_wldev
*dev
,
1284 u16 shm_size_offset
, u8 rate
)
1286 const u8
*probe_resp_data
;
1289 size
= dev
->wl
->current_beacon
->len
;
1290 probe_resp_data
= b43_generate_probe_resp(dev
, &size
, rate
);
1291 if (unlikely(!probe_resp_data
))
1294 /* Looks like PLCP headers plus packet timings are stored for
1295 * all possible basic rates
1297 b43_write_probe_resp_plcp(dev
, 0x31A, size
, B43_CCK_RATE_1MB
);
1298 b43_write_probe_resp_plcp(dev
, 0x32C, size
, B43_CCK_RATE_2MB
);
1299 b43_write_probe_resp_plcp(dev
, 0x33E, size
, B43_CCK_RATE_5MB
);
1300 b43_write_probe_resp_plcp(dev
, 0x350, size
, B43_CCK_RATE_11MB
);
1302 size
= min((size_t) size
, 0x200 - sizeof(struct b43_plcp_hdr6
));
1303 b43_write_template_common(dev
, probe_resp_data
,
1304 size
, ram_offset
, shm_size_offset
, rate
);
1305 kfree(probe_resp_data
);
1308 /* Asynchronously update the packet templates in template RAM.
1309 * Locking: Requires wl->irq_lock to be locked. */
1310 static void b43_update_templates(struct b43_wl
*wl
, struct sk_buff
*beacon
)
1312 /* This is the top half of the ansynchronous beacon update.
1313 * The bottom half is the beacon IRQ.
1314 * Beacon update must be asynchronous to avoid sending an
1315 * invalid beacon. This can happen for example, if the firmware
1316 * transmits a beacon while we are updating it. */
1318 if (wl
->current_beacon
)
1319 dev_kfree_skb_any(wl
->current_beacon
);
1320 wl
->current_beacon
= beacon
;
1321 wl
->beacon0_uploaded
= 0;
1322 wl
->beacon1_uploaded
= 0;
1325 static void b43_set_ssid(struct b43_wldev
*dev
, const u8
* ssid
, u8 ssid_len
)
1330 len
= min((u16
) ssid_len
, (u16
) 0x100);
1331 for (i
= 0; i
< len
; i
+= sizeof(u32
)) {
1332 tmp
= (u32
) (ssid
[i
+ 0]);
1334 tmp
|= (u32
) (ssid
[i
+ 1]) << 8;
1336 tmp
|= (u32
) (ssid
[i
+ 2]) << 16;
1338 tmp
|= (u32
) (ssid
[i
+ 3]) << 24;
1339 b43_shm_write32(dev
, B43_SHM_SHARED
, 0x380 + i
, tmp
);
1341 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x48, len
);
1344 static void b43_set_beacon_int(struct b43_wldev
*dev
, u16 beacon_int
)
1347 if (dev
->dev
->id
.revision
>= 3) {
1348 b43_write32(dev
, 0x188, (beacon_int
<< 16));
1350 b43_write16(dev
, 0x606, (beacon_int
>> 6));
1351 b43_write16(dev
, 0x610, beacon_int
);
1353 b43_time_unlock(dev
);
1356 static void handle_irq_beacon(struct b43_wldev
*dev
)
1358 struct b43_wl
*wl
= dev
->wl
;
1361 if (!b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
))
1364 /* This is the bottom half of the asynchronous beacon update. */
1366 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1367 if (!(cmd
& B43_MACCMD_BEACON0_VALID
)) {
1368 if (!wl
->beacon0_uploaded
) {
1369 b43_write_beacon_template(dev
, 0x68, 0x18,
1371 b43_write_probe_resp_template(dev
, 0x268, 0x4A,
1373 wl
->beacon0_uploaded
= 1;
1375 cmd
|= B43_MACCMD_BEACON0_VALID
;
1377 if (!(cmd
& B43_MACCMD_BEACON1_VALID
)) {
1378 if (!wl
->beacon1_uploaded
) {
1379 b43_write_beacon_template(dev
, 0x468, 0x1A,
1381 wl
->beacon1_uploaded
= 1;
1383 cmd
|= B43_MACCMD_BEACON1_VALID
;
1385 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1388 static void handle_irq_ucode_debug(struct b43_wldev
*dev
)
1393 /* Interrupt handler bottom-half */
1394 static void b43_interrupt_tasklet(struct b43_wldev
*dev
)
1397 u32 dma_reason
[ARRAY_SIZE(dev
->dma_reason
)];
1398 u32 merged_dma_reason
= 0;
1400 unsigned long flags
;
1402 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
1404 B43_WARN_ON(b43_status(dev
) != B43_STAT_STARTED
);
1406 reason
= dev
->irq_reason
;
1407 for (i
= 0; i
< ARRAY_SIZE(dma_reason
); i
++) {
1408 dma_reason
[i
] = dev
->dma_reason
[i
];
1409 merged_dma_reason
|= dma_reason
[i
];
1412 if (unlikely(reason
& B43_IRQ_MAC_TXERR
))
1413 b43err(dev
->wl
, "MAC transmission error\n");
1415 if (unlikely(reason
& B43_IRQ_PHY_TXERR
)) {
1416 b43err(dev
->wl
, "PHY transmission error\n");
1418 if (unlikely(atomic_dec_and_test(&dev
->phy
.txerr_cnt
))) {
1419 atomic_set(&dev
->phy
.txerr_cnt
,
1420 B43_PHY_TX_BADNESS_LIMIT
);
1421 b43err(dev
->wl
, "Too many PHY TX errors, "
1422 "restarting the controller\n");
1423 b43_controller_restart(dev
, "PHY TX errors");
1427 if (unlikely(merged_dma_reason
& (B43_DMAIRQ_FATALMASK
|
1428 B43_DMAIRQ_NONFATALMASK
))) {
1429 if (merged_dma_reason
& B43_DMAIRQ_FATALMASK
) {
1430 b43err(dev
->wl
, "Fatal DMA error: "
1431 "0x%08X, 0x%08X, 0x%08X, "
1432 "0x%08X, 0x%08X, 0x%08X\n",
1433 dma_reason
[0], dma_reason
[1],
1434 dma_reason
[2], dma_reason
[3],
1435 dma_reason
[4], dma_reason
[5]);
1436 b43_controller_restart(dev
, "DMA error");
1438 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
1441 if (merged_dma_reason
& B43_DMAIRQ_NONFATALMASK
) {
1442 b43err(dev
->wl
, "DMA error: "
1443 "0x%08X, 0x%08X, 0x%08X, "
1444 "0x%08X, 0x%08X, 0x%08X\n",
1445 dma_reason
[0], dma_reason
[1],
1446 dma_reason
[2], dma_reason
[3],
1447 dma_reason
[4], dma_reason
[5]);
1451 if (unlikely(reason
& B43_IRQ_UCODE_DEBUG
))
1452 handle_irq_ucode_debug(dev
);
1453 if (reason
& B43_IRQ_TBTT_INDI
)
1454 handle_irq_tbtt_indication(dev
);
1455 if (reason
& B43_IRQ_ATIM_END
)
1456 handle_irq_atim_end(dev
);
1457 if (reason
& B43_IRQ_BEACON
)
1458 handle_irq_beacon(dev
);
1459 if (reason
& B43_IRQ_PMQ
)
1460 handle_irq_pmq(dev
);
1461 if (reason
& B43_IRQ_TXFIFO_FLUSH_OK
)
1463 if (reason
& B43_IRQ_NOISESAMPLE_OK
)
1464 handle_irq_noise(dev
);
1466 /* Check the DMA reason registers for received data. */
1467 if (dma_reason
[0] & B43_DMAIRQ_RX_DONE
)
1468 b43_dma_rx(dev
->dma
.rx_ring0
);
1469 if (dma_reason
[3] & B43_DMAIRQ_RX_DONE
)
1470 b43_dma_rx(dev
->dma
.rx_ring3
);
1471 B43_WARN_ON(dma_reason
[1] & B43_DMAIRQ_RX_DONE
);
1472 B43_WARN_ON(dma_reason
[2] & B43_DMAIRQ_RX_DONE
);
1473 B43_WARN_ON(dma_reason
[4] & B43_DMAIRQ_RX_DONE
);
1474 B43_WARN_ON(dma_reason
[5] & B43_DMAIRQ_RX_DONE
);
1476 if (reason
& B43_IRQ_TX_OK
)
1477 handle_irq_transmit_status(dev
);
1479 b43_interrupt_enable(dev
, dev
->irq_savedstate
);
1481 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
1484 static void b43_interrupt_ack(struct b43_wldev
*dev
, u32 reason
)
1486 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, reason
);
1488 b43_write32(dev
, B43_MMIO_DMA0_REASON
, dev
->dma_reason
[0]);
1489 b43_write32(dev
, B43_MMIO_DMA1_REASON
, dev
->dma_reason
[1]);
1490 b43_write32(dev
, B43_MMIO_DMA2_REASON
, dev
->dma_reason
[2]);
1491 b43_write32(dev
, B43_MMIO_DMA3_REASON
, dev
->dma_reason
[3]);
1492 b43_write32(dev
, B43_MMIO_DMA4_REASON
, dev
->dma_reason
[4]);
1493 b43_write32(dev
, B43_MMIO_DMA5_REASON
, dev
->dma_reason
[5]);
1496 /* Interrupt handler top-half */
1497 static irqreturn_t
b43_interrupt_handler(int irq
, void *dev_id
)
1499 irqreturn_t ret
= IRQ_NONE
;
1500 struct b43_wldev
*dev
= dev_id
;
1506 spin_lock(&dev
->wl
->irq_lock
);
1508 if (b43_status(dev
) < B43_STAT_STARTED
)
1510 reason
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
1511 if (reason
== 0xffffffff) /* shared IRQ */
1514 reason
&= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
1518 dev
->dma_reason
[0] = b43_read32(dev
, B43_MMIO_DMA0_REASON
)
1520 dev
->dma_reason
[1] = b43_read32(dev
, B43_MMIO_DMA1_REASON
)
1522 dev
->dma_reason
[2] = b43_read32(dev
, B43_MMIO_DMA2_REASON
)
1524 dev
->dma_reason
[3] = b43_read32(dev
, B43_MMIO_DMA3_REASON
)
1526 dev
->dma_reason
[4] = b43_read32(dev
, B43_MMIO_DMA4_REASON
)
1528 dev
->dma_reason
[5] = b43_read32(dev
, B43_MMIO_DMA5_REASON
)
1531 b43_interrupt_ack(dev
, reason
);
1532 /* disable all IRQs. They are enabled again in the bottom half. */
1533 dev
->irq_savedstate
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
1534 /* save the reason code and call our bottom half. */
1535 dev
->irq_reason
= reason
;
1536 tasklet_schedule(&dev
->isr_tasklet
);
1539 spin_unlock(&dev
->wl
->irq_lock
);
1544 static void b43_release_firmware(struct b43_wldev
*dev
)
1546 release_firmware(dev
->fw
.ucode
);
1547 dev
->fw
.ucode
= NULL
;
1548 release_firmware(dev
->fw
.pcm
);
1550 release_firmware(dev
->fw
.initvals
);
1551 dev
->fw
.initvals
= NULL
;
1552 release_firmware(dev
->fw
.initvals_band
);
1553 dev
->fw
.initvals_band
= NULL
;
1556 static void b43_print_fw_helptext(struct b43_wl
*wl
)
1558 b43err(wl
, "You must go to "
1559 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1560 "and download the correct firmware (version 4).\n");
1563 static int do_request_fw(struct b43_wldev
*dev
,
1565 const struct firmware
**fw
)
1567 char path
[sizeof(modparam_fwpostfix
) + 32];
1568 struct b43_fw_header
*hdr
;
1575 snprintf(path
, ARRAY_SIZE(path
),
1577 modparam_fwpostfix
, name
);
1578 err
= request_firmware(fw
, path
, dev
->dev
->dev
);
1580 b43err(dev
->wl
, "Firmware file \"%s\" not found "
1581 "or load failed.\n", path
);
1584 if ((*fw
)->size
< sizeof(struct b43_fw_header
))
1586 hdr
= (struct b43_fw_header
*)((*fw
)->data
);
1587 switch (hdr
->type
) {
1588 case B43_FW_TYPE_UCODE
:
1589 case B43_FW_TYPE_PCM
:
1590 size
= be32_to_cpu(hdr
->size
);
1591 if (size
!= (*fw
)->size
- sizeof(struct b43_fw_header
))
1594 case B43_FW_TYPE_IV
:
1605 b43err(dev
->wl
, "Firmware file \"%s\" format error.\n", path
);
1609 static int b43_request_firmware(struct b43_wldev
*dev
)
1611 struct b43_firmware
*fw
= &dev
->fw
;
1612 const u8 rev
= dev
->dev
->id
.revision
;
1613 const char *filename
;
1617 tmshigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
1619 if ((rev
>= 5) && (rev
<= 10))
1620 filename
= "ucode5";
1621 else if ((rev
>= 11) && (rev
<= 12))
1622 filename
= "ucode11";
1624 filename
= "ucode13";
1627 err
= do_request_fw(dev
, filename
, &fw
->ucode
);
1632 if ((rev
>= 5) && (rev
<= 10))
1638 err
= do_request_fw(dev
, filename
, &fw
->pcm
);
1642 if (!fw
->initvals
) {
1643 switch (dev
->phy
.type
) {
1645 if ((rev
>= 5) && (rev
<= 10)) {
1646 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
1647 filename
= "a0g1initvals5";
1649 filename
= "a0g0initvals5";
1651 goto err_no_initvals
;
1654 if ((rev
>= 5) && (rev
<= 10))
1655 filename
= "b0g0initvals5";
1657 filename
= "lp0initvals13";
1659 goto err_no_initvals
;
1662 goto err_no_initvals
;
1664 err
= do_request_fw(dev
, filename
, &fw
->initvals
);
1668 if (!fw
->initvals_band
) {
1669 switch (dev
->phy
.type
) {
1671 if ((rev
>= 5) && (rev
<= 10)) {
1672 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
1673 filename
= "a0g1bsinitvals5";
1675 filename
= "a0g0bsinitvals5";
1676 } else if (rev
>= 11)
1679 goto err_no_initvals
;
1682 if ((rev
>= 5) && (rev
<= 10))
1683 filename
= "b0g0bsinitvals5";
1687 goto err_no_initvals
;
1690 goto err_no_initvals
;
1692 err
= do_request_fw(dev
, filename
, &fw
->initvals_band
);
1700 b43_print_fw_helptext(dev
->wl
);
1705 b43err(dev
->wl
, "No microcode available for core rev %u\n", rev
);
1710 b43err(dev
->wl
, "No PCM available for core rev %u\n", rev
);
1715 b43err(dev
->wl
, "No Initial Values firmware file for PHY %u, "
1716 "core rev %u\n", dev
->phy
.type
, rev
);
1720 b43_release_firmware(dev
);
1724 static int b43_upload_microcode(struct b43_wldev
*dev
)
1726 const size_t hdr_len
= sizeof(struct b43_fw_header
);
1728 unsigned int i
, len
;
1729 u16 fwrev
, fwpatch
, fwdate
, fwtime
;
1733 /* Upload Microcode. */
1734 data
= (__be32
*) (dev
->fw
.ucode
->data
+ hdr_len
);
1735 len
= (dev
->fw
.ucode
->size
- hdr_len
) / sizeof(__be32
);
1736 b43_shm_control_word(dev
, B43_SHM_UCODE
| B43_SHM_AUTOINC_W
, 0x0000);
1737 for (i
= 0; i
< len
; i
++) {
1738 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
1743 /* Upload PCM data. */
1744 data
= (__be32
*) (dev
->fw
.pcm
->data
+ hdr_len
);
1745 len
= (dev
->fw
.pcm
->size
- hdr_len
) / sizeof(__be32
);
1746 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EA);
1747 b43_write32(dev
, B43_MMIO_SHM_DATA
, 0x00004000);
1748 /* No need for autoinc bit in SHM_HW */
1749 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EB);
1750 for (i
= 0; i
< len
; i
++) {
1751 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
1756 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_ALL
);
1757 b43_write32(dev
, B43_MMIO_MACCTL
,
1758 B43_MACCTL_PSM_RUN
|
1759 B43_MACCTL_IHR_ENABLED
| B43_MACCTL_INFRA
);
1761 /* Wait for the microcode to load and respond */
1764 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
1765 if (tmp
== B43_IRQ_MAC_SUSPENDED
)
1769 b43err(dev
->wl
, "Microcode not responding\n");
1770 b43_print_fw_helptext(dev
->wl
);
1776 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
); /* dummy read */
1778 /* Get and check the revisions. */
1779 fwrev
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEREV
);
1780 fwpatch
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEPATCH
);
1781 fwdate
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEDATE
);
1782 fwtime
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODETIME
);
1784 if (fwrev
<= 0x128) {
1785 b43err(dev
->wl
, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1786 "binary drivers older than version 4.x is unsupported. "
1787 "You must upgrade your firmware files.\n");
1788 b43_print_fw_helptext(dev
->wl
);
1789 b43_write32(dev
, B43_MMIO_MACCTL
, 0);
1793 b43dbg(dev
->wl
, "Loading firmware version %u.%u "
1794 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1796 (fwdate
>> 12) & 0xF, (fwdate
>> 8) & 0xF, fwdate
& 0xFF,
1797 (fwtime
>> 11) & 0x1F, (fwtime
>> 5) & 0x3F, fwtime
& 0x1F);
1799 dev
->fw
.rev
= fwrev
;
1800 dev
->fw
.patch
= fwpatch
;
1806 static int b43_write_initvals(struct b43_wldev
*dev
,
1807 const struct b43_iv
*ivals
,
1811 const struct b43_iv
*iv
;
1816 BUILD_BUG_ON(sizeof(struct b43_iv
) != 6);
1818 for (i
= 0; i
< count
; i
++) {
1819 if (array_size
< sizeof(iv
->offset_size
))
1821 array_size
-= sizeof(iv
->offset_size
);
1822 offset
= be16_to_cpu(iv
->offset_size
);
1823 bit32
= !!(offset
& B43_IV_32BIT
);
1824 offset
&= B43_IV_OFFSET_MASK
;
1825 if (offset
>= 0x1000)
1830 if (array_size
< sizeof(iv
->data
.d32
))
1832 array_size
-= sizeof(iv
->data
.d32
);
1834 value
= be32_to_cpu(get_unaligned(&iv
->data
.d32
));
1835 b43_write32(dev
, offset
, value
);
1837 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
1843 if (array_size
< sizeof(iv
->data
.d16
))
1845 array_size
-= sizeof(iv
->data
.d16
);
1847 value
= be16_to_cpu(iv
->data
.d16
);
1848 b43_write16(dev
, offset
, value
);
1850 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
1861 b43err(dev
->wl
, "Initial Values Firmware file-format error.\n");
1862 b43_print_fw_helptext(dev
->wl
);
1867 static int b43_upload_initvals(struct b43_wldev
*dev
)
1869 const size_t hdr_len
= sizeof(struct b43_fw_header
);
1870 const struct b43_fw_header
*hdr
;
1871 struct b43_firmware
*fw
= &dev
->fw
;
1872 const struct b43_iv
*ivals
;
1876 hdr
= (const struct b43_fw_header
*)(fw
->initvals
->data
);
1877 ivals
= (const struct b43_iv
*)(fw
->initvals
->data
+ hdr_len
);
1878 count
= be32_to_cpu(hdr
->size
);
1879 err
= b43_write_initvals(dev
, ivals
, count
,
1880 fw
->initvals
->size
- hdr_len
);
1883 if (fw
->initvals_band
) {
1884 hdr
= (const struct b43_fw_header
*)(fw
->initvals_band
->data
);
1885 ivals
= (const struct b43_iv
*)(fw
->initvals_band
->data
+ hdr_len
);
1886 count
= be32_to_cpu(hdr
->size
);
1887 err
= b43_write_initvals(dev
, ivals
, count
,
1888 fw
->initvals_band
->size
- hdr_len
);
1897 /* Initialize the GPIOs
1898 * http://bcm-specs.sipsolutions.net/GPIO
1900 static int b43_gpio_init(struct b43_wldev
*dev
)
1902 struct ssb_bus
*bus
= dev
->dev
->bus
;
1903 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
1906 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
1907 & ~B43_MACCTL_GPOUTSMSK
);
1909 b43_write16(dev
, B43_MMIO_GPIO_MASK
, b43_read16(dev
, B43_MMIO_GPIO_MASK
)
1914 if (dev
->dev
->bus
->chip_id
== 0x4301) {
1918 if (0 /* FIXME: conditional unknown */ ) {
1919 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
1920 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
1925 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_PACTRL
) {
1926 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
1927 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
1932 if (dev
->dev
->id
.revision
>= 2)
1933 mask
|= 0x0010; /* FIXME: This is redundant. */
1935 #ifdef CONFIG_SSB_DRIVER_PCICORE
1936 pcidev
= bus
->pcicore
.dev
;
1938 gpiodev
= bus
->chipco
.dev
? : pcidev
;
1941 ssb_write32(gpiodev
, B43_GPIO_CONTROL
,
1942 (ssb_read32(gpiodev
, B43_GPIO_CONTROL
)
1948 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1949 static void b43_gpio_cleanup(struct b43_wldev
*dev
)
1951 struct ssb_bus
*bus
= dev
->dev
->bus
;
1952 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
1954 #ifdef CONFIG_SSB_DRIVER_PCICORE
1955 pcidev
= bus
->pcicore
.dev
;
1957 gpiodev
= bus
->chipco
.dev
? : pcidev
;
1960 ssb_write32(gpiodev
, B43_GPIO_CONTROL
, 0);
1963 /* http://bcm-specs.sipsolutions.net/EnableMac */
1964 void b43_mac_enable(struct b43_wldev
*dev
)
1966 dev
->mac_suspended
--;
1967 B43_WARN_ON(dev
->mac_suspended
< 0);
1968 B43_WARN_ON(irqs_disabled());
1969 if (dev
->mac_suspended
== 0) {
1970 b43_write32(dev
, B43_MMIO_MACCTL
,
1971 b43_read32(dev
, B43_MMIO_MACCTL
)
1972 | B43_MACCTL_ENABLED
);
1973 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
,
1974 B43_IRQ_MAC_SUSPENDED
);
1976 b43_read32(dev
, B43_MMIO_MACCTL
);
1977 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
1978 b43_power_saving_ctl_bits(dev
, 0);
1980 /* Re-enable IRQs. */
1981 spin_lock_irq(&dev
->wl
->irq_lock
);
1982 b43_interrupt_enable(dev
, dev
->irq_savedstate
);
1983 spin_unlock_irq(&dev
->wl
->irq_lock
);
1987 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1988 void b43_mac_suspend(struct b43_wldev
*dev
)
1994 B43_WARN_ON(irqs_disabled());
1995 B43_WARN_ON(dev
->mac_suspended
< 0);
1997 if (dev
->mac_suspended
== 0) {
1998 /* Mask IRQs before suspending MAC. Otherwise
1999 * the MAC stays busy and won't suspend. */
2000 spin_lock_irq(&dev
->wl
->irq_lock
);
2001 tmp
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
2002 spin_unlock_irq(&dev
->wl
->irq_lock
);
2003 b43_synchronize_irq(dev
);
2004 dev
->irq_savedstate
= tmp
;
2006 b43_power_saving_ctl_bits(dev
, B43_PS_AWAKE
);
2007 b43_write32(dev
, B43_MMIO_MACCTL
,
2008 b43_read32(dev
, B43_MMIO_MACCTL
)
2009 & ~B43_MACCTL_ENABLED
);
2010 /* force pci to flush the write */
2011 b43_read32(dev
, B43_MMIO_MACCTL
);
2012 for (i
= 40; i
; i
--) {
2013 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2014 if (tmp
& B43_IRQ_MAC_SUSPENDED
)
2018 b43err(dev
->wl
, "MAC suspend failed\n");
2021 dev
->mac_suspended
++;
2024 static void b43_adjust_opmode(struct b43_wldev
*dev
)
2026 struct b43_wl
*wl
= dev
->wl
;
2030 ctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2031 /* Reset status to STA infrastructure mode. */
2032 ctl
&= ~B43_MACCTL_AP
;
2033 ctl
&= ~B43_MACCTL_KEEP_CTL
;
2034 ctl
&= ~B43_MACCTL_KEEP_BADPLCP
;
2035 ctl
&= ~B43_MACCTL_KEEP_BAD
;
2036 ctl
&= ~B43_MACCTL_PROMISC
;
2037 ctl
&= ~B43_MACCTL_BEACPROMISC
;
2038 ctl
|= B43_MACCTL_INFRA
;
2040 if (b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
))
2041 ctl
|= B43_MACCTL_AP
;
2042 else if (b43_is_mode(wl
, IEEE80211_IF_TYPE_IBSS
))
2043 ctl
&= ~B43_MACCTL_INFRA
;
2045 if (wl
->filter_flags
& FIF_CONTROL
)
2046 ctl
|= B43_MACCTL_KEEP_CTL
;
2047 if (wl
->filter_flags
& FIF_FCSFAIL
)
2048 ctl
|= B43_MACCTL_KEEP_BAD
;
2049 if (wl
->filter_flags
& FIF_PLCPFAIL
)
2050 ctl
|= B43_MACCTL_KEEP_BADPLCP
;
2051 if (wl
->filter_flags
& FIF_PROMISC_IN_BSS
)
2052 ctl
|= B43_MACCTL_PROMISC
;
2053 if (wl
->filter_flags
& FIF_BCN_PRBRESP_PROMISC
)
2054 ctl
|= B43_MACCTL_BEACPROMISC
;
2056 /* Workaround: On old hardware the HW-MAC-address-filter
2057 * doesn't work properly, so always run promisc in filter
2058 * it in software. */
2059 if (dev
->dev
->id
.revision
<= 4)
2060 ctl
|= B43_MACCTL_PROMISC
;
2062 b43_write32(dev
, B43_MMIO_MACCTL
, ctl
);
2065 if ((ctl
& B43_MACCTL_INFRA
) && !(ctl
& B43_MACCTL_AP
)) {
2066 if (dev
->dev
->bus
->chip_id
== 0x4306 &&
2067 dev
->dev
->bus
->chip_rev
== 3)
2072 b43_write16(dev
, 0x612, cfp_pretbtt
);
2075 static void b43_rate_memory_write(struct b43_wldev
*dev
, u16 rate
, int is_ofdm
)
2081 offset
+= (b43_plcp_get_ratecode_ofdm(rate
) & 0x000F) * 2;
2084 offset
+= (b43_plcp_get_ratecode_cck(rate
) & 0x000F) * 2;
2086 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ 0x20,
2087 b43_shm_read16(dev
, B43_SHM_SHARED
, offset
));
2090 static void b43_rate_memory_init(struct b43_wldev
*dev
)
2092 switch (dev
->phy
.type
) {
2095 b43_rate_memory_write(dev
, B43_OFDM_RATE_6MB
, 1);
2096 b43_rate_memory_write(dev
, B43_OFDM_RATE_12MB
, 1);
2097 b43_rate_memory_write(dev
, B43_OFDM_RATE_18MB
, 1);
2098 b43_rate_memory_write(dev
, B43_OFDM_RATE_24MB
, 1);
2099 b43_rate_memory_write(dev
, B43_OFDM_RATE_36MB
, 1);
2100 b43_rate_memory_write(dev
, B43_OFDM_RATE_48MB
, 1);
2101 b43_rate_memory_write(dev
, B43_OFDM_RATE_54MB
, 1);
2102 if (dev
->phy
.type
== B43_PHYTYPE_A
)
2106 b43_rate_memory_write(dev
, B43_CCK_RATE_1MB
, 0);
2107 b43_rate_memory_write(dev
, B43_CCK_RATE_2MB
, 0);
2108 b43_rate_memory_write(dev
, B43_CCK_RATE_5MB
, 0);
2109 b43_rate_memory_write(dev
, B43_CCK_RATE_11MB
, 0);
2116 /* Set the TX-Antenna for management frames sent by firmware. */
2117 static void b43_mgmtframe_txantenna(struct b43_wldev
*dev
, int antenna
)
2124 ant
|= B43_TX4_PHY_ANT0
;
2127 ant
|= B43_TX4_PHY_ANT1
;
2129 case B43_ANTENNA_AUTO
:
2130 ant
|= B43_TX4_PHY_ANTLAST
;
2136 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2139 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
);
2140 tmp
= (tmp
& ~B43_TX4_PHY_ANT
) | ant
;
2141 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
, tmp
);
2143 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
);
2144 tmp
= (tmp
& ~B43_TX4_PHY_ANT
) | ant
;
2145 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
, tmp
);
2146 /* For Probe Resposes */
2147 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
);
2148 tmp
= (tmp
& ~B43_TX4_PHY_ANT
) | ant
;
2149 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
, tmp
);
2152 /* This is the opposite of b43_chip_init() */
2153 static void b43_chip_exit(struct b43_wldev
*dev
)
2155 b43_radio_turn_off(dev
, 1);
2156 b43_gpio_cleanup(dev
);
2157 /* firmware is released later */
2160 /* Initialize the chip
2161 * http://bcm-specs.sipsolutions.net/ChipInit
2163 static int b43_chip_init(struct b43_wldev
*dev
)
2165 struct b43_phy
*phy
= &dev
->phy
;
2170 b43_write32(dev
, B43_MMIO_MACCTL
,
2171 B43_MACCTL_PSM_JMP0
| B43_MACCTL_IHR_ENABLED
);
2173 err
= b43_request_firmware(dev
);
2176 err
= b43_upload_microcode(dev
);
2178 goto out
; /* firmware is released later */
2180 err
= b43_gpio_init(dev
);
2182 goto out
; /* firmware is released later */
2184 err
= b43_upload_initvals(dev
);
2186 goto err_gpio_clean
;
2187 b43_radio_turn_on(dev
);
2189 b43_write16(dev
, 0x03E6, 0x0000);
2190 err
= b43_phy_init(dev
);
2194 /* Select initial Interference Mitigation. */
2195 tmp
= phy
->interfmode
;
2196 phy
->interfmode
= B43_INTERFMODE_NONE
;
2197 b43_radio_set_interference_mitigation(dev
, tmp
);
2199 b43_set_rx_antenna(dev
, B43_ANTENNA_DEFAULT
);
2200 b43_mgmtframe_txantenna(dev
, B43_ANTENNA_DEFAULT
);
2202 if (phy
->type
== B43_PHYTYPE_B
) {
2203 value16
= b43_read16(dev
, 0x005E);
2205 b43_write16(dev
, 0x005E, value16
);
2207 b43_write32(dev
, 0x0100, 0x01000000);
2208 if (dev
->dev
->id
.revision
< 5)
2209 b43_write32(dev
, 0x010C, 0x01000000);
2211 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2212 & ~B43_MACCTL_INFRA
);
2213 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2214 | B43_MACCTL_INFRA
);
2216 /* Probe Response Timeout value */
2217 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2218 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0074, 0x0000);
2220 /* Initially set the wireless operation mode. */
2221 b43_adjust_opmode(dev
);
2223 if (dev
->dev
->id
.revision
< 3) {
2224 b43_write16(dev
, 0x060E, 0x0000);
2225 b43_write16(dev
, 0x0610, 0x8000);
2226 b43_write16(dev
, 0x0604, 0x0000);
2227 b43_write16(dev
, 0x0606, 0x0200);
2229 b43_write32(dev
, 0x0188, 0x80000000);
2230 b43_write32(dev
, 0x018C, 0x02000000);
2232 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, 0x00004000);
2233 b43_write32(dev
, B43_MMIO_DMA0_IRQ_MASK
, 0x0001DC00);
2234 b43_write32(dev
, B43_MMIO_DMA1_IRQ_MASK
, 0x0000DC00);
2235 b43_write32(dev
, B43_MMIO_DMA2_IRQ_MASK
, 0x0000DC00);
2236 b43_write32(dev
, B43_MMIO_DMA3_IRQ_MASK
, 0x0001DC00);
2237 b43_write32(dev
, B43_MMIO_DMA4_IRQ_MASK
, 0x0000DC00);
2238 b43_write32(dev
, B43_MMIO_DMA5_IRQ_MASK
, 0x0000DC00);
2240 value32
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
2241 value32
|= 0x00100000;
2242 ssb_write32(dev
->dev
, SSB_TMSLOW
, value32
);
2244 b43_write16(dev
, B43_MMIO_POWERUP_DELAY
,
2245 dev
->dev
->bus
->chipco
.fast_pwrup_delay
);
2248 b43dbg(dev
->wl
, "Chip initialized\n");
2253 b43_radio_turn_off(dev
, 1);
2255 b43_gpio_cleanup(dev
);
2259 static void b43_periodic_every120sec(struct b43_wldev
*dev
)
2261 struct b43_phy
*phy
= &dev
->phy
;
2263 if (phy
->type
!= B43_PHYTYPE_G
|| phy
->rev
< 2)
2266 b43_mac_suspend(dev
);
2267 b43_lo_g_measure(dev
);
2268 b43_mac_enable(dev
);
2269 if (b43_has_hardware_pctl(phy
))
2270 b43_lo_g_ctl_mark_all_unused(dev
);
2273 static void b43_periodic_every60sec(struct b43_wldev
*dev
)
2275 struct b43_phy
*phy
= &dev
->phy
;
2277 if (!b43_has_hardware_pctl(phy
))
2278 b43_lo_g_ctl_mark_all_unused(dev
);
2279 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_RSSI
) {
2280 b43_mac_suspend(dev
);
2281 b43_calc_nrssi_slope(dev
);
2282 if ((phy
->radio_ver
== 0x2050) && (phy
->radio_rev
== 8)) {
2283 u8 old_chan
= phy
->channel
;
2285 /* VCO Calibration */
2287 b43_radio_selectchannel(dev
, 1, 0);
2289 b43_radio_selectchannel(dev
, 13, 0);
2290 b43_radio_selectchannel(dev
, old_chan
, 0);
2292 b43_mac_enable(dev
);
2296 static void b43_periodic_every30sec(struct b43_wldev
*dev
)
2298 /* Update device statistics. */
2299 b43_calculate_link_quality(dev
);
2302 static void b43_periodic_every15sec(struct b43_wldev
*dev
)
2304 struct b43_phy
*phy
= &dev
->phy
;
2306 if (phy
->type
== B43_PHYTYPE_G
) {
2307 //TODO: update_aci_moving_average
2308 if (phy
->aci_enable
&& phy
->aci_wlan_automatic
) {
2309 b43_mac_suspend(dev
);
2310 if (!phy
->aci_enable
&& 1 /*TODO: not scanning? */ ) {
2311 if (0 /*TODO: bunch of conditions */ ) {
2312 b43_radio_set_interference_mitigation
2313 (dev
, B43_INTERFMODE_MANUALWLAN
);
2315 } else if (1 /*TODO*/) {
2317 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2318 b43_radio_set_interference_mitigation(dev,
2319 B43_INTERFMODE_NONE);
2323 b43_mac_enable(dev
);
2324 } else if (phy
->interfmode
== B43_INTERFMODE_NONWLAN
&&
2326 //TODO: implement rev1 workaround
2329 b43_phy_xmitpower(dev
); //FIXME: unless scanning?
2330 //TODO for APHY (temperature?)
2332 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
2336 static void do_periodic_work(struct b43_wldev
*dev
)
2340 state
= dev
->periodic_state
;
2342 b43_periodic_every120sec(dev
);
2344 b43_periodic_every60sec(dev
);
2346 b43_periodic_every30sec(dev
);
2347 b43_periodic_every15sec(dev
);
2350 /* Periodic work locking policy:
2351 * The whole periodic work handler is protected by
2352 * wl->mutex. If another lock is needed somewhere in the
2353 * pwork callchain, it's aquired in-place, where it's needed.
2355 static void b43_periodic_work_handler(struct work_struct
*work
)
2357 struct b43_wldev
*dev
= container_of(work
, struct b43_wldev
,
2358 periodic_work
.work
);
2359 struct b43_wl
*wl
= dev
->wl
;
2360 unsigned long delay
;
2362 mutex_lock(&wl
->mutex
);
2364 if (unlikely(b43_status(dev
) != B43_STAT_STARTED
))
2366 if (b43_debug(dev
, B43_DBG_PWORK_STOP
))
2369 do_periodic_work(dev
);
2371 dev
->periodic_state
++;
2373 if (b43_debug(dev
, B43_DBG_PWORK_FAST
))
2374 delay
= msecs_to_jiffies(50);
2376 delay
= round_jiffies_relative(HZ
* 15);
2377 queue_delayed_work(wl
->hw
->workqueue
, &dev
->periodic_work
, delay
);
2379 mutex_unlock(&wl
->mutex
);
2382 static void b43_periodic_tasks_setup(struct b43_wldev
*dev
)
2384 struct delayed_work
*work
= &dev
->periodic_work
;
2386 dev
->periodic_state
= 0;
2387 INIT_DELAYED_WORK(work
, b43_periodic_work_handler
);
2388 queue_delayed_work(dev
->wl
->hw
->workqueue
, work
, 0);
2391 /* Check if communication with the device works correctly. */
2392 static int b43_validate_chipaccess(struct b43_wldev
*dev
)
2396 backup
= b43_shm_read32(dev
, B43_SHM_SHARED
, 0);
2398 /* Check for read/write and endianness problems. */
2399 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0x55AAAA55);
2400 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0x55AAAA55)
2402 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0xAA5555AA);
2403 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0xAA5555AA)
2406 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, backup
);
2408 if ((dev
->dev
->id
.revision
>= 3) && (dev
->dev
->id
.revision
<= 10)) {
2409 /* The 32bit register shadows the two 16bit registers
2410 * with update sideeffects. Validate this. */
2411 b43_write16(dev
, B43_MMIO_TSF_CFP_START
, 0xAAAA);
2412 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0xCCCCBBBB);
2413 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_LOW
) != 0xBBBB)
2415 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_HIGH
) != 0xCCCC)
2418 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0);
2420 v
= b43_read32(dev
, B43_MMIO_MACCTL
);
2421 v
|= B43_MACCTL_GMODE
;
2422 if (v
!= (B43_MACCTL_GMODE
| B43_MACCTL_IHR_ENABLED
))
2427 b43err(dev
->wl
, "Failed to validate the chipaccess\n");
2431 static void b43_security_init(struct b43_wldev
*dev
)
2433 dev
->max_nr_keys
= (dev
->dev
->id
.revision
>= 5) ? 58 : 20;
2434 B43_WARN_ON(dev
->max_nr_keys
> ARRAY_SIZE(dev
->key
));
2435 dev
->ktp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_KTP
);
2436 /* KTP is a word address, but we address SHM bytewise.
2437 * So multiply by two.
2440 if (dev
->dev
->id
.revision
>= 5) {
2441 /* Number of RCMTA address slots */
2442 b43_write16(dev
, B43_MMIO_RCMTA_COUNT
, dev
->max_nr_keys
- 8);
2444 b43_clear_keys(dev
);
2447 static int b43_rng_read(struct hwrng
*rng
, u32
* data
)
2449 struct b43_wl
*wl
= (struct b43_wl
*)rng
->priv
;
2450 unsigned long flags
;
2452 /* Don't take wl->mutex here, as it could deadlock with
2453 * hwrng internal locking. It's not needed to take
2454 * wl->mutex here, anyway. */
2456 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2457 *data
= b43_read16(wl
->current_dev
, B43_MMIO_RNG
);
2458 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2460 return (sizeof(u16
));
2463 static void b43_rng_exit(struct b43_wl
*wl
)
2465 if (wl
->rng_initialized
)
2466 hwrng_unregister(&wl
->rng
);
2469 static int b43_rng_init(struct b43_wl
*wl
)
2473 snprintf(wl
->rng_name
, ARRAY_SIZE(wl
->rng_name
),
2474 "%s_%s", KBUILD_MODNAME
, wiphy_name(wl
->hw
->wiphy
));
2475 wl
->rng
.name
= wl
->rng_name
;
2476 wl
->rng
.data_read
= b43_rng_read
;
2477 wl
->rng
.priv
= (unsigned long)wl
;
2478 wl
->rng_initialized
= 1;
2479 err
= hwrng_register(&wl
->rng
);
2481 wl
->rng_initialized
= 0;
2482 b43err(wl
, "Failed to register the random "
2483 "number generator (%d)\n", err
);
2489 static int b43_op_tx(struct ieee80211_hw
*hw
,
2490 struct sk_buff
*skb
,
2491 struct ieee80211_tx_control
*ctl
)
2493 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2494 struct b43_wldev
*dev
= wl
->current_dev
;
2499 if (unlikely(b43_status(dev
) < B43_STAT_STARTED
))
2501 /* DMA-TX is done without a global lock. */
2502 err
= b43_dma_tx(dev
, skb
, ctl
);
2505 return NETDEV_TX_BUSY
;
2506 return NETDEV_TX_OK
;
2509 static int b43_op_conf_tx(struct ieee80211_hw
*hw
,
2511 const struct ieee80211_tx_queue_params
*params
)
2516 static int b43_op_get_tx_stats(struct ieee80211_hw
*hw
,
2517 struct ieee80211_tx_queue_stats
*stats
)
2519 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2520 struct b43_wldev
*dev
= wl
->current_dev
;
2521 unsigned long flags
;
2526 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2527 if (likely(b43_status(dev
) >= B43_STAT_STARTED
)) {
2528 b43_dma_get_tx_stats(dev
, stats
);
2531 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2536 static int b43_op_get_stats(struct ieee80211_hw
*hw
,
2537 struct ieee80211_low_level_stats
*stats
)
2539 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2540 unsigned long flags
;
2542 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2543 memcpy(stats
, &wl
->ieee_stats
, sizeof(*stats
));
2544 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2549 static const char *phymode_to_string(unsigned int phymode
)
2564 static int find_wldev_for_phymode(struct b43_wl
*wl
,
2565 unsigned int phymode
,
2566 struct b43_wldev
**dev
, bool * gmode
)
2568 struct b43_wldev
*d
;
2570 list_for_each_entry(d
, &wl
->devlist
, list
) {
2571 if (d
->phy
.possible_phymodes
& phymode
) {
2572 /* Ok, this device supports the PHY-mode.
2573 * Now figure out how the gmode bit has to be
2574 * set to support it. */
2575 if (phymode
== B43_PHYMODE_A
)
2588 static void b43_put_phy_into_reset(struct b43_wldev
*dev
)
2590 struct ssb_device
*sdev
= dev
->dev
;
2593 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
2594 tmslow
&= ~B43_TMSLOW_GMODE
;
2595 tmslow
|= B43_TMSLOW_PHYRESET
;
2596 tmslow
|= SSB_TMSLOW_FGC
;
2597 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
2600 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
2601 tmslow
&= ~SSB_TMSLOW_FGC
;
2602 tmslow
|= B43_TMSLOW_PHYRESET
;
2603 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
2607 /* Expects wl->mutex locked */
2608 static int b43_switch_phymode(struct b43_wl
*wl
, unsigned int new_mode
)
2610 struct b43_wldev
*up_dev
;
2611 struct b43_wldev
*down_dev
;
2616 err
= find_wldev_for_phymode(wl
, new_mode
, &up_dev
, &gmode
);
2618 b43err(wl
, "Could not find a device for %s-PHY mode\n",
2619 phymode_to_string(new_mode
));
2622 if ((up_dev
== wl
->current_dev
) &&
2623 (!!wl
->current_dev
->phy
.gmode
== !!gmode
)) {
2624 /* This device is already running. */
2627 b43dbg(wl
, "Reconfiguring PHYmode to %s-PHY\n",
2628 phymode_to_string(new_mode
));
2629 down_dev
= wl
->current_dev
;
2631 prev_status
= b43_status(down_dev
);
2632 /* Shutdown the currently running core. */
2633 if (prev_status
>= B43_STAT_STARTED
)
2634 b43_wireless_core_stop(down_dev
);
2635 if (prev_status
>= B43_STAT_INITIALIZED
)
2636 b43_wireless_core_exit(down_dev
);
2638 if (down_dev
!= up_dev
) {
2639 /* We switch to a different core, so we put PHY into
2640 * RESET on the old core. */
2641 b43_put_phy_into_reset(down_dev
);
2644 /* Now start the new core. */
2645 up_dev
->phy
.gmode
= gmode
;
2646 if (prev_status
>= B43_STAT_INITIALIZED
) {
2647 err
= b43_wireless_core_init(up_dev
);
2649 b43err(wl
, "Fatal: Could not initialize device for "
2650 "newly selected %s-PHY mode\n",
2651 phymode_to_string(new_mode
));
2655 if (prev_status
>= B43_STAT_STARTED
) {
2656 err
= b43_wireless_core_start(up_dev
);
2658 b43err(wl
, "Fatal: Coult not start device for "
2659 "newly selected %s-PHY mode\n",
2660 phymode_to_string(new_mode
));
2661 b43_wireless_core_exit(up_dev
);
2665 B43_WARN_ON(b43_status(up_dev
) != prev_status
);
2667 wl
->current_dev
= up_dev
;
2671 /* Whoops, failed to init the new core. No core is operating now. */
2672 wl
->current_dev
= NULL
;
2676 /* Check if the use of the antenna that ieee80211 told us to
2677 * use is possible. This will fall back to DEFAULT.
2678 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2679 u8
b43_ieee80211_antenna_sanitize(struct b43_wldev
*dev
,
2684 if (antenna_nr
== 0) {
2685 /* Zero means "use default antenna". That's always OK. */
2689 /* Get the mask of available antennas. */
2691 antenna_mask
= dev
->dev
->bus
->sprom
.ant_available_bg
;
2693 antenna_mask
= dev
->dev
->bus
->sprom
.ant_available_a
;
2695 if (!(antenna_mask
& (1 << (antenna_nr
- 1)))) {
2696 /* This antenna is not available. Fall back to default. */
2703 static int b43_antenna_from_ieee80211(struct b43_wldev
*dev
, u8 antenna
)
2705 antenna
= b43_ieee80211_antenna_sanitize(dev
, antenna
);
2707 case 0: /* default/diversity */
2708 return B43_ANTENNA_DEFAULT
;
2709 case 1: /* Antenna 0 */
2710 return B43_ANTENNA0
;
2711 case 2: /* Antenna 1 */
2712 return B43_ANTENNA1
;
2714 return B43_ANTENNA_DEFAULT
;
2718 static int b43_op_config(struct ieee80211_hw
*hw
, struct ieee80211_conf
*conf
)
2720 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2721 struct b43_wldev
*dev
;
2722 struct b43_phy
*phy
;
2723 unsigned long flags
;
2724 unsigned int new_phymode
= 0xFFFF;
2729 mutex_lock(&wl
->mutex
);
2731 /* Switch the PHY mode (if necessary). */
2732 switch (conf
->phymode
) {
2733 case MODE_IEEE80211A
:
2734 new_phymode
= B43_PHYMODE_A
;
2736 case MODE_IEEE80211B
:
2737 new_phymode
= B43_PHYMODE_B
;
2739 case MODE_IEEE80211G
:
2740 new_phymode
= B43_PHYMODE_G
;
2745 err
= b43_switch_phymode(wl
, new_phymode
);
2747 goto out_unlock_mutex
;
2748 dev
= wl
->current_dev
;
2751 /* Disable IRQs while reconfiguring the device.
2752 * This makes it possible to drop the spinlock throughout
2753 * the reconfiguration process. */
2754 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2755 if (b43_status(dev
) < B43_STAT_STARTED
) {
2756 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2757 goto out_unlock_mutex
;
2759 savedirqs
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
2760 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2761 b43_synchronize_irq(dev
);
2763 /* Switch to the requested channel.
2764 * The firmware takes care of races with the TX handler. */
2765 if (conf
->channel_val
!= phy
->channel
)
2766 b43_radio_selectchannel(dev
, conf
->channel_val
, 0);
2768 /* Enable/Disable ShortSlot timing. */
2769 if ((!!(conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
)) !=
2771 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
2772 if (conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
)
2773 b43_short_slot_timing_enable(dev
);
2775 b43_short_slot_timing_disable(dev
);
2778 dev
->wl
->radiotap_enabled
= !!(conf
->flags
& IEEE80211_CONF_RADIOTAP
);
2780 /* Adjust the desired TX power level. */
2781 if (conf
->power_level
!= 0) {
2782 if (conf
->power_level
!= phy
->power_level
) {
2783 phy
->power_level
= conf
->power_level
;
2784 b43_phy_xmitpower(dev
);
2788 /* Antennas for RX and management frame TX. */
2789 antenna
= b43_antenna_from_ieee80211(dev
, conf
->antenna_sel_tx
);
2790 b43_mgmtframe_txantenna(dev
, antenna
);
2791 antenna
= b43_antenna_from_ieee80211(dev
, conf
->antenna_sel_rx
);
2792 b43_set_rx_antenna(dev
, antenna
);
2794 /* Update templates for AP mode. */
2795 if (b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
))
2796 b43_set_beacon_int(dev
, conf
->beacon_int
);
2798 if (!!conf
->radio_enabled
!= phy
->radio_on
) {
2799 if (conf
->radio_enabled
) {
2800 b43_radio_turn_on(dev
);
2801 b43info(dev
->wl
, "Radio turned on by software\n");
2802 if (!dev
->radio_hw_enable
) {
2803 b43info(dev
->wl
, "The hardware RF-kill button "
2804 "still turns the radio physically off. "
2805 "Press the button to turn it on.\n");
2808 b43_radio_turn_off(dev
, 0);
2809 b43info(dev
->wl
, "Radio turned off by software\n");
2813 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2814 b43_interrupt_enable(dev
, savedirqs
);
2816 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2818 mutex_unlock(&wl
->mutex
);
2823 static int b43_op_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
2824 const u8
*local_addr
, const u8
*addr
,
2825 struct ieee80211_key_conf
*key
)
2827 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2828 struct b43_wldev
*dev
;
2829 unsigned long flags
;
2833 DECLARE_MAC_BUF(mac
);
2835 if (modparam_nohwcrypt
)
2836 return -ENOSPC
; /* User disabled HW-crypto */
2838 mutex_lock(&wl
->mutex
);
2839 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2841 dev
= wl
->current_dev
;
2843 if (!dev
|| b43_status(dev
) < B43_STAT_INITIALIZED
)
2849 if (key
->keylen
== 5)
2850 algorithm
= B43_SEC_ALGO_WEP40
;
2852 algorithm
= B43_SEC_ALGO_WEP104
;
2855 algorithm
= B43_SEC_ALGO_TKIP
;
2858 algorithm
= B43_SEC_ALGO_AES
;
2864 index
= (u8
) (key
->keyidx
);
2870 if (algorithm
== B43_SEC_ALGO_TKIP
) {
2871 /* FIXME: No TKIP hardware encryption for now. */
2876 if (is_broadcast_ether_addr(addr
)) {
2877 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2878 err
= b43_key_write(dev
, index
, algorithm
,
2879 key
->key
, key
->keylen
, NULL
, key
);
2882 * either pairwise key or address is 00:00:00:00:00:00
2883 * for transmit-only keys
2885 err
= b43_key_write(dev
, -1, algorithm
,
2886 key
->key
, key
->keylen
, addr
, key
);
2891 if (algorithm
== B43_SEC_ALGO_WEP40
||
2892 algorithm
== B43_SEC_ALGO_WEP104
) {
2893 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_USEDEFKEYS
);
2896 b43_hf_read(dev
) & ~B43_HF_USEDEFKEYS
);
2898 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
2901 err
= b43_key_clear(dev
, key
->hw_key_idx
);
2910 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2911 mutex_unlock(&wl
->mutex
);
2913 b43dbg(wl
, "%s hardware based encryption for keyidx: %d, "
2915 cmd
== SET_KEY
? "Using" : "Disabling", key
->keyidx
,
2916 print_mac(mac
, addr
));
2921 static void b43_op_configure_filter(struct ieee80211_hw
*hw
,
2922 unsigned int changed
, unsigned int *fflags
,
2923 int mc_count
, struct dev_addr_list
*mc_list
)
2925 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2926 struct b43_wldev
*dev
= wl
->current_dev
;
2927 unsigned long flags
;
2934 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2935 *fflags
&= FIF_PROMISC_IN_BSS
|
2941 FIF_BCN_PRBRESP_PROMISC
;
2943 changed
&= FIF_PROMISC_IN_BSS
|
2949 FIF_BCN_PRBRESP_PROMISC
;
2951 wl
->filter_flags
= *fflags
;
2953 if (changed
&& b43_status(dev
) >= B43_STAT_INITIALIZED
)
2954 b43_adjust_opmode(dev
);
2955 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2958 static int b43_op_config_interface(struct ieee80211_hw
*hw
,
2959 struct ieee80211_vif
*vif
,
2960 struct ieee80211_if_conf
*conf
)
2962 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2963 struct b43_wldev
*dev
= wl
->current_dev
;
2964 unsigned long flags
;
2968 mutex_lock(&wl
->mutex
);
2969 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2970 B43_WARN_ON(wl
->vif
!= vif
);
2972 memcpy(wl
->bssid
, conf
->bssid
, ETH_ALEN
);
2974 memset(wl
->bssid
, 0, ETH_ALEN
);
2975 if (b43_status(dev
) >= B43_STAT_INITIALIZED
) {
2976 if (b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
)) {
2977 B43_WARN_ON(conf
->type
!= IEEE80211_IF_TYPE_AP
);
2978 b43_set_ssid(dev
, conf
->ssid
, conf
->ssid_len
);
2980 b43_update_templates(wl
, conf
->beacon
);
2982 b43_write_mac_bssid_templates(dev
);
2984 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2985 mutex_unlock(&wl
->mutex
);
2990 /* Locking: wl->mutex */
2991 static void b43_wireless_core_stop(struct b43_wldev
*dev
)
2993 struct b43_wl
*wl
= dev
->wl
;
2994 unsigned long flags
;
2996 if (b43_status(dev
) < B43_STAT_STARTED
)
2999 /* Disable and sync interrupts. We must do this before than
3000 * setting the status to INITIALIZED, as the interrupt handler
3001 * won't care about IRQs then. */
3002 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3003 dev
->irq_savedstate
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
3004 b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
); /* flush */
3005 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3006 b43_synchronize_irq(dev
);
3008 b43_set_status(dev
, B43_STAT_INITIALIZED
);
3010 mutex_unlock(&wl
->mutex
);
3011 /* Must unlock as it would otherwise deadlock. No races here.
3012 * Cancel the possibly running self-rearming periodic work. */
3013 cancel_delayed_work_sync(&dev
->periodic_work
);
3014 mutex_lock(&wl
->mutex
);
3016 ieee80211_stop_queues(wl
->hw
); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3018 b43_mac_suspend(dev
);
3019 free_irq(dev
->dev
->irq
, dev
);
3020 b43dbg(wl
, "Wireless interface stopped\n");
3023 /* Locking: wl->mutex */
3024 static int b43_wireless_core_start(struct b43_wldev
*dev
)
3028 B43_WARN_ON(b43_status(dev
) != B43_STAT_INITIALIZED
);
3030 drain_txstatus_queue(dev
);
3031 err
= request_irq(dev
->dev
->irq
, b43_interrupt_handler
,
3032 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
3034 b43err(dev
->wl
, "Cannot request IRQ-%d\n", dev
->dev
->irq
);
3038 /* We are ready to run. */
3039 b43_set_status(dev
, B43_STAT_STARTED
);
3041 /* Start data flow (TX/RX). */
3042 b43_mac_enable(dev
);
3043 b43_interrupt_enable(dev
, dev
->irq_savedstate
);
3044 ieee80211_start_queues(dev
->wl
->hw
);
3046 /* Start maintainance work */
3047 b43_periodic_tasks_setup(dev
);
3049 b43dbg(dev
->wl
, "Wireless interface started\n");
3054 /* Get PHY and RADIO versioning numbers */
3055 static int b43_phy_versioning(struct b43_wldev
*dev
)
3057 struct b43_phy
*phy
= &dev
->phy
;
3065 int unsupported
= 0;
3067 /* Get PHY versioning */
3068 tmp
= b43_read16(dev
, B43_MMIO_PHY_VER
);
3069 analog_type
= (tmp
& B43_PHYVER_ANALOG
) >> B43_PHYVER_ANALOG_SHIFT
;
3070 phy_type
= (tmp
& B43_PHYVER_TYPE
) >> B43_PHYVER_TYPE_SHIFT
;
3071 phy_rev
= (tmp
& B43_PHYVER_VERSION
);
3078 if (phy_rev
!= 2 && phy_rev
!= 4 && phy_rev
!= 6
3086 #ifdef CONFIG_B43_NPHY
3096 b43err(dev
->wl
, "FOUND UNSUPPORTED PHY "
3097 "(Analog %u, Type %u, Revision %u)\n",
3098 analog_type
, phy_type
, phy_rev
);
3101 b43dbg(dev
->wl
, "Found PHY: Analog %u, Type %u, Revision %u\n",
3102 analog_type
, phy_type
, phy_rev
);
3104 /* Get RADIO versioning */
3105 if (dev
->dev
->bus
->chip_id
== 0x4317) {
3106 if (dev
->dev
->bus
->chip_rev
== 0)
3108 else if (dev
->dev
->bus
->chip_rev
== 1)
3113 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, B43_RADIOCTL_ID
);
3114 tmp
= b43_read16(dev
, B43_MMIO_RADIO_DATA_HIGH
);
3116 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, B43_RADIOCTL_ID
);
3117 tmp
|= b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
3119 radio_manuf
= (tmp
& 0x00000FFF);
3120 radio_ver
= (tmp
& 0x0FFFF000) >> 12;
3121 radio_rev
= (tmp
& 0xF0000000) >> 28;
3122 if (radio_manuf
!= 0x17F /* Broadcom */)
3126 if (radio_ver
!= 0x2060)
3130 if (radio_manuf
!= 0x17F)
3134 if ((radio_ver
& 0xFFF0) != 0x2050)
3138 if (radio_ver
!= 0x2050)
3149 b43err(dev
->wl
, "FOUND UNSUPPORTED RADIO "
3150 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3151 radio_manuf
, radio_ver
, radio_rev
);
3154 b43dbg(dev
->wl
, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3155 radio_manuf
, radio_ver
, radio_rev
);
3157 phy
->radio_manuf
= radio_manuf
;
3158 phy
->radio_ver
= radio_ver
;
3159 phy
->radio_rev
= radio_rev
;
3161 phy
->analog
= analog_type
;
3162 phy
->type
= phy_type
;
3168 static void setup_struct_phy_for_init(struct b43_wldev
*dev
,
3169 struct b43_phy
*phy
)
3171 struct b43_txpower_lo_control
*lo
;
3174 memset(phy
->minlowsig
, 0xFF, sizeof(phy
->minlowsig
));
3175 memset(phy
->minlowsigpos
, 0, sizeof(phy
->minlowsigpos
));
3177 phy
->aci_enable
= 0;
3178 phy
->aci_wlan_automatic
= 0;
3179 phy
->aci_hw_rssi
= 0;
3181 phy
->radio_off_context
.valid
= 0;
3183 lo
= phy
->lo_control
;
3185 memset(lo
, 0, sizeof(*(phy
->lo_control
)));
3189 phy
->max_lb_gain
= 0;
3190 phy
->trsw_rx_gain
= 0;
3191 phy
->txpwr_offset
= 0;
3194 phy
->nrssislope
= 0;
3195 for (i
= 0; i
< ARRAY_SIZE(phy
->nrssi
); i
++)
3196 phy
->nrssi
[i
] = -1000;
3197 for (i
= 0; i
< ARRAY_SIZE(phy
->nrssi_lt
); i
++)
3198 phy
->nrssi_lt
[i
] = i
;
3200 phy
->lofcal
= 0xFFFF;
3201 phy
->initval
= 0xFFFF;
3203 phy
->interfmode
= B43_INTERFMODE_NONE
;
3204 phy
->channel
= 0xFF;
3206 phy
->hardware_power_control
= !!modparam_hwpctl
;
3208 /* PHY TX errors counter. */
3209 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
3211 /* OFDM-table address caching. */
3212 phy
->ofdmtab_addr_direction
= B43_OFDMTAB_DIRECTION_UNKNOWN
;
3215 static void setup_struct_wldev_for_init(struct b43_wldev
*dev
)
3219 /* Assume the radio is enabled. If it's not enabled, the state will
3220 * immediately get fixed on the first periodic work run. */
3221 dev
->radio_hw_enable
= 1;
3224 memset(&dev
->stats
, 0, sizeof(dev
->stats
));
3226 setup_struct_phy_for_init(dev
, &dev
->phy
);
3228 /* IRQ related flags */
3229 dev
->irq_reason
= 0;
3230 memset(dev
->dma_reason
, 0, sizeof(dev
->dma_reason
));
3231 dev
->irq_savedstate
= B43_IRQ_MASKTEMPLATE
;
3233 dev
->mac_suspended
= 1;
3235 /* Noise calculation context */
3236 memset(&dev
->noisecalc
, 0, sizeof(dev
->noisecalc
));
3239 static void b43_bluetooth_coext_enable(struct b43_wldev
*dev
)
3241 struct ssb_sprom
*sprom
= &dev
->dev
->bus
->sprom
;
3244 if (!(sprom
->boardflags_lo
& B43_BFL_BTCOEXIST
))
3246 if (dev
->phy
.type
!= B43_PHYTYPE_B
&& !dev
->phy
.gmode
)
3249 hf
= b43_hf_read(dev
);
3250 if (sprom
->boardflags_lo
& B43_BFL_BTCMOD
)
3251 hf
|= B43_HF_BTCOEXALT
;
3253 hf
|= B43_HF_BTCOEX
;
3254 b43_hf_write(dev
, hf
);
3258 static void b43_bluetooth_coext_disable(struct b43_wldev
*dev
)
3262 static void b43_imcfglo_timeouts_workaround(struct b43_wldev
*dev
)
3264 #ifdef CONFIG_SSB_DRIVER_PCICORE
3265 struct ssb_bus
*bus
= dev
->dev
->bus
;
3268 if (bus
->pcicore
.dev
&&
3269 bus
->pcicore
.dev
->id
.coreid
== SSB_DEV_PCI
&&
3270 bus
->pcicore
.dev
->id
.revision
<= 5) {
3271 /* IMCFGLO timeouts workaround. */
3272 tmp
= ssb_read32(dev
->dev
, SSB_IMCFGLO
);
3273 tmp
&= ~SSB_IMCFGLO_REQTO
;
3274 tmp
&= ~SSB_IMCFGLO_SERTO
;
3275 switch (bus
->bustype
) {
3276 case SSB_BUSTYPE_PCI
:
3277 case SSB_BUSTYPE_PCMCIA
:
3280 case SSB_BUSTYPE_SSB
:
3284 ssb_write32(dev
->dev
, SSB_IMCFGLO
, tmp
);
3286 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3289 /* Write the short and long frame retry limit values. */
3290 static void b43_set_retry_limits(struct b43_wldev
*dev
,
3291 unsigned int short_retry
,
3292 unsigned int long_retry
)
3294 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3295 * the chip-internal counter. */
3296 short_retry
= min(short_retry
, (unsigned int)0xF);
3297 long_retry
= min(long_retry
, (unsigned int)0xF);
3299 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_SRLIMIT
,
3301 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_LRLIMIT
,
3305 /* Shutdown a wireless core */
3306 /* Locking: wl->mutex */
3307 static void b43_wireless_core_exit(struct b43_wldev
*dev
)
3309 struct b43_phy
*phy
= &dev
->phy
;
3311 B43_WARN_ON(b43_status(dev
) > B43_STAT_INITIALIZED
);
3312 if (b43_status(dev
) != B43_STAT_INITIALIZED
)
3314 b43_set_status(dev
, B43_STAT_UNINIT
);
3317 b43_rng_exit(dev
->wl
);
3320 b43_radio_turn_off(dev
, 1);
3321 b43_switch_analog(dev
, 0);
3322 if (phy
->dyn_tssi_tbl
)
3323 kfree(phy
->tssi2dbm
);
3324 kfree(phy
->lo_control
);
3325 phy
->lo_control
= NULL
;
3326 if (dev
->wl
->current_beacon
) {
3327 dev_kfree_skb_any(dev
->wl
->current_beacon
);
3328 dev
->wl
->current_beacon
= NULL
;
3331 ssb_device_disable(dev
->dev
, 0);
3332 ssb_bus_may_powerdown(dev
->dev
->bus
);
3335 /* Initialize a wireless core */
3336 static int b43_wireless_core_init(struct b43_wldev
*dev
)
3338 struct b43_wl
*wl
= dev
->wl
;
3339 struct ssb_bus
*bus
= dev
->dev
->bus
;
3340 struct ssb_sprom
*sprom
= &bus
->sprom
;
3341 struct b43_phy
*phy
= &dev
->phy
;
3345 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
3347 err
= ssb_bus_powerup(bus
, 0);
3350 if (!ssb_device_is_enabled(dev
->dev
)) {
3351 tmp
= phy
->gmode
? B43_TMSLOW_GMODE
: 0;
3352 b43_wireless_core_reset(dev
, tmp
);
3355 if ((phy
->type
== B43_PHYTYPE_B
) || (phy
->type
== B43_PHYTYPE_G
)) {
3357 kzalloc(sizeof(*(phy
->lo_control
)), GFP_KERNEL
);
3358 if (!phy
->lo_control
) {
3363 setup_struct_wldev_for_init(dev
);
3365 err
= b43_phy_init_tssi2dbm_table(dev
);
3367 goto err_kfree_lo_control
;
3369 /* Enable IRQ routing to this device. */
3370 ssb_pcicore_dev_irqvecs_enable(&bus
->pcicore
, dev
->dev
);
3372 b43_imcfglo_timeouts_workaround(dev
);
3373 b43_bluetooth_coext_disable(dev
);
3374 b43_phy_early_init(dev
);
3375 err
= b43_chip_init(dev
);
3377 goto err_kfree_tssitbl
;
3378 b43_shm_write16(dev
, B43_SHM_SHARED
,
3379 B43_SHM_SH_WLCOREREV
, dev
->dev
->id
.revision
);
3380 hf
= b43_hf_read(dev
);
3381 if (phy
->type
== B43_PHYTYPE_G
) {
3385 if (sprom
->boardflags_lo
& B43_BFL_PACTRL
)
3386 hf
|= B43_HF_OFDMPABOOST
;
3387 } else if (phy
->type
== B43_PHYTYPE_B
) {
3389 if (phy
->rev
>= 2 && phy
->radio_ver
== 0x2050)
3392 b43_hf_write(dev
, hf
);
3394 b43_set_retry_limits(dev
, B43_DEFAULT_SHORT_RETRY_LIMIT
,
3395 B43_DEFAULT_LONG_RETRY_LIMIT
);
3396 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_SFFBLIM
, 3);
3397 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_LFFBLIM
, 2);
3399 /* Disable sending probe responses from firmware.
3400 * Setting the MaxTime to one usec will always trigger
3401 * a timeout, so we never send any probe resp.
3402 * A timeout of zero is infinite. */
3403 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRMAXTIME
, 1);
3405 b43_rate_memory_init(dev
);
3407 /* Minimum Contention Window */
3408 if (phy
->type
== B43_PHYTYPE_B
) {
3409 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0x1F);
3411 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0xF);
3413 /* Maximum Contention Window */
3414 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MAXCONT
, 0x3FF);
3416 err
= b43_dma_init(dev
);
3423 b43_write16(dev
, 0x0612, 0x0050);
3424 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0416, 0x0050);
3425 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0414, 0x01F4);
3428 b43_bluetooth_coext_enable(dev
);
3430 ssb_bus_powerup(bus
, 1); /* Enable dynamic PCTL */
3431 memset(wl
->bssid
, 0, ETH_ALEN
);
3432 memset(wl
->mac_addr
, 0, ETH_ALEN
);
3433 b43_upload_card_macaddress(dev
);
3434 b43_security_init(dev
);
3437 b43_set_status(dev
, B43_STAT_INITIALIZED
);
3446 if (phy
->dyn_tssi_tbl
)
3447 kfree(phy
->tssi2dbm
);
3448 err_kfree_lo_control
:
3449 kfree(phy
->lo_control
);
3450 phy
->lo_control
= NULL
;
3452 ssb_bus_may_powerdown(bus
);
3453 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
3457 static int b43_op_add_interface(struct ieee80211_hw
*hw
,
3458 struct ieee80211_if_init_conf
*conf
)
3460 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3461 struct b43_wldev
*dev
;
3462 unsigned long flags
;
3463 int err
= -EOPNOTSUPP
;
3465 /* TODO: allow WDS/AP devices to coexist */
3467 if (conf
->type
!= IEEE80211_IF_TYPE_AP
&&
3468 conf
->type
!= IEEE80211_IF_TYPE_STA
&&
3469 conf
->type
!= IEEE80211_IF_TYPE_WDS
&&
3470 conf
->type
!= IEEE80211_IF_TYPE_IBSS
)
3473 mutex_lock(&wl
->mutex
);
3475 goto out_mutex_unlock
;
3477 b43dbg(wl
, "Adding Interface type %d\n", conf
->type
);
3479 dev
= wl
->current_dev
;
3481 wl
->vif
= conf
->vif
;
3482 wl
->if_type
= conf
->type
;
3483 memcpy(wl
->mac_addr
, conf
->mac_addr
, ETH_ALEN
);
3485 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3486 b43_adjust_opmode(dev
);
3487 b43_upload_card_macaddress(dev
);
3488 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3492 mutex_unlock(&wl
->mutex
);
3497 static void b43_op_remove_interface(struct ieee80211_hw
*hw
,
3498 struct ieee80211_if_init_conf
*conf
)
3500 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3501 struct b43_wldev
*dev
= wl
->current_dev
;
3502 unsigned long flags
;
3504 b43dbg(wl
, "Removing Interface type %d\n", conf
->type
);
3506 mutex_lock(&wl
->mutex
);
3508 B43_WARN_ON(!wl
->operating
);
3509 B43_WARN_ON(wl
->vif
!= conf
->vif
);
3514 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3515 b43_adjust_opmode(dev
);
3516 memset(wl
->mac_addr
, 0, ETH_ALEN
);
3517 b43_upload_card_macaddress(dev
);
3518 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3520 mutex_unlock(&wl
->mutex
);
3523 static int b43_op_start(struct ieee80211_hw
*hw
)
3525 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3526 struct b43_wldev
*dev
= wl
->current_dev
;
3530 /* First register RFkill.
3531 * LEDs that are registered later depend on it. */
3532 b43_rfkill_init(dev
);
3534 mutex_lock(&wl
->mutex
);
3536 if (b43_status(dev
) < B43_STAT_INITIALIZED
) {
3537 err
= b43_wireless_core_init(dev
);
3539 goto out_mutex_unlock
;
3543 if (b43_status(dev
) < B43_STAT_STARTED
) {
3544 err
= b43_wireless_core_start(dev
);
3547 b43_wireless_core_exit(dev
);
3548 goto out_mutex_unlock
;
3553 mutex_unlock(&wl
->mutex
);
3558 static void b43_op_stop(struct ieee80211_hw
*hw
)
3560 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3561 struct b43_wldev
*dev
= wl
->current_dev
;
3563 b43_rfkill_exit(dev
);
3565 mutex_lock(&wl
->mutex
);
3566 if (b43_status(dev
) >= B43_STAT_STARTED
)
3567 b43_wireless_core_stop(dev
);
3568 b43_wireless_core_exit(dev
);
3569 mutex_unlock(&wl
->mutex
);
3572 static int b43_op_set_retry_limit(struct ieee80211_hw
*hw
,
3573 u32 short_retry_limit
, u32 long_retry_limit
)
3575 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3576 struct b43_wldev
*dev
;
3579 mutex_lock(&wl
->mutex
);
3580 dev
= wl
->current_dev
;
3581 if (unlikely(!dev
|| (b43_status(dev
) < B43_STAT_INITIALIZED
))) {
3585 b43_set_retry_limits(dev
, short_retry_limit
, long_retry_limit
);
3587 mutex_unlock(&wl
->mutex
);
3592 static int b43_op_beacon_set_tim(struct ieee80211_hw
*hw
, int aid
, int set
)
3594 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3595 struct sk_buff
*beacon
;
3596 unsigned long flags
;
3598 /* We could modify the existing beacon and set the aid bit in
3599 * the TIM field, but that would probably require resizing and
3600 * moving of data within the beacon template.
3601 * Simply request a new beacon and let mac80211 do the hard work. */
3602 beacon
= ieee80211_beacon_get(hw
, wl
->vif
, NULL
);
3603 if (unlikely(!beacon
))
3605 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3606 b43_update_templates(wl
, beacon
);
3607 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3612 static int b43_op_ibss_beacon_update(struct ieee80211_hw
*hw
,
3613 struct sk_buff
*beacon
,
3614 struct ieee80211_tx_control
*ctl
)
3616 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3617 unsigned long flags
;
3619 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3620 b43_update_templates(wl
, beacon
);
3621 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3626 static const struct ieee80211_ops b43_hw_ops
= {
3628 .conf_tx
= b43_op_conf_tx
,
3629 .add_interface
= b43_op_add_interface
,
3630 .remove_interface
= b43_op_remove_interface
,
3631 .config
= b43_op_config
,
3632 .config_interface
= b43_op_config_interface
,
3633 .configure_filter
= b43_op_configure_filter
,
3634 .set_key
= b43_op_set_key
,
3635 .get_stats
= b43_op_get_stats
,
3636 .get_tx_stats
= b43_op_get_tx_stats
,
3637 .start
= b43_op_start
,
3638 .stop
= b43_op_stop
,
3639 .set_retry_limit
= b43_op_set_retry_limit
,
3640 .set_tim
= b43_op_beacon_set_tim
,
3641 .beacon_update
= b43_op_ibss_beacon_update
,
3644 /* Hard-reset the chip. Do not call this directly.
3645 * Use b43_controller_restart()
3647 static void b43_chip_reset(struct work_struct
*work
)
3649 struct b43_wldev
*dev
=
3650 container_of(work
, struct b43_wldev
, restart_work
);
3651 struct b43_wl
*wl
= dev
->wl
;
3655 mutex_lock(&wl
->mutex
);
3657 prev_status
= b43_status(dev
);
3658 /* Bring the device down... */
3659 if (prev_status
>= B43_STAT_STARTED
)
3660 b43_wireless_core_stop(dev
);
3661 if (prev_status
>= B43_STAT_INITIALIZED
)
3662 b43_wireless_core_exit(dev
);
3664 /* ...and up again. */
3665 if (prev_status
>= B43_STAT_INITIALIZED
) {
3666 err
= b43_wireless_core_init(dev
);
3670 if (prev_status
>= B43_STAT_STARTED
) {
3671 err
= b43_wireless_core_start(dev
);
3673 b43_wireless_core_exit(dev
);
3678 mutex_unlock(&wl
->mutex
);
3680 b43err(wl
, "Controller restart FAILED\n");
3682 b43info(wl
, "Controller restarted\n");
3685 static int b43_setup_modes(struct b43_wldev
*dev
,
3686 bool have_2ghz_phy
, bool have_5ghz_phy
)
3688 struct ieee80211_hw
*hw
= dev
->wl
->hw
;
3689 struct ieee80211_hw_mode
*mode
;
3690 struct b43_phy
*phy
= &dev
->phy
;
3693 /* XXX: This function will go away soon, when mac80211
3694 * band stuff is rewritten. So this is just a hack.
3695 * For now we always claim GPHY mode, as there is no
3696 * support for NPHY and APHY in the device, yet.
3697 * This assumption is OK, as any B, N or A PHY will already
3698 * have died a horrible sanity check death earlier. */
3700 mode
= &phy
->hwmodes
[0];
3701 mode
->mode
= MODE_IEEE80211G
;
3702 mode
->num_channels
= b43_2ghz_chantable_size
;
3703 mode
->channels
= b43_2ghz_chantable
;
3704 mode
->num_rates
= b43_g_ratetable_size
;
3705 mode
->rates
= b43_g_ratetable
;
3706 err
= ieee80211_register_hwmode(hw
, mode
);
3709 phy
->possible_phymodes
|= B43_PHYMODE_G
;
3714 static void b43_wireless_core_detach(struct b43_wldev
*dev
)
3716 /* We release firmware that late to not be required to re-request
3717 * is all the time when we reinit the core. */
3718 b43_release_firmware(dev
);
3721 static int b43_wireless_core_attach(struct b43_wldev
*dev
)
3723 struct b43_wl
*wl
= dev
->wl
;
3724 struct ssb_bus
*bus
= dev
->dev
->bus
;
3725 struct pci_dev
*pdev
= bus
->host_pci
;
3727 bool have_2ghz_phy
= 0, have_5ghz_phy
= 0;
3730 /* Do NOT do any device initialization here.
3731 * Do it in wireless_core_init() instead.
3732 * This function is for gathering basic information about the HW, only.
3733 * Also some structs may be set up here. But most likely you want to have
3734 * that in core_init(), too.
3737 err
= ssb_bus_powerup(bus
, 0);
3739 b43err(wl
, "Bus powerup failed\n");
3742 /* Get the PHY type. */
3743 if (dev
->dev
->id
.revision
>= 5) {
3746 tmshigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
3747 have_2ghz_phy
= !!(tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
);
3748 have_5ghz_phy
= !!(tmshigh
& B43_TMSHIGH_HAVE_5GHZ_PHY
);
3752 dev
->phy
.gmode
= have_2ghz_phy
;
3753 tmp
= dev
->phy
.gmode
? B43_TMSLOW_GMODE
: 0;
3754 b43_wireless_core_reset(dev
, tmp
);
3756 err
= b43_phy_versioning(dev
);
3759 /* Check if this device supports multiband. */
3761 (pdev
->device
!= 0x4312 &&
3762 pdev
->device
!= 0x4319 && pdev
->device
!= 0x4324)) {
3763 /* No multiband support. */
3766 switch (dev
->phy
.type
) {
3778 if (dev
->phy
.type
== B43_PHYTYPE_A
) {
3780 b43err(wl
, "IEEE 802.11a devices are unsupported\n");
3784 dev
->phy
.gmode
= have_2ghz_phy
;
3785 tmp
= dev
->phy
.gmode
? B43_TMSLOW_GMODE
: 0;
3786 b43_wireless_core_reset(dev
, tmp
);
3788 err
= b43_validate_chipaccess(dev
);
3791 err
= b43_setup_modes(dev
, have_2ghz_phy
, have_5ghz_phy
);
3795 /* Now set some default "current_dev" */
3796 if (!wl
->current_dev
)
3797 wl
->current_dev
= dev
;
3798 INIT_WORK(&dev
->restart_work
, b43_chip_reset
);
3800 b43_radio_turn_off(dev
, 1);
3801 b43_switch_analog(dev
, 0);
3802 ssb_device_disable(dev
->dev
, 0);
3803 ssb_bus_may_powerdown(bus
);
3809 ssb_bus_may_powerdown(bus
);
3813 static void b43_one_core_detach(struct ssb_device
*dev
)
3815 struct b43_wldev
*wldev
;
3818 wldev
= ssb_get_drvdata(dev
);
3820 cancel_work_sync(&wldev
->restart_work
);
3821 b43_debugfs_remove_device(wldev
);
3822 b43_wireless_core_detach(wldev
);
3823 list_del(&wldev
->list
);
3825 ssb_set_drvdata(dev
, NULL
);
3829 static int b43_one_core_attach(struct ssb_device
*dev
, struct b43_wl
*wl
)
3831 struct b43_wldev
*wldev
;
3832 struct pci_dev
*pdev
;
3835 if (!list_empty(&wl
->devlist
)) {
3836 /* We are not the first core on this chip. */
3837 pdev
= dev
->bus
->host_pci
;
3838 /* Only special chips support more than one wireless
3839 * core, although some of the other chips have more than
3840 * one wireless core as well. Check for this and
3844 ((pdev
->device
!= 0x4321) &&
3845 (pdev
->device
!= 0x4313) && (pdev
->device
!= 0x431A))) {
3846 b43dbg(wl
, "Ignoring unconnected 802.11 core\n");
3851 wldev
= kzalloc(sizeof(*wldev
), GFP_KERNEL
);
3857 b43_set_status(wldev
, B43_STAT_UNINIT
);
3858 wldev
->bad_frames_preempt
= modparam_bad_frames_preempt
;
3859 tasklet_init(&wldev
->isr_tasklet
,
3860 (void (*)(unsigned long))b43_interrupt_tasklet
,
3861 (unsigned long)wldev
);
3862 INIT_LIST_HEAD(&wldev
->list
);
3864 err
= b43_wireless_core_attach(wldev
);
3866 goto err_kfree_wldev
;
3868 list_add(&wldev
->list
, &wl
->devlist
);
3870 ssb_set_drvdata(dev
, wldev
);
3871 b43_debugfs_add_device(wldev
);
3881 static void b43_sprom_fixup(struct ssb_bus
*bus
)
3883 /* boardflags workarounds */
3884 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_DELL
&&
3885 bus
->chip_id
== 0x4301 && bus
->boardinfo
.rev
== 0x74)
3886 bus
->sprom
.boardflags_lo
|= B43_BFL_BTCOEXIST
;
3887 if (bus
->boardinfo
.vendor
== PCI_VENDOR_ID_APPLE
&&
3888 bus
->boardinfo
.type
== 0x4E && bus
->boardinfo
.rev
> 0x40)
3889 bus
->sprom
.boardflags_lo
|= B43_BFL_PACTRL
;
3892 static void b43_wireless_exit(struct ssb_device
*dev
, struct b43_wl
*wl
)
3894 struct ieee80211_hw
*hw
= wl
->hw
;
3896 ssb_set_devtypedata(dev
, NULL
);
3897 ieee80211_free_hw(hw
);
3900 static int b43_wireless_init(struct ssb_device
*dev
)
3902 struct ssb_sprom
*sprom
= &dev
->bus
->sprom
;
3903 struct ieee80211_hw
*hw
;
3907 b43_sprom_fixup(dev
->bus
);
3909 hw
= ieee80211_alloc_hw(sizeof(*wl
), &b43_hw_ops
);
3911 b43err(NULL
, "Could not allocate ieee80211 device\n");
3916 hw
->flags
= IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE
|
3917 IEEE80211_HW_RX_INCLUDES_FCS
;
3918 hw
->max_signal
= 100;
3919 hw
->max_rssi
= -110;
3920 hw
->max_noise
= -110;
3921 hw
->queues
= 1; /* FIXME: hardware has more queues */
3922 SET_IEEE80211_DEV(hw
, dev
->dev
);
3923 if (is_valid_ether_addr(sprom
->et1mac
))
3924 SET_IEEE80211_PERM_ADDR(hw
, sprom
->et1mac
);
3926 SET_IEEE80211_PERM_ADDR(hw
, sprom
->il0mac
);
3928 /* Get and initialize struct b43_wl */
3929 wl
= hw_to_b43_wl(hw
);
3930 memset(wl
, 0, sizeof(*wl
));
3932 spin_lock_init(&wl
->irq_lock
);
3933 spin_lock_init(&wl
->leds_lock
);
3934 mutex_init(&wl
->mutex
);
3935 INIT_LIST_HEAD(&wl
->devlist
);
3937 ssb_set_devtypedata(dev
, wl
);
3938 b43info(wl
, "Broadcom %04X WLAN found\n", dev
->bus
->chip_id
);
3944 static int b43_probe(struct ssb_device
*dev
, const struct ssb_device_id
*id
)
3950 wl
= ssb_get_devtypedata(dev
);
3952 /* Probing the first core. Must setup common struct b43_wl */
3954 err
= b43_wireless_init(dev
);
3957 wl
= ssb_get_devtypedata(dev
);
3960 err
= b43_one_core_attach(dev
, wl
);
3962 goto err_wireless_exit
;
3965 err
= ieee80211_register_hw(wl
->hw
);
3967 goto err_one_core_detach
;
3973 err_one_core_detach
:
3974 b43_one_core_detach(dev
);
3977 b43_wireless_exit(dev
, wl
);
3981 static void b43_remove(struct ssb_device
*dev
)
3983 struct b43_wl
*wl
= ssb_get_devtypedata(dev
);
3984 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
3987 if (wl
->current_dev
== wldev
)
3988 ieee80211_unregister_hw(wl
->hw
);
3990 b43_one_core_detach(dev
);
3992 if (list_empty(&wl
->devlist
)) {
3993 /* Last core on the chip unregistered.
3994 * We can destroy common struct b43_wl.
3996 b43_wireless_exit(dev
, wl
);
4000 /* Perform a hardware reset. This can be called from any context. */
4001 void b43_controller_restart(struct b43_wldev
*dev
, const char *reason
)
4003 /* Must avoid requeueing, if we are in shutdown. */
4004 if (b43_status(dev
) < B43_STAT_INITIALIZED
)
4006 b43info(dev
->wl
, "Controller RESET (%s) ...\n", reason
);
4007 queue_work(dev
->wl
->hw
->workqueue
, &dev
->restart_work
);
4012 static int b43_suspend(struct ssb_device
*dev
, pm_message_t state
)
4014 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
4015 struct b43_wl
*wl
= wldev
->wl
;
4017 b43dbg(wl
, "Suspending...\n");
4019 mutex_lock(&wl
->mutex
);
4020 wldev
->suspend_init_status
= b43_status(wldev
);
4021 if (wldev
->suspend_init_status
>= B43_STAT_STARTED
)
4022 b43_wireless_core_stop(wldev
);
4023 if (wldev
->suspend_init_status
>= B43_STAT_INITIALIZED
)
4024 b43_wireless_core_exit(wldev
);
4025 mutex_unlock(&wl
->mutex
);
4027 b43dbg(wl
, "Device suspended.\n");
4032 static int b43_resume(struct ssb_device
*dev
)
4034 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
4035 struct b43_wl
*wl
= wldev
->wl
;
4038 b43dbg(wl
, "Resuming...\n");
4040 mutex_lock(&wl
->mutex
);
4041 if (wldev
->suspend_init_status
>= B43_STAT_INITIALIZED
) {
4042 err
= b43_wireless_core_init(wldev
);
4044 b43err(wl
, "Resume failed at core init\n");
4048 if (wldev
->suspend_init_status
>= B43_STAT_STARTED
) {
4049 err
= b43_wireless_core_start(wldev
);
4051 b43_wireless_core_exit(wldev
);
4052 b43err(wl
, "Resume failed at core start\n");
4056 mutex_unlock(&wl
->mutex
);
4058 b43dbg(wl
, "Device resumed.\n");
4063 #else /* CONFIG_PM */
4064 # define b43_suspend NULL
4065 # define b43_resume NULL
4066 #endif /* CONFIG_PM */
4068 static struct ssb_driver b43_ssb_driver
= {
4069 .name
= KBUILD_MODNAME
,
4070 .id_table
= b43_ssb_tbl
,
4072 .remove
= b43_remove
,
4073 .suspend
= b43_suspend
,
4074 .resume
= b43_resume
,
4077 static int __init
b43_init(void)
4082 err
= b43_pcmcia_init();
4085 err
= ssb_driver_register(&b43_ssb_driver
);
4087 goto err_pcmcia_exit
;
4098 static void __exit
b43_exit(void)
4100 ssb_driver_unregister(&b43_ssb_driver
);
4105 module_init(b43_init
)
4106 module_exit(b43_exit
)