3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
56 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
57 MODULE_AUTHOR("Martin Langer");
58 MODULE_AUTHOR("Stefano Brivio");
59 MODULE_AUTHOR("Michael Buesch");
60 MODULE_LICENSE("GPL");
62 extern char *nvram_get(char *name
);
64 #if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
65 static int modparam_pio
;
66 module_param_named(pio
, modparam_pio
, int, 0444);
67 MODULE_PARM_DESC(pio
, "enable(1) / disable(0) PIO mode");
68 #elif defined(CONFIG_B43_DMA)
69 # define modparam_pio 0
70 #elif defined(CONFIG_B43_PIO)
71 # define modparam_pio 1
74 static int modparam_bad_frames_preempt
;
75 module_param_named(bad_frames_preempt
, modparam_bad_frames_preempt
, int, 0444);
76 MODULE_PARM_DESC(bad_frames_preempt
,
77 "enable(1) / disable(0) Bad Frames Preemption");
79 static int modparam_short_retry
= B43_DEFAULT_SHORT_RETRY_LIMIT
;
80 module_param_named(short_retry
, modparam_short_retry
, int, 0444);
81 MODULE_PARM_DESC(short_retry
, "Short-Retry-Limit (0 - 15)");
83 static int modparam_long_retry
= B43_DEFAULT_LONG_RETRY_LIMIT
;
84 module_param_named(long_retry
, modparam_long_retry
, int, 0444);
85 MODULE_PARM_DESC(long_retry
, "Long-Retry-Limit (0 - 15)");
87 static int modparam_noleds
;
88 module_param_named(noleds
, modparam_noleds
, int, 0444);
89 MODULE_PARM_DESC(noleds
, "Turn off all LED activity");
91 static char modparam_fwpostfix
[16];
92 module_param_string(fwpostfix
, modparam_fwpostfix
, 16, 0444);
93 MODULE_PARM_DESC(fwpostfix
, "Postfix for the .fw files to load.");
95 static int modparam_mon_keep_bad
;
96 module_param_named(mon_keep_bad
, modparam_mon_keep_bad
, int, 0444);
97 MODULE_PARM_DESC(mon_keep_bad
, "Keep bad frames in monitor mode");
99 static int modparam_mon_keep_badplcp
;
100 module_param_named(mon_keep_badplcp
, modparam_mon_keep_bad
, int, 0444);
101 MODULE_PARM_DESC(mon_keep_badplcp
, "Keep frames with bad PLCP in monitor mode");
103 static int modparam_hwpctl
;
104 module_param_named(hwpctl
, modparam_hwpctl
, int, 0444);
105 MODULE_PARM_DESC(hwpctl
, "Enable hardware-side power control (default off)");
107 static int modparam_nohwcrypt
;
108 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
109 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
111 static const struct ssb_device_id b43_ssb_tbl
[] = {
112 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 5),
113 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 6),
114 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 7),
115 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 9),
116 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 10),
120 MODULE_DEVICE_TABLE(ssb
, b43_ssb_tbl
);
122 /* Channel and ratetables are shared for all devices.
123 * They can't be const, because ieee80211 puts some precalculated
124 * data in there. This data is the same for all devices, so we don't
125 * get concurrency issues */
126 #define RATETAB_ENT(_rateid, _flags) \
128 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
133 static struct ieee80211_rate __b43_ratetable
[] = {
134 RATETAB_ENT(B43_CCK_RATE_1MB
, IEEE80211_RATE_CCK
),
135 RATETAB_ENT(B43_CCK_RATE_2MB
, IEEE80211_RATE_CCK_2
),
136 RATETAB_ENT(B43_CCK_RATE_5MB
, IEEE80211_RATE_CCK_2
),
137 RATETAB_ENT(B43_CCK_RATE_11MB
, IEEE80211_RATE_CCK_2
),
138 RATETAB_ENT(B43_OFDM_RATE_6MB
, IEEE80211_RATE_OFDM
),
139 RATETAB_ENT(B43_OFDM_RATE_9MB
, IEEE80211_RATE_OFDM
),
140 RATETAB_ENT(B43_OFDM_RATE_12MB
, IEEE80211_RATE_OFDM
),
141 RATETAB_ENT(B43_OFDM_RATE_18MB
, IEEE80211_RATE_OFDM
),
142 RATETAB_ENT(B43_OFDM_RATE_24MB
, IEEE80211_RATE_OFDM
),
143 RATETAB_ENT(B43_OFDM_RATE_36MB
, IEEE80211_RATE_OFDM
),
144 RATETAB_ENT(B43_OFDM_RATE_48MB
, IEEE80211_RATE_OFDM
),
145 RATETAB_ENT(B43_OFDM_RATE_54MB
, IEEE80211_RATE_OFDM
),
148 #define b43_a_ratetable (__b43_ratetable + 4)
149 #define b43_a_ratetable_size 8
150 #define b43_b_ratetable (__b43_ratetable + 0)
151 #define b43_b_ratetable_size 4
152 #define b43_g_ratetable (__b43_ratetable + 0)
153 #define b43_g_ratetable_size 12
155 #define CHANTAB_ENT(_chanid, _freq) \
160 .flag = IEEE80211_CHAN_W_SCAN | \
161 IEEE80211_CHAN_W_ACTIVE_SCAN | \
162 IEEE80211_CHAN_W_IBSS, \
163 .power_level = 0xFF, \
164 .antenna_max = 0xFF, \
166 static struct ieee80211_channel b43_bg_chantable
[] = {
167 CHANTAB_ENT(1, 2412),
168 CHANTAB_ENT(2, 2417),
169 CHANTAB_ENT(3, 2422),
170 CHANTAB_ENT(4, 2427),
171 CHANTAB_ENT(5, 2432),
172 CHANTAB_ENT(6, 2437),
173 CHANTAB_ENT(7, 2442),
174 CHANTAB_ENT(8, 2447),
175 CHANTAB_ENT(9, 2452),
176 CHANTAB_ENT(10, 2457),
177 CHANTAB_ENT(11, 2462),
178 CHANTAB_ENT(12, 2467),
179 CHANTAB_ENT(13, 2472),
180 CHANTAB_ENT(14, 2484),
183 #define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable)
184 static struct ieee80211_channel b43_a_chantable
[] = {
185 CHANTAB_ENT(36, 5180),
186 CHANTAB_ENT(40, 5200),
187 CHANTAB_ENT(44, 5220),
188 CHANTAB_ENT(48, 5240),
189 CHANTAB_ENT(52, 5260),
190 CHANTAB_ENT(56, 5280),
191 CHANTAB_ENT(60, 5300),
192 CHANTAB_ENT(64, 5320),
193 CHANTAB_ENT(149, 5745),
194 CHANTAB_ENT(153, 5765),
195 CHANTAB_ENT(157, 5785),
196 CHANTAB_ENT(161, 5805),
197 CHANTAB_ENT(165, 5825),
200 #define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable)
202 static void b43_wireless_core_exit(struct b43_wldev
*dev
);
203 static int b43_wireless_core_init(struct b43_wldev
*dev
);
204 static void b43_wireless_core_stop(struct b43_wldev
*dev
);
205 static int b43_wireless_core_start(struct b43_wldev
*dev
);
207 static int b43_ratelimit(struct b43_wl
*wl
)
209 if (!wl
|| !wl
->current_dev
)
211 if (b43_status(wl
->current_dev
) < B43_STAT_STARTED
)
213 /* We are up and running.
214 * Ratelimit the messages to avoid DoS over the net. */
215 return net_ratelimit();
218 void b43info(struct b43_wl
*wl
, const char *fmt
, ...)
222 if (!b43_ratelimit(wl
))
225 printk(KERN_INFO
"b43-%s: ",
226 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
231 void b43err(struct b43_wl
*wl
, const char *fmt
, ...)
235 if (!b43_ratelimit(wl
))
238 printk(KERN_ERR
"b43-%s ERROR: ",
239 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
244 void b43warn(struct b43_wl
*wl
, const char *fmt
, ...)
248 if (!b43_ratelimit(wl
))
251 printk(KERN_WARNING
"b43-%s warning: ",
252 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
258 void b43dbg(struct b43_wl
*wl
, const char *fmt
, ...)
263 printk(KERN_DEBUG
"b43-%s debug: ",
264 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
270 static void b43_ram_write(struct b43_wldev
*dev
, u16 offset
, u32 val
)
274 B43_WARN_ON(offset
% 4 != 0);
276 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
277 if (macctl
& B43_MACCTL_BE
)
280 b43_write32(dev
, B43_MMIO_RAM_CONTROL
, offset
);
282 b43_write32(dev
, B43_MMIO_RAM_DATA
, val
);
286 void b43_shm_control_word(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
290 /* "offset" is the WORD offset. */
295 b43_write32(dev
, B43_MMIO_SHM_CONTROL
, control
);
298 u32
b43_shm_read32(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
302 if (routing
== B43_SHM_SHARED
) {
303 B43_WARN_ON(offset
& 0x0001);
304 if (offset
& 0x0003) {
305 /* Unaligned access */
306 b43_shm_control_word(dev
, routing
, offset
>> 2);
307 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
309 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
310 ret
|= b43_read16(dev
, B43_MMIO_SHM_DATA
);
316 b43_shm_control_word(dev
, routing
, offset
);
317 ret
= b43_read32(dev
, B43_MMIO_SHM_DATA
);
322 u16
b43_shm_read16(struct b43_wldev
* dev
, u16 routing
, u16 offset
)
326 if (routing
== B43_SHM_SHARED
) {
327 B43_WARN_ON(offset
& 0x0001);
328 if (offset
& 0x0003) {
329 /* Unaligned access */
330 b43_shm_control_word(dev
, routing
, offset
>> 2);
331 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
337 b43_shm_control_word(dev
, routing
, offset
);
338 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA
);
343 void b43_shm_write32(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u32 value
)
345 if (routing
== B43_SHM_SHARED
) {
346 B43_WARN_ON(offset
& 0x0001);
347 if (offset
& 0x0003) {
348 /* Unaligned access */
349 b43_shm_control_word(dev
, routing
, offset
>> 2);
351 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
,
352 (value
>> 16) & 0xffff);
354 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
356 b43_write16(dev
, B43_MMIO_SHM_DATA
, value
& 0xffff);
361 b43_shm_control_word(dev
, routing
, offset
);
363 b43_write32(dev
, B43_MMIO_SHM_DATA
, value
);
366 void b43_shm_write16(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u16 value
)
368 if (routing
== B43_SHM_SHARED
) {
369 B43_WARN_ON(offset
& 0x0001);
370 if (offset
& 0x0003) {
371 /* Unaligned access */
372 b43_shm_control_word(dev
, routing
, offset
>> 2);
374 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
, value
);
379 b43_shm_control_word(dev
, routing
, offset
);
381 b43_write16(dev
, B43_MMIO_SHM_DATA
, value
);
385 u32
b43_hf_read(struct b43_wldev
* dev
)
389 ret
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFHI
);
391 ret
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFLO
);
396 /* Write HostFlags */
397 void b43_hf_write(struct b43_wldev
*dev
, u32 value
)
399 b43_shm_write16(dev
, B43_SHM_SHARED
,
400 B43_SHM_SH_HOSTFLO
, (value
& 0x0000FFFF));
401 b43_shm_write16(dev
, B43_SHM_SHARED
,
402 B43_SHM_SH_HOSTFHI
, ((value
& 0xFFFF0000) >> 16));
405 void b43_tsf_read(struct b43_wldev
*dev
, u64
* tsf
)
407 /* We need to be careful. As we read the TSF from multiple
408 * registers, we should take care of register overflows.
409 * In theory, the whole tsf read process should be atomic.
410 * We try to be atomic here, by restaring the read process,
411 * if any of the high registers changed (overflew).
413 if (dev
->dev
->id
.revision
>= 3) {
414 u32 low
, high
, high2
;
417 high
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
);
418 low
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
);
419 high2
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
);
420 } while (unlikely(high
!= high2
));
428 u16 test1
, test2
, test3
;
431 v3
= b43_read16(dev
, B43_MMIO_TSF_3
);
432 v2
= b43_read16(dev
, B43_MMIO_TSF_2
);
433 v1
= b43_read16(dev
, B43_MMIO_TSF_1
);
434 v0
= b43_read16(dev
, B43_MMIO_TSF_0
);
436 test3
= b43_read16(dev
, B43_MMIO_TSF_3
);
437 test2
= b43_read16(dev
, B43_MMIO_TSF_2
);
438 test1
= b43_read16(dev
, B43_MMIO_TSF_1
);
439 } while (v3
!= test3
|| v2
!= test2
|| v1
!= test1
);
453 static void b43_time_lock(struct b43_wldev
*dev
)
457 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
458 macctl
|= B43_MACCTL_TBTTHOLD
;
459 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
460 /* Commit the write */
461 b43_read32(dev
, B43_MMIO_MACCTL
);
464 static void b43_time_unlock(struct b43_wldev
*dev
)
468 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
469 macctl
&= ~B43_MACCTL_TBTTHOLD
;
470 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
471 /* Commit the write */
472 b43_read32(dev
, B43_MMIO_MACCTL
);
475 static void b43_tsf_write_locked(struct b43_wldev
*dev
, u64 tsf
)
477 /* Be careful with the in-progress timer.
478 * First zero out the low register, so we have a full
479 * register-overflow duration to complete the operation.
481 if (dev
->dev
->id
.revision
>= 3) {
482 u32 lo
= (tsf
& 0x00000000FFFFFFFFULL
);
483 u32 hi
= (tsf
& 0xFFFFFFFF00000000ULL
) >> 32;
485 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
, 0);
487 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
, hi
);
489 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
, lo
);
491 u16 v0
= (tsf
& 0x000000000000FFFFULL
);
492 u16 v1
= (tsf
& 0x00000000FFFF0000ULL
) >> 16;
493 u16 v2
= (tsf
& 0x0000FFFF00000000ULL
) >> 32;
494 u16 v3
= (tsf
& 0xFFFF000000000000ULL
) >> 48;
496 b43_write16(dev
, B43_MMIO_TSF_0
, 0);
498 b43_write16(dev
, B43_MMIO_TSF_3
, v3
);
500 b43_write16(dev
, B43_MMIO_TSF_2
, v2
);
502 b43_write16(dev
, B43_MMIO_TSF_1
, v1
);
504 b43_write16(dev
, B43_MMIO_TSF_0
, v0
);
508 void b43_tsf_write(struct b43_wldev
*dev
, u64 tsf
)
511 b43_tsf_write_locked(dev
, tsf
);
512 b43_time_unlock(dev
);
516 void b43_macfilter_set(struct b43_wldev
*dev
, u16 offset
, const u8
* mac
)
518 static const u8 zero_addr
[ETH_ALEN
] = { 0 };
525 b43_write16(dev
, B43_MMIO_MACFILTER_CONTROL
, offset
);
529 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
532 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
535 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
538 static void b43_write_mac_bssid_templates(struct b43_wldev
*dev
)
542 u8 mac_bssid
[ETH_ALEN
* 2];
546 bssid
= dev
->wl
->bssid
;
547 mac
= dev
->wl
->mac_addr
;
549 b43_macfilter_set(dev
, B43_MACFILTER_BSSID
, bssid
);
551 memcpy(mac_bssid
, mac
, ETH_ALEN
);
552 memcpy(mac_bssid
+ ETH_ALEN
, bssid
, ETH_ALEN
);
554 /* Write our MAC address and BSSID to template ram */
555 for (i
= 0; i
< ARRAY_SIZE(mac_bssid
); i
+= sizeof(u32
)) {
556 tmp
= (u32
) (mac_bssid
[i
+ 0]);
557 tmp
|= (u32
) (mac_bssid
[i
+ 1]) << 8;
558 tmp
|= (u32
) (mac_bssid
[i
+ 2]) << 16;
559 tmp
|= (u32
) (mac_bssid
[i
+ 3]) << 24;
560 b43_ram_write(dev
, 0x20 + i
, tmp
);
564 static void b43_upload_card_macaddress(struct b43_wldev
*dev
,
568 memcpy(dev
->wl
->mac_addr
, mac_addr
, ETH_ALEN
);
570 memset(dev
->wl
->mac_addr
, 0, ETH_ALEN
);
571 b43_write_mac_bssid_templates(dev
);
572 b43_macfilter_set(dev
, B43_MACFILTER_SELF
, mac_addr
);
575 static void b43_set_slot_time(struct b43_wldev
*dev
, u16 slot_time
)
577 /* slot_time is in usec. */
578 if (dev
->phy
.type
!= B43_PHYTYPE_G
)
580 b43_write16(dev
, 0x684, 510 + slot_time
);
581 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0010, slot_time
);
584 static void b43_short_slot_timing_enable(struct b43_wldev
*dev
)
586 b43_set_slot_time(dev
, 9);
590 static void b43_short_slot_timing_disable(struct b43_wldev
*dev
)
592 b43_set_slot_time(dev
, 20);
596 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
597 * Returns the _previously_ enabled IRQ mask.
599 static inline u32
b43_interrupt_enable(struct b43_wldev
*dev
, u32 mask
)
603 old_mask
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
604 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, old_mask
| mask
);
609 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
610 * Returns the _previously_ enabled IRQ mask.
612 static inline u32
b43_interrupt_disable(struct b43_wldev
*dev
, u32 mask
)
616 old_mask
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
617 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, old_mask
& ~mask
);
622 /* Synchronize IRQ top- and bottom-half.
623 * IRQs must be masked before calling this.
624 * This must not be called with the irq_lock held.
626 static void b43_synchronize_irq(struct b43_wldev
*dev
)
628 synchronize_irq(dev
->dev
->irq
);
629 tasklet_kill(&dev
->isr_tasklet
);
632 /* DummyTransmission function, as documented on
633 * http://bcm-specs.sipsolutions.net/DummyTransmission
635 void b43_dummy_transmission(struct b43_wldev
*dev
)
637 struct b43_phy
*phy
= &dev
->phy
;
638 unsigned int i
, max_loop
;
651 buffer
[0] = 0x000201CC;
656 buffer
[0] = 0x000B846E;
663 for (i
= 0; i
< 5; i
++)
664 b43_ram_write(dev
, i
* 4, buffer
[i
]);
667 b43_read32(dev
, B43_MMIO_MACCTL
);
669 b43_write16(dev
, 0x0568, 0x0000);
670 b43_write16(dev
, 0x07C0, 0x0000);
671 value
= ((phy
->type
== B43_PHYTYPE_A
) ? 1 : 0);
672 b43_write16(dev
, 0x050C, value
);
673 b43_write16(dev
, 0x0508, 0x0000);
674 b43_write16(dev
, 0x050A, 0x0000);
675 b43_write16(dev
, 0x054C, 0x0000);
676 b43_write16(dev
, 0x056A, 0x0014);
677 b43_write16(dev
, 0x0568, 0x0826);
678 b43_write16(dev
, 0x0500, 0x0000);
679 b43_write16(dev
, 0x0502, 0x0030);
681 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
682 b43_radio_write16(dev
, 0x0051, 0x0017);
683 for (i
= 0x00; i
< max_loop
; i
++) {
684 value
= b43_read16(dev
, 0x050E);
689 for (i
= 0x00; i
< 0x0A; i
++) {
690 value
= b43_read16(dev
, 0x050E);
695 for (i
= 0x00; i
< 0x0A; i
++) {
696 value
= b43_read16(dev
, 0x0690);
697 if (!(value
& 0x0100))
701 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
702 b43_radio_write16(dev
, 0x0051, 0x0037);
705 static void key_write(struct b43_wldev
*dev
,
706 u8 index
, u8 algorithm
, const u8
* key
)
713 /* Key index/algo block */
714 kidx
= b43_kidx_to_fw(dev
, index
);
715 value
= ((kidx
<< 4) | algorithm
);
716 b43_shm_write16(dev
, B43_SHM_SHARED
,
717 B43_SHM_SH_KEYIDXBLOCK
+ (kidx
* 2), value
);
719 /* Write the key to the Key Table Pointer offset */
720 offset
= dev
->ktp
+ (index
* B43_SEC_KEYSIZE
);
721 for (i
= 0; i
< B43_SEC_KEYSIZE
; i
+= 2) {
723 value
|= (u16
) (key
[i
+ 1]) << 8;
724 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
, value
);
728 static void keymac_write(struct b43_wldev
*dev
, u8 index
, const u8
* addr
)
730 u32 addrtmp
[2] = { 0, 0, };
731 u8 per_sta_keys_start
= 8;
733 if (b43_new_kidx_api(dev
))
734 per_sta_keys_start
= 4;
736 B43_WARN_ON(index
< per_sta_keys_start
);
737 /* We have two default TX keys and possibly two default RX keys.
738 * Physical mac 0 is mapped to physical key 4 or 8, depending
739 * on the firmware version.
740 * So we must adjust the index here.
742 index
-= per_sta_keys_start
;
745 addrtmp
[0] = addr
[0];
746 addrtmp
[0] |= ((u32
) (addr
[1]) << 8);
747 addrtmp
[0] |= ((u32
) (addr
[2]) << 16);
748 addrtmp
[0] |= ((u32
) (addr
[3]) << 24);
749 addrtmp
[1] = addr
[4];
750 addrtmp
[1] |= ((u32
) (addr
[5]) << 8);
753 if (dev
->dev
->id
.revision
>= 5) {
754 /* Receive match transmitter address mechanism */
755 b43_shm_write32(dev
, B43_SHM_RCMTA
,
756 (index
* 2) + 0, addrtmp
[0]);
757 b43_shm_write16(dev
, B43_SHM_RCMTA
,
758 (index
* 2) + 1, addrtmp
[1]);
760 /* RXE (Receive Engine) and
761 * PSM (Programmable State Machine) mechanism
764 /* TODO write to RCM 16, 19, 22 and 25 */
766 b43_shm_write32(dev
, B43_SHM_SHARED
,
767 B43_SHM_SH_PSM
+ (index
* 6) + 0,
769 b43_shm_write16(dev
, B43_SHM_SHARED
,
770 B43_SHM_SH_PSM
+ (index
* 6) + 4,
776 static void do_key_write(struct b43_wldev
*dev
,
777 u8 index
, u8 algorithm
,
778 const u8
* key
, size_t key_len
, const u8
* mac_addr
)
780 u8 buf
[B43_SEC_KEYSIZE
] = { 0, };
781 u8 per_sta_keys_start
= 8;
783 if (b43_new_kidx_api(dev
))
784 per_sta_keys_start
= 4;
786 B43_WARN_ON(index
>= dev
->max_nr_keys
);
787 B43_WARN_ON(key_len
> B43_SEC_KEYSIZE
);
789 if (index
>= per_sta_keys_start
)
790 keymac_write(dev
, index
, NULL
); /* First zero out mac. */
792 memcpy(buf
, key
, key_len
);
793 key_write(dev
, index
, algorithm
, buf
);
794 if (index
>= per_sta_keys_start
)
795 keymac_write(dev
, index
, mac_addr
);
797 dev
->key
[index
].algorithm
= algorithm
;
800 static int b43_key_write(struct b43_wldev
*dev
,
801 int index
, u8 algorithm
,
802 const u8
* key
, size_t key_len
,
804 struct ieee80211_key_conf
*keyconf
)
809 if (key_len
> B43_SEC_KEYSIZE
)
811 for (i
= 0; i
< dev
->max_nr_keys
; i
++) {
812 /* Check that we don't already have this key. */
813 B43_WARN_ON(dev
->key
[i
].keyconf
== keyconf
);
816 /* Either pairwise key or address is 00:00:00:00:00:00
817 * for transmit-only keys. Search the index. */
818 if (b43_new_kidx_api(dev
))
822 for (i
= sta_keys_start
; i
< dev
->max_nr_keys
; i
++) {
823 if (!dev
->key
[i
].keyconf
) {
830 b43err(dev
->wl
, "Out of hardware key memory\n");
834 B43_WARN_ON(index
> 3);
836 do_key_write(dev
, index
, algorithm
, key
, key_len
, mac_addr
);
837 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
839 B43_WARN_ON(mac_addr
);
840 do_key_write(dev
, index
+ 4, algorithm
, key
, key_len
, NULL
);
842 keyconf
->hw_key_idx
= index
;
843 dev
->key
[index
].keyconf
= keyconf
;
848 static int b43_key_clear(struct b43_wldev
*dev
, int index
)
850 if (B43_WARN_ON((index
< 0) || (index
>= dev
->max_nr_keys
)))
852 do_key_write(dev
, index
, B43_SEC_ALGO_NONE
,
853 NULL
, B43_SEC_KEYSIZE
, NULL
);
854 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
855 do_key_write(dev
, index
+ 4, B43_SEC_ALGO_NONE
,
856 NULL
, B43_SEC_KEYSIZE
, NULL
);
858 dev
->key
[index
].keyconf
= NULL
;
863 static void b43_clear_keys(struct b43_wldev
*dev
)
867 for (i
= 0; i
< dev
->max_nr_keys
; i
++)
868 b43_key_clear(dev
, i
);
871 void b43_power_saving_ctl_bits(struct b43_wldev
*dev
, unsigned int ps_flags
)
879 B43_WARN_ON((ps_flags
& B43_PS_ENABLED
) &&
880 (ps_flags
& B43_PS_DISABLED
));
881 B43_WARN_ON((ps_flags
& B43_PS_AWAKE
) && (ps_flags
& B43_PS_ASLEEP
));
883 if (ps_flags
& B43_PS_ENABLED
) {
885 } else if (ps_flags
& B43_PS_DISABLED
) {
888 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
889 // and thus is not an AP and we are associated, set bit 25
891 if (ps_flags
& B43_PS_AWAKE
) {
893 } else if (ps_flags
& B43_PS_ASLEEP
) {
896 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
897 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
898 // successful, set bit26
901 /* FIXME: For now we force awake-on and hwps-off */
905 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
907 macctl
|= B43_MACCTL_HWPS
;
909 macctl
&= ~B43_MACCTL_HWPS
;
911 macctl
|= B43_MACCTL_AWAKE
;
913 macctl
&= ~B43_MACCTL_AWAKE
;
914 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
916 b43_read32(dev
, B43_MMIO_MACCTL
);
917 if (awake
&& dev
->dev
->id
.revision
>= 5) {
918 /* Wait for the microcode to wake up. */
919 for (i
= 0; i
< 100; i
++) {
920 ucstat
= b43_shm_read16(dev
, B43_SHM_SHARED
,
921 B43_SHM_SH_UCODESTAT
);
922 if (ucstat
!= B43_SHM_SH_UCODESTAT_SLEEP
)
929 /* Turn the Analog ON/OFF */
930 static void b43_switch_analog(struct b43_wldev
*dev
, int on
)
932 b43_write16(dev
, B43_MMIO_PHY0
, on
? 0 : 0xF4);
935 void b43_wireless_core_reset(struct b43_wldev
*dev
, u32 flags
)
940 flags
|= B43_TMSLOW_PHYCLKEN
;
941 flags
|= B43_TMSLOW_PHYRESET
;
942 ssb_device_enable(dev
->dev
, flags
);
943 msleep(2); /* Wait for the PLL to turn on. */
945 /* Now take the PHY out of Reset again */
946 tmslow
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
947 tmslow
|= SSB_TMSLOW_FGC
;
948 tmslow
&= ~B43_TMSLOW_PHYRESET
;
949 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
950 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
952 tmslow
&= ~SSB_TMSLOW_FGC
;
953 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
954 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
958 b43_switch_analog(dev
, 1);
960 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
961 macctl
&= ~B43_MACCTL_GMODE
;
962 if (flags
& B43_TMSLOW_GMODE
)
963 macctl
|= B43_MACCTL_GMODE
;
964 macctl
|= B43_MACCTL_IHR_ENABLED
;
965 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
968 static void handle_irq_transmit_status(struct b43_wldev
*dev
)
972 struct b43_txstatus stat
;
975 v0
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
976 if (!(v0
& 0x00000001))
978 v1
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
980 stat
.cookie
= (v0
>> 16);
981 stat
.seq
= (v1
& 0x0000FFFF);
982 stat
.phy_stat
= ((v1
& 0x00FF0000) >> 16);
983 tmp
= (v0
& 0x0000FFFF);
984 stat
.frame_count
= ((tmp
& 0xF000) >> 12);
985 stat
.rts_count
= ((tmp
& 0x0F00) >> 8);
986 stat
.supp_reason
= ((tmp
& 0x001C) >> 2);
987 stat
.pm_indicated
= !!(tmp
& 0x0080);
988 stat
.intermediate
= !!(tmp
& 0x0040);
989 stat
.for_ampdu
= !!(tmp
& 0x0020);
990 stat
.acked
= !!(tmp
& 0x0002);
992 b43_handle_txstatus(dev
, &stat
);
996 static void drain_txstatus_queue(struct b43_wldev
*dev
)
1000 if (dev
->dev
->id
.revision
< 5)
1002 /* Read all entries from the microcode TXstatus FIFO
1003 * and throw them away.
1006 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
1007 if (!(dummy
& 0x00000001))
1009 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
1013 static u32
b43_jssi_read(struct b43_wldev
*dev
)
1017 val
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x08A);
1019 val
|= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x088);
1024 static void b43_jssi_write(struct b43_wldev
*dev
, u32 jssi
)
1026 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x088, (jssi
& 0x0000FFFF));
1027 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x08A, (jssi
& 0xFFFF0000) >> 16);
1030 static void b43_generate_noise_sample(struct b43_wldev
*dev
)
1032 b43_jssi_write(dev
, 0x7F7F7F7F);
1033 b43_write32(dev
, B43_MMIO_STATUS2_BITFIELD
,
1034 b43_read32(dev
, B43_MMIO_STATUS2_BITFIELD
)
1036 B43_WARN_ON(dev
->noisecalc
.channel_at_start
!= dev
->phy
.channel
);
1039 static void b43_calculate_link_quality(struct b43_wldev
*dev
)
1041 /* Top half of Link Quality calculation. */
1043 if (dev
->noisecalc
.calculation_running
)
1045 dev
->noisecalc
.channel_at_start
= dev
->phy
.channel
;
1046 dev
->noisecalc
.calculation_running
= 1;
1047 dev
->noisecalc
.nr_samples
= 0;
1049 b43_generate_noise_sample(dev
);
1052 static void handle_irq_noise(struct b43_wldev
*dev
)
1054 struct b43_phy
*phy
= &dev
->phy
;
1060 /* Bottom half of Link Quality calculation. */
1062 B43_WARN_ON(!dev
->noisecalc
.calculation_running
);
1063 if (dev
->noisecalc
.channel_at_start
!= phy
->channel
)
1064 goto drop_calculation
;
1065 *((u32
*) noise
) = cpu_to_le32(b43_jssi_read(dev
));
1066 if (noise
[0] == 0x7F || noise
[1] == 0x7F ||
1067 noise
[2] == 0x7F || noise
[3] == 0x7F)
1070 /* Get the noise samples. */
1071 B43_WARN_ON(dev
->noisecalc
.nr_samples
>= 8);
1072 i
= dev
->noisecalc
.nr_samples
;
1073 noise
[0] = limit_value(noise
[0], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1074 noise
[1] = limit_value(noise
[1], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1075 noise
[2] = limit_value(noise
[2], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1076 noise
[3] = limit_value(noise
[3], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1077 dev
->noisecalc
.samples
[i
][0] = phy
->nrssi_lt
[noise
[0]];
1078 dev
->noisecalc
.samples
[i
][1] = phy
->nrssi_lt
[noise
[1]];
1079 dev
->noisecalc
.samples
[i
][2] = phy
->nrssi_lt
[noise
[2]];
1080 dev
->noisecalc
.samples
[i
][3] = phy
->nrssi_lt
[noise
[3]];
1081 dev
->noisecalc
.nr_samples
++;
1082 if (dev
->noisecalc
.nr_samples
== 8) {
1083 /* Calculate the Link Quality by the noise samples. */
1085 for (i
= 0; i
< 8; i
++) {
1086 for (j
= 0; j
< 4; j
++)
1087 average
+= dev
->noisecalc
.samples
[i
][j
];
1093 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x40C);
1094 tmp
= (tmp
/ 128) & 0x1F;
1104 dev
->stats
.link_noise
= average
;
1106 dev
->noisecalc
.calculation_running
= 0;
1110 b43_generate_noise_sample(dev
);
1113 static void handle_irq_tbtt_indication(struct b43_wldev
*dev
)
1115 if (b43_is_mode(dev
->wl
, IEEE80211_IF_TYPE_AP
)) {
1118 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1119 b43_power_saving_ctl_bits(dev
, 0);
1121 dev
->reg124_set_0x4
= 0;
1122 if (b43_is_mode(dev
->wl
, IEEE80211_IF_TYPE_IBSS
))
1123 dev
->reg124_set_0x4
= 1;
1126 static void handle_irq_atim_end(struct b43_wldev
*dev
)
1128 if (!dev
->reg124_set_0x4
/*FIXME rename this variable */ )
1130 b43_write32(dev
, B43_MMIO_STATUS2_BITFIELD
,
1131 b43_read32(dev
, B43_MMIO_STATUS2_BITFIELD
)
1135 static void handle_irq_pmq(struct b43_wldev
*dev
)
1142 tmp
= b43_read32(dev
, B43_MMIO_PS_STATUS
);
1143 if (!(tmp
& 0x00000008))
1146 /* 16bit write is odd, but correct. */
1147 b43_write16(dev
, B43_MMIO_PS_STATUS
, 0x0002);
1150 static void b43_write_template_common(struct b43_wldev
*dev
,
1151 const u8
* data
, u16 size
,
1153 u16 shm_size_offset
, u8 rate
)
1156 struct b43_plcp_hdr4 plcp
;
1159 b43_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1160 b43_ram_write(dev
, ram_offset
, le32_to_cpu(plcp
.data
));
1161 ram_offset
+= sizeof(u32
);
1162 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1163 * So leave the first two bytes of the next write blank.
1165 tmp
= (u32
) (data
[0]) << 16;
1166 tmp
|= (u32
) (data
[1]) << 24;
1167 b43_ram_write(dev
, ram_offset
, tmp
);
1168 ram_offset
+= sizeof(u32
);
1169 for (i
= 2; i
< size
; i
+= sizeof(u32
)) {
1170 tmp
= (u32
) (data
[i
+ 0]);
1172 tmp
|= (u32
) (data
[i
+ 1]) << 8;
1174 tmp
|= (u32
) (data
[i
+ 2]) << 16;
1176 tmp
|= (u32
) (data
[i
+ 3]) << 24;
1177 b43_ram_write(dev
, ram_offset
+ i
- 2, tmp
);
1179 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_size_offset
,
1180 size
+ sizeof(struct b43_plcp_hdr6
));
1183 static void b43_write_beacon_template(struct b43_wldev
*dev
,
1185 u16 shm_size_offset
, u8 rate
)
1190 B43_WARN_ON(!dev
->cached_beacon
);
1191 len
= min((size_t) dev
->cached_beacon
->len
,
1192 0x200 - sizeof(struct b43_plcp_hdr6
));
1193 data
= (const u8
*)(dev
->cached_beacon
->data
);
1194 b43_write_template_common(dev
, data
,
1195 len
, ram_offset
, shm_size_offset
, rate
);
1198 static void b43_write_probe_resp_plcp(struct b43_wldev
*dev
,
1199 u16 shm_offset
, u16 size
, u8 rate
)
1201 struct b43_plcp_hdr4 plcp
;
1206 b43_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1207 dur
= ieee80211_generic_frame_duration(dev
->wl
->hw
,
1208 dev
->wl
->if_id
, size
,
1209 B43_RATE_TO_BASE100KBPS(rate
));
1210 /* Write PLCP in two parts and timing for packet transfer */
1211 tmp
= le32_to_cpu(plcp
.data
);
1212 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
, tmp
& 0xFFFF);
1213 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
+ 2, tmp
>> 16);
1214 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
+ 6, le16_to_cpu(dur
));
1217 /* Instead of using custom probe response template, this function
1218 * just patches custom beacon template by:
1219 * 1) Changing packet type
1220 * 2) Patching duration field
1223 static u8
*b43_generate_probe_resp(struct b43_wldev
*dev
,
1224 u16
* dest_size
, u8 rate
)
1228 u16 src_size
, elem_size
, src_pos
, dest_pos
;
1230 struct ieee80211_hdr
*hdr
;
1232 B43_WARN_ON(!dev
->cached_beacon
);
1233 src_size
= dev
->cached_beacon
->len
;
1234 src_data
= (const u8
*)dev
->cached_beacon
->data
;
1236 if (unlikely(src_size
< 0x24)) {
1237 b43dbg(dev
->wl
, "b43_generate_probe_resp: " "invalid beacon\n");
1241 dest_data
= kmalloc(src_size
, GFP_ATOMIC
);
1242 if (unlikely(!dest_data
))
1245 /* 0x24 is offset of first variable-len Information-Element
1248 memcpy(dest_data
, src_data
, 0x24);
1249 src_pos
= dest_pos
= 0x24;
1250 for (; src_pos
< src_size
- 2; src_pos
+= elem_size
) {
1251 elem_size
= src_data
[src_pos
+ 1] + 2;
1252 if (src_data
[src_pos
] != 0x05) { /* TIM */
1253 memcpy(dest_data
+ dest_pos
, src_data
+ src_pos
,
1255 dest_pos
+= elem_size
;
1258 *dest_size
= dest_pos
;
1259 hdr
= (struct ieee80211_hdr
*)dest_data
;
1261 /* Set the frame control. */
1262 hdr
->frame_control
= cpu_to_le16(IEEE80211_FTYPE_MGMT
|
1263 IEEE80211_STYPE_PROBE_RESP
);
1264 dur
= ieee80211_generic_frame_duration(dev
->wl
->hw
,
1265 dev
->wl
->if_id
, *dest_size
,
1266 B43_RATE_TO_BASE100KBPS(rate
));
1267 hdr
->duration_id
= dur
;
1272 static void b43_write_probe_resp_template(struct b43_wldev
*dev
,
1274 u16 shm_size_offset
, u8 rate
)
1276 u8
*probe_resp_data
;
1279 B43_WARN_ON(!dev
->cached_beacon
);
1280 size
= dev
->cached_beacon
->len
;
1281 probe_resp_data
= b43_generate_probe_resp(dev
, &size
, rate
);
1282 if (unlikely(!probe_resp_data
))
1285 /* Looks like PLCP headers plus packet timings are stored for
1286 * all possible basic rates
1288 b43_write_probe_resp_plcp(dev
, 0x31A, size
, B43_CCK_RATE_1MB
);
1289 b43_write_probe_resp_plcp(dev
, 0x32C, size
, B43_CCK_RATE_2MB
);
1290 b43_write_probe_resp_plcp(dev
, 0x33E, size
, B43_CCK_RATE_5MB
);
1291 b43_write_probe_resp_plcp(dev
, 0x350, size
, B43_CCK_RATE_11MB
);
1293 size
= min((size_t) size
, 0x200 - sizeof(struct b43_plcp_hdr6
));
1294 b43_write_template_common(dev
, probe_resp_data
,
1295 size
, ram_offset
, shm_size_offset
, rate
);
1296 kfree(probe_resp_data
);
1299 static int b43_refresh_cached_beacon(struct b43_wldev
*dev
,
1300 struct sk_buff
*beacon
)
1302 if (dev
->cached_beacon
)
1303 kfree_skb(dev
->cached_beacon
);
1304 dev
->cached_beacon
= beacon
;
1309 static void b43_update_templates(struct b43_wldev
*dev
)
1313 B43_WARN_ON(!dev
->cached_beacon
);
1315 b43_write_beacon_template(dev
, 0x68, 0x18, B43_CCK_RATE_1MB
);
1316 b43_write_beacon_template(dev
, 0x468, 0x1A, B43_CCK_RATE_1MB
);
1317 b43_write_probe_resp_template(dev
, 0x268, 0x4A, B43_CCK_RATE_11MB
);
1319 status
= b43_read32(dev
, B43_MMIO_STATUS2_BITFIELD
);
1321 b43_write32(dev
, B43_MMIO_STATUS2_BITFIELD
, status
);
1324 static void b43_refresh_templates(struct b43_wldev
*dev
, struct sk_buff
*beacon
)
1328 err
= b43_refresh_cached_beacon(dev
, beacon
);
1331 b43_update_templates(dev
);
1334 static void b43_set_ssid(struct b43_wldev
*dev
, const u8
* ssid
, u8 ssid_len
)
1339 len
= min((u16
) ssid_len
, (u16
) 0x100);
1340 for (i
= 0; i
< len
; i
+= sizeof(u32
)) {
1341 tmp
= (u32
) (ssid
[i
+ 0]);
1343 tmp
|= (u32
) (ssid
[i
+ 1]) << 8;
1345 tmp
|= (u32
) (ssid
[i
+ 2]) << 16;
1347 tmp
|= (u32
) (ssid
[i
+ 3]) << 24;
1348 b43_shm_write32(dev
, B43_SHM_SHARED
, 0x380 + i
, tmp
);
1350 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x48, len
);
1353 static void b43_set_beacon_int(struct b43_wldev
*dev
, u16 beacon_int
)
1356 if (dev
->dev
->id
.revision
>= 3) {
1357 b43_write32(dev
, 0x188, (beacon_int
<< 16));
1359 b43_write16(dev
, 0x606, (beacon_int
>> 6));
1360 b43_write16(dev
, 0x610, beacon_int
);
1362 b43_time_unlock(dev
);
1365 static void handle_irq_beacon(struct b43_wldev
*dev
)
1369 if (!b43_is_mode(dev
->wl
, IEEE80211_IF_TYPE_AP
))
1372 dev
->irq_savedstate
&= ~B43_IRQ_BEACON
;
1373 status
= b43_read32(dev
, B43_MMIO_STATUS2_BITFIELD
);
1375 if (!dev
->cached_beacon
|| ((status
& 0x1) && (status
& 0x2))) {
1376 /* ACK beacon IRQ. */
1377 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_BEACON
);
1378 dev
->irq_savedstate
|= B43_IRQ_BEACON
;
1379 if (dev
->cached_beacon
)
1380 kfree_skb(dev
->cached_beacon
);
1381 dev
->cached_beacon
= NULL
;
1384 if (!(status
& 0x1)) {
1385 b43_write_beacon_template(dev
, 0x68, 0x18, B43_CCK_RATE_1MB
);
1387 b43_write32(dev
, B43_MMIO_STATUS2_BITFIELD
, status
);
1389 if (!(status
& 0x2)) {
1390 b43_write_beacon_template(dev
, 0x468, 0x1A, B43_CCK_RATE_1MB
);
1392 b43_write32(dev
, B43_MMIO_STATUS2_BITFIELD
, status
);
1396 static void handle_irq_ucode_debug(struct b43_wldev
*dev
)
1401 /* Interrupt handler bottom-half */
1402 static void b43_interrupt_tasklet(struct b43_wldev
*dev
)
1405 u32 dma_reason
[ARRAY_SIZE(dev
->dma_reason
)];
1406 u32 merged_dma_reason
= 0;
1407 int i
, activity
= 0;
1408 unsigned long flags
;
1410 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
1412 B43_WARN_ON(b43_status(dev
) != B43_STAT_STARTED
);
1414 reason
= dev
->irq_reason
;
1415 for (i
= 0; i
< ARRAY_SIZE(dma_reason
); i
++) {
1416 dma_reason
[i
] = dev
->dma_reason
[i
];
1417 merged_dma_reason
|= dma_reason
[i
];
1420 if (unlikely(reason
& B43_IRQ_MAC_TXERR
))
1421 b43err(dev
->wl
, "MAC transmission error\n");
1423 if (unlikely(reason
& B43_IRQ_PHY_TXERR
))
1424 b43err(dev
->wl
, "PHY transmission error\n");
1426 if (unlikely(merged_dma_reason
& (B43_DMAIRQ_FATALMASK
|
1427 B43_DMAIRQ_NONFATALMASK
))) {
1428 if (merged_dma_reason
& B43_DMAIRQ_FATALMASK
) {
1429 b43err(dev
->wl
, "Fatal DMA error: "
1430 "0x%08X, 0x%08X, 0x%08X, "
1431 "0x%08X, 0x%08X, 0x%08X\n",
1432 dma_reason
[0], dma_reason
[1],
1433 dma_reason
[2], dma_reason
[3],
1434 dma_reason
[4], dma_reason
[5]);
1435 b43_controller_restart(dev
, "DMA error");
1437 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
1440 if (merged_dma_reason
& B43_DMAIRQ_NONFATALMASK
) {
1441 b43err(dev
->wl
, "DMA error: "
1442 "0x%08X, 0x%08X, 0x%08X, "
1443 "0x%08X, 0x%08X, 0x%08X\n",
1444 dma_reason
[0], dma_reason
[1],
1445 dma_reason
[2], dma_reason
[3],
1446 dma_reason
[4], dma_reason
[5]);
1450 if (unlikely(reason
& B43_IRQ_UCODE_DEBUG
))
1451 handle_irq_ucode_debug(dev
);
1452 if (reason
& B43_IRQ_TBTT_INDI
)
1453 handle_irq_tbtt_indication(dev
);
1454 if (reason
& B43_IRQ_ATIM_END
)
1455 handle_irq_atim_end(dev
);
1456 if (reason
& B43_IRQ_BEACON
)
1457 handle_irq_beacon(dev
);
1458 if (reason
& B43_IRQ_PMQ
)
1459 handle_irq_pmq(dev
);
1460 if (reason
& B43_IRQ_TXFIFO_FLUSH_OK
) ;
1461 /*TODO*/ if (reason
& B43_IRQ_NOISESAMPLE_OK
)
1462 handle_irq_noise(dev
);
1464 /* Check the DMA reason registers for received data. */
1465 if (dma_reason
[0] & B43_DMAIRQ_RX_DONE
) {
1466 if (b43_using_pio(dev
))
1467 b43_pio_rx(dev
->pio
.queue0
);
1469 b43_dma_rx(dev
->dma
.rx_ring0
);
1470 /* We intentionally don't set "activity" to 1, here. */
1472 B43_WARN_ON(dma_reason
[1] & B43_DMAIRQ_RX_DONE
);
1473 B43_WARN_ON(dma_reason
[2] & B43_DMAIRQ_RX_DONE
);
1474 if (dma_reason
[3] & B43_DMAIRQ_RX_DONE
) {
1475 if (b43_using_pio(dev
))
1476 b43_pio_rx(dev
->pio
.queue3
);
1478 b43_dma_rx(dev
->dma
.rx_ring3
);
1481 B43_WARN_ON(dma_reason
[4] & B43_DMAIRQ_RX_DONE
);
1482 B43_WARN_ON(dma_reason
[5] & B43_DMAIRQ_RX_DONE
);
1484 if (reason
& B43_IRQ_TX_OK
) {
1485 handle_irq_transmit_status(dev
);
1487 //TODO: In AP mode, this also causes sending of powersave responses.
1490 if (!modparam_noleds
)
1491 b43_leds_update(dev
, activity
);
1492 b43_interrupt_enable(dev
, dev
->irq_savedstate
);
1494 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
1497 static void pio_irq_workaround(struct b43_wldev
*dev
, u16 base
, int queueidx
)
1501 rxctl
= b43_read16(dev
, base
+ B43_PIO_RXCTL
);
1502 if (rxctl
& B43_PIO_RXCTL_DATAAVAILABLE
)
1503 dev
->dma_reason
[queueidx
] |= B43_DMAIRQ_RX_DONE
;
1505 dev
->dma_reason
[queueidx
] &= ~B43_DMAIRQ_RX_DONE
;
1508 static void b43_interrupt_ack(struct b43_wldev
*dev
, u32 reason
)
1510 if (b43_using_pio(dev
) &&
1511 (dev
->dev
->id
.revision
< 3) &&
1512 (!(reason
& B43_IRQ_PIO_WORKAROUND
))) {
1513 /* Apply a PIO specific workaround to the dma_reasons */
1514 pio_irq_workaround(dev
, B43_MMIO_PIO1_BASE
, 0);
1515 pio_irq_workaround(dev
, B43_MMIO_PIO2_BASE
, 1);
1516 pio_irq_workaround(dev
, B43_MMIO_PIO3_BASE
, 2);
1517 pio_irq_workaround(dev
, B43_MMIO_PIO4_BASE
, 3);
1520 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, reason
);
1522 b43_write32(dev
, B43_MMIO_DMA0_REASON
, dev
->dma_reason
[0]);
1523 b43_write32(dev
, B43_MMIO_DMA1_REASON
, dev
->dma_reason
[1]);
1524 b43_write32(dev
, B43_MMIO_DMA2_REASON
, dev
->dma_reason
[2]);
1525 b43_write32(dev
, B43_MMIO_DMA3_REASON
, dev
->dma_reason
[3]);
1526 b43_write32(dev
, B43_MMIO_DMA4_REASON
, dev
->dma_reason
[4]);
1527 b43_write32(dev
, B43_MMIO_DMA5_REASON
, dev
->dma_reason
[5]);
1530 /* Interrupt handler top-half */
1531 static irqreturn_t
b43_interrupt_handler(int irq
, void *dev_id
)
1533 irqreturn_t ret
= IRQ_NONE
;
1534 struct b43_wldev
*dev
= dev_id
;
1540 spin_lock(&dev
->wl
->irq_lock
);
1542 if (b43_status(dev
) < B43_STAT_STARTED
)
1544 reason
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
1545 if (reason
== 0xffffffff) /* shared IRQ */
1548 reason
&= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
1552 dev
->dma_reason
[0] = b43_read32(dev
, B43_MMIO_DMA0_REASON
)
1554 dev
->dma_reason
[1] = b43_read32(dev
, B43_MMIO_DMA1_REASON
)
1556 dev
->dma_reason
[2] = b43_read32(dev
, B43_MMIO_DMA2_REASON
)
1558 dev
->dma_reason
[3] = b43_read32(dev
, B43_MMIO_DMA3_REASON
)
1560 dev
->dma_reason
[4] = b43_read32(dev
, B43_MMIO_DMA4_REASON
)
1562 dev
->dma_reason
[5] = b43_read32(dev
, B43_MMIO_DMA5_REASON
)
1565 b43_interrupt_ack(dev
, reason
);
1566 /* disable all IRQs. They are enabled again in the bottom half. */
1567 dev
->irq_savedstate
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
1568 /* save the reason code and call our bottom half. */
1569 dev
->irq_reason
= reason
;
1570 tasklet_schedule(&dev
->isr_tasklet
);
1573 spin_unlock(&dev
->wl
->irq_lock
);
1578 static void b43_release_firmware(struct b43_wldev
*dev
)
1580 release_firmware(dev
->fw
.ucode
);
1581 dev
->fw
.ucode
= NULL
;
1582 release_firmware(dev
->fw
.pcm
);
1584 release_firmware(dev
->fw
.initvals
);
1585 dev
->fw
.initvals
= NULL
;
1586 release_firmware(dev
->fw
.initvals_band
);
1587 dev
->fw
.initvals_band
= NULL
;
1590 static void b43_print_fw_helptext(struct b43_wl
*wl
)
1592 b43err(wl
, "You must go to "
1593 "http://linuxwireless.org/en/users/Drivers/bcm43xx#devicefirmware "
1594 "and download the correct firmware (version 4).\n");
1597 static int do_request_fw(struct b43_wldev
*dev
,
1599 const struct firmware
**fw
)
1601 const size_t plen
= sizeof(modparam_fwpostfix
) + 32;
1603 struct b43_fw_header
*hdr
;
1610 snprintf(path
, ARRAY_SIZE(path
),
1612 modparam_fwpostfix
, name
);
1613 err
= request_firmware(fw
, path
, dev
->dev
->dev
);
1615 b43err(dev
->wl
, "Firmware file \"%s\" not found "
1616 "or load failed.\n", path
);
1619 if ((*fw
)->size
< sizeof(struct b43_fw_header
))
1621 hdr
= (struct b43_fw_header
*)((*fw
)->data
);
1622 switch (hdr
->type
) {
1623 case B43_FW_TYPE_UCODE
:
1624 case B43_FW_TYPE_PCM
:
1625 size
= be32_to_cpu(hdr
->size
);
1626 if (size
!= (*fw
)->size
- sizeof(struct b43_fw_header
))
1629 case B43_FW_TYPE_IV
:
1640 b43err(dev
->wl
, "Firmware file \"%s\" format error.\n", path
);
1644 static int b43_request_firmware(struct b43_wldev
*dev
)
1646 struct b43_firmware
*fw
= &dev
->fw
;
1647 const u8 rev
= dev
->dev
->id
.revision
;
1648 const char *filename
;
1652 tmshigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
1654 if ((rev
>= 5) && (rev
<= 10))
1655 filename
= "ucode5";
1656 else if ((rev
>= 11) && (rev
<= 12))
1657 filename
= "ucode11";
1659 filename
= "ucode13";
1662 err
= do_request_fw(dev
, filename
, &fw
->ucode
);
1667 if ((rev
>= 5) && (rev
<= 10))
1673 err
= do_request_fw(dev
, filename
, &fw
->pcm
);
1677 if (!fw
->initvals
) {
1678 switch (dev
->phy
.type
) {
1680 if ((rev
>= 5) && (rev
<= 10)) {
1681 if (tmshigh
& B43_TMSHIGH_GPHY
)
1682 filename
= "a0g1initvals5";
1684 filename
= "a0g0initvals5";
1686 goto err_no_initvals
;
1689 if ((rev
>= 5) && (rev
<= 10))
1690 filename
= "b0g0initvals5";
1692 filename
= "lp0initvals13";
1694 goto err_no_initvals
;
1697 goto err_no_initvals
;
1699 err
= do_request_fw(dev
, filename
, &fw
->initvals
);
1703 if (!fw
->initvals_band
) {
1704 switch (dev
->phy
.type
) {
1706 if ((rev
>= 5) && (rev
<= 10)) {
1707 if (tmshigh
& B43_TMSHIGH_GPHY
)
1708 filename
= "a0g1bsinitvals5";
1710 filename
= "a0g0bsinitvals5";
1711 } else if (rev
>= 11)
1714 goto err_no_initvals
;
1717 if ((rev
>= 5) && (rev
<= 10))
1718 filename
= "b0g0bsinitvals5";
1722 goto err_no_initvals
;
1725 goto err_no_initvals
;
1727 err
= do_request_fw(dev
, filename
, &fw
->initvals_band
);
1735 b43_print_fw_helptext(dev
->wl
);
1740 b43err(dev
->wl
, "No microcode available for core rev %u\n", rev
);
1745 b43err(dev
->wl
, "No PCM available for core rev %u\n", rev
);
1750 b43err(dev
->wl
, "No Initial Values firmware file for PHY %u, "
1751 "core rev %u\n", dev
->phy
.type
, rev
);
1755 b43_release_firmware(dev
);
1759 static int b43_upload_microcode(struct b43_wldev
*dev
)
1761 const size_t hdr_len
= sizeof(struct b43_fw_header
);
1763 unsigned int i
, len
;
1764 u16 fwrev
, fwpatch
, fwdate
, fwtime
;
1768 /* Upload Microcode. */
1769 data
= (__be32
*) (dev
->fw
.ucode
->data
+ hdr_len
);
1770 len
= (dev
->fw
.ucode
->size
- hdr_len
) / sizeof(__be32
);
1771 b43_shm_control_word(dev
, B43_SHM_UCODE
| B43_SHM_AUTOINC_W
, 0x0000);
1772 for (i
= 0; i
< len
; i
++) {
1773 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
1778 /* Upload PCM data. */
1779 data
= (__be32
*) (dev
->fw
.pcm
->data
+ hdr_len
);
1780 len
= (dev
->fw
.pcm
->size
- hdr_len
) / sizeof(__be32
);
1781 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EA);
1782 b43_write32(dev
, B43_MMIO_SHM_DATA
, 0x00004000);
1783 /* No need for autoinc bit in SHM_HW */
1784 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EB);
1785 for (i
= 0; i
< len
; i
++) {
1786 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
1791 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_ALL
);
1792 b43_write32(dev
, B43_MMIO_MACCTL
,
1793 B43_MACCTL_PSM_RUN
|
1794 B43_MACCTL_IHR_ENABLED
| B43_MACCTL_INFRA
);
1796 /* Wait for the microcode to load and respond */
1799 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
1800 if (tmp
== B43_IRQ_MAC_SUSPENDED
)
1804 b43err(dev
->wl
, "Microcode not responding\n");
1805 b43_print_fw_helptext(dev
->wl
);
1811 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
); /* dummy read */
1813 /* Get and check the revisions. */
1814 fwrev
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEREV
);
1815 fwpatch
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEPATCH
);
1816 fwdate
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEDATE
);
1817 fwtime
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODETIME
);
1819 if (fwrev
<= 0x128) {
1820 b43err(dev
->wl
, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1821 "binary drivers older than version 4.x is unsupported. "
1822 "You must upgrade your firmware files.\n");
1823 b43_print_fw_helptext(dev
->wl
);
1824 b43_write32(dev
, B43_MMIO_MACCTL
, 0);
1828 b43dbg(dev
->wl
, "Loading firmware version %u.%u "
1829 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1831 (fwdate
>> 12) & 0xF, (fwdate
>> 8) & 0xF, fwdate
& 0xFF,
1832 (fwtime
>> 11) & 0x1F, (fwtime
>> 5) & 0x3F, fwtime
& 0x1F);
1834 dev
->fw
.rev
= fwrev
;
1835 dev
->fw
.patch
= fwpatch
;
1841 static int b43_write_initvals(struct b43_wldev
*dev
,
1842 const struct b43_iv
*ivals
,
1846 const struct b43_iv
*iv
;
1851 BUILD_BUG_ON(sizeof(struct b43_iv
) != 6);
1853 for (i
= 0; i
< count
; i
++) {
1854 if (array_size
< sizeof(iv
->offset_size
))
1856 array_size
-= sizeof(iv
->offset_size
);
1857 offset
= be16_to_cpu(iv
->offset_size
);
1858 bit32
= !!(offset
& B43_IV_32BIT
);
1859 offset
&= B43_IV_OFFSET_MASK
;
1860 if (offset
>= 0x1000)
1865 if (array_size
< sizeof(iv
->data
.d32
))
1867 array_size
-= sizeof(iv
->data
.d32
);
1869 value
= be32_to_cpu(get_unaligned(&iv
->data
.d32
));
1870 b43_write32(dev
, offset
, value
);
1872 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
1878 if (array_size
< sizeof(iv
->data
.d16
))
1880 array_size
-= sizeof(iv
->data
.d16
);
1882 value
= be16_to_cpu(iv
->data
.d16
);
1883 b43_write16(dev
, offset
, value
);
1885 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
1896 b43err(dev
->wl
, "Initial Values Firmware file-format error.\n");
1897 b43_print_fw_helptext(dev
->wl
);
1902 static int b43_upload_initvals(struct b43_wldev
*dev
)
1904 const size_t hdr_len
= sizeof(struct b43_fw_header
);
1905 const struct b43_fw_header
*hdr
;
1906 struct b43_firmware
*fw
= &dev
->fw
;
1907 const struct b43_iv
*ivals
;
1911 hdr
= (const struct b43_fw_header
*)(fw
->initvals
->data
);
1912 ivals
= (const struct b43_iv
*)(fw
->initvals
->data
+ hdr_len
);
1913 count
= be32_to_cpu(hdr
->size
);
1914 err
= b43_write_initvals(dev
, ivals
, count
,
1915 fw
->initvals
->size
- hdr_len
);
1918 if (fw
->initvals_band
) {
1919 hdr
= (const struct b43_fw_header
*)(fw
->initvals_band
->data
);
1920 ivals
= (const struct b43_iv
*)(fw
->initvals_band
->data
+ hdr_len
);
1921 count
= be32_to_cpu(hdr
->size
);
1922 err
= b43_write_initvals(dev
, ivals
, count
,
1923 fw
->initvals_band
->size
- hdr_len
);
1932 /* Initialize the GPIOs
1933 * http://bcm-specs.sipsolutions.net/GPIO
1935 static int b43_gpio_init(struct b43_wldev
*dev
)
1937 struct ssb_bus
*bus
= dev
->dev
->bus
;
1938 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
1941 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
1942 & ~B43_MACCTL_GPOUTSMSK
);
1944 b43_leds_switch_all(dev
, 0);
1945 b43_write16(dev
, B43_MMIO_GPIO_MASK
, b43_read16(dev
, B43_MMIO_GPIO_MASK
)
1950 if (dev
->dev
->bus
->chip_id
== 0x4301) {
1954 if (0 /* FIXME: conditional unknown */ ) {
1955 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
1956 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
1961 if (dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& B43_BFL_PACTRL
) {
1962 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
1963 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
1968 if (dev
->dev
->id
.revision
>= 2)
1969 mask
|= 0x0010; /* FIXME: This is redundant. */
1971 #ifdef CONFIG_SSB_DRIVER_PCICORE
1972 pcidev
= bus
->pcicore
.dev
;
1974 gpiodev
= bus
->chipco
.dev
? : pcidev
;
1977 ssb_write32(gpiodev
, B43_GPIO_CONTROL
,
1978 (ssb_read32(gpiodev
, B43_GPIO_CONTROL
)
1984 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1985 static void b43_gpio_cleanup(struct b43_wldev
*dev
)
1987 struct ssb_bus
*bus
= dev
->dev
->bus
;
1988 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
1990 #ifdef CONFIG_SSB_DRIVER_PCICORE
1991 pcidev
= bus
->pcicore
.dev
;
1993 gpiodev
= bus
->chipco
.dev
? : pcidev
;
1996 ssb_write32(gpiodev
, B43_GPIO_CONTROL
, 0);
1999 /* http://bcm-specs.sipsolutions.net/EnableMac */
2000 void b43_mac_enable(struct b43_wldev
*dev
)
2002 dev
->mac_suspended
--;
2003 B43_WARN_ON(dev
->mac_suspended
< 0);
2004 if (dev
->mac_suspended
== 0) {
2005 b43_write32(dev
, B43_MMIO_MACCTL
,
2006 b43_read32(dev
, B43_MMIO_MACCTL
)
2007 | B43_MACCTL_ENABLED
);
2008 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
,
2009 B43_IRQ_MAC_SUSPENDED
);
2011 b43_read32(dev
, B43_MMIO_MACCTL
);
2012 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2013 b43_power_saving_ctl_bits(dev
, 0);
2017 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2018 void b43_mac_suspend(struct b43_wldev
*dev
)
2023 B43_WARN_ON(dev
->mac_suspended
< 0);
2024 if (dev
->mac_suspended
== 0) {
2025 b43_power_saving_ctl_bits(dev
, B43_PS_AWAKE
);
2026 b43_write32(dev
, B43_MMIO_MACCTL
,
2027 b43_read32(dev
, B43_MMIO_MACCTL
)
2028 & ~B43_MACCTL_ENABLED
);
2029 /* force pci to flush the write */
2030 b43_read32(dev
, B43_MMIO_MACCTL
);
2031 for (i
= 10000; i
; i
--) {
2032 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2033 if (tmp
& B43_IRQ_MAC_SUSPENDED
)
2037 b43err(dev
->wl
, "MAC suspend failed\n");
2040 dev
->mac_suspended
++;
2043 static void b43_adjust_opmode(struct b43_wldev
*dev
)
2045 struct b43_wl
*wl
= dev
->wl
;
2049 ctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2050 /* Reset status to STA infrastructure mode. */
2051 ctl
&= ~B43_MACCTL_AP
;
2052 ctl
&= ~B43_MACCTL_KEEP_CTL
;
2053 ctl
&= ~B43_MACCTL_KEEP_BADPLCP
;
2054 ctl
&= ~B43_MACCTL_KEEP_BAD
;
2055 ctl
&= ~B43_MACCTL_PROMISC
;
2056 ctl
|= B43_MACCTL_INFRA
;
2058 if (wl
->operating
) {
2059 switch (wl
->if_type
) {
2060 case IEEE80211_IF_TYPE_AP
:
2061 ctl
|= B43_MACCTL_AP
;
2063 case IEEE80211_IF_TYPE_IBSS
:
2064 ctl
&= ~B43_MACCTL_INFRA
;
2066 case IEEE80211_IF_TYPE_STA
:
2067 case IEEE80211_IF_TYPE_MNTR
:
2068 case IEEE80211_IF_TYPE_WDS
:
2075 ctl
|= B43_MACCTL_KEEP_CTL
;
2076 if (modparam_mon_keep_bad
)
2077 ctl
|= B43_MACCTL_KEEP_BAD
;
2078 if (modparam_mon_keep_badplcp
)
2079 ctl
|= B43_MACCTL_KEEP_BADPLCP
;
2082 ctl
|= B43_MACCTL_PROMISC
;
2083 /* Workaround: On old hardware the HW-MAC-address-filter
2084 * doesn't work properly, so always run promisc in filter
2085 * it in software. */
2086 if (dev
->dev
->id
.revision
<= 4)
2087 ctl
|= B43_MACCTL_PROMISC
;
2089 b43_write32(dev
, B43_MMIO_MACCTL
, ctl
);
2092 if ((ctl
& B43_MACCTL_INFRA
) && !(ctl
& B43_MACCTL_AP
)) {
2093 if (dev
->dev
->bus
->chip_id
== 0x4306 &&
2094 dev
->dev
->bus
->chip_rev
== 3)
2099 b43_write16(dev
, 0x612, cfp_pretbtt
);
2102 static void b43_rate_memory_write(struct b43_wldev
*dev
, u16 rate
, int is_ofdm
)
2108 offset
+= (b43_plcp_get_ratecode_ofdm(rate
) & 0x000F) * 2;
2111 offset
+= (b43_plcp_get_ratecode_cck(rate
) & 0x000F) * 2;
2113 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ 0x20,
2114 b43_shm_read16(dev
, B43_SHM_SHARED
, offset
));
2117 static void b43_rate_memory_init(struct b43_wldev
*dev
)
2119 switch (dev
->phy
.type
) {
2122 b43_rate_memory_write(dev
, B43_OFDM_RATE_6MB
, 1);
2123 b43_rate_memory_write(dev
, B43_OFDM_RATE_12MB
, 1);
2124 b43_rate_memory_write(dev
, B43_OFDM_RATE_18MB
, 1);
2125 b43_rate_memory_write(dev
, B43_OFDM_RATE_24MB
, 1);
2126 b43_rate_memory_write(dev
, B43_OFDM_RATE_36MB
, 1);
2127 b43_rate_memory_write(dev
, B43_OFDM_RATE_48MB
, 1);
2128 b43_rate_memory_write(dev
, B43_OFDM_RATE_54MB
, 1);
2129 if (dev
->phy
.type
== B43_PHYTYPE_A
)
2133 b43_rate_memory_write(dev
, B43_CCK_RATE_1MB
, 0);
2134 b43_rate_memory_write(dev
, B43_CCK_RATE_2MB
, 0);
2135 b43_rate_memory_write(dev
, B43_CCK_RATE_5MB
, 0);
2136 b43_rate_memory_write(dev
, B43_CCK_RATE_11MB
, 0);
2143 /* Set the TX-Antenna for management frames sent by firmware. */
2144 static void b43_mgmtframe_txantenna(struct b43_wldev
*dev
, int antenna
)
2151 ant
|= B43_TX4_PHY_ANT0
;
2154 ant
|= B43_TX4_PHY_ANT1
;
2156 case B43_ANTENNA_AUTO
:
2157 ant
|= B43_TX4_PHY_ANTLAST
;
2163 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2166 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
);
2167 tmp
= (tmp
& ~B43_TX4_PHY_ANT
) | ant
;
2168 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
, tmp
);
2170 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
);
2171 tmp
= (tmp
& ~B43_TX4_PHY_ANT
) | ant
;
2172 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
, tmp
);
2173 /* For Probe Resposes */
2174 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
);
2175 tmp
= (tmp
& ~B43_TX4_PHY_ANT
) | ant
;
2176 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
, tmp
);
2179 /* This is the opposite of b43_chip_init() */
2180 static void b43_chip_exit(struct b43_wldev
*dev
)
2182 b43_radio_turn_off(dev
);
2183 if (!modparam_noleds
)
2185 b43_gpio_cleanup(dev
);
2186 /* firmware is released later */
2189 /* Initialize the chip
2190 * http://bcm-specs.sipsolutions.net/ChipInit
2192 static int b43_chip_init(struct b43_wldev
*dev
)
2194 struct b43_phy
*phy
= &dev
->phy
;
2199 b43_write32(dev
, B43_MMIO_MACCTL
,
2200 B43_MACCTL_PSM_JMP0
| B43_MACCTL_IHR_ENABLED
);
2202 err
= b43_request_firmware(dev
);
2205 err
= b43_upload_microcode(dev
);
2207 goto out
; /* firmware is released later */
2209 err
= b43_gpio_init(dev
);
2211 goto out
; /* firmware is released later */
2212 err
= b43_upload_initvals(dev
);
2214 goto err_gpio_cleanup
;
2215 b43_radio_turn_on(dev
);
2216 dev
->radio_hw_enable
= b43_is_hw_radio_enabled(dev
);
2217 b43dbg(dev
->wl
, "Radio %s by hardware\n",
2218 (dev
->radio_hw_enable
== 0) ? "disabled" : "enabled");
2220 b43_write16(dev
, 0x03E6, 0x0000);
2221 err
= b43_phy_init(dev
);
2225 /* Select initial Interference Mitigation. */
2226 tmp
= phy
->interfmode
;
2227 phy
->interfmode
= B43_INTERFMODE_NONE
;
2228 b43_radio_set_interference_mitigation(dev
, tmp
);
2230 b43_set_rx_antenna(dev
, B43_ANTENNA_DEFAULT
);
2231 b43_mgmtframe_txantenna(dev
, B43_ANTENNA_DEFAULT
);
2233 if (phy
->type
== B43_PHYTYPE_B
) {
2234 value16
= b43_read16(dev
, 0x005E);
2236 b43_write16(dev
, 0x005E, value16
);
2238 b43_write32(dev
, 0x0100, 0x01000000);
2239 if (dev
->dev
->id
.revision
< 5)
2240 b43_write32(dev
, 0x010C, 0x01000000);
2242 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2243 & ~B43_MACCTL_INFRA
);
2244 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2245 | B43_MACCTL_INFRA
);
2246 /* Let beacons come through */
2247 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2248 | B43_MACCTL_BEACPROMISC
);
2250 if (b43_using_pio(dev
)) {
2251 b43_write32(dev
, 0x0210, 0x00000100);
2252 b43_write32(dev
, 0x0230, 0x00000100);
2253 b43_write32(dev
, 0x0250, 0x00000100);
2254 b43_write32(dev
, 0x0270, 0x00000100);
2255 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0034, 0x0000);
2258 /* Probe Response Timeout value */
2259 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2260 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0074, 0x0000);
2262 /* Initially set the wireless operation mode. */
2263 b43_adjust_opmode(dev
);
2265 if (dev
->dev
->id
.revision
< 3) {
2266 b43_write16(dev
, 0x060E, 0x0000);
2267 b43_write16(dev
, 0x0610, 0x8000);
2268 b43_write16(dev
, 0x0604, 0x0000);
2269 b43_write16(dev
, 0x0606, 0x0200);
2271 b43_write32(dev
, 0x0188, 0x80000000);
2272 b43_write32(dev
, 0x018C, 0x02000000);
2274 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, 0x00004000);
2275 b43_write32(dev
, B43_MMIO_DMA0_IRQ_MASK
, 0x0001DC00);
2276 b43_write32(dev
, B43_MMIO_DMA1_IRQ_MASK
, 0x0000DC00);
2277 b43_write32(dev
, B43_MMIO_DMA2_IRQ_MASK
, 0x0000DC00);
2278 b43_write32(dev
, B43_MMIO_DMA3_IRQ_MASK
, 0x0001DC00);
2279 b43_write32(dev
, B43_MMIO_DMA4_IRQ_MASK
, 0x0000DC00);
2280 b43_write32(dev
, B43_MMIO_DMA5_IRQ_MASK
, 0x0000DC00);
2282 value32
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
2283 value32
|= 0x00100000;
2284 ssb_write32(dev
->dev
, SSB_TMSLOW
, value32
);
2286 b43_write16(dev
, B43_MMIO_POWERUP_DELAY
,
2287 dev
->dev
->bus
->chipco
.fast_pwrup_delay
);
2290 b43dbg(dev
->wl
, "Chip initialized\n");
2295 b43_radio_turn_off(dev
);
2297 b43_gpio_cleanup(dev
);
2301 static void b43_periodic_every120sec(struct b43_wldev
*dev
)
2303 struct b43_phy
*phy
= &dev
->phy
;
2305 if (phy
->type
!= B43_PHYTYPE_G
|| phy
->rev
< 2)
2308 b43_mac_suspend(dev
);
2309 b43_lo_g_measure(dev
);
2310 b43_mac_enable(dev
);
2311 if (b43_has_hardware_pctl(phy
))
2312 b43_lo_g_ctl_mark_all_unused(dev
);
2315 static void b43_periodic_every60sec(struct b43_wldev
*dev
)
2317 struct b43_phy
*phy
= &dev
->phy
;
2319 if (!b43_has_hardware_pctl(phy
))
2320 b43_lo_g_ctl_mark_all_unused(dev
);
2321 if (dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& B43_BFL_RSSI
) {
2322 b43_mac_suspend(dev
);
2323 b43_calc_nrssi_slope(dev
);
2324 if ((phy
->radio_ver
== 0x2050) && (phy
->radio_rev
== 8)) {
2325 u8 old_chan
= phy
->channel
;
2327 /* VCO Calibration */
2329 b43_radio_selectchannel(dev
, 1, 0);
2331 b43_radio_selectchannel(dev
, 13, 0);
2332 b43_radio_selectchannel(dev
, old_chan
, 0);
2334 b43_mac_enable(dev
);
2338 static void b43_periodic_every30sec(struct b43_wldev
*dev
)
2340 /* Update device statistics. */
2341 b43_calculate_link_quality(dev
);
2344 static void b43_periodic_every15sec(struct b43_wldev
*dev
)
2346 struct b43_phy
*phy
= &dev
->phy
;
2348 if (phy
->type
== B43_PHYTYPE_G
) {
2349 //TODO: update_aci_moving_average
2350 if (phy
->aci_enable
&& phy
->aci_wlan_automatic
) {
2351 b43_mac_suspend(dev
);
2352 if (!phy
->aci_enable
&& 1 /*TODO: not scanning? */ ) {
2353 if (0 /*TODO: bunch of conditions */ ) {
2354 b43_radio_set_interference_mitigation
2355 (dev
, B43_INTERFMODE_MANUALWLAN
);
2357 } else if (1 /*TODO*/) {
2359 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2360 b43_radio_set_interference_mitigation(dev,
2361 B43_INTERFMODE_NONE);
2365 b43_mac_enable(dev
);
2366 } else if (phy
->interfmode
== B43_INTERFMODE_NONWLAN
&&
2368 //TODO: implement rev1 workaround
2371 b43_phy_xmitpower(dev
); //FIXME: unless scanning?
2372 //TODO for APHY (temperature?)
2375 static void b43_periodic_every1sec(struct b43_wldev
*dev
)
2377 int radio_hw_enable
;
2379 /* check if radio hardware enabled status changed */
2380 radio_hw_enable
= b43_is_hw_radio_enabled(dev
);
2381 if (unlikely(dev
->radio_hw_enable
!= radio_hw_enable
)) {
2382 dev
->radio_hw_enable
= radio_hw_enable
;
2383 b43dbg(dev
->wl
, "Radio hardware status changed to %s\n",
2384 (radio_hw_enable
== 0) ? "disabled" : "enabled");
2385 b43_leds_update(dev
, 0);
2389 static void do_periodic_work(struct b43_wldev
*dev
)
2393 state
= dev
->periodic_state
;
2394 if (state
% 120 == 0)
2395 b43_periodic_every120sec(dev
);
2396 if (state
% 60 == 0)
2397 b43_periodic_every60sec(dev
);
2398 if (state
% 30 == 0)
2399 b43_periodic_every30sec(dev
);
2400 if (state
% 15 == 0)
2401 b43_periodic_every15sec(dev
);
2402 b43_periodic_every1sec(dev
);
2405 /* Estimate a "Badness" value based on the periodic work
2406 * state-machine state. "Badness" is worse (bigger), if the
2407 * periodic work will take longer.
2409 static int estimate_periodic_work_badness(unsigned int state
)
2413 if (state
% 120 == 0) /* every 120 sec */
2415 if (state
% 60 == 0) /* every 60 sec */
2417 if (state
% 30 == 0) /* every 30 sec */
2419 if (state
% 15 == 0) /* every 15 sec */
2422 #define BADNESS_LIMIT 4
2426 static void b43_periodic_work_handler(struct work_struct
*work
)
2428 struct b43_wldev
*dev
=
2429 container_of(work
, struct b43_wldev
, periodic_work
.work
);
2430 unsigned long flags
, delay
;
2434 mutex_lock(&dev
->wl
->mutex
);
2436 if (unlikely(b43_status(dev
) != B43_STAT_STARTED
))
2438 if (b43_debug(dev
, B43_DBG_PWORK_STOP
))
2441 badness
= estimate_periodic_work_badness(dev
->periodic_state
);
2442 if (badness
> BADNESS_LIMIT
) {
2443 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
2444 /* Suspend TX as we don't want to transmit packets while
2445 * we recalibrate the hardware. */
2446 b43_tx_suspend(dev
);
2447 savedirqs
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
2448 /* Periodic work will take a long time, so we want it to
2449 * be preemtible and release the spinlock. */
2450 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
2451 b43_synchronize_irq(dev
);
2453 do_periodic_work(dev
);
2455 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
2456 b43_interrupt_enable(dev
, savedirqs
);
2459 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
2461 /* Take the global driver lock. This will lock any operation. */
2462 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
2464 do_periodic_work(dev
);
2467 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
2469 dev
->periodic_state
++;
2471 if (b43_debug(dev
, B43_DBG_PWORK_FAST
))
2472 delay
= msecs_to_jiffies(50);
2474 delay
= round_jiffies(HZ
);
2475 queue_delayed_work(dev
->wl
->hw
->workqueue
, &dev
->periodic_work
, delay
);
2477 mutex_unlock(&dev
->wl
->mutex
);
2480 static void b43_periodic_tasks_setup(struct b43_wldev
*dev
)
2482 struct delayed_work
*work
= &dev
->periodic_work
;
2484 dev
->periodic_state
= 0;
2485 INIT_DELAYED_WORK(work
, b43_periodic_work_handler
);
2486 queue_delayed_work(dev
->wl
->hw
->workqueue
, work
, 0);
2489 /* Validate access to the chip (SHM) */
2490 static int b43_validate_chipaccess(struct b43_wldev
*dev
)
2495 shm_backup
= b43_shm_read32(dev
, B43_SHM_SHARED
, 0);
2496 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0xAA5555AA);
2497 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0xAA5555AA)
2499 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0x55AAAA55);
2500 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0x55AAAA55)
2502 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, shm_backup
);
2504 value
= b43_read32(dev
, B43_MMIO_MACCTL
);
2505 if ((value
| B43_MACCTL_GMODE
) !=
2506 (B43_MACCTL_GMODE
| B43_MACCTL_IHR_ENABLED
))
2509 value
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2515 b43err(dev
->wl
, "Failed to validate the chipaccess\n");
2519 static void b43_security_init(struct b43_wldev
*dev
)
2521 dev
->max_nr_keys
= (dev
->dev
->id
.revision
>= 5) ? 58 : 20;
2522 B43_WARN_ON(dev
->max_nr_keys
> ARRAY_SIZE(dev
->key
));
2523 dev
->ktp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_KTP
);
2524 /* KTP is a word address, but we address SHM bytewise.
2525 * So multiply by two.
2528 if (dev
->dev
->id
.revision
>= 5) {
2529 /* Number of RCMTA address slots */
2530 b43_write16(dev
, B43_MMIO_RCMTA_COUNT
, dev
->max_nr_keys
- 8);
2532 b43_clear_keys(dev
);
2535 static int b43_rng_read(struct hwrng
*rng
, u32
* data
)
2537 struct b43_wl
*wl
= (struct b43_wl
*)rng
->priv
;
2538 unsigned long flags
;
2540 /* Don't take wl->mutex here, as it could deadlock with
2541 * hwrng internal locking. It's not needed to take
2542 * wl->mutex here, anyway. */
2544 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2545 *data
= b43_read16(wl
->current_dev
, B43_MMIO_RNG
);
2546 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2548 return (sizeof(u16
));
2551 static void b43_rng_exit(struct b43_wl
*wl
)
2553 if (wl
->rng_initialized
)
2554 hwrng_unregister(&wl
->rng
);
2557 static int b43_rng_init(struct b43_wl
*wl
)
2561 snprintf(wl
->rng_name
, ARRAY_SIZE(wl
->rng_name
),
2562 "%s_%s", KBUILD_MODNAME
, wiphy_name(wl
->hw
->wiphy
));
2563 wl
->rng
.name
= wl
->rng_name
;
2564 wl
->rng
.data_read
= b43_rng_read
;
2565 wl
->rng
.priv
= (unsigned long)wl
;
2566 wl
->rng_initialized
= 1;
2567 err
= hwrng_register(&wl
->rng
);
2569 wl
->rng_initialized
= 0;
2570 b43err(wl
, "Failed to register the random "
2571 "number generator (%d)\n", err
);
2577 static int b43_tx(struct ieee80211_hw
*hw
,
2578 struct sk_buff
*skb
, struct ieee80211_tx_control
*ctl
)
2580 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2581 struct b43_wldev
*dev
= wl
->current_dev
;
2583 unsigned long flags
;
2587 if (unlikely(b43_status(dev
) < B43_STAT_STARTED
))
2589 /* DMA-TX is done without a global lock. */
2590 if (b43_using_pio(dev
)) {
2591 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2592 err
= b43_pio_tx(dev
, skb
, ctl
);
2593 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2595 err
= b43_dma_tx(dev
, skb
, ctl
);
2598 return NETDEV_TX_BUSY
;
2599 return NETDEV_TX_OK
;
2602 static int b43_conf_tx(struct ieee80211_hw
*hw
,
2604 const struct ieee80211_tx_queue_params
*params
)
2609 static int b43_get_tx_stats(struct ieee80211_hw
*hw
,
2610 struct ieee80211_tx_queue_stats
*stats
)
2612 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2613 struct b43_wldev
*dev
= wl
->current_dev
;
2614 unsigned long flags
;
2619 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2620 if (likely(b43_status(dev
) >= B43_STAT_STARTED
)) {
2621 if (b43_using_pio(dev
))
2622 b43_pio_get_tx_stats(dev
, stats
);
2624 b43_dma_get_tx_stats(dev
, stats
);
2627 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2632 static int b43_get_stats(struct ieee80211_hw
*hw
,
2633 struct ieee80211_low_level_stats
*stats
)
2635 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2636 unsigned long flags
;
2638 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2639 memcpy(stats
, &wl
->ieee_stats
, sizeof(*stats
));
2640 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2645 static const char *phymode_to_string(unsigned int phymode
)
2660 static int find_wldev_for_phymode(struct b43_wl
*wl
,
2661 unsigned int phymode
,
2662 struct b43_wldev
**dev
, bool * gmode
)
2664 struct b43_wldev
*d
;
2666 list_for_each_entry(d
, &wl
->devlist
, list
) {
2667 if (d
->phy
.possible_phymodes
& phymode
) {
2668 /* Ok, this device supports the PHY-mode.
2669 * Now figure out how the gmode bit has to be
2670 * set to support it. */
2671 if (phymode
== B43_PHYMODE_A
)
2684 static void b43_put_phy_into_reset(struct b43_wldev
*dev
)
2686 struct ssb_device
*sdev
= dev
->dev
;
2689 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
2690 tmslow
&= ~B43_TMSLOW_GMODE
;
2691 tmslow
|= B43_TMSLOW_PHYRESET
;
2692 tmslow
|= SSB_TMSLOW_FGC
;
2693 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
2696 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
2697 tmslow
&= ~SSB_TMSLOW_FGC
;
2698 tmslow
|= B43_TMSLOW_PHYRESET
;
2699 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
2703 /* Expects wl->mutex locked */
2704 static int b43_switch_phymode(struct b43_wl
*wl
, unsigned int new_mode
)
2706 struct b43_wldev
*up_dev
;
2707 struct b43_wldev
*down_dev
;
2712 err
= find_wldev_for_phymode(wl
, new_mode
, &up_dev
, &gmode
);
2714 b43err(wl
, "Could not find a device for %s-PHY mode\n",
2715 phymode_to_string(new_mode
));
2718 if ((up_dev
== wl
->current_dev
) &&
2719 (!!wl
->current_dev
->phy
.gmode
== !!gmode
)) {
2720 /* This device is already running. */
2723 b43dbg(wl
, "Reconfiguring PHYmode to %s-PHY\n",
2724 phymode_to_string(new_mode
));
2725 down_dev
= wl
->current_dev
;
2727 prev_status
= b43_status(down_dev
);
2728 /* Shutdown the currently running core. */
2729 if (prev_status
>= B43_STAT_STARTED
)
2730 b43_wireless_core_stop(down_dev
);
2731 if (prev_status
>= B43_STAT_INITIALIZED
)
2732 b43_wireless_core_exit(down_dev
);
2734 if (down_dev
!= up_dev
) {
2735 /* We switch to a different core, so we put PHY into
2736 * RESET on the old core. */
2737 b43_put_phy_into_reset(down_dev
);
2740 /* Now start the new core. */
2741 up_dev
->phy
.gmode
= gmode
;
2742 if (prev_status
>= B43_STAT_INITIALIZED
) {
2743 err
= b43_wireless_core_init(up_dev
);
2745 b43err(wl
, "Fatal: Could not initialize device for "
2746 "newly selected %s-PHY mode\n",
2747 phymode_to_string(new_mode
));
2751 if (prev_status
>= B43_STAT_STARTED
) {
2752 err
= b43_wireless_core_start(up_dev
);
2754 b43err(wl
, "Fatal: Coult not start device for "
2755 "newly selected %s-PHY mode\n",
2756 phymode_to_string(new_mode
));
2757 b43_wireless_core_exit(up_dev
);
2761 B43_WARN_ON(b43_status(up_dev
) != prev_status
);
2763 wl
->current_dev
= up_dev
;
2767 /* Whoops, failed to init the new core. No core is operating now. */
2768 wl
->current_dev
= NULL
;
2772 static int b43_antenna_from_ieee80211(u8 antenna
)
2775 case 0: /* default/diversity */
2776 return B43_ANTENNA_DEFAULT
;
2777 case 1: /* Antenna 0 */
2778 return B43_ANTENNA0
;
2779 case 2: /* Antenna 1 */
2780 return B43_ANTENNA1
;
2782 return B43_ANTENNA_DEFAULT
;
2786 static int b43_dev_config(struct ieee80211_hw
*hw
, struct ieee80211_conf
*conf
)
2788 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2789 struct b43_wldev
*dev
;
2790 struct b43_phy
*phy
;
2791 unsigned long flags
;
2792 unsigned int new_phymode
= 0xFFFF;
2798 antenna_tx
= b43_antenna_from_ieee80211(conf
->antenna_sel_tx
);
2799 antenna_rx
= b43_antenna_from_ieee80211(conf
->antenna_sel_rx
);
2801 mutex_lock(&wl
->mutex
);
2803 /* Switch the PHY mode (if necessary). */
2804 switch (conf
->phymode
) {
2805 case MODE_IEEE80211A
:
2806 new_phymode
= B43_PHYMODE_A
;
2808 case MODE_IEEE80211B
:
2809 new_phymode
= B43_PHYMODE_B
;
2811 case MODE_IEEE80211G
:
2812 new_phymode
= B43_PHYMODE_G
;
2817 err
= b43_switch_phymode(wl
, new_phymode
);
2819 goto out_unlock_mutex
;
2820 dev
= wl
->current_dev
;
2823 /* Disable IRQs while reconfiguring the device.
2824 * This makes it possible to drop the spinlock throughout
2825 * the reconfiguration process. */
2826 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2827 if (b43_status(dev
) < B43_STAT_STARTED
) {
2828 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2829 goto out_unlock_mutex
;
2831 savedirqs
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
2832 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2833 b43_synchronize_irq(dev
);
2835 /* Switch to the requested channel.
2836 * The firmware takes care of races with the TX handler. */
2837 if (conf
->channel_val
!= phy
->channel
)
2838 b43_radio_selectchannel(dev
, conf
->channel_val
, 0);
2840 /* Enable/Disable ShortSlot timing. */
2841 if ((!!(conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
)) !=
2843 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
2844 if (conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
)
2845 b43_short_slot_timing_enable(dev
);
2847 b43_short_slot_timing_disable(dev
);
2850 /* Adjust the desired TX power level. */
2851 if (conf
->power_level
!= 0) {
2852 if (conf
->power_level
!= phy
->power_level
) {
2853 phy
->power_level
= conf
->power_level
;
2854 b43_phy_xmitpower(dev
);
2858 /* Antennas for RX and management frame TX. */
2859 b43_mgmtframe_txantenna(dev
, antenna_tx
);
2860 b43_set_rx_antenna(dev
, antenna_rx
);
2862 /* Update templates for AP mode. */
2863 if (b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
))
2864 b43_set_beacon_int(dev
, conf
->beacon_int
);
2866 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2867 b43_interrupt_enable(dev
, savedirqs
);
2869 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2871 mutex_unlock(&wl
->mutex
);
2876 static int b43_dev_set_key(struct ieee80211_hw
*hw
,
2877 set_key_cmd cmd
, const u8
*local_addr
,
2878 const u8
*addr
, struct ieee80211_key_conf
*key
)
2880 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2881 struct b43_wldev
*dev
= wl
->current_dev
;
2882 unsigned long flags
;
2887 if (modparam_nohwcrypt
)
2888 return -ENOSPC
; /* User disabled HW-crypto */
2894 algorithm
= B43_SEC_ALGO_NONE
;
2897 if (key
->keylen
== 5)
2898 algorithm
= B43_SEC_ALGO_WEP40
;
2900 algorithm
= B43_SEC_ALGO_WEP104
;
2903 algorithm
= B43_SEC_ALGO_TKIP
;
2906 algorithm
= B43_SEC_ALGO_AES
;
2913 index
= (u8
) (key
->keyidx
);
2917 mutex_lock(&wl
->mutex
);
2918 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2920 if (b43_status(dev
) < B43_STAT_INITIALIZED
) {
2927 if (algorithm
== B43_SEC_ALGO_TKIP
) {
2928 /* FIXME: No TKIP hardware encryption for now. */
2933 if (is_broadcast_ether_addr(addr
)) {
2934 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2935 err
= b43_key_write(dev
, index
, algorithm
,
2936 key
->key
, key
->keylen
, NULL
, key
);
2939 * either pairwise key or address is 00:00:00:00:00:00
2940 * for transmit-only keys
2942 err
= b43_key_write(dev
, -1, algorithm
,
2943 key
->key
, key
->keylen
, addr
, key
);
2948 if (algorithm
== B43_SEC_ALGO_WEP40
||
2949 algorithm
== B43_SEC_ALGO_WEP104
) {
2950 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_USEDEFKEYS
);
2953 b43_hf_read(dev
) & ~B43_HF_USEDEFKEYS
);
2955 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
2958 err
= b43_key_clear(dev
, key
->hw_key_idx
);
2967 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2968 mutex_unlock(&wl
->mutex
);
2971 b43dbg(wl
, "%s hardware based encryption for keyidx: %d, "
2972 "mac: " MAC_FMT
"\n",
2973 cmd
== SET_KEY
? "Using" : "Disabling", key
->keyidx
,
2979 static void b43_set_multicast_list(struct ieee80211_hw
*hw
,
2980 unsigned short netflags
, int mc_count
)
2982 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2983 struct b43_wldev
*dev
= wl
->current_dev
;
2984 unsigned long flags
;
2988 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2989 if (wl
->promisc
!= !!(netflags
& IFF_PROMISC
)) {
2990 wl
->promisc
= !!(netflags
& IFF_PROMISC
);
2991 if (b43_status(dev
) >= B43_STAT_INITIALIZED
)
2992 b43_adjust_opmode(dev
);
2994 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2997 static int b43_config_interface(struct ieee80211_hw
*hw
,
2998 int if_id
, struct ieee80211_if_conf
*conf
)
3000 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3001 struct b43_wldev
*dev
= wl
->current_dev
;
3002 unsigned long flags
;
3006 mutex_lock(&wl
->mutex
);
3007 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3008 if (conf
->type
!= IEEE80211_IF_TYPE_MNTR
) {
3009 B43_WARN_ON(wl
->if_id
!= if_id
);
3011 memcpy(wl
->bssid
, conf
->bssid
, ETH_ALEN
);
3013 memset(wl
->bssid
, 0, ETH_ALEN
);
3014 if (b43_status(dev
) >= B43_STAT_INITIALIZED
) {
3015 if (b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
)) {
3016 B43_WARN_ON(conf
->type
!= IEEE80211_IF_TYPE_AP
);
3017 b43_set_ssid(dev
, conf
->ssid
, conf
->ssid_len
);
3019 b43_refresh_templates(dev
, conf
->beacon
);
3021 b43_write_mac_bssid_templates(dev
);
3024 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3025 mutex_unlock(&wl
->mutex
);
3030 /* Locking: wl->mutex */
3031 static void b43_wireless_core_stop(struct b43_wldev
*dev
)
3033 struct b43_wl
*wl
= dev
->wl
;
3034 unsigned long flags
;
3036 if (b43_status(dev
) < B43_STAT_STARTED
)
3038 b43_set_status(dev
, B43_STAT_INITIALIZED
);
3040 mutex_unlock(&wl
->mutex
);
3041 /* Must unlock as it would otherwise deadlock. No races here.
3042 * Cancel the possibly running self-rearming periodic work. */
3043 cancel_delayed_work_sync(&dev
->periodic_work
);
3044 mutex_lock(&wl
->mutex
);
3046 ieee80211_stop_queues(wl
->hw
); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3048 /* Disable and sync interrupts. */
3049 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3050 dev
->irq_savedstate
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
3051 b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
); /* flush */
3052 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3053 b43_synchronize_irq(dev
);
3055 b43_mac_suspend(dev
);
3056 free_irq(dev
->dev
->irq
, dev
);
3057 b43dbg(wl
, "Wireless interface stopped\n");
3060 /* Locking: wl->mutex */
3061 static int b43_wireless_core_start(struct b43_wldev
*dev
)
3065 B43_WARN_ON(b43_status(dev
) != B43_STAT_INITIALIZED
);
3067 drain_txstatus_queue(dev
);
3068 err
= request_irq(dev
->dev
->irq
, b43_interrupt_handler
,
3069 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
3071 b43err(dev
->wl
, "Cannot request IRQ-%d\n", dev
->dev
->irq
);
3075 /* We are ready to run. */
3076 b43_set_status(dev
, B43_STAT_STARTED
);
3078 /* Start data flow (TX/RX). */
3079 b43_mac_enable(dev
);
3080 b43_interrupt_enable(dev
, dev
->irq_savedstate
);
3081 ieee80211_start_queues(dev
->wl
->hw
);
3083 /* Start maintainance work */
3084 b43_periodic_tasks_setup(dev
);
3086 b43dbg(dev
->wl
, "Wireless interface started\n");
3091 /* Get PHY and RADIO versioning numbers */
3092 static int b43_phy_versioning(struct b43_wldev
*dev
)
3094 struct b43_phy
*phy
= &dev
->phy
;
3102 int unsupported
= 0;
3104 /* Get PHY versioning */
3105 tmp
= b43_read16(dev
, B43_MMIO_PHY_VER
);
3106 analog_type
= (tmp
& B43_PHYVER_ANALOG
) >> B43_PHYVER_ANALOG_SHIFT
;
3107 phy_type
= (tmp
& B43_PHYVER_TYPE
) >> B43_PHYVER_TYPE_SHIFT
;
3108 phy_rev
= (tmp
& B43_PHYVER_VERSION
);
3115 if (phy_rev
!= 2 && phy_rev
!= 4 && phy_rev
!= 6
3127 b43err(dev
->wl
, "FOUND UNSUPPORTED PHY "
3128 "(Analog %u, Type %u, Revision %u)\n",
3129 analog_type
, phy_type
, phy_rev
);
3132 b43dbg(dev
->wl
, "Found PHY: Analog %u, Type %u, Revision %u\n",
3133 analog_type
, phy_type
, phy_rev
);
3135 /* Get RADIO versioning */
3136 if (dev
->dev
->bus
->chip_id
== 0x4317) {
3137 if (dev
->dev
->bus
->chip_rev
== 0)
3139 else if (dev
->dev
->bus
->chip_rev
== 1)
3144 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, B43_RADIOCTL_ID
);
3145 tmp
= b43_read16(dev
, B43_MMIO_RADIO_DATA_HIGH
);
3147 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, B43_RADIOCTL_ID
);
3148 tmp
|= b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
3150 radio_manuf
= (tmp
& 0x00000FFF);
3151 radio_ver
= (tmp
& 0x0FFFF000) >> 12;
3152 radio_rev
= (tmp
& 0xF0000000) >> 28;
3155 if (radio_ver
!= 0x2060)
3159 if (radio_manuf
!= 0x17F)
3163 if ((radio_ver
& 0xFFF0) != 0x2050)
3167 if (radio_ver
!= 0x2050)
3174 b43err(dev
->wl
, "FOUND UNSUPPORTED RADIO "
3175 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3176 radio_manuf
, radio_ver
, radio_rev
);
3179 b43dbg(dev
->wl
, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3180 radio_manuf
, radio_ver
, radio_rev
);
3182 phy
->radio_manuf
= radio_manuf
;
3183 phy
->radio_ver
= radio_ver
;
3184 phy
->radio_rev
= radio_rev
;
3186 phy
->analog
= analog_type
;
3187 phy
->type
= phy_type
;
3193 static void setup_struct_phy_for_init(struct b43_wldev
*dev
,
3194 struct b43_phy
*phy
)
3196 struct b43_txpower_lo_control
*lo
;
3199 memset(phy
->minlowsig
, 0xFF, sizeof(phy
->minlowsig
));
3200 memset(phy
->minlowsigpos
, 0, sizeof(phy
->minlowsigpos
));
3205 phy
->aci_enable
= 0;
3206 phy
->aci_wlan_automatic
= 0;
3207 phy
->aci_hw_rssi
= 0;
3209 lo
= phy
->lo_control
;
3211 memset(lo
, 0, sizeof(*(phy
->lo_control
)));
3215 phy
->max_lb_gain
= 0;
3216 phy
->trsw_rx_gain
= 0;
3217 phy
->txpwr_offset
= 0;
3220 phy
->nrssislope
= 0;
3221 for (i
= 0; i
< ARRAY_SIZE(phy
->nrssi
); i
++)
3222 phy
->nrssi
[i
] = -1000;
3223 for (i
= 0; i
< ARRAY_SIZE(phy
->nrssi_lt
); i
++)
3224 phy
->nrssi_lt
[i
] = i
;
3226 phy
->lofcal
= 0xFFFF;
3227 phy
->initval
= 0xFFFF;
3229 spin_lock_init(&phy
->lock
);
3230 phy
->interfmode
= B43_INTERFMODE_NONE
;
3231 phy
->channel
= 0xFF;
3233 phy
->hardware_power_control
= !!modparam_hwpctl
;
3236 static void setup_struct_wldev_for_init(struct b43_wldev
*dev
)
3239 dev
->reg124_set_0x4
= 0;
3242 memset(&dev
->stats
, 0, sizeof(dev
->stats
));
3244 setup_struct_phy_for_init(dev
, &dev
->phy
);
3246 /* IRQ related flags */
3247 dev
->irq_reason
= 0;
3248 memset(dev
->dma_reason
, 0, sizeof(dev
->dma_reason
));
3249 dev
->irq_savedstate
= B43_IRQ_MASKTEMPLATE
;
3251 dev
->mac_suspended
= 1;
3253 /* Noise calculation context */
3254 memset(&dev
->noisecalc
, 0, sizeof(dev
->noisecalc
));
3257 static void b43_bluetooth_coext_enable(struct b43_wldev
*dev
)
3259 struct ssb_sprom
*sprom
= &dev
->dev
->bus
->sprom
;
3262 if (!(sprom
->r1
.boardflags_lo
& B43_BFL_BTCOEXIST
))
3264 if (dev
->phy
.type
!= B43_PHYTYPE_B
&& !dev
->phy
.gmode
)
3267 hf
= b43_hf_read(dev
);
3268 if (sprom
->r1
.boardflags_lo
& B43_BFL_BTCMOD
)
3269 hf
|= B43_HF_BTCOEXALT
;
3271 hf
|= B43_HF_BTCOEX
;
3272 b43_hf_write(dev
, hf
);
3276 static void b43_bluetooth_coext_disable(struct b43_wldev
*dev
)
3280 static void b43_imcfglo_timeouts_workaround(struct b43_wldev
*dev
)
3282 #ifdef CONFIG_SSB_DRIVER_PCICORE
3283 struct ssb_bus
*bus
= dev
->dev
->bus
;
3286 if (bus
->pcicore
.dev
&&
3287 bus
->pcicore
.dev
->id
.coreid
== SSB_DEV_PCI
&&
3288 bus
->pcicore
.dev
->id
.revision
<= 5) {
3289 /* IMCFGLO timeouts workaround. */
3290 tmp
= ssb_read32(dev
->dev
, SSB_IMCFGLO
);
3291 tmp
&= ~SSB_IMCFGLO_REQTO
;
3292 tmp
&= ~SSB_IMCFGLO_SERTO
;
3293 switch (bus
->bustype
) {
3294 case SSB_BUSTYPE_PCI
:
3295 case SSB_BUSTYPE_PCMCIA
:
3298 case SSB_BUSTYPE_SSB
:
3302 ssb_write32(dev
->dev
, SSB_IMCFGLO
, tmp
);
3304 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3307 /* Shutdown a wireless core */
3308 /* Locking: wl->mutex */
3309 static void b43_wireless_core_exit(struct b43_wldev
*dev
)
3311 struct b43_phy
*phy
= &dev
->phy
;
3313 B43_WARN_ON(b43_status(dev
) > B43_STAT_INITIALIZED
);
3314 if (b43_status(dev
) != B43_STAT_INITIALIZED
)
3316 b43_set_status(dev
, B43_STAT_UNINIT
);
3318 b43_rng_exit(dev
->wl
);
3322 b43_radio_turn_off(dev
);
3323 b43_switch_analog(dev
, 0);
3324 if (phy
->dyn_tssi_tbl
)
3325 kfree(phy
->tssi2dbm
);
3326 kfree(phy
->lo_control
);
3327 phy
->lo_control
= NULL
;
3328 ssb_device_disable(dev
->dev
, 0);
3329 ssb_bus_may_powerdown(dev
->dev
->bus
);
3332 /* Initialize a wireless core */
3333 static int b43_wireless_core_init(struct b43_wldev
*dev
)
3335 struct b43_wl
*wl
= dev
->wl
;
3336 struct ssb_bus
*bus
= dev
->dev
->bus
;
3337 struct ssb_sprom
*sprom
= &bus
->sprom
;
3338 struct b43_phy
*phy
= &dev
->phy
;
3342 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
3344 err
= ssb_bus_powerup(bus
, 0);
3347 if (!ssb_device_is_enabled(dev
->dev
)) {
3348 tmp
= phy
->gmode
? B43_TMSLOW_GMODE
: 0;
3349 b43_wireless_core_reset(dev
, tmp
);
3352 if ((phy
->type
== B43_PHYTYPE_B
) || (phy
->type
== B43_PHYTYPE_G
)) {
3354 kzalloc(sizeof(*(phy
->lo_control
)), GFP_KERNEL
);
3355 if (!phy
->lo_control
) {
3360 setup_struct_wldev_for_init(dev
);
3362 err
= b43_phy_init_tssi2dbm_table(dev
);
3364 goto err_kfree_lo_control
;
3366 /* Enable IRQ routing to this device. */
3367 ssb_pcicore_dev_irqvecs_enable(&bus
->pcicore
, dev
->dev
);
3369 b43_imcfglo_timeouts_workaround(dev
);
3370 b43_bluetooth_coext_disable(dev
);
3371 b43_phy_early_init(dev
);
3372 err
= b43_chip_init(dev
);
3374 goto err_kfree_tssitbl
;
3375 b43_shm_write16(dev
, B43_SHM_SHARED
,
3376 B43_SHM_SH_WLCOREREV
, dev
->dev
->id
.revision
);
3377 hf
= b43_hf_read(dev
);
3378 if (phy
->type
== B43_PHYTYPE_G
) {
3382 if (sprom
->r1
.boardflags_lo
& B43_BFL_PACTRL
)
3383 hf
|= B43_HF_OFDMPABOOST
;
3384 } else if (phy
->type
== B43_PHYTYPE_B
) {
3386 if (phy
->rev
>= 2 && phy
->radio_ver
== 0x2050)
3389 b43_hf_write(dev
, hf
);
3391 /* Short/Long Retry Limit.
3392 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
3393 * the chip-internal counter.
3395 tmp
= limit_value(modparam_short_retry
, 0, 0xF);
3396 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_SRLIMIT
, tmp
);
3397 tmp
= limit_value(modparam_long_retry
, 0, 0xF);
3398 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_LRLIMIT
, tmp
);
3400 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_SFFBLIM
, 3);
3401 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_LFFBLIM
, 2);
3403 /* Disable sending probe responses from firmware.
3404 * Setting the MaxTime to one usec will always trigger
3405 * a timeout, so we never send any probe resp.
3406 * A timeout of zero is infinite. */
3407 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRMAXTIME
, 1);
3409 b43_rate_memory_init(dev
);
3411 /* Minimum Contention Window */
3412 if (phy
->type
== B43_PHYTYPE_B
) {
3413 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0x1F);
3415 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0xF);
3417 /* Maximum Contention Window */
3418 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MAXCONT
, 0x3FF);
3421 if (b43_using_pio(dev
)) {
3422 err
= b43_pio_init(dev
);
3424 err
= b43_dma_init(dev
);
3428 } while (err
== -EAGAIN
);
3434 b43_write16(dev
, 0x0612, 0x0050);
3435 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0416, 0x0050);
3436 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0414, 0x01F4);
3439 b43_bluetooth_coext_enable(dev
);
3441 ssb_bus_powerup(bus
, 1); /* Enable dynamic PCTL */
3442 memset(wl
->bssid
, 0, ETH_ALEN
);
3443 b43_upload_card_macaddress(dev
, NULL
);
3444 b43_security_init(dev
);
3447 b43_set_status(dev
, B43_STAT_INITIALIZED
);
3455 if (phy
->dyn_tssi_tbl
)
3456 kfree(phy
->tssi2dbm
);
3457 err_kfree_lo_control
:
3458 kfree(phy
->lo_control
);
3459 phy
->lo_control
= NULL
;
3461 ssb_bus_may_powerdown(bus
);
3462 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
3466 static int b43_add_interface(struct ieee80211_hw
*hw
,
3467 struct ieee80211_if_init_conf
*conf
)
3469 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3470 struct b43_wldev
*dev
;
3471 unsigned long flags
;
3472 int err
= -EOPNOTSUPP
;
3475 mutex_lock(&wl
->mutex
);
3476 if ((conf
->type
!= IEEE80211_IF_TYPE_MNTR
) && wl
->operating
)
3477 goto out_mutex_unlock
;
3479 b43dbg(wl
, "Adding Interface type %d\n", conf
->type
);
3481 dev
= wl
->current_dev
;
3482 if (b43_status(dev
) < B43_STAT_INITIALIZED
) {
3483 err
= b43_wireless_core_init(dev
);
3485 goto out_mutex_unlock
;
3488 if (b43_status(dev
) < B43_STAT_STARTED
) {
3489 err
= b43_wireless_core_start(dev
);
3492 b43_wireless_core_exit(dev
);
3493 goto out_mutex_unlock
;
3497 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3498 switch (conf
->type
) {
3499 case IEEE80211_IF_TYPE_MNTR
:
3504 wl
->if_id
= conf
->if_id
;
3505 wl
->if_type
= conf
->type
;
3506 b43_upload_card_macaddress(dev
, conf
->mac_addr
);
3508 b43_adjust_opmode(dev
);
3509 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3513 mutex_unlock(&wl
->mutex
);
3518 static void b43_remove_interface(struct ieee80211_hw
*hw
,
3519 struct ieee80211_if_init_conf
*conf
)
3521 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3522 struct b43_wldev
*dev
;
3523 unsigned long flags
;
3525 b43dbg(wl
, "Removing Interface type %d\n", conf
->type
);
3527 mutex_lock(&wl
->mutex
);
3528 if (conf
->type
== IEEE80211_IF_TYPE_MNTR
) {
3530 B43_WARN_ON(wl
->monitor
< 0);
3532 B43_WARN_ON(!wl
->operating
);
3536 dev
= wl
->current_dev
;
3537 if (!wl
->operating
&& wl
->monitor
== 0) {
3538 /* No interface left. */
3539 if (b43_status(dev
) >= B43_STAT_STARTED
)
3540 b43_wireless_core_stop(dev
);
3541 b43_wireless_core_exit(dev
);
3543 /* Just monitor interfaces left. */
3544 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3545 b43_adjust_opmode(dev
);
3547 b43_upload_card_macaddress(dev
, NULL
);
3548 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3550 mutex_unlock(&wl
->mutex
);
3553 static const struct ieee80211_ops b43_hw_ops
= {
3555 .conf_tx
= b43_conf_tx
,
3556 .add_interface
= b43_add_interface
,
3557 .remove_interface
= b43_remove_interface
,
3558 .config
= b43_dev_config
,
3559 .config_interface
= b43_config_interface
,
3560 .set_multicast_list
= b43_set_multicast_list
,
3561 .set_key
= b43_dev_set_key
,
3562 .get_stats
= b43_get_stats
,
3563 .get_tx_stats
= b43_get_tx_stats
,
3566 /* Hard-reset the chip. Do not call this directly.
3567 * Use b43_controller_restart()
3569 static void b43_chip_reset(struct work_struct
*work
)
3571 struct b43_wldev
*dev
=
3572 container_of(work
, struct b43_wldev
, restart_work
);
3573 struct b43_wl
*wl
= dev
->wl
;
3577 mutex_lock(&wl
->mutex
);
3579 prev_status
= b43_status(dev
);
3580 /* Bring the device down... */
3581 if (prev_status
>= B43_STAT_STARTED
)
3582 b43_wireless_core_stop(dev
);
3583 if (prev_status
>= B43_STAT_INITIALIZED
)
3584 b43_wireless_core_exit(dev
);
3586 /* ...and up again. */
3587 if (prev_status
>= B43_STAT_INITIALIZED
) {
3588 err
= b43_wireless_core_init(dev
);
3592 if (prev_status
>= B43_STAT_STARTED
) {
3593 err
= b43_wireless_core_start(dev
);
3595 b43_wireless_core_exit(dev
);
3600 mutex_unlock(&wl
->mutex
);
3602 b43err(wl
, "Controller restart FAILED\n");
3604 b43info(wl
, "Controller restarted\n");
3607 static int b43_setup_modes(struct b43_wldev
*dev
,
3608 int have_aphy
, int have_bphy
, int have_gphy
)
3610 struct ieee80211_hw
*hw
= dev
->wl
->hw
;
3611 struct ieee80211_hw_mode
*mode
;
3612 struct b43_phy
*phy
= &dev
->phy
;
3616 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3619 phy
->possible_phymodes
= 0;
3622 B43_WARN_ON(cnt
>= B43_MAX_PHYHWMODES
);
3623 mode
= &phy
->hwmodes
[cnt
];
3625 mode
->mode
= MODE_IEEE80211A
;
3626 mode
->num_channels
= b43_a_chantable_size
;
3627 mode
->channels
= b43_a_chantable
;
3628 mode
->num_rates
= b43_a_ratetable_size
;
3629 mode
->rates
= b43_a_ratetable
;
3630 err
= ieee80211_register_hwmode(hw
, mode
);
3634 phy
->possible_phymodes
|= B43_PHYMODE_A
;
3639 B43_WARN_ON(cnt
>= B43_MAX_PHYHWMODES
);
3640 mode
= &phy
->hwmodes
[cnt
];
3642 mode
->mode
= MODE_IEEE80211B
;
3643 mode
->num_channels
= b43_bg_chantable_size
;
3644 mode
->channels
= b43_bg_chantable
;
3645 mode
->num_rates
= b43_b_ratetable_size
;
3646 mode
->rates
= b43_b_ratetable
;
3647 err
= ieee80211_register_hwmode(hw
, mode
);
3651 phy
->possible_phymodes
|= B43_PHYMODE_B
;
3656 B43_WARN_ON(cnt
>= B43_MAX_PHYHWMODES
);
3657 mode
= &phy
->hwmodes
[cnt
];
3659 mode
->mode
= MODE_IEEE80211G
;
3660 mode
->num_channels
= b43_bg_chantable_size
;
3661 mode
->channels
= b43_bg_chantable
;
3662 mode
->num_rates
= b43_g_ratetable_size
;
3663 mode
->rates
= b43_g_ratetable
;
3664 err
= ieee80211_register_hwmode(hw
, mode
);
3668 phy
->possible_phymodes
|= B43_PHYMODE_G
;
3678 static void b43_wireless_core_detach(struct b43_wldev
*dev
)
3680 /* We release firmware that late to not be required to re-request
3681 * is all the time when we reinit the core. */
3682 b43_release_firmware(dev
);
3685 static int b43_wireless_core_attach(struct b43_wldev
*dev
)
3687 struct b43_wl
*wl
= dev
->wl
;
3688 struct ssb_bus
*bus
= dev
->dev
->bus
;
3689 struct pci_dev
*pdev
= bus
->host_pci
;
3691 int have_aphy
= 0, have_bphy
= 0, have_gphy
= 0;
3694 /* Do NOT do any device initialization here.
3695 * Do it in wireless_core_init() instead.
3696 * This function is for gathering basic information about the HW, only.
3697 * Also some structs may be set up here. But most likely you want to have
3698 * that in core_init(), too.
3701 err
= ssb_bus_powerup(bus
, 0);
3703 b43err(wl
, "Bus powerup failed\n");
3706 /* Get the PHY type. */
3707 if (dev
->dev
->id
.revision
>= 5) {
3710 tmshigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
3711 have_aphy
= !!(tmshigh
& B43_TMSHIGH_APHY
);
3712 have_gphy
= !!(tmshigh
& B43_TMSHIGH_GPHY
);
3713 if (!have_aphy
&& !have_gphy
)
3715 } else if (dev
->dev
->id
.revision
== 4) {
3721 /* Initialize LEDs structs. */
3722 err
= b43_leds_init(dev
);
3726 dev
->phy
.gmode
= (have_gphy
|| have_bphy
);
3727 tmp
= dev
->phy
.gmode
? B43_TMSLOW_GMODE
: 0;
3728 b43_wireless_core_reset(dev
, tmp
);
3730 err
= b43_phy_versioning(dev
);
3733 /* Check if this device supports multiband. */
3735 (pdev
->device
!= 0x4312 &&
3736 pdev
->device
!= 0x4319 && pdev
->device
!= 0x4324)) {
3737 /* No multiband support. */
3741 switch (dev
->phy
.type
) {
3755 dev
->phy
.gmode
= (have_gphy
|| have_bphy
);
3756 tmp
= dev
->phy
.gmode
? B43_TMSLOW_GMODE
: 0;
3757 b43_wireless_core_reset(dev
, tmp
);
3759 err
= b43_validate_chipaccess(dev
);
3762 err
= b43_setup_modes(dev
, have_aphy
, have_bphy
, have_gphy
);
3766 /* Now set some default "current_dev" */
3767 if (!wl
->current_dev
)
3768 wl
->current_dev
= dev
;
3769 INIT_WORK(&dev
->restart_work
, b43_chip_reset
);
3771 b43_radio_turn_off(dev
);
3772 b43_switch_analog(dev
, 0);
3773 ssb_device_disable(dev
->dev
, 0);
3774 ssb_bus_may_powerdown(bus
);
3782 ssb_bus_may_powerdown(bus
);
3786 static void b43_one_core_detach(struct ssb_device
*dev
)
3788 struct b43_wldev
*wldev
;
3791 wldev
= ssb_get_drvdata(dev
);
3793 cancel_work_sync(&wldev
->restart_work
);
3794 b43_debugfs_remove_device(wldev
);
3795 b43_wireless_core_detach(wldev
);
3796 list_del(&wldev
->list
);
3798 ssb_set_drvdata(dev
, NULL
);
3802 static int b43_one_core_attach(struct ssb_device
*dev
, struct b43_wl
*wl
)
3804 struct b43_wldev
*wldev
;
3805 struct pci_dev
*pdev
;
3808 if (!list_empty(&wl
->devlist
)) {
3809 /* We are not the first core on this chip. */
3810 pdev
= dev
->bus
->host_pci
;
3811 /* Only special chips support more than one wireless
3812 * core, although some of the other chips have more than
3813 * one wireless core as well. Check for this and
3817 ((pdev
->device
!= 0x4321) &&
3818 (pdev
->device
!= 0x4313) && (pdev
->device
!= 0x431A))) {
3819 b43dbg(wl
, "Ignoring unconnected 802.11 core\n");
3824 wldev
= kzalloc(sizeof(*wldev
), GFP_KERNEL
);
3830 b43_set_status(wldev
, B43_STAT_UNINIT
);
3831 wldev
->bad_frames_preempt
= modparam_bad_frames_preempt
;
3832 tasklet_init(&wldev
->isr_tasklet
,
3833 (void (*)(unsigned long))b43_interrupt_tasklet
,
3834 (unsigned long)wldev
);
3836 wldev
->__using_pio
= 1;
3837 INIT_LIST_HEAD(&wldev
->list
);
3839 err
= b43_wireless_core_attach(wldev
);
3841 goto err_kfree_wldev
;
3843 list_add(&wldev
->list
, &wl
->devlist
);
3845 ssb_set_drvdata(dev
, wldev
);
3846 b43_debugfs_add_device(wldev
);
3856 static void b43_sprom_fixup(struct ssb_bus
*bus
)
3858 /* boardflags workarounds */
3859 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_DELL
&&
3860 bus
->chip_id
== 0x4301 && bus
->boardinfo
.rev
== 0x74)
3861 bus
->sprom
.r1
.boardflags_lo
|= B43_BFL_BTCOEXIST
;
3862 if (bus
->boardinfo
.vendor
== PCI_VENDOR_ID_APPLE
&&
3863 bus
->boardinfo
.type
== 0x4E && bus
->boardinfo
.rev
> 0x40)
3864 bus
->sprom
.r1
.boardflags_lo
|= B43_BFL_PACTRL
;
3866 /* Handle case when gain is not set in sprom */
3867 if (bus
->sprom
.r1
.antenna_gain_a
== 0xFF)
3868 bus
->sprom
.r1
.antenna_gain_a
= 2;
3869 if (bus
->sprom
.r1
.antenna_gain_bg
== 0xFF)
3870 bus
->sprom
.r1
.antenna_gain_bg
= 2;
3872 /* Convert Antennagain values to Q5.2 */
3873 bus
->sprom
.r1
.antenna_gain_a
<<= 2;
3874 bus
->sprom
.r1
.antenna_gain_bg
<<= 2;
3877 static void b43_wireless_exit(struct ssb_device
*dev
, struct b43_wl
*wl
)
3879 struct ieee80211_hw
*hw
= wl
->hw
;
3881 ssb_set_devtypedata(dev
, NULL
);
3882 ieee80211_free_hw(hw
);
3885 static int b43_wireless_init(struct ssb_device
*dev
)
3887 struct ssb_sprom
*sprom
= &dev
->bus
->sprom
;
3888 struct ieee80211_hw
*hw
;
3892 b43_sprom_fixup(dev
->bus
);
3894 hw
= ieee80211_alloc_hw(sizeof(*wl
), &b43_hw_ops
);
3896 b43err(NULL
, "Could not allocate ieee80211 device\n");
3901 hw
->flags
= IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE
|
3902 IEEE80211_HW_MONITOR_DURING_OPER
;
3903 hw
->max_signal
= 100;
3904 hw
->max_rssi
= -110;
3905 hw
->max_noise
= -110;
3906 hw
->queues
= 1; /* FIXME: hardware has more queues */
3907 SET_IEEE80211_DEV(hw
, dev
->dev
);
3908 if (is_valid_ether_addr(sprom
->r1
.et1mac
))
3909 SET_IEEE80211_PERM_ADDR(hw
, sprom
->r1
.et1mac
);
3911 SET_IEEE80211_PERM_ADDR(hw
, sprom
->r1
.il0mac
);
3913 /* Get and initialize struct b43_wl */
3914 wl
= hw_to_b43_wl(hw
);
3915 memset(wl
, 0, sizeof(*wl
));
3917 spin_lock_init(&wl
->irq_lock
);
3918 spin_lock_init(&wl
->leds_lock
);
3919 mutex_init(&wl
->mutex
);
3920 INIT_LIST_HEAD(&wl
->devlist
);
3922 ssb_set_devtypedata(dev
, wl
);
3923 b43info(wl
, "Broadcom %04X WLAN found\n", dev
->bus
->chip_id
);
3929 static int b43_probe(struct ssb_device
*dev
, const struct ssb_device_id
*id
)
3935 wl
= ssb_get_devtypedata(dev
);
3937 /* Probing the first core. Must setup common struct b43_wl */
3939 err
= b43_wireless_init(dev
);
3942 wl
= ssb_get_devtypedata(dev
);
3945 err
= b43_one_core_attach(dev
, wl
);
3947 goto err_wireless_exit
;
3950 err
= ieee80211_register_hw(wl
->hw
);
3952 goto err_one_core_detach
;
3958 err_one_core_detach
:
3959 b43_one_core_detach(dev
);
3962 b43_wireless_exit(dev
, wl
);
3966 static void b43_remove(struct ssb_device
*dev
)
3968 struct b43_wl
*wl
= ssb_get_devtypedata(dev
);
3969 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
3972 if (wl
->current_dev
== wldev
)
3973 ieee80211_unregister_hw(wl
->hw
);
3975 b43_one_core_detach(dev
);
3977 if (list_empty(&wl
->devlist
)) {
3978 /* Last core on the chip unregistered.
3979 * We can destroy common struct b43_wl.
3981 b43_wireless_exit(dev
, wl
);
3985 /* Perform a hardware reset. This can be called from any context. */
3986 void b43_controller_restart(struct b43_wldev
*dev
, const char *reason
)
3988 /* Must avoid requeueing, if we are in shutdown. */
3989 if (b43_status(dev
) < B43_STAT_INITIALIZED
)
3991 b43info(dev
->wl
, "Controller RESET (%s) ...\n", reason
);
3992 queue_work(dev
->wl
->hw
->workqueue
, &dev
->restart_work
);
3997 static int b43_suspend(struct ssb_device
*dev
, pm_message_t state
)
3999 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
4000 struct b43_wl
*wl
= wldev
->wl
;
4002 b43dbg(wl
, "Suspending...\n");
4004 mutex_lock(&wl
->mutex
);
4005 wldev
->suspend_init_status
= b43_status(wldev
);
4006 if (wldev
->suspend_init_status
>= B43_STAT_STARTED
)
4007 b43_wireless_core_stop(wldev
);
4008 if (wldev
->suspend_init_status
>= B43_STAT_INITIALIZED
)
4009 b43_wireless_core_exit(wldev
);
4010 mutex_unlock(&wl
->mutex
);
4012 b43dbg(wl
, "Device suspended.\n");
4017 static int b43_resume(struct ssb_device
*dev
)
4019 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
4020 struct b43_wl
*wl
= wldev
->wl
;
4023 b43dbg(wl
, "Resuming...\n");
4025 mutex_lock(&wl
->mutex
);
4026 if (wldev
->suspend_init_status
>= B43_STAT_INITIALIZED
) {
4027 err
= b43_wireless_core_init(wldev
);
4029 b43err(wl
, "Resume failed at core init\n");
4033 if (wldev
->suspend_init_status
>= B43_STAT_STARTED
) {
4034 err
= b43_wireless_core_start(wldev
);
4036 b43_wireless_core_exit(wldev
);
4037 b43err(wl
, "Resume failed at core start\n");
4041 mutex_unlock(&wl
->mutex
);
4043 b43dbg(wl
, "Device resumed.\n");
4048 #else /* CONFIG_PM */
4049 # define b43_suspend NULL
4050 # define b43_resume NULL
4051 #endif /* CONFIG_PM */
4053 static struct ssb_driver b43_ssb_driver
= {
4054 .name
= KBUILD_MODNAME
,
4055 .id_table
= b43_ssb_tbl
,
4057 .remove
= b43_remove
,
4058 .suspend
= b43_suspend
,
4059 .resume
= b43_resume
,
4062 static int __init
b43_init(void)
4067 err
= b43_pcmcia_init();
4070 err
= ssb_driver_register(&b43_ssb_driver
);
4072 goto err_pcmcia_exit
;
4083 static void __exit
b43_exit(void)
4085 ssb_driver_unregister(&b43_ssb_driver
);
4090 module_init(b43_init
)
4091 module_exit(b43_exit
)