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b43: Fix PHY register routing
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / b43 / phy.c
1 /*
2
3 Broadcom B43 wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; see the file COPYING. If not, write to
23 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
24 Boston, MA 02110-1301, USA.
25
26 */
27
28 #include <linux/delay.h>
29 #include <linux/io.h>
30 #include <linux/types.h>
31
32 #include "b43.h"
33 #include "phy.h"
34 #include "nphy.h"
35 #include "main.h"
36 #include "tables.h"
37 #include "lo.h"
38 #include "wa.h"
39
40
41 static const s8 b43_tssi2dbm_b_table[] = {
42 0x4D, 0x4C, 0x4B, 0x4A,
43 0x4A, 0x49, 0x48, 0x47,
44 0x47, 0x46, 0x45, 0x45,
45 0x44, 0x43, 0x42, 0x42,
46 0x41, 0x40, 0x3F, 0x3E,
47 0x3D, 0x3C, 0x3B, 0x3A,
48 0x39, 0x38, 0x37, 0x36,
49 0x35, 0x34, 0x32, 0x31,
50 0x30, 0x2F, 0x2D, 0x2C,
51 0x2B, 0x29, 0x28, 0x26,
52 0x25, 0x23, 0x21, 0x1F,
53 0x1D, 0x1A, 0x17, 0x14,
54 0x10, 0x0C, 0x06, 0x00,
55 -7, -7, -7, -7,
56 -7, -7, -7, -7,
57 -7, -7, -7, -7,
58 };
59
60 static const s8 b43_tssi2dbm_g_table[] = {
61 77, 77, 77, 76,
62 76, 76, 75, 75,
63 74, 74, 73, 73,
64 73, 72, 72, 71,
65 71, 70, 70, 69,
66 68, 68, 67, 67,
67 66, 65, 65, 64,
68 63, 63, 62, 61,
69 60, 59, 58, 57,
70 56, 55, 54, 53,
71 52, 50, 49, 47,
72 45, 43, 40, 37,
73 33, 28, 22, 14,
74 5, -7, -20, -20,
75 -20, -20, -20, -20,
76 -20, -20, -20, -20,
77 };
78
79 const u8 b43_radio_channel_codes_bg[] = {
80 12, 17, 22, 27,
81 32, 37, 42, 47,
82 52, 57, 62, 67,
83 72, 84,
84 };
85
86 static void b43_phy_initg(struct b43_wldev *dev);
87
88 /* Reverse the bits of a 4bit value.
89 * Example: 1101 is flipped 1011
90 */
91 static u16 flip_4bit(u16 value)
92 {
93 u16 flipped = 0x0000;
94
95 B43_WARN_ON(value & ~0x000F);
96
97 flipped |= (value & 0x0001) << 3;
98 flipped |= (value & 0x0002) << 1;
99 flipped |= (value & 0x0004) >> 1;
100 flipped |= (value & 0x0008) >> 3;
101
102 return flipped;
103 }
104
105 static void generate_rfatt_list(struct b43_wldev *dev,
106 struct b43_rfatt_list *list)
107 {
108 struct b43_phy *phy = &dev->phy;
109
110 /* APHY.rev < 5 || GPHY.rev < 6 */
111 static const struct b43_rfatt rfatt_0[] = {
112 {.att = 3,.with_padmix = 0,},
113 {.att = 1,.with_padmix = 0,},
114 {.att = 5,.with_padmix = 0,},
115 {.att = 7,.with_padmix = 0,},
116 {.att = 9,.with_padmix = 0,},
117 {.att = 2,.with_padmix = 0,},
118 {.att = 0,.with_padmix = 0,},
119 {.att = 4,.with_padmix = 0,},
120 {.att = 6,.with_padmix = 0,},
121 {.att = 8,.with_padmix = 0,},
122 {.att = 1,.with_padmix = 1,},
123 {.att = 2,.with_padmix = 1,},
124 {.att = 3,.with_padmix = 1,},
125 {.att = 4,.with_padmix = 1,},
126 };
127 /* Radio.rev == 8 && Radio.version == 0x2050 */
128 static const struct b43_rfatt rfatt_1[] = {
129 {.att = 2,.with_padmix = 1,},
130 {.att = 4,.with_padmix = 1,},
131 {.att = 6,.with_padmix = 1,},
132 {.att = 8,.with_padmix = 1,},
133 {.att = 10,.with_padmix = 1,},
134 {.att = 12,.with_padmix = 1,},
135 {.att = 14,.with_padmix = 1,},
136 };
137 /* Otherwise */
138 static const struct b43_rfatt rfatt_2[] = {
139 {.att = 0,.with_padmix = 1,},
140 {.att = 2,.with_padmix = 1,},
141 {.att = 4,.with_padmix = 1,},
142 {.att = 6,.with_padmix = 1,},
143 {.att = 8,.with_padmix = 1,},
144 {.att = 9,.with_padmix = 1,},
145 {.att = 9,.with_padmix = 1,},
146 };
147
148 if ((phy->type == B43_PHYTYPE_A && phy->rev < 5) ||
149 (phy->type == B43_PHYTYPE_G && phy->rev < 6)) {
150 /* Software pctl */
151 list->list = rfatt_0;
152 list->len = ARRAY_SIZE(rfatt_0);
153 list->min_val = 0;
154 list->max_val = 9;
155 return;
156 }
157 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
158 /* Hardware pctl */
159 list->list = rfatt_1;
160 list->len = ARRAY_SIZE(rfatt_1);
161 list->min_val = 2;
162 list->max_val = 14;
163 return;
164 }
165 /* Hardware pctl */
166 list->list = rfatt_2;
167 list->len = ARRAY_SIZE(rfatt_2);
168 list->min_val = 0;
169 list->max_val = 9;
170 }
171
172 static void generate_bbatt_list(struct b43_wldev *dev,
173 struct b43_bbatt_list *list)
174 {
175 static const struct b43_bbatt bbatt_0[] = {
176 {.att = 0,},
177 {.att = 1,},
178 {.att = 2,},
179 {.att = 3,},
180 {.att = 4,},
181 {.att = 5,},
182 {.att = 6,},
183 {.att = 7,},
184 {.att = 8,},
185 };
186
187 list->list = bbatt_0;
188 list->len = ARRAY_SIZE(bbatt_0);
189 list->min_val = 0;
190 list->max_val = 8;
191 }
192
193 bool b43_has_hardware_pctl(struct b43_phy *phy)
194 {
195 if (!phy->hardware_power_control)
196 return 0;
197 switch (phy->type) {
198 case B43_PHYTYPE_A:
199 if (phy->rev >= 5)
200 return 1;
201 break;
202 case B43_PHYTYPE_G:
203 if (phy->rev >= 6)
204 return 1;
205 break;
206 default:
207 B43_WARN_ON(1);
208 }
209 return 0;
210 }
211
212 static void b43_shm_clear_tssi(struct b43_wldev *dev)
213 {
214 struct b43_phy *phy = &dev->phy;
215
216 switch (phy->type) {
217 case B43_PHYTYPE_A:
218 b43_shm_write16(dev, B43_SHM_SHARED, 0x0068, 0x7F7F);
219 b43_shm_write16(dev, B43_SHM_SHARED, 0x006a, 0x7F7F);
220 break;
221 case B43_PHYTYPE_B:
222 case B43_PHYTYPE_G:
223 b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
224 b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
225 b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
226 b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
227 break;
228 }
229 }
230
231 void b43_raw_phy_lock(struct b43_wldev *dev)
232 {
233 struct b43_phy *phy = &dev->phy;
234
235 B43_WARN_ON(!irqs_disabled());
236
237 /* We had a check for MACCTL==0 here, but I think that doesn't
238 * make sense, as MACCTL is never 0 when this is called.
239 * --mb */
240 B43_WARN_ON(b43_read32(dev, B43_MMIO_MACCTL) == 0);
241
242 if (dev->dev->id.revision < 3) {
243 b43_mac_suspend(dev);
244 spin_lock(&phy->lock);
245 } else {
246 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
247 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
248 }
249 phy->locked = 1;
250 }
251
252 void b43_raw_phy_unlock(struct b43_wldev *dev)
253 {
254 struct b43_phy *phy = &dev->phy;
255
256 B43_WARN_ON(!irqs_disabled());
257 if (dev->dev->id.revision < 3) {
258 if (phy->locked) {
259 spin_unlock(&phy->lock);
260 b43_mac_enable(dev);
261 }
262 } else {
263 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
264 b43_power_saving_ctl_bits(dev, 0);
265 }
266 phy->locked = 0;
267 }
268
269 /* Different PHYs require different register routing flags.
270 * This adjusts (and does sanity checks on) the routing flags.
271 */
272 static inline u16 adjust_phyreg_for_phytype(struct b43_phy *phy,
273 u16 offset, struct b43_wldev *dev)
274 {
275 if (phy->type == B43_PHYTYPE_A) {
276 /* OFDM registers are base-registers for the A-PHY. */
277 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
278 offset &= ~B43_PHYROUTE;
279 offset |= B43_PHYROUTE_BASE;
280 }
281 }
282
283 #if B43_DEBUG
284 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
285 /* Ext-G registers are only available on G-PHYs */
286 if (phy->type != B43_PHYTYPE_G) {
287 b43err(dev->wl, "Invalid EXT-G PHY access at "
288 "0x%04X on PHY type %u\n", offset, phy->type);
289 dump_stack();
290 }
291 }
292 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
293 /* N-BMODE registers are only available on N-PHYs */
294 if (phy->type != B43_PHYTYPE_N) {
295 b43err(dev->wl, "Invalid N-BMODE PHY access at "
296 "0x%04X on PHY type %u\n", offset, phy->type);
297 dump_stack();
298 }
299 }
300 #endif /* B43_DEBUG */
301
302 return offset;
303 }
304
305 u16 b43_phy_read(struct b43_wldev * dev, u16 offset)
306 {
307 struct b43_phy *phy = &dev->phy;
308
309 offset = adjust_phyreg_for_phytype(phy, offset, dev);
310 b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
311 return b43_read16(dev, B43_MMIO_PHY_DATA);
312 }
313
314 void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val)
315 {
316 struct b43_phy *phy = &dev->phy;
317
318 offset = adjust_phyreg_for_phytype(phy, offset, dev);
319 b43_write16(dev, B43_MMIO_PHY_CONTROL, offset);
320 b43_write16(dev, B43_MMIO_PHY_DATA, val);
321 }
322
323 /* Adjust the transmission power output (G-PHY) */
324 void b43_set_txpower_g(struct b43_wldev *dev,
325 const struct b43_bbatt *bbatt,
326 const struct b43_rfatt *rfatt, u8 tx_control)
327 {
328 struct b43_phy *phy = &dev->phy;
329 struct b43_txpower_lo_control *lo = phy->lo_control;
330 u16 bb, rf;
331 u16 tx_bias, tx_magn;
332
333 bb = bbatt->att;
334 rf = rfatt->att;
335 tx_bias = lo->tx_bias;
336 tx_magn = lo->tx_magn;
337 if (unlikely(tx_bias == 0xFF))
338 tx_bias = 0;
339
340 /* Save the values for later */
341 phy->tx_control = tx_control;
342 memcpy(&phy->rfatt, rfatt, sizeof(*rfatt));
343 memcpy(&phy->bbatt, bbatt, sizeof(*bbatt));
344
345 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
346 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
347 "rfatt(%u), tx_control(0x%02X), "
348 "tx_bias(0x%02X), tx_magn(0x%02X)\n",
349 bb, rf, tx_control, tx_bias, tx_magn);
350 }
351
352 b43_phy_set_baseband_attenuation(dev, bb);
353 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
354 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
355 b43_radio_write16(dev, 0x43,
356 (rf & 0x000F) | (tx_control & 0x0070));
357 } else {
358 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
359 & 0xFFF0) | (rf & 0x000F));
360 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
361 & ~0x0070) | (tx_control &
362 0x0070));
363 }
364 if (has_tx_magnification(phy)) {
365 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
366 } else {
367 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
368 & 0xFFF0) | (tx_bias & 0x000F));
369 }
370 if (phy->type == B43_PHYTYPE_G)
371 b43_lo_g_adjust(dev);
372 }
373
374 static void default_baseband_attenuation(struct b43_wldev *dev,
375 struct b43_bbatt *bb)
376 {
377 struct b43_phy *phy = &dev->phy;
378
379 if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
380 bb->att = 0;
381 else
382 bb->att = 2;
383 }
384
385 static void default_radio_attenuation(struct b43_wldev *dev,
386 struct b43_rfatt *rf)
387 {
388 struct ssb_bus *bus = dev->dev->bus;
389 struct b43_phy *phy = &dev->phy;
390
391 rf->with_padmix = 0;
392
393 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
394 bus->boardinfo.type == SSB_BOARD_BCM4309G) {
395 if (bus->boardinfo.rev < 0x43) {
396 rf->att = 2;
397 return;
398 } else if (bus->boardinfo.rev < 0x51) {
399 rf->att = 3;
400 return;
401 }
402 }
403
404 if (phy->type == B43_PHYTYPE_A) {
405 rf->att = 0x60;
406 return;
407 }
408
409 switch (phy->radio_ver) {
410 case 0x2053:
411 switch (phy->radio_rev) {
412 case 1:
413 rf->att = 6;
414 return;
415 }
416 break;
417 case 0x2050:
418 switch (phy->radio_rev) {
419 case 0:
420 rf->att = 5;
421 return;
422 case 1:
423 if (phy->type == B43_PHYTYPE_G) {
424 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
425 && bus->boardinfo.type == SSB_BOARD_BCM4309G
426 && bus->boardinfo.rev >= 30)
427 rf->att = 3;
428 else if (bus->boardinfo.vendor ==
429 SSB_BOARDVENDOR_BCM
430 && bus->boardinfo.type ==
431 SSB_BOARD_BU4306)
432 rf->att = 3;
433 else
434 rf->att = 1;
435 } else {
436 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
437 && bus->boardinfo.type == SSB_BOARD_BCM4309G
438 && bus->boardinfo.rev >= 30)
439 rf->att = 7;
440 else
441 rf->att = 6;
442 }
443 return;
444 case 2:
445 if (phy->type == B43_PHYTYPE_G) {
446 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
447 && bus->boardinfo.type == SSB_BOARD_BCM4309G
448 && bus->boardinfo.rev >= 30)
449 rf->att = 3;
450 else if (bus->boardinfo.vendor ==
451 SSB_BOARDVENDOR_BCM
452 && bus->boardinfo.type ==
453 SSB_BOARD_BU4306)
454 rf->att = 5;
455 else if (bus->chip_id == 0x4320)
456 rf->att = 4;
457 else
458 rf->att = 3;
459 } else
460 rf->att = 6;
461 return;
462 case 3:
463 rf->att = 5;
464 return;
465 case 4:
466 case 5:
467 rf->att = 1;
468 return;
469 case 6:
470 case 7:
471 rf->att = 5;
472 return;
473 case 8:
474 rf->att = 0xA;
475 rf->with_padmix = 1;
476 return;
477 case 9:
478 default:
479 rf->att = 5;
480 return;
481 }
482 }
483 rf->att = 5;
484 }
485
486 static u16 default_tx_control(struct b43_wldev *dev)
487 {
488 struct b43_phy *phy = &dev->phy;
489
490 if (phy->radio_ver != 0x2050)
491 return 0;
492 if (phy->radio_rev == 1)
493 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
494 if (phy->radio_rev < 6)
495 return B43_TXCTL_PA2DB;
496 if (phy->radio_rev == 8)
497 return B43_TXCTL_TXMIX;
498 return 0;
499 }
500
501 /* This func is called "PHY calibrate" in the specs... */
502 void b43_phy_early_init(struct b43_wldev *dev)
503 {
504 struct b43_phy *phy = &dev->phy;
505 struct b43_txpower_lo_control *lo = phy->lo_control;
506
507 default_baseband_attenuation(dev, &phy->bbatt);
508 default_radio_attenuation(dev, &phy->rfatt);
509 phy->tx_control = (default_tx_control(dev) << 4);
510
511 /* Commit previous writes */
512 b43_read32(dev, B43_MMIO_MACCTL);
513
514 if (phy->type == B43_PHYTYPE_B || phy->type == B43_PHYTYPE_G) {
515 generate_rfatt_list(dev, &lo->rfatt_list);
516 generate_bbatt_list(dev, &lo->bbatt_list);
517 }
518 if (phy->type == B43_PHYTYPE_G && phy->rev == 1) {
519 /* Workaround: Temporarly disable gmode through the early init
520 * phase, as the gmode stuff is not needed for phy rev 1 */
521 phy->gmode = 0;
522 b43_wireless_core_reset(dev, 0);
523 b43_phy_initg(dev);
524 phy->gmode = 1;
525 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
526 }
527 }
528
529 /* GPHY_TSSI_Power_Lookup_Table_Init */
530 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
531 {
532 struct b43_phy *phy = &dev->phy;
533 int i;
534 u16 value;
535
536 for (i = 0; i < 32; i++)
537 b43_ofdmtab_write16(dev, 0x3C20, i, phy->tssi2dbm[i]);
538 for (i = 32; i < 64; i++)
539 b43_ofdmtab_write16(dev, 0x3C00, i - 32, phy->tssi2dbm[i]);
540 for (i = 0; i < 64; i += 2) {
541 value = (u16) phy->tssi2dbm[i];
542 value |= ((u16) phy->tssi2dbm[i + 1]) << 8;
543 b43_phy_write(dev, 0x380 + (i / 2), value);
544 }
545 }
546
547 /* GPHY_Gain_Lookup_Table_Init */
548 static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
549 {
550 struct b43_phy *phy = &dev->phy;
551 struct b43_txpower_lo_control *lo = phy->lo_control;
552 u16 nr_written = 0;
553 u16 tmp;
554 u8 rf, bb;
555
556 if (!lo->lo_measured) {
557 b43_phy_write(dev, 0x3FF, 0);
558 return;
559 }
560
561 for (rf = 0; rf < lo->rfatt_list.len; rf++) {
562 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
563 if (nr_written >= 0x40)
564 return;
565 tmp = lo->bbatt_list.list[bb].att;
566 tmp <<= 8;
567 if (phy->radio_rev == 8)
568 tmp |= 0x50;
569 else
570 tmp |= 0x40;
571 tmp |= lo->rfatt_list.list[rf].att;
572 b43_phy_write(dev, 0x3C0 + nr_written, tmp);
573 nr_written++;
574 }
575 }
576 }
577
578 /* GPHY_DC_Lookup_Table */
579 void b43_gphy_dc_lt_init(struct b43_wldev *dev)
580 {
581 struct b43_phy *phy = &dev->phy;
582 struct b43_txpower_lo_control *lo = phy->lo_control;
583 struct b43_loctl *loctl0;
584 struct b43_loctl *loctl1;
585 int i;
586 int rf_offset, bb_offset;
587 u16 tmp;
588
589 for (i = 0; i < lo->rfatt_list.len + lo->bbatt_list.len; i += 2) {
590 rf_offset = i / lo->rfatt_list.len;
591 bb_offset = i % lo->rfatt_list.len;
592
593 loctl0 = b43_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
594 &lo->bbatt_list.list[bb_offset]);
595 if (i + 1 < lo->rfatt_list.len * lo->bbatt_list.len) {
596 rf_offset = (i + 1) / lo->rfatt_list.len;
597 bb_offset = (i + 1) % lo->rfatt_list.len;
598
599 loctl1 =
600 b43_get_lo_g_ctl(dev,
601 &lo->rfatt_list.list[rf_offset],
602 &lo->bbatt_list.list[bb_offset]);
603 } else
604 loctl1 = loctl0;
605
606 tmp = ((u16) loctl0->q & 0xF);
607 tmp |= ((u16) loctl0->i & 0xF) << 4;
608 tmp |= ((u16) loctl1->q & 0xF) << 8;
609 tmp |= ((u16) loctl1->i & 0xF) << 12; //FIXME?
610 b43_phy_write(dev, 0x3A0 + (i / 2), tmp);
611 }
612 }
613
614 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
615 {
616 //TODO
617 }
618
619 static void hardware_pctl_init_gphy(struct b43_wldev *dev)
620 {
621 struct b43_phy *phy = &dev->phy;
622
623 b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
624 | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
625 b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
626 | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
627 b43_gphy_tssi_power_lt_init(dev);
628 b43_gphy_gain_lt_init(dev);
629 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) & 0xFFBF);
630 b43_phy_write(dev, 0x0014, 0x0000);
631
632 B43_WARN_ON(phy->rev < 6);
633 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
634 | 0x0800);
635 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478)
636 & 0xFEFF);
637 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801)
638 & 0xFFBF);
639
640 b43_gphy_dc_lt_init(dev);
641 }
642
643 /* HardwarePowerControl init for A and G PHY */
644 static void b43_hardware_pctl_init(struct b43_wldev *dev)
645 {
646 struct b43_phy *phy = &dev->phy;
647
648 if (!b43_has_hardware_pctl(phy)) {
649 /* No hardware power control */
650 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
651 return;
652 }
653 /* Init the hwpctl related hardware */
654 switch (phy->type) {
655 case B43_PHYTYPE_A:
656 hardware_pctl_init_aphy(dev);
657 break;
658 case B43_PHYTYPE_G:
659 hardware_pctl_init_gphy(dev);
660 break;
661 default:
662 B43_WARN_ON(1);
663 }
664 /* Enable hardware pctl in firmware. */
665 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
666 }
667
668 static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
669 {
670 struct b43_phy *phy = &dev->phy;
671
672 if (!b43_has_hardware_pctl(phy)) {
673 b43_phy_write(dev, 0x047A, 0xC111);
674 return;
675 }
676
677 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036) & 0xFEFF);
678 b43_phy_write(dev, 0x002F, 0x0202);
679 b43_phy_write(dev, 0x047C, b43_phy_read(dev, 0x047C) | 0x0002);
680 b43_phy_write(dev, 0x047A, b43_phy_read(dev, 0x047A) | 0xF000);
681 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
682 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
683 & 0xFF0F) | 0x0010);
684 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
685 | 0x8000);
686 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
687 & 0xFFC0) | 0x0010);
688 b43_phy_write(dev, 0x002E, 0xC07F);
689 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
690 | 0x0400);
691 } else {
692 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
693 | 0x0200);
694 b43_phy_write(dev, 0x0036, b43_phy_read(dev, 0x0036)
695 | 0x0400);
696 b43_phy_write(dev, 0x005D, b43_phy_read(dev, 0x005D)
697 & 0x7FFF);
698 b43_phy_write(dev, 0x004F, b43_phy_read(dev, 0x004F)
699 & 0xFFFE);
700 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
701 & 0xFFC0) | 0x0010);
702 b43_phy_write(dev, 0x002E, 0xC07F);
703 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
704 & 0xFF0F) | 0x0010);
705 }
706 }
707
708 /* Intialize B/G PHY power control
709 * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
710 */
711 static void b43_phy_init_pctl(struct b43_wldev *dev)
712 {
713 struct ssb_bus *bus = dev->dev->bus;
714 struct b43_phy *phy = &dev->phy;
715 struct b43_rfatt old_rfatt;
716 struct b43_bbatt old_bbatt;
717 u8 old_tx_control = 0;
718
719 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
720 (bus->boardinfo.type == SSB_BOARD_BU4306))
721 return;
722
723 b43_phy_write(dev, 0x0028, 0x8018);
724
725 /* This does something with the Analog... */
726 b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
727 & 0xFFDF);
728
729 if (phy->type == B43_PHYTYPE_G && !phy->gmode)
730 return;
731 b43_hardware_pctl_early_init(dev);
732 if (phy->cur_idle_tssi == 0) {
733 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
734 b43_radio_write16(dev, 0x0076,
735 (b43_radio_read16(dev, 0x0076)
736 & 0x00F7) | 0x0084);
737 } else {
738 struct b43_rfatt rfatt;
739 struct b43_bbatt bbatt;
740
741 memcpy(&old_rfatt, &phy->rfatt, sizeof(old_rfatt));
742 memcpy(&old_bbatt, &phy->bbatt, sizeof(old_bbatt));
743 old_tx_control = phy->tx_control;
744
745 bbatt.att = 11;
746 if (phy->radio_rev == 8) {
747 rfatt.att = 15;
748 rfatt.with_padmix = 1;
749 } else {
750 rfatt.att = 9;
751 rfatt.with_padmix = 0;
752 }
753 b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
754 }
755 b43_dummy_transmission(dev);
756 phy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
757 if (B43_DEBUG) {
758 /* Current-Idle-TSSI sanity check. */
759 if (abs(phy->cur_idle_tssi - phy->tgt_idle_tssi) >= 20) {
760 b43dbg(dev->wl,
761 "!WARNING! Idle-TSSI phy->cur_idle_tssi "
762 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
763 "adjustment.\n", phy->cur_idle_tssi,
764 phy->tgt_idle_tssi);
765 phy->cur_idle_tssi = 0;
766 }
767 }
768 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
769 b43_radio_write16(dev, 0x0076,
770 b43_radio_read16(dev, 0x0076)
771 & 0xFF7B);
772 } else {
773 b43_set_txpower_g(dev, &old_bbatt,
774 &old_rfatt, old_tx_control);
775 }
776 }
777 b43_hardware_pctl_init(dev);
778 b43_shm_clear_tssi(dev);
779 }
780
781 static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
782 {
783 int i;
784
785 if (dev->phy.rev < 3) {
786 if (enable)
787 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
788 b43_ofdmtab_write16(dev,
789 B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
790 b43_ofdmtab_write16(dev,
791 B43_OFDMTAB_WRSSI, i, 0xFFF8);
792 }
793 else
794 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
795 b43_ofdmtab_write16(dev,
796 B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
797 b43_ofdmtab_write16(dev,
798 B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
799 }
800 } else {
801 if (enable)
802 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
803 b43_ofdmtab_write16(dev,
804 B43_OFDMTAB_WRSSI, i, 0x0820);
805 else
806 for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
807 b43_ofdmtab_write16(dev,
808 B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
809 }
810 }
811
812 static void b43_phy_ww(struct b43_wldev *dev)
813 {
814 u16 b, curr_s, best_s = 0xFFFF;
815 int i;
816
817 b43_phy_write(dev, B43_PHY_CRS0,
818 b43_phy_read(dev, B43_PHY_CRS0) & ~B43_PHY_CRS0_EN);
819 b43_phy_write(dev, B43_PHY_OFDM(0x1B),
820 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) | 0x1000);
821 b43_phy_write(dev, B43_PHY_OFDM(0x82),
822 (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & 0xF0FF) | 0x0300);
823 b43_radio_write16(dev, 0x0009,
824 b43_radio_read16(dev, 0x0009) | 0x0080);
825 b43_radio_write16(dev, 0x0012,
826 (b43_radio_read16(dev, 0x0012) & 0xFFFC) | 0x0002);
827 b43_wa_initgains(dev);
828 b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
829 b = b43_phy_read(dev, B43_PHY_PWRDOWN);
830 b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
831 b43_radio_write16(dev, 0x0004,
832 b43_radio_read16(dev, 0x0004) | 0x0004);
833 for (i = 0x10; i <= 0x20; i++) {
834 b43_radio_write16(dev, 0x0013, i);
835 curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
836 if (!curr_s) {
837 best_s = 0x0000;
838 break;
839 } else if (curr_s >= 0x0080)
840 curr_s = 0x0100 - curr_s;
841 if (curr_s < best_s)
842 best_s = curr_s;
843 }
844 b43_phy_write(dev, B43_PHY_PWRDOWN, b);
845 b43_radio_write16(dev, 0x0004,
846 b43_radio_read16(dev, 0x0004) & 0xFFFB);
847 b43_radio_write16(dev, 0x0013, best_s);
848 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
849 b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
850 b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
851 b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
852 b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
853 b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
854 b43_phy_write(dev, B43_PHY_OFDM(0xBB),
855 (b43_phy_read(dev, B43_PHY_OFDM(0xBB)) & 0xF000) | 0x0053);
856 b43_phy_write(dev, B43_PHY_OFDM61,
857 (b43_phy_read(dev, B43_PHY_OFDM61 & 0xFE1F)) | 0x0120);
858 b43_phy_write(dev, B43_PHY_OFDM(0x13),
859 (b43_phy_read(dev, B43_PHY_OFDM(0x13)) & 0x0FFF) | 0x3000);
860 b43_phy_write(dev, B43_PHY_OFDM(0x14),
861 (b43_phy_read(dev, B43_PHY_OFDM(0x14)) & 0x0FFF) | 0x3000);
862 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
863 for (i = 0; i < 6; i++)
864 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
865 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
866 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
867 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
868 b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
869 b43_phy_write(dev, B43_PHY_CRS0,
870 b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
871 }
872
873 /* Initialize APHY. This is also called for the GPHY in some cases. */
874 static void b43_phy_inita(struct b43_wldev *dev)
875 {
876 struct ssb_bus *bus = dev->dev->bus;
877 struct b43_phy *phy = &dev->phy;
878
879 might_sleep();
880
881 if (phy->rev >= 6) {
882 if (phy->type == B43_PHYTYPE_A)
883 b43_phy_write(dev, B43_PHY_OFDM(0x1B),
884 b43_phy_read(dev, B43_PHY_OFDM(0x1B)) & ~0x1000);
885 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
886 b43_phy_write(dev, B43_PHY_ENCORE,
887 b43_phy_read(dev, B43_PHY_ENCORE) | 0x0010);
888 else
889 b43_phy_write(dev, B43_PHY_ENCORE,
890 b43_phy_read(dev, B43_PHY_ENCORE) & ~0x1010);
891 }
892
893 b43_wa_all(dev);
894
895 if (phy->type == B43_PHYTYPE_A) {
896 if (phy->gmode && (phy->rev < 3))
897 b43_phy_write(dev, 0x0034,
898 b43_phy_read(dev, 0x0034) | 0x0001);
899 b43_phy_rssiagc(dev, 0);
900
901 b43_phy_write(dev, B43_PHY_CRS0,
902 b43_phy_read(dev, B43_PHY_CRS0) | B43_PHY_CRS0_EN);
903
904 b43_radio_init2060(dev);
905
906 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
907 ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
908 (bus->boardinfo.type == SSB_BOARD_BU4309))) {
909 ; //TODO: A PHY LO
910 }
911
912 if (phy->rev >= 3)
913 b43_phy_ww(dev);
914
915 hardware_pctl_init_aphy(dev);
916
917 //TODO: radar detection
918 }
919
920 if ((phy->type == B43_PHYTYPE_G) &&
921 (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) {
922 b43_phy_write(dev, B43_PHY_OFDM(0x6E),
923 (b43_phy_read(dev, B43_PHY_OFDM(0x6E))
924 & 0xE000) | 0x3CF);
925 }
926 }
927
928 static void b43_phy_initb2(struct b43_wldev *dev)
929 {
930 struct b43_phy *phy = &dev->phy;
931 u16 offset, val;
932
933 b43_write16(dev, 0x03EC, 0x3F22);
934 b43_phy_write(dev, 0x0020, 0x301C);
935 b43_phy_write(dev, 0x0026, 0x0000);
936 b43_phy_write(dev, 0x0030, 0x00C6);
937 b43_phy_write(dev, 0x0088, 0x3E00);
938 val = 0x3C3D;
939 for (offset = 0x0089; offset < 0x00A7; offset++) {
940 b43_phy_write(dev, offset, val);
941 val -= 0x0202;
942 }
943 b43_phy_write(dev, 0x03E4, 0x3000);
944 b43_radio_selectchannel(dev, phy->channel, 0);
945 if (phy->radio_ver != 0x2050) {
946 b43_radio_write16(dev, 0x0075, 0x0080);
947 b43_radio_write16(dev, 0x0079, 0x0081);
948 }
949 b43_radio_write16(dev, 0x0050, 0x0020);
950 b43_radio_write16(dev, 0x0050, 0x0023);
951 if (phy->radio_ver == 0x2050) {
952 b43_radio_write16(dev, 0x0050, 0x0020);
953 b43_radio_write16(dev, 0x005A, 0x0070);
954 b43_radio_write16(dev, 0x005B, 0x007B);
955 b43_radio_write16(dev, 0x005C, 0x00B0);
956 b43_radio_write16(dev, 0x007A, 0x000F);
957 b43_phy_write(dev, 0x0038, 0x0677);
958 b43_radio_init2050(dev);
959 }
960 b43_phy_write(dev, 0x0014, 0x0080);
961 b43_phy_write(dev, 0x0032, 0x00CA);
962 b43_phy_write(dev, 0x0032, 0x00CC);
963 b43_phy_write(dev, 0x0035, 0x07C2);
964 b43_lo_b_measure(dev);
965 b43_phy_write(dev, 0x0026, 0xCC00);
966 if (phy->radio_ver != 0x2050)
967 b43_phy_write(dev, 0x0026, 0xCE00);
968 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1000);
969 b43_phy_write(dev, 0x002A, 0x88A3);
970 if (phy->radio_ver != 0x2050)
971 b43_phy_write(dev, 0x002A, 0x88C2);
972 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
973 b43_phy_init_pctl(dev);
974 }
975
976 static void b43_phy_initb4(struct b43_wldev *dev)
977 {
978 struct b43_phy *phy = &dev->phy;
979 u16 offset, val;
980
981 b43_write16(dev, 0x03EC, 0x3F22);
982 b43_phy_write(dev, 0x0020, 0x301C);
983 b43_phy_write(dev, 0x0026, 0x0000);
984 b43_phy_write(dev, 0x0030, 0x00C6);
985 b43_phy_write(dev, 0x0088, 0x3E00);
986 val = 0x3C3D;
987 for (offset = 0x0089; offset < 0x00A7; offset++) {
988 b43_phy_write(dev, offset, val);
989 val -= 0x0202;
990 }
991 b43_phy_write(dev, 0x03E4, 0x3000);
992 b43_radio_selectchannel(dev, phy->channel, 0);
993 if (phy->radio_ver != 0x2050) {
994 b43_radio_write16(dev, 0x0075, 0x0080);
995 b43_radio_write16(dev, 0x0079, 0x0081);
996 }
997 b43_radio_write16(dev, 0x0050, 0x0020);
998 b43_radio_write16(dev, 0x0050, 0x0023);
999 if (phy->radio_ver == 0x2050) {
1000 b43_radio_write16(dev, 0x0050, 0x0020);
1001 b43_radio_write16(dev, 0x005A, 0x0070);
1002 b43_radio_write16(dev, 0x005B, 0x007B);
1003 b43_radio_write16(dev, 0x005C, 0x00B0);
1004 b43_radio_write16(dev, 0x007A, 0x000F);
1005 b43_phy_write(dev, 0x0038, 0x0677);
1006 b43_radio_init2050(dev);
1007 }
1008 b43_phy_write(dev, 0x0014, 0x0080);
1009 b43_phy_write(dev, 0x0032, 0x00CA);
1010 if (phy->radio_ver == 0x2050)
1011 b43_phy_write(dev, 0x0032, 0x00E0);
1012 b43_phy_write(dev, 0x0035, 0x07C2);
1013
1014 b43_lo_b_measure(dev);
1015
1016 b43_phy_write(dev, 0x0026, 0xCC00);
1017 if (phy->radio_ver == 0x2050)
1018 b43_phy_write(dev, 0x0026, 0xCE00);
1019 b43_write16(dev, B43_MMIO_CHANNEL_EXT, 0x1100);
1020 b43_phy_write(dev, 0x002A, 0x88A3);
1021 if (phy->radio_ver == 0x2050)
1022 b43_phy_write(dev, 0x002A, 0x88C2);
1023 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1024 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
1025 b43_calc_nrssi_slope(dev);
1026 b43_calc_nrssi_threshold(dev);
1027 }
1028 b43_phy_init_pctl(dev);
1029 }
1030
1031 static void b43_phy_initb5(struct b43_wldev *dev)
1032 {
1033 struct ssb_bus *bus = dev->dev->bus;
1034 struct b43_phy *phy = &dev->phy;
1035 u16 offset, value;
1036 u8 old_channel;
1037
1038 if (phy->analog == 1) {
1039 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
1040 | 0x0050);
1041 }
1042 if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1043 (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1044 value = 0x2120;
1045 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1046 b43_phy_write(dev, offset, value);
1047 value += 0x202;
1048 }
1049 }
1050 b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
1051 | 0x0700);
1052 if (phy->radio_ver == 0x2050)
1053 b43_phy_write(dev, 0x0038, 0x0667);
1054
1055 if (phy->gmode || phy->rev >= 2) {
1056 if (phy->radio_ver == 0x2050) {
1057 b43_radio_write16(dev, 0x007A,
1058 b43_radio_read16(dev, 0x007A)
1059 | 0x0020);
1060 b43_radio_write16(dev, 0x0051,
1061 b43_radio_read16(dev, 0x0051)
1062 | 0x0004);
1063 }
1064 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1065
1066 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1067 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1068
1069 b43_phy_write(dev, 0x001C, 0x186A);
1070
1071 b43_phy_write(dev, 0x0013,
1072 (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
1073 b43_phy_write(dev, 0x0035,
1074 (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
1075 b43_phy_write(dev, 0x005D,
1076 (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
1077 }
1078
1079 if (dev->bad_frames_preempt) {
1080 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
1081 b43_phy_read(dev,
1082 B43_PHY_RADIO_BITFIELD) | (1 << 11));
1083 }
1084
1085 if (phy->analog == 1) {
1086 b43_phy_write(dev, 0x0026, 0xCE00);
1087 b43_phy_write(dev, 0x0021, 0x3763);
1088 b43_phy_write(dev, 0x0022, 0x1BC3);
1089 b43_phy_write(dev, 0x0023, 0x06F9);
1090 b43_phy_write(dev, 0x0024, 0x037E);
1091 } else
1092 b43_phy_write(dev, 0x0026, 0xCC00);
1093 b43_phy_write(dev, 0x0030, 0x00C6);
1094 b43_write16(dev, 0x03EC, 0x3F22);
1095
1096 if (phy->analog == 1)
1097 b43_phy_write(dev, 0x0020, 0x3E1C);
1098 else
1099 b43_phy_write(dev, 0x0020, 0x301C);
1100
1101 if (phy->analog == 0)
1102 b43_write16(dev, 0x03E4, 0x3000);
1103
1104 old_channel = phy->channel;
1105 /* Force to channel 7, even if not supported. */
1106 b43_radio_selectchannel(dev, 7, 0);
1107
1108 if (phy->radio_ver != 0x2050) {
1109 b43_radio_write16(dev, 0x0075, 0x0080);
1110 b43_radio_write16(dev, 0x0079, 0x0081);
1111 }
1112
1113 b43_radio_write16(dev, 0x0050, 0x0020);
1114 b43_radio_write16(dev, 0x0050, 0x0023);
1115
1116 if (phy->radio_ver == 0x2050) {
1117 b43_radio_write16(dev, 0x0050, 0x0020);
1118 b43_radio_write16(dev, 0x005A, 0x0070);
1119 }
1120
1121 b43_radio_write16(dev, 0x005B, 0x007B);
1122 b43_radio_write16(dev, 0x005C, 0x00B0);
1123
1124 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
1125
1126 b43_radio_selectchannel(dev, old_channel, 0);
1127
1128 b43_phy_write(dev, 0x0014, 0x0080);
1129 b43_phy_write(dev, 0x0032, 0x00CA);
1130 b43_phy_write(dev, 0x002A, 0x88A3);
1131
1132 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1133
1134 if (phy->radio_ver == 0x2050)
1135 b43_radio_write16(dev, 0x005D, 0x000D);
1136
1137 b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1138 }
1139
1140 static void b43_phy_initb6(struct b43_wldev *dev)
1141 {
1142 struct b43_phy *phy = &dev->phy;
1143 u16 offset, val;
1144 u8 old_channel;
1145
1146 b43_phy_write(dev, 0x003E, 0x817A);
1147 b43_radio_write16(dev, 0x007A,
1148 (b43_radio_read16(dev, 0x007A) | 0x0058));
1149 if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1150 b43_radio_write16(dev, 0x51, 0x37);
1151 b43_radio_write16(dev, 0x52, 0x70);
1152 b43_radio_write16(dev, 0x53, 0xB3);
1153 b43_radio_write16(dev, 0x54, 0x9B);
1154 b43_radio_write16(dev, 0x5A, 0x88);
1155 b43_radio_write16(dev, 0x5B, 0x88);
1156 b43_radio_write16(dev, 0x5D, 0x88);
1157 b43_radio_write16(dev, 0x5E, 0x88);
1158 b43_radio_write16(dev, 0x7D, 0x88);
1159 b43_hf_write(dev, b43_hf_read(dev)
1160 | B43_HF_TSSIRPSMW);
1161 }
1162 B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7); /* We had code for these revs here... */
1163 if (phy->radio_rev == 8) {
1164 b43_radio_write16(dev, 0x51, 0);
1165 b43_radio_write16(dev, 0x52, 0x40);
1166 b43_radio_write16(dev, 0x53, 0xB7);
1167 b43_radio_write16(dev, 0x54, 0x98);
1168 b43_radio_write16(dev, 0x5A, 0x88);
1169 b43_radio_write16(dev, 0x5B, 0x6B);
1170 b43_radio_write16(dev, 0x5C, 0x0F);
1171 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_ALTIQ) {
1172 b43_radio_write16(dev, 0x5D, 0xFA);
1173 b43_radio_write16(dev, 0x5E, 0xD8);
1174 } else {
1175 b43_radio_write16(dev, 0x5D, 0xF5);
1176 b43_radio_write16(dev, 0x5E, 0xB8);
1177 }
1178 b43_radio_write16(dev, 0x0073, 0x0003);
1179 b43_radio_write16(dev, 0x007D, 0x00A8);
1180 b43_radio_write16(dev, 0x007C, 0x0001);
1181 b43_radio_write16(dev, 0x007E, 0x0008);
1182 }
1183 val = 0x1E1F;
1184 for (offset = 0x0088; offset < 0x0098; offset++) {
1185 b43_phy_write(dev, offset, val);
1186 val -= 0x0202;
1187 }
1188 val = 0x3E3F;
1189 for (offset = 0x0098; offset < 0x00A8; offset++) {
1190 b43_phy_write(dev, offset, val);
1191 val -= 0x0202;
1192 }
1193 val = 0x2120;
1194 for (offset = 0x00A8; offset < 0x00C8; offset++) {
1195 b43_phy_write(dev, offset, (val & 0x3F3F));
1196 val += 0x0202;
1197 }
1198 if (phy->type == B43_PHYTYPE_G) {
1199 b43_radio_write16(dev, 0x007A,
1200 b43_radio_read16(dev, 0x007A) | 0x0020);
1201 b43_radio_write16(dev, 0x0051,
1202 b43_radio_read16(dev, 0x0051) | 0x0004);
1203 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x0100);
1204 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x2000);
1205 b43_phy_write(dev, 0x5B, 0);
1206 b43_phy_write(dev, 0x5C, 0);
1207 }
1208
1209 old_channel = phy->channel;
1210 if (old_channel >= 8)
1211 b43_radio_selectchannel(dev, 1, 0);
1212 else
1213 b43_radio_selectchannel(dev, 13, 0);
1214
1215 b43_radio_write16(dev, 0x0050, 0x0020);
1216 b43_radio_write16(dev, 0x0050, 0x0023);
1217 udelay(40);
1218 if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1219 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1220 | 0x0002));
1221 b43_radio_write16(dev, 0x50, 0x20);
1222 }
1223 if (phy->radio_rev <= 2) {
1224 b43_radio_write16(dev, 0x7C, 0x20);
1225 b43_radio_write16(dev, 0x5A, 0x70);
1226 b43_radio_write16(dev, 0x5B, 0x7B);
1227 b43_radio_write16(dev, 0x5C, 0xB0);
1228 }
1229 b43_radio_write16(dev, 0x007A,
1230 (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1231
1232 b43_radio_selectchannel(dev, old_channel, 0);
1233
1234 b43_phy_write(dev, 0x0014, 0x0200);
1235 if (phy->radio_rev >= 6)
1236 b43_phy_write(dev, 0x2A, 0x88C2);
1237 else
1238 b43_phy_write(dev, 0x2A, 0x8AC0);
1239 b43_phy_write(dev, 0x0038, 0x0668);
1240 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1241 if (phy->radio_rev <= 5) {
1242 b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
1243 & 0xFF80) | 0x0003);
1244 }
1245 if (phy->radio_rev <= 2)
1246 b43_radio_write16(dev, 0x005D, 0x000D);
1247
1248 if (phy->analog == 4) {
1249 b43_write16(dev, 0x3E4, 9);
1250 b43_phy_write(dev, 0x61, b43_phy_read(dev, 0x61)
1251 & 0x0FFF);
1252 } else {
1253 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1254 | 0x0004);
1255 }
1256 if (phy->type == B43_PHYTYPE_B) {
1257 b43_write16(dev, 0x03E6, 0x8140);
1258 b43_phy_write(dev, 0x0016, 0x0410);
1259 b43_phy_write(dev, 0x0017, 0x0820);
1260 b43_phy_write(dev, 0x0062, 0x0007);
1261 b43_radio_init2050(dev);
1262 b43_lo_g_measure(dev);
1263 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
1264 b43_calc_nrssi_slope(dev);
1265 b43_calc_nrssi_threshold(dev);
1266 }
1267 b43_phy_init_pctl(dev);
1268 } else if (phy->type == B43_PHYTYPE_G)
1269 b43_write16(dev, 0x03E6, 0x0);
1270 }
1271
1272 static void b43_calc_loopback_gain(struct b43_wldev *dev)
1273 {
1274 struct b43_phy *phy = &dev->phy;
1275 u16 backup_phy[16] = { 0 };
1276 u16 backup_radio[3];
1277 u16 backup_bband;
1278 u16 i, j, loop_i_max;
1279 u16 trsw_rx;
1280 u16 loop1_outer_done, loop1_inner_done;
1281
1282 backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1283 backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1284 backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1285 backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1286 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1287 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1288 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1289 }
1290 backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1291 backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1292 backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1293 backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1294 backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1295 backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1296 backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1297 backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1298 backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1299 backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1300 backup_bband = phy->bbatt.att;
1301 backup_radio[0] = b43_radio_read16(dev, 0x52);
1302 backup_radio[1] = b43_radio_read16(dev, 0x43);
1303 backup_radio[2] = b43_radio_read16(dev, 0x7A);
1304
1305 b43_phy_write(dev, B43_PHY_CRS0,
1306 b43_phy_read(dev, B43_PHY_CRS0) & 0x3FFF);
1307 b43_phy_write(dev, B43_PHY_CCKBBANDCFG,
1308 b43_phy_read(dev, B43_PHY_CCKBBANDCFG) | 0x8000);
1309 b43_phy_write(dev, B43_PHY_RFOVER,
1310 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0002);
1311 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1312 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFD);
1313 b43_phy_write(dev, B43_PHY_RFOVER,
1314 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0001);
1315 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1316 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xFFFE);
1317 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1318 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1319 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0001);
1320 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1321 b43_phy_read(dev,
1322 B43_PHY_ANALOGOVERVAL) & 0xFFFE);
1323 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1324 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0002);
1325 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1326 b43_phy_read(dev,
1327 B43_PHY_ANALOGOVERVAL) & 0xFFFD);
1328 }
1329 b43_phy_write(dev, B43_PHY_RFOVER,
1330 b43_phy_read(dev, B43_PHY_RFOVER) | 0x000C);
1331 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1332 b43_phy_read(dev, B43_PHY_RFOVERVAL) | 0x000C);
1333 b43_phy_write(dev, B43_PHY_RFOVER,
1334 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0030);
1335 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1336 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1337 & 0xFFCF) | 0x10);
1338
1339 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1340 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1341 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1342
1343 b43_phy_write(dev, B43_PHY_CCK(0x0A),
1344 b43_phy_read(dev, B43_PHY_CCK(0x0A)) | 0x2000);
1345 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1346 b43_phy_write(dev, B43_PHY_ANALOGOVER,
1347 b43_phy_read(dev, B43_PHY_ANALOGOVER) | 0x0004);
1348 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1349 b43_phy_read(dev,
1350 B43_PHY_ANALOGOVERVAL) & 0xFFFB);
1351 }
1352 b43_phy_write(dev, B43_PHY_CCK(0x03),
1353 (b43_phy_read(dev, B43_PHY_CCK(0x03))
1354 & 0xFF9F) | 0x40);
1355
1356 if (phy->radio_rev == 8) {
1357 b43_radio_write16(dev, 0x43, 0x000F);
1358 } else {
1359 b43_radio_write16(dev, 0x52, 0);
1360 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1361 & 0xFFF0) | 0x9);
1362 }
1363 b43_phy_set_baseband_attenuation(dev, 11);
1364
1365 if (phy->rev >= 3)
1366 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1367 else
1368 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1369 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1370
1371 b43_phy_write(dev, B43_PHY_CCK(0x2B),
1372 (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1373 & 0xFFC0) | 0x01);
1374 b43_phy_write(dev, B43_PHY_CCK(0x2B),
1375 (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1376 & 0xC0FF) | 0x800);
1377
1378 b43_phy_write(dev, B43_PHY_RFOVER,
1379 b43_phy_read(dev, B43_PHY_RFOVER) | 0x0100);
1380 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1381 b43_phy_read(dev, B43_PHY_RFOVERVAL) & 0xCFFF);
1382
1383 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) {
1384 if (phy->rev >= 7) {
1385 b43_phy_write(dev, B43_PHY_RFOVER,
1386 b43_phy_read(dev, B43_PHY_RFOVER)
1387 | 0x0800);
1388 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1389 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1390 | 0x8000);
1391 }
1392 }
1393 b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1394 & 0x00F7);
1395
1396 j = 0;
1397 loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1398 for (i = 0; i < loop_i_max; i++) {
1399 for (j = 0; j < 16; j++) {
1400 b43_radio_write16(dev, 0x43, i);
1401 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1402 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1403 & 0xF0FF) | (j << 8));
1404 b43_phy_write(dev, B43_PHY_PGACTL,
1405 (b43_phy_read(dev, B43_PHY_PGACTL)
1406 & 0x0FFF) | 0xA000);
1407 b43_phy_write(dev, B43_PHY_PGACTL,
1408 b43_phy_read(dev, B43_PHY_PGACTL)
1409 | 0xF000);
1410 udelay(20);
1411 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1412 goto exit_loop1;
1413 }
1414 }
1415 exit_loop1:
1416 loop1_outer_done = i;
1417 loop1_inner_done = j;
1418 if (j >= 8) {
1419 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1420 b43_phy_read(dev, B43_PHY_RFOVERVAL)
1421 | 0x30);
1422 trsw_rx = 0x1B;
1423 for (j = j - 8; j < 16; j++) {
1424 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1425 (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1426 & 0xF0FF) | (j << 8));
1427 b43_phy_write(dev, B43_PHY_PGACTL,
1428 (b43_phy_read(dev, B43_PHY_PGACTL)
1429 & 0x0FFF) | 0xA000);
1430 b43_phy_write(dev, B43_PHY_PGACTL,
1431 b43_phy_read(dev, B43_PHY_PGACTL)
1432 | 0xF000);
1433 udelay(20);
1434 trsw_rx -= 3;
1435 if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1436 goto exit_loop2;
1437 }
1438 } else
1439 trsw_rx = 0x18;
1440 exit_loop2:
1441
1442 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1443 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1444 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1445 }
1446 b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
1447 b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
1448 b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
1449 b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
1450 b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
1451 b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1452 b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1453 b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
1454 b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1455
1456 b43_phy_set_baseband_attenuation(dev, backup_bband);
1457
1458 b43_radio_write16(dev, 0x52, backup_radio[0]);
1459 b43_radio_write16(dev, 0x43, backup_radio[1]);
1460 b43_radio_write16(dev, 0x7A, backup_radio[2]);
1461
1462 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1463 udelay(10);
1464 b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1465 b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1466 b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1467 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1468
1469 phy->max_lb_gain =
1470 ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1471 phy->trsw_rx_gain = trsw_rx * 2;
1472 }
1473
1474 static void b43_phy_initg(struct b43_wldev *dev)
1475 {
1476 struct b43_phy *phy = &dev->phy;
1477 u16 tmp;
1478
1479 if (phy->rev == 1)
1480 b43_phy_initb5(dev);
1481 else
1482 b43_phy_initb6(dev);
1483
1484 if (phy->rev >= 2 || phy->gmode)
1485 b43_phy_inita(dev);
1486
1487 if (phy->rev >= 2) {
1488 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
1489 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
1490 }
1491 if (phy->rev == 2) {
1492 b43_phy_write(dev, B43_PHY_RFOVER, 0);
1493 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1494 }
1495 if (phy->rev > 5) {
1496 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
1497 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
1498 }
1499 if (phy->gmode || phy->rev >= 2) {
1500 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
1501 tmp &= B43_PHYVER_VERSION;
1502 if (tmp == 3 || tmp == 5) {
1503 b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
1504 b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
1505 }
1506 if (tmp == 5) {
1507 b43_phy_write(dev, B43_PHY_OFDM(0xCC),
1508 (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
1509 & 0x00FF) | 0x1F00);
1510 }
1511 }
1512 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
1513 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
1514 if (phy->radio_rev == 8) {
1515 b43_phy_write(dev, B43_PHY_EXTG(0x01),
1516 b43_phy_read(dev, B43_PHY_EXTG(0x01))
1517 | 0x80);
1518 b43_phy_write(dev, B43_PHY_OFDM(0x3E),
1519 b43_phy_read(dev, B43_PHY_OFDM(0x3E))
1520 | 0x4);
1521 }
1522 if (has_loopback_gain(phy))
1523 b43_calc_loopback_gain(dev);
1524
1525 if (phy->radio_rev != 8) {
1526 if (phy->initval == 0xFFFF)
1527 phy->initval = b43_radio_init2050(dev);
1528 else
1529 b43_radio_write16(dev, 0x0078, phy->initval);
1530 }
1531 if (phy->lo_control->tx_bias == 0xFF) {
1532 b43_lo_g_measure(dev);
1533 } else {
1534 if (has_tx_magnification(phy)) {
1535 b43_radio_write16(dev, 0x52,
1536 (b43_radio_read16(dev, 0x52) & 0xFF00)
1537 | phy->lo_control->tx_bias | phy->
1538 lo_control->tx_magn);
1539 } else {
1540 b43_radio_write16(dev, 0x52,
1541 (b43_radio_read16(dev, 0x52) & 0xFFF0)
1542 | phy->lo_control->tx_bias);
1543 }
1544 if (phy->rev >= 6) {
1545 b43_phy_write(dev, B43_PHY_CCK(0x36),
1546 (b43_phy_read(dev, B43_PHY_CCK(0x36))
1547 & 0x0FFF) | (phy->lo_control->
1548 tx_bias << 12));
1549 }
1550 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
1551 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
1552 else
1553 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
1554 if (phy->rev < 2)
1555 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
1556 else
1557 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
1558 }
1559 if (phy->gmode || phy->rev >= 2) {
1560 b43_lo_g_adjust(dev);
1561 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
1562 }
1563
1564 if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
1565 /* The specs state to update the NRSSI LT with
1566 * the value 0x7FFFFFFF here. I think that is some weird
1567 * compiler optimization in the original driver.
1568 * Essentially, what we do here is resetting all NRSSI LT
1569 * entries to -32 (see the limit_value() in nrssi_hw_update())
1570 */
1571 b43_nrssi_hw_update(dev, 0xFFFF); //FIXME?
1572 b43_calc_nrssi_threshold(dev);
1573 } else if (phy->gmode || phy->rev >= 2) {
1574 if (phy->nrssi[0] == -1000) {
1575 B43_WARN_ON(phy->nrssi[1] != -1000);
1576 b43_calc_nrssi_slope(dev);
1577 } else
1578 b43_calc_nrssi_threshold(dev);
1579 }
1580 if (phy->radio_rev == 8)
1581 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
1582 b43_phy_init_pctl(dev);
1583 /* FIXME: The spec says in the following if, the 0 should be replaced
1584 'if OFDM may not be used in the current locale'
1585 but OFDM is legal everywhere */
1586 if ((dev->dev->bus->chip_id == 0x4306
1587 && dev->dev->bus->chip_package == 2) || 0) {
1588 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
1589 & 0xBFFF);
1590 b43_phy_write(dev, B43_PHY_OFDM(0xC3),
1591 b43_phy_read(dev, B43_PHY_OFDM(0xC3))
1592 & 0x7FFF);
1593 }
1594 }
1595
1596 /* Set the baseband attenuation value on chip. */
1597 void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
1598 u16 baseband_attenuation)
1599 {
1600 struct b43_phy *phy = &dev->phy;
1601
1602 if (phy->analog == 0) {
1603 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
1604 & 0xFFF0) |
1605 baseband_attenuation);
1606 } else if (phy->analog > 1) {
1607 b43_phy_write(dev, B43_PHY_DACCTL,
1608 (b43_phy_read(dev, B43_PHY_DACCTL)
1609 & 0xFFC3) | (baseband_attenuation << 2));
1610 } else {
1611 b43_phy_write(dev, B43_PHY_DACCTL,
1612 (b43_phy_read(dev, B43_PHY_DACCTL)
1613 & 0xFF87) | (baseband_attenuation << 3));
1614 }
1615 }
1616
1617 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1618 * This function converts a TSSI value to dBm in Q5.2
1619 */
1620 static s8 b43_phy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
1621 {
1622 struct b43_phy *phy = &dev->phy;
1623 s8 dbm = 0;
1624 s32 tmp;
1625
1626 tmp = (phy->tgt_idle_tssi - phy->cur_idle_tssi + tssi);
1627
1628 switch (phy->type) {
1629 case B43_PHYTYPE_A:
1630 tmp += 0x80;
1631 tmp = limit_value(tmp, 0x00, 0xFF);
1632 dbm = phy->tssi2dbm[tmp];
1633 //TODO: There's a FIXME on the specs
1634 break;
1635 case B43_PHYTYPE_B:
1636 case B43_PHYTYPE_G:
1637 tmp = limit_value(tmp, 0x00, 0x3F);
1638 dbm = phy->tssi2dbm[tmp];
1639 break;
1640 default:
1641 B43_WARN_ON(1);
1642 }
1643
1644 return dbm;
1645 }
1646
1647 void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
1648 int *_bbatt, int *_rfatt)
1649 {
1650 int rfatt = *_rfatt;
1651 int bbatt = *_bbatt;
1652 struct b43_txpower_lo_control *lo = dev->phy.lo_control;
1653
1654 /* Get baseband and radio attenuation values into their permitted ranges.
1655 * Radio attenuation affects power level 4 times as much as baseband. */
1656
1657 /* Range constants */
1658 const int rf_min = lo->rfatt_list.min_val;
1659 const int rf_max = lo->rfatt_list.max_val;
1660 const int bb_min = lo->bbatt_list.min_val;
1661 const int bb_max = lo->bbatt_list.max_val;
1662
1663 while (1) {
1664 if (rfatt > rf_max && bbatt > bb_max - 4)
1665 break; /* Can not get it into ranges */
1666 if (rfatt < rf_min && bbatt < bb_min + 4)
1667 break; /* Can not get it into ranges */
1668 if (bbatt > bb_max && rfatt > rf_max - 1)
1669 break; /* Can not get it into ranges */
1670 if (bbatt < bb_min && rfatt < rf_min + 1)
1671 break; /* Can not get it into ranges */
1672
1673 if (bbatt > bb_max) {
1674 bbatt -= 4;
1675 rfatt += 1;
1676 continue;
1677 }
1678 if (bbatt < bb_min) {
1679 bbatt += 4;
1680 rfatt -= 1;
1681 continue;
1682 }
1683 if (rfatt > rf_max) {
1684 rfatt -= 1;
1685 bbatt += 4;
1686 continue;
1687 }
1688 if (rfatt < rf_min) {
1689 rfatt += 1;
1690 bbatt -= 4;
1691 continue;
1692 }
1693 break;
1694 }
1695
1696 *_rfatt = limit_value(rfatt, rf_min, rf_max);
1697 *_bbatt = limit_value(bbatt, bb_min, bb_max);
1698 }
1699
1700 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1701 void b43_phy_xmitpower(struct b43_wldev *dev)
1702 {
1703 struct ssb_bus *bus = dev->dev->bus;
1704 struct b43_phy *phy = &dev->phy;
1705
1706 if (phy->cur_idle_tssi == 0)
1707 return;
1708 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1709 (bus->boardinfo.type == SSB_BOARD_BU4306))
1710 return;
1711 #ifdef CONFIG_B43_DEBUG
1712 if (phy->manual_txpower_control)
1713 return;
1714 #endif
1715
1716 switch (phy->type) {
1717 case B43_PHYTYPE_A:{
1718
1719 //TODO: Nothing for A PHYs yet :-/
1720
1721 break;
1722 }
1723 case B43_PHYTYPE_B:
1724 case B43_PHYTYPE_G:{
1725 u16 tmp;
1726 s8 v0, v1, v2, v3;
1727 s8 average;
1728 int max_pwr;
1729 int desired_pwr, estimated_pwr, pwr_adjust;
1730 int rfatt_delta, bbatt_delta;
1731 int rfatt, bbatt;
1732 u8 tx_control;
1733 unsigned long phylock_flags;
1734
1735 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x0058);
1736 v0 = (s8) (tmp & 0x00FF);
1737 v1 = (s8) ((tmp & 0xFF00) >> 8);
1738 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x005A);
1739 v2 = (s8) (tmp & 0x00FF);
1740 v3 = (s8) ((tmp & 0xFF00) >> 8);
1741 tmp = 0;
1742
1743 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
1744 || v3 == 0x7F) {
1745 tmp =
1746 b43_shm_read16(dev, B43_SHM_SHARED, 0x0070);
1747 v0 = (s8) (tmp & 0x00FF);
1748 v1 = (s8) ((tmp & 0xFF00) >> 8);
1749 tmp =
1750 b43_shm_read16(dev, B43_SHM_SHARED, 0x0072);
1751 v2 = (s8) (tmp & 0x00FF);
1752 v3 = (s8) ((tmp & 0xFF00) >> 8);
1753 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F
1754 || v3 == 0x7F)
1755 return;
1756 v0 = (v0 + 0x20) & 0x3F;
1757 v1 = (v1 + 0x20) & 0x3F;
1758 v2 = (v2 + 0x20) & 0x3F;
1759 v3 = (v3 + 0x20) & 0x3F;
1760 tmp = 1;
1761 }
1762 b43_shm_clear_tssi(dev);
1763
1764 average = (v0 + v1 + v2 + v3 + 2) / 4;
1765
1766 if (tmp
1767 && (b43_shm_read16(dev, B43_SHM_SHARED, 0x005E) &
1768 0x8))
1769 average -= 13;
1770
1771 estimated_pwr =
1772 b43_phy_estimate_power_out(dev, average);
1773
1774 max_pwr = dev->dev->bus->sprom.maxpwr_bg;
1775 if ((dev->dev->bus->sprom.boardflags_lo
1776 & B43_BFL_PACTRL) && (phy->type == B43_PHYTYPE_G))
1777 max_pwr -= 0x3;
1778 if (unlikely(max_pwr <= 0)) {
1779 b43warn(dev->wl,
1780 "Invalid max-TX-power value in SPROM.\n");
1781 max_pwr = 60; /* fake it */
1782 dev->dev->bus->sprom.maxpwr_bg = max_pwr;
1783 }
1784
1785 /*TODO:
1786 max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
1787 where REG is the max power as per the regulatory domain
1788 */
1789
1790 /* Get desired power (in Q5.2) */
1791 desired_pwr = INT_TO_Q52(phy->power_level);
1792 /* And limit it. max_pwr already is Q5.2 */
1793 desired_pwr = limit_value(desired_pwr, 0, max_pwr);
1794 if (b43_debug(dev, B43_DBG_XMITPOWER)) {
1795 b43dbg(dev->wl,
1796 "Current TX power output: " Q52_FMT
1797 " dBm, " "Desired TX power output: "
1798 Q52_FMT " dBm\n", Q52_ARG(estimated_pwr),
1799 Q52_ARG(desired_pwr));
1800 }
1801
1802 /* Calculate the adjustment delta. */
1803 pwr_adjust = desired_pwr - estimated_pwr;
1804
1805 /* RF attenuation delta. */
1806 rfatt_delta = ((pwr_adjust + 7) / 8);
1807 /* Lower attenuation => Bigger power output. Negate it. */
1808 rfatt_delta = -rfatt_delta;
1809
1810 /* Baseband attenuation delta. */
1811 bbatt_delta = pwr_adjust / 2;
1812 /* Lower attenuation => Bigger power output. Negate it. */
1813 bbatt_delta = -bbatt_delta;
1814 /* RF att affects power level 4 times as much as
1815 * Baseband attennuation. Subtract it. */
1816 bbatt_delta -= 4 * rfatt_delta;
1817
1818 /* So do we finally need to adjust something? */
1819 if ((rfatt_delta == 0) && (bbatt_delta == 0)) {
1820 b43_lo_g_ctl_mark_cur_used(dev);
1821 return;
1822 }
1823
1824 /* Calculate the new attenuation values. */
1825 bbatt = phy->bbatt.att;
1826 bbatt += bbatt_delta;
1827 rfatt = phy->rfatt.att;
1828 rfatt += rfatt_delta;
1829
1830 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
1831 tx_control = phy->tx_control;
1832 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
1833 if (rfatt <= 1) {
1834 if (tx_control == 0) {
1835 tx_control =
1836 B43_TXCTL_PA2DB |
1837 B43_TXCTL_TXMIX;
1838 rfatt += 2;
1839 bbatt += 2;
1840 } else if (dev->dev->bus->sprom.
1841 boardflags_lo &
1842 B43_BFL_PACTRL) {
1843 bbatt += 4 * (rfatt - 2);
1844 rfatt = 2;
1845 }
1846 } else if (rfatt > 4 && tx_control) {
1847 tx_control = 0;
1848 if (bbatt < 3) {
1849 rfatt -= 3;
1850 bbatt += 2;
1851 } else {
1852 rfatt -= 2;
1853 bbatt -= 2;
1854 }
1855 }
1856 }
1857 /* Save the control values */
1858 phy->tx_control = tx_control;
1859 b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
1860 phy->rfatt.att = rfatt;
1861 phy->bbatt.att = bbatt;
1862
1863 /* Adjust the hardware */
1864 b43_phy_lock(dev, phylock_flags);
1865 b43_radio_lock(dev);
1866 b43_set_txpower_g(dev, &phy->bbatt, &phy->rfatt,
1867 phy->tx_control);
1868 b43_lo_g_ctl_mark_cur_used(dev);
1869 b43_radio_unlock(dev);
1870 b43_phy_unlock(dev, phylock_flags);
1871 break;
1872 }
1873 default:
1874 B43_WARN_ON(1);
1875 }
1876 }
1877
1878 static inline s32 b43_tssi2dbm_ad(s32 num, s32 den)
1879 {
1880 if (num < 0)
1881 return num / den;
1882 else
1883 return (num + den / 2) / den;
1884 }
1885
1886 static inline
1887 s8 b43_tssi2dbm_entry(s8 entry[], u8 index, s16 pab0, s16 pab1, s16 pab2)
1888 {
1889 s32 m1, m2, f = 256, q, delta;
1890 s8 i = 0;
1891
1892 m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
1893 m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
1894 do {
1895 if (i > 15)
1896 return -EINVAL;
1897 q = b43_tssi2dbm_ad(f * 4096 -
1898 b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
1899 delta = abs(q - f);
1900 f = q;
1901 i++;
1902 } while (delta >= 2);
1903 entry[index] = limit_value(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
1904 return 0;
1905 }
1906
1907 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
1908 int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev)
1909 {
1910 struct b43_phy *phy = &dev->phy;
1911 s16 pab0, pab1, pab2;
1912 u8 idx;
1913 s8 *dyn_tssi2dbm;
1914
1915 if (phy->type == B43_PHYTYPE_A) {
1916 pab0 = (s16) (dev->dev->bus->sprom.pa1b0);
1917 pab1 = (s16) (dev->dev->bus->sprom.pa1b1);
1918 pab2 = (s16) (dev->dev->bus->sprom.pa1b2);
1919 } else {
1920 pab0 = (s16) (dev->dev->bus->sprom.pa0b0);
1921 pab1 = (s16) (dev->dev->bus->sprom.pa0b1);
1922 pab2 = (s16) (dev->dev->bus->sprom.pa0b2);
1923 }
1924
1925 if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
1926 phy->tgt_idle_tssi = 0x34;
1927 phy->tssi2dbm = b43_tssi2dbm_b_table;
1928 return 0;
1929 }
1930
1931 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
1932 pab0 != -1 && pab1 != -1 && pab2 != -1) {
1933 /* The pabX values are set in SPROM. Use them. */
1934 if (phy->type == B43_PHYTYPE_A) {
1935 if ((s8) dev->dev->bus->sprom.itssi_a != 0 &&
1936 (s8) dev->dev->bus->sprom.itssi_a != -1)
1937 phy->tgt_idle_tssi =
1938 (s8) (dev->dev->bus->sprom.itssi_a);
1939 else
1940 phy->tgt_idle_tssi = 62;
1941 } else {
1942 if ((s8) dev->dev->bus->sprom.itssi_bg != 0 &&
1943 (s8) dev->dev->bus->sprom.itssi_bg != -1)
1944 phy->tgt_idle_tssi =
1945 (s8) (dev->dev->bus->sprom.itssi_bg);
1946 else
1947 phy->tgt_idle_tssi = 62;
1948 }
1949 dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
1950 if (dyn_tssi2dbm == NULL) {
1951 b43err(dev->wl, "Could not allocate memory "
1952 "for tssi2dbm table\n");
1953 return -ENOMEM;
1954 }
1955 for (idx = 0; idx < 64; idx++)
1956 if (b43_tssi2dbm_entry
1957 (dyn_tssi2dbm, idx, pab0, pab1, pab2)) {
1958 phy->tssi2dbm = NULL;
1959 b43err(dev->wl, "Could not generate "
1960 "tssi2dBm table\n");
1961 kfree(dyn_tssi2dbm);
1962 return -ENODEV;
1963 }
1964 phy->tssi2dbm = dyn_tssi2dbm;
1965 phy->dyn_tssi_tbl = 1;
1966 } else {
1967 /* pabX values not set in SPROM. */
1968 switch (phy->type) {
1969 case B43_PHYTYPE_A:
1970 /* APHY needs a generated table. */
1971 phy->tssi2dbm = NULL;
1972 b43err(dev->wl, "Could not generate tssi2dBm "
1973 "table (wrong SPROM info)!\n");
1974 return -ENODEV;
1975 case B43_PHYTYPE_B:
1976 phy->tgt_idle_tssi = 0x34;
1977 phy->tssi2dbm = b43_tssi2dbm_b_table;
1978 break;
1979 case B43_PHYTYPE_G:
1980 phy->tgt_idle_tssi = 0x34;
1981 phy->tssi2dbm = b43_tssi2dbm_g_table;
1982 break;
1983 }
1984 }
1985
1986 return 0;
1987 }
1988
1989 int b43_phy_init(struct b43_wldev *dev)
1990 {
1991 struct b43_phy *phy = &dev->phy;
1992 bool unsupported = 0;
1993 int err = 0;
1994
1995 switch (phy->type) {
1996 case B43_PHYTYPE_A:
1997 if (phy->rev == 2 || phy->rev == 3)
1998 b43_phy_inita(dev);
1999 else
2000 unsupported = 1;
2001 break;
2002 case B43_PHYTYPE_B:
2003 switch (phy->rev) {
2004 case 2:
2005 b43_phy_initb2(dev);
2006 break;
2007 case 4:
2008 b43_phy_initb4(dev);
2009 break;
2010 case 5:
2011 b43_phy_initb5(dev);
2012 break;
2013 case 6:
2014 b43_phy_initb6(dev);
2015 break;
2016 default:
2017 unsupported = 1;
2018 }
2019 break;
2020 case B43_PHYTYPE_G:
2021 b43_phy_initg(dev);
2022 break;
2023 case B43_PHYTYPE_N:
2024 err = b43_phy_initn(dev);
2025 break;
2026 default:
2027 unsupported = 1;
2028 }
2029 if (unsupported)
2030 b43err(dev->wl, "Unknown PHYTYPE found\n");
2031
2032 return err;
2033 }
2034
2035 void b43_set_rx_antenna(struct b43_wldev *dev, int antenna)
2036 {
2037 struct b43_phy *phy = &dev->phy;
2038 u32 hf;
2039 u16 tmp;
2040 int autodiv = 0;
2041
2042 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2043 autodiv = 1;
2044
2045 hf = b43_hf_read(dev);
2046 hf &= ~B43_HF_ANTDIVHELP;
2047 b43_hf_write(dev, hf);
2048
2049 switch (phy->type) {
2050 case B43_PHYTYPE_A:
2051 case B43_PHYTYPE_G:
2052 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
2053 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2054 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2055 << B43_PHY_BBANDCFG_RXANT_SHIFT;
2056 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
2057
2058 if (autodiv) {
2059 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2060 if (antenna == B43_ANTENNA_AUTO0)
2061 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2062 else
2063 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2064 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2065 }
2066 if (phy->type == B43_PHYTYPE_G) {
2067 tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2068 if (autodiv)
2069 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2070 else
2071 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2072 b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2073 if (phy->rev >= 2) {
2074 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2075 tmp |= B43_PHY_OFDM61_10;
2076 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2077
2078 tmp =
2079 b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
2080 tmp = (tmp & 0xFF00) | 0x15;
2081 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
2082 tmp);
2083
2084 if (phy->rev == 2) {
2085 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2086 8);
2087 } else {
2088 tmp =
2089 b43_phy_read(dev,
2090 B43_PHY_ADIVRELATED);
2091 tmp = (tmp & 0xFF00) | 8;
2092 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2093 tmp);
2094 }
2095 }
2096 if (phy->rev >= 6)
2097 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2098 } else {
2099 if (phy->rev < 3) {
2100 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2101 tmp = (tmp & 0xFF00) | 0x24;
2102 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2103 } else {
2104 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2105 tmp |= 0x10;
2106 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2107 if (phy->analog == 3) {
2108 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2109 0x1D);
2110 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2111 8);
2112 } else {
2113 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
2114 0x3A);
2115 tmp =
2116 b43_phy_read(dev,
2117 B43_PHY_ADIVRELATED);
2118 tmp = (tmp & 0xFF00) | 8;
2119 b43_phy_write(dev, B43_PHY_ADIVRELATED,
2120 tmp);
2121 }
2122 }
2123 }
2124 break;
2125 case B43_PHYTYPE_B:
2126 tmp = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
2127 tmp &= ~B43_PHY_BBANDCFG_RXANT;
2128 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2129 << B43_PHY_BBANDCFG_RXANT_SHIFT;
2130 b43_phy_write(dev, B43_PHY_CCKBBANDCFG, tmp);
2131 break;
2132 default:
2133 B43_WARN_ON(1);
2134 }
2135
2136 hf |= B43_HF_ANTDIVHELP;
2137 b43_hf_write(dev, hf);
2138 }
2139
2140 /* Get the freq, as it has to be written to the device. */
2141 static inline u16 channel2freq_bg(u8 channel)
2142 {
2143 B43_WARN_ON(!(channel >= 1 && channel <= 14));
2144
2145 return b43_radio_channel_codes_bg[channel - 1];
2146 }
2147
2148 /* Get the freq, as it has to be written to the device. */
2149 static inline u16 channel2freq_a(u8 channel)
2150 {
2151 B43_WARN_ON(channel > 200);
2152
2153 return (5000 + 5 * channel);
2154 }
2155
2156 void b43_radio_lock(struct b43_wldev *dev)
2157 {
2158 u32 macctl;
2159
2160 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2161 macctl |= B43_MACCTL_RADIOLOCK;
2162 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2163 /* Commit the write and wait for the device
2164 * to exit any radio register access. */
2165 b43_read32(dev, B43_MMIO_MACCTL);
2166 udelay(10);
2167 }
2168
2169 void b43_radio_unlock(struct b43_wldev *dev)
2170 {
2171 u32 macctl;
2172
2173 /* Commit any write */
2174 b43_read16(dev, B43_MMIO_PHY_VER);
2175 /* unlock */
2176 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2177 macctl &= ~B43_MACCTL_RADIOLOCK;
2178 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2179 }
2180
2181 u16 b43_radio_read16(struct b43_wldev *dev, u16 offset)
2182 {
2183 struct b43_phy *phy = &dev->phy;
2184
2185 /* Offset 1 is a 32-bit register. */
2186 B43_WARN_ON(offset == 1);
2187
2188 switch (phy->type) {
2189 case B43_PHYTYPE_A:
2190 offset |= 0x40;
2191 break;
2192 case B43_PHYTYPE_B:
2193 if (phy->radio_ver == 0x2053) {
2194 if (offset < 0x70)
2195 offset += 0x80;
2196 else if (offset < 0x80)
2197 offset += 0x70;
2198 } else if (phy->radio_ver == 0x2050) {
2199 offset |= 0x80;
2200 } else
2201 B43_WARN_ON(1);
2202 break;
2203 case B43_PHYTYPE_G:
2204 offset |= 0x80;
2205 break;
2206 case B43_PHYTYPE_N:
2207 offset |= 0x100;
2208 break;
2209 case B43_PHYTYPE_LP:
2210 /* No adjustment required. */
2211 break;
2212 default:
2213 B43_WARN_ON(1);
2214 }
2215
2216 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2217 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2218 }
2219
2220 void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val)
2221 {
2222 /* Offset 1 is a 32-bit register. */
2223 B43_WARN_ON(offset == 1);
2224
2225 b43_write16(dev, B43_MMIO_RADIO_CONTROL, offset);
2226 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, val);
2227 }
2228
2229 static void b43_set_all_gains(struct b43_wldev *dev,
2230 s16 first, s16 second, s16 third)
2231 {
2232 struct b43_phy *phy = &dev->phy;
2233 u16 i;
2234 u16 start = 0x08, end = 0x18;
2235 u16 tmp;
2236 u16 table;
2237
2238 if (phy->rev <= 1) {
2239 start = 0x10;
2240 end = 0x20;
2241 }
2242
2243 table = B43_OFDMTAB_GAINX;
2244 if (phy->rev <= 1)
2245 table = B43_OFDMTAB_GAINX_R1;
2246 for (i = 0; i < 4; i++)
2247 b43_ofdmtab_write16(dev, table, i, first);
2248
2249 for (i = start; i < end; i++)
2250 b43_ofdmtab_write16(dev, table, i, second);
2251
2252 if (third != -1) {
2253 tmp = ((u16) third << 14) | ((u16) third << 6);
2254 b43_phy_write(dev, 0x04A0,
2255 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
2256 b43_phy_write(dev, 0x04A1,
2257 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
2258 b43_phy_write(dev, 0x04A2,
2259 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
2260 }
2261 b43_dummy_transmission(dev);
2262 }
2263
2264 static void b43_set_original_gains(struct b43_wldev *dev)
2265 {
2266 struct b43_phy *phy = &dev->phy;
2267 u16 i, tmp;
2268 u16 table;
2269 u16 start = 0x0008, end = 0x0018;
2270
2271 if (phy->rev <= 1) {
2272 start = 0x0010;
2273 end = 0x0020;
2274 }
2275
2276 table = B43_OFDMTAB_GAINX;
2277 if (phy->rev <= 1)
2278 table = B43_OFDMTAB_GAINX_R1;
2279 for (i = 0; i < 4; i++) {
2280 tmp = (i & 0xFFFC);
2281 tmp |= (i & 0x0001) << 1;
2282 tmp |= (i & 0x0002) >> 1;
2283
2284 b43_ofdmtab_write16(dev, table, i, tmp);
2285 }
2286
2287 for (i = start; i < end; i++)
2288 b43_ofdmtab_write16(dev, table, i, i - start);
2289
2290 b43_phy_write(dev, 0x04A0,
2291 (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
2292 b43_phy_write(dev, 0x04A1,
2293 (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
2294 b43_phy_write(dev, 0x04A2,
2295 (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
2296 b43_dummy_transmission(dev);
2297 }
2298
2299 /* Synthetic PU workaround */
2300 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
2301 {
2302 struct b43_phy *phy = &dev->phy;
2303
2304 might_sleep();
2305
2306 if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
2307 /* We do not need the workaround. */
2308 return;
2309 }
2310
2311 if (channel <= 10) {
2312 b43_write16(dev, B43_MMIO_CHANNEL,
2313 channel2freq_bg(channel + 4));
2314 } else {
2315 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
2316 }
2317 msleep(1);
2318 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2319 }
2320
2321 u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel)
2322 {
2323 struct b43_phy *phy = &dev->phy;
2324 u8 ret = 0;
2325 u16 saved, rssi, temp;
2326 int i, j = 0;
2327
2328 saved = b43_phy_read(dev, 0x0403);
2329 b43_radio_selectchannel(dev, channel, 0);
2330 b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2331 if (phy->aci_hw_rssi)
2332 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2333 else
2334 rssi = saved & 0x3F;
2335 /* clamp temp to signed 5bit */
2336 if (rssi > 32)
2337 rssi -= 64;
2338 for (i = 0; i < 100; i++) {
2339 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2340 if (temp > 32)
2341 temp -= 64;
2342 if (temp < rssi)
2343 j++;
2344 if (j >= 20)
2345 ret = 1;
2346 }
2347 b43_phy_write(dev, 0x0403, saved);
2348
2349 return ret;
2350 }
2351
2352 u8 b43_radio_aci_scan(struct b43_wldev * dev)
2353 {
2354 struct b43_phy *phy = &dev->phy;
2355 u8 ret[13];
2356 unsigned int channel = phy->channel;
2357 unsigned int i, j, start, end;
2358 unsigned long phylock_flags;
2359
2360 if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2361 return 0;
2362
2363 b43_phy_lock(dev, phylock_flags);
2364 b43_radio_lock(dev);
2365 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2366 b43_phy_write(dev, B43_PHY_G_CRS,
2367 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2368 b43_set_all_gains(dev, 3, 8, 1);
2369
2370 start = (channel - 5 > 0) ? channel - 5 : 1;
2371 end = (channel + 5 < 14) ? channel + 5 : 13;
2372
2373 for (i = start; i <= end; i++) {
2374 if (abs(channel - i) > 2)
2375 ret[i - 1] = b43_radio_aci_detect(dev, i);
2376 }
2377 b43_radio_selectchannel(dev, channel, 0);
2378 b43_phy_write(dev, 0x0802,
2379 (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2380 b43_phy_write(dev, 0x0403, b43_phy_read(dev, 0x0403) & 0xFFF8);
2381 b43_phy_write(dev, B43_PHY_G_CRS,
2382 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2383 b43_set_original_gains(dev);
2384 for (i = 0; i < 13; i++) {
2385 if (!ret[i])
2386 continue;
2387 end = (i + 5 < 13) ? i + 5 : 13;
2388 for (j = i; j < end; j++)
2389 ret[j] = 1;
2390 }
2391 b43_radio_unlock(dev);
2392 b43_phy_unlock(dev, phylock_flags);
2393
2394 return ret[channel - 1];
2395 }
2396
2397 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2398 void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
2399 {
2400 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2401 mmiowb();
2402 b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
2403 }
2404
2405 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2406 s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
2407 {
2408 u16 val;
2409
2410 b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
2411 val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
2412
2413 return (s16) val;
2414 }
2415
2416 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2417 void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
2418 {
2419 u16 i;
2420 s16 tmp;
2421
2422 for (i = 0; i < 64; i++) {
2423 tmp = b43_nrssi_hw_read(dev, i);
2424 tmp -= val;
2425 tmp = limit_value(tmp, -32, 31);
2426 b43_nrssi_hw_write(dev, i, tmp);
2427 }
2428 }
2429
2430 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2431 void b43_nrssi_mem_update(struct b43_wldev *dev)
2432 {
2433 struct b43_phy *phy = &dev->phy;
2434 s16 i, delta;
2435 s32 tmp;
2436
2437 delta = 0x1F - phy->nrssi[0];
2438 for (i = 0; i < 64; i++) {
2439 tmp = (i - delta) * phy->nrssislope;
2440 tmp /= 0x10000;
2441 tmp += 0x3A;
2442 tmp = limit_value(tmp, 0, 0x3F);
2443 phy->nrssi_lt[i] = tmp;
2444 }
2445 }
2446
2447 static void b43_calc_nrssi_offset(struct b43_wldev *dev)
2448 {
2449 struct b43_phy *phy = &dev->phy;
2450 u16 backup[20] = { 0 };
2451 s16 v47F;
2452 u16 i;
2453 u16 saved = 0xFFFF;
2454
2455 backup[0] = b43_phy_read(dev, 0x0001);
2456 backup[1] = b43_phy_read(dev, 0x0811);
2457 backup[2] = b43_phy_read(dev, 0x0812);
2458 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2459 backup[3] = b43_phy_read(dev, 0x0814);
2460 backup[4] = b43_phy_read(dev, 0x0815);
2461 }
2462 backup[5] = b43_phy_read(dev, 0x005A);
2463 backup[6] = b43_phy_read(dev, 0x0059);
2464 backup[7] = b43_phy_read(dev, 0x0058);
2465 backup[8] = b43_phy_read(dev, 0x000A);
2466 backup[9] = b43_phy_read(dev, 0x0003);
2467 backup[10] = b43_radio_read16(dev, 0x007A);
2468 backup[11] = b43_radio_read16(dev, 0x0043);
2469
2470 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) & 0x7FFF);
2471 b43_phy_write(dev, 0x0001,
2472 (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
2473 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2474 b43_phy_write(dev, 0x0812,
2475 (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
2476 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
2477 if (phy->rev >= 6) {
2478 backup[12] = b43_phy_read(dev, 0x002E);
2479 backup[13] = b43_phy_read(dev, 0x002F);
2480 backup[14] = b43_phy_read(dev, 0x080F);
2481 backup[15] = b43_phy_read(dev, 0x0810);
2482 backup[16] = b43_phy_read(dev, 0x0801);
2483 backup[17] = b43_phy_read(dev, 0x0060);
2484 backup[18] = b43_phy_read(dev, 0x0014);
2485 backup[19] = b43_phy_read(dev, 0x0478);
2486
2487 b43_phy_write(dev, 0x002E, 0);
2488 b43_phy_write(dev, 0x002F, 0);
2489 b43_phy_write(dev, 0x080F, 0);
2490 b43_phy_write(dev, 0x0810, 0);
2491 b43_phy_write(dev, 0x0478, b43_phy_read(dev, 0x0478) | 0x0100);
2492 b43_phy_write(dev, 0x0801, b43_phy_read(dev, 0x0801) | 0x0040);
2493 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060) | 0x0040);
2494 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014) | 0x0200);
2495 }
2496 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
2497 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
2498 udelay(30);
2499
2500 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2501 if (v47F >= 0x20)
2502 v47F -= 0x40;
2503 if (v47F == 31) {
2504 for (i = 7; i >= 4; i--) {
2505 b43_radio_write16(dev, 0x007B, i);
2506 udelay(20);
2507 v47F =
2508 (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2509 if (v47F >= 0x20)
2510 v47F -= 0x40;
2511 if (v47F < 31 && saved == 0xFFFF)
2512 saved = i;
2513 }
2514 if (saved == 0xFFFF)
2515 saved = 4;
2516 } else {
2517 b43_radio_write16(dev, 0x007A,
2518 b43_radio_read16(dev, 0x007A) & 0x007F);
2519 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2520 b43_phy_write(dev, 0x0814,
2521 b43_phy_read(dev, 0x0814) | 0x0001);
2522 b43_phy_write(dev, 0x0815,
2523 b43_phy_read(dev, 0x0815) & 0xFFFE);
2524 }
2525 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x000C);
2526 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x000C);
2527 b43_phy_write(dev, 0x0811, b43_phy_read(dev, 0x0811) | 0x0030);
2528 b43_phy_write(dev, 0x0812, b43_phy_read(dev, 0x0812) | 0x0030);
2529 b43_phy_write(dev, 0x005A, 0x0480);
2530 b43_phy_write(dev, 0x0059, 0x0810);
2531 b43_phy_write(dev, 0x0058, 0x000D);
2532 if (phy->rev == 0) {
2533 b43_phy_write(dev, 0x0003, 0x0122);
2534 } else {
2535 b43_phy_write(dev, 0x000A, b43_phy_read(dev, 0x000A)
2536 | 0x2000);
2537 }
2538 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2539 b43_phy_write(dev, 0x0814,
2540 b43_phy_read(dev, 0x0814) | 0x0004);
2541 b43_phy_write(dev, 0x0815,
2542 b43_phy_read(dev, 0x0815) & 0xFFFB);
2543 }
2544 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
2545 | 0x0040);
2546 b43_radio_write16(dev, 0x007A,
2547 b43_radio_read16(dev, 0x007A) | 0x000F);
2548 b43_set_all_gains(dev, 3, 0, 1);
2549 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
2550 & 0x00F0) | 0x000F);
2551 udelay(30);
2552 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2553 if (v47F >= 0x20)
2554 v47F -= 0x40;
2555 if (v47F == -32) {
2556 for (i = 0; i < 4; i++) {
2557 b43_radio_write16(dev, 0x007B, i);
2558 udelay(20);
2559 v47F =
2560 (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
2561 0x003F);
2562 if (v47F >= 0x20)
2563 v47F -= 0x40;
2564 if (v47F > -31 && saved == 0xFFFF)
2565 saved = i;
2566 }
2567 if (saved == 0xFFFF)
2568 saved = 3;
2569 } else
2570 saved = 0;
2571 }
2572 b43_radio_write16(dev, 0x007B, saved);
2573
2574 if (phy->rev >= 6) {
2575 b43_phy_write(dev, 0x002E, backup[12]);
2576 b43_phy_write(dev, 0x002F, backup[13]);
2577 b43_phy_write(dev, 0x080F, backup[14]);
2578 b43_phy_write(dev, 0x0810, backup[15]);
2579 }
2580 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2581 b43_phy_write(dev, 0x0814, backup[3]);
2582 b43_phy_write(dev, 0x0815, backup[4]);
2583 }
2584 b43_phy_write(dev, 0x005A, backup[5]);
2585 b43_phy_write(dev, 0x0059, backup[6]);
2586 b43_phy_write(dev, 0x0058, backup[7]);
2587 b43_phy_write(dev, 0x000A, backup[8]);
2588 b43_phy_write(dev, 0x0003, backup[9]);
2589 b43_radio_write16(dev, 0x0043, backup[11]);
2590 b43_radio_write16(dev, 0x007A, backup[10]);
2591 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
2592 b43_phy_write(dev, 0x0429, b43_phy_read(dev, 0x0429) | 0x8000);
2593 b43_set_original_gains(dev);
2594 if (phy->rev >= 6) {
2595 b43_phy_write(dev, 0x0801, backup[16]);
2596 b43_phy_write(dev, 0x0060, backup[17]);
2597 b43_phy_write(dev, 0x0014, backup[18]);
2598 b43_phy_write(dev, 0x0478, backup[19]);
2599 }
2600 b43_phy_write(dev, 0x0001, backup[0]);
2601 b43_phy_write(dev, 0x0812, backup[2]);
2602 b43_phy_write(dev, 0x0811, backup[1]);
2603 }
2604
2605 void b43_calc_nrssi_slope(struct b43_wldev *dev)
2606 {
2607 struct b43_phy *phy = &dev->phy;
2608 u16 backup[18] = { 0 };
2609 u16 tmp;
2610 s16 nrssi0, nrssi1;
2611
2612 switch (phy->type) {
2613 case B43_PHYTYPE_B:
2614 backup[0] = b43_radio_read16(dev, 0x007A);
2615 backup[1] = b43_radio_read16(dev, 0x0052);
2616 backup[2] = b43_radio_read16(dev, 0x0043);
2617 backup[3] = b43_phy_read(dev, 0x0030);
2618 backup[4] = b43_phy_read(dev, 0x0026);
2619 backup[5] = b43_phy_read(dev, 0x0015);
2620 backup[6] = b43_phy_read(dev, 0x002A);
2621 backup[7] = b43_phy_read(dev, 0x0020);
2622 backup[8] = b43_phy_read(dev, 0x005A);
2623 backup[9] = b43_phy_read(dev, 0x0059);
2624 backup[10] = b43_phy_read(dev, 0x0058);
2625 backup[11] = b43_read16(dev, 0x03E2);
2626 backup[12] = b43_read16(dev, 0x03E6);
2627 backup[13] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2628
2629 tmp = b43_radio_read16(dev, 0x007A);
2630 tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
2631 b43_radio_write16(dev, 0x007A, tmp);
2632 b43_phy_write(dev, 0x0030, 0x00FF);
2633 b43_write16(dev, 0x03EC, 0x7F7F);
2634 b43_phy_write(dev, 0x0026, 0x0000);
2635 b43_phy_write(dev, 0x0015, b43_phy_read(dev, 0x0015) | 0x0020);
2636 b43_phy_write(dev, 0x002A, 0x08A3);
2637 b43_radio_write16(dev, 0x007A,
2638 b43_radio_read16(dev, 0x007A) | 0x0080);
2639
2640 nrssi0 = (s16) b43_phy_read(dev, 0x0027);
2641 b43_radio_write16(dev, 0x007A,
2642 b43_radio_read16(dev, 0x007A) & 0x007F);
2643 if (phy->rev >= 2) {
2644 b43_write16(dev, 0x03E6, 0x0040);
2645 } else if (phy->rev == 0) {
2646 b43_write16(dev, 0x03E6, 0x0122);
2647 } else {
2648 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2649 b43_read16(dev,
2650 B43_MMIO_CHANNEL_EXT) & 0x2000);
2651 }
2652 b43_phy_write(dev, 0x0020, 0x3F3F);
2653 b43_phy_write(dev, 0x0015, 0xF330);
2654 b43_radio_write16(dev, 0x005A, 0x0060);
2655 b43_radio_write16(dev, 0x0043,
2656 b43_radio_read16(dev, 0x0043) & 0x00F0);
2657 b43_phy_write(dev, 0x005A, 0x0480);
2658 b43_phy_write(dev, 0x0059, 0x0810);
2659 b43_phy_write(dev, 0x0058, 0x000D);
2660 udelay(20);
2661
2662 nrssi1 = (s16) b43_phy_read(dev, 0x0027);
2663 b43_phy_write(dev, 0x0030, backup[3]);
2664 b43_radio_write16(dev, 0x007A, backup[0]);
2665 b43_write16(dev, 0x03E2, backup[11]);
2666 b43_phy_write(dev, 0x0026, backup[4]);
2667 b43_phy_write(dev, 0x0015, backup[5]);
2668 b43_phy_write(dev, 0x002A, backup[6]);
2669 b43_synth_pu_workaround(dev, phy->channel);
2670 if (phy->rev != 0)
2671 b43_write16(dev, 0x03F4, backup[13]);
2672
2673 b43_phy_write(dev, 0x0020, backup[7]);
2674 b43_phy_write(dev, 0x005A, backup[8]);
2675 b43_phy_write(dev, 0x0059, backup[9]);
2676 b43_phy_write(dev, 0x0058, backup[10]);
2677 b43_radio_write16(dev, 0x0052, backup[1]);
2678 b43_radio_write16(dev, 0x0043, backup[2]);
2679
2680 if (nrssi0 == nrssi1)
2681 phy->nrssislope = 0x00010000;
2682 else
2683 phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2684
2685 if (nrssi0 <= -4) {
2686 phy->nrssi[0] = nrssi0;
2687 phy->nrssi[1] = nrssi1;
2688 }
2689 break;
2690 case B43_PHYTYPE_G:
2691 if (phy->radio_rev >= 9)
2692 return;
2693 if (phy->radio_rev == 8)
2694 b43_calc_nrssi_offset(dev);
2695
2696 b43_phy_write(dev, B43_PHY_G_CRS,
2697 b43_phy_read(dev, B43_PHY_G_CRS) & 0x7FFF);
2698 b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) & 0xFFFC);
2699 backup[7] = b43_read16(dev, 0x03E2);
2700 b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
2701 backup[0] = b43_radio_read16(dev, 0x007A);
2702 backup[1] = b43_radio_read16(dev, 0x0052);
2703 backup[2] = b43_radio_read16(dev, 0x0043);
2704 backup[3] = b43_phy_read(dev, 0x0015);
2705 backup[4] = b43_phy_read(dev, 0x005A);
2706 backup[5] = b43_phy_read(dev, 0x0059);
2707 backup[6] = b43_phy_read(dev, 0x0058);
2708 backup[8] = b43_read16(dev, 0x03E6);
2709 backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
2710 if (phy->rev >= 3) {
2711 backup[10] = b43_phy_read(dev, 0x002E);
2712 backup[11] = b43_phy_read(dev, 0x002F);
2713 backup[12] = b43_phy_read(dev, 0x080F);
2714 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
2715 backup[14] = b43_phy_read(dev, 0x0801);
2716 backup[15] = b43_phy_read(dev, 0x0060);
2717 backup[16] = b43_phy_read(dev, 0x0014);
2718 backup[17] = b43_phy_read(dev, 0x0478);
2719 b43_phy_write(dev, 0x002E, 0);
2720 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
2721 switch (phy->rev) {
2722 case 4:
2723 case 6:
2724 case 7:
2725 b43_phy_write(dev, 0x0478,
2726 b43_phy_read(dev, 0x0478)
2727 | 0x0100);
2728 b43_phy_write(dev, 0x0801,
2729 b43_phy_read(dev, 0x0801)
2730 | 0x0040);
2731 break;
2732 case 3:
2733 case 5:
2734 b43_phy_write(dev, 0x0801,
2735 b43_phy_read(dev, 0x0801)
2736 & 0xFFBF);
2737 break;
2738 }
2739 b43_phy_write(dev, 0x0060, b43_phy_read(dev, 0x0060)
2740 | 0x0040);
2741 b43_phy_write(dev, 0x0014, b43_phy_read(dev, 0x0014)
2742 | 0x0200);
2743 }
2744 b43_radio_write16(dev, 0x007A,
2745 b43_radio_read16(dev, 0x007A) | 0x0070);
2746 b43_set_all_gains(dev, 0, 8, 0);
2747 b43_radio_write16(dev, 0x007A,
2748 b43_radio_read16(dev, 0x007A) & 0x00F7);
2749 if (phy->rev >= 2) {
2750 b43_phy_write(dev, 0x0811,
2751 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
2752 0x0030);
2753 b43_phy_write(dev, 0x0812,
2754 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
2755 0x0010);
2756 }
2757 b43_radio_write16(dev, 0x007A,
2758 b43_radio_read16(dev, 0x007A) | 0x0080);
2759 udelay(20);
2760
2761 nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2762 if (nrssi0 >= 0x0020)
2763 nrssi0 -= 0x0040;
2764
2765 b43_radio_write16(dev, 0x007A,
2766 b43_radio_read16(dev, 0x007A) & 0x007F);
2767 if (phy->rev >= 2) {
2768 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
2769 & 0xFF9F) | 0x0040);
2770 }
2771
2772 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2773 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2774 | 0x2000);
2775 b43_radio_write16(dev, 0x007A,
2776 b43_radio_read16(dev, 0x007A) | 0x000F);
2777 b43_phy_write(dev, 0x0015, 0xF330);
2778 if (phy->rev >= 2) {
2779 b43_phy_write(dev, 0x0812,
2780 (b43_phy_read(dev, 0x0812) & 0xFFCF) |
2781 0x0020);
2782 b43_phy_write(dev, 0x0811,
2783 (b43_phy_read(dev, 0x0811) & 0xFFCF) |
2784 0x0020);
2785 }
2786
2787 b43_set_all_gains(dev, 3, 0, 1);
2788 if (phy->radio_rev == 8) {
2789 b43_radio_write16(dev, 0x0043, 0x001F);
2790 } else {
2791 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
2792 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
2793 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
2794 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
2795 }
2796 b43_phy_write(dev, 0x005A, 0x0480);
2797 b43_phy_write(dev, 0x0059, 0x0810);
2798 b43_phy_write(dev, 0x0058, 0x000D);
2799 udelay(20);
2800 nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
2801 if (nrssi1 >= 0x0020)
2802 nrssi1 -= 0x0040;
2803 if (nrssi0 == nrssi1)
2804 phy->nrssislope = 0x00010000;
2805 else
2806 phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2807 if (nrssi0 >= -4) {
2808 phy->nrssi[0] = nrssi1;
2809 phy->nrssi[1] = nrssi0;
2810 }
2811 if (phy->rev >= 3) {
2812 b43_phy_write(dev, 0x002E, backup[10]);
2813 b43_phy_write(dev, 0x002F, backup[11]);
2814 b43_phy_write(dev, 0x080F, backup[12]);
2815 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
2816 }
2817 if (phy->rev >= 2) {
2818 b43_phy_write(dev, 0x0812,
2819 b43_phy_read(dev, 0x0812) & 0xFFCF);
2820 b43_phy_write(dev, 0x0811,
2821 b43_phy_read(dev, 0x0811) & 0xFFCF);
2822 }
2823
2824 b43_radio_write16(dev, 0x007A, backup[0]);
2825 b43_radio_write16(dev, 0x0052, backup[1]);
2826 b43_radio_write16(dev, 0x0043, backup[2]);
2827 b43_write16(dev, 0x03E2, backup[7]);
2828 b43_write16(dev, 0x03E6, backup[8]);
2829 b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
2830 b43_phy_write(dev, 0x0015, backup[3]);
2831 b43_phy_write(dev, 0x005A, backup[4]);
2832 b43_phy_write(dev, 0x0059, backup[5]);
2833 b43_phy_write(dev, 0x0058, backup[6]);
2834 b43_synth_pu_workaround(dev, phy->channel);
2835 b43_phy_write(dev, 0x0802,
2836 b43_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
2837 b43_set_original_gains(dev);
2838 b43_phy_write(dev, B43_PHY_G_CRS,
2839 b43_phy_read(dev, B43_PHY_G_CRS) | 0x8000);
2840 if (phy->rev >= 3) {
2841 b43_phy_write(dev, 0x0801, backup[14]);
2842 b43_phy_write(dev, 0x0060, backup[15]);
2843 b43_phy_write(dev, 0x0014, backup[16]);
2844 b43_phy_write(dev, 0x0478, backup[17]);
2845 }
2846 b43_nrssi_mem_update(dev);
2847 b43_calc_nrssi_threshold(dev);
2848 break;
2849 default:
2850 B43_WARN_ON(1);
2851 }
2852 }
2853
2854 void b43_calc_nrssi_threshold(struct b43_wldev *dev)
2855 {
2856 struct b43_phy *phy = &dev->phy;
2857 s32 threshold;
2858 s32 a, b;
2859 s16 tmp16;
2860 u16 tmp_u16;
2861
2862 switch (phy->type) {
2863 case B43_PHYTYPE_B:{
2864 if (phy->radio_ver != 0x2050)
2865 return;
2866 if (!
2867 (dev->dev->bus->sprom.
2868 boardflags_lo & B43_BFL_RSSI))
2869 return;
2870
2871 if (phy->radio_rev >= 6) {
2872 threshold =
2873 (phy->nrssi[1] - phy->nrssi[0]) * 32;
2874 threshold += 20 * (phy->nrssi[0] + 1);
2875 threshold /= 40;
2876 } else
2877 threshold = phy->nrssi[1] - 5;
2878
2879 threshold = limit_value(threshold, 0, 0x3E);
2880 b43_phy_read(dev, 0x0020); /* dummy read */
2881 b43_phy_write(dev, 0x0020,
2882 (((u16) threshold) << 8) | 0x001C);
2883
2884 if (phy->radio_rev >= 6) {
2885 b43_phy_write(dev, 0x0087, 0x0E0D);
2886 b43_phy_write(dev, 0x0086, 0x0C0B);
2887 b43_phy_write(dev, 0x0085, 0x0A09);
2888 b43_phy_write(dev, 0x0084, 0x0808);
2889 b43_phy_write(dev, 0x0083, 0x0808);
2890 b43_phy_write(dev, 0x0082, 0x0604);
2891 b43_phy_write(dev, 0x0081, 0x0302);
2892 b43_phy_write(dev, 0x0080, 0x0100);
2893 }
2894 break;
2895 }
2896 case B43_PHYTYPE_G:
2897 if (!phy->gmode ||
2898 !(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
2899 tmp16 = b43_nrssi_hw_read(dev, 0x20);
2900 if (tmp16 >= 0x20)
2901 tmp16 -= 0x40;
2902 if (tmp16 < 3) {
2903 b43_phy_write(dev, 0x048A,
2904 (b43_phy_read(dev, 0x048A)
2905 & 0xF000) | 0x09EB);
2906 } else {
2907 b43_phy_write(dev, 0x048A,
2908 (b43_phy_read(dev, 0x048A)
2909 & 0xF000) | 0x0AED);
2910 }
2911 } else {
2912 if (phy->interfmode == B43_INTERFMODE_NONWLAN) {
2913 a = 0xE;
2914 b = 0xA;
2915 } else if (!phy->aci_wlan_automatic && phy->aci_enable) {
2916 a = 0x13;
2917 b = 0x12;
2918 } else {
2919 a = 0xE;
2920 b = 0x11;
2921 }
2922
2923 a = a * (phy->nrssi[1] - phy->nrssi[0]);
2924 a += (phy->nrssi[0] << 6);
2925 if (a < 32)
2926 a += 31;
2927 else
2928 a += 32;
2929 a = a >> 6;
2930 a = limit_value(a, -31, 31);
2931
2932 b = b * (phy->nrssi[1] - phy->nrssi[0]);
2933 b += (phy->nrssi[0] << 6);
2934 if (b < 32)
2935 b += 31;
2936 else
2937 b += 32;
2938 b = b >> 6;
2939 b = limit_value(b, -31, 31);
2940
2941 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
2942 tmp_u16 |= ((u32) b & 0x0000003F);
2943 tmp_u16 |= (((u32) a & 0x0000003F) << 6);
2944 b43_phy_write(dev, 0x048A, tmp_u16);
2945 }
2946 break;
2947 default:
2948 B43_WARN_ON(1);
2949 }
2950 }
2951
2952 /* Stack implementation to save/restore values from the
2953 * interference mitigation code.
2954 * It is save to restore values in random order.
2955 */
2956 static void _stack_save(u32 * _stackptr, size_t * stackidx,
2957 u8 id, u16 offset, u16 value)
2958 {
2959 u32 *stackptr = &(_stackptr[*stackidx]);
2960
2961 B43_WARN_ON(offset & 0xF000);
2962 B43_WARN_ON(id & 0xF0);
2963 *stackptr = offset;
2964 *stackptr |= ((u32) id) << 12;
2965 *stackptr |= ((u32) value) << 16;
2966 (*stackidx)++;
2967 B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
2968 }
2969
2970 static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
2971 {
2972 size_t i;
2973
2974 B43_WARN_ON(offset & 0xF000);
2975 B43_WARN_ON(id & 0xF0);
2976 for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
2977 if ((*stackptr & 0x00000FFF) != offset)
2978 continue;
2979 if (((*stackptr & 0x0000F000) >> 12) != id)
2980 continue;
2981 return ((*stackptr & 0xFFFF0000) >> 16);
2982 }
2983 B43_WARN_ON(1);
2984
2985 return 0;
2986 }
2987
2988 #define phy_stacksave(offset) \
2989 do { \
2990 _stack_save(stack, &stackidx, 0x1, (offset), \
2991 b43_phy_read(dev, (offset))); \
2992 } while (0)
2993 #define phy_stackrestore(offset) \
2994 do { \
2995 b43_phy_write(dev, (offset), \
2996 _stack_restore(stack, 0x1, \
2997 (offset))); \
2998 } while (0)
2999 #define radio_stacksave(offset) \
3000 do { \
3001 _stack_save(stack, &stackidx, 0x2, (offset), \
3002 b43_radio_read16(dev, (offset))); \
3003 } while (0)
3004 #define radio_stackrestore(offset) \
3005 do { \
3006 b43_radio_write16(dev, (offset), \
3007 _stack_restore(stack, 0x2, \
3008 (offset))); \
3009 } while (0)
3010 #define ofdmtab_stacksave(table, offset) \
3011 do { \
3012 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
3013 b43_ofdmtab_read16(dev, (table), (offset))); \
3014 } while (0)
3015 #define ofdmtab_stackrestore(table, offset) \
3016 do { \
3017 b43_ofdmtab_write16(dev, (table), (offset), \
3018 _stack_restore(stack, 0x3, \
3019 (offset)|(table))); \
3020 } while (0)
3021
3022 static void
3023 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
3024 {
3025 struct b43_phy *phy = &dev->phy;
3026 u16 tmp, flipped;
3027 size_t stackidx = 0;
3028 u32 *stack = phy->interfstack;
3029
3030 switch (mode) {
3031 case B43_INTERFMODE_NONWLAN:
3032 if (phy->rev != 1) {
3033 b43_phy_write(dev, 0x042B,
3034 b43_phy_read(dev, 0x042B) | 0x0800);
3035 b43_phy_write(dev, B43_PHY_G_CRS,
3036 b43_phy_read(dev,
3037 B43_PHY_G_CRS) & ~0x4000);
3038 break;
3039 }
3040 radio_stacksave(0x0078);
3041 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
3042 flipped = flip_4bit(tmp);
3043 if (flipped < 10 && flipped >= 8)
3044 flipped = 7;
3045 else if (flipped >= 10)
3046 flipped -= 3;
3047 flipped = flip_4bit(flipped);
3048 flipped = (flipped << 1) | 0x0020;
3049 b43_radio_write16(dev, 0x0078, flipped);
3050
3051 b43_calc_nrssi_threshold(dev);
3052
3053 phy_stacksave(0x0406);
3054 b43_phy_write(dev, 0x0406, 0x7E28);
3055
3056 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) | 0x0800);
3057 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3058 b43_phy_read(dev,
3059 B43_PHY_RADIO_BITFIELD) | 0x1000);
3060
3061 phy_stacksave(0x04A0);
3062 b43_phy_write(dev, 0x04A0,
3063 (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
3064 phy_stacksave(0x04A1);
3065 b43_phy_write(dev, 0x04A1,
3066 (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
3067 phy_stacksave(0x04A2);
3068 b43_phy_write(dev, 0x04A2,
3069 (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
3070 phy_stacksave(0x04A8);
3071 b43_phy_write(dev, 0x04A8,
3072 (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
3073 phy_stacksave(0x04AB);
3074 b43_phy_write(dev, 0x04AB,
3075 (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
3076
3077 phy_stacksave(0x04A7);
3078 b43_phy_write(dev, 0x04A7, 0x0002);
3079 phy_stacksave(0x04A3);
3080 b43_phy_write(dev, 0x04A3, 0x287A);
3081 phy_stacksave(0x04A9);
3082 b43_phy_write(dev, 0x04A9, 0x2027);
3083 phy_stacksave(0x0493);
3084 b43_phy_write(dev, 0x0493, 0x32F5);
3085 phy_stacksave(0x04AA);
3086 b43_phy_write(dev, 0x04AA, 0x2027);
3087 phy_stacksave(0x04AC);
3088 b43_phy_write(dev, 0x04AC, 0x32F5);
3089 break;
3090 case B43_INTERFMODE_MANUALWLAN:
3091 if (b43_phy_read(dev, 0x0033) & 0x0800)
3092 break;
3093
3094 phy->aci_enable = 1;
3095
3096 phy_stacksave(B43_PHY_RADIO_BITFIELD);
3097 phy_stacksave(B43_PHY_G_CRS);
3098 if (phy->rev < 2) {
3099 phy_stacksave(0x0406);
3100 } else {
3101 phy_stacksave(0x04C0);
3102 phy_stacksave(0x04C1);
3103 }
3104 phy_stacksave(0x0033);
3105 phy_stacksave(0x04A7);
3106 phy_stacksave(0x04A3);
3107 phy_stacksave(0x04A9);
3108 phy_stacksave(0x04AA);
3109 phy_stacksave(0x04AC);
3110 phy_stacksave(0x0493);
3111 phy_stacksave(0x04A1);
3112 phy_stacksave(0x04A0);
3113 phy_stacksave(0x04A2);
3114 phy_stacksave(0x048A);
3115 phy_stacksave(0x04A8);
3116 phy_stacksave(0x04AB);
3117 if (phy->rev == 2) {
3118 phy_stacksave(0x04AD);
3119 phy_stacksave(0x04AE);
3120 } else if (phy->rev >= 3) {
3121 phy_stacksave(0x04AD);
3122 phy_stacksave(0x0415);
3123 phy_stacksave(0x0416);
3124 phy_stacksave(0x0417);
3125 ofdmtab_stacksave(0x1A00, 0x2);
3126 ofdmtab_stacksave(0x1A00, 0x3);
3127 }
3128 phy_stacksave(0x042B);
3129 phy_stacksave(0x048C);
3130
3131 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3132 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3133 & ~0x1000);
3134 b43_phy_write(dev, B43_PHY_G_CRS,
3135 (b43_phy_read(dev, B43_PHY_G_CRS)
3136 & 0xFFFC) | 0x0002);
3137
3138 b43_phy_write(dev, 0x0033, 0x0800);
3139 b43_phy_write(dev, 0x04A3, 0x2027);
3140 b43_phy_write(dev, 0x04A9, 0x1CA8);
3141 b43_phy_write(dev, 0x0493, 0x287A);
3142 b43_phy_write(dev, 0x04AA, 0x1CA8);
3143 b43_phy_write(dev, 0x04AC, 0x287A);
3144
3145 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3146 & 0xFFC0) | 0x001A);
3147 b43_phy_write(dev, 0x04A7, 0x000D);
3148
3149 if (phy->rev < 2) {
3150 b43_phy_write(dev, 0x0406, 0xFF0D);
3151 } else if (phy->rev == 2) {
3152 b43_phy_write(dev, 0x04C0, 0xFFFF);
3153 b43_phy_write(dev, 0x04C1, 0x00A9);
3154 } else {
3155 b43_phy_write(dev, 0x04C0, 0x00C1);
3156 b43_phy_write(dev, 0x04C1, 0x0059);
3157 }
3158
3159 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3160 & 0xC0FF) | 0x1800);
3161 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
3162 & 0xFFC0) | 0x0015);
3163 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3164 & 0xCFFF) | 0x1000);
3165 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3166 & 0xF0FF) | 0x0A00);
3167 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3168 & 0xCFFF) | 0x1000);
3169 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3170 & 0xF0FF) | 0x0800);
3171 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3172 & 0xFFCF) | 0x0010);
3173 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
3174 & 0xFFF0) | 0x0005);
3175 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3176 & 0xFFCF) | 0x0010);
3177 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
3178 & 0xFFF0) | 0x0006);
3179 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3180 & 0xF0FF) | 0x0800);
3181 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
3182 & 0xF0FF) | 0x0500);
3183 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
3184 & 0xFFF0) | 0x000B);
3185
3186 if (phy->rev >= 3) {
3187 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3188 & ~0x8000);
3189 b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
3190 & 0x8000) | 0x36D8);
3191 b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
3192 & 0x8000) | 0x36D8);
3193 b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
3194 & 0xFE00) | 0x016D);
3195 } else {
3196 b43_phy_write(dev, 0x048A, b43_phy_read(dev, 0x048A)
3197 | 0x1000);
3198 b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
3199 & 0x9FFF) | 0x2000);
3200 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
3201 }
3202 if (phy->rev >= 2) {
3203 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B)
3204 | 0x0800);
3205 }
3206 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
3207 & 0xF0FF) | 0x0200);
3208 if (phy->rev == 2) {
3209 b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
3210 & 0xFF00) | 0x007F);
3211 b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
3212 & 0x00FF) | 0x1300);
3213 } else if (phy->rev >= 6) {
3214 b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
3215 b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
3216 b43_phy_write(dev, 0x04AD, b43_phy_read(dev, 0x04AD)
3217 & 0x00FF);
3218 }
3219 b43_calc_nrssi_slope(dev);
3220 break;
3221 default:
3222 B43_WARN_ON(1);
3223 }
3224 }
3225
3226 static void
3227 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
3228 {
3229 struct b43_phy *phy = &dev->phy;
3230 u32 *stack = phy->interfstack;
3231
3232 switch (mode) {
3233 case B43_INTERFMODE_NONWLAN:
3234 if (phy->rev != 1) {
3235 b43_phy_write(dev, 0x042B,
3236 b43_phy_read(dev, 0x042B) & ~0x0800);
3237 b43_phy_write(dev, B43_PHY_G_CRS,
3238 b43_phy_read(dev,
3239 B43_PHY_G_CRS) | 0x4000);
3240 break;
3241 }
3242 radio_stackrestore(0x0078);
3243 b43_calc_nrssi_threshold(dev);
3244 phy_stackrestore(0x0406);
3245 b43_phy_write(dev, 0x042B, b43_phy_read(dev, 0x042B) & ~0x0800);
3246 if (!dev->bad_frames_preempt) {
3247 b43_phy_write(dev, B43_PHY_RADIO_BITFIELD,
3248 b43_phy_read(dev, B43_PHY_RADIO_BITFIELD)
3249 & ~(1 << 11));
3250 }
3251 b43_phy_write(dev, B43_PHY_G_CRS,
3252 b43_phy_read(dev, B43_PHY_G_CRS) | 0x4000);
3253 phy_stackrestore(0x04A0);
3254 phy_stackrestore(0x04A1);
3255 phy_stackrestore(0x04A2);
3256 phy_stackrestore(0x04A8);
3257 phy_stackrestore(0x04AB);
3258 phy_stackrestore(0x04A7);
3259 phy_stackrestore(0x04A3);
3260 phy_stackrestore(0x04A9);
3261 phy_stackrestore(0x0493);
3262 phy_stackrestore(0x04AA);
3263 phy_stackrestore(0x04AC);
3264 break;
3265 case B43_INTERFMODE_MANUALWLAN:
3266 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
3267 break;
3268
3269 phy->aci_enable = 0;
3270
3271 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
3272 phy_stackrestore(B43_PHY_G_CRS);
3273 phy_stackrestore(0x0033);
3274 phy_stackrestore(0x04A3);
3275 phy_stackrestore(0x04A9);
3276 phy_stackrestore(0x0493);
3277 phy_stackrestore(0x04AA);
3278 phy_stackrestore(0x04AC);
3279 phy_stackrestore(0x04A0);
3280 phy_stackrestore(0x04A7);
3281 if (phy->rev >= 2) {
3282 phy_stackrestore(0x04C0);
3283 phy_stackrestore(0x04C1);
3284 } else
3285 phy_stackrestore(0x0406);
3286 phy_stackrestore(0x04A1);
3287 phy_stackrestore(0x04AB);
3288 phy_stackrestore(0x04A8);
3289 if (phy->rev == 2) {
3290 phy_stackrestore(0x04AD);
3291 phy_stackrestore(0x04AE);
3292 } else if (phy->rev >= 3) {
3293 phy_stackrestore(0x04AD);
3294 phy_stackrestore(0x0415);
3295 phy_stackrestore(0x0416);
3296 phy_stackrestore(0x0417);
3297 ofdmtab_stackrestore(0x1A00, 0x2);
3298 ofdmtab_stackrestore(0x1A00, 0x3);
3299 }
3300 phy_stackrestore(0x04A2);
3301 phy_stackrestore(0x048A);
3302 phy_stackrestore(0x042B);
3303 phy_stackrestore(0x048C);
3304 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
3305 b43_calc_nrssi_slope(dev);
3306 break;
3307 default:
3308 B43_WARN_ON(1);
3309 }
3310 }
3311
3312 #undef phy_stacksave
3313 #undef phy_stackrestore
3314 #undef radio_stacksave
3315 #undef radio_stackrestore
3316 #undef ofdmtab_stacksave
3317 #undef ofdmtab_stackrestore
3318
3319 int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode)
3320 {
3321 struct b43_phy *phy = &dev->phy;
3322 int currentmode;
3323
3324 if ((phy->type != B43_PHYTYPE_G) || (phy->rev == 0) || (!phy->gmode))
3325 return -ENODEV;
3326
3327 phy->aci_wlan_automatic = 0;
3328 switch (mode) {
3329 case B43_INTERFMODE_AUTOWLAN:
3330 phy->aci_wlan_automatic = 1;
3331 if (phy->aci_enable)
3332 mode = B43_INTERFMODE_MANUALWLAN;
3333 else
3334 mode = B43_INTERFMODE_NONE;
3335 break;
3336 case B43_INTERFMODE_NONE:
3337 case B43_INTERFMODE_NONWLAN:
3338 case B43_INTERFMODE_MANUALWLAN:
3339 break;
3340 default:
3341 return -EINVAL;
3342 }
3343
3344 currentmode = phy->interfmode;
3345 if (currentmode == mode)
3346 return 0;
3347 if (currentmode != B43_INTERFMODE_NONE)
3348 b43_radio_interference_mitigation_disable(dev, currentmode);
3349
3350 if (mode == B43_INTERFMODE_NONE) {
3351 phy->aci_enable = 0;
3352 phy->aci_hw_rssi = 0;
3353 } else
3354 b43_radio_interference_mitigation_enable(dev, mode);
3355 phy->interfmode = mode;
3356
3357 return 0;
3358 }
3359
3360 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
3361 {
3362 u16 reg, index, ret;
3363
3364 static const u8 rcc_table[] = {
3365 0x02, 0x03, 0x01, 0x0F,
3366 0x06, 0x07, 0x05, 0x0F,
3367 0x0A, 0x0B, 0x09, 0x0F,
3368 0x0E, 0x0F, 0x0D, 0x0F,
3369 };
3370
3371 reg = b43_radio_read16(dev, 0x60);
3372 index = (reg & 0x001E) >> 1;
3373 ret = rcc_table[index] << 1;
3374 ret |= (reg & 0x0001);
3375 ret |= 0x0020;
3376
3377 return ret;
3378 }
3379
3380 #define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
3381 static u16 radio2050_rfover_val(struct b43_wldev *dev,
3382 u16 phy_register, unsigned int lpd)
3383 {
3384 struct b43_phy *phy = &dev->phy;
3385 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
3386
3387 if (!phy->gmode)
3388 return 0;
3389
3390 if (has_loopback_gain(phy)) {
3391 int max_lb_gain = phy->max_lb_gain;
3392 u16 extlna;
3393 u16 i;
3394
3395 if (phy->radio_rev == 8)
3396 max_lb_gain += 0x3E;
3397 else
3398 max_lb_gain += 0x26;
3399 if (max_lb_gain >= 0x46) {
3400 extlna = 0x3000;
3401 max_lb_gain -= 0x46;
3402 } else if (max_lb_gain >= 0x3A) {
3403 extlna = 0x1000;
3404 max_lb_gain -= 0x3A;
3405 } else if (max_lb_gain >= 0x2E) {
3406 extlna = 0x2000;
3407 max_lb_gain -= 0x2E;
3408 } else {
3409 extlna = 0;
3410 max_lb_gain -= 0x10;
3411 }
3412
3413 for (i = 0; i < 16; i++) {
3414 max_lb_gain -= (i * 6);
3415 if (max_lb_gain < 6)
3416 break;
3417 }
3418
3419 if ((phy->rev < 7) ||
3420 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
3421 if (phy_register == B43_PHY_RFOVER) {
3422 return 0x1B3;
3423 } else if (phy_register == B43_PHY_RFOVERVAL) {
3424 extlna |= (i << 8);
3425 switch (lpd) {
3426 case LPD(0, 1, 1):
3427 return 0x0F92;
3428 case LPD(0, 0, 1):
3429 case LPD(1, 0, 1):
3430 return (0x0092 | extlna);
3431 case LPD(1, 0, 0):
3432 return (0x0093 | extlna);
3433 }
3434 B43_WARN_ON(1);
3435 }
3436 B43_WARN_ON(1);
3437 } else {
3438 if (phy_register == B43_PHY_RFOVER) {
3439 return 0x9B3;
3440 } else if (phy_register == B43_PHY_RFOVERVAL) {
3441 if (extlna)
3442 extlna |= 0x8000;
3443 extlna |= (i << 8);
3444 switch (lpd) {
3445 case LPD(0, 1, 1):
3446 return 0x8F92;
3447 case LPD(0, 0, 1):
3448 return (0x8092 | extlna);
3449 case LPD(1, 0, 1):
3450 return (0x2092 | extlna);
3451 case LPD(1, 0, 0):
3452 return (0x2093 | extlna);
3453 }
3454 B43_WARN_ON(1);
3455 }
3456 B43_WARN_ON(1);
3457 }
3458 } else {
3459 if ((phy->rev < 7) ||
3460 !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
3461 if (phy_register == B43_PHY_RFOVER) {
3462 return 0x1B3;
3463 } else if (phy_register == B43_PHY_RFOVERVAL) {
3464 switch (lpd) {
3465 case LPD(0, 1, 1):
3466 return 0x0FB2;
3467 case LPD(0, 0, 1):
3468 return 0x00B2;
3469 case LPD(1, 0, 1):
3470 return 0x30B2;
3471 case LPD(1, 0, 0):
3472 return 0x30B3;
3473 }
3474 B43_WARN_ON(1);
3475 }
3476 B43_WARN_ON(1);
3477 } else {
3478 if (phy_register == B43_PHY_RFOVER) {
3479 return 0x9B3;
3480 } else if (phy_register == B43_PHY_RFOVERVAL) {
3481 switch (lpd) {
3482 case LPD(0, 1, 1):
3483 return 0x8FB2;
3484 case LPD(0, 0, 1):
3485 return 0x80B2;
3486 case LPD(1, 0, 1):
3487 return 0x20B2;
3488 case LPD(1, 0, 0):
3489 return 0x20B3;
3490 }
3491 B43_WARN_ON(1);
3492 }
3493 B43_WARN_ON(1);
3494 }
3495 }
3496 return 0;
3497 }
3498
3499 struct init2050_saved_values {
3500 /* Core registers */
3501 u16 reg_3EC;
3502 u16 reg_3E6;
3503 u16 reg_3F4;
3504 /* Radio registers */
3505 u16 radio_43;
3506 u16 radio_51;
3507 u16 radio_52;
3508 /* PHY registers */
3509 u16 phy_pgactl;
3510 u16 phy_cck_5A;
3511 u16 phy_cck_59;
3512 u16 phy_cck_58;
3513 u16 phy_cck_30;
3514 u16 phy_rfover;
3515 u16 phy_rfoverval;
3516 u16 phy_analogover;
3517 u16 phy_analogoverval;
3518 u16 phy_crs0;
3519 u16 phy_classctl;
3520 u16 phy_lo_mask;
3521 u16 phy_lo_ctl;
3522 u16 phy_syncctl;
3523 };
3524
3525 u16 b43_radio_init2050(struct b43_wldev *dev)
3526 {
3527 struct b43_phy *phy = &dev->phy;
3528 struct init2050_saved_values sav;
3529 u16 rcc;
3530 u16 radio78;
3531 u16 ret;
3532 u16 i, j;
3533 u32 tmp1 = 0, tmp2 = 0;
3534
3535 memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */
3536
3537 sav.radio_43 = b43_radio_read16(dev, 0x43);
3538 sav.radio_51 = b43_radio_read16(dev, 0x51);
3539 sav.radio_52 = b43_radio_read16(dev, 0x52);
3540 sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
3541 sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
3542 sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
3543 sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
3544
3545 if (phy->type == B43_PHYTYPE_B) {
3546 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
3547 sav.reg_3EC = b43_read16(dev, 0x3EC);
3548
3549 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
3550 b43_write16(dev, 0x3EC, 0x3F3F);
3551 } else if (phy->gmode || phy->rev >= 2) {
3552 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
3553 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
3554 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
3555 sav.phy_analogoverval =
3556 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
3557 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
3558 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
3559
3560 b43_phy_write(dev, B43_PHY_ANALOGOVER,
3561 b43_phy_read(dev, B43_PHY_ANALOGOVER)
3562 | 0x0003);
3563 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
3564 b43_phy_read(dev, B43_PHY_ANALOGOVERVAL)
3565 & 0xFFFC);
3566 b43_phy_write(dev, B43_PHY_CRS0, b43_phy_read(dev, B43_PHY_CRS0)
3567 & 0x7FFF);
3568 b43_phy_write(dev, B43_PHY_CLASSCTL,
3569 b43_phy_read(dev, B43_PHY_CLASSCTL)
3570 & 0xFFFC);
3571 if (has_loopback_gain(phy)) {
3572 sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
3573 sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
3574
3575 if (phy->rev >= 3)
3576 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
3577 else
3578 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
3579 b43_phy_write(dev, B43_PHY_LO_CTL, 0);
3580 }
3581
3582 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3583 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3584 LPD(0, 1, 1)));
3585 b43_phy_write(dev, B43_PHY_RFOVER,
3586 radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
3587 }
3588 b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
3589
3590 sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
3591 b43_phy_write(dev, B43_PHY_SYNCCTL, b43_phy_read(dev, B43_PHY_SYNCCTL)
3592 & 0xFF7F);
3593 sav.reg_3E6 = b43_read16(dev, 0x3E6);
3594 sav.reg_3F4 = b43_read16(dev, 0x3F4);
3595
3596 if (phy->analog == 0) {
3597 b43_write16(dev, 0x03E6, 0x0122);
3598 } else {
3599 if (phy->analog >= 2) {
3600 b43_phy_write(dev, B43_PHY_CCK(0x03),
3601 (b43_phy_read(dev, B43_PHY_CCK(0x03))
3602 & 0xFFBF) | 0x40);
3603 }
3604 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3605 (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
3606 }
3607
3608 rcc = b43_radio_core_calibration_value(dev);
3609
3610 if (phy->type == B43_PHYTYPE_B)
3611 b43_radio_write16(dev, 0x78, 0x26);
3612 if (phy->gmode || phy->rev >= 2) {
3613 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3614 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3615 LPD(0, 1, 1)));
3616 }
3617 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
3618 b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
3619 if (phy->gmode || phy->rev >= 2) {
3620 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3621 radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
3622 LPD(0, 0, 1)));
3623 }
3624 b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
3625 b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
3626 | 0x0004);
3627 if (phy->radio_rev == 8) {
3628 b43_radio_write16(dev, 0x43, 0x1F);
3629 } else {
3630 b43_radio_write16(dev, 0x52, 0);
3631 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
3632 & 0xFFF0) | 0x0009);
3633 }
3634 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3635
3636 for (i = 0; i < 16; i++) {
3637 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
3638 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
3639 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
3640 if (phy->gmode || phy->rev >= 2) {
3641 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3642 radio2050_rfover_val(dev,
3643 B43_PHY_RFOVERVAL,
3644 LPD(1, 0, 1)));
3645 }
3646 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3647 udelay(10);
3648 if (phy->gmode || phy->rev >= 2) {
3649 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3650 radio2050_rfover_val(dev,
3651 B43_PHY_RFOVERVAL,
3652 LPD(1, 0, 1)));
3653 }
3654 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3655 udelay(10);
3656 if (phy->gmode || phy->rev >= 2) {
3657 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3658 radio2050_rfover_val(dev,
3659 B43_PHY_RFOVERVAL,
3660 LPD(1, 0, 0)));
3661 }
3662 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3663 udelay(20);
3664 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3665 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3666 if (phy->gmode || phy->rev >= 2) {
3667 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3668 radio2050_rfover_val(dev,
3669 B43_PHY_RFOVERVAL,
3670 LPD(1, 0, 1)));
3671 }
3672 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3673 }
3674 udelay(10);
3675
3676 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3677 tmp1++;
3678 tmp1 >>= 9;
3679
3680 for (i = 0; i < 16; i++) {
3681 radio78 = ((flip_4bit(i) << 1) | 0x20);
3682 b43_radio_write16(dev, 0x78, radio78);
3683 udelay(10);
3684 for (j = 0; j < 16; j++) {
3685 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
3686 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
3687 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
3688 if (phy->gmode || phy->rev >= 2) {
3689 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3690 radio2050_rfover_val(dev,
3691 B43_PHY_RFOVERVAL,
3692 LPD(1, 0,
3693 1)));
3694 }
3695 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3696 udelay(10);
3697 if (phy->gmode || phy->rev >= 2) {
3698 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3699 radio2050_rfover_val(dev,
3700 B43_PHY_RFOVERVAL,
3701 LPD(1, 0,
3702 1)));
3703 }
3704 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
3705 udelay(10);
3706 if (phy->gmode || phy->rev >= 2) {
3707 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3708 radio2050_rfover_val(dev,
3709 B43_PHY_RFOVERVAL,
3710 LPD(1, 0,
3711 0)));
3712 }
3713 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
3714 udelay(10);
3715 tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
3716 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
3717 if (phy->gmode || phy->rev >= 2) {
3718 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3719 radio2050_rfover_val(dev,
3720 B43_PHY_RFOVERVAL,
3721 LPD(1, 0,
3722 1)));
3723 }
3724 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
3725 }
3726 tmp2++;
3727 tmp2 >>= 8;
3728 if (tmp1 < tmp2)
3729 break;
3730 }
3731
3732 /* Restore the registers */
3733 b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
3734 b43_radio_write16(dev, 0x51, sav.radio_51);
3735 b43_radio_write16(dev, 0x52, sav.radio_52);
3736 b43_radio_write16(dev, 0x43, sav.radio_43);
3737 b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
3738 b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
3739 b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
3740 b43_write16(dev, 0x3E6, sav.reg_3E6);
3741 if (phy->analog != 0)
3742 b43_write16(dev, 0x3F4, sav.reg_3F4);
3743 b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
3744 b43_synth_pu_workaround(dev, phy->channel);
3745 if (phy->type == B43_PHYTYPE_B) {
3746 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
3747 b43_write16(dev, 0x3EC, sav.reg_3EC);
3748 } else if (phy->gmode) {
3749 b43_write16(dev, B43_MMIO_PHY_RADIO,
3750 b43_read16(dev, B43_MMIO_PHY_RADIO)
3751 & 0x7FFF);
3752 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
3753 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
3754 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
3755 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
3756 sav.phy_analogoverval);
3757 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
3758 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
3759 if (has_loopback_gain(phy)) {
3760 b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
3761 b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
3762 }
3763 }
3764 if (i > 15)
3765 ret = radio78;
3766 else
3767 ret = rcc;
3768
3769 return ret;
3770 }
3771
3772 void b43_radio_init2060(struct b43_wldev *dev)
3773 {
3774 int err;
3775
3776 b43_radio_write16(dev, 0x0004, 0x00C0);
3777 b43_radio_write16(dev, 0x0005, 0x0008);
3778 b43_radio_write16(dev, 0x0009, 0x0040);
3779 b43_radio_write16(dev, 0x0005, 0x00AA);
3780 b43_radio_write16(dev, 0x0032, 0x008F);
3781 b43_radio_write16(dev, 0x0006, 0x008F);
3782 b43_radio_write16(dev, 0x0034, 0x008F);
3783 b43_radio_write16(dev, 0x002C, 0x0007);
3784 b43_radio_write16(dev, 0x0082, 0x0080);
3785 b43_radio_write16(dev, 0x0080, 0x0000);
3786 b43_radio_write16(dev, 0x003F, 0x00DA);
3787 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
3788 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
3789 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
3790 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
3791 msleep(1); /* delay 400usec */
3792
3793 b43_radio_write16(dev, 0x0081,
3794 (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
3795 msleep(1); /* delay 400usec */
3796
3797 b43_radio_write16(dev, 0x0005,
3798 (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
3799 b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
3800 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
3801 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
3802 b43_radio_write16(dev, 0x0081,
3803 (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
3804 b43_radio_write16(dev, 0x0005,
3805 (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
3806 b43_phy_write(dev, 0x0063, 0xDDC6);
3807 b43_phy_write(dev, 0x0069, 0x07BE);
3808 b43_phy_write(dev, 0x006A, 0x0000);
3809
3810 err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_A, 0);
3811 B43_WARN_ON(err);
3812
3813 msleep(1);
3814 }
3815
3816 static inline u16 freq_r3A_value(u16 frequency)
3817 {
3818 u16 value;
3819
3820 if (frequency < 5091)
3821 value = 0x0040;
3822 else if (frequency < 5321)
3823 value = 0x0000;
3824 else if (frequency < 5806)
3825 value = 0x0080;
3826 else
3827 value = 0x0040;
3828
3829 return value;
3830 }
3831
3832 void b43_radio_set_tx_iq(struct b43_wldev *dev)
3833 {
3834 static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
3835 static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
3836 u16 tmp = b43_radio_read16(dev, 0x001E);
3837 int i, j;
3838
3839 for (i = 0; i < 5; i++) {
3840 for (j = 0; j < 5; j++) {
3841 if (tmp == (data_high[i] << 4 | data_low[j])) {
3842 b43_phy_write(dev, 0x0069,
3843 (i - j) << 8 | 0x00C0);
3844 return;
3845 }
3846 }
3847 }
3848 }
3849
3850 int b43_radio_selectchannel(struct b43_wldev *dev,
3851 u8 channel, int synthetic_pu_workaround)
3852 {
3853 struct b43_phy *phy = &dev->phy;
3854 u16 r8, tmp;
3855 u16 freq;
3856 u16 channelcookie;
3857
3858 if (channel == 0xFF) {
3859 switch (phy->type) {
3860 case B43_PHYTYPE_A:
3861 channel = B43_DEFAULT_CHANNEL_A;
3862 break;
3863 case B43_PHYTYPE_B:
3864 case B43_PHYTYPE_G:
3865 channel = B43_DEFAULT_CHANNEL_BG;
3866 break;
3867 default:
3868 B43_WARN_ON(1);
3869 }
3870 }
3871
3872 /* First we set the channel radio code to prevent the
3873 * firmware from sending ghost packets.
3874 */
3875 channelcookie = channel;
3876 if (phy->type == B43_PHYTYPE_A)
3877 channelcookie |= 0x100;
3878 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
3879
3880 if (phy->type == B43_PHYTYPE_A) {
3881 if (channel > 200)
3882 return -EINVAL;
3883 freq = channel2freq_a(channel);
3884
3885 r8 = b43_radio_read16(dev, 0x0008);
3886 b43_write16(dev, 0x03F0, freq);
3887 b43_radio_write16(dev, 0x0008, r8);
3888
3889 //TODO: write max channel TX power? to Radio 0x2D
3890 tmp = b43_radio_read16(dev, 0x002E);
3891 tmp &= 0x0080;
3892 //TODO: OR tmp with the Power out estimation for this channel?
3893 b43_radio_write16(dev, 0x002E, tmp);
3894
3895 if (freq >= 4920 && freq <= 5500) {
3896 /*
3897 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
3898 * = (freq * 0.025862069
3899 */
3900 r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
3901 }
3902 b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
3903 b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
3904 b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
3905 b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
3906 & 0x000F) | (r8 << 4));
3907 b43_radio_write16(dev, 0x002A, (r8 << 4));
3908 b43_radio_write16(dev, 0x002B, (r8 << 4));
3909 b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
3910 & 0x00F0) | (r8 << 4));
3911 b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
3912 & 0xFF0F) | 0x00B0);
3913 b43_radio_write16(dev, 0x0035, 0x00AA);
3914 b43_radio_write16(dev, 0x0036, 0x0085);
3915 b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
3916 & 0xFF20) |
3917 freq_r3A_value(freq));
3918 b43_radio_write16(dev, 0x003D,
3919 b43_radio_read16(dev, 0x003D) & 0x00FF);
3920 b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
3921 & 0xFF7F) | 0x0080);
3922 b43_radio_write16(dev, 0x0035,
3923 b43_radio_read16(dev, 0x0035) & 0xFFEF);
3924 b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
3925 & 0xFFEF) | 0x0010);
3926 b43_radio_set_tx_iq(dev);
3927 //TODO: TSSI2dbm workaround
3928 b43_phy_xmitpower(dev); //FIXME correct?
3929 } else {
3930 if ((channel < 1) || (channel > 14))
3931 return -EINVAL;
3932
3933 if (synthetic_pu_workaround)
3934 b43_synth_pu_workaround(dev, channel);
3935
3936 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
3937
3938 if (channel == 14) {
3939 if (dev->dev->bus->sprom.country_code ==
3940 SSB_SPROM1CCODE_JAPAN)
3941 b43_hf_write(dev,
3942 b43_hf_read(dev) & ~B43_HF_ACPR);
3943 else
3944 b43_hf_write(dev,
3945 b43_hf_read(dev) | B43_HF_ACPR);
3946 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3947 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3948 | (1 << 11));
3949 } else {
3950 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
3951 b43_read16(dev, B43_MMIO_CHANNEL_EXT)
3952 & 0xF7BF);
3953 }
3954 }
3955
3956 phy->channel = channel;
3957 /* Wait for the radio to tune to the channel and stabilize. */
3958 msleep(8);
3959
3960 return 0;
3961 }
3962
3963 void b43_radio_turn_on(struct b43_wldev *dev)
3964 {
3965 struct b43_phy *phy = &dev->phy;
3966 int err;
3967 u8 channel;
3968
3969 might_sleep();
3970
3971 if (phy->radio_on)
3972 return;
3973
3974 switch (phy->type) {
3975 case B43_PHYTYPE_A:
3976 b43_radio_write16(dev, 0x0004, 0x00C0);
3977 b43_radio_write16(dev, 0x0005, 0x0008);
3978 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) & 0xFFF7);
3979 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) & 0xFFF7);
3980 b43_radio_init2060(dev);
3981 break;
3982 case B43_PHYTYPE_B:
3983 case B43_PHYTYPE_G:
3984 b43_phy_write(dev, 0x0015, 0x8000);
3985 b43_phy_write(dev, 0x0015, 0xCC00);
3986 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
3987 if (phy->radio_off_context.valid) {
3988 /* Restore the RFover values. */
3989 b43_phy_write(dev, B43_PHY_RFOVER,
3990 phy->radio_off_context.rfover);
3991 b43_phy_write(dev, B43_PHY_RFOVERVAL,
3992 phy->radio_off_context.rfoverval);
3993 phy->radio_off_context.valid = 0;
3994 }
3995 channel = phy->channel;
3996 err = b43_radio_selectchannel(dev, B43_DEFAULT_CHANNEL_BG, 1);
3997 err |= b43_radio_selectchannel(dev, channel, 0);
3998 B43_WARN_ON(err);
3999 break;
4000 default:
4001 B43_WARN_ON(1);
4002 }
4003 phy->radio_on = 1;
4004 }
4005
4006 void b43_radio_turn_off(struct b43_wldev *dev, bool force)
4007 {
4008 struct b43_phy *phy = &dev->phy;
4009
4010 if (!phy->radio_on && !force)
4011 return;
4012
4013 if (phy->type == B43_PHYTYPE_A) {
4014 b43_radio_write16(dev, 0x0004, 0x00FF);
4015 b43_radio_write16(dev, 0x0005, 0x00FB);
4016 b43_phy_write(dev, 0x0010, b43_phy_read(dev, 0x0010) | 0x0008);
4017 b43_phy_write(dev, 0x0011, b43_phy_read(dev, 0x0011) | 0x0008);
4018 }
4019 if (phy->type == B43_PHYTYPE_G && dev->dev->id.revision >= 5) {
4020 u16 rfover, rfoverval;
4021
4022 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
4023 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
4024 if (!force) {
4025 phy->radio_off_context.rfover = rfover;
4026 phy->radio_off_context.rfoverval = rfoverval;
4027 phy->radio_off_context.valid = 1;
4028 }
4029 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
4030 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
4031 } else
4032 b43_phy_write(dev, 0x0015, 0xAA00);
4033 phy->radio_on = 0;
4034 }
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