drivers/net/wireless/b43/phy.h

   1 #ifndef B43_PHY_H_
   2 #define B43_PHY_H_
   3
   4 #include <linux/types.h>
   5
   6 struct b43_wldev;
   7 struct b43_phy;
   8
   9 /*** PHY Registers ***/
  10
  11 /* Routing */
  12 #define B43_PHYROUTE_OFDM_GPHY          0x0400 /* OFDM register routing for G-PHYs */
  13 #define B43_PHYROUTE_EXT_GPHY           0x0800 /* Extended G-PHY registers */
  14 #define B43_PHYROUTE_N_BMODE            0x3000 /* N-PHY BMODE registers */
  15
  16 /* Base registers. */
  17 #define B43_PHY_BASE(reg)               (reg)
  18 /* N-PHY registers. */
  19 #define B43_PHY_N(reg)                  (reg)
  20 /* OFDM (A) registers of a G-PHY */
  21 #define B43_PHY_OFDM(reg)               ((reg) | B43_PHYROUTE_OFDM_GPHY)
  22 /* Extended G-PHY registers */
  23 #define B43_PHY_EXTG(reg)               ((reg) | B43_PHYROUTE_EXT_GPHY)
  24
  25 /* OFDM (A) PHY Registers */
  26 #define B43_PHY_VERSION_OFDM            B43_PHY_OFDM(0x00)      /* Versioning register for A-PHY */
  27 #define B43_PHY_BBANDCFG                B43_PHY_OFDM(0x01)      /* Baseband config */
  28 #define  B43_PHY_BBANDCFG_RXANT         0x180   /* RX Antenna selection */
  29 #define  B43_PHY_BBANDCFG_RXANT_SHIFT   7
  30 #define B43_PHY_PWRDOWN                 B43_PHY_OFDM(0x03)      /* Powerdown */
  31 #define B43_PHY_CRSTHRES1_R1            B43_PHY_OFDM(0x06)      /* CRS Threshold 1 (phy.rev 1 only) */
  32 #define B43_PHY_LNAHPFCTL               B43_PHY_OFDM(0x1C)      /* LNA/HPF control */
  33 #define B43_PHY_LPFGAINCTL              B43_PHY_OFDM(0x20)      /* LPF Gain control */
  34 #define B43_PHY_ADIVRELATED             B43_PHY_OFDM(0x27)      /* FIXME rename */
  35 #define B43_PHY_CRS0                    B43_PHY_OFDM(0x29)
  36 #define  B43_PHY_CRS0_EN                0x4000
  37 #define B43_PHY_PEAK_COUNT              B43_PHY_OFDM(0x30)
  38 #define B43_PHY_ANTDWELL                B43_PHY_OFDM(0x2B)      /* Antenna dwell */
  39 #define  B43_PHY_ANTDWELL_AUTODIV1      0x0100  /* Automatic RX diversity start antenna */
  40 #define B43_PHY_ENCORE                  B43_PHY_OFDM(0x49)      /* "Encore" (RangeMax / BroadRange) */
  41 #define  B43_PHY_ENCORE_EN              0x0200  /* Encore enable */
  42 #define B43_PHY_LMS                     B43_PHY_OFDM(0x55)
  43 #define B43_PHY_OFDM61                  B43_PHY_OFDM(0x61)      /* FIXME rename */
  44 #define  B43_PHY_OFDM61_10              0x0010  /* FIXME rename */
  45 #define B43_PHY_IQBAL                   B43_PHY_OFDM(0x69)      /* I/Q balance */
  46 #define B43_PHY_BBTXDC_BIAS             B43_PHY_OFDM(0x6B)      /* Baseband TX DC bias */
  47 #define B43_PHY_OTABLECTL               B43_PHY_OFDM(0x72)      /* OFDM table control (see below) */
  48 #define  B43_PHY_OTABLEOFF              0x03FF  /* OFDM table offset (see below) */
  49 #define  B43_PHY_OTABLENR               0xFC00  /* OFDM table number (see below) */
  50 #define  B43_PHY_OTABLENR_SHIFT         10
  51 #define B43_PHY_OTABLEI                 B43_PHY_OFDM(0x73)      /* OFDM table data I */
  52 #define B43_PHY_OTABLEQ                 B43_PHY_OFDM(0x74)      /* OFDM table data Q */
  53 #define B43_PHY_HPWR_TSSICTL            B43_PHY_OFDM(0x78)      /* Hardware power TSSI control */
  54 #define B43_PHY_ADCCTL                  B43_PHY_OFDM(0x7A)      /* ADC control */
  55 #define B43_PHY_IDLE_TSSI               B43_PHY_OFDM(0x7B)
  56 #define B43_PHY_A_TEMP_SENSE            B43_PHY_OFDM(0x7C)      /* A PHY temperature sense */
  57 #define B43_PHY_NRSSITHRES              B43_PHY_OFDM(0x8A)      /* NRSSI threshold */
  58 #define B43_PHY_ANTWRSETT               B43_PHY_OFDM(0x8C)      /* Antenna WR settle */
  59 #define  B43_PHY_ANTWRSETT_ARXDIV       0x2000  /* Automatic RX diversity enabled */
  60 #define B43_PHY_CLIPPWRDOWNT            B43_PHY_OFDM(0x93)      /* Clip powerdown threshold */
  61 #define B43_PHY_OFDM9B                  B43_PHY_OFDM(0x9B)      /* FIXME rename */
  62 #define B43_PHY_N1P1GAIN                B43_PHY_OFDM(0xA0)
  63 #define B43_PHY_P1P2GAIN                B43_PHY_OFDM(0xA1)
  64 #define B43_PHY_N1N2GAIN                B43_PHY_OFDM(0xA2)
  65 #define B43_PHY_CLIPTHRES               B43_PHY_OFDM(0xA3)
  66 #define B43_PHY_CLIPN1P2THRES           B43_PHY_OFDM(0xA4)
  67 #define B43_PHY_CCKSHIFTBITS_WA         B43_PHY_OFDM(0xA5)      /* CCK shiftbits workaround, FIXME rename */
  68 #define B43_PHY_CCKSHIFTBITS            B43_PHY_OFDM(0xA7)      /* FIXME rename */
  69 #define B43_PHY_DIVSRCHIDX              B43_PHY_OFDM(0xA8)      /* Divider search gain/index */
  70 #define B43_PHY_CLIPP2THRES             B43_PHY_OFDM(0xA9)
  71 #define B43_PHY_CLIPP3THRES             B43_PHY_OFDM(0xAA)
  72 #define B43_PHY_DIVP1P2GAIN             B43_PHY_OFDM(0xAB)
  73 #define B43_PHY_DIVSRCHGAINBACK         B43_PHY_OFDM(0xAD)      /* Divider search gain back */
  74 #define B43_PHY_DIVSRCHGAINCHNG         B43_PHY_OFDM(0xAE)      /* Divider search gain change */
  75 #define B43_PHY_CRSTHRES1               B43_PHY_OFDM(0xC0)      /* CRS Threshold 1 (phy.rev >= 2 only) */
  76 #define B43_PHY_CRSTHRES2               B43_PHY_OFDM(0xC1)      /* CRS Threshold 2 (phy.rev >= 2 only) */
  77 #define B43_PHY_TSSIP_LTBASE            B43_PHY_OFDM(0x380)     /* TSSI power lookup table base */
  78 #define B43_PHY_DC_LTBASE               B43_PHY_OFDM(0x3A0)     /* DC lookup table base */
  79 #define B43_PHY_GAIN_LTBASE             B43_PHY_OFDM(0x3C0)     /* Gain lookup table base */
  80
  81 /* CCK (B) PHY Registers */
  82 #define B43_PHY_VERSION_CCK             B43_PHY_BASE(0x00)      /* Versioning register for B-PHY */
  83 #define B43_PHY_CCKBBANDCFG             B43_PHY_BASE(0x01)      /* Contains antenna 0/1 control bit */
  84 #define B43_PHY_PGACTL                  B43_PHY_BASE(0x15)      /* PGA control */
  85 #define  B43_PHY_PGACTL_LPF             0x1000  /* Low pass filter (?) */
  86 #define  B43_PHY_PGACTL_LOWBANDW        0x0040  /* Low bandwidth flag */
  87 #define  B43_PHY_PGACTL_UNKNOWN         0xEFA0
  88 #define B43_PHY_FBCTL1                  B43_PHY_BASE(0x18)      /* Frequency bandwidth control 1 */
  89 #define B43_PHY_ITSSI                   B43_PHY_BASE(0x29)      /* Idle TSSI */
  90 #define B43_PHY_LO_LEAKAGE              B43_PHY_BASE(0x2D)      /* Measured LO leakage */
  91 #define B43_PHY_ENERGY                  B43_PHY_BASE(0x33)      /* Energy */
  92 #define B43_PHY_SYNCCTL                 B43_PHY_BASE(0x35)
  93 #define B43_PHY_FBCTL2                  B43_PHY_BASE(0x38)      /* Frequency bandwidth control 2 */
  94 #define B43_PHY_DACCTL                  B43_PHY_BASE(0x60)      /* DAC control */
  95 #define B43_PHY_RCCALOVER               B43_PHY_BASE(0x78)      /* RC calibration override */
  96
  97 /* Extended G-PHY Registers */
  98 #define B43_PHY_CLASSCTL                B43_PHY_EXTG(0x02)      /* Classify control */
  99 #define B43_PHY_GTABCTL                 B43_PHY_EXTG(0x03)      /* G-PHY table control (see below) */
 100 #define  B43_PHY_GTABOFF                0x03FF  /* G-PHY table offset (see below) */
 101 #define  B43_PHY_GTABNR                 0xFC00  /* G-PHY table number (see below) */
 102 #define  B43_PHY_GTABNR_SHIFT           10
 103 #define B43_PHY_GTABDATA                B43_PHY_EXTG(0x04)      /* G-PHY table data */
 104 #define B43_PHY_LO_MASK                 B43_PHY_EXTG(0x0F)      /* Local Oscillator control mask */
 105 #define B43_PHY_LO_CTL                  B43_PHY_EXTG(0x10)      /* Local Oscillator control */
 106 #define B43_PHY_RFOVER                  B43_PHY_EXTG(0x11)      /* RF override */
 107 #define B43_PHY_RFOVERVAL               B43_PHY_EXTG(0x12)      /* RF override value */
 108 #define  B43_PHY_RFOVERVAL_EXTLNA       0x8000
 109 #define  B43_PHY_RFOVERVAL_LNA          0x7000
 110 #define  B43_PHY_RFOVERVAL_LNA_SHIFT    12
 111 #define  B43_PHY_RFOVERVAL_PGA          0x0F00
 112 #define  B43_PHY_RFOVERVAL_PGA_SHIFT    8
 113 #define  B43_PHY_RFOVERVAL_UNK          0x0010  /* Unknown, always set. */
 114 #define  B43_PHY_RFOVERVAL_TRSWRX       0x00E0
 115 #define  B43_PHY_RFOVERVAL_BW           0x0003  /* Bandwidth flags */
 116 #define   B43_PHY_RFOVERVAL_BW_LPF      0x0001  /* Low Pass Filter */
 117 #define   B43_PHY_RFOVERVAL_BW_LBW      0x0002  /* Low Bandwidth (when set), high when unset */
 118 #define B43_PHY_ANALOGOVER              B43_PHY_EXTG(0x14)      /* Analog override */
 119 #define B43_PHY_ANALOGOVERVAL           B43_PHY_EXTG(0x15)      /* Analog override value */
 120
 121 /*** OFDM table numbers ***/
 122 #define B43_OFDMTAB(number, offset)     (((number) << B43_PHY_OTABLENR_SHIFT) | (offset))
 123 #define B43_OFDMTAB_AGC1                B43_OFDMTAB(0x00, 0)
 124 #define B43_OFDMTAB_GAIN0               B43_OFDMTAB(0x00, 0)
 125 #define B43_OFDMTAB_GAINX               B43_OFDMTAB(0x01, 0)    //TODO rename
 126 #define B43_OFDMTAB_GAIN1               B43_OFDMTAB(0x01, 4)
 127 #define B43_OFDMTAB_AGC3                B43_OFDMTAB(0x02, 0)
 128 #define B43_OFDMTAB_GAIN2               B43_OFDMTAB(0x02, 3)
 129 #define B43_OFDMTAB_LNAHPFGAIN1         B43_OFDMTAB(0x03, 0)
 130 #define B43_OFDMTAB_WRSSI               B43_OFDMTAB(0x04, 0)
 131 #define B43_OFDMTAB_LNAHPFGAIN2         B43_OFDMTAB(0x04, 0)
 132 #define B43_OFDMTAB_NOISESCALE          B43_OFDMTAB(0x05, 0)
 133 #define B43_OFDMTAB_AGC2                B43_OFDMTAB(0x06, 0)
 134 #define B43_OFDMTAB_ROTOR               B43_OFDMTAB(0x08, 0)
 135 #define B43_OFDMTAB_ADVRETARD           B43_OFDMTAB(0x09, 0)
 136 #define B43_OFDMTAB_DAC                 B43_OFDMTAB(0x0C, 0)
 137 #define B43_OFDMTAB_DC                  B43_OFDMTAB(0x0E, 7)
 138 #define B43_OFDMTAB_PWRDYN2             B43_OFDMTAB(0x0E, 12)
 139 #define B43_OFDMTAB_LNAGAIN             B43_OFDMTAB(0x0E, 13)
 140 #define B43_OFDMTAB_UNKNOWN_0F          B43_OFDMTAB(0x0F, 0)    //TODO rename
 141 #define B43_OFDMTAB_UNKNOWN_APHY        B43_OFDMTAB(0x0F, 7)    //TODO rename
 142 #define B43_OFDMTAB_LPFGAIN             B43_OFDMTAB(0x0F, 12)
 143 #define B43_OFDMTAB_RSSI                B43_OFDMTAB(0x10, 0)
 144 #define B43_OFDMTAB_UNKNOWN_11          B43_OFDMTAB(0x11, 4)    //TODO rename
 145 #define B43_OFDMTAB_AGC1_R1             B43_OFDMTAB(0x13, 0)
 146 #define B43_OFDMTAB_GAINX_R1            B43_OFDMTAB(0x14, 0)    //TODO remove!
 147 #define B43_OFDMTAB_MINSIGSQ            B43_OFDMTAB(0x14, 0)
 148 #define B43_OFDMTAB_AGC3_R1             B43_OFDMTAB(0x15, 0)
 149 #define B43_OFDMTAB_WRSSI_R1            B43_OFDMTAB(0x15, 4)
 150 #define B43_OFDMTAB_TSSI                B43_OFDMTAB(0x15, 0)
 151 #define B43_OFDMTAB_DACRFPABB           B43_OFDMTAB(0x16, 0)
 152 #define B43_OFDMTAB_DACOFF              B43_OFDMTAB(0x17, 0)
 153 #define B43_OFDMTAB_DCBIAS              B43_OFDMTAB(0x18, 0)
 154
 155 u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
 156 void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
 157                          u16 offset, u16 value);
 158 u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
 159 void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
 160                          u16 offset, u32 value);
 161
 162 /*** G-PHY table numbers */
 163 #define B43_GTAB(number, offset)        (((number) << B43_PHY_GTABNR_SHIFT) | (offset))
 164 #define B43_GTAB_NRSSI                  B43_GTAB(0x00, 0)
 165 #define B43_GTAB_TRFEMW                 B43_GTAB(0x0C, 0x120)
 166 #define B43_GTAB_ORIGTR                 B43_GTAB(0x2E, 0x298)
 167
 168 u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset);        //TODO implement
 169 void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value);   //TODO implement
 170
 171 #define B43_DEFAULT_CHANNEL_A   36
 172 #define B43_DEFAULT_CHANNEL_BG  6
 173
 174 enum {
 175         B43_ANTENNA0,           /* Antenna 0 */
 176         B43_ANTENNA1,           /* Antenna 0 */
 177         B43_ANTENNA_AUTO1,      /* Automatic, starting with antenna 1 */
 178         B43_ANTENNA_AUTO0,      /* Automatic, starting with antenna 0 */
 179
 180         B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
 181         B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
 182 };
 183
 184 enum {
 185         B43_INTERFMODE_NONE,
 186         B43_INTERFMODE_NONWLAN,
 187         B43_INTERFMODE_MANUALWLAN,
 188         B43_INTERFMODE_AUTOWLAN,
 189 };
 190
 191 /* Masks for the different PHY versioning registers. */
 192 #define B43_PHYVER_ANALOG               0xF000
 193 #define B43_PHYVER_ANALOG_SHIFT         12
 194 #define B43_PHYVER_TYPE                 0x0F00
 195 #define B43_PHYVER_TYPE_SHIFT           8
 196 #define B43_PHYVER_VERSION              0x00FF
 197
 198 void b43_raw_phy_lock(struct b43_wldev *dev);
 199 #define b43_phy_lock(dev, flags) \
 200         do {                                    \
 201                 local_irq_save(flags);          \
 202                 b43_raw_phy_lock(dev);  \
 203         } while (0)
 204 void b43_raw_phy_unlock(struct b43_wldev *dev);
 205 #define b43_phy_unlock(dev, flags) \
 206         do {                                    \
 207                 b43_raw_phy_unlock(dev);        \
 208                 local_irq_restore(flags);       \
 209         } while (0)
 210
 211 u16 b43_phy_read(struct b43_wldev *dev, u16 offset);
 212 void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val);
 213
 214 int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev);
 215
 216 void b43_phy_early_init(struct b43_wldev *dev);
 217 int b43_phy_init(struct b43_wldev *dev);
 218
 219 void b43_set_rx_antenna(struct b43_wldev *dev, int antenna);
 220
 221 void b43_phy_xmitpower(struct b43_wldev *dev);
 222 void b43_gphy_dc_lt_init(struct b43_wldev *dev);
 223
 224 /* Returns the boolean whether the board has HardwarePowerControl */
 225 bool b43_has_hardware_pctl(struct b43_phy *phy);
 226 /* Returns the boolean whether "TX Magnification" is enabled. */
 227 #define has_tx_magnification(phy) \
 228         (((phy)->rev >= 2) &&                   \
 229          ((phy)->radio_ver == 0x2050) &&        \
 230          ((phy)->radio_rev == 8))
 231 /* Card uses the loopback gain stuff */
 232 #define has_loopback_gain(phy) \
 233         (((phy)->rev > 1) || ((phy)->gmode))
 234
 235 /* Radio Attenuation (RF Attenuation) */
 236 struct b43_rfatt {
 237         u8 att;                 /* Attenuation value */
 238         bool with_padmix;       /* Flag, PAD Mixer enabled. */
 239 };
 240 struct b43_rfatt_list {
 241         /* Attenuation values list */
 242         const struct b43_rfatt *list;
 243         u8 len;
 244         /* Minimum/Maximum attenuation values */
 245         u8 min_val;
 246         u8 max_val;
 247 };
 248
 249 /* Baseband Attenuation */
 250 struct b43_bbatt {
 251         u8 att;                 /* Attenuation value */
 252 };
 253 struct b43_bbatt_list {
 254         /* Attenuation values list */
 255         const struct b43_bbatt *list;
 256         u8 len;
 257         /* Minimum/Maximum attenuation values */
 258         u8 min_val;
 259         u8 max_val;
 260 };
 261
 262 /* tx_control bits. */
 263 #define B43_TXCTL_PA3DB         0x40    /* PA Gain 3dB */
 264 #define B43_TXCTL_PA2DB         0x20    /* PA Gain 2dB */
 265 #define B43_TXCTL_TXMIX         0x10    /* TX Mixer Gain */
 266
 267 /* Write BasebandAttenuation value to the device. */
 268 void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
 269                                       u16 baseband_attenuation);
 270
 271 extern const u8 b43_radio_channel_codes_bg[];
 272
 273 void b43_radio_lock(struct b43_wldev *dev);
 274 void b43_radio_unlock(struct b43_wldev *dev);
 275
 276 u16 b43_radio_read16(struct b43_wldev *dev, u16 offset);
 277 void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val);
 278
 279 u16 b43_radio_init2050(struct b43_wldev *dev);
 280 void b43_radio_init2060(struct b43_wldev *dev);
 281
 282 void b43_radio_turn_on(struct b43_wldev *dev);
 283 void b43_radio_turn_off(struct b43_wldev *dev, bool force);
 284
 285 int b43_radio_selectchannel(struct b43_wldev *dev, u8 channel,
 286                             int synthetic_pu_workaround);
 287
 288 u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel);
 289 u8 b43_radio_aci_scan(struct b43_wldev *dev);
 290
 291 int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode);
 292
 293 void b43_calc_nrssi_slope(struct b43_wldev *dev);
 294 void b43_calc_nrssi_threshold(struct b43_wldev *dev);
 295 s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset);
 296 void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val);
 297 void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val);
 298 void b43_nrssi_mem_update(struct b43_wldev *dev);
 299
 300 void b43_radio_set_tx_iq(struct b43_wldev *dev);
 301 u16 b43_radio_calibrationvalue(struct b43_wldev *dev);
 302
 303 void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
 304                                      int *_bbatt, int *_rfatt);
 305
 306 void b43_set_txpower_g(struct b43_wldev *dev,
 307                        const struct b43_bbatt *bbatt,
 308                        const struct b43_rfatt *rfatt, u8 tx_control);
 309
 310 #endif /* B43_PHY_H_ */