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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / b43 / phy_n.c
1 /*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23 */
24
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/types.h>
28
29 #include "b43.h"
30 #include "phy_n.h"
31 #include "tables_nphy.h"
32 #include "main.h"
33
34 struct nphy_txgains {
35 u16 txgm[2];
36 u16 pga[2];
37 u16 pad[2];
38 u16 ipa[2];
39 };
40
41 struct nphy_iqcal_params {
42 u16 txgm;
43 u16 pga;
44 u16 pad;
45 u16 ipa;
46 u16 cal_gain;
47 u16 ncorr[5];
48 };
49
50 struct nphy_iq_est {
51 s32 iq0_prod;
52 u32 i0_pwr;
53 u32 q0_pwr;
54 s32 iq1_prod;
55 u32 i1_pwr;
56 u32 q1_pwr;
57 };
58
59 enum b43_nphy_rf_sequence {
60 B43_RFSEQ_RX2TX,
61 B43_RFSEQ_TX2RX,
62 B43_RFSEQ_RESET2RX,
63 B43_RFSEQ_UPDATE_GAINH,
64 B43_RFSEQ_UPDATE_GAINL,
65 B43_RFSEQ_UPDATE_GAINU,
66 };
67
68 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
69 u8 *events, u8 *delays, u8 length);
70 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
71 enum b43_nphy_rf_sequence seq);
72 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
73 u16 value, u8 core, bool off);
74 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
75 u16 value, u8 core);
76 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel);
77
78 static inline bool b43_empty_chanspec(struct b43_chanspec *chanspec)
79 {
80 return !chanspec->channel && !chanspec->sideband &&
81 !chanspec->b_width && !chanspec->b_freq;
82 }
83
84 static inline bool b43_eq_chanspecs(struct b43_chanspec *chanspec1,
85 struct b43_chanspec *chanspec2)
86 {
87 return (chanspec1->channel == chanspec2->channel &&
88 chanspec1->sideband == chanspec2->sideband &&
89 chanspec1->b_width == chanspec2->b_width &&
90 chanspec1->b_freq == chanspec2->b_freq);
91 }
92
93 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
94 {//TODO
95 }
96
97 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
98 {//TODO
99 }
100
101 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
102 bool ignore_tssi)
103 {//TODO
104 return B43_TXPWR_RES_DONE;
105 }
106
107 static void b43_chantab_radio_upload(struct b43_wldev *dev,
108 const struct b43_nphy_channeltab_entry_rev2 *e)
109 {
110 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
111 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
112 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
113 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
114 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
115
116 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
117 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
118 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
119 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
120 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
121
122 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
123 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
124 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
125 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
126 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
127
128 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
129 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
130 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
131 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
132 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
133
134 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
135 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
136 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
137 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
138 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
139
140 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
141 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
142 }
143
144 static void b43_chantab_phy_upload(struct b43_wldev *dev,
145 const struct b43_phy_n_sfo_cfg *e)
146 {
147 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
148 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
149 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
150 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
151 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
152 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
153 }
154
155 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
156 {
157 //TODO
158 }
159
160
161 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
162 static void b43_radio_2055_setup(struct b43_wldev *dev,
163 const struct b43_nphy_channeltab_entry_rev2 *e)
164 {
165 B43_WARN_ON(dev->phy.rev >= 3);
166
167 b43_chantab_radio_upload(dev, e);
168 udelay(50);
169 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
170 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
171 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
172 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
173 udelay(300);
174 }
175
176 static void b43_radio_init2055_pre(struct b43_wldev *dev)
177 {
178 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
179 ~B43_NPHY_RFCTL_CMD_PORFORCE);
180 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
181 B43_NPHY_RFCTL_CMD_CHIP0PU |
182 B43_NPHY_RFCTL_CMD_OEPORFORCE);
183 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
184 B43_NPHY_RFCTL_CMD_PORFORCE);
185 }
186
187 static void b43_radio_init2055_post(struct b43_wldev *dev)
188 {
189 struct b43_phy_n *nphy = dev->phy.n;
190 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
191 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
192 int i;
193 u16 val;
194 bool workaround = false;
195
196 if (sprom->revision < 4)
197 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
198 binfo->type != 0x46D ||
199 binfo->rev < 0x41);
200 else
201 workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0);
202
203 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
204 if (workaround) {
205 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
206 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
207 }
208 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
209 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
210 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
211 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
212 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
213 msleep(1);
214 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
215 for (i = 0; i < 200; i++) {
216 val = b43_radio_read(dev, B2055_CAL_COUT2);
217 if (val & 0x80) {
218 i = 0;
219 break;
220 }
221 udelay(10);
222 }
223 if (i)
224 b43err(dev->wl, "radio post init timeout\n");
225 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
226 nphy_channel_switch(dev, dev->phy.channel);
227 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
228 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
229 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
230 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
231 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
232 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
233 if (!nphy->gain_boost) {
234 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
235 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
236 } else {
237 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
238 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
239 }
240 udelay(2);
241 }
242
243 /*
244 * Initialize a Broadcom 2055 N-radio
245 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
246 */
247 static void b43_radio_init2055(struct b43_wldev *dev)
248 {
249 b43_radio_init2055_pre(dev);
250 if (b43_status(dev) < B43_STAT_INITIALIZED)
251 b2055_upload_inittab(dev, 0, 1);
252 else
253 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
254 b43_radio_init2055_post(dev);
255 }
256
257 /*
258 * Initialize a Broadcom 2056 N-radio
259 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
260 */
261 static void b43_radio_init2056(struct b43_wldev *dev)
262 {
263 /* TODO */
264 }
265
266
267 /*
268 * Upload the N-PHY tables.
269 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
270 */
271 static void b43_nphy_tables_init(struct b43_wldev *dev)
272 {
273 if (dev->phy.rev < 3)
274 b43_nphy_rev0_1_2_tables_init(dev);
275 else
276 b43_nphy_rev3plus_tables_init(dev);
277 }
278
279 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
280 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
281 {
282 struct b43_phy_n *nphy = dev->phy.n;
283 enum ieee80211_band band;
284 u16 tmp;
285
286 if (!enable) {
287 nphy->rfctrl_intc1_save = b43_phy_read(dev,
288 B43_NPHY_RFCTL_INTC1);
289 nphy->rfctrl_intc2_save = b43_phy_read(dev,
290 B43_NPHY_RFCTL_INTC2);
291 band = b43_current_band(dev->wl);
292 if (dev->phy.rev >= 3) {
293 if (band == IEEE80211_BAND_5GHZ)
294 tmp = 0x600;
295 else
296 tmp = 0x480;
297 } else {
298 if (band == IEEE80211_BAND_5GHZ)
299 tmp = 0x180;
300 else
301 tmp = 0x120;
302 }
303 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
304 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
305 } else {
306 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
307 nphy->rfctrl_intc1_save);
308 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
309 nphy->rfctrl_intc2_save);
310 }
311 }
312
313 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
314 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
315 {
316 struct b43_phy_n *nphy = dev->phy.n;
317 u16 tmp;
318 enum ieee80211_band band = b43_current_band(dev->wl);
319 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
320 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
321
322 if (dev->phy.rev >= 3) {
323 if (ipa) {
324 tmp = 4;
325 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
326 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
327 }
328
329 tmp = 1;
330 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
331 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
332 }
333 }
334
335 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
336 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
337 {
338 u32 tmslow;
339
340 if (dev->phy.type != B43_PHYTYPE_N)
341 return;
342
343 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
344 if (force)
345 tmslow |= SSB_TMSLOW_FGC;
346 else
347 tmslow &= ~SSB_TMSLOW_FGC;
348 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
349 }
350
351 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
352 static void b43_nphy_reset_cca(struct b43_wldev *dev)
353 {
354 u16 bbcfg;
355
356 b43_nphy_bmac_clock_fgc(dev, 1);
357 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
358 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
359 udelay(1);
360 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
361 b43_nphy_bmac_clock_fgc(dev, 0);
362 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
363 }
364
365 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
366 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
367 {
368 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
369
370 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
371 if (preamble == 1)
372 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
373 else
374 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
375
376 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
377 }
378
379 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
380 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
381 {
382 struct b43_phy_n *nphy = dev->phy.n;
383
384 bool override = false;
385 u16 chain = 0x33;
386
387 if (nphy->txrx_chain == 0) {
388 chain = 0x11;
389 override = true;
390 } else if (nphy->txrx_chain == 1) {
391 chain = 0x22;
392 override = true;
393 }
394
395 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
396 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
397 chain);
398
399 if (override)
400 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
401 B43_NPHY_RFSEQMODE_CAOVER);
402 else
403 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
404 ~B43_NPHY_RFSEQMODE_CAOVER);
405 }
406
407 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
408 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
409 u16 samps, u8 time, bool wait)
410 {
411 int i;
412 u16 tmp;
413
414 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
415 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
416 if (wait)
417 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
418 else
419 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
420
421 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
422
423 for (i = 1000; i; i--) {
424 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
425 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
426 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
427 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
428 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
429 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
430 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
431 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
432
433 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
434 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
435 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
436 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
437 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
438 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
439 return;
440 }
441 udelay(10);
442 }
443 memset(est, 0, sizeof(*est));
444 }
445
446 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
447 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
448 struct b43_phy_n_iq_comp *pcomp)
449 {
450 if (write) {
451 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
452 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
453 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
454 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
455 } else {
456 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
457 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
458 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
459 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
460 }
461 }
462
463 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
464 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
465 {
466 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
467
468 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
469 if (core == 0) {
470 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
471 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
472 } else {
473 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
474 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
475 }
476 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
477 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
478 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
479 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
480 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
481 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
482 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
483 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
484 }
485
486 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
487 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
488 {
489 u8 rxval, txval;
490 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
491
492 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
493 if (core == 0) {
494 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
495 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
496 } else {
497 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
498 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
499 }
500 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
501 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
502 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
503 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
504 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
505 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
506 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
507 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
508
509 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
510 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
511
512 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
513 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
514 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
515 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
516 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
517 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
518 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
519 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
520 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
521
522 if (core == 0) {
523 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
524 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
525 } else {
526 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
527 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
528 }
529
530 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
531 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
532 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
533
534 if (core == 0) {
535 rxval = 1;
536 txval = 8;
537 } else {
538 rxval = 4;
539 txval = 2;
540 }
541 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
542 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
543 }
544
545 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
546 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
547 {
548 int i;
549 s32 iq;
550 u32 ii;
551 u32 qq;
552 int iq_nbits, qq_nbits;
553 int arsh, brsh;
554 u16 tmp, a, b;
555
556 struct nphy_iq_est est;
557 struct b43_phy_n_iq_comp old;
558 struct b43_phy_n_iq_comp new = { };
559 bool error = false;
560
561 if (mask == 0)
562 return;
563
564 b43_nphy_rx_iq_coeffs(dev, false, &old);
565 b43_nphy_rx_iq_coeffs(dev, true, &new);
566 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
567 new = old;
568
569 for (i = 0; i < 2; i++) {
570 if (i == 0 && (mask & 1)) {
571 iq = est.iq0_prod;
572 ii = est.i0_pwr;
573 qq = est.q0_pwr;
574 } else if (i == 1 && (mask & 2)) {
575 iq = est.iq1_prod;
576 ii = est.i1_pwr;
577 qq = est.q1_pwr;
578 } else {
579 B43_WARN_ON(1);
580 continue;
581 }
582
583 if (ii + qq < 2) {
584 error = true;
585 break;
586 }
587
588 iq_nbits = fls(abs(iq));
589 qq_nbits = fls(qq);
590
591 arsh = iq_nbits - 20;
592 if (arsh >= 0) {
593 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
594 tmp = ii >> arsh;
595 } else {
596 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
597 tmp = ii << -arsh;
598 }
599 if (tmp == 0) {
600 error = true;
601 break;
602 }
603 a /= tmp;
604
605 brsh = qq_nbits - 11;
606 if (brsh >= 0) {
607 b = (qq << (31 - qq_nbits));
608 tmp = ii >> brsh;
609 } else {
610 b = (qq << (31 - qq_nbits));
611 tmp = ii << -brsh;
612 }
613 if (tmp == 0) {
614 error = true;
615 break;
616 }
617 b = int_sqrt(b / tmp - a * a) - (1 << 10);
618
619 if (i == 0 && (mask & 0x1)) {
620 if (dev->phy.rev >= 3) {
621 new.a0 = a & 0x3FF;
622 new.b0 = b & 0x3FF;
623 } else {
624 new.a0 = b & 0x3FF;
625 new.b0 = a & 0x3FF;
626 }
627 } else if (i == 1 && (mask & 0x2)) {
628 if (dev->phy.rev >= 3) {
629 new.a1 = a & 0x3FF;
630 new.b1 = b & 0x3FF;
631 } else {
632 new.a1 = b & 0x3FF;
633 new.b1 = a & 0x3FF;
634 }
635 }
636 }
637
638 if (error)
639 new = old;
640
641 b43_nphy_rx_iq_coeffs(dev, true, &new);
642 }
643
644 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
645 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
646 {
647 u16 array[4];
648 int i;
649
650 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
651 for (i = 0; i < 4; i++)
652 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
653
654 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
655 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
656 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
657 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
658 }
659
660 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
661 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
662 {
663 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
664 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
665 }
666
667 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
668 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
669 {
670 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
671 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
672 }
673
674 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
675 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
676 {
677 if (dev->phy.rev >= 3) {
678 if (!init)
679 return;
680 if (0 /* FIXME */) {
681 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
682 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
683 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
684 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
685 }
686 } else {
687 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
688 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
689
690 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
691 0xFC00);
692 b43_write32(dev, B43_MMIO_MACCTL,
693 b43_read32(dev, B43_MMIO_MACCTL) &
694 ~B43_MACCTL_GPOUTSMSK);
695 b43_write16(dev, B43_MMIO_GPIO_MASK,
696 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
697 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
698 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
699
700 if (init) {
701 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
702 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
703 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
704 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
705 }
706 }
707 }
708
709 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
710 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
711 {
712 u16 tmp;
713
714 if (dev->dev->id.revision == 16)
715 b43_mac_suspend(dev);
716
717 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
718 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
719 B43_NPHY_CLASSCTL_WAITEDEN);
720 tmp &= ~mask;
721 tmp |= (val & mask);
722 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
723
724 if (dev->dev->id.revision == 16)
725 b43_mac_enable(dev);
726
727 return tmp;
728 }
729
730 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
731 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
732 {
733 struct b43_phy *phy = &dev->phy;
734 struct b43_phy_n *nphy = phy->n;
735
736 if (enable) {
737 u16 clip[] = { 0xFFFF, 0xFFFF };
738 if (nphy->deaf_count++ == 0) {
739 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
740 b43_nphy_classifier(dev, 0x7, 0);
741 b43_nphy_read_clip_detection(dev, nphy->clip_state);
742 b43_nphy_write_clip_detection(dev, clip);
743 }
744 b43_nphy_reset_cca(dev);
745 } else {
746 if (--nphy->deaf_count == 0) {
747 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
748 b43_nphy_write_clip_detection(dev, nphy->clip_state);
749 }
750 }
751 }
752
753 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
754 static void b43_nphy_stop_playback(struct b43_wldev *dev)
755 {
756 struct b43_phy_n *nphy = dev->phy.n;
757 u16 tmp;
758
759 if (nphy->hang_avoid)
760 b43_nphy_stay_in_carrier_search(dev, 1);
761
762 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
763 if (tmp & 0x1)
764 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
765 else if (tmp & 0x2)
766 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
767
768 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
769
770 if (nphy->bb_mult_save & 0x80000000) {
771 tmp = nphy->bb_mult_save & 0xFFFF;
772 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
773 nphy->bb_mult_save = 0;
774 }
775
776 if (nphy->hang_avoid)
777 b43_nphy_stay_in_carrier_search(dev, 0);
778 }
779
780 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
781 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
782 {
783 struct b43_phy_n *nphy = dev->phy.n;
784
785 u8 channel = nphy->radio_chanspec.channel;
786 int tone[2] = { 57, 58 };
787 u32 noise[2] = { 0x3FF, 0x3FF };
788
789 B43_WARN_ON(dev->phy.rev < 3);
790
791 if (nphy->hang_avoid)
792 b43_nphy_stay_in_carrier_search(dev, 1);
793
794 if (nphy->gband_spurwar_en) {
795 /* TODO: N PHY Adjust Analog Pfbw (7) */
796 if (channel == 11 && dev->phy.is_40mhz)
797 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
798 else
799 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
800 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
801 }
802
803 if (nphy->aband_spurwar_en) {
804 if (channel == 54) {
805 tone[0] = 0x20;
806 noise[0] = 0x25F;
807 } else if (channel == 38 || channel == 102 || channel == 118) {
808 if (0 /* FIXME */) {
809 tone[0] = 0x20;
810 noise[0] = 0x21F;
811 } else {
812 tone[0] = 0;
813 noise[0] = 0;
814 }
815 } else if (channel == 134) {
816 tone[0] = 0x20;
817 noise[0] = 0x21F;
818 } else if (channel == 151) {
819 tone[0] = 0x10;
820 noise[0] = 0x23F;
821 } else if (channel == 153 || channel == 161) {
822 tone[0] = 0x30;
823 noise[0] = 0x23F;
824 } else {
825 tone[0] = 0;
826 noise[0] = 0;
827 }
828
829 if (!tone[0] && !noise[0])
830 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
831 else
832 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
833 }
834
835 if (nphy->hang_avoid)
836 b43_nphy_stay_in_carrier_search(dev, 0);
837 }
838
839 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
840 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
841 {
842 struct b43_phy_n *nphy = dev->phy.n;
843
844 u8 i;
845 s16 tmp;
846 u16 data[4];
847 s16 gain[2];
848 u16 minmax[2];
849 u16 lna_gain[4] = { -2, 10, 19, 25 };
850
851 if (nphy->hang_avoid)
852 b43_nphy_stay_in_carrier_search(dev, 1);
853
854 if (nphy->gain_boost) {
855 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
856 gain[0] = 6;
857 gain[1] = 6;
858 } else {
859 tmp = 40370 - 315 * nphy->radio_chanspec.channel;
860 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
861 tmp = 23242 - 224 * nphy->radio_chanspec.channel;
862 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
863 }
864 } else {
865 gain[0] = 0;
866 gain[1] = 0;
867 }
868
869 for (i = 0; i < 2; i++) {
870 if (nphy->elna_gain_config) {
871 data[0] = 19 + gain[i];
872 data[1] = 25 + gain[i];
873 data[2] = 25 + gain[i];
874 data[3] = 25 + gain[i];
875 } else {
876 data[0] = lna_gain[0] + gain[i];
877 data[1] = lna_gain[1] + gain[i];
878 data[2] = lna_gain[2] + gain[i];
879 data[3] = lna_gain[3] + gain[i];
880 }
881 b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data);
882
883 minmax[i] = 23 + gain[i];
884 }
885
886 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
887 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
888 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
889 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
890
891 if (nphy->hang_avoid)
892 b43_nphy_stay_in_carrier_search(dev, 0);
893 }
894
895 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
896 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
897 {
898 struct b43_phy_n *nphy = dev->phy.n;
899 u8 i, j;
900 u8 code;
901
902 /* TODO: for PHY >= 3
903 s8 *lna1_gain, *lna2_gain;
904 u8 *gain_db, *gain_bits;
905 u16 *rfseq_init;
906 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
907 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
908 */
909
910 u8 rfseq_events[3] = { 6, 8, 7 };
911 u8 rfseq_delays[3] = { 10, 30, 1 };
912
913 if (dev->phy.rev >= 3) {
914 /* TODO */
915 } else {
916 /* Set Clip 2 detect */
917 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
918 B43_NPHY_C1_CGAINI_CL2DETECT);
919 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
920 B43_NPHY_C2_CGAINI_CL2DETECT);
921
922 /* Set narrowband clip threshold */
923 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
924 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
925
926 if (!dev->phy.is_40mhz) {
927 /* Set dwell lengths */
928 b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
929 b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
930 b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
931 b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
932 }
933
934 /* Set wideband clip 2 threshold */
935 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
936 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
937 21);
938 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
939 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
940 21);
941
942 if (!dev->phy.is_40mhz) {
943 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
944 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
945 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
946 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
947 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
948 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
949 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
950 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
951 }
952
953 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
954
955 if (nphy->gain_boost) {
956 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
957 dev->phy.is_40mhz)
958 code = 4;
959 else
960 code = 5;
961 } else {
962 code = dev->phy.is_40mhz ? 6 : 7;
963 }
964
965 /* Set HPVGA2 index */
966 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
967 ~B43_NPHY_C1_INITGAIN_HPVGA2,
968 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
969 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
970 ~B43_NPHY_C2_INITGAIN_HPVGA2,
971 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
972
973 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
974 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
975 (code << 8 | 0x7C));
976 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
977 (code << 8 | 0x7C));
978
979 b43_nphy_adjust_lna_gain_table(dev);
980
981 if (nphy->elna_gain_config) {
982 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
983 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
984 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
985 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
986 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
987
988 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
989 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
990 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
991 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
992 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
993
994 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
995 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
996 (code << 8 | 0x74));
997 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
998 (code << 8 | 0x74));
999 }
1000
1001 if (dev->phy.rev == 2) {
1002 for (i = 0; i < 4; i++) {
1003 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1004 (0x0400 * i) + 0x0020);
1005 for (j = 0; j < 21; j++)
1006 b43_phy_write(dev,
1007 B43_NPHY_TABLE_DATALO, 3 * j);
1008 }
1009
1010 b43_nphy_set_rf_sequence(dev, 5,
1011 rfseq_events, rfseq_delays, 3);
1012 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1013 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1014 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1015
1016 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1017 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1018 0xFF80, 4);
1019 }
1020 }
1021 }
1022
1023 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1024 static void b43_nphy_workarounds(struct b43_wldev *dev)
1025 {
1026 struct ssb_bus *bus = dev->dev->bus;
1027 struct b43_phy *phy = &dev->phy;
1028 struct b43_phy_n *nphy = phy->n;
1029
1030 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1031 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1032
1033 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1034 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1035
1036 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1037 b43_nphy_classifier(dev, 1, 0);
1038 else
1039 b43_nphy_classifier(dev, 1, 1);
1040
1041 if (nphy->hang_avoid)
1042 b43_nphy_stay_in_carrier_search(dev, 1);
1043
1044 b43_phy_set(dev, B43_NPHY_IQFLIP,
1045 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1046
1047 if (dev->phy.rev >= 3) {
1048 /* TODO */
1049 } else {
1050 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1051 nphy->band5g_pwrgain) {
1052 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1053 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1054 } else {
1055 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1056 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1057 }
1058
1059 /* TODO: convert to b43_ntab_write? */
1060 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
1061 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1062 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
1063 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1064 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
1065 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1066 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
1067 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1068
1069 if (dev->phy.rev < 2) {
1070 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1071 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1072 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1073 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1074 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1075 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1076 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1077 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1078 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1079 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1080 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1081 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1082 }
1083
1084 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1085 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1086 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1087 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1088
1089 if (bus->sprom.boardflags2_lo & 0x100 &&
1090 bus->boardinfo.type == 0x8B) {
1091 delays1[0] = 0x1;
1092 delays1[5] = 0x14;
1093 }
1094 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1095 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1096
1097 b43_nphy_gain_ctrl_workarounds(dev);
1098
1099 if (dev->phy.rev < 2) {
1100 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1101 b43_hf_write(dev, b43_hf_read(dev) |
1102 B43_HF_MLADVW);
1103 } else if (dev->phy.rev == 2) {
1104 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1105 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1106 }
1107
1108 if (dev->phy.rev < 2)
1109 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1110 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1111
1112 /* Set phase track alpha and beta */
1113 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1114 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1115 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1116 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1117 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1118 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1119
1120 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1121 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1122 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1123 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1124 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1125
1126 if (dev->phy.rev == 2)
1127 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1128 B43_NPHY_FINERX2_CGC_DECGC);
1129 }
1130
1131 if (nphy->hang_avoid)
1132 b43_nphy_stay_in_carrier_search(dev, 0);
1133 }
1134
1135 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1136 static int b43_nphy_load_samples(struct b43_wldev *dev,
1137 struct b43_c32 *samples, u16 len) {
1138 struct b43_phy_n *nphy = dev->phy.n;
1139 u16 i;
1140 u32 *data;
1141
1142 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1143 if (!data) {
1144 b43err(dev->wl, "allocation for samples loading failed\n");
1145 return -ENOMEM;
1146 }
1147 if (nphy->hang_avoid)
1148 b43_nphy_stay_in_carrier_search(dev, 1);
1149
1150 for (i = 0; i < len; i++) {
1151 data[i] = (samples[i].i & 0x3FF << 10);
1152 data[i] |= samples[i].q & 0x3FF;
1153 }
1154 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1155
1156 kfree(data);
1157 if (nphy->hang_avoid)
1158 b43_nphy_stay_in_carrier_search(dev, 0);
1159 return 0;
1160 }
1161
1162 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1163 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1164 bool test)
1165 {
1166 int i;
1167 u16 bw, len, rot, angle;
1168 struct b43_c32 *samples;
1169
1170
1171 bw = (dev->phy.is_40mhz) ? 40 : 20;
1172 len = bw << 3;
1173
1174 if (test) {
1175 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1176 bw = 82;
1177 else
1178 bw = 80;
1179
1180 if (dev->phy.is_40mhz)
1181 bw <<= 1;
1182
1183 len = bw << 1;
1184 }
1185
1186 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1187 if (!samples) {
1188 b43err(dev->wl, "allocation for samples generation failed\n");
1189 return 0;
1190 }
1191 rot = (((freq * 36) / bw) << 16) / 100;
1192 angle = 0;
1193
1194 for (i = 0; i < len; i++) {
1195 samples[i] = b43_cordic(angle);
1196 angle += rot;
1197 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1198 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1199 }
1200
1201 i = b43_nphy_load_samples(dev, samples, len);
1202 kfree(samples);
1203 return (i < 0) ? 0 : len;
1204 }
1205
1206 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1207 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1208 u16 wait, bool iqmode, bool dac_test)
1209 {
1210 struct b43_phy_n *nphy = dev->phy.n;
1211 int i;
1212 u16 seq_mode;
1213 u32 tmp;
1214
1215 if (nphy->hang_avoid)
1216 b43_nphy_stay_in_carrier_search(dev, true);
1217
1218 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1219 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1220 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1221 }
1222
1223 if (!dev->phy.is_40mhz)
1224 tmp = 0x6464;
1225 else
1226 tmp = 0x4747;
1227 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1228
1229 if (nphy->hang_avoid)
1230 b43_nphy_stay_in_carrier_search(dev, false);
1231
1232 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1233
1234 if (loops != 0xFFFF)
1235 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1236 else
1237 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1238
1239 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1240
1241 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1242
1243 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1244 if (iqmode) {
1245 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1246 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1247 } else {
1248 if (dac_test)
1249 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1250 else
1251 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1252 }
1253 for (i = 0; i < 100; i++) {
1254 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1255 i = 0;
1256 break;
1257 }
1258 udelay(10);
1259 }
1260 if (i)
1261 b43err(dev->wl, "run samples timeout\n");
1262
1263 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1264 }
1265
1266 /*
1267 * Transmits a known value for LO calibration
1268 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1269 */
1270 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1271 bool iqmode, bool dac_test)
1272 {
1273 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1274 if (samp == 0)
1275 return -1;
1276 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1277 return 0;
1278 }
1279
1280 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1281 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1282 {
1283 struct b43_phy_n *nphy = dev->phy.n;
1284 int i, j;
1285 u32 tmp;
1286 u32 cur_real, cur_imag, real_part, imag_part;
1287
1288 u16 buffer[7];
1289
1290 if (nphy->hang_avoid)
1291 b43_nphy_stay_in_carrier_search(dev, true);
1292
1293 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1294
1295 for (i = 0; i < 2; i++) {
1296 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1297 (buffer[i * 2 + 1] & 0x3FF);
1298 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1299 (((i + 26) << 10) | 320));
1300 for (j = 0; j < 128; j++) {
1301 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1302 ((tmp >> 16) & 0xFFFF));
1303 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1304 (tmp & 0xFFFF));
1305 }
1306 }
1307
1308 for (i = 0; i < 2; i++) {
1309 tmp = buffer[5 + i];
1310 real_part = (tmp >> 8) & 0xFF;
1311 imag_part = (tmp & 0xFF);
1312 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1313 (((i + 26) << 10) | 448));
1314
1315 if (dev->phy.rev >= 3) {
1316 cur_real = real_part;
1317 cur_imag = imag_part;
1318 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1319 }
1320
1321 for (j = 0; j < 128; j++) {
1322 if (dev->phy.rev < 3) {
1323 cur_real = (real_part * loscale[j] + 128) >> 8;
1324 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1325 tmp = ((cur_real & 0xFF) << 8) |
1326 (cur_imag & 0xFF);
1327 }
1328 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1329 ((tmp >> 16) & 0xFFFF));
1330 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1331 (tmp & 0xFFFF));
1332 }
1333 }
1334
1335 if (dev->phy.rev >= 3) {
1336 b43_shm_write16(dev, B43_SHM_SHARED,
1337 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1338 b43_shm_write16(dev, B43_SHM_SHARED,
1339 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1340 }
1341
1342 if (nphy->hang_avoid)
1343 b43_nphy_stay_in_carrier_search(dev, false);
1344 }
1345
1346 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1347 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1348 u8 *events, u8 *delays, u8 length)
1349 {
1350 struct b43_phy_n *nphy = dev->phy.n;
1351 u8 i;
1352 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1353 u16 offset1 = cmd << 4;
1354 u16 offset2 = offset1 + 0x80;
1355
1356 if (nphy->hang_avoid)
1357 b43_nphy_stay_in_carrier_search(dev, true);
1358
1359 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1360 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1361
1362 for (i = length; i < 16; i++) {
1363 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1364 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1365 }
1366
1367 if (nphy->hang_avoid)
1368 b43_nphy_stay_in_carrier_search(dev, false);
1369 }
1370
1371 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1372 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1373 enum b43_nphy_rf_sequence seq)
1374 {
1375 static const u16 trigger[] = {
1376 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1377 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1378 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1379 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1380 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1381 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1382 };
1383 int i;
1384 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1385
1386 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1387
1388 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1389 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1390 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1391 for (i = 0; i < 200; i++) {
1392 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1393 goto ok;
1394 msleep(1);
1395 }
1396 b43err(dev->wl, "RF sequence status timeout\n");
1397 ok:
1398 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1399 }
1400
1401 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1402 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1403 u16 value, u8 core, bool off)
1404 {
1405 int i;
1406 u8 index = fls(field);
1407 u8 addr, en_addr, val_addr;
1408 /* we expect only one bit set */
1409 B43_WARN_ON(field & (~(1 << (index - 1))));
1410
1411 if (dev->phy.rev >= 3) {
1412 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1413 for (i = 0; i < 2; i++) {
1414 if (index == 0 || index == 16) {
1415 b43err(dev->wl,
1416 "Unsupported RF Ctrl Override call\n");
1417 return;
1418 }
1419
1420 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1421 en_addr = B43_PHY_N((i == 0) ?
1422 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1423 val_addr = B43_PHY_N((i == 0) ?
1424 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1425
1426 if (off) {
1427 b43_phy_mask(dev, en_addr, ~(field));
1428 b43_phy_mask(dev, val_addr,
1429 ~(rf_ctrl->val_mask));
1430 } else {
1431 if (core == 0 || ((1 << core) & i) != 0) {
1432 b43_phy_set(dev, en_addr, field);
1433 b43_phy_maskset(dev, val_addr,
1434 ~(rf_ctrl->val_mask),
1435 (value << rf_ctrl->val_shift));
1436 }
1437 }
1438 }
1439 } else {
1440 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1441 if (off) {
1442 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1443 value = 0;
1444 } else {
1445 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1446 }
1447
1448 for (i = 0; i < 2; i++) {
1449 if (index <= 1 || index == 16) {
1450 b43err(dev->wl,
1451 "Unsupported RF Ctrl Override call\n");
1452 return;
1453 }
1454
1455 if (index == 2 || index == 10 ||
1456 (index >= 13 && index <= 15)) {
1457 core = 1;
1458 }
1459
1460 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1461 addr = B43_PHY_N((i == 0) ?
1462 rf_ctrl->addr0 : rf_ctrl->addr1);
1463
1464 if ((core & (1 << i)) != 0)
1465 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1466 (value << rf_ctrl->shift));
1467
1468 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1469 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1470 B43_NPHY_RFCTL_CMD_START);
1471 udelay(1);
1472 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1473 }
1474 }
1475 }
1476
1477 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1478 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1479 u16 value, u8 core)
1480 {
1481 u8 i, j;
1482 u16 reg, tmp, val;
1483
1484 B43_WARN_ON(dev->phy.rev < 3);
1485 B43_WARN_ON(field > 4);
1486
1487 for (i = 0; i < 2; i++) {
1488 if ((core == 1 && i == 1) || (core == 2 && !i))
1489 continue;
1490
1491 reg = (i == 0) ?
1492 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1493 b43_phy_mask(dev, reg, 0xFBFF);
1494
1495 switch (field) {
1496 case 0:
1497 b43_phy_write(dev, reg, 0);
1498 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1499 break;
1500 case 1:
1501 if (!i) {
1502 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1503 0xFC3F, (value << 6));
1504 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1505 0xFFFE, 1);
1506 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1507 B43_NPHY_RFCTL_CMD_START);
1508 for (j = 0; j < 100; j++) {
1509 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1510 j = 0;
1511 break;
1512 }
1513 udelay(10);
1514 }
1515 if (j)
1516 b43err(dev->wl,
1517 "intc override timeout\n");
1518 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1519 0xFFFE);
1520 } else {
1521 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1522 0xFC3F, (value << 6));
1523 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1524 0xFFFE, 1);
1525 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1526 B43_NPHY_RFCTL_CMD_RXTX);
1527 for (j = 0; j < 100; j++) {
1528 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1529 j = 0;
1530 break;
1531 }
1532 udelay(10);
1533 }
1534 if (j)
1535 b43err(dev->wl,
1536 "intc override timeout\n");
1537 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1538 0xFFFE);
1539 }
1540 break;
1541 case 2:
1542 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1543 tmp = 0x0020;
1544 val = value << 5;
1545 } else {
1546 tmp = 0x0010;
1547 val = value << 4;
1548 }
1549 b43_phy_maskset(dev, reg, ~tmp, val);
1550 break;
1551 case 3:
1552 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1553 tmp = 0x0001;
1554 val = value;
1555 } else {
1556 tmp = 0x0004;
1557 val = value << 2;
1558 }
1559 b43_phy_maskset(dev, reg, ~tmp, val);
1560 break;
1561 case 4:
1562 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1563 tmp = 0x0002;
1564 val = value << 1;
1565 } else {
1566 tmp = 0x0008;
1567 val = value << 3;
1568 }
1569 b43_phy_maskset(dev, reg, ~tmp, val);
1570 break;
1571 }
1572 }
1573 }
1574
1575 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1576 {
1577 unsigned int i;
1578 u16 val;
1579
1580 val = 0x1E1F;
1581 for (i = 0; i < 14; i++) {
1582 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1583 val -= 0x202;
1584 }
1585 val = 0x3E3F;
1586 for (i = 0; i < 16; i++) {
1587 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1588 val -= 0x202;
1589 }
1590 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1591 }
1592
1593 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1594 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1595 s8 offset, u8 core, u8 rail, u8 type)
1596 {
1597 u16 tmp;
1598 bool core1or5 = (core == 1) || (core == 5);
1599 bool core2or5 = (core == 2) || (core == 5);
1600
1601 offset = clamp_val(offset, -32, 31);
1602 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1603
1604 if (core1or5 && (rail == 0) && (type == 2))
1605 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1606 if (core1or5 && (rail == 1) && (type == 2))
1607 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1608 if (core2or5 && (rail == 0) && (type == 2))
1609 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1610 if (core2or5 && (rail == 1) && (type == 2))
1611 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1612 if (core1or5 && (rail == 0) && (type == 0))
1613 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1614 if (core1or5 && (rail == 1) && (type == 0))
1615 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1616 if (core2or5 && (rail == 0) && (type == 0))
1617 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1618 if (core2or5 && (rail == 1) && (type == 0))
1619 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1620 if (core1or5 && (rail == 0) && (type == 1))
1621 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1622 if (core1or5 && (rail == 1) && (type == 1))
1623 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1624 if (core2or5 && (rail == 0) && (type == 1))
1625 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1626 if (core2or5 && (rail == 1) && (type == 1))
1627 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1628 if (core1or5 && (rail == 0) && (type == 6))
1629 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1630 if (core1or5 && (rail == 1) && (type == 6))
1631 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1632 if (core2or5 && (rail == 0) && (type == 6))
1633 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1634 if (core2or5 && (rail == 1) && (type == 6))
1635 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1636 if (core1or5 && (rail == 0) && (type == 3))
1637 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1638 if (core1or5 && (rail == 1) && (type == 3))
1639 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1640 if (core2or5 && (rail == 0) && (type == 3))
1641 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1642 if (core2or5 && (rail == 1) && (type == 3))
1643 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1644 if (core1or5 && (type == 4))
1645 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1646 if (core2or5 && (type == 4))
1647 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1648 if (core1or5 && (type == 5))
1649 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1650 if (core2or5 && (type == 5))
1651 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1652 }
1653
1654 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1655 {
1656 u16 val;
1657
1658 if (type < 3)
1659 val = 0;
1660 else if (type == 6)
1661 val = 1;
1662 else if (type == 3)
1663 val = 2;
1664 else
1665 val = 3;
1666
1667 val = (val << 12) | (val << 14);
1668 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1669 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1670
1671 if (type < 3) {
1672 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1673 (type + 1) << 4);
1674 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1675 (type + 1) << 4);
1676 }
1677
1678 /* TODO use some definitions */
1679 if (code == 0) {
1680 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1681 if (type < 3) {
1682 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1683 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1684 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1685 udelay(20);
1686 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1687 }
1688 } else {
1689 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1690 0x3000);
1691 if (type < 3) {
1692 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1693 0xFEC7, 0x0180);
1694 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1695 0xEFDC, (code << 1 | 0x1021));
1696 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1697 udelay(20);
1698 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1699 }
1700 }
1701 }
1702
1703 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1704 {
1705 struct b43_phy_n *nphy = dev->phy.n;
1706 u8 i;
1707 u16 reg, val;
1708
1709 if (code == 0) {
1710 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1711 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1712 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1713 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1714 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1715 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1716 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1717 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1718 } else {
1719 for (i = 0; i < 2; i++) {
1720 if ((code == 1 && i == 1) || (code == 2 && !i))
1721 continue;
1722
1723 reg = (i == 0) ?
1724 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1725 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1726
1727 if (type < 3) {
1728 reg = (i == 0) ?
1729 B43_NPHY_AFECTL_C1 :
1730 B43_NPHY_AFECTL_C2;
1731 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1732
1733 reg = (i == 0) ?
1734 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1735 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1736 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1737
1738 if (type == 0)
1739 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1740 else if (type == 1)
1741 val = 16;
1742 else
1743 val = 32;
1744 b43_phy_set(dev, reg, val);
1745
1746 reg = (i == 0) ?
1747 B43_NPHY_TXF_40CO_B1S0 :
1748 B43_NPHY_TXF_40CO_B32S1;
1749 b43_phy_set(dev, reg, 0x0020);
1750 } else {
1751 if (type == 6)
1752 val = 0x0100;
1753 else if (type == 3)
1754 val = 0x0200;
1755 else
1756 val = 0x0300;
1757
1758 reg = (i == 0) ?
1759 B43_NPHY_AFECTL_C1 :
1760 B43_NPHY_AFECTL_C2;
1761
1762 b43_phy_maskset(dev, reg, 0xFCFF, val);
1763 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1764
1765 if (type != 3 && type != 6) {
1766 enum ieee80211_band band =
1767 b43_current_band(dev->wl);
1768
1769 if ((nphy->ipa2g_on &&
1770 band == IEEE80211_BAND_2GHZ) ||
1771 (nphy->ipa5g_on &&
1772 band == IEEE80211_BAND_5GHZ))
1773 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1774 else
1775 val = 0x11;
1776 reg = (i == 0) ? 0x2000 : 0x3000;
1777 reg |= B2055_PADDRV;
1778 b43_radio_write16(dev, reg, val);
1779
1780 reg = (i == 0) ?
1781 B43_NPHY_AFECTL_OVER1 :
1782 B43_NPHY_AFECTL_OVER;
1783 b43_phy_set(dev, reg, 0x0200);
1784 }
1785 }
1786 }
1787 }
1788 }
1789
1790 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1791 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1792 {
1793 if (dev->phy.rev >= 3)
1794 b43_nphy_rev3_rssi_select(dev, code, type);
1795 else
1796 b43_nphy_rev2_rssi_select(dev, code, type);
1797 }
1798
1799 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1800 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1801 {
1802 int i;
1803 for (i = 0; i < 2; i++) {
1804 if (type == 2) {
1805 if (i == 0) {
1806 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1807 0xFC, buf[0]);
1808 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1809 0xFC, buf[1]);
1810 } else {
1811 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1812 0xFC, buf[2 * i]);
1813 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1814 0xFC, buf[2 * i + 1]);
1815 }
1816 } else {
1817 if (i == 0)
1818 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1819 0xF3, buf[0] << 2);
1820 else
1821 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1822 0xF3, buf[2 * i + 1] << 2);
1823 }
1824 }
1825 }
1826
1827 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1828 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1829 u8 nsamp)
1830 {
1831 int i;
1832 int out;
1833 u16 save_regs_phy[9];
1834 u16 s[2];
1835
1836 if (dev->phy.rev >= 3) {
1837 save_regs_phy[0] = b43_phy_read(dev,
1838 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1839 save_regs_phy[1] = b43_phy_read(dev,
1840 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1841 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1842 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1843 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1844 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1845 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1846 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1847 }
1848
1849 b43_nphy_rssi_select(dev, 5, type);
1850
1851 if (dev->phy.rev < 2) {
1852 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1853 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1854 }
1855
1856 for (i = 0; i < 4; i++)
1857 buf[i] = 0;
1858
1859 for (i = 0; i < nsamp; i++) {
1860 if (dev->phy.rev < 2) {
1861 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1862 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1863 } else {
1864 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1865 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1866 }
1867
1868 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1869 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1870 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1871 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1872 }
1873 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1874 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1875
1876 if (dev->phy.rev < 2)
1877 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1878
1879 if (dev->phy.rev >= 3) {
1880 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1881 save_regs_phy[0]);
1882 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1883 save_regs_phy[1]);
1884 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1885 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1886 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1887 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1888 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1889 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1890 }
1891
1892 return out;
1893 }
1894
1895 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1896 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1897 {
1898 int i, j;
1899 u8 state[4];
1900 u8 code, val;
1901 u16 class, override;
1902 u8 regs_save_radio[2];
1903 u16 regs_save_phy[2];
1904 s8 offset[4];
1905
1906 u16 clip_state[2];
1907 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1908 s32 results_min[4] = { };
1909 u8 vcm_final[4] = { };
1910 s32 results[4][4] = { };
1911 s32 miniq[4][2] = { };
1912
1913 if (type == 2) {
1914 code = 0;
1915 val = 6;
1916 } else if (type < 2) {
1917 code = 25;
1918 val = 4;
1919 } else {
1920 B43_WARN_ON(1);
1921 return;
1922 }
1923
1924 class = b43_nphy_classifier(dev, 0, 0);
1925 b43_nphy_classifier(dev, 7, 4);
1926 b43_nphy_read_clip_detection(dev, clip_state);
1927 b43_nphy_write_clip_detection(dev, clip_off);
1928
1929 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1930 override = 0x140;
1931 else
1932 override = 0x110;
1933
1934 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1935 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1936 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1937 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1938
1939 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1940 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1941 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1942 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1943
1944 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1945 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1946 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1947 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1948 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1949 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1950
1951 b43_nphy_rssi_select(dev, 5, type);
1952 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1953 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1954
1955 for (i = 0; i < 4; i++) {
1956 u8 tmp[4];
1957 for (j = 0; j < 4; j++)
1958 tmp[j] = i;
1959 if (type != 1)
1960 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1961 b43_nphy_poll_rssi(dev, type, results[i], 8);
1962 if (type < 2)
1963 for (j = 0; j < 2; j++)
1964 miniq[i][j] = min(results[i][2 * j],
1965 results[i][2 * j + 1]);
1966 }
1967
1968 for (i = 0; i < 4; i++) {
1969 s32 mind = 40;
1970 u8 minvcm = 0;
1971 s32 minpoll = 249;
1972 s32 curr;
1973 for (j = 0; j < 4; j++) {
1974 if (type == 2)
1975 curr = abs(results[j][i]);
1976 else
1977 curr = abs(miniq[j][i / 2] - code * 8);
1978
1979 if (curr < mind) {
1980 mind = curr;
1981 minvcm = j;
1982 }
1983
1984 if (results[j][i] < minpoll)
1985 minpoll = results[j][i];
1986 }
1987 results_min[i] = minpoll;
1988 vcm_final[i] = minvcm;
1989 }
1990
1991 if (type != 1)
1992 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1993
1994 for (i = 0; i < 4; i++) {
1995 offset[i] = (code * 8) - results[vcm_final[i]][i];
1996
1997 if (offset[i] < 0)
1998 offset[i] = -((abs(offset[i]) + 4) / 8);
1999 else
2000 offset[i] = (offset[i] + 4) / 8;
2001
2002 if (results_min[i] == 248)
2003 offset[i] = code - 32;
2004
2005 if (i % 2 == 0)
2006 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
2007 type);
2008 else
2009 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
2010 type);
2011 }
2012
2013 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2014 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
2015
2016 switch (state[2]) {
2017 case 1:
2018 b43_nphy_rssi_select(dev, 1, 2);
2019 break;
2020 case 4:
2021 b43_nphy_rssi_select(dev, 1, 0);
2022 break;
2023 case 2:
2024 b43_nphy_rssi_select(dev, 1, 1);
2025 break;
2026 default:
2027 b43_nphy_rssi_select(dev, 1, 1);
2028 break;
2029 }
2030
2031 switch (state[3]) {
2032 case 1:
2033 b43_nphy_rssi_select(dev, 2, 2);
2034 break;
2035 case 4:
2036 b43_nphy_rssi_select(dev, 2, 0);
2037 break;
2038 default:
2039 b43_nphy_rssi_select(dev, 2, 1);
2040 break;
2041 }
2042
2043 b43_nphy_rssi_select(dev, 0, type);
2044
2045 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2046 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2047 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2048 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2049
2050 b43_nphy_classifier(dev, 7, class);
2051 b43_nphy_write_clip_detection(dev, clip_state);
2052 }
2053
2054 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2055 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2056 {
2057 /* TODO */
2058 }
2059
2060 /*
2061 * RSSI Calibration
2062 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2063 */
2064 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2065 {
2066 if (dev->phy.rev >= 3) {
2067 b43_nphy_rev3_rssi_cal(dev);
2068 } else {
2069 b43_nphy_rev2_rssi_cal(dev, 2);
2070 b43_nphy_rev2_rssi_cal(dev, 0);
2071 b43_nphy_rev2_rssi_cal(dev, 1);
2072 }
2073 }
2074
2075 /*
2076 * Restore RSSI Calibration
2077 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2078 */
2079 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2080 {
2081 struct b43_phy_n *nphy = dev->phy.n;
2082
2083 u16 *rssical_radio_regs = NULL;
2084 u16 *rssical_phy_regs = NULL;
2085
2086 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2087 if (b43_empty_chanspec(&nphy->rssical_chanspec_2G))
2088 return;
2089 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2090 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2091 } else {
2092 if (b43_empty_chanspec(&nphy->rssical_chanspec_5G))
2093 return;
2094 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2095 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2096 }
2097
2098 /* TODO use some definitions */
2099 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2100 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2101
2102 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2103 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2104 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2105 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2106
2107 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2108 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2109 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2110 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2111
2112 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2113 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2114 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2115 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2116 }
2117
2118 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2119 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2120 {
2121 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2122 if (dev->phy.rev >= 6) {
2123 /* TODO If the chip is 47162
2124 return txpwrctrl_tx_gain_ipa_rev5 */
2125 return txpwrctrl_tx_gain_ipa_rev6;
2126 } else if (dev->phy.rev >= 5) {
2127 return txpwrctrl_tx_gain_ipa_rev5;
2128 } else {
2129 return txpwrctrl_tx_gain_ipa;
2130 }
2131 } else {
2132 return txpwrctrl_tx_gain_ipa_5g;
2133 }
2134 }
2135
2136 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2137 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2138 {
2139 struct b43_phy_n *nphy = dev->phy.n;
2140 u16 *save = nphy->tx_rx_cal_radio_saveregs;
2141 u16 tmp;
2142 u8 offset, i;
2143
2144 if (dev->phy.rev >= 3) {
2145 for (i = 0; i < 2; i++) {
2146 tmp = (i == 0) ? 0x2000 : 0x3000;
2147 offset = i * 11;
2148
2149 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2150 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2151 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2152 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2153 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2154 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2155 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2156 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2157 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2158 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2159 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2160
2161 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2162 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2163 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2164 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2165 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2166 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2167 if (nphy->ipa5g_on) {
2168 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2169 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2170 } else {
2171 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2172 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2173 }
2174 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2175 } else {
2176 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2177 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2178 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2179 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2180 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2181 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2182 if (nphy->ipa2g_on) {
2183 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2184 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2185 (dev->phy.rev < 5) ? 0x11 : 0x01);
2186 } else {
2187 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2188 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2189 }
2190 }
2191 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2192 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2193 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2194 }
2195 } else {
2196 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2197 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2198
2199 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2200 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2201
2202 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2203 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2204
2205 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2206 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2207
2208 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2209 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2210
2211 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2212 B43_NPHY_BANDCTL_5GHZ)) {
2213 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2214 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2215 } else {
2216 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2217 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2218 }
2219
2220 if (dev->phy.rev < 2) {
2221 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2222 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2223 } else {
2224 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2225 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2226 }
2227 }
2228 }
2229
2230 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2231 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2232 struct nphy_txgains target,
2233 struct nphy_iqcal_params *params)
2234 {
2235 int i, j, indx;
2236 u16 gain;
2237
2238 if (dev->phy.rev >= 3) {
2239 params->txgm = target.txgm[core];
2240 params->pga = target.pga[core];
2241 params->pad = target.pad[core];
2242 params->ipa = target.ipa[core];
2243 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2244 (params->pad << 4) | (params->ipa);
2245 for (j = 0; j < 5; j++)
2246 params->ncorr[j] = 0x79;
2247 } else {
2248 gain = (target.pad[core]) | (target.pga[core] << 4) |
2249 (target.txgm[core] << 8);
2250
2251 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2252 1 : 0;
2253 for (i = 0; i < 9; i++)
2254 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2255 break;
2256 i = min(i, 8);
2257
2258 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2259 params->pga = tbl_iqcal_gainparams[indx][i][2];
2260 params->pad = tbl_iqcal_gainparams[indx][i][3];
2261 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2262 (params->pad << 2);
2263 for (j = 0; j < 4; j++)
2264 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2265 }
2266 }
2267
2268 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2269 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2270 {
2271 struct b43_phy_n *nphy = dev->phy.n;
2272 int i;
2273 u16 scale, entry;
2274
2275 u16 tmp = nphy->txcal_bbmult;
2276 if (core == 0)
2277 tmp >>= 8;
2278 tmp &= 0xff;
2279
2280 for (i = 0; i < 18; i++) {
2281 scale = (ladder_lo[i].percent * tmp) / 100;
2282 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2283 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2284
2285 scale = (ladder_iq[i].percent * tmp) / 100;
2286 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2287 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2288 }
2289 }
2290
2291 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2292 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2293 {
2294 int i;
2295 for (i = 0; i < 15; i++)
2296 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2297 tbl_tx_filter_coef_rev4[2][i]);
2298 }
2299
2300 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2301 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2302 {
2303 int i, j;
2304 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2305 u16 offset[] = { 0x186, 0x195, 0x2C5 };
2306
2307 for (i = 0; i < 3; i++)
2308 for (j = 0; j < 15; j++)
2309 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2310 tbl_tx_filter_coef_rev4[i][j]);
2311
2312 if (dev->phy.is_40mhz) {
2313 for (j = 0; j < 15; j++)
2314 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2315 tbl_tx_filter_coef_rev4[3][j]);
2316 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2317 for (j = 0; j < 15; j++)
2318 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2319 tbl_tx_filter_coef_rev4[5][j]);
2320 }
2321
2322 if (dev->phy.channel == 14)
2323 for (j = 0; j < 15; j++)
2324 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2325 tbl_tx_filter_coef_rev4[6][j]);
2326 }
2327
2328 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2329 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2330 {
2331 struct b43_phy_n *nphy = dev->phy.n;
2332
2333 u16 curr_gain[2];
2334 struct nphy_txgains target;
2335 const u32 *table = NULL;
2336
2337 if (nphy->txpwrctrl == 0) {
2338 int i;
2339
2340 if (nphy->hang_avoid)
2341 b43_nphy_stay_in_carrier_search(dev, true);
2342 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2343 if (nphy->hang_avoid)
2344 b43_nphy_stay_in_carrier_search(dev, false);
2345
2346 for (i = 0; i < 2; ++i) {
2347 if (dev->phy.rev >= 3) {
2348 target.ipa[i] = curr_gain[i] & 0x000F;
2349 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2350 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2351 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2352 } else {
2353 target.ipa[i] = curr_gain[i] & 0x0003;
2354 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2355 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2356 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2357 }
2358 }
2359 } else {
2360 int i;
2361 u16 index[2];
2362 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2363 B43_NPHY_TXPCTL_STAT_BIDX) >>
2364 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2365 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2366 B43_NPHY_TXPCTL_STAT_BIDX) >>
2367 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2368
2369 for (i = 0; i < 2; ++i) {
2370 if (dev->phy.rev >= 3) {
2371 enum ieee80211_band band =
2372 b43_current_band(dev->wl);
2373
2374 if ((nphy->ipa2g_on &&
2375 band == IEEE80211_BAND_2GHZ) ||
2376 (nphy->ipa5g_on &&
2377 band == IEEE80211_BAND_5GHZ)) {
2378 table = b43_nphy_get_ipa_gain_table(dev);
2379 } else {
2380 if (band == IEEE80211_BAND_5GHZ) {
2381 if (dev->phy.rev == 3)
2382 table = b43_ntab_tx_gain_rev3_5ghz;
2383 else if (dev->phy.rev == 4)
2384 table = b43_ntab_tx_gain_rev4_5ghz;
2385 else
2386 table = b43_ntab_tx_gain_rev5plus_5ghz;
2387 } else {
2388 table = b43_ntab_tx_gain_rev3plus_2ghz;
2389 }
2390 }
2391
2392 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2393 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2394 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2395 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2396 } else {
2397 table = b43_ntab_tx_gain_rev0_1_2;
2398
2399 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2400 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2401 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2402 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2403 }
2404 }
2405 }
2406
2407 return target;
2408 }
2409
2410 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2411 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2412 {
2413 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2414
2415 if (dev->phy.rev >= 3) {
2416 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2417 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2418 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2419 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2420 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2421 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2422 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2423 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2424 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2425 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2426 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2427 b43_nphy_reset_cca(dev);
2428 } else {
2429 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2430 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2431 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2432 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2433 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2434 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2435 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2436 }
2437 }
2438
2439 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2440 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2441 {
2442 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2443 u16 tmp;
2444
2445 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2446 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2447 if (dev->phy.rev >= 3) {
2448 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2449 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2450
2451 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2452 regs[2] = tmp;
2453 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2454
2455 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2456 regs[3] = tmp;
2457 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2458
2459 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2460 b43_phy_mask(dev, B43_NPHY_BBCFG,
2461 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2462
2463 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2464 regs[5] = tmp;
2465 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2466
2467 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2468 regs[6] = tmp;
2469 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2470 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2471 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2472
2473 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2474 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2475 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2476
2477 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2478 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2479 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2480 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2481 } else {
2482 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2483 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2484 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2485 regs[2] = tmp;
2486 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2487 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2488 regs[3] = tmp;
2489 tmp |= 0x2000;
2490 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2491 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2492 regs[4] = tmp;
2493 tmp |= 0x2000;
2494 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2495 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2496 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2497 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2498 tmp = 0x0180;
2499 else
2500 tmp = 0x0120;
2501 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2502 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2503 }
2504 }
2505
2506 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2507 static void b43_nphy_save_cal(struct b43_wldev *dev)
2508 {
2509 struct b43_phy_n *nphy = dev->phy.n;
2510
2511 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2512 u16 *txcal_radio_regs = NULL;
2513 struct b43_chanspec *iqcal_chanspec;
2514 u16 *table = NULL;
2515
2516 if (nphy->hang_avoid)
2517 b43_nphy_stay_in_carrier_search(dev, 1);
2518
2519 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2520 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2521 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2522 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2523 table = nphy->cal_cache.txcal_coeffs_2G;
2524 } else {
2525 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2526 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2527 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2528 table = nphy->cal_cache.txcal_coeffs_5G;
2529 }
2530
2531 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2532 /* TODO use some definitions */
2533 if (dev->phy.rev >= 3) {
2534 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2535 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2536 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2537 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2538 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2539 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2540 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2541 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2542 } else {
2543 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2544 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2545 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2546 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2547 }
2548 *iqcal_chanspec = nphy->radio_chanspec;
2549 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2550
2551 if (nphy->hang_avoid)
2552 b43_nphy_stay_in_carrier_search(dev, 0);
2553 }
2554
2555 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2556 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2557 {
2558 struct b43_phy_n *nphy = dev->phy.n;
2559
2560 u16 coef[4];
2561 u16 *loft = NULL;
2562 u16 *table = NULL;
2563
2564 int i;
2565 u16 *txcal_radio_regs = NULL;
2566 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2567
2568 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2569 if (b43_empty_chanspec(&nphy->iqcal_chanspec_2G))
2570 return;
2571 table = nphy->cal_cache.txcal_coeffs_2G;
2572 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2573 } else {
2574 if (b43_empty_chanspec(&nphy->iqcal_chanspec_5G))
2575 return;
2576 table = nphy->cal_cache.txcal_coeffs_5G;
2577 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2578 }
2579
2580 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2581
2582 for (i = 0; i < 4; i++) {
2583 if (dev->phy.rev >= 3)
2584 table[i] = coef[i];
2585 else
2586 coef[i] = 0;
2587 }
2588
2589 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2590 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2591 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2592
2593 if (dev->phy.rev < 2)
2594 b43_nphy_tx_iq_workaround(dev);
2595
2596 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2597 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2598 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2599 } else {
2600 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2601 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2602 }
2603
2604 /* TODO use some definitions */
2605 if (dev->phy.rev >= 3) {
2606 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2607 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2608 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2609 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2610 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2611 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2612 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2613 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2614 } else {
2615 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2616 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2617 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2618 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2619 }
2620 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2621 }
2622
2623 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2624 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2625 struct nphy_txgains target,
2626 bool full, bool mphase)
2627 {
2628 struct b43_phy_n *nphy = dev->phy.n;
2629 int i;
2630 int error = 0;
2631 int freq;
2632 bool avoid = false;
2633 u8 length;
2634 u16 tmp, core, type, count, max, numb, last, cmd;
2635 const u16 *table;
2636 bool phy6or5x;
2637
2638 u16 buffer[11];
2639 u16 diq_start = 0;
2640 u16 save[2];
2641 u16 gain[2];
2642 struct nphy_iqcal_params params[2];
2643 bool updated[2] = { };
2644
2645 b43_nphy_stay_in_carrier_search(dev, true);
2646
2647 if (dev->phy.rev >= 4) {
2648 avoid = nphy->hang_avoid;
2649 nphy->hang_avoid = 0;
2650 }
2651
2652 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2653
2654 for (i = 0; i < 2; i++) {
2655 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2656 gain[i] = params[i].cal_gain;
2657 }
2658
2659 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2660
2661 b43_nphy_tx_cal_radio_setup(dev);
2662 b43_nphy_tx_cal_phy_setup(dev);
2663
2664 phy6or5x = dev->phy.rev >= 6 ||
2665 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2666 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2667 if (phy6or5x) {
2668 if (dev->phy.is_40mhz) {
2669 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2670 tbl_tx_iqlo_cal_loft_ladder_40);
2671 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2672 tbl_tx_iqlo_cal_iqimb_ladder_40);
2673 } else {
2674 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2675 tbl_tx_iqlo_cal_loft_ladder_20);
2676 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2677 tbl_tx_iqlo_cal_iqimb_ladder_20);
2678 }
2679 }
2680
2681 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2682
2683 if (!dev->phy.is_40mhz)
2684 freq = 2500;
2685 else
2686 freq = 5000;
2687
2688 if (nphy->mphase_cal_phase_id > 2)
2689 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2690 0xFFFF, 0, true, false);
2691 else
2692 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2693
2694 if (error == 0) {
2695 if (nphy->mphase_cal_phase_id > 2) {
2696 table = nphy->mphase_txcal_bestcoeffs;
2697 length = 11;
2698 if (dev->phy.rev < 3)
2699 length -= 2;
2700 } else {
2701 if (!full && nphy->txiqlocal_coeffsvalid) {
2702 table = nphy->txiqlocal_bestc;
2703 length = 11;
2704 if (dev->phy.rev < 3)
2705 length -= 2;
2706 } else {
2707 full = true;
2708 if (dev->phy.rev >= 3) {
2709 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2710 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2711 } else {
2712 table = tbl_tx_iqlo_cal_startcoefs;
2713 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2714 }
2715 }
2716 }
2717
2718 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2719
2720 if (full) {
2721 if (dev->phy.rev >= 3)
2722 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2723 else
2724 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2725 } else {
2726 if (dev->phy.rev >= 3)
2727 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2728 else
2729 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2730 }
2731
2732 if (mphase) {
2733 count = nphy->mphase_txcal_cmdidx;
2734 numb = min(max,
2735 (u16)(count + nphy->mphase_txcal_numcmds));
2736 } else {
2737 count = 0;
2738 numb = max;
2739 }
2740
2741 for (; count < numb; count++) {
2742 if (full) {
2743 if (dev->phy.rev >= 3)
2744 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2745 else
2746 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2747 } else {
2748 if (dev->phy.rev >= 3)
2749 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2750 else
2751 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2752 }
2753
2754 core = (cmd & 0x3000) >> 12;
2755 type = (cmd & 0x0F00) >> 8;
2756
2757 if (phy6or5x && updated[core] == 0) {
2758 b43_nphy_update_tx_cal_ladder(dev, core);
2759 updated[core] = 1;
2760 }
2761
2762 tmp = (params[core].ncorr[type] << 8) | 0x66;
2763 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2764
2765 if (type == 1 || type == 3 || type == 4) {
2766 buffer[0] = b43_ntab_read(dev,
2767 B43_NTAB16(15, 69 + core));
2768 diq_start = buffer[0];
2769 buffer[0] = 0;
2770 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2771 0);
2772 }
2773
2774 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2775 for (i = 0; i < 2000; i++) {
2776 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2777 if (tmp & 0xC000)
2778 break;
2779 udelay(10);
2780 }
2781
2782 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2783 buffer);
2784 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2785 buffer);
2786
2787 if (type == 1 || type == 3 || type == 4)
2788 buffer[0] = diq_start;
2789 }
2790
2791 if (mphase)
2792 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2793
2794 last = (dev->phy.rev < 3) ? 6 : 7;
2795
2796 if (!mphase || nphy->mphase_cal_phase_id == last) {
2797 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2798 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2799 if (dev->phy.rev < 3) {
2800 buffer[0] = 0;
2801 buffer[1] = 0;
2802 buffer[2] = 0;
2803 buffer[3] = 0;
2804 }
2805 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2806 buffer);
2807 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2808 buffer);
2809 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2810 buffer);
2811 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2812 buffer);
2813 length = 11;
2814 if (dev->phy.rev < 3)
2815 length -= 2;
2816 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2817 nphy->txiqlocal_bestc);
2818 nphy->txiqlocal_coeffsvalid = true;
2819 nphy->txiqlocal_chanspec = nphy->radio_chanspec;
2820 } else {
2821 length = 11;
2822 if (dev->phy.rev < 3)
2823 length -= 2;
2824 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2825 nphy->mphase_txcal_bestcoeffs);
2826 }
2827
2828 b43_nphy_stop_playback(dev);
2829 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2830 }
2831
2832 b43_nphy_tx_cal_phy_cleanup(dev);
2833 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2834
2835 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2836 b43_nphy_tx_iq_workaround(dev);
2837
2838 if (dev->phy.rev >= 4)
2839 nphy->hang_avoid = avoid;
2840
2841 b43_nphy_stay_in_carrier_search(dev, false);
2842
2843 return error;
2844 }
2845
2846 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2847 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2848 {
2849 struct b43_phy_n *nphy = dev->phy.n;
2850 u8 i;
2851 u16 buffer[7];
2852 bool equal = true;
2853
2854 if (!nphy->txiqlocal_coeffsvalid ||
2855 b43_eq_chanspecs(&nphy->txiqlocal_chanspec, &nphy->radio_chanspec))
2856 return;
2857
2858 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2859 for (i = 0; i < 4; i++) {
2860 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2861 equal = false;
2862 break;
2863 }
2864 }
2865
2866 if (!equal) {
2867 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2868 nphy->txiqlocal_bestc);
2869 for (i = 0; i < 4; i++)
2870 buffer[i] = 0;
2871 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2872 buffer);
2873 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2874 &nphy->txiqlocal_bestc[5]);
2875 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2876 &nphy->txiqlocal_bestc[5]);
2877 }
2878 }
2879
2880 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2881 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2882 struct nphy_txgains target, u8 type, bool debug)
2883 {
2884 struct b43_phy_n *nphy = dev->phy.n;
2885 int i, j, index;
2886 u8 rfctl[2];
2887 u8 afectl_core;
2888 u16 tmp[6];
2889 u16 cur_hpf1, cur_hpf2, cur_lna;
2890 u32 real, imag;
2891 enum ieee80211_band band;
2892
2893 u8 use;
2894 u16 cur_hpf;
2895 u16 lna[3] = { 3, 3, 1 };
2896 u16 hpf1[3] = { 7, 2, 0 };
2897 u16 hpf2[3] = { 2, 0, 0 };
2898 u32 power[3] = { };
2899 u16 gain_save[2];
2900 u16 cal_gain[2];
2901 struct nphy_iqcal_params cal_params[2];
2902 struct nphy_iq_est est;
2903 int ret = 0;
2904 bool playtone = true;
2905 int desired = 13;
2906
2907 b43_nphy_stay_in_carrier_search(dev, 1);
2908
2909 if (dev->phy.rev < 2)
2910 b43_nphy_reapply_tx_cal_coeffs(dev);
2911 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2912 for (i = 0; i < 2; i++) {
2913 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2914 cal_gain[i] = cal_params[i].cal_gain;
2915 }
2916 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2917
2918 for (i = 0; i < 2; i++) {
2919 if (i == 0) {
2920 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2921 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2922 afectl_core = B43_NPHY_AFECTL_C1;
2923 } else {
2924 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2925 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2926 afectl_core = B43_NPHY_AFECTL_C2;
2927 }
2928
2929 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2930 tmp[2] = b43_phy_read(dev, afectl_core);
2931 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2932 tmp[4] = b43_phy_read(dev, rfctl[0]);
2933 tmp[5] = b43_phy_read(dev, rfctl[1]);
2934
2935 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2936 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
2937 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2938 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2939 (1 - i));
2940 b43_phy_set(dev, afectl_core, 0x0006);
2941 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2942
2943 band = b43_current_band(dev->wl);
2944
2945 if (nphy->rxcalparams & 0xFF000000) {
2946 if (band == IEEE80211_BAND_5GHZ)
2947 b43_phy_write(dev, rfctl[0], 0x140);
2948 else
2949 b43_phy_write(dev, rfctl[0], 0x110);
2950 } else {
2951 if (band == IEEE80211_BAND_5GHZ)
2952 b43_phy_write(dev, rfctl[0], 0x180);
2953 else
2954 b43_phy_write(dev, rfctl[0], 0x120);
2955 }
2956
2957 if (band == IEEE80211_BAND_5GHZ)
2958 b43_phy_write(dev, rfctl[1], 0x148);
2959 else
2960 b43_phy_write(dev, rfctl[1], 0x114);
2961
2962 if (nphy->rxcalparams & 0x10000) {
2963 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2964 (i + 1));
2965 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2966 (2 - i));
2967 }
2968
2969 for (j = 0; i < 4; j++) {
2970 if (j < 3) {
2971 cur_lna = lna[j];
2972 cur_hpf1 = hpf1[j];
2973 cur_hpf2 = hpf2[j];
2974 } else {
2975 if (power[1] > 10000) {
2976 use = 1;
2977 cur_hpf = cur_hpf1;
2978 index = 2;
2979 } else {
2980 if (power[0] > 10000) {
2981 use = 1;
2982 cur_hpf = cur_hpf1;
2983 index = 1;
2984 } else {
2985 index = 0;
2986 use = 2;
2987 cur_hpf = cur_hpf2;
2988 }
2989 }
2990 cur_lna = lna[index];
2991 cur_hpf1 = hpf1[index];
2992 cur_hpf2 = hpf2[index];
2993 cur_hpf += desired - hweight32(power[index]);
2994 cur_hpf = clamp_val(cur_hpf, 0, 10);
2995 if (use == 1)
2996 cur_hpf1 = cur_hpf;
2997 else
2998 cur_hpf2 = cur_hpf;
2999 }
3000
3001 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3002 (cur_lna << 2));
3003 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3004 false);
3005 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3006 b43_nphy_stop_playback(dev);
3007
3008 if (playtone) {
3009 ret = b43_nphy_tx_tone(dev, 4000,
3010 (nphy->rxcalparams & 0xFFFF),
3011 false, false);
3012 playtone = false;
3013 } else {
3014 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3015 false, false);
3016 }
3017
3018 if (ret == 0) {
3019 if (j < 3) {
3020 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3021 false);
3022 if (i == 0) {
3023 real = est.i0_pwr;
3024 imag = est.q0_pwr;
3025 } else {
3026 real = est.i1_pwr;
3027 imag = est.q1_pwr;
3028 }
3029 power[i] = ((real + imag) / 1024) + 1;
3030 } else {
3031 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3032 }
3033 b43_nphy_stop_playback(dev);
3034 }
3035
3036 if (ret != 0)
3037 break;
3038 }
3039
3040 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3041 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3042 b43_phy_write(dev, rfctl[1], tmp[5]);
3043 b43_phy_write(dev, rfctl[0], tmp[4]);
3044 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3045 b43_phy_write(dev, afectl_core, tmp[2]);
3046 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3047
3048 if (ret != 0)
3049 break;
3050 }
3051
3052 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3053 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3054 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3055
3056 b43_nphy_stay_in_carrier_search(dev, 0);
3057
3058 return ret;
3059 }
3060
3061 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3062 struct nphy_txgains target, u8 type, bool debug)
3063 {
3064 return -1;
3065 }
3066
3067 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3068 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3069 struct nphy_txgains target, u8 type, bool debug)
3070 {
3071 if (dev->phy.rev >= 3)
3072 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3073 else
3074 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3075 }
3076
3077 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3078 static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3079 {
3080 u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
3081 if (on)
3082 tmslow |= SSB_TMSLOW_PHYCLK;
3083 else
3084 tmslow &= ~SSB_TMSLOW_PHYCLK;
3085 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
3086 }
3087
3088 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3089 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3090 {
3091 struct b43_phy *phy = &dev->phy;
3092 struct b43_phy_n *nphy = phy->n;
3093 u16 buf[16];
3094
3095 nphy->phyrxchain = mask;
3096
3097 if (0 /* FIXME clk */)
3098 return;
3099
3100 b43_mac_suspend(dev);
3101
3102 if (nphy->hang_avoid)
3103 b43_nphy_stay_in_carrier_search(dev, true);
3104
3105 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3106 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3107
3108 if ((mask & 0x3) != 0x3) {
3109 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3110 if (dev->phy.rev >= 3) {
3111 /* TODO */
3112 }
3113 } else {
3114 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3115 if (dev->phy.rev >= 3) {
3116 /* TODO */
3117 }
3118 }
3119
3120 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3121
3122 if (nphy->hang_avoid)
3123 b43_nphy_stay_in_carrier_search(dev, false);
3124
3125 b43_mac_enable(dev);
3126 }
3127
3128 /*
3129 * Init N-PHY
3130 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3131 */
3132 int b43_phy_initn(struct b43_wldev *dev)
3133 {
3134 struct ssb_bus *bus = dev->dev->bus;
3135 struct b43_phy *phy = &dev->phy;
3136 struct b43_phy_n *nphy = phy->n;
3137 u8 tx_pwr_state;
3138 struct nphy_txgains target;
3139 u16 tmp;
3140 enum ieee80211_band tmp2;
3141 bool do_rssi_cal;
3142
3143 u16 clip[2];
3144 bool do_cal = false;
3145
3146 if ((dev->phy.rev >= 3) &&
3147 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3148 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3149 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3150 }
3151 nphy->deaf_count = 0;
3152 b43_nphy_tables_init(dev);
3153 nphy->crsminpwr_adjusted = false;
3154 nphy->noisevars_adjusted = false;
3155
3156 /* Clear all overrides */
3157 if (dev->phy.rev >= 3) {
3158 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3159 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3160 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3161 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3162 } else {
3163 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3164 }
3165 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3166 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3167 if (dev->phy.rev < 6) {
3168 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3169 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3170 }
3171 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3172 ~(B43_NPHY_RFSEQMODE_CAOVER |
3173 B43_NPHY_RFSEQMODE_TROVER));
3174 if (dev->phy.rev >= 3)
3175 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3176 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3177
3178 if (dev->phy.rev <= 2) {
3179 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3180 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3181 ~B43_NPHY_BPHY_CTL3_SCALE,
3182 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3183 }
3184 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3185 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3186
3187 if (bus->sprom.boardflags2_lo & 0x100 ||
3188 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3189 bus->boardinfo.type == 0x8B))
3190 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3191 else
3192 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3193 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3194 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3195 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3196
3197 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3198 b43_nphy_update_txrx_chain(dev);
3199
3200 if (phy->rev < 2) {
3201 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3202 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3203 }
3204
3205 tmp2 = b43_current_band(dev->wl);
3206 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3207 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3208 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3209 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3210 nphy->papd_epsilon_offset[0] << 7);
3211 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3212 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3213 nphy->papd_epsilon_offset[1] << 7);
3214 b43_nphy_int_pa_set_tx_dig_filters(dev);
3215 } else if (phy->rev >= 5) {
3216 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3217 }
3218
3219 b43_nphy_workarounds(dev);
3220
3221 /* Reset CCA, in init code it differs a little from standard way */
3222 b43_nphy_bmac_clock_fgc(dev, 1);
3223 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3224 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3225 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3226 b43_nphy_bmac_clock_fgc(dev, 0);
3227
3228 b43_nphy_mac_phy_clock_set(dev, true);
3229
3230 b43_nphy_pa_override(dev, false);
3231 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3232 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3233 b43_nphy_pa_override(dev, true);
3234
3235 b43_nphy_classifier(dev, 0, 0);
3236 b43_nphy_read_clip_detection(dev, clip);
3237 tx_pwr_state = nphy->txpwrctrl;
3238 /* TODO N PHY TX power control with argument 0
3239 (turning off power control) */
3240 /* TODO Fix the TX Power Settings */
3241 /* TODO N PHY TX Power Control Idle TSSI */
3242 /* TODO N PHY TX Power Control Setup */
3243
3244 if (phy->rev >= 3) {
3245 /* TODO */
3246 } else {
3247 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3248 b43_ntab_tx_gain_rev0_1_2);
3249 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3250 b43_ntab_tx_gain_rev0_1_2);
3251 }
3252
3253 if (nphy->phyrxchain != 3)
3254 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3255 if (nphy->mphase_cal_phase_id > 0)
3256 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3257
3258 do_rssi_cal = false;
3259 if (phy->rev >= 3) {
3260 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3261 do_rssi_cal =
3262 b43_empty_chanspec(&nphy->rssical_chanspec_2G);
3263 else
3264 do_rssi_cal =
3265 b43_empty_chanspec(&nphy->rssical_chanspec_5G);
3266
3267 if (do_rssi_cal)
3268 b43_nphy_rssi_cal(dev);
3269 else
3270 b43_nphy_restore_rssi_cal(dev);
3271 } else {
3272 b43_nphy_rssi_cal(dev);
3273 }
3274
3275 if (!((nphy->measure_hold & 0x6) != 0)) {
3276 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3277 do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_2G);
3278 else
3279 do_cal = b43_empty_chanspec(&nphy->iqcal_chanspec_5G);
3280
3281 if (nphy->mute)
3282 do_cal = false;
3283
3284 if (do_cal) {
3285 target = b43_nphy_get_tx_gains(dev);
3286
3287 if (nphy->antsel_type == 2)
3288 b43_nphy_superswitch_init(dev, true);
3289 if (nphy->perical != 2) {
3290 b43_nphy_rssi_cal(dev);
3291 if (phy->rev >= 3) {
3292 nphy->cal_orig_pwr_idx[0] =
3293 nphy->txpwrindex[0].index_internal;
3294 nphy->cal_orig_pwr_idx[1] =
3295 nphy->txpwrindex[1].index_internal;
3296 /* TODO N PHY Pre Calibrate TX Gain */
3297 target = b43_nphy_get_tx_gains(dev);
3298 }
3299 }
3300 }
3301 }
3302
3303 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3304 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3305 b43_nphy_save_cal(dev);
3306 else if (nphy->mphase_cal_phase_id == 0)
3307 ;/* N PHY Periodic Calibration with argument 3 */
3308 } else {
3309 b43_nphy_restore_cal(dev);
3310 }
3311
3312 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3313 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3314 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3315 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3316 if (phy->rev >= 3 && phy->rev <= 6)
3317 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3318 b43_nphy_tx_lp_fbw(dev);
3319 if (phy->rev >= 3)
3320 b43_nphy_spur_workaround(dev);
3321
3322 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3323 return 0;
3324 }
3325
3326 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3327 static void b43_nphy_chanspec_setup(struct b43_wldev *dev,
3328 const struct b43_phy_n_sfo_cfg *e,
3329 struct b43_chanspec chanspec)
3330 {
3331 struct b43_phy *phy = &dev->phy;
3332 struct b43_phy_n *nphy = dev->phy.n;
3333
3334 u16 tmp;
3335 u32 tmp32;
3336
3337 tmp = b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3338 if (chanspec.b_freq == 1 && tmp == 0) {
3339 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3340 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3341 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3342 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3343 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3344 } else if (chanspec.b_freq == 1) {
3345 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3346 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3347 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3348 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3349 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3350 }
3351
3352 b43_chantab_phy_upload(dev, e);
3353
3354 tmp = chanspec.channel;
3355 if (chanspec.b_freq == 1)
3356 tmp |= 0x0100;
3357 if (chanspec.b_width == 3)
3358 tmp |= 0x0200;
3359 b43_shm_write16(dev, B43_SHM_SHARED, 0xA0, tmp);
3360
3361 if (nphy->radio_chanspec.channel == 14) {
3362 b43_nphy_classifier(dev, 2, 0);
3363 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3364 } else {
3365 b43_nphy_classifier(dev, 2, 2);
3366 if (chanspec.b_freq == 2)
3367 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3368 }
3369
3370 if (nphy->txpwrctrl)
3371 b43_nphy_tx_power_fix(dev);
3372
3373 if (dev->phy.rev < 3)
3374 b43_nphy_adjust_lna_gain_table(dev);
3375
3376 b43_nphy_tx_lp_fbw(dev);
3377
3378 if (dev->phy.rev >= 3 && 0) {
3379 /* TODO */
3380 }
3381
3382 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3383
3384 if (phy->rev >= 3)
3385 b43_nphy_spur_workaround(dev);
3386 }
3387
3388 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3389 static int b43_nphy_set_chanspec(struct b43_wldev *dev,
3390 struct b43_chanspec chanspec)
3391 {
3392 struct b43_phy_n *nphy = dev->phy.n;
3393
3394 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3395 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
3396
3397 u8 tmp;
3398 u8 channel = chanspec.channel;
3399
3400 if (dev->phy.rev >= 3) {
3401 /* TODO */
3402 tabent_r3 = NULL;
3403 if (!tabent_r3)
3404 return -ESRCH;
3405 } else {
3406 tabent_r2 = b43_nphy_get_chantabent_rev2(dev, channel);
3407 if (!tabent_r2)
3408 return -ESRCH;
3409 }
3410
3411 nphy->radio_chanspec = chanspec;
3412
3413 if (chanspec.b_width != nphy->b_width)
3414 ; /* TODO: BMAC BW Set (chanspec.b_width) */
3415
3416 /* TODO: use defines */
3417 if (chanspec.b_width == 3) {
3418 if (chanspec.sideband == 2)
3419 b43_phy_set(dev, B43_NPHY_RXCTL,
3420 B43_NPHY_RXCTL_BSELU20);
3421 else
3422 b43_phy_mask(dev, B43_NPHY_RXCTL,
3423 ~B43_NPHY_RXCTL_BSELU20);
3424 }
3425
3426 if (dev->phy.rev >= 3) {
3427 tmp = (chanspec.b_freq == 1) ? 4 : 0;
3428 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3429 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
3430 b43_nphy_chanspec_setup(dev, &(tabent_r3->phy_regs), chanspec);
3431 } else {
3432 tmp = (chanspec.b_freq == 1) ? 0x0020 : 0x0050;
3433 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3434 b43_radio_2055_setup(dev, tabent_r2);
3435 b43_nphy_chanspec_setup(dev, &(tabent_r2->phy_regs), chanspec);
3436 }
3437
3438 return 0;
3439 }
3440
3441 /* Tune the hardware to a new channel */
3442 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
3443 {
3444 struct b43_phy_n *nphy = dev->phy.n;
3445
3446 struct b43_chanspec chanspec;
3447 chanspec = nphy->radio_chanspec;
3448 chanspec.channel = channel;
3449
3450 return b43_nphy_set_chanspec(dev, chanspec);
3451 }
3452
3453 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3454 {
3455 struct b43_phy_n *nphy;
3456
3457 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3458 if (!nphy)
3459 return -ENOMEM;
3460 dev->phy.n = nphy;
3461
3462 return 0;
3463 }
3464
3465 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3466 {
3467 struct b43_phy *phy = &dev->phy;
3468 struct b43_phy_n *nphy = phy->n;
3469
3470 memset(nphy, 0, sizeof(*nphy));
3471
3472 //TODO init struct b43_phy_n
3473 }
3474
3475 static void b43_nphy_op_free(struct b43_wldev *dev)
3476 {
3477 struct b43_phy *phy = &dev->phy;
3478 struct b43_phy_n *nphy = phy->n;
3479
3480 kfree(nphy);
3481 phy->n = NULL;
3482 }
3483
3484 static int b43_nphy_op_init(struct b43_wldev *dev)
3485 {
3486 return b43_phy_initn(dev);
3487 }
3488
3489 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3490 {
3491 #if B43_DEBUG
3492 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3493 /* OFDM registers are onnly available on A/G-PHYs */
3494 b43err(dev->wl, "Invalid OFDM PHY access at "
3495 "0x%04X on N-PHY\n", offset);
3496 dump_stack();
3497 }
3498 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3499 /* Ext-G registers are only available on G-PHYs */
3500 b43err(dev->wl, "Invalid EXT-G PHY access at "
3501 "0x%04X on N-PHY\n", offset);
3502 dump_stack();
3503 }
3504 #endif /* B43_DEBUG */
3505 }
3506
3507 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3508 {
3509 check_phyreg(dev, reg);
3510 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3511 return b43_read16(dev, B43_MMIO_PHY_DATA);
3512 }
3513
3514 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3515 {
3516 check_phyreg(dev, reg);
3517 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3518 b43_write16(dev, B43_MMIO_PHY_DATA, value);
3519 }
3520
3521 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3522 {
3523 /* Register 1 is a 32-bit register. */
3524 B43_WARN_ON(reg == 1);
3525 /* N-PHY needs 0x100 for read access */
3526 reg |= 0x100;
3527
3528 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3529 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3530 }
3531
3532 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3533 {
3534 /* Register 1 is a 32-bit register. */
3535 B43_WARN_ON(reg == 1);
3536
3537 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3538 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3539 }
3540
3541 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3542 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3543 bool blocked)
3544 {
3545 struct b43_phy_n *nphy = dev->phy.n;
3546
3547 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3548 b43err(dev->wl, "MAC not suspended\n");
3549
3550 if (blocked) {
3551 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3552 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3553 if (dev->phy.rev >= 3) {
3554 b43_radio_mask(dev, 0x09, ~0x2);
3555
3556 b43_radio_write(dev, 0x204D, 0);
3557 b43_radio_write(dev, 0x2053, 0);
3558 b43_radio_write(dev, 0x2058, 0);
3559 b43_radio_write(dev, 0x205E, 0);
3560 b43_radio_mask(dev, 0x2062, ~0xF0);
3561 b43_radio_write(dev, 0x2064, 0);
3562
3563 b43_radio_write(dev, 0x304D, 0);
3564 b43_radio_write(dev, 0x3053, 0);
3565 b43_radio_write(dev, 0x3058, 0);
3566 b43_radio_write(dev, 0x305E, 0);
3567 b43_radio_mask(dev, 0x3062, ~0xF0);
3568 b43_radio_write(dev, 0x3064, 0);
3569 }
3570 } else {
3571 if (dev->phy.rev >= 3) {
3572 b43_radio_init2056(dev);
3573 b43_nphy_set_chanspec(dev, nphy->radio_chanspec);
3574 } else {
3575 b43_radio_init2055(dev);
3576 }
3577 }
3578 }
3579
3580 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3581 {
3582 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3583 on ? 0 : 0x7FFF);
3584 }
3585
3586 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3587 unsigned int new_channel)
3588 {
3589 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3590 if ((new_channel < 1) || (new_channel > 14))
3591 return -EINVAL;
3592 } else {
3593 if (new_channel > 200)
3594 return -EINVAL;
3595 }
3596
3597 return nphy_channel_switch(dev, new_channel);
3598 }
3599
3600 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3601 {
3602 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3603 return 1;
3604 return 36;
3605 }
3606
3607 const struct b43_phy_operations b43_phyops_n = {
3608 .allocate = b43_nphy_op_allocate,
3609 .free = b43_nphy_op_free,
3610 .prepare_structs = b43_nphy_op_prepare_structs,
3611 .init = b43_nphy_op_init,
3612 .phy_read = b43_nphy_op_read,
3613 .phy_write = b43_nphy_op_write,
3614 .radio_read = b43_nphy_op_radio_read,
3615 .radio_write = b43_nphy_op_radio_write,
3616 .software_rfkill = b43_nphy_op_software_rfkill,
3617 .switch_analog = b43_nphy_op_switch_analog,
3618 .switch_channel = b43_nphy_op_switch_channel,
3619 .get_default_chan = b43_nphy_op_get_default_chan,
3620 .recalc_txpower = b43_nphy_op_recalc_txpower,
3621 .adjust_txpower = b43_nphy_op_adjust_txpower,
3622 };
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