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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / b43 / phy_n.c
1 /*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23 */
24
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/types.h>
28
29 #include "b43.h"
30 #include "phy_n.h"
31 #include "tables_nphy.h"
32 #include "radio_2055.h"
33 #include "radio_2056.h"
34 #include "main.h"
35
36 struct nphy_txgains {
37 u16 txgm[2];
38 u16 pga[2];
39 u16 pad[2];
40 u16 ipa[2];
41 };
42
43 struct nphy_iqcal_params {
44 u16 txgm;
45 u16 pga;
46 u16 pad;
47 u16 ipa;
48 u16 cal_gain;
49 u16 ncorr[5];
50 };
51
52 struct nphy_iq_est {
53 s32 iq0_prod;
54 u32 i0_pwr;
55 u32 q0_pwr;
56 s32 iq1_prod;
57 u32 i1_pwr;
58 u32 q1_pwr;
59 };
60
61 enum b43_nphy_rf_sequence {
62 B43_RFSEQ_RX2TX,
63 B43_RFSEQ_TX2RX,
64 B43_RFSEQ_RESET2RX,
65 B43_RFSEQ_UPDATE_GAINH,
66 B43_RFSEQ_UPDATE_GAINL,
67 B43_RFSEQ_UPDATE_GAINU,
68 };
69
70 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
71 u8 *events, u8 *delays, u8 length);
72 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
73 enum b43_nphy_rf_sequence seq);
74 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
75 u16 value, u8 core, bool off);
76 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
77 u16 value, u8 core);
78
79 static inline bool b43_channel_type_is_40mhz(
80 enum nl80211_channel_type channel_type)
81 {
82 return (channel_type == NL80211_CHAN_HT40MINUS ||
83 channel_type == NL80211_CHAN_HT40PLUS);
84 }
85
86 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
87 {//TODO
88 }
89
90 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
91 {//TODO
92 }
93
94 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
95 bool ignore_tssi)
96 {//TODO
97 return B43_TXPWR_RES_DONE;
98 }
99
100 static void b43_chantab_radio_upload(struct b43_wldev *dev,
101 const struct b43_nphy_channeltab_entry_rev2 *e)
102 {
103 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
104 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
105 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
106 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
107 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
108
109 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
110 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
111 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
112 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
113 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
114
115 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
116 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
117 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
118 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
119 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
120
121 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
122 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
123 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
124 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
125 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
126
127 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
128 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
129 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
130 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
131 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
132
133 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
134 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
135 }
136
137 static void b43_chantab_phy_upload(struct b43_wldev *dev,
138 const struct b43_phy_n_sfo_cfg *e)
139 {
140 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
141 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
142 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
143 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
144 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
145 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
146 }
147
148 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
149 {
150 //TODO
151 }
152
153
154 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
155 static void b43_radio_2055_setup(struct b43_wldev *dev,
156 const struct b43_nphy_channeltab_entry_rev2 *e)
157 {
158 B43_WARN_ON(dev->phy.rev >= 3);
159
160 b43_chantab_radio_upload(dev, e);
161 udelay(50);
162 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
163 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
164 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
165 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
166 udelay(300);
167 }
168
169 static void b43_radio_init2055_pre(struct b43_wldev *dev)
170 {
171 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
172 ~B43_NPHY_RFCTL_CMD_PORFORCE);
173 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
174 B43_NPHY_RFCTL_CMD_CHIP0PU |
175 B43_NPHY_RFCTL_CMD_OEPORFORCE);
176 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
177 B43_NPHY_RFCTL_CMD_PORFORCE);
178 }
179
180 static void b43_radio_init2055_post(struct b43_wldev *dev)
181 {
182 struct b43_phy_n *nphy = dev->phy.n;
183 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
184 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
185 int i;
186 u16 val;
187 bool workaround = false;
188
189 if (sprom->revision < 4)
190 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
191 binfo->type != 0x46D ||
192 binfo->rev < 0x41);
193 else
194 workaround = ((sprom->boardflags_hi & B43_BFH_NOPA) == 0);
195
196 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
197 if (workaround) {
198 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
199 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
200 }
201 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
202 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
203 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
204 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
205 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
206 msleep(1);
207 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
208 for (i = 0; i < 200; i++) {
209 val = b43_radio_read(dev, B2055_CAL_COUT2);
210 if (val & 0x80) {
211 i = 0;
212 break;
213 }
214 udelay(10);
215 }
216 if (i)
217 b43err(dev->wl, "radio post init timeout\n");
218 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
219 b43_switch_channel(dev, dev->phy.channel);
220 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
221 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
222 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
223 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
224 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
225 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
226 if (!nphy->gain_boost) {
227 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
228 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
229 } else {
230 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
231 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
232 }
233 udelay(2);
234 }
235
236 /*
237 * Initialize a Broadcom 2055 N-radio
238 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
239 */
240 static void b43_radio_init2055(struct b43_wldev *dev)
241 {
242 b43_radio_init2055_pre(dev);
243 if (b43_status(dev) < B43_STAT_INITIALIZED)
244 b2055_upload_inittab(dev, 0, 1);
245 else
246 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
247 b43_radio_init2055_post(dev);
248 }
249
250 /*
251 * Initialize a Broadcom 2056 N-radio
252 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
253 */
254 static void b43_radio_init2056(struct b43_wldev *dev)
255 {
256 /* TODO */
257 }
258
259
260 /*
261 * Upload the N-PHY tables.
262 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
263 */
264 static void b43_nphy_tables_init(struct b43_wldev *dev)
265 {
266 if (dev->phy.rev < 3)
267 b43_nphy_rev0_1_2_tables_init(dev);
268 else
269 b43_nphy_rev3plus_tables_init(dev);
270 }
271
272 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
273 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
274 {
275 struct b43_phy_n *nphy = dev->phy.n;
276 enum ieee80211_band band;
277 u16 tmp;
278
279 if (!enable) {
280 nphy->rfctrl_intc1_save = b43_phy_read(dev,
281 B43_NPHY_RFCTL_INTC1);
282 nphy->rfctrl_intc2_save = b43_phy_read(dev,
283 B43_NPHY_RFCTL_INTC2);
284 band = b43_current_band(dev->wl);
285 if (dev->phy.rev >= 3) {
286 if (band == IEEE80211_BAND_5GHZ)
287 tmp = 0x600;
288 else
289 tmp = 0x480;
290 } else {
291 if (band == IEEE80211_BAND_5GHZ)
292 tmp = 0x180;
293 else
294 tmp = 0x120;
295 }
296 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
297 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
298 } else {
299 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
300 nphy->rfctrl_intc1_save);
301 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
302 nphy->rfctrl_intc2_save);
303 }
304 }
305
306 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
307 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
308 {
309 struct b43_phy_n *nphy = dev->phy.n;
310 u16 tmp;
311 enum ieee80211_band band = b43_current_band(dev->wl);
312 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
313 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
314
315 if (dev->phy.rev >= 3) {
316 if (ipa) {
317 tmp = 4;
318 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
319 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
320 }
321
322 tmp = 1;
323 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
324 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
325 }
326 }
327
328 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
329 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
330 {
331 u32 tmslow;
332
333 if (dev->phy.type != B43_PHYTYPE_N)
334 return;
335
336 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
337 if (force)
338 tmslow |= SSB_TMSLOW_FGC;
339 else
340 tmslow &= ~SSB_TMSLOW_FGC;
341 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
342 }
343
344 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
345 static void b43_nphy_reset_cca(struct b43_wldev *dev)
346 {
347 u16 bbcfg;
348
349 b43_nphy_bmac_clock_fgc(dev, 1);
350 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
351 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
352 udelay(1);
353 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
354 b43_nphy_bmac_clock_fgc(dev, 0);
355 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
356 }
357
358 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
359 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
360 {
361 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
362
363 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
364 if (preamble == 1)
365 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
366 else
367 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
368
369 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
370 }
371
372 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
373 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
374 {
375 struct b43_phy_n *nphy = dev->phy.n;
376
377 bool override = false;
378 u16 chain = 0x33;
379
380 if (nphy->txrx_chain == 0) {
381 chain = 0x11;
382 override = true;
383 } else if (nphy->txrx_chain == 1) {
384 chain = 0x22;
385 override = true;
386 }
387
388 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
389 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
390 chain);
391
392 if (override)
393 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
394 B43_NPHY_RFSEQMODE_CAOVER);
395 else
396 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
397 ~B43_NPHY_RFSEQMODE_CAOVER);
398 }
399
400 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
401 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
402 u16 samps, u8 time, bool wait)
403 {
404 int i;
405 u16 tmp;
406
407 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
408 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
409 if (wait)
410 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
411 else
412 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
413
414 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
415
416 for (i = 1000; i; i--) {
417 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
418 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
419 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
420 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
421 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
422 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
423 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
424 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
425
426 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
427 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
428 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
429 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
430 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
431 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
432 return;
433 }
434 udelay(10);
435 }
436 memset(est, 0, sizeof(*est));
437 }
438
439 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
440 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
441 struct b43_phy_n_iq_comp *pcomp)
442 {
443 if (write) {
444 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
445 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
446 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
447 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
448 } else {
449 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
450 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
451 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
452 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
453 }
454 }
455
456 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
457 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
458 {
459 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
460
461 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
462 if (core == 0) {
463 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
464 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
465 } else {
466 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
467 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
468 }
469 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
470 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
471 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
472 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
473 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
474 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
475 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
476 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
477 }
478
479 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
480 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
481 {
482 u8 rxval, txval;
483 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
484
485 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
486 if (core == 0) {
487 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
488 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
489 } else {
490 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
491 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
492 }
493 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
494 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
495 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
496 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
497 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
498 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
499 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
500 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
501
502 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
503 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
504
505 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
506 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
507 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
508 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
509 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
510 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
511 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
512 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
513 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
514
515 if (core == 0) {
516 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
517 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
518 } else {
519 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
520 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
521 }
522
523 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
524 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
525 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
526
527 if (core == 0) {
528 rxval = 1;
529 txval = 8;
530 } else {
531 rxval = 4;
532 txval = 2;
533 }
534 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
535 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
536 }
537
538 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
539 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
540 {
541 int i;
542 s32 iq;
543 u32 ii;
544 u32 qq;
545 int iq_nbits, qq_nbits;
546 int arsh, brsh;
547 u16 tmp, a, b;
548
549 struct nphy_iq_est est;
550 struct b43_phy_n_iq_comp old;
551 struct b43_phy_n_iq_comp new = { };
552 bool error = false;
553
554 if (mask == 0)
555 return;
556
557 b43_nphy_rx_iq_coeffs(dev, false, &old);
558 b43_nphy_rx_iq_coeffs(dev, true, &new);
559 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
560 new = old;
561
562 for (i = 0; i < 2; i++) {
563 if (i == 0 && (mask & 1)) {
564 iq = est.iq0_prod;
565 ii = est.i0_pwr;
566 qq = est.q0_pwr;
567 } else if (i == 1 && (mask & 2)) {
568 iq = est.iq1_prod;
569 ii = est.i1_pwr;
570 qq = est.q1_pwr;
571 } else {
572 B43_WARN_ON(1);
573 continue;
574 }
575
576 if (ii + qq < 2) {
577 error = true;
578 break;
579 }
580
581 iq_nbits = fls(abs(iq));
582 qq_nbits = fls(qq);
583
584 arsh = iq_nbits - 20;
585 if (arsh >= 0) {
586 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
587 tmp = ii >> arsh;
588 } else {
589 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
590 tmp = ii << -arsh;
591 }
592 if (tmp == 0) {
593 error = true;
594 break;
595 }
596 a /= tmp;
597
598 brsh = qq_nbits - 11;
599 if (brsh >= 0) {
600 b = (qq << (31 - qq_nbits));
601 tmp = ii >> brsh;
602 } else {
603 b = (qq << (31 - qq_nbits));
604 tmp = ii << -brsh;
605 }
606 if (tmp == 0) {
607 error = true;
608 break;
609 }
610 b = int_sqrt(b / tmp - a * a) - (1 << 10);
611
612 if (i == 0 && (mask & 0x1)) {
613 if (dev->phy.rev >= 3) {
614 new.a0 = a & 0x3FF;
615 new.b0 = b & 0x3FF;
616 } else {
617 new.a0 = b & 0x3FF;
618 new.b0 = a & 0x3FF;
619 }
620 } else if (i == 1 && (mask & 0x2)) {
621 if (dev->phy.rev >= 3) {
622 new.a1 = a & 0x3FF;
623 new.b1 = b & 0x3FF;
624 } else {
625 new.a1 = b & 0x3FF;
626 new.b1 = a & 0x3FF;
627 }
628 }
629 }
630
631 if (error)
632 new = old;
633
634 b43_nphy_rx_iq_coeffs(dev, true, &new);
635 }
636
637 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
638 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
639 {
640 u16 array[4];
641 int i;
642
643 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
644 for (i = 0; i < 4; i++)
645 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
646
647 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
648 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
649 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
650 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
651 }
652
653 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
654 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
655 {
656 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
657 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
658 }
659
660 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
661 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
662 {
663 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
664 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
665 }
666
667 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
668 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
669 {
670 if (dev->phy.rev >= 3) {
671 if (!init)
672 return;
673 if (0 /* FIXME */) {
674 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
675 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
676 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
677 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
678 }
679 } else {
680 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
681 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
682
683 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
684 0xFC00);
685 b43_write32(dev, B43_MMIO_MACCTL,
686 b43_read32(dev, B43_MMIO_MACCTL) &
687 ~B43_MACCTL_GPOUTSMSK);
688 b43_write16(dev, B43_MMIO_GPIO_MASK,
689 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
690 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
691 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
692
693 if (init) {
694 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
695 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
696 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
697 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
698 }
699 }
700 }
701
702 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
703 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
704 {
705 u16 tmp;
706
707 if (dev->dev->id.revision == 16)
708 b43_mac_suspend(dev);
709
710 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
711 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
712 B43_NPHY_CLASSCTL_WAITEDEN);
713 tmp &= ~mask;
714 tmp |= (val & mask);
715 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
716
717 if (dev->dev->id.revision == 16)
718 b43_mac_enable(dev);
719
720 return tmp;
721 }
722
723 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
724 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
725 {
726 struct b43_phy *phy = &dev->phy;
727 struct b43_phy_n *nphy = phy->n;
728
729 if (enable) {
730 u16 clip[] = { 0xFFFF, 0xFFFF };
731 if (nphy->deaf_count++ == 0) {
732 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
733 b43_nphy_classifier(dev, 0x7, 0);
734 b43_nphy_read_clip_detection(dev, nphy->clip_state);
735 b43_nphy_write_clip_detection(dev, clip);
736 }
737 b43_nphy_reset_cca(dev);
738 } else {
739 if (--nphy->deaf_count == 0) {
740 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
741 b43_nphy_write_clip_detection(dev, nphy->clip_state);
742 }
743 }
744 }
745
746 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
747 static void b43_nphy_stop_playback(struct b43_wldev *dev)
748 {
749 struct b43_phy_n *nphy = dev->phy.n;
750 u16 tmp;
751
752 if (nphy->hang_avoid)
753 b43_nphy_stay_in_carrier_search(dev, 1);
754
755 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
756 if (tmp & 0x1)
757 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
758 else if (tmp & 0x2)
759 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
760
761 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
762
763 if (nphy->bb_mult_save & 0x80000000) {
764 tmp = nphy->bb_mult_save & 0xFFFF;
765 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
766 nphy->bb_mult_save = 0;
767 }
768
769 if (nphy->hang_avoid)
770 b43_nphy_stay_in_carrier_search(dev, 0);
771 }
772
773 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
774 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
775 {
776 struct b43_phy_n *nphy = dev->phy.n;
777
778 u8 channel = dev->phy.channel;
779 int tone[2] = { 57, 58 };
780 u32 noise[2] = { 0x3FF, 0x3FF };
781
782 B43_WARN_ON(dev->phy.rev < 3);
783
784 if (nphy->hang_avoid)
785 b43_nphy_stay_in_carrier_search(dev, 1);
786
787 if (nphy->gband_spurwar_en) {
788 /* TODO: N PHY Adjust Analog Pfbw (7) */
789 if (channel == 11 && dev->phy.is_40mhz)
790 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
791 else
792 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
793 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
794 }
795
796 if (nphy->aband_spurwar_en) {
797 if (channel == 54) {
798 tone[0] = 0x20;
799 noise[0] = 0x25F;
800 } else if (channel == 38 || channel == 102 || channel == 118) {
801 if (0 /* FIXME */) {
802 tone[0] = 0x20;
803 noise[0] = 0x21F;
804 } else {
805 tone[0] = 0;
806 noise[0] = 0;
807 }
808 } else if (channel == 134) {
809 tone[0] = 0x20;
810 noise[0] = 0x21F;
811 } else if (channel == 151) {
812 tone[0] = 0x10;
813 noise[0] = 0x23F;
814 } else if (channel == 153 || channel == 161) {
815 tone[0] = 0x30;
816 noise[0] = 0x23F;
817 } else {
818 tone[0] = 0;
819 noise[0] = 0;
820 }
821
822 if (!tone[0] && !noise[0])
823 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
824 else
825 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
826 }
827
828 if (nphy->hang_avoid)
829 b43_nphy_stay_in_carrier_search(dev, 0);
830 }
831
832 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
833 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
834 {
835 struct b43_phy_n *nphy = dev->phy.n;
836
837 u8 i;
838 s16 tmp;
839 u16 data[4];
840 s16 gain[2];
841 u16 minmax[2];
842 u16 lna_gain[4] = { -2, 10, 19, 25 };
843
844 if (nphy->hang_avoid)
845 b43_nphy_stay_in_carrier_search(dev, 1);
846
847 if (nphy->gain_boost) {
848 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
849 gain[0] = 6;
850 gain[1] = 6;
851 } else {
852 tmp = 40370 - 315 * dev->phy.channel;
853 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
854 tmp = 23242 - 224 * dev->phy.channel;
855 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
856 }
857 } else {
858 gain[0] = 0;
859 gain[1] = 0;
860 }
861
862 for (i = 0; i < 2; i++) {
863 if (nphy->elna_gain_config) {
864 data[0] = 19 + gain[i];
865 data[1] = 25 + gain[i];
866 data[2] = 25 + gain[i];
867 data[3] = 25 + gain[i];
868 } else {
869 data[0] = lna_gain[0] + gain[i];
870 data[1] = lna_gain[1] + gain[i];
871 data[2] = lna_gain[2] + gain[i];
872 data[3] = lna_gain[3] + gain[i];
873 }
874 b43_ntab_write_bulk(dev, B43_NTAB16(10, 8), 4, data);
875
876 minmax[i] = 23 + gain[i];
877 }
878
879 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
880 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
881 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
882 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
883
884 if (nphy->hang_avoid)
885 b43_nphy_stay_in_carrier_search(dev, 0);
886 }
887
888 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
889 static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
890 {
891 struct b43_phy_n *nphy = dev->phy.n;
892 u8 i, j;
893 u8 code;
894
895 /* TODO: for PHY >= 3
896 s8 *lna1_gain, *lna2_gain;
897 u8 *gain_db, *gain_bits;
898 u16 *rfseq_init;
899 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
900 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
901 */
902
903 u8 rfseq_events[3] = { 6, 8, 7 };
904 u8 rfseq_delays[3] = { 10, 30, 1 };
905
906 if (dev->phy.rev >= 3) {
907 /* TODO */
908 } else {
909 /* Set Clip 2 detect */
910 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
911 B43_NPHY_C1_CGAINI_CL2DETECT);
912 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
913 B43_NPHY_C2_CGAINI_CL2DETECT);
914
915 /* Set narrowband clip threshold */
916 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
917 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
918
919 if (!dev->phy.is_40mhz) {
920 /* Set dwell lengths */
921 b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
922 b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
923 b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
924 b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
925 }
926
927 /* Set wideband clip 2 threshold */
928 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
929 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
930 21);
931 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
932 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
933 21);
934
935 if (!dev->phy.is_40mhz) {
936 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
937 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
938 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
939 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
940 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
941 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
942 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
943 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
944 }
945
946 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
947
948 if (nphy->gain_boost) {
949 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
950 dev->phy.is_40mhz)
951 code = 4;
952 else
953 code = 5;
954 } else {
955 code = dev->phy.is_40mhz ? 6 : 7;
956 }
957
958 /* Set HPVGA2 index */
959 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
960 ~B43_NPHY_C1_INITGAIN_HPVGA2,
961 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
962 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
963 ~B43_NPHY_C2_INITGAIN_HPVGA2,
964 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
965
966 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
967 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
968 (code << 8 | 0x7C));
969 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
970 (code << 8 | 0x7C));
971
972 b43_nphy_adjust_lna_gain_table(dev);
973
974 if (nphy->elna_gain_config) {
975 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
976 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
977 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
978 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
979 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
980
981 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
982 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
983 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
984 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
985 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
986
987 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
988 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
989 (code << 8 | 0x74));
990 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
991 (code << 8 | 0x74));
992 }
993
994 if (dev->phy.rev == 2) {
995 for (i = 0; i < 4; i++) {
996 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
997 (0x0400 * i) + 0x0020);
998 for (j = 0; j < 21; j++)
999 b43_phy_write(dev,
1000 B43_NPHY_TABLE_DATALO, 3 * j);
1001 }
1002
1003 b43_nphy_set_rf_sequence(dev, 5,
1004 rfseq_events, rfseq_delays, 3);
1005 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1006 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1007 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1008
1009 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1010 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1011 0xFF80, 4);
1012 }
1013 }
1014 }
1015
1016 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1017 static void b43_nphy_workarounds(struct b43_wldev *dev)
1018 {
1019 struct ssb_bus *bus = dev->dev->bus;
1020 struct b43_phy *phy = &dev->phy;
1021 struct b43_phy_n *nphy = phy->n;
1022
1023 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1024 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1025
1026 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1027 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1028
1029 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1030 b43_nphy_classifier(dev, 1, 0);
1031 else
1032 b43_nphy_classifier(dev, 1, 1);
1033
1034 if (nphy->hang_avoid)
1035 b43_nphy_stay_in_carrier_search(dev, 1);
1036
1037 b43_phy_set(dev, B43_NPHY_IQFLIP,
1038 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1039
1040 if (dev->phy.rev >= 3) {
1041 /* TODO */
1042 } else {
1043 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1044 nphy->band5g_pwrgain) {
1045 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1046 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1047 } else {
1048 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1049 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1050 }
1051
1052 /* TODO: convert to b43_ntab_write? */
1053 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
1054 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1055 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
1056 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1057 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
1058 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1059 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
1060 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1061
1062 if (dev->phy.rev < 2) {
1063 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1064 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1065 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1066 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1067 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1068 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1069 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1070 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1071 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1072 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1073 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1074 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1075 }
1076
1077 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1078 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1079 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1080 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1081
1082 if (bus->sprom.boardflags2_lo & 0x100 &&
1083 bus->boardinfo.type == 0x8B) {
1084 delays1[0] = 0x1;
1085 delays1[5] = 0x14;
1086 }
1087 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1088 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
1089
1090 b43_nphy_gain_ctrl_workarounds(dev);
1091
1092 if (dev->phy.rev < 2) {
1093 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
1094 b43_hf_write(dev, b43_hf_read(dev) |
1095 B43_HF_MLADVW);
1096 } else if (dev->phy.rev == 2) {
1097 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1098 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1099 }
1100
1101 if (dev->phy.rev < 2)
1102 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1103 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1104
1105 /* Set phase track alpha and beta */
1106 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1107 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1108 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1109 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1110 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1111 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1112
1113 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
1114 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
1115 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1116 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1117 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1118
1119 if (dev->phy.rev == 2)
1120 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1121 B43_NPHY_FINERX2_CGC_DECGC);
1122 }
1123
1124 if (nphy->hang_avoid)
1125 b43_nphy_stay_in_carrier_search(dev, 0);
1126 }
1127
1128 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1129 static int b43_nphy_load_samples(struct b43_wldev *dev,
1130 struct b43_c32 *samples, u16 len) {
1131 struct b43_phy_n *nphy = dev->phy.n;
1132 u16 i;
1133 u32 *data;
1134
1135 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1136 if (!data) {
1137 b43err(dev->wl, "allocation for samples loading failed\n");
1138 return -ENOMEM;
1139 }
1140 if (nphy->hang_avoid)
1141 b43_nphy_stay_in_carrier_search(dev, 1);
1142
1143 for (i = 0; i < len; i++) {
1144 data[i] = (samples[i].i & 0x3FF << 10);
1145 data[i] |= samples[i].q & 0x3FF;
1146 }
1147 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1148
1149 kfree(data);
1150 if (nphy->hang_avoid)
1151 b43_nphy_stay_in_carrier_search(dev, 0);
1152 return 0;
1153 }
1154
1155 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1156 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1157 bool test)
1158 {
1159 int i;
1160 u16 bw, len, rot, angle;
1161 struct b43_c32 *samples;
1162
1163
1164 bw = (dev->phy.is_40mhz) ? 40 : 20;
1165 len = bw << 3;
1166
1167 if (test) {
1168 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1169 bw = 82;
1170 else
1171 bw = 80;
1172
1173 if (dev->phy.is_40mhz)
1174 bw <<= 1;
1175
1176 len = bw << 1;
1177 }
1178
1179 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
1180 if (!samples) {
1181 b43err(dev->wl, "allocation for samples generation failed\n");
1182 return 0;
1183 }
1184 rot = (((freq * 36) / bw) << 16) / 100;
1185 angle = 0;
1186
1187 for (i = 0; i < len; i++) {
1188 samples[i] = b43_cordic(angle);
1189 angle += rot;
1190 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1191 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
1192 }
1193
1194 i = b43_nphy_load_samples(dev, samples, len);
1195 kfree(samples);
1196 return (i < 0) ? 0 : len;
1197 }
1198
1199 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1200 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1201 u16 wait, bool iqmode, bool dac_test)
1202 {
1203 struct b43_phy_n *nphy = dev->phy.n;
1204 int i;
1205 u16 seq_mode;
1206 u32 tmp;
1207
1208 if (nphy->hang_avoid)
1209 b43_nphy_stay_in_carrier_search(dev, true);
1210
1211 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1212 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1213 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1214 }
1215
1216 if (!dev->phy.is_40mhz)
1217 tmp = 0x6464;
1218 else
1219 tmp = 0x4747;
1220 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1221
1222 if (nphy->hang_avoid)
1223 b43_nphy_stay_in_carrier_search(dev, false);
1224
1225 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1226
1227 if (loops != 0xFFFF)
1228 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1229 else
1230 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1231
1232 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1233
1234 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1235
1236 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1237 if (iqmode) {
1238 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1239 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1240 } else {
1241 if (dac_test)
1242 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1243 else
1244 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1245 }
1246 for (i = 0; i < 100; i++) {
1247 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1248 i = 0;
1249 break;
1250 }
1251 udelay(10);
1252 }
1253 if (i)
1254 b43err(dev->wl, "run samples timeout\n");
1255
1256 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1257 }
1258
1259 /*
1260 * Transmits a known value for LO calibration
1261 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1262 */
1263 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1264 bool iqmode, bool dac_test)
1265 {
1266 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1267 if (samp == 0)
1268 return -1;
1269 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1270 return 0;
1271 }
1272
1273 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1274 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1275 {
1276 struct b43_phy_n *nphy = dev->phy.n;
1277 int i, j;
1278 u32 tmp;
1279 u32 cur_real, cur_imag, real_part, imag_part;
1280
1281 u16 buffer[7];
1282
1283 if (nphy->hang_avoid)
1284 b43_nphy_stay_in_carrier_search(dev, true);
1285
1286 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1287
1288 for (i = 0; i < 2; i++) {
1289 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1290 (buffer[i * 2 + 1] & 0x3FF);
1291 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1292 (((i + 26) << 10) | 320));
1293 for (j = 0; j < 128; j++) {
1294 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1295 ((tmp >> 16) & 0xFFFF));
1296 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1297 (tmp & 0xFFFF));
1298 }
1299 }
1300
1301 for (i = 0; i < 2; i++) {
1302 tmp = buffer[5 + i];
1303 real_part = (tmp >> 8) & 0xFF;
1304 imag_part = (tmp & 0xFF);
1305 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1306 (((i + 26) << 10) | 448));
1307
1308 if (dev->phy.rev >= 3) {
1309 cur_real = real_part;
1310 cur_imag = imag_part;
1311 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1312 }
1313
1314 for (j = 0; j < 128; j++) {
1315 if (dev->phy.rev < 3) {
1316 cur_real = (real_part * loscale[j] + 128) >> 8;
1317 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1318 tmp = ((cur_real & 0xFF) << 8) |
1319 (cur_imag & 0xFF);
1320 }
1321 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1322 ((tmp >> 16) & 0xFFFF));
1323 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1324 (tmp & 0xFFFF));
1325 }
1326 }
1327
1328 if (dev->phy.rev >= 3) {
1329 b43_shm_write16(dev, B43_SHM_SHARED,
1330 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1331 b43_shm_write16(dev, B43_SHM_SHARED,
1332 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1333 }
1334
1335 if (nphy->hang_avoid)
1336 b43_nphy_stay_in_carrier_search(dev, false);
1337 }
1338
1339 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1340 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1341 u8 *events, u8 *delays, u8 length)
1342 {
1343 struct b43_phy_n *nphy = dev->phy.n;
1344 u8 i;
1345 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1346 u16 offset1 = cmd << 4;
1347 u16 offset2 = offset1 + 0x80;
1348
1349 if (nphy->hang_avoid)
1350 b43_nphy_stay_in_carrier_search(dev, true);
1351
1352 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1353 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1354
1355 for (i = length; i < 16; i++) {
1356 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1357 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1358 }
1359
1360 if (nphy->hang_avoid)
1361 b43_nphy_stay_in_carrier_search(dev, false);
1362 }
1363
1364 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1365 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1366 enum b43_nphy_rf_sequence seq)
1367 {
1368 static const u16 trigger[] = {
1369 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1370 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1371 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1372 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1373 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1374 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1375 };
1376 int i;
1377 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1378
1379 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1380
1381 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1382 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1383 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1384 for (i = 0; i < 200; i++) {
1385 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1386 goto ok;
1387 msleep(1);
1388 }
1389 b43err(dev->wl, "RF sequence status timeout\n");
1390 ok:
1391 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1392 }
1393
1394 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1395 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1396 u16 value, u8 core, bool off)
1397 {
1398 int i;
1399 u8 index = fls(field);
1400 u8 addr, en_addr, val_addr;
1401 /* we expect only one bit set */
1402 B43_WARN_ON(field & (~(1 << (index - 1))));
1403
1404 if (dev->phy.rev >= 3) {
1405 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1406 for (i = 0; i < 2; i++) {
1407 if (index == 0 || index == 16) {
1408 b43err(dev->wl,
1409 "Unsupported RF Ctrl Override call\n");
1410 return;
1411 }
1412
1413 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1414 en_addr = B43_PHY_N((i == 0) ?
1415 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1416 val_addr = B43_PHY_N((i == 0) ?
1417 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1418
1419 if (off) {
1420 b43_phy_mask(dev, en_addr, ~(field));
1421 b43_phy_mask(dev, val_addr,
1422 ~(rf_ctrl->val_mask));
1423 } else {
1424 if (core == 0 || ((1 << core) & i) != 0) {
1425 b43_phy_set(dev, en_addr, field);
1426 b43_phy_maskset(dev, val_addr,
1427 ~(rf_ctrl->val_mask),
1428 (value << rf_ctrl->val_shift));
1429 }
1430 }
1431 }
1432 } else {
1433 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1434 if (off) {
1435 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1436 value = 0;
1437 } else {
1438 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1439 }
1440
1441 for (i = 0; i < 2; i++) {
1442 if (index <= 1 || index == 16) {
1443 b43err(dev->wl,
1444 "Unsupported RF Ctrl Override call\n");
1445 return;
1446 }
1447
1448 if (index == 2 || index == 10 ||
1449 (index >= 13 && index <= 15)) {
1450 core = 1;
1451 }
1452
1453 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1454 addr = B43_PHY_N((i == 0) ?
1455 rf_ctrl->addr0 : rf_ctrl->addr1);
1456
1457 if ((core & (1 << i)) != 0)
1458 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1459 (value << rf_ctrl->shift));
1460
1461 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1462 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1463 B43_NPHY_RFCTL_CMD_START);
1464 udelay(1);
1465 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1466 }
1467 }
1468 }
1469
1470 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1471 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1472 u16 value, u8 core)
1473 {
1474 u8 i, j;
1475 u16 reg, tmp, val;
1476
1477 B43_WARN_ON(dev->phy.rev < 3);
1478 B43_WARN_ON(field > 4);
1479
1480 for (i = 0; i < 2; i++) {
1481 if ((core == 1 && i == 1) || (core == 2 && !i))
1482 continue;
1483
1484 reg = (i == 0) ?
1485 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1486 b43_phy_mask(dev, reg, 0xFBFF);
1487
1488 switch (field) {
1489 case 0:
1490 b43_phy_write(dev, reg, 0);
1491 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1492 break;
1493 case 1:
1494 if (!i) {
1495 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1496 0xFC3F, (value << 6));
1497 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1498 0xFFFE, 1);
1499 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1500 B43_NPHY_RFCTL_CMD_START);
1501 for (j = 0; j < 100; j++) {
1502 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1503 j = 0;
1504 break;
1505 }
1506 udelay(10);
1507 }
1508 if (j)
1509 b43err(dev->wl,
1510 "intc override timeout\n");
1511 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1512 0xFFFE);
1513 } else {
1514 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1515 0xFC3F, (value << 6));
1516 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1517 0xFFFE, 1);
1518 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1519 B43_NPHY_RFCTL_CMD_RXTX);
1520 for (j = 0; j < 100; j++) {
1521 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1522 j = 0;
1523 break;
1524 }
1525 udelay(10);
1526 }
1527 if (j)
1528 b43err(dev->wl,
1529 "intc override timeout\n");
1530 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1531 0xFFFE);
1532 }
1533 break;
1534 case 2:
1535 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1536 tmp = 0x0020;
1537 val = value << 5;
1538 } else {
1539 tmp = 0x0010;
1540 val = value << 4;
1541 }
1542 b43_phy_maskset(dev, reg, ~tmp, val);
1543 break;
1544 case 3:
1545 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1546 tmp = 0x0001;
1547 val = value;
1548 } else {
1549 tmp = 0x0004;
1550 val = value << 2;
1551 }
1552 b43_phy_maskset(dev, reg, ~tmp, val);
1553 break;
1554 case 4:
1555 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1556 tmp = 0x0002;
1557 val = value << 1;
1558 } else {
1559 tmp = 0x0008;
1560 val = value << 3;
1561 }
1562 b43_phy_maskset(dev, reg, ~tmp, val);
1563 break;
1564 }
1565 }
1566 }
1567
1568 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1569 {
1570 unsigned int i;
1571 u16 val;
1572
1573 val = 0x1E1F;
1574 for (i = 0; i < 14; i++) {
1575 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1576 val -= 0x202;
1577 }
1578 val = 0x3E3F;
1579 for (i = 0; i < 16; i++) {
1580 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1581 val -= 0x202;
1582 }
1583 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1584 }
1585
1586 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1587 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1588 s8 offset, u8 core, u8 rail, u8 type)
1589 {
1590 u16 tmp;
1591 bool core1or5 = (core == 1) || (core == 5);
1592 bool core2or5 = (core == 2) || (core == 5);
1593
1594 offset = clamp_val(offset, -32, 31);
1595 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1596
1597 if (core1or5 && (rail == 0) && (type == 2))
1598 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1599 if (core1or5 && (rail == 1) && (type == 2))
1600 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1601 if (core2or5 && (rail == 0) && (type == 2))
1602 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1603 if (core2or5 && (rail == 1) && (type == 2))
1604 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1605 if (core1or5 && (rail == 0) && (type == 0))
1606 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1607 if (core1or5 && (rail == 1) && (type == 0))
1608 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1609 if (core2or5 && (rail == 0) && (type == 0))
1610 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1611 if (core2or5 && (rail == 1) && (type == 0))
1612 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1613 if (core1or5 && (rail == 0) && (type == 1))
1614 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1615 if (core1or5 && (rail == 1) && (type == 1))
1616 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1617 if (core2or5 && (rail == 0) && (type == 1))
1618 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1619 if (core2or5 && (rail == 1) && (type == 1))
1620 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1621 if (core1or5 && (rail == 0) && (type == 6))
1622 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1623 if (core1or5 && (rail == 1) && (type == 6))
1624 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1625 if (core2or5 && (rail == 0) && (type == 6))
1626 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1627 if (core2or5 && (rail == 1) && (type == 6))
1628 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1629 if (core1or5 && (rail == 0) && (type == 3))
1630 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1631 if (core1or5 && (rail == 1) && (type == 3))
1632 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1633 if (core2or5 && (rail == 0) && (type == 3))
1634 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1635 if (core2or5 && (rail == 1) && (type == 3))
1636 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1637 if (core1or5 && (type == 4))
1638 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1639 if (core2or5 && (type == 4))
1640 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1641 if (core1or5 && (type == 5))
1642 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1643 if (core2or5 && (type == 5))
1644 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1645 }
1646
1647 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1648 {
1649 u16 val;
1650
1651 if (type < 3)
1652 val = 0;
1653 else if (type == 6)
1654 val = 1;
1655 else if (type == 3)
1656 val = 2;
1657 else
1658 val = 3;
1659
1660 val = (val << 12) | (val << 14);
1661 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1662 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1663
1664 if (type < 3) {
1665 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1666 (type + 1) << 4);
1667 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1668 (type + 1) << 4);
1669 }
1670
1671 /* TODO use some definitions */
1672 if (code == 0) {
1673 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1674 if (type < 3) {
1675 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1676 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1677 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1678 udelay(20);
1679 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1680 }
1681 } else {
1682 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1683 0x3000);
1684 if (type < 3) {
1685 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1686 0xFEC7, 0x0180);
1687 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1688 0xEFDC, (code << 1 | 0x1021));
1689 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1690 udelay(20);
1691 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1692 }
1693 }
1694 }
1695
1696 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1697 {
1698 struct b43_phy_n *nphy = dev->phy.n;
1699 u8 i;
1700 u16 reg, val;
1701
1702 if (code == 0) {
1703 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1704 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1705 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1706 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1707 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1708 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1709 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1710 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1711 } else {
1712 for (i = 0; i < 2; i++) {
1713 if ((code == 1 && i == 1) || (code == 2 && !i))
1714 continue;
1715
1716 reg = (i == 0) ?
1717 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1718 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1719
1720 if (type < 3) {
1721 reg = (i == 0) ?
1722 B43_NPHY_AFECTL_C1 :
1723 B43_NPHY_AFECTL_C2;
1724 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1725
1726 reg = (i == 0) ?
1727 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1728 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1729 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1730
1731 if (type == 0)
1732 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1733 else if (type == 1)
1734 val = 16;
1735 else
1736 val = 32;
1737 b43_phy_set(dev, reg, val);
1738
1739 reg = (i == 0) ?
1740 B43_NPHY_TXF_40CO_B1S0 :
1741 B43_NPHY_TXF_40CO_B32S1;
1742 b43_phy_set(dev, reg, 0x0020);
1743 } else {
1744 if (type == 6)
1745 val = 0x0100;
1746 else if (type == 3)
1747 val = 0x0200;
1748 else
1749 val = 0x0300;
1750
1751 reg = (i == 0) ?
1752 B43_NPHY_AFECTL_C1 :
1753 B43_NPHY_AFECTL_C2;
1754
1755 b43_phy_maskset(dev, reg, 0xFCFF, val);
1756 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1757
1758 if (type != 3 && type != 6) {
1759 enum ieee80211_band band =
1760 b43_current_band(dev->wl);
1761
1762 if ((nphy->ipa2g_on &&
1763 band == IEEE80211_BAND_2GHZ) ||
1764 (nphy->ipa5g_on &&
1765 band == IEEE80211_BAND_5GHZ))
1766 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1767 else
1768 val = 0x11;
1769 reg = (i == 0) ? 0x2000 : 0x3000;
1770 reg |= B2055_PADDRV;
1771 b43_radio_write16(dev, reg, val);
1772
1773 reg = (i == 0) ?
1774 B43_NPHY_AFECTL_OVER1 :
1775 B43_NPHY_AFECTL_OVER;
1776 b43_phy_set(dev, reg, 0x0200);
1777 }
1778 }
1779 }
1780 }
1781 }
1782
1783 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1784 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1785 {
1786 if (dev->phy.rev >= 3)
1787 b43_nphy_rev3_rssi_select(dev, code, type);
1788 else
1789 b43_nphy_rev2_rssi_select(dev, code, type);
1790 }
1791
1792 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1793 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1794 {
1795 int i;
1796 for (i = 0; i < 2; i++) {
1797 if (type == 2) {
1798 if (i == 0) {
1799 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1800 0xFC, buf[0]);
1801 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1802 0xFC, buf[1]);
1803 } else {
1804 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1805 0xFC, buf[2 * i]);
1806 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1807 0xFC, buf[2 * i + 1]);
1808 }
1809 } else {
1810 if (i == 0)
1811 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1812 0xF3, buf[0] << 2);
1813 else
1814 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1815 0xF3, buf[2 * i + 1] << 2);
1816 }
1817 }
1818 }
1819
1820 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1821 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1822 u8 nsamp)
1823 {
1824 int i;
1825 int out;
1826 u16 save_regs_phy[9];
1827 u16 s[2];
1828
1829 if (dev->phy.rev >= 3) {
1830 save_regs_phy[0] = b43_phy_read(dev,
1831 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1832 save_regs_phy[1] = b43_phy_read(dev,
1833 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1834 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1835 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1836 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1837 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1838 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1839 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1840 }
1841
1842 b43_nphy_rssi_select(dev, 5, type);
1843
1844 if (dev->phy.rev < 2) {
1845 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1846 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1847 }
1848
1849 for (i = 0; i < 4; i++)
1850 buf[i] = 0;
1851
1852 for (i = 0; i < nsamp; i++) {
1853 if (dev->phy.rev < 2) {
1854 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1855 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1856 } else {
1857 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1858 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1859 }
1860
1861 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1862 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1863 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1864 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1865 }
1866 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1867 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1868
1869 if (dev->phy.rev < 2)
1870 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1871
1872 if (dev->phy.rev >= 3) {
1873 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1874 save_regs_phy[0]);
1875 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1876 save_regs_phy[1]);
1877 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1878 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1879 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1880 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1881 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1882 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1883 }
1884
1885 return out;
1886 }
1887
1888 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1889 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1890 {
1891 int i, j;
1892 u8 state[4];
1893 u8 code, val;
1894 u16 class, override;
1895 u8 regs_save_radio[2];
1896 u16 regs_save_phy[2];
1897 s8 offset[4];
1898
1899 u16 clip_state[2];
1900 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1901 s32 results_min[4] = { };
1902 u8 vcm_final[4] = { };
1903 s32 results[4][4] = { };
1904 s32 miniq[4][2] = { };
1905
1906 if (type == 2) {
1907 code = 0;
1908 val = 6;
1909 } else if (type < 2) {
1910 code = 25;
1911 val = 4;
1912 } else {
1913 B43_WARN_ON(1);
1914 return;
1915 }
1916
1917 class = b43_nphy_classifier(dev, 0, 0);
1918 b43_nphy_classifier(dev, 7, 4);
1919 b43_nphy_read_clip_detection(dev, clip_state);
1920 b43_nphy_write_clip_detection(dev, clip_off);
1921
1922 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1923 override = 0x140;
1924 else
1925 override = 0x110;
1926
1927 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1928 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1929 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1930 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1931
1932 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1933 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1934 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1935 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1936
1937 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1938 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1939 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1940 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1941 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1942 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1943
1944 b43_nphy_rssi_select(dev, 5, type);
1945 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1946 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1947
1948 for (i = 0; i < 4; i++) {
1949 u8 tmp[4];
1950 for (j = 0; j < 4; j++)
1951 tmp[j] = i;
1952 if (type != 1)
1953 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1954 b43_nphy_poll_rssi(dev, type, results[i], 8);
1955 if (type < 2)
1956 for (j = 0; j < 2; j++)
1957 miniq[i][j] = min(results[i][2 * j],
1958 results[i][2 * j + 1]);
1959 }
1960
1961 for (i = 0; i < 4; i++) {
1962 s32 mind = 40;
1963 u8 minvcm = 0;
1964 s32 minpoll = 249;
1965 s32 curr;
1966 for (j = 0; j < 4; j++) {
1967 if (type == 2)
1968 curr = abs(results[j][i]);
1969 else
1970 curr = abs(miniq[j][i / 2] - code * 8);
1971
1972 if (curr < mind) {
1973 mind = curr;
1974 minvcm = j;
1975 }
1976
1977 if (results[j][i] < minpoll)
1978 minpoll = results[j][i];
1979 }
1980 results_min[i] = minpoll;
1981 vcm_final[i] = minvcm;
1982 }
1983
1984 if (type != 1)
1985 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1986
1987 for (i = 0; i < 4; i++) {
1988 offset[i] = (code * 8) - results[vcm_final[i]][i];
1989
1990 if (offset[i] < 0)
1991 offset[i] = -((abs(offset[i]) + 4) / 8);
1992 else
1993 offset[i] = (offset[i] + 4) / 8;
1994
1995 if (results_min[i] == 248)
1996 offset[i] = code - 32;
1997
1998 if (i % 2 == 0)
1999 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
2000 type);
2001 else
2002 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
2003 type);
2004 }
2005
2006 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
2007 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
2008
2009 switch (state[2]) {
2010 case 1:
2011 b43_nphy_rssi_select(dev, 1, 2);
2012 break;
2013 case 4:
2014 b43_nphy_rssi_select(dev, 1, 0);
2015 break;
2016 case 2:
2017 b43_nphy_rssi_select(dev, 1, 1);
2018 break;
2019 default:
2020 b43_nphy_rssi_select(dev, 1, 1);
2021 break;
2022 }
2023
2024 switch (state[3]) {
2025 case 1:
2026 b43_nphy_rssi_select(dev, 2, 2);
2027 break;
2028 case 4:
2029 b43_nphy_rssi_select(dev, 2, 0);
2030 break;
2031 default:
2032 b43_nphy_rssi_select(dev, 2, 1);
2033 break;
2034 }
2035
2036 b43_nphy_rssi_select(dev, 0, type);
2037
2038 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2039 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2040 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2041 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2042
2043 b43_nphy_classifier(dev, 7, class);
2044 b43_nphy_write_clip_detection(dev, clip_state);
2045 }
2046
2047 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2048 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2049 {
2050 /* TODO */
2051 }
2052
2053 /*
2054 * RSSI Calibration
2055 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2056 */
2057 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2058 {
2059 if (dev->phy.rev >= 3) {
2060 b43_nphy_rev3_rssi_cal(dev);
2061 } else {
2062 b43_nphy_rev2_rssi_cal(dev, 2);
2063 b43_nphy_rev2_rssi_cal(dev, 0);
2064 b43_nphy_rev2_rssi_cal(dev, 1);
2065 }
2066 }
2067
2068 /*
2069 * Restore RSSI Calibration
2070 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2071 */
2072 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2073 {
2074 struct b43_phy_n *nphy = dev->phy.n;
2075
2076 u16 *rssical_radio_regs = NULL;
2077 u16 *rssical_phy_regs = NULL;
2078
2079 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2080 if (!nphy->rssical_chanspec_2G.center_freq)
2081 return;
2082 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2083 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2084 } else {
2085 if (!nphy->rssical_chanspec_5G.center_freq)
2086 return;
2087 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2088 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2089 }
2090
2091 /* TODO use some definitions */
2092 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2093 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2094
2095 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2096 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2097 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2098 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2099
2100 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2101 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2102 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2103 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2104
2105 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2106 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2107 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2108 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2109 }
2110
2111 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2112 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2113 {
2114 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2115 if (dev->phy.rev >= 6) {
2116 /* TODO If the chip is 47162
2117 return txpwrctrl_tx_gain_ipa_rev5 */
2118 return txpwrctrl_tx_gain_ipa_rev6;
2119 } else if (dev->phy.rev >= 5) {
2120 return txpwrctrl_tx_gain_ipa_rev5;
2121 } else {
2122 return txpwrctrl_tx_gain_ipa;
2123 }
2124 } else {
2125 return txpwrctrl_tx_gain_ipa_5g;
2126 }
2127 }
2128
2129 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2130 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2131 {
2132 struct b43_phy_n *nphy = dev->phy.n;
2133 u16 *save = nphy->tx_rx_cal_radio_saveregs;
2134 u16 tmp;
2135 u8 offset, i;
2136
2137 if (dev->phy.rev >= 3) {
2138 for (i = 0; i < 2; i++) {
2139 tmp = (i == 0) ? 0x2000 : 0x3000;
2140 offset = i * 11;
2141
2142 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2143 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2144 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2145 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2146 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2147 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2148 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2149 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2150 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2151 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2152 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2153
2154 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2155 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2156 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2157 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2158 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2159 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2160 if (nphy->ipa5g_on) {
2161 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2162 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2163 } else {
2164 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2165 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2166 }
2167 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2168 } else {
2169 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2170 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2171 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2172 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2173 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2174 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2175 if (nphy->ipa2g_on) {
2176 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2177 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2178 (dev->phy.rev < 5) ? 0x11 : 0x01);
2179 } else {
2180 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2181 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2182 }
2183 }
2184 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2185 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2186 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2187 }
2188 } else {
2189 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2190 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2191
2192 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2193 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2194
2195 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2196 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2197
2198 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2199 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2200
2201 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2202 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2203
2204 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2205 B43_NPHY_BANDCTL_5GHZ)) {
2206 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2207 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2208 } else {
2209 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2210 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2211 }
2212
2213 if (dev->phy.rev < 2) {
2214 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2215 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2216 } else {
2217 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2218 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2219 }
2220 }
2221 }
2222
2223 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2224 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2225 struct nphy_txgains target,
2226 struct nphy_iqcal_params *params)
2227 {
2228 int i, j, indx;
2229 u16 gain;
2230
2231 if (dev->phy.rev >= 3) {
2232 params->txgm = target.txgm[core];
2233 params->pga = target.pga[core];
2234 params->pad = target.pad[core];
2235 params->ipa = target.ipa[core];
2236 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2237 (params->pad << 4) | (params->ipa);
2238 for (j = 0; j < 5; j++)
2239 params->ncorr[j] = 0x79;
2240 } else {
2241 gain = (target.pad[core]) | (target.pga[core] << 4) |
2242 (target.txgm[core] << 8);
2243
2244 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2245 1 : 0;
2246 for (i = 0; i < 9; i++)
2247 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2248 break;
2249 i = min(i, 8);
2250
2251 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2252 params->pga = tbl_iqcal_gainparams[indx][i][2];
2253 params->pad = tbl_iqcal_gainparams[indx][i][3];
2254 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2255 (params->pad << 2);
2256 for (j = 0; j < 4; j++)
2257 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2258 }
2259 }
2260
2261 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2262 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2263 {
2264 struct b43_phy_n *nphy = dev->phy.n;
2265 int i;
2266 u16 scale, entry;
2267
2268 u16 tmp = nphy->txcal_bbmult;
2269 if (core == 0)
2270 tmp >>= 8;
2271 tmp &= 0xff;
2272
2273 for (i = 0; i < 18; i++) {
2274 scale = (ladder_lo[i].percent * tmp) / 100;
2275 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2276 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2277
2278 scale = (ladder_iq[i].percent * tmp) / 100;
2279 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2280 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2281 }
2282 }
2283
2284 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2285 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2286 {
2287 int i;
2288 for (i = 0; i < 15; i++)
2289 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2290 tbl_tx_filter_coef_rev4[2][i]);
2291 }
2292
2293 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2294 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2295 {
2296 int i, j;
2297 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2298 u16 offset[] = { 0x186, 0x195, 0x2C5 };
2299
2300 for (i = 0; i < 3; i++)
2301 for (j = 0; j < 15; j++)
2302 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2303 tbl_tx_filter_coef_rev4[i][j]);
2304
2305 if (dev->phy.is_40mhz) {
2306 for (j = 0; j < 15; j++)
2307 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2308 tbl_tx_filter_coef_rev4[3][j]);
2309 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2310 for (j = 0; j < 15; j++)
2311 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2312 tbl_tx_filter_coef_rev4[5][j]);
2313 }
2314
2315 if (dev->phy.channel == 14)
2316 for (j = 0; j < 15; j++)
2317 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2318 tbl_tx_filter_coef_rev4[6][j]);
2319 }
2320
2321 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2322 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2323 {
2324 struct b43_phy_n *nphy = dev->phy.n;
2325
2326 u16 curr_gain[2];
2327 struct nphy_txgains target;
2328 const u32 *table = NULL;
2329
2330 if (nphy->txpwrctrl == 0) {
2331 int i;
2332
2333 if (nphy->hang_avoid)
2334 b43_nphy_stay_in_carrier_search(dev, true);
2335 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2336 if (nphy->hang_avoid)
2337 b43_nphy_stay_in_carrier_search(dev, false);
2338
2339 for (i = 0; i < 2; ++i) {
2340 if (dev->phy.rev >= 3) {
2341 target.ipa[i] = curr_gain[i] & 0x000F;
2342 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2343 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2344 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2345 } else {
2346 target.ipa[i] = curr_gain[i] & 0x0003;
2347 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2348 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2349 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2350 }
2351 }
2352 } else {
2353 int i;
2354 u16 index[2];
2355 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2356 B43_NPHY_TXPCTL_STAT_BIDX) >>
2357 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2358 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2359 B43_NPHY_TXPCTL_STAT_BIDX) >>
2360 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2361
2362 for (i = 0; i < 2; ++i) {
2363 if (dev->phy.rev >= 3) {
2364 enum ieee80211_band band =
2365 b43_current_band(dev->wl);
2366
2367 if ((nphy->ipa2g_on &&
2368 band == IEEE80211_BAND_2GHZ) ||
2369 (nphy->ipa5g_on &&
2370 band == IEEE80211_BAND_5GHZ)) {
2371 table = b43_nphy_get_ipa_gain_table(dev);
2372 } else {
2373 if (band == IEEE80211_BAND_5GHZ) {
2374 if (dev->phy.rev == 3)
2375 table = b43_ntab_tx_gain_rev3_5ghz;
2376 else if (dev->phy.rev == 4)
2377 table = b43_ntab_tx_gain_rev4_5ghz;
2378 else
2379 table = b43_ntab_tx_gain_rev5plus_5ghz;
2380 } else {
2381 table = b43_ntab_tx_gain_rev3plus_2ghz;
2382 }
2383 }
2384
2385 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2386 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2387 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2388 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2389 } else {
2390 table = b43_ntab_tx_gain_rev0_1_2;
2391
2392 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2393 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2394 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2395 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2396 }
2397 }
2398 }
2399
2400 return target;
2401 }
2402
2403 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2404 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2405 {
2406 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2407
2408 if (dev->phy.rev >= 3) {
2409 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2410 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2411 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2412 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2413 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2414 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2415 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2416 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2417 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2418 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2419 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2420 b43_nphy_reset_cca(dev);
2421 } else {
2422 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2423 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2424 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2425 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2426 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2427 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2428 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2429 }
2430 }
2431
2432 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2433 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2434 {
2435 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2436 u16 tmp;
2437
2438 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2439 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2440 if (dev->phy.rev >= 3) {
2441 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2442 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2443
2444 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2445 regs[2] = tmp;
2446 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2447
2448 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2449 regs[3] = tmp;
2450 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2451
2452 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2453 b43_phy_mask(dev, B43_NPHY_BBCFG,
2454 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
2455
2456 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2457 regs[5] = tmp;
2458 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2459
2460 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2461 regs[6] = tmp;
2462 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2463 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2464 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2465
2466 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2467 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2468 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2469
2470 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2471 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2472 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2473 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2474 } else {
2475 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2476 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2477 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2478 regs[2] = tmp;
2479 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2480 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2481 regs[3] = tmp;
2482 tmp |= 0x2000;
2483 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2484 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2485 regs[4] = tmp;
2486 tmp |= 0x2000;
2487 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2488 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2489 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2490 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2491 tmp = 0x0180;
2492 else
2493 tmp = 0x0120;
2494 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2495 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2496 }
2497 }
2498
2499 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2500 static void b43_nphy_save_cal(struct b43_wldev *dev)
2501 {
2502 struct b43_phy_n *nphy = dev->phy.n;
2503
2504 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2505 u16 *txcal_radio_regs = NULL;
2506 struct b43_chanspec *iqcal_chanspec;
2507 u16 *table = NULL;
2508
2509 if (nphy->hang_avoid)
2510 b43_nphy_stay_in_carrier_search(dev, 1);
2511
2512 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2513 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2514 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2515 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2516 table = nphy->cal_cache.txcal_coeffs_2G;
2517 } else {
2518 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2519 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2520 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2521 table = nphy->cal_cache.txcal_coeffs_5G;
2522 }
2523
2524 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2525 /* TODO use some definitions */
2526 if (dev->phy.rev >= 3) {
2527 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2528 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2529 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2530 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2531 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2532 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2533 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2534 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2535 } else {
2536 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2537 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2538 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2539 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2540 }
2541 iqcal_chanspec->center_freq = dev->phy.channel_freq;
2542 iqcal_chanspec->channel_type = dev->phy.channel_type;
2543 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
2544
2545 if (nphy->hang_avoid)
2546 b43_nphy_stay_in_carrier_search(dev, 0);
2547 }
2548
2549 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2550 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2551 {
2552 struct b43_phy_n *nphy = dev->phy.n;
2553
2554 u16 coef[4];
2555 u16 *loft = NULL;
2556 u16 *table = NULL;
2557
2558 int i;
2559 u16 *txcal_radio_regs = NULL;
2560 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2561
2562 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2563 if (!nphy->iqcal_chanspec_2G.center_freq)
2564 return;
2565 table = nphy->cal_cache.txcal_coeffs_2G;
2566 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2567 } else {
2568 if (!nphy->iqcal_chanspec_5G.center_freq)
2569 return;
2570 table = nphy->cal_cache.txcal_coeffs_5G;
2571 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2572 }
2573
2574 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2575
2576 for (i = 0; i < 4; i++) {
2577 if (dev->phy.rev >= 3)
2578 table[i] = coef[i];
2579 else
2580 coef[i] = 0;
2581 }
2582
2583 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2584 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2585 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2586
2587 if (dev->phy.rev < 2)
2588 b43_nphy_tx_iq_workaround(dev);
2589
2590 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2591 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2592 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2593 } else {
2594 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2595 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2596 }
2597
2598 /* TODO use some definitions */
2599 if (dev->phy.rev >= 3) {
2600 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2601 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2602 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2603 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2604 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2605 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2606 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2607 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2608 } else {
2609 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2610 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2611 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2612 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2613 }
2614 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2615 }
2616
2617 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2618 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2619 struct nphy_txgains target,
2620 bool full, bool mphase)
2621 {
2622 struct b43_phy_n *nphy = dev->phy.n;
2623 int i;
2624 int error = 0;
2625 int freq;
2626 bool avoid = false;
2627 u8 length;
2628 u16 tmp, core, type, count, max, numb, last, cmd;
2629 const u16 *table;
2630 bool phy6or5x;
2631
2632 u16 buffer[11];
2633 u16 diq_start = 0;
2634 u16 save[2];
2635 u16 gain[2];
2636 struct nphy_iqcal_params params[2];
2637 bool updated[2] = { };
2638
2639 b43_nphy_stay_in_carrier_search(dev, true);
2640
2641 if (dev->phy.rev >= 4) {
2642 avoid = nphy->hang_avoid;
2643 nphy->hang_avoid = 0;
2644 }
2645
2646 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2647
2648 for (i = 0; i < 2; i++) {
2649 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2650 gain[i] = params[i].cal_gain;
2651 }
2652
2653 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2654
2655 b43_nphy_tx_cal_radio_setup(dev);
2656 b43_nphy_tx_cal_phy_setup(dev);
2657
2658 phy6or5x = dev->phy.rev >= 6 ||
2659 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2660 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2661 if (phy6or5x) {
2662 if (dev->phy.is_40mhz) {
2663 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2664 tbl_tx_iqlo_cal_loft_ladder_40);
2665 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2666 tbl_tx_iqlo_cal_iqimb_ladder_40);
2667 } else {
2668 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2669 tbl_tx_iqlo_cal_loft_ladder_20);
2670 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2671 tbl_tx_iqlo_cal_iqimb_ladder_20);
2672 }
2673 }
2674
2675 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2676
2677 if (!dev->phy.is_40mhz)
2678 freq = 2500;
2679 else
2680 freq = 5000;
2681
2682 if (nphy->mphase_cal_phase_id > 2)
2683 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2684 0xFFFF, 0, true, false);
2685 else
2686 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2687
2688 if (error == 0) {
2689 if (nphy->mphase_cal_phase_id > 2) {
2690 table = nphy->mphase_txcal_bestcoeffs;
2691 length = 11;
2692 if (dev->phy.rev < 3)
2693 length -= 2;
2694 } else {
2695 if (!full && nphy->txiqlocal_coeffsvalid) {
2696 table = nphy->txiqlocal_bestc;
2697 length = 11;
2698 if (dev->phy.rev < 3)
2699 length -= 2;
2700 } else {
2701 full = true;
2702 if (dev->phy.rev >= 3) {
2703 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2704 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2705 } else {
2706 table = tbl_tx_iqlo_cal_startcoefs;
2707 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2708 }
2709 }
2710 }
2711
2712 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2713
2714 if (full) {
2715 if (dev->phy.rev >= 3)
2716 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2717 else
2718 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2719 } else {
2720 if (dev->phy.rev >= 3)
2721 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2722 else
2723 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2724 }
2725
2726 if (mphase) {
2727 count = nphy->mphase_txcal_cmdidx;
2728 numb = min(max,
2729 (u16)(count + nphy->mphase_txcal_numcmds));
2730 } else {
2731 count = 0;
2732 numb = max;
2733 }
2734
2735 for (; count < numb; count++) {
2736 if (full) {
2737 if (dev->phy.rev >= 3)
2738 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2739 else
2740 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2741 } else {
2742 if (dev->phy.rev >= 3)
2743 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2744 else
2745 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2746 }
2747
2748 core = (cmd & 0x3000) >> 12;
2749 type = (cmd & 0x0F00) >> 8;
2750
2751 if (phy6or5x && updated[core] == 0) {
2752 b43_nphy_update_tx_cal_ladder(dev, core);
2753 updated[core] = 1;
2754 }
2755
2756 tmp = (params[core].ncorr[type] << 8) | 0x66;
2757 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2758
2759 if (type == 1 || type == 3 || type == 4) {
2760 buffer[0] = b43_ntab_read(dev,
2761 B43_NTAB16(15, 69 + core));
2762 diq_start = buffer[0];
2763 buffer[0] = 0;
2764 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2765 0);
2766 }
2767
2768 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2769 for (i = 0; i < 2000; i++) {
2770 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2771 if (tmp & 0xC000)
2772 break;
2773 udelay(10);
2774 }
2775
2776 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2777 buffer);
2778 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2779 buffer);
2780
2781 if (type == 1 || type == 3 || type == 4)
2782 buffer[0] = diq_start;
2783 }
2784
2785 if (mphase)
2786 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2787
2788 last = (dev->phy.rev < 3) ? 6 : 7;
2789
2790 if (!mphase || nphy->mphase_cal_phase_id == last) {
2791 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2792 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2793 if (dev->phy.rev < 3) {
2794 buffer[0] = 0;
2795 buffer[1] = 0;
2796 buffer[2] = 0;
2797 buffer[3] = 0;
2798 }
2799 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2800 buffer);
2801 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
2802 buffer);
2803 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2804 buffer);
2805 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2806 buffer);
2807 length = 11;
2808 if (dev->phy.rev < 3)
2809 length -= 2;
2810 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2811 nphy->txiqlocal_bestc);
2812 nphy->txiqlocal_coeffsvalid = true;
2813 nphy->txiqlocal_chanspec.center_freq =
2814 dev->phy.channel_freq;
2815 nphy->txiqlocal_chanspec.channel_type =
2816 dev->phy.channel_type;
2817 } else {
2818 length = 11;
2819 if (dev->phy.rev < 3)
2820 length -= 2;
2821 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2822 nphy->mphase_txcal_bestcoeffs);
2823 }
2824
2825 b43_nphy_stop_playback(dev);
2826 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2827 }
2828
2829 b43_nphy_tx_cal_phy_cleanup(dev);
2830 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2831
2832 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2833 b43_nphy_tx_iq_workaround(dev);
2834
2835 if (dev->phy.rev >= 4)
2836 nphy->hang_avoid = avoid;
2837
2838 b43_nphy_stay_in_carrier_search(dev, false);
2839
2840 return error;
2841 }
2842
2843 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2844 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2845 {
2846 struct b43_phy_n *nphy = dev->phy.n;
2847 u8 i;
2848 u16 buffer[7];
2849 bool equal = true;
2850
2851 if (!nphy->txiqlocal_coeffsvalid ||
2852 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
2853 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
2854 return;
2855
2856 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2857 for (i = 0; i < 4; i++) {
2858 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2859 equal = false;
2860 break;
2861 }
2862 }
2863
2864 if (!equal) {
2865 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2866 nphy->txiqlocal_bestc);
2867 for (i = 0; i < 4; i++)
2868 buffer[i] = 0;
2869 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2870 buffer);
2871 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2872 &nphy->txiqlocal_bestc[5]);
2873 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2874 &nphy->txiqlocal_bestc[5]);
2875 }
2876 }
2877
2878 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2879 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2880 struct nphy_txgains target, u8 type, bool debug)
2881 {
2882 struct b43_phy_n *nphy = dev->phy.n;
2883 int i, j, index;
2884 u8 rfctl[2];
2885 u8 afectl_core;
2886 u16 tmp[6];
2887 u16 cur_hpf1, cur_hpf2, cur_lna;
2888 u32 real, imag;
2889 enum ieee80211_band band;
2890
2891 u8 use;
2892 u16 cur_hpf;
2893 u16 lna[3] = { 3, 3, 1 };
2894 u16 hpf1[3] = { 7, 2, 0 };
2895 u16 hpf2[3] = { 2, 0, 0 };
2896 u32 power[3] = { };
2897 u16 gain_save[2];
2898 u16 cal_gain[2];
2899 struct nphy_iqcal_params cal_params[2];
2900 struct nphy_iq_est est;
2901 int ret = 0;
2902 bool playtone = true;
2903 int desired = 13;
2904
2905 b43_nphy_stay_in_carrier_search(dev, 1);
2906
2907 if (dev->phy.rev < 2)
2908 b43_nphy_reapply_tx_cal_coeffs(dev);
2909 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2910 for (i = 0; i < 2; i++) {
2911 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2912 cal_gain[i] = cal_params[i].cal_gain;
2913 }
2914 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2915
2916 for (i = 0; i < 2; i++) {
2917 if (i == 0) {
2918 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2919 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2920 afectl_core = B43_NPHY_AFECTL_C1;
2921 } else {
2922 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2923 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2924 afectl_core = B43_NPHY_AFECTL_C2;
2925 }
2926
2927 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2928 tmp[2] = b43_phy_read(dev, afectl_core);
2929 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2930 tmp[4] = b43_phy_read(dev, rfctl[0]);
2931 tmp[5] = b43_phy_read(dev, rfctl[1]);
2932
2933 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2934 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
2935 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2936 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2937 (1 - i));
2938 b43_phy_set(dev, afectl_core, 0x0006);
2939 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2940
2941 band = b43_current_band(dev->wl);
2942
2943 if (nphy->rxcalparams & 0xFF000000) {
2944 if (band == IEEE80211_BAND_5GHZ)
2945 b43_phy_write(dev, rfctl[0], 0x140);
2946 else
2947 b43_phy_write(dev, rfctl[0], 0x110);
2948 } else {
2949 if (band == IEEE80211_BAND_5GHZ)
2950 b43_phy_write(dev, rfctl[0], 0x180);
2951 else
2952 b43_phy_write(dev, rfctl[0], 0x120);
2953 }
2954
2955 if (band == IEEE80211_BAND_5GHZ)
2956 b43_phy_write(dev, rfctl[1], 0x148);
2957 else
2958 b43_phy_write(dev, rfctl[1], 0x114);
2959
2960 if (nphy->rxcalparams & 0x10000) {
2961 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2962 (i + 1));
2963 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2964 (2 - i));
2965 }
2966
2967 for (j = 0; i < 4; j++) {
2968 if (j < 3) {
2969 cur_lna = lna[j];
2970 cur_hpf1 = hpf1[j];
2971 cur_hpf2 = hpf2[j];
2972 } else {
2973 if (power[1] > 10000) {
2974 use = 1;
2975 cur_hpf = cur_hpf1;
2976 index = 2;
2977 } else {
2978 if (power[0] > 10000) {
2979 use = 1;
2980 cur_hpf = cur_hpf1;
2981 index = 1;
2982 } else {
2983 index = 0;
2984 use = 2;
2985 cur_hpf = cur_hpf2;
2986 }
2987 }
2988 cur_lna = lna[index];
2989 cur_hpf1 = hpf1[index];
2990 cur_hpf2 = hpf2[index];
2991 cur_hpf += desired - hweight32(power[index]);
2992 cur_hpf = clamp_val(cur_hpf, 0, 10);
2993 if (use == 1)
2994 cur_hpf1 = cur_hpf;
2995 else
2996 cur_hpf2 = cur_hpf;
2997 }
2998
2999 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3000 (cur_lna << 2));
3001 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3002 false);
3003 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3004 b43_nphy_stop_playback(dev);
3005
3006 if (playtone) {
3007 ret = b43_nphy_tx_tone(dev, 4000,
3008 (nphy->rxcalparams & 0xFFFF),
3009 false, false);
3010 playtone = false;
3011 } else {
3012 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3013 false, false);
3014 }
3015
3016 if (ret == 0) {
3017 if (j < 3) {
3018 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3019 false);
3020 if (i == 0) {
3021 real = est.i0_pwr;
3022 imag = est.q0_pwr;
3023 } else {
3024 real = est.i1_pwr;
3025 imag = est.q1_pwr;
3026 }
3027 power[i] = ((real + imag) / 1024) + 1;
3028 } else {
3029 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3030 }
3031 b43_nphy_stop_playback(dev);
3032 }
3033
3034 if (ret != 0)
3035 break;
3036 }
3037
3038 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3039 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3040 b43_phy_write(dev, rfctl[1], tmp[5]);
3041 b43_phy_write(dev, rfctl[0], tmp[4]);
3042 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3043 b43_phy_write(dev, afectl_core, tmp[2]);
3044 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3045
3046 if (ret != 0)
3047 break;
3048 }
3049
3050 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
3051 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3052 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
3053
3054 b43_nphy_stay_in_carrier_search(dev, 0);
3055
3056 return ret;
3057 }
3058
3059 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3060 struct nphy_txgains target, u8 type, bool debug)
3061 {
3062 return -1;
3063 }
3064
3065 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3066 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3067 struct nphy_txgains target, u8 type, bool debug)
3068 {
3069 if (dev->phy.rev >= 3)
3070 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3071 else
3072 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3073 }
3074
3075 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3076 static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3077 {
3078 u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
3079 if (on)
3080 tmslow |= SSB_TMSLOW_PHYCLK;
3081 else
3082 tmslow &= ~SSB_TMSLOW_PHYCLK;
3083 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
3084 }
3085
3086 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3087 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3088 {
3089 struct b43_phy *phy = &dev->phy;
3090 struct b43_phy_n *nphy = phy->n;
3091 u16 buf[16];
3092
3093 nphy->phyrxchain = mask;
3094
3095 if (0 /* FIXME clk */)
3096 return;
3097
3098 b43_mac_suspend(dev);
3099
3100 if (nphy->hang_avoid)
3101 b43_nphy_stay_in_carrier_search(dev, true);
3102
3103 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3104 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3105
3106 if ((mask & 0x3) != 0x3) {
3107 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3108 if (dev->phy.rev >= 3) {
3109 /* TODO */
3110 }
3111 } else {
3112 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3113 if (dev->phy.rev >= 3) {
3114 /* TODO */
3115 }
3116 }
3117
3118 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3119
3120 if (nphy->hang_avoid)
3121 b43_nphy_stay_in_carrier_search(dev, false);
3122
3123 b43_mac_enable(dev);
3124 }
3125
3126 /*
3127 * Init N-PHY
3128 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3129 */
3130 int b43_phy_initn(struct b43_wldev *dev)
3131 {
3132 struct ssb_bus *bus = dev->dev->bus;
3133 struct b43_phy *phy = &dev->phy;
3134 struct b43_phy_n *nphy = phy->n;
3135 u8 tx_pwr_state;
3136 struct nphy_txgains target;
3137 u16 tmp;
3138 enum ieee80211_band tmp2;
3139 bool do_rssi_cal;
3140
3141 u16 clip[2];
3142 bool do_cal = false;
3143
3144 if ((dev->phy.rev >= 3) &&
3145 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3146 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3147 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3148 }
3149 nphy->deaf_count = 0;
3150 b43_nphy_tables_init(dev);
3151 nphy->crsminpwr_adjusted = false;
3152 nphy->noisevars_adjusted = false;
3153
3154 /* Clear all overrides */
3155 if (dev->phy.rev >= 3) {
3156 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3157 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3158 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3159 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3160 } else {
3161 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3162 }
3163 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3164 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
3165 if (dev->phy.rev < 6) {
3166 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3167 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3168 }
3169 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3170 ~(B43_NPHY_RFSEQMODE_CAOVER |
3171 B43_NPHY_RFSEQMODE_TROVER));
3172 if (dev->phy.rev >= 3)
3173 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
3174 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3175
3176 if (dev->phy.rev <= 2) {
3177 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3178 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3179 ~B43_NPHY_BPHY_CTL3_SCALE,
3180 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3181 }
3182 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3183 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3184
3185 if (bus->sprom.boardflags2_lo & 0x100 ||
3186 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3187 bus->boardinfo.type == 0x8B))
3188 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3189 else
3190 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3191 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3192 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3193 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
3194
3195 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
3196 b43_nphy_update_txrx_chain(dev);
3197
3198 if (phy->rev < 2) {
3199 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3200 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3201 }
3202
3203 tmp2 = b43_current_band(dev->wl);
3204 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3205 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3206 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3207 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3208 nphy->papd_epsilon_offset[0] << 7);
3209 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3210 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3211 nphy->papd_epsilon_offset[1] << 7);
3212 b43_nphy_int_pa_set_tx_dig_filters(dev);
3213 } else if (phy->rev >= 5) {
3214 b43_nphy_ext_pa_set_tx_dig_filters(dev);
3215 }
3216
3217 b43_nphy_workarounds(dev);
3218
3219 /* Reset CCA, in init code it differs a little from standard way */
3220 b43_nphy_bmac_clock_fgc(dev, 1);
3221 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3222 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3223 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
3224 b43_nphy_bmac_clock_fgc(dev, 0);
3225
3226 b43_nphy_mac_phy_clock_set(dev, true);
3227
3228 b43_nphy_pa_override(dev, false);
3229 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3230 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3231 b43_nphy_pa_override(dev, true);
3232
3233 b43_nphy_classifier(dev, 0, 0);
3234 b43_nphy_read_clip_detection(dev, clip);
3235 tx_pwr_state = nphy->txpwrctrl;
3236 /* TODO N PHY TX power control with argument 0
3237 (turning off power control) */
3238 /* TODO Fix the TX Power Settings */
3239 /* TODO N PHY TX Power Control Idle TSSI */
3240 /* TODO N PHY TX Power Control Setup */
3241
3242 if (phy->rev >= 3) {
3243 /* TODO */
3244 } else {
3245 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3246 b43_ntab_tx_gain_rev0_1_2);
3247 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3248 b43_ntab_tx_gain_rev0_1_2);
3249 }
3250
3251 if (nphy->phyrxchain != 3)
3252 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
3253 if (nphy->mphase_cal_phase_id > 0)
3254 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3255
3256 do_rssi_cal = false;
3257 if (phy->rev >= 3) {
3258 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3259 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
3260 else
3261 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
3262
3263 if (do_rssi_cal)
3264 b43_nphy_rssi_cal(dev);
3265 else
3266 b43_nphy_restore_rssi_cal(dev);
3267 } else {
3268 b43_nphy_rssi_cal(dev);
3269 }
3270
3271 if (!((nphy->measure_hold & 0x6) != 0)) {
3272 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3273 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
3274 else
3275 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
3276
3277 if (nphy->mute)
3278 do_cal = false;
3279
3280 if (do_cal) {
3281 target = b43_nphy_get_tx_gains(dev);
3282
3283 if (nphy->antsel_type == 2)
3284 b43_nphy_superswitch_init(dev, true);
3285 if (nphy->perical != 2) {
3286 b43_nphy_rssi_cal(dev);
3287 if (phy->rev >= 3) {
3288 nphy->cal_orig_pwr_idx[0] =
3289 nphy->txpwrindex[0].index_internal;
3290 nphy->cal_orig_pwr_idx[1] =
3291 nphy->txpwrindex[1].index_internal;
3292 /* TODO N PHY Pre Calibrate TX Gain */
3293 target = b43_nphy_get_tx_gains(dev);
3294 }
3295 }
3296 }
3297 }
3298
3299 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3300 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3301 b43_nphy_save_cal(dev);
3302 else if (nphy->mphase_cal_phase_id == 0)
3303 ;/* N PHY Periodic Calibration with argument 3 */
3304 } else {
3305 b43_nphy_restore_cal(dev);
3306 }
3307
3308 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3309 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3310 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3311 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3312 if (phy->rev >= 3 && phy->rev <= 6)
3313 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3314 b43_nphy_tx_lp_fbw(dev);
3315 if (phy->rev >= 3)
3316 b43_nphy_spur_workaround(dev);
3317
3318 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3319 return 0;
3320 }
3321
3322 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
3323 static void b43_nphy_channel_setup(struct b43_wldev *dev,
3324 const struct b43_phy_n_sfo_cfg *e,
3325 struct ieee80211_channel *new_channel)
3326 {
3327 struct b43_phy *phy = &dev->phy;
3328 struct b43_phy_n *nphy = dev->phy.n;
3329
3330 u16 old_band_5ghz;
3331 u32 tmp32;
3332
3333 old_band_5ghz =
3334 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3335 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
3336 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3337 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3338 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3339 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3340 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
3341 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
3342 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3343 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3344 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3345 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
3346 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3347 }
3348
3349 b43_chantab_phy_upload(dev, e);
3350
3351 if (new_channel->hw_value == 14) {
3352 b43_nphy_classifier(dev, 2, 0);
3353 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3354 } else {
3355 b43_nphy_classifier(dev, 2, 2);
3356 if (new_channel->band == IEEE80211_BAND_2GHZ)
3357 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3358 }
3359
3360 if (nphy->txpwrctrl)
3361 b43_nphy_tx_power_fix(dev);
3362
3363 if (dev->phy.rev < 3)
3364 b43_nphy_adjust_lna_gain_table(dev);
3365
3366 b43_nphy_tx_lp_fbw(dev);
3367
3368 if (dev->phy.rev >= 3 && 0) {
3369 /* TODO */
3370 }
3371
3372 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3373
3374 if (phy->rev >= 3)
3375 b43_nphy_spur_workaround(dev);
3376 }
3377
3378 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
3379 static int b43_nphy_set_channel(struct b43_wldev *dev,
3380 struct ieee80211_channel *channel,
3381 enum nl80211_channel_type channel_type)
3382 {
3383 struct b43_phy *phy = &dev->phy;
3384 struct b43_phy_n *nphy = dev->phy.n;
3385
3386 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3387 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
3388
3389 u8 tmp;
3390
3391 if (dev->phy.rev >= 3) {
3392 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3393 channel->center_freq);
3394 tabent_r3 = NULL;
3395 if (!tabent_r3)
3396 return -ESRCH;
3397 } else {
3398 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3399 channel->hw_value);
3400 if (!tabent_r2)
3401 return -ESRCH;
3402 }
3403
3404 /* Channel is set later in common code, but we need to set it on our
3405 own to let this function's subcalls work properly. */
3406 phy->channel = channel->hw_value;
3407 phy->channel_freq = channel->center_freq;
3408
3409 if (b43_channel_type_is_40mhz(phy->channel_type) !=
3410 b43_channel_type_is_40mhz(channel_type))
3411 ; /* TODO: BMAC BW Set (channel_type) */
3412
3413 if (channel_type == NL80211_CHAN_HT40PLUS)
3414 b43_phy_set(dev, B43_NPHY_RXCTL,
3415 B43_NPHY_RXCTL_BSELU20);
3416 else if (channel_type == NL80211_CHAN_HT40MINUS)
3417 b43_phy_mask(dev, B43_NPHY_RXCTL,
3418 ~B43_NPHY_RXCTL_BSELU20);
3419
3420 if (dev->phy.rev >= 3) {
3421 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
3422 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
3423 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
3424 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
3425 } else {
3426 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
3427 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
3428 b43_radio_2055_setup(dev, tabent_r2);
3429 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
3430 }
3431
3432 return 0;
3433 }
3434
3435 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3436 {
3437 struct b43_phy_n *nphy;
3438
3439 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3440 if (!nphy)
3441 return -ENOMEM;
3442 dev->phy.n = nphy;
3443
3444 return 0;
3445 }
3446
3447 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3448 {
3449 struct b43_phy *phy = &dev->phy;
3450 struct b43_phy_n *nphy = phy->n;
3451
3452 memset(nphy, 0, sizeof(*nphy));
3453
3454 //TODO init struct b43_phy_n
3455 }
3456
3457 static void b43_nphy_op_free(struct b43_wldev *dev)
3458 {
3459 struct b43_phy *phy = &dev->phy;
3460 struct b43_phy_n *nphy = phy->n;
3461
3462 kfree(nphy);
3463 phy->n = NULL;
3464 }
3465
3466 static int b43_nphy_op_init(struct b43_wldev *dev)
3467 {
3468 return b43_phy_initn(dev);
3469 }
3470
3471 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3472 {
3473 #if B43_DEBUG
3474 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3475 /* OFDM registers are onnly available on A/G-PHYs */
3476 b43err(dev->wl, "Invalid OFDM PHY access at "
3477 "0x%04X on N-PHY\n", offset);
3478 dump_stack();
3479 }
3480 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3481 /* Ext-G registers are only available on G-PHYs */
3482 b43err(dev->wl, "Invalid EXT-G PHY access at "
3483 "0x%04X on N-PHY\n", offset);
3484 dump_stack();
3485 }
3486 #endif /* B43_DEBUG */
3487 }
3488
3489 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3490 {
3491 check_phyreg(dev, reg);
3492 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3493 return b43_read16(dev, B43_MMIO_PHY_DATA);
3494 }
3495
3496 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3497 {
3498 check_phyreg(dev, reg);
3499 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3500 b43_write16(dev, B43_MMIO_PHY_DATA, value);
3501 }
3502
3503 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3504 {
3505 /* Register 1 is a 32-bit register. */
3506 B43_WARN_ON(reg == 1);
3507 /* N-PHY needs 0x100 for read access */
3508 reg |= 0x100;
3509
3510 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3511 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3512 }
3513
3514 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3515 {
3516 /* Register 1 is a 32-bit register. */
3517 B43_WARN_ON(reg == 1);
3518
3519 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3520 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3521 }
3522
3523 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
3524 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3525 bool blocked)
3526 {
3527 struct b43_phy_n *nphy = dev->phy.n;
3528
3529 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3530 b43err(dev->wl, "MAC not suspended\n");
3531
3532 if (blocked) {
3533 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3534 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3535 if (dev->phy.rev >= 3) {
3536 b43_radio_mask(dev, 0x09, ~0x2);
3537
3538 b43_radio_write(dev, 0x204D, 0);
3539 b43_radio_write(dev, 0x2053, 0);
3540 b43_radio_write(dev, 0x2058, 0);
3541 b43_radio_write(dev, 0x205E, 0);
3542 b43_radio_mask(dev, 0x2062, ~0xF0);
3543 b43_radio_write(dev, 0x2064, 0);
3544
3545 b43_radio_write(dev, 0x304D, 0);
3546 b43_radio_write(dev, 0x3053, 0);
3547 b43_radio_write(dev, 0x3058, 0);
3548 b43_radio_write(dev, 0x305E, 0);
3549 b43_radio_mask(dev, 0x3062, ~0xF0);
3550 b43_radio_write(dev, 0x3064, 0);
3551 }
3552 } else {
3553 if (dev->phy.rev >= 3) {
3554 b43_radio_init2056(dev);
3555 b43_switch_channel(dev, dev->phy.channel);
3556 } else {
3557 b43_radio_init2055(dev);
3558 }
3559 }
3560 }
3561
3562 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3563 {
3564 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3565 on ? 0 : 0x7FFF);
3566 }
3567
3568 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3569 unsigned int new_channel)
3570 {
3571 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
3572 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
3573
3574 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3575 if ((new_channel < 1) || (new_channel > 14))
3576 return -EINVAL;
3577 } else {
3578 if (new_channel > 200)
3579 return -EINVAL;
3580 }
3581
3582 return b43_nphy_set_channel(dev, channel, channel_type);
3583 }
3584
3585 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3586 {
3587 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3588 return 1;
3589 return 36;
3590 }
3591
3592 const struct b43_phy_operations b43_phyops_n = {
3593 .allocate = b43_nphy_op_allocate,
3594 .free = b43_nphy_op_free,
3595 .prepare_structs = b43_nphy_op_prepare_structs,
3596 .init = b43_nphy_op_init,
3597 .phy_read = b43_nphy_op_read,
3598 .phy_write = b43_nphy_op_write,
3599 .radio_read = b43_nphy_op_radio_read,
3600 .radio_write = b43_nphy_op_radio_write,
3601 .software_rfkill = b43_nphy_op_software_rfkill,
3602 .switch_analog = b43_nphy_op_switch_analog,
3603 .switch_channel = b43_nphy_op_switch_channel,
3604 .get_default_chan = b43_nphy_op_get_default_chan,
3605 .recalc_txpower = b43_nphy_op_recalc_txpower,
3606 .adjust_txpower = b43_nphy_op_adjust_txpower,
3607 };
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