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Merge tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / b43 / phy_n.c
1 /*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <m@bues.ch>
7 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; see the file COPYING. If not, write to
21 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
22 Boston, MA 02110-1301, USA.
23
24 */
25
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
29
30 #include "b43.h"
31 #include "phy_n.h"
32 #include "tables_nphy.h"
33 #include "radio_2055.h"
34 #include "radio_2056.h"
35 #include "main.h"
36
37 struct nphy_txgains {
38 u16 txgm[2];
39 u16 pga[2];
40 u16 pad[2];
41 u16 ipa[2];
42 };
43
44 struct nphy_iqcal_params {
45 u16 txgm;
46 u16 pga;
47 u16 pad;
48 u16 ipa;
49 u16 cal_gain;
50 u16 ncorr[5];
51 };
52
53 struct nphy_iq_est {
54 s32 iq0_prod;
55 u32 i0_pwr;
56 u32 q0_pwr;
57 s32 iq1_prod;
58 u32 i1_pwr;
59 u32 q1_pwr;
60 };
61
62 enum b43_nphy_rf_sequence {
63 B43_RFSEQ_RX2TX,
64 B43_RFSEQ_TX2RX,
65 B43_RFSEQ_RESET2RX,
66 B43_RFSEQ_UPDATE_GAINH,
67 B43_RFSEQ_UPDATE_GAINL,
68 B43_RFSEQ_UPDATE_GAINU,
69 };
70
71 enum b43_nphy_rssi_type {
72 B43_NPHY_RSSI_X = 0,
73 B43_NPHY_RSSI_Y,
74 B43_NPHY_RSSI_Z,
75 B43_NPHY_RSSI_PWRDET,
76 B43_NPHY_RSSI_TSSI_I,
77 B43_NPHY_RSSI_TSSI_Q,
78 B43_NPHY_RSSI_TBD,
79 };
80
81 static inline bool b43_nphy_ipa(struct b43_wldev *dev)
82 {
83 enum ieee80211_band band = b43_current_band(dev->wl);
84 return ((dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
85 (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ));
86 }
87
88 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
89 static u8 b43_nphy_get_rx_core_state(struct b43_wldev *dev)
90 {
91 return (b43_phy_read(dev, B43_NPHY_RFSEQCA) & B43_NPHY_RFSEQCA_RXEN) >>
92 B43_NPHY_RFSEQCA_RXEN_SHIFT;
93 }
94
95 /**************************************************
96 * RF (just without b43_nphy_rf_control_intc_override)
97 **************************************************/
98
99 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
100 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
101 enum b43_nphy_rf_sequence seq)
102 {
103 static const u16 trigger[] = {
104 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
105 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
106 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
107 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
108 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
109 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
110 };
111 int i;
112 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
113
114 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
115
116 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
117 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
118 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
119 for (i = 0; i < 200; i++) {
120 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
121 goto ok;
122 msleep(1);
123 }
124 b43err(dev->wl, "RF sequence status timeout\n");
125 ok:
126 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
127 }
128
129 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
130 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
131 u16 value, u8 core, bool off)
132 {
133 int i;
134 u8 index = fls(field);
135 u8 addr, en_addr, val_addr;
136 /* we expect only one bit set */
137 B43_WARN_ON(field & (~(1 << (index - 1))));
138
139 if (dev->phy.rev >= 3) {
140 const struct nphy_rf_control_override_rev3 *rf_ctrl;
141 for (i = 0; i < 2; i++) {
142 if (index == 0 || index == 16) {
143 b43err(dev->wl,
144 "Unsupported RF Ctrl Override call\n");
145 return;
146 }
147
148 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
149 en_addr = B43_PHY_N((i == 0) ?
150 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
151 val_addr = B43_PHY_N((i == 0) ?
152 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
153
154 if (off) {
155 b43_phy_mask(dev, en_addr, ~(field));
156 b43_phy_mask(dev, val_addr,
157 ~(rf_ctrl->val_mask));
158 } else {
159 if (core == 0 || ((1 << i) & core)) {
160 b43_phy_set(dev, en_addr, field);
161 b43_phy_maskset(dev, val_addr,
162 ~(rf_ctrl->val_mask),
163 (value << rf_ctrl->val_shift));
164 }
165 }
166 }
167 } else {
168 const struct nphy_rf_control_override_rev2 *rf_ctrl;
169 if (off) {
170 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
171 value = 0;
172 } else {
173 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
174 }
175
176 for (i = 0; i < 2; i++) {
177 if (index <= 1 || index == 16) {
178 b43err(dev->wl,
179 "Unsupported RF Ctrl Override call\n");
180 return;
181 }
182
183 if (index == 2 || index == 10 ||
184 (index >= 13 && index <= 15)) {
185 core = 1;
186 }
187
188 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
189 addr = B43_PHY_N((i == 0) ?
190 rf_ctrl->addr0 : rf_ctrl->addr1);
191
192 if ((1 << i) & core)
193 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
194 (value << rf_ctrl->shift));
195
196 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
197 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
198 B43_NPHY_RFCTL_CMD_START);
199 udelay(1);
200 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
201 }
202 }
203 }
204
205 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
206 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
207 u16 value, u8 core)
208 {
209 u8 i, j;
210 u16 reg, tmp, val;
211
212 B43_WARN_ON(dev->phy.rev < 3);
213 B43_WARN_ON(field > 4);
214
215 for (i = 0; i < 2; i++) {
216 if ((core == 1 && i == 1) || (core == 2 && !i))
217 continue;
218
219 reg = (i == 0) ?
220 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
221 b43_phy_set(dev, reg, 0x400);
222
223 switch (field) {
224 case 0:
225 b43_phy_write(dev, reg, 0);
226 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
227 break;
228 case 1:
229 if (!i) {
230 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
231 0xFC3F, (value << 6));
232 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
233 0xFFFE, 1);
234 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
235 B43_NPHY_RFCTL_CMD_START);
236 for (j = 0; j < 100; j++) {
237 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START)) {
238 j = 0;
239 break;
240 }
241 udelay(10);
242 }
243 if (j)
244 b43err(dev->wl,
245 "intc override timeout\n");
246 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
247 0xFFFE);
248 } else {
249 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
250 0xFC3F, (value << 6));
251 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
252 0xFFFE, 1);
253 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
254 B43_NPHY_RFCTL_CMD_RXTX);
255 for (j = 0; j < 100; j++) {
256 if (!(b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX)) {
257 j = 0;
258 break;
259 }
260 udelay(10);
261 }
262 if (j)
263 b43err(dev->wl,
264 "intc override timeout\n");
265 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
266 0xFFFE);
267 }
268 break;
269 case 2:
270 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
271 tmp = 0x0020;
272 val = value << 5;
273 } else {
274 tmp = 0x0010;
275 val = value << 4;
276 }
277 b43_phy_maskset(dev, reg, ~tmp, val);
278 break;
279 case 3:
280 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
281 tmp = 0x0001;
282 val = value;
283 } else {
284 tmp = 0x0004;
285 val = value << 2;
286 }
287 b43_phy_maskset(dev, reg, ~tmp, val);
288 break;
289 case 4:
290 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
291 tmp = 0x0002;
292 val = value << 1;
293 } else {
294 tmp = 0x0008;
295 val = value << 3;
296 }
297 b43_phy_maskset(dev, reg, ~tmp, val);
298 break;
299 }
300 }
301 }
302
303 /**************************************************
304 * Various PHY ops
305 **************************************************/
306
307 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
308 static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
309 const u16 *clip_st)
310 {
311 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
312 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
313 }
314
315 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
316 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
317 {
318 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
319 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
320 }
321
322 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
323 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
324 {
325 u16 tmp;
326
327 if (dev->dev->core_rev == 16)
328 b43_mac_suspend(dev);
329
330 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
331 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
332 B43_NPHY_CLASSCTL_WAITEDEN);
333 tmp &= ~mask;
334 tmp |= (val & mask);
335 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
336
337 if (dev->dev->core_rev == 16)
338 b43_mac_enable(dev);
339
340 return tmp;
341 }
342
343 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
344 static void b43_nphy_reset_cca(struct b43_wldev *dev)
345 {
346 u16 bbcfg;
347
348 b43_phy_force_clock(dev, 1);
349 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
350 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
351 udelay(1);
352 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
353 b43_phy_force_clock(dev, 0);
354 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
355 }
356
357 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
358 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
359 {
360 struct b43_phy *phy = &dev->phy;
361 struct b43_phy_n *nphy = phy->n;
362
363 if (enable) {
364 static const u16 clip[] = { 0xFFFF, 0xFFFF };
365 if (nphy->deaf_count++ == 0) {
366 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
367 b43_nphy_classifier(dev, 0x7, 0);
368 b43_nphy_read_clip_detection(dev, nphy->clip_state);
369 b43_nphy_write_clip_detection(dev, clip);
370 }
371 b43_nphy_reset_cca(dev);
372 } else {
373 if (--nphy->deaf_count == 0) {
374 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
375 b43_nphy_write_clip_detection(dev, nphy->clip_state);
376 }
377 }
378 }
379
380 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
381 static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
382 {
383 struct b43_phy_n *nphy = dev->phy.n;
384
385 u8 i;
386 s16 tmp;
387 u16 data[4];
388 s16 gain[2];
389 u16 minmax[2];
390 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
391
392 if (nphy->hang_avoid)
393 b43_nphy_stay_in_carrier_search(dev, 1);
394
395 if (nphy->gain_boost) {
396 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
397 gain[0] = 6;
398 gain[1] = 6;
399 } else {
400 tmp = 40370 - 315 * dev->phy.channel;
401 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
402 tmp = 23242 - 224 * dev->phy.channel;
403 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
404 }
405 } else {
406 gain[0] = 0;
407 gain[1] = 0;
408 }
409
410 for (i = 0; i < 2; i++) {
411 if (nphy->elna_gain_config) {
412 data[0] = 19 + gain[i];
413 data[1] = 25 + gain[i];
414 data[2] = 25 + gain[i];
415 data[3] = 25 + gain[i];
416 } else {
417 data[0] = lna_gain[0] + gain[i];
418 data[1] = lna_gain[1] + gain[i];
419 data[2] = lna_gain[2] + gain[i];
420 data[3] = lna_gain[3] + gain[i];
421 }
422 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
423
424 minmax[i] = 23 + gain[i];
425 }
426
427 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
428 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
429 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
430 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
431
432 if (nphy->hang_avoid)
433 b43_nphy_stay_in_carrier_search(dev, 0);
434 }
435
436 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
437 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
438 u8 *events, u8 *delays, u8 length)
439 {
440 struct b43_phy_n *nphy = dev->phy.n;
441 u8 i;
442 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
443 u16 offset1 = cmd << 4;
444 u16 offset2 = offset1 + 0x80;
445
446 if (nphy->hang_avoid)
447 b43_nphy_stay_in_carrier_search(dev, true);
448
449 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
450 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
451
452 for (i = length; i < 16; i++) {
453 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
454 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
455 }
456
457 if (nphy->hang_avoid)
458 b43_nphy_stay_in_carrier_search(dev, false);
459 }
460
461 /**************************************************
462 * Radio 0x2056
463 **************************************************/
464
465 static void b43_chantab_radio_2056_upload(struct b43_wldev *dev,
466 const struct b43_nphy_channeltab_entry_rev3 *e)
467 {
468 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1);
469 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2);
470 b43_radio_write(dev, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv);
471 b43_radio_write(dev, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2);
472 b43_radio_write(dev, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1);
473 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1,
474 e->radio_syn_pll_loopfilter1);
475 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2,
476 e->radio_syn_pll_loopfilter2);
477 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER3,
478 e->radio_syn_pll_loopfilter3);
479 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4,
480 e->radio_syn_pll_loopfilter4);
481 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER5,
482 e->radio_syn_pll_loopfilter5);
483 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR27,
484 e->radio_syn_reserved_addr27);
485 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR28,
486 e->radio_syn_reserved_addr28);
487 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR29,
488 e->radio_syn_reserved_addr29);
489 b43_radio_write(dev, B2056_SYN_LOGEN_VCOBUF1,
490 e->radio_syn_logen_vcobuf1);
491 b43_radio_write(dev, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2);
492 b43_radio_write(dev, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3);
493 b43_radio_write(dev, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4);
494
495 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA_TUNE,
496 e->radio_rx0_lnaa_tune);
497 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG_TUNE,
498 e->radio_rx0_lnag_tune);
499
500 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE,
501 e->radio_tx0_intpaa_boost_tune);
502 b43_radio_write(dev, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE,
503 e->radio_tx0_intpag_boost_tune);
504 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE,
505 e->radio_tx0_pada_boost_tune);
506 b43_radio_write(dev, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE,
507 e->radio_tx0_padg_boost_tune);
508 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE,
509 e->radio_tx0_pgaa_boost_tune);
510 b43_radio_write(dev, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE,
511 e->radio_tx0_pgag_boost_tune);
512 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE,
513 e->radio_tx0_mixa_boost_tune);
514 b43_radio_write(dev, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE,
515 e->radio_tx0_mixg_boost_tune);
516
517 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA_TUNE,
518 e->radio_rx1_lnaa_tune);
519 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG_TUNE,
520 e->radio_rx1_lnag_tune);
521
522 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE,
523 e->radio_tx1_intpaa_boost_tune);
524 b43_radio_write(dev, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE,
525 e->radio_tx1_intpag_boost_tune);
526 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE,
527 e->radio_tx1_pada_boost_tune);
528 b43_radio_write(dev, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE,
529 e->radio_tx1_padg_boost_tune);
530 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE,
531 e->radio_tx1_pgaa_boost_tune);
532 b43_radio_write(dev, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE,
533 e->radio_tx1_pgag_boost_tune);
534 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE,
535 e->radio_tx1_mixa_boost_tune);
536 b43_radio_write(dev, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE,
537 e->radio_tx1_mixg_boost_tune);
538 }
539
540 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */
541 static void b43_radio_2056_setup(struct b43_wldev *dev,
542 const struct b43_nphy_channeltab_entry_rev3 *e)
543 {
544 struct ssb_sprom *sprom = dev->dev->bus_sprom;
545 enum ieee80211_band band = b43_current_band(dev->wl);
546 u16 offset;
547 u8 i;
548 u16 bias, cbias, pag_boost, pgag_boost, mixg_boost, padg_boost;
549
550 B43_WARN_ON(dev->phy.rev < 3);
551
552 b43_chantab_radio_2056_upload(dev, e);
553 b2056_upload_syn_pll_cp2(dev, band == IEEE80211_BAND_5GHZ);
554
555 if (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
556 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
557 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
558 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
559 if (dev->dev->chip_id == 0x4716) {
560 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x14);
561 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0);
562 } else {
563 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x0B);
564 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x14);
565 }
566 }
567 if (sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
568 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
569 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER1, 0x1F);
570 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER2, 0x1F);
571 b43_radio_write(dev, B2056_SYN_PLL_LOOPFILTER4, 0x05);
572 b43_radio_write(dev, B2056_SYN_PLL_CP2, 0x0C);
573 }
574
575 if (dev->phy.n->ipa2g_on && band == IEEE80211_BAND_2GHZ) {
576 for (i = 0; i < 2; i++) {
577 offset = i ? B2056_TX1 : B2056_TX0;
578 if (dev->phy.rev >= 5) {
579 b43_radio_write(dev,
580 offset | B2056_TX_PADG_IDAC, 0xcc);
581
582 if (dev->dev->chip_id == 0x4716) {
583 bias = 0x40;
584 cbias = 0x45;
585 pag_boost = 0x5;
586 pgag_boost = 0x33;
587 mixg_boost = 0x55;
588 } else {
589 bias = 0x25;
590 cbias = 0x20;
591 pag_boost = 0x4;
592 pgag_boost = 0x03;
593 mixg_boost = 0x65;
594 }
595 padg_boost = 0x77;
596
597 b43_radio_write(dev,
598 offset | B2056_TX_INTPAG_IMAIN_STAT,
599 bias);
600 b43_radio_write(dev,
601 offset | B2056_TX_INTPAG_IAUX_STAT,
602 bias);
603 b43_radio_write(dev,
604 offset | B2056_TX_INTPAG_CASCBIAS,
605 cbias);
606 b43_radio_write(dev,
607 offset | B2056_TX_INTPAG_BOOST_TUNE,
608 pag_boost);
609 b43_radio_write(dev,
610 offset | B2056_TX_PGAG_BOOST_TUNE,
611 pgag_boost);
612 b43_radio_write(dev,
613 offset | B2056_TX_PADG_BOOST_TUNE,
614 padg_boost);
615 b43_radio_write(dev,
616 offset | B2056_TX_MIXG_BOOST_TUNE,
617 mixg_boost);
618 } else {
619 bias = dev->phy.is_40mhz ? 0x40 : 0x20;
620 b43_radio_write(dev,
621 offset | B2056_TX_INTPAG_IMAIN_STAT,
622 bias);
623 b43_radio_write(dev,
624 offset | B2056_TX_INTPAG_IAUX_STAT,
625 bias);
626 b43_radio_write(dev,
627 offset | B2056_TX_INTPAG_CASCBIAS,
628 0x30);
629 }
630 b43_radio_write(dev, offset | B2056_TX_PA_SPARE1, 0xee);
631 }
632 } else if (dev->phy.n->ipa5g_on && band == IEEE80211_BAND_5GHZ) {
633 /* TODO */
634 }
635
636 udelay(50);
637 /* VCO calibration */
638 b43_radio_write(dev, B2056_SYN_PLL_VCOCAL12, 0x00);
639 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
640 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x18);
641 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x38);
642 b43_radio_write(dev, B2056_TX_INTPAA_PA_MISC, 0x39);
643 udelay(300);
644 }
645
646 static void b43_radio_init2056_pre(struct b43_wldev *dev)
647 {
648 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
649 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
650 /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */
651 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
652 B43_NPHY_RFCTL_CMD_OEPORFORCE);
653 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
654 ~B43_NPHY_RFCTL_CMD_OEPORFORCE);
655 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
656 B43_NPHY_RFCTL_CMD_CHIP0PU);
657 }
658
659 static void b43_radio_init2056_post(struct b43_wldev *dev)
660 {
661 b43_radio_set(dev, B2056_SYN_COM_CTRL, 0xB);
662 b43_radio_set(dev, B2056_SYN_COM_PU, 0x2);
663 b43_radio_set(dev, B2056_SYN_COM_RESET, 0x2);
664 msleep(1);
665 b43_radio_mask(dev, B2056_SYN_COM_RESET, ~0x2);
666 b43_radio_mask(dev, B2056_SYN_PLL_MAST2, ~0xFC);
667 b43_radio_mask(dev, B2056_SYN_RCCAL_CTRL0, ~0x1);
668 /*
669 if (nphy->init_por)
670 Call Radio 2056 Recalibrate
671 */
672 }
673
674 /*
675 * Initialize a Broadcom 2056 N-radio
676 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
677 */
678 static void b43_radio_init2056(struct b43_wldev *dev)
679 {
680 b43_radio_init2056_pre(dev);
681 b2056_upload_inittabs(dev, 0, 0);
682 b43_radio_init2056_post(dev);
683 }
684
685 /**************************************************
686 * Radio 0x2055
687 **************************************************/
688
689 static void b43_chantab_radio_upload(struct b43_wldev *dev,
690 const struct b43_nphy_channeltab_entry_rev2 *e)
691 {
692 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
693 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
694 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
695 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
696 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
697
698 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
699 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
700 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
701 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
702 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
703
704 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
705 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
706 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
707 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
708 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
709
710 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
711 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
712 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
713 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
714 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
715
716 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
717 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
718 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
719 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
720 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
721
722 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
723 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
724 }
725
726 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
727 static void b43_radio_2055_setup(struct b43_wldev *dev,
728 const struct b43_nphy_channeltab_entry_rev2 *e)
729 {
730 B43_WARN_ON(dev->phy.rev >= 3);
731
732 b43_chantab_radio_upload(dev, e);
733 udelay(50);
734 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
735 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
736 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
737 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
738 udelay(300);
739 }
740
741 static void b43_radio_init2055_pre(struct b43_wldev *dev)
742 {
743 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
744 ~B43_NPHY_RFCTL_CMD_PORFORCE);
745 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
746 B43_NPHY_RFCTL_CMD_CHIP0PU |
747 B43_NPHY_RFCTL_CMD_OEPORFORCE);
748 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
749 B43_NPHY_RFCTL_CMD_PORFORCE);
750 }
751
752 static void b43_radio_init2055_post(struct b43_wldev *dev)
753 {
754 struct b43_phy_n *nphy = dev->phy.n;
755 struct ssb_sprom *sprom = dev->dev->bus_sprom;
756 int i;
757 u16 val;
758 bool workaround = false;
759
760 if (sprom->revision < 4)
761 workaround = (dev->dev->board_vendor != PCI_VENDOR_ID_BROADCOM
762 && dev->dev->board_type == 0x46D
763 && dev->dev->board_rev >= 0x41);
764 else
765 workaround =
766 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
767
768 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
769 if (workaround) {
770 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
771 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
772 }
773 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
774 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
775 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
776 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
777 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
778 msleep(1);
779 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
780 for (i = 0; i < 200; i++) {
781 val = b43_radio_read(dev, B2055_CAL_COUT2);
782 if (val & 0x80) {
783 i = 0;
784 break;
785 }
786 udelay(10);
787 }
788 if (i)
789 b43err(dev->wl, "radio post init timeout\n");
790 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
791 b43_switch_channel(dev, dev->phy.channel);
792 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
793 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
794 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
795 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
796 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
797 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
798 if (!nphy->gain_boost) {
799 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
800 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
801 } else {
802 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
803 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
804 }
805 udelay(2);
806 }
807
808 /*
809 * Initialize a Broadcom 2055 N-radio
810 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
811 */
812 static void b43_radio_init2055(struct b43_wldev *dev)
813 {
814 b43_radio_init2055_pre(dev);
815 if (b43_status(dev) < B43_STAT_INITIALIZED) {
816 /* Follow wl, not specs. Do not force uploading all regs */
817 b2055_upload_inittab(dev, 0, 0);
818 } else {
819 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
820 b2055_upload_inittab(dev, ghz5, 0);
821 }
822 b43_radio_init2055_post(dev);
823 }
824
825 /**************************************************
826 * Samples
827 **************************************************/
828
829 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
830 static int b43_nphy_load_samples(struct b43_wldev *dev,
831 struct b43_c32 *samples, u16 len) {
832 struct b43_phy_n *nphy = dev->phy.n;
833 u16 i;
834 u32 *data;
835
836 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
837 if (!data) {
838 b43err(dev->wl, "allocation for samples loading failed\n");
839 return -ENOMEM;
840 }
841 if (nphy->hang_avoid)
842 b43_nphy_stay_in_carrier_search(dev, 1);
843
844 for (i = 0; i < len; i++) {
845 data[i] = (samples[i].i & 0x3FF << 10);
846 data[i] |= samples[i].q & 0x3FF;
847 }
848 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
849
850 kfree(data);
851 if (nphy->hang_avoid)
852 b43_nphy_stay_in_carrier_search(dev, 0);
853 return 0;
854 }
855
856 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
857 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
858 bool test)
859 {
860 int i;
861 u16 bw, len, rot, angle;
862 struct b43_c32 *samples;
863
864
865 bw = (dev->phy.is_40mhz) ? 40 : 20;
866 len = bw << 3;
867
868 if (test) {
869 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
870 bw = 82;
871 else
872 bw = 80;
873
874 if (dev->phy.is_40mhz)
875 bw <<= 1;
876
877 len = bw << 1;
878 }
879
880 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
881 if (!samples) {
882 b43err(dev->wl, "allocation for samples generation failed\n");
883 return 0;
884 }
885 rot = (((freq * 36) / bw) << 16) / 100;
886 angle = 0;
887
888 for (i = 0; i < len; i++) {
889 samples[i] = b43_cordic(angle);
890 angle += rot;
891 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
892 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
893 }
894
895 i = b43_nphy_load_samples(dev, samples, len);
896 kfree(samples);
897 return (i < 0) ? 0 : len;
898 }
899
900 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
901 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
902 u16 wait, bool iqmode, bool dac_test)
903 {
904 struct b43_phy_n *nphy = dev->phy.n;
905 int i;
906 u16 seq_mode;
907 u32 tmp;
908
909 if (nphy->hang_avoid)
910 b43_nphy_stay_in_carrier_search(dev, true);
911
912 if ((nphy->bb_mult_save & 0x80000000) == 0) {
913 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
914 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
915 }
916
917 if (!dev->phy.is_40mhz)
918 tmp = 0x6464;
919 else
920 tmp = 0x4747;
921 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
922
923 if (nphy->hang_avoid)
924 b43_nphy_stay_in_carrier_search(dev, false);
925
926 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
927
928 if (loops != 0xFFFF)
929 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
930 else
931 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
932
933 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
934
935 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
936
937 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
938 if (iqmode) {
939 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
940 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
941 } else {
942 if (dac_test)
943 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
944 else
945 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
946 }
947 for (i = 0; i < 100; i++) {
948 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & 1)) {
949 i = 0;
950 break;
951 }
952 udelay(10);
953 }
954 if (i)
955 b43err(dev->wl, "run samples timeout\n");
956
957 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
958 }
959
960 /**************************************************
961 * RSSI
962 **************************************************/
963
964 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
965 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
966 s8 offset, u8 core, u8 rail,
967 enum b43_nphy_rssi_type type)
968 {
969 u16 tmp;
970 bool core1or5 = (core == 1) || (core == 5);
971 bool core2or5 = (core == 2) || (core == 5);
972
973 offset = clamp_val(offset, -32, 31);
974 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
975
976 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
977 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
978 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
979 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
980 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Z))
981 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
982 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Z))
983 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
984
985 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
986 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
987 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
988 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
989 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_X))
990 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
991 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_X))
992 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
993
994 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
995 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
996 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
997 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
998 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_Y))
999 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1000 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_Y))
1001 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1002
1003 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1004 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1005 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1006 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1007 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_TBD))
1008 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1009 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_TBD))
1010 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1011
1012 if (core1or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1013 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1014 if (core1or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1015 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1016 if (core2or5 && (rail == 0) && (type == B43_NPHY_RSSI_PWRDET))
1017 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1018 if (core2or5 && (rail == 1) && (type == B43_NPHY_RSSI_PWRDET))
1019 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1020
1021 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_I))
1022 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1023 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_I))
1024 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1025
1026 if (core1or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1027 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1028 if (core2or5 && (type == B43_NPHY_RSSI_TSSI_Q))
1029 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1030 }
1031
1032 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1033 {
1034 u8 i;
1035 u16 reg, val;
1036
1037 if (code == 0) {
1038 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1039 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1040 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1041 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1042 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1043 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1044 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1045 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1046 } else {
1047 for (i = 0; i < 2; i++) {
1048 if ((code == 1 && i == 1) || (code == 2 && !i))
1049 continue;
1050
1051 reg = (i == 0) ?
1052 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1053 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1054
1055 if (type < 3) {
1056 reg = (i == 0) ?
1057 B43_NPHY_AFECTL_C1 :
1058 B43_NPHY_AFECTL_C2;
1059 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1060
1061 reg = (i == 0) ?
1062 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1063 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1064 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1065
1066 if (type == 0)
1067 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1068 else if (type == 1)
1069 val = 16;
1070 else
1071 val = 32;
1072 b43_phy_set(dev, reg, val);
1073
1074 reg = (i == 0) ?
1075 B43_NPHY_TXF_40CO_B1S0 :
1076 B43_NPHY_TXF_40CO_B32S1;
1077 b43_phy_set(dev, reg, 0x0020);
1078 } else {
1079 if (type == 6)
1080 val = 0x0100;
1081 else if (type == 3)
1082 val = 0x0200;
1083 else
1084 val = 0x0300;
1085
1086 reg = (i == 0) ?
1087 B43_NPHY_AFECTL_C1 :
1088 B43_NPHY_AFECTL_C2;
1089
1090 b43_phy_maskset(dev, reg, 0xFCFF, val);
1091 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1092
1093 if (type != 3 && type != 6) {
1094 enum ieee80211_band band =
1095 b43_current_band(dev->wl);
1096
1097 if (b43_nphy_ipa(dev))
1098 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1099 else
1100 val = 0x11;
1101 reg = (i == 0) ? 0x2000 : 0x3000;
1102 reg |= B2055_PADDRV;
1103 b43_radio_write16(dev, reg, val);
1104
1105 reg = (i == 0) ?
1106 B43_NPHY_AFECTL_OVER1 :
1107 B43_NPHY_AFECTL_OVER;
1108 b43_phy_set(dev, reg, 0x0200);
1109 }
1110 }
1111 }
1112 }
1113 }
1114
1115 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1116 {
1117 u16 val;
1118
1119 if (type < 3)
1120 val = 0;
1121 else if (type == 6)
1122 val = 1;
1123 else if (type == 3)
1124 val = 2;
1125 else
1126 val = 3;
1127
1128 val = (val << 12) | (val << 14);
1129 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1130 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1131
1132 if (type < 3) {
1133 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1134 (type + 1) << 4);
1135 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1136 (type + 1) << 4);
1137 }
1138
1139 if (code == 0) {
1140 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x3000);
1141 if (type < 3) {
1142 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1143 ~(B43_NPHY_RFCTL_CMD_RXEN |
1144 B43_NPHY_RFCTL_CMD_CORESEL));
1145 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1146 ~(0x1 << 12 |
1147 0x1 << 5 |
1148 0x1 << 1 |
1149 0x1));
1150 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
1151 ~B43_NPHY_RFCTL_CMD_START);
1152 udelay(20);
1153 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1154 }
1155 } else {
1156 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x3000);
1157 if (type < 3) {
1158 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1159 ~(B43_NPHY_RFCTL_CMD_RXEN |
1160 B43_NPHY_RFCTL_CMD_CORESEL),
1161 (B43_NPHY_RFCTL_CMD_RXEN |
1162 code << B43_NPHY_RFCTL_CMD_CORESEL_SHIFT));
1163 b43_phy_set(dev, B43_NPHY_RFCTL_OVER,
1164 (0x1 << 12 |
1165 0x1 << 5 |
1166 0x1 << 1 |
1167 0x1));
1168 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1169 B43_NPHY_RFCTL_CMD_START);
1170 udelay(20);
1171 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~0x1);
1172 }
1173 }
1174 }
1175
1176 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1177 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1178 {
1179 if (dev->phy.rev >= 3)
1180 b43_nphy_rev3_rssi_select(dev, code, type);
1181 else
1182 b43_nphy_rev2_rssi_select(dev, code, type);
1183 }
1184
1185 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1186 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1187 {
1188 int i;
1189 for (i = 0; i < 2; i++) {
1190 if (type == 2) {
1191 if (i == 0) {
1192 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1193 0xFC, buf[0]);
1194 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1195 0xFC, buf[1]);
1196 } else {
1197 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1198 0xFC, buf[2 * i]);
1199 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1200 0xFC, buf[2 * i + 1]);
1201 }
1202 } else {
1203 if (i == 0)
1204 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1205 0xF3, buf[0] << 2);
1206 else
1207 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1208 0xF3, buf[2 * i + 1] << 2);
1209 }
1210 }
1211 }
1212
1213 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1214 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1215 u8 nsamp)
1216 {
1217 int i;
1218 int out;
1219 u16 save_regs_phy[9];
1220 u16 s[2];
1221
1222 if (dev->phy.rev >= 3) {
1223 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1224 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1225 save_regs_phy[2] = b43_phy_read(dev,
1226 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1227 save_regs_phy[3] = b43_phy_read(dev,
1228 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1229 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1230 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1231 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1232 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1233 save_regs_phy[8] = 0;
1234 } else {
1235 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1236 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1237 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1238 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1239 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1240 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1241 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
1242 save_regs_phy[7] = 0;
1243 save_regs_phy[8] = 0;
1244 }
1245
1246 b43_nphy_rssi_select(dev, 5, type);
1247
1248 if (dev->phy.rev < 2) {
1249 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1250 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1251 }
1252
1253 for (i = 0; i < 4; i++)
1254 buf[i] = 0;
1255
1256 for (i = 0; i < nsamp; i++) {
1257 if (dev->phy.rev < 2) {
1258 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1259 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1260 } else {
1261 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1262 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1263 }
1264
1265 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1266 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1267 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1268 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1269 }
1270 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1271 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1272
1273 if (dev->phy.rev < 2)
1274 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1275
1276 if (dev->phy.rev >= 3) {
1277 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1278 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1279 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1280 save_regs_phy[2]);
1281 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1282 save_regs_phy[3]);
1283 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1284 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1285 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1286 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1287 } else {
1288 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1289 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1290 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1291 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1292 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1293 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1294 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
1295 }
1296
1297 return out;
1298 }
1299
1300 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1301 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1302 {
1303 struct b43_phy_n *nphy = dev->phy.n;
1304
1305 u16 saved_regs_phy_rfctl[2];
1306 u16 saved_regs_phy[13];
1307 u16 regs_to_store[] = {
1308 B43_NPHY_AFECTL_OVER1, B43_NPHY_AFECTL_OVER,
1309 B43_NPHY_AFECTL_C1, B43_NPHY_AFECTL_C2,
1310 B43_NPHY_TXF_40CO_B1S1, B43_NPHY_RFCTL_OVER,
1311 B43_NPHY_TXF_40CO_B1S0, B43_NPHY_TXF_40CO_B32S1,
1312 B43_NPHY_RFCTL_CMD,
1313 B43_NPHY_RFCTL_LUT_TRSW_UP1, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1314 B43_NPHY_RFCTL_RSSIO1, B43_NPHY_RFCTL_RSSIO2
1315 };
1316
1317 u16 class;
1318
1319 u16 clip_state[2];
1320 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1321
1322 u8 vcm_final = 0;
1323 s8 offset[4];
1324 s32 results[8][4] = { };
1325 s32 results_min[4] = { };
1326 s32 poll_results[4] = { };
1327
1328 u16 *rssical_radio_regs = NULL;
1329 u16 *rssical_phy_regs = NULL;
1330
1331 u16 r; /* routing */
1332 u8 rx_core_state;
1333 u8 core, i, j;
1334
1335 class = b43_nphy_classifier(dev, 0, 0);
1336 b43_nphy_classifier(dev, 7, 4);
1337 b43_nphy_read_clip_detection(dev, clip_state);
1338 b43_nphy_write_clip_detection(dev, clip_off);
1339
1340 saved_regs_phy_rfctl[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1341 saved_regs_phy_rfctl[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1342 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1343 saved_regs_phy[i] = b43_phy_read(dev, regs_to_store[i]);
1344
1345 b43_nphy_rf_control_intc_override(dev, 0, 0, 7);
1346 b43_nphy_rf_control_intc_override(dev, 1, 1, 7);
1347 b43_nphy_rf_control_override(dev, 0x1, 0, 0, false);
1348 b43_nphy_rf_control_override(dev, 0x2, 1, 0, false);
1349 b43_nphy_rf_control_override(dev, 0x80, 1, 0, false);
1350 b43_nphy_rf_control_override(dev, 0x40, 1, 0, false);
1351
1352 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1353 b43_nphy_rf_control_override(dev, 0x20, 0, 0, false);
1354 b43_nphy_rf_control_override(dev, 0x10, 1, 0, false);
1355 } else {
1356 b43_nphy_rf_control_override(dev, 0x10, 0, 0, false);
1357 b43_nphy_rf_control_override(dev, 0x20, 1, 0, false);
1358 }
1359
1360 rx_core_state = b43_nphy_get_rx_core_state(dev);
1361 for (core = 0; core < 2; core++) {
1362 if (!(rx_core_state & (1 << core)))
1363 continue;
1364 r = core ? B2056_RX1 : B2056_RX0;
1365 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, 2);
1366 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, 2);
1367 for (i = 0; i < 8; i++) {
1368 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1369 i << 2);
1370 b43_nphy_poll_rssi(dev, 2, results[i], 8);
1371 }
1372 for (i = 0; i < 4; i += 2) {
1373 s32 curr;
1374 s32 mind = 40;
1375 s32 minpoll = 249;
1376 u8 minvcm = 0;
1377 if (2 * core != i)
1378 continue;
1379 for (j = 0; j < 8; j++) {
1380 curr = results[j][i] * results[j][i] +
1381 results[j][i + 1] * results[j][i];
1382 if (curr < mind) {
1383 mind = curr;
1384 minvcm = j;
1385 }
1386 if (results[j][i] < minpoll)
1387 minpoll = results[j][i];
1388 }
1389 vcm_final = minvcm;
1390 results_min[i] = minpoll;
1391 }
1392 b43_radio_maskset(dev, r | B2056_RX_RSSI_MISC, 0xE3,
1393 vcm_final << 2);
1394 for (i = 0; i < 4; i++) {
1395 if (core != i / 2)
1396 continue;
1397 offset[i] = -results[vcm_final][i];
1398 if (offset[i] < 0)
1399 offset[i] = -((abs(offset[i]) + 4) / 8);
1400 else
1401 offset[i] = (offset[i] + 4) / 8;
1402 if (results_min[i] == 248)
1403 offset[i] = -32;
1404 b43_nphy_scale_offset_rssi(dev, 0, offset[i],
1405 (i / 2 == 0) ? 1 : 2,
1406 (i % 2 == 0) ? 0 : 1,
1407 2);
1408 }
1409 }
1410 for (core = 0; core < 2; core++) {
1411 if (!(rx_core_state & (1 << core)))
1412 continue;
1413 for (i = 0; i < 2; i++) {
1414 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 0, i);
1415 b43_nphy_scale_offset_rssi(dev, 0, 0, core + 1, 1, i);
1416 b43_nphy_poll_rssi(dev, i, poll_results, 8);
1417 for (j = 0; j < 4; j++) {
1418 if (j / 2 == core) {
1419 offset[j] = 232 - poll_results[j];
1420 if (offset[j] < 0)
1421 offset[j] = -(abs(offset[j] + 4) / 8);
1422 else
1423 offset[j] = (offset[j] + 4) / 8;
1424 b43_nphy_scale_offset_rssi(dev, 0,
1425 offset[2 * core], core + 1, j % 2, i);
1426 }
1427 }
1428 }
1429 }
1430
1431 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]);
1432 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]);
1433
1434 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1435
1436 b43_phy_set(dev, B43_NPHY_TXF_40CO_B1S1, 0x1);
1437 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_START);
1438 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1439
1440 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1441 b43_phy_set(dev, B43_NPHY_RFCTL_CMD, B43_NPHY_RFCTL_CMD_RXTX);
1442 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1, ~0x1);
1443
1444 for (i = 0; i < ARRAY_SIZE(regs_to_store); i++)
1445 b43_phy_write(dev, regs_to_store[i], saved_regs_phy[i]);
1446
1447 /* Store for future configuration */
1448 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1449 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1450 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1451 } else {
1452 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1453 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1454 }
1455 rssical_radio_regs[0] = b43_radio_read(dev, 0x602B);
1456 rssical_radio_regs[0] = b43_radio_read(dev, 0x702B);
1457 rssical_phy_regs[0] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Z);
1458 rssical_phy_regs[1] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z);
1459 rssical_phy_regs[2] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Z);
1460 rssical_phy_regs[3] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z);
1461 rssical_phy_regs[4] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_X);
1462 rssical_phy_regs[5] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_X);
1463 rssical_phy_regs[6] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_X);
1464 rssical_phy_regs[7] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_X);
1465 rssical_phy_regs[8] = b43_phy_read(dev, B43_NPHY_RSSIMC_0I_RSSI_Y);
1466 rssical_phy_regs[9] = b43_phy_read(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y);
1467 rssical_phy_regs[10] = b43_phy_read(dev, B43_NPHY_RSSIMC_1I_RSSI_Y);
1468 rssical_phy_regs[11] = b43_phy_read(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y);
1469
1470 /* Remember for which channel we store configuration */
1471 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1472 nphy->rssical_chanspec_2G.center_freq = dev->phy.channel_freq;
1473 else
1474 nphy->rssical_chanspec_5G.center_freq = dev->phy.channel_freq;
1475
1476 /* End of calibration, restore configuration */
1477 b43_nphy_classifier(dev, 7, class);
1478 b43_nphy_write_clip_detection(dev, clip_state);
1479 }
1480
1481 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1482 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1483 {
1484 int i, j;
1485 u8 state[4];
1486 u8 code, val;
1487 u16 class, override;
1488 u8 regs_save_radio[2];
1489 u16 regs_save_phy[2];
1490
1491 s8 offset[4];
1492 u8 core;
1493 u8 rail;
1494
1495 u16 clip_state[2];
1496 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1497 s32 results_min[4] = { };
1498 u8 vcm_final[4] = { };
1499 s32 results[4][4] = { };
1500 s32 miniq[4][2] = { };
1501
1502 if (type == 2) {
1503 code = 0;
1504 val = 6;
1505 } else if (type < 2) {
1506 code = 25;
1507 val = 4;
1508 } else {
1509 B43_WARN_ON(1);
1510 return;
1511 }
1512
1513 class = b43_nphy_classifier(dev, 0, 0);
1514 b43_nphy_classifier(dev, 7, 4);
1515 b43_nphy_read_clip_detection(dev, clip_state);
1516 b43_nphy_write_clip_detection(dev, clip_off);
1517
1518 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1519 override = 0x140;
1520 else
1521 override = 0x110;
1522
1523 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1524 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1525 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1526 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1527
1528 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1529 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1530 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1531 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1532
1533 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1534 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1535 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1536 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1537 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1538 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1539
1540 b43_nphy_rssi_select(dev, 5, type);
1541 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1542 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1543
1544 for (i = 0; i < 4; i++) {
1545 u8 tmp[4];
1546 for (j = 0; j < 4; j++)
1547 tmp[j] = i;
1548 if (type != 1)
1549 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1550 b43_nphy_poll_rssi(dev, type, results[i], 8);
1551 if (type < 2)
1552 for (j = 0; j < 2; j++)
1553 miniq[i][j] = min(results[i][2 * j],
1554 results[i][2 * j + 1]);
1555 }
1556
1557 for (i = 0; i < 4; i++) {
1558 s32 mind = 40;
1559 u8 minvcm = 0;
1560 s32 minpoll = 249;
1561 s32 curr;
1562 for (j = 0; j < 4; j++) {
1563 if (type == 2)
1564 curr = abs(results[j][i]);
1565 else
1566 curr = abs(miniq[j][i / 2] - code * 8);
1567
1568 if (curr < mind) {
1569 mind = curr;
1570 minvcm = j;
1571 }
1572
1573 if (results[j][i] < minpoll)
1574 minpoll = results[j][i];
1575 }
1576 results_min[i] = minpoll;
1577 vcm_final[i] = minvcm;
1578 }
1579
1580 if (type != 1)
1581 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1582
1583 for (i = 0; i < 4; i++) {
1584 offset[i] = (code * 8) - results[vcm_final[i]][i];
1585
1586 if (offset[i] < 0)
1587 offset[i] = -((abs(offset[i]) + 4) / 8);
1588 else
1589 offset[i] = (offset[i] + 4) / 8;
1590
1591 if (results_min[i] == 248)
1592 offset[i] = code - 32;
1593
1594 core = (i / 2) ? 2 : 1;
1595 rail = (i % 2) ? 1 : 0;
1596
1597 b43_nphy_scale_offset_rssi(dev, 0, offset[i], core, rail,
1598 type);
1599 }
1600
1601 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1602 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
1603
1604 switch (state[2]) {
1605 case 1:
1606 b43_nphy_rssi_select(dev, 1, 2);
1607 break;
1608 case 4:
1609 b43_nphy_rssi_select(dev, 1, 0);
1610 break;
1611 case 2:
1612 b43_nphy_rssi_select(dev, 1, 1);
1613 break;
1614 default:
1615 b43_nphy_rssi_select(dev, 1, 1);
1616 break;
1617 }
1618
1619 switch (state[3]) {
1620 case 1:
1621 b43_nphy_rssi_select(dev, 2, 2);
1622 break;
1623 case 4:
1624 b43_nphy_rssi_select(dev, 2, 0);
1625 break;
1626 default:
1627 b43_nphy_rssi_select(dev, 2, 1);
1628 break;
1629 }
1630
1631 b43_nphy_rssi_select(dev, 0, type);
1632
1633 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1634 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1635 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1636 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1637
1638 b43_nphy_classifier(dev, 7, class);
1639 b43_nphy_write_clip_detection(dev, clip_state);
1640 /* Specs don't say about reset here, but it makes wl and b43 dumps
1641 identical, it really seems wl performs this */
1642 b43_nphy_reset_cca(dev);
1643 }
1644
1645 /*
1646 * RSSI Calibration
1647 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1648 */
1649 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1650 {
1651 if (dev->phy.rev >= 3) {
1652 b43_nphy_rev3_rssi_cal(dev);
1653 } else {
1654 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Z);
1655 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_X);
1656 b43_nphy_rev2_rssi_cal(dev, B43_NPHY_RSSI_Y);
1657 }
1658 }
1659
1660 /**************************************************
1661 * Workarounds
1662 **************************************************/
1663
1664 static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1665 {
1666 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1667
1668 bool ghz5;
1669 bool ext_lna;
1670 u16 rssi_gain;
1671 struct nphy_gain_ctl_workaround_entry *e;
1672 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
1673 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
1674
1675 /* Prepare values */
1676 ghz5 = b43_phy_read(dev, B43_NPHY_BANDCTL)
1677 & B43_NPHY_BANDCTL_5GHZ;
1678 ext_lna = ghz5 ? sprom->boardflags_hi & B43_BFH_EXTLNA_5GHZ :
1679 sprom->boardflags_lo & B43_BFL_EXTLNA;
1680 e = b43_nphy_get_gain_ctl_workaround_ent(dev, ghz5, ext_lna);
1681 if (ghz5 && dev->phy.rev >= 5)
1682 rssi_gain = 0x90;
1683 else
1684 rssi_gain = 0x50;
1685
1686 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1687
1688 /* Set Clip 2 detect */
1689 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
1690 B43_NPHY_C1_CGAINI_CL2DETECT);
1691 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1692 B43_NPHY_C2_CGAINI_CL2DETECT);
1693
1694 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1695 0x17);
1696 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1697 0x17);
1698 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0);
1699 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0);
1700 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00);
1701 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00);
1702 b43_radio_write(dev, B2056_RX0 | B2056_RX_RSSI_GAIN,
1703 rssi_gain);
1704 b43_radio_write(dev, B2056_RX1 | B2056_RX_RSSI_GAIN,
1705 rssi_gain);
1706 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1707 0x17);
1708 b43_radio_write(dev, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC,
1709 0x17);
1710 b43_radio_write(dev, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF);
1711 b43_radio_write(dev, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF);
1712
1713 b43_ntab_write_bulk(dev, B43_NTAB8(0, 8), 4, e->lna1_gain);
1714 b43_ntab_write_bulk(dev, B43_NTAB8(1, 8), 4, e->lna1_gain);
1715 b43_ntab_write_bulk(dev, B43_NTAB8(0, 16), 4, e->lna2_gain);
1716 b43_ntab_write_bulk(dev, B43_NTAB8(1, 16), 4, e->lna2_gain);
1717 b43_ntab_write_bulk(dev, B43_NTAB8(0, 32), 10, e->gain_db);
1718 b43_ntab_write_bulk(dev, B43_NTAB8(1, 32), 10, e->gain_db);
1719 b43_ntab_write_bulk(dev, B43_NTAB8(2, 32), 10, e->gain_bits);
1720 b43_ntab_write_bulk(dev, B43_NTAB8(3, 32), 10, e->gain_bits);
1721 b43_ntab_write_bulk(dev, B43_NTAB8(0, 0x40), 6, lpf_gain);
1722 b43_ntab_write_bulk(dev, B43_NTAB8(1, 0x40), 6, lpf_gain);
1723 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
1724 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
1725
1726 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain);
1727 b43_phy_write(dev, 0x2A7, e->init_gain);
1728 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
1729 e->rfseq_init);
1730
1731 /* TODO: check defines. Do not match variables names */
1732 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain);
1733 b43_phy_write(dev, 0x2A9, e->cliphi_gain);
1734 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain);
1735 b43_phy_write(dev, 0x2AB, e->clipmd_gain);
1736 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain);
1737 b43_phy_write(dev, 0x2AD, e->cliplo_gain);
1738
1739 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin);
1740 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl);
1741 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
1742 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
1743 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
1744 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1745 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip);
1746 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1747 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip);
1748 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1749 }
1750
1751 static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
1752 {
1753 struct b43_phy_n *nphy = dev->phy.n;
1754
1755 u8 i, j;
1756 u8 code;
1757 u16 tmp;
1758 u8 rfseq_events[3] = { 6, 8, 7 };
1759 u8 rfseq_delays[3] = { 10, 30, 1 };
1760
1761 /* Set Clip 2 detect */
1762 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
1763 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
1764
1765 /* Set narrowband clip threshold */
1766 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
1767 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
1768
1769 if (!dev->phy.is_40mhz) {
1770 /* Set dwell lengths */
1771 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
1772 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
1773 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
1774 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
1775 }
1776
1777 /* Set wideband clip 2 threshold */
1778 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
1779 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2, 21);
1780 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
1781 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
1782
1783 if (!dev->phy.is_40mhz) {
1784 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
1785 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
1786 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
1787 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
1788 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
1789 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
1790 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
1791 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
1792 }
1793
1794 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
1795
1796 if (nphy->gain_boost) {
1797 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
1798 dev->phy.is_40mhz)
1799 code = 4;
1800 else
1801 code = 5;
1802 } else {
1803 code = dev->phy.is_40mhz ? 6 : 7;
1804 }
1805
1806 /* Set HPVGA2 index */
1807 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN, ~B43_NPHY_C1_INITGAIN_HPVGA2,
1808 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
1809 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN, ~B43_NPHY_C2_INITGAIN_HPVGA2,
1810 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
1811
1812 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1813 /* specs say about 2 loops, but wl does 4 */
1814 for (i = 0; i < 4; i++)
1815 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, (code << 8 | 0x7C));
1816
1817 b43_nphy_adjust_lna_gain_table(dev);
1818
1819 if (nphy->elna_gain_config) {
1820 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
1821 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1822 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1823 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1824 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1825
1826 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
1827 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
1828 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1829 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1830 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
1831
1832 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
1833 /* specs say about 2 loops, but wl does 4 */
1834 for (i = 0; i < 4; i++)
1835 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1836 (code << 8 | 0x74));
1837 }
1838
1839 if (dev->phy.rev == 2) {
1840 for (i = 0; i < 4; i++) {
1841 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1842 (0x0400 * i) + 0x0020);
1843 for (j = 0; j < 21; j++) {
1844 tmp = j * (i < 2 ? 3 : 1);
1845 b43_phy_write(dev,
1846 B43_NPHY_TABLE_DATALO, tmp);
1847 }
1848 }
1849 }
1850
1851 b43_nphy_set_rf_sequence(dev, 5, rfseq_events, rfseq_delays, 3);
1852 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
1853 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
1854 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1855
1856 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1857 b43_phy_maskset(dev, B43_PHY_N(0xC5D), 0xFF80, 4);
1858 }
1859
1860 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
1861 static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
1862 {
1863 if (dev->phy.rev >= 3)
1864 b43_nphy_gain_ctl_workarounds_rev3plus(dev);
1865 else
1866 b43_nphy_gain_ctl_workarounds_rev1_2(dev);
1867 }
1868
1869 static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
1870 {
1871 struct b43_phy_n *nphy = dev->phy.n;
1872 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1873
1874 /* TX to RX */
1875 u8 tx2rx_events[8] = { 0x4, 0x3, 0x6, 0x5, 0x2, 0x1, 0x8, 0x1F };
1876 u8 tx2rx_delays[8] = { 8, 4, 2, 2, 4, 4, 6, 1 };
1877 /* RX to TX */
1878 u8 rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3,
1879 0x1F };
1880 u8 rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 };
1881 u8 rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F };
1882 u8 rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 };
1883
1884 u16 tmp16;
1885 u32 tmp32;
1886
1887 b43_phy_write(dev, 0x23f, 0x1f8);
1888 b43_phy_write(dev, 0x240, 0x1f8);
1889
1890 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
1891 tmp32 &= 0xffffff;
1892 b43_ntab_write(dev, B43_NTAB32(30, 0), tmp32);
1893
1894 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x0125);
1895 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x01B3);
1896 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x0105);
1897 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x016E);
1898 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
1899 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
1900
1901 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C);
1902 b43_phy_write(dev, 0x2AE, 0x000C);
1903
1904 /* TX to RX */
1905 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
1906 ARRAY_SIZE(tx2rx_events));
1907
1908 /* RX to TX */
1909 if (b43_nphy_ipa(dev))
1910 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
1911 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
1912 if (nphy->hw_phyrxchain != 3 &&
1913 nphy->hw_phyrxchain != nphy->hw_phytxchain) {
1914 if (b43_nphy_ipa(dev)) {
1915 rx2tx_delays[5] = 59;
1916 rx2tx_delays[6] = 1;
1917 rx2tx_events[7] = 0x1F;
1918 }
1919 b43_nphy_set_rf_sequence(dev, 1, rx2tx_events, rx2tx_delays,
1920 ARRAY_SIZE(rx2tx_events));
1921 }
1922
1923 tmp16 = (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ?
1924 0x2 : 0x9C40;
1925 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
1926
1927 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700);
1928
1929 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
1930 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
1931
1932 b43_nphy_gain_ctl_workarounds(dev);
1933
1934 b43_ntab_write(dev, B43_NTAB16(8, 0), 2);
1935 b43_ntab_write(dev, B43_NTAB16(8, 16), 2);
1936
1937 /* TODO */
1938
1939 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1940 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00);
1941 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1942 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06);
1943 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1944 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07);
1945 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1946 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88);
1947 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1948 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00);
1949 b43_radio_write(dev, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1950 b43_radio_write(dev, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00);
1951
1952 /* N PHY WAR TX Chain Update with hw_phytxchain as argument */
1953
1954 if ((sprom->boardflags2_lo & B43_BFL2_APLL_WAR &&
1955 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
1956 (sprom->boardflags2_lo & B43_BFL2_GPLL_WAR &&
1957 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ))
1958 tmp32 = 0x00088888;
1959 else
1960 tmp32 = 0x88888888;
1961 b43_ntab_write(dev, B43_NTAB32(30, 1), tmp32);
1962 b43_ntab_write(dev, B43_NTAB32(30, 2), tmp32);
1963 b43_ntab_write(dev, B43_NTAB32(30, 3), tmp32);
1964
1965 if (dev->phy.rev == 4 &&
1966 b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1967 b43_radio_write(dev, B2056_TX0 | B2056_TX_GMBB_IDAC,
1968 0x70);
1969 b43_radio_write(dev, B2056_TX1 | B2056_TX_GMBB_IDAC,
1970 0x70);
1971 }
1972
1973 b43_phy_write(dev, 0x224, 0x03eb);
1974 b43_phy_write(dev, 0x225, 0x03eb);
1975 b43_phy_write(dev, 0x226, 0x0341);
1976 b43_phy_write(dev, 0x227, 0x0341);
1977 b43_phy_write(dev, 0x228, 0x042b);
1978 b43_phy_write(dev, 0x229, 0x042b);
1979 b43_phy_write(dev, 0x22a, 0x0381);
1980 b43_phy_write(dev, 0x22b, 0x0381);
1981 b43_phy_write(dev, 0x22c, 0x042b);
1982 b43_phy_write(dev, 0x22d, 0x042b);
1983 b43_phy_write(dev, 0x22e, 0x0381);
1984 b43_phy_write(dev, 0x22f, 0x0381);
1985 }
1986
1987 static void b43_nphy_workarounds_rev1_2(struct b43_wldev *dev)
1988 {
1989 struct ssb_sprom *sprom = dev->dev->bus_sprom;
1990 struct b43_phy *phy = &dev->phy;
1991 struct b43_phy_n *nphy = phy->n;
1992
1993 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1994 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1995
1996 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1997 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1998
1999 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
2000 nphy->band5g_pwrgain) {
2001 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
2002 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
2003 } else {
2004 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
2005 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
2006 }
2007
2008 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0x000A);
2009 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0x000A);
2010 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
2011 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
2012
2013 if (dev->phy.rev < 2) {
2014 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0x0000);
2015 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0x0000);
2016 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
2017 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
2018 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x0800);
2019 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x0800);
2020 }
2021
2022 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
2023 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
2024 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
2025 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
2026
2027 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD &&
2028 dev->dev->board_type == 0x8B) {
2029 delays1[0] = 0x1;
2030 delays1[5] = 0x14;
2031 }
2032 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
2033 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
2034
2035 b43_nphy_gain_ctl_workarounds(dev);
2036
2037 if (dev->phy.rev < 2) {
2038 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
2039 b43_hf_write(dev, b43_hf_read(dev) |
2040 B43_HF_MLADVW);
2041 } else if (dev->phy.rev == 2) {
2042 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
2043 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
2044 }
2045
2046 if (dev->phy.rev < 2)
2047 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
2048 ~B43_NPHY_SCRAM_SIGCTL_SCM);
2049
2050 /* Set phase track alpha and beta */
2051 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
2052 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
2053 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
2054 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
2055 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
2056 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
2057
2058 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
2059 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
2060 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
2061 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
2062 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
2063
2064 if (dev->phy.rev == 2)
2065 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
2066 B43_NPHY_FINERX2_CGC_DECGC);
2067 }
2068
2069 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
2070 static void b43_nphy_workarounds(struct b43_wldev *dev)
2071 {
2072 struct b43_phy *phy = &dev->phy;
2073 struct b43_phy_n *nphy = phy->n;
2074
2075 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2076 b43_nphy_classifier(dev, 1, 0);
2077 else
2078 b43_nphy_classifier(dev, 1, 1);
2079
2080 if (nphy->hang_avoid)
2081 b43_nphy_stay_in_carrier_search(dev, 1);
2082
2083 b43_phy_set(dev, B43_NPHY_IQFLIP,
2084 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
2085
2086 if (dev->phy.rev >= 3)
2087 b43_nphy_workarounds_rev3plus(dev);
2088 else
2089 b43_nphy_workarounds_rev1_2(dev);
2090
2091 if (nphy->hang_avoid)
2092 b43_nphy_stay_in_carrier_search(dev, 0);
2093 }
2094
2095 /**************************************************
2096 * Tx/Rx common
2097 **************************************************/
2098
2099 /*
2100 * Transmits a known value for LO calibration
2101 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
2102 */
2103 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
2104 bool iqmode, bool dac_test)
2105 {
2106 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
2107 if (samp == 0)
2108 return -1;
2109 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
2110 return 0;
2111 }
2112
2113 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
2114 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
2115 {
2116 struct b43_phy_n *nphy = dev->phy.n;
2117
2118 bool override = false;
2119 u16 chain = 0x33;
2120
2121 if (nphy->txrx_chain == 0) {
2122 chain = 0x11;
2123 override = true;
2124 } else if (nphy->txrx_chain == 1) {
2125 chain = 0x22;
2126 override = true;
2127 }
2128
2129 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2130 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
2131 chain);
2132
2133 if (override)
2134 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
2135 B43_NPHY_RFSEQMODE_CAOVER);
2136 else
2137 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2138 ~B43_NPHY_RFSEQMODE_CAOVER);
2139 }
2140
2141 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
2142 static void b43_nphy_stop_playback(struct b43_wldev *dev)
2143 {
2144 struct b43_phy_n *nphy = dev->phy.n;
2145 u16 tmp;
2146
2147 if (nphy->hang_avoid)
2148 b43_nphy_stay_in_carrier_search(dev, 1);
2149
2150 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
2151 if (tmp & 0x1)
2152 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
2153 else if (tmp & 0x2)
2154 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
2155
2156 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
2157
2158 if (nphy->bb_mult_save & 0x80000000) {
2159 tmp = nphy->bb_mult_save & 0xFFFF;
2160 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
2161 nphy->bb_mult_save = 0;
2162 }
2163
2164 if (nphy->hang_avoid)
2165 b43_nphy_stay_in_carrier_search(dev, 0);
2166 }
2167
2168 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2169 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2170 struct nphy_txgains target,
2171 struct nphy_iqcal_params *params)
2172 {
2173 int i, j, indx;
2174 u16 gain;
2175
2176 if (dev->phy.rev >= 3) {
2177 params->txgm = target.txgm[core];
2178 params->pga = target.pga[core];
2179 params->pad = target.pad[core];
2180 params->ipa = target.ipa[core];
2181 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2182 (params->pad << 4) | (params->ipa);
2183 for (j = 0; j < 5; j++)
2184 params->ncorr[j] = 0x79;
2185 } else {
2186 gain = (target.pad[core]) | (target.pga[core] << 4) |
2187 (target.txgm[core] << 8);
2188
2189 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2190 1 : 0;
2191 for (i = 0; i < 9; i++)
2192 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2193 break;
2194 i = min(i, 8);
2195
2196 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2197 params->pga = tbl_iqcal_gainparams[indx][i][2];
2198 params->pad = tbl_iqcal_gainparams[indx][i][3];
2199 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2200 (params->pad << 2);
2201 for (j = 0; j < 4; j++)
2202 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2203 }
2204 }
2205
2206 /**************************************************
2207 * Tx and Rx
2208 **************************************************/
2209
2210 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
2211 {//TODO
2212 }
2213
2214 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
2215 {//TODO
2216 }
2217
2218 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
2219 bool ignore_tssi)
2220 {//TODO
2221 return B43_TXPWR_RES_DONE;
2222 }
2223
2224 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
2225 static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
2226 {
2227 struct b43_phy_n *nphy = dev->phy.n;
2228 u8 i;
2229 u16 bmask, val, tmp;
2230 enum ieee80211_band band = b43_current_band(dev->wl);
2231
2232 if (nphy->hang_avoid)
2233 b43_nphy_stay_in_carrier_search(dev, 1);
2234
2235 nphy->txpwrctrl = enable;
2236 if (!enable) {
2237 if (dev->phy.rev >= 3 &&
2238 (b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
2239 (B43_NPHY_TXPCTL_CMD_COEFF |
2240 B43_NPHY_TXPCTL_CMD_HWPCTLEN |
2241 B43_NPHY_TXPCTL_CMD_PCTLEN))) {
2242 /* We disable enabled TX pwr ctl, save it's state */
2243 nphy->tx_pwr_idx[0] = b43_phy_read(dev,
2244 B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
2245 nphy->tx_pwr_idx[1] = b43_phy_read(dev,
2246 B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
2247 }
2248
2249 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
2250 for (i = 0; i < 84; i++)
2251 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2252
2253 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6C40);
2254 for (i = 0; i < 84; i++)
2255 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0);
2256
2257 tmp = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2258 if (dev->phy.rev >= 3)
2259 tmp |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2260 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD, ~tmp);
2261
2262 if (dev->phy.rev >= 3) {
2263 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2264 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2265 } else {
2266 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2267 }
2268
2269 if (dev->phy.rev == 2)
2270 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2271 ~B43_NPHY_BPHY_CTL3_SCALE, 0x53);
2272 else if (dev->phy.rev < 2)
2273 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2274 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
2275
2276 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2277 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
2278 } else {
2279 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
2280 nphy->adj_pwr_tbl);
2281 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
2282 nphy->adj_pwr_tbl);
2283
2284 bmask = B43_NPHY_TXPCTL_CMD_COEFF |
2285 B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2286 /* wl does useless check for "enable" param here */
2287 val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
2288 if (dev->phy.rev >= 3) {
2289 bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2290 if (val)
2291 val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
2292 }
2293 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
2294
2295 if (band == IEEE80211_BAND_5GHZ) {
2296 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2297 ~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
2298 if (dev->phy.rev > 1)
2299 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2300 ~B43_NPHY_TXPCTL_INIT_PIDXI1,
2301 0x64);
2302 }
2303
2304 if (dev->phy.rev >= 3) {
2305 if (nphy->tx_pwr_idx[0] != 128 &&
2306 nphy->tx_pwr_idx[1] != 128) {
2307 /* Recover TX pwr ctl state */
2308 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2309 ~B43_NPHY_TXPCTL_CMD_INIT,
2310 nphy->tx_pwr_idx[0]);
2311 if (dev->phy.rev > 1)
2312 b43_phy_maskset(dev,
2313 B43_NPHY_TXPCTL_INIT,
2314 ~0xff, nphy->tx_pwr_idx[1]);
2315 }
2316 }
2317
2318 if (dev->phy.rev >= 3) {
2319 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
2320 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
2321 } else {
2322 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
2323 }
2324
2325 if (dev->phy.rev == 2)
2326 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
2327 else if (dev->phy.rev < 2)
2328 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
2329
2330 if (dev->phy.rev < 2 && dev->phy.is_40mhz)
2331 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
2332
2333 if (b43_nphy_ipa(dev)) {
2334 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
2335 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
2336 }
2337 }
2338
2339 if (nphy->hang_avoid)
2340 b43_nphy_stay_in_carrier_search(dev, 0);
2341 }
2342
2343 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */
2344 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
2345 {
2346 struct b43_phy_n *nphy = dev->phy.n;
2347 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2348
2349 u8 txpi[2], bbmult, i;
2350 u16 tmp, radio_gain, dac_gain;
2351 u16 freq = dev->phy.channel_freq;
2352 u32 txgain;
2353 /* u32 gaintbl; rev3+ */
2354
2355 if (nphy->hang_avoid)
2356 b43_nphy_stay_in_carrier_search(dev, 1);
2357
2358 if (dev->phy.rev >= 7) {
2359 txpi[0] = txpi[1] = 30;
2360 } else if (dev->phy.rev >= 3) {
2361 txpi[0] = 40;
2362 txpi[1] = 40;
2363 } else if (sprom->revision < 4) {
2364 txpi[0] = 72;
2365 txpi[1] = 72;
2366 } else {
2367 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2368 txpi[0] = sprom->txpid2g[0];
2369 txpi[1] = sprom->txpid2g[1];
2370 } else if (freq >= 4900 && freq < 5100) {
2371 txpi[0] = sprom->txpid5gl[0];
2372 txpi[1] = sprom->txpid5gl[1];
2373 } else if (freq >= 5100 && freq < 5500) {
2374 txpi[0] = sprom->txpid5g[0];
2375 txpi[1] = sprom->txpid5g[1];
2376 } else if (freq >= 5500) {
2377 txpi[0] = sprom->txpid5gh[0];
2378 txpi[1] = sprom->txpid5gh[1];
2379 } else {
2380 txpi[0] = 91;
2381 txpi[1] = 91;
2382 }
2383 }
2384 if (dev->phy.rev < 7 &&
2385 (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100))
2386 txpi[0] = txpi[1] = 91;
2387
2388 /*
2389 for (i = 0; i < 2; i++) {
2390 nphy->txpwrindex[i].index_internal = txpi[i];
2391 nphy->txpwrindex[i].index_internal_save = txpi[i];
2392 }
2393 */
2394
2395 for (i = 0; i < 2; i++) {
2396 txgain = *(b43_nphy_get_tx_gain_table(dev) + txpi[i]);
2397
2398 if (dev->phy.rev >= 3)
2399 radio_gain = (txgain >> 16) & 0x1FFFF;
2400 else
2401 radio_gain = (txgain >> 16) & 0x1FFF;
2402
2403 if (dev->phy.rev >= 7)
2404 dac_gain = (txgain >> 8) & 0x7;
2405 else
2406 dac_gain = (txgain >> 8) & 0x3F;
2407 bbmult = txgain & 0xFF;
2408
2409 if (dev->phy.rev >= 3) {
2410 if (i == 0)
2411 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0100);
2412 else
2413 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0100);
2414 } else {
2415 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x4000);
2416 }
2417
2418 if (i == 0)
2419 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN1, dac_gain);
2420 else
2421 b43_phy_write(dev, B43_NPHY_AFECTL_DACGAIN2, dac_gain);
2422
2423 b43_ntab_write(dev, B43_NTAB16(0x7, 0x110 + i), radio_gain);
2424
2425 tmp = b43_ntab_read(dev, B43_NTAB16(0xF, 0x57));
2426 if (i == 0)
2427 tmp = (tmp & 0x00FF) | (bbmult << 8);
2428 else
2429 tmp = (tmp & 0xFF00) | bbmult;
2430 b43_ntab_write(dev, B43_NTAB16(0xF, 0x57), tmp);
2431
2432 if (b43_nphy_ipa(dev)) {
2433 u32 tmp32;
2434 u16 reg = (i == 0) ?
2435 B43_NPHY_PAPD_EN0 : B43_NPHY_PAPD_EN1;
2436 tmp32 = b43_ntab_read(dev, B43_NTAB32(26 + i,
2437 576 + txpi[i]));
2438 b43_phy_maskset(dev, reg, 0xE00F, (u32) tmp32 << 4);
2439 b43_phy_set(dev, reg, 0x4);
2440 }
2441 }
2442
2443 b43_phy_mask(dev, B43_NPHY_BPHY_CTL2, ~B43_NPHY_BPHY_CTL2_LUT);
2444
2445 if (nphy->hang_avoid)
2446 b43_nphy_stay_in_carrier_search(dev, 0);
2447 }
2448
2449 static void b43_nphy_ipa_internal_tssi_setup(struct b43_wldev *dev)
2450 {
2451 struct b43_phy *phy = &dev->phy;
2452
2453 u8 core;
2454 u16 r; /* routing */
2455
2456 if (phy->rev >= 7) {
2457 for (core = 0; core < 2; core++) {
2458 r = core ? 0x190 : 0x170;
2459 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2460 b43_radio_write(dev, r + 0x5, 0x5);
2461 b43_radio_write(dev, r + 0x9, 0xE);
2462 if (phy->rev != 5)
2463 b43_radio_write(dev, r + 0xA, 0);
2464 if (phy->rev != 7)
2465 b43_radio_write(dev, r + 0xB, 1);
2466 else
2467 b43_radio_write(dev, r + 0xB, 0x31);
2468 } else {
2469 b43_radio_write(dev, r + 0x5, 0x9);
2470 b43_radio_write(dev, r + 0x9, 0xC);
2471 b43_radio_write(dev, r + 0xB, 0x0);
2472 if (phy->rev != 5)
2473 b43_radio_write(dev, r + 0xA, 1);
2474 else
2475 b43_radio_write(dev, r + 0xA, 0x31);
2476 }
2477 b43_radio_write(dev, r + 0x6, 0);
2478 b43_radio_write(dev, r + 0x7, 0);
2479 b43_radio_write(dev, r + 0x8, 3);
2480 b43_radio_write(dev, r + 0xC, 0);
2481 }
2482 } else {
2483 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2484 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x128);
2485 else
2486 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR31, 0x80);
2487 b43_radio_write(dev, B2056_SYN_RESERVED_ADDR30, 0);
2488 b43_radio_write(dev, B2056_SYN_GPIO_MASTER1, 0x29);
2489
2490 for (core = 0; core < 2; core++) {
2491 r = core ? B2056_TX1 : B2056_TX0;
2492
2493 b43_radio_write(dev, r | B2056_TX_IQCAL_VCM_HG, 0);
2494 b43_radio_write(dev, r | B2056_TX_IQCAL_IDAC, 0);
2495 b43_radio_write(dev, r | B2056_TX_TSSI_VCM, 3);
2496 b43_radio_write(dev, r | B2056_TX_TX_AMP_DET, 0);
2497 b43_radio_write(dev, r | B2056_TX_TSSI_MISC1, 8);
2498 b43_radio_write(dev, r | B2056_TX_TSSI_MISC2, 0);
2499 b43_radio_write(dev, r | B2056_TX_TSSI_MISC3, 0);
2500 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2501 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
2502 0x5);
2503 if (phy->rev != 5)
2504 b43_radio_write(dev, r | B2056_TX_TSSIA,
2505 0x00);
2506 if (phy->rev >= 5)
2507 b43_radio_write(dev, r | B2056_TX_TSSIG,
2508 0x31);
2509 else
2510 b43_radio_write(dev, r | B2056_TX_TSSIG,
2511 0x11);
2512 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
2513 0xE);
2514 } else {
2515 b43_radio_write(dev, r | B2056_TX_TX_SSI_MASTER,
2516 0x9);
2517 b43_radio_write(dev, r | B2056_TX_TSSIA, 0x31);
2518 b43_radio_write(dev, r | B2056_TX_TSSIG, 0x0);
2519 b43_radio_write(dev, r | B2056_TX_TX_SSI_MUX,
2520 0xC);
2521 }
2522 }
2523 }
2524 }
2525
2526 /*
2527 * Stop radio and transmit known signal. Then check received signal strength to
2528 * get TSSI (Transmit Signal Strength Indicator).
2529 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi
2530 */
2531 static void b43_nphy_tx_power_ctl_idle_tssi(struct b43_wldev *dev)
2532 {
2533 struct b43_phy *phy = &dev->phy;
2534 struct b43_phy_n *nphy = dev->phy.n;
2535
2536 u32 tmp;
2537 s32 rssi[4] = { };
2538
2539 /* TODO: check if we can transmit */
2540
2541 if (b43_nphy_ipa(dev))
2542 b43_nphy_ipa_internal_tssi_setup(dev);
2543
2544 if (phy->rev >= 7)
2545 ; /* TODO: Override Rev7 with 0x2000, 0, 3, 0, 0 as arguments */
2546 else if (phy->rev >= 3)
2547 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, false);
2548
2549 b43_nphy_stop_playback(dev);
2550 b43_nphy_tx_tone(dev, 0xFA0, 0, false, false);
2551 udelay(20);
2552 tmp = b43_nphy_poll_rssi(dev, 4, rssi, 1);
2553 b43_nphy_stop_playback(dev);
2554 b43_nphy_rssi_select(dev, 0, 0);
2555
2556 if (phy->rev >= 7)
2557 ; /* TODO: Override Rev7 with 0x2000, 0, 3, 1, 0 as arguments */
2558 else if (phy->rev >= 3)
2559 b43_nphy_rf_control_override(dev, 0x2000, 0, 3, true);
2560
2561 if (phy->rev >= 3) {
2562 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF;
2563 nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF;
2564 } else {
2565 nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF;
2566 nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF;
2567 }
2568 nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF;
2569 nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF;
2570 }
2571
2572 /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */
2573 static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
2574 {
2575 struct b43_phy_n *nphy = dev->phy.n;
2576
2577 u8 idx, delta;
2578 u8 i, stf_mode;
2579
2580 for (i = 0; i < 4; i++)
2581 nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i];
2582
2583 for (stf_mode = 0; stf_mode < 4; stf_mode++) {
2584 delta = 0;
2585 switch (stf_mode) {
2586 case 0:
2587 if (dev->phy.is_40mhz && dev->phy.rev >= 5) {
2588 idx = 68;
2589 } else {
2590 delta = 1;
2591 idx = dev->phy.is_40mhz ? 52 : 4;
2592 }
2593 break;
2594 case 1:
2595 idx = dev->phy.is_40mhz ? 76 : 28;
2596 break;
2597 case 2:
2598 idx = dev->phy.is_40mhz ? 84 : 36;
2599 break;
2600 case 3:
2601 idx = dev->phy.is_40mhz ? 92 : 44;
2602 break;
2603 }
2604
2605 for (i = 0; i < 20; i++) {
2606 nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] =
2607 nphy->tx_power_offset[idx];
2608 if (i == 0)
2609 idx += delta;
2610 if (i == 14)
2611 idx += 1 - delta;
2612 if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 ||
2613 i == 13)
2614 idx += 1;
2615 }
2616 }
2617 }
2618
2619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */
2620 static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
2621 {
2622 struct b43_phy_n *nphy = dev->phy.n;
2623 struct ssb_sprom *sprom = dev->dev->bus_sprom;
2624
2625 s16 a1[2], b0[2], b1[2];
2626 u8 idle[2];
2627 s8 target[2];
2628 s32 num, den, pwr;
2629 u32 regval[64];
2630
2631 u16 freq = dev->phy.channel_freq;
2632 u16 tmp;
2633 u16 r; /* routing */
2634 u8 i, c;
2635
2636 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
2637 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
2638 b43_read32(dev, B43_MMIO_MACCTL);
2639 udelay(1);
2640 }
2641
2642 if (nphy->hang_avoid)
2643 b43_nphy_stay_in_carrier_search(dev, true);
2644
2645 b43_phy_set(dev, B43_NPHY_TSSIMODE, B43_NPHY_TSSIMODE_EN);
2646 if (dev->phy.rev >= 3)
2647 b43_phy_mask(dev, B43_NPHY_TXPCTL_CMD,
2648 ~B43_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF);
2649 else
2650 b43_phy_set(dev, B43_NPHY_TXPCTL_CMD,
2651 B43_NPHY_TXPCTL_CMD_PCTLEN);
2652
2653 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
2654 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
2655
2656 if (sprom->revision < 4) {
2657 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g;
2658 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g;
2659 target[0] = target[1] = 52;
2660 a1[0] = a1[1] = -424;
2661 b0[0] = b0[1] = 5612;
2662 b1[0] = b1[1] = -1393;
2663 } else {
2664 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2665 for (c = 0; c < 2; c++) {
2666 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g;
2667 target[c] = sprom->core_pwr_info[c].maxpwr_2g;
2668 a1[c] = sprom->core_pwr_info[c].pa_2g[0];
2669 b0[c] = sprom->core_pwr_info[c].pa_2g[1];
2670 b1[c] = sprom->core_pwr_info[c].pa_2g[2];
2671 }
2672 } else if (freq >= 4900 && freq < 5100) {
2673 for (c = 0; c < 2; c++) {
2674 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
2675 target[c] = sprom->core_pwr_info[c].maxpwr_5gl;
2676 a1[c] = sprom->core_pwr_info[c].pa_5gl[0];
2677 b0[c] = sprom->core_pwr_info[c].pa_5gl[1];
2678 b1[c] = sprom->core_pwr_info[c].pa_5gl[2];
2679 }
2680 } else if (freq >= 5100 && freq < 5500) {
2681 for (c = 0; c < 2; c++) {
2682 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
2683 target[c] = sprom->core_pwr_info[c].maxpwr_5g;
2684 a1[c] = sprom->core_pwr_info[c].pa_5g[0];
2685 b0[c] = sprom->core_pwr_info[c].pa_5g[1];
2686 b1[c] = sprom->core_pwr_info[c].pa_5g[2];
2687 }
2688 } else if (freq >= 5500) {
2689 for (c = 0; c < 2; c++) {
2690 idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g;
2691 target[c] = sprom->core_pwr_info[c].maxpwr_5gh;
2692 a1[c] = sprom->core_pwr_info[c].pa_5gh[0];
2693 b0[c] = sprom->core_pwr_info[c].pa_5gh[1];
2694 b1[c] = sprom->core_pwr_info[c].pa_5gh[2];
2695 }
2696 } else {
2697 idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g;
2698 idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g;
2699 target[0] = target[1] = 52;
2700 a1[0] = a1[1] = -424;
2701 b0[0] = b0[1] = 5612;
2702 b1[0] = b1[1] = -1393;
2703 }
2704 }
2705 /* target[0] = target[1] = nphy->tx_power_max; */
2706
2707 if (dev->phy.rev >= 3) {
2708 if (sprom->fem.ghz2.tssipos)
2709 b43_phy_set(dev, B43_NPHY_TXPCTL_ITSSI, 0x4000);
2710 if (dev->phy.rev >= 7) {
2711 for (c = 0; c < 2; c++) {
2712 r = c ? 0x190 : 0x170;
2713 if (b43_nphy_ipa(dev))
2714 b43_radio_write(dev, r + 0x9, (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) ? 0xE : 0xC);
2715 }
2716 } else {
2717 if (b43_nphy_ipa(dev)) {
2718 tmp = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
2719 b43_radio_write(dev,
2720 B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp);
2721 b43_radio_write(dev,
2722 B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp);
2723 } else {
2724 b43_radio_write(dev,
2725 B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11);
2726 b43_radio_write(dev,
2727 B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11);
2728 }
2729 }
2730 }
2731
2732 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
2733 b43_maskset32(dev, B43_MMIO_MACCTL, ~0, 0x200000);
2734 b43_read32(dev, B43_MMIO_MACCTL);
2735 udelay(1);
2736 }
2737
2738 if (dev->phy.rev >= 7) {
2739 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2740 ~B43_NPHY_TXPCTL_CMD_INIT, 0x19);
2741 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2742 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x19);
2743 } else {
2744 b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
2745 ~B43_NPHY_TXPCTL_CMD_INIT, 0x40);
2746 if (dev->phy.rev > 1)
2747 b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
2748 ~B43_NPHY_TXPCTL_INIT_PIDXI1, 0x40);
2749 }
2750
2751 if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
2752 b43_maskset32(dev, B43_MMIO_MACCTL, ~0x200000, 0);
2753
2754 b43_phy_write(dev, B43_NPHY_TXPCTL_N,
2755 0xF0 << B43_NPHY_TXPCTL_N_TSSID_SHIFT |
2756 3 << B43_NPHY_TXPCTL_N_NPTIL2_SHIFT);
2757 b43_phy_write(dev, B43_NPHY_TXPCTL_ITSSI,
2758 idle[0] << B43_NPHY_TXPCTL_ITSSI_0_SHIFT |
2759 idle[1] << B43_NPHY_TXPCTL_ITSSI_1_SHIFT |
2760 B43_NPHY_TXPCTL_ITSSI_BINF);
2761 b43_phy_write(dev, B43_NPHY_TXPCTL_TPWR,
2762 target[0] << B43_NPHY_TXPCTL_TPWR_0_SHIFT |
2763 target[1] << B43_NPHY_TXPCTL_TPWR_1_SHIFT);
2764
2765 for (c = 0; c < 2; c++) {
2766 for (i = 0; i < 64; i++) {
2767 num = 8 * (16 * b0[c] + b1[c] * i);
2768 den = 32768 + a1[c] * i;
2769 pwr = max((4 * num + den / 2) / den, -8);
2770 if (dev->phy.rev < 3 && (i <= (31 - idle[c] + 1)))
2771 pwr = max(pwr, target[c] + 1);
2772 regval[i] = pwr;
2773 }
2774 b43_ntab_write_bulk(dev, B43_NTAB32(26 + c, 0), 64, regval);
2775 }
2776
2777 b43_nphy_tx_prepare_adjusted_power_table(dev);
2778 /*
2779 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, nphy->adj_pwr_tbl);
2780 b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84, nphy->adj_pwr_tbl);
2781 */
2782
2783 if (nphy->hang_avoid)
2784 b43_nphy_stay_in_carrier_search(dev, false);
2785 }
2786
2787 static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
2788 {
2789 struct b43_phy *phy = &dev->phy;
2790
2791 const u32 *table = NULL;
2792 u32 rfpwr_offset;
2793 u8 pga_gain;
2794 int i;
2795
2796 table = b43_nphy_get_tx_gain_table(dev);
2797 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128, table);
2798 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128, table);
2799
2800 if (phy->rev >= 3) {
2801 #if 0
2802 nphy->gmval = (table[0] >> 16) & 0x7000;
2803 #endif
2804
2805 for (i = 0; i < 128; i++) {
2806 pga_gain = (table[i] >> 24) & 0xF;
2807 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2808 rfpwr_offset =
2809 b43_ntab_papd_pga_gain_delta_ipa_2g[pga_gain];
2810 else
2811 rfpwr_offset =
2812 0; /* FIXME */
2813 b43_ntab_write(dev, B43_NTAB32(26, 576 + i),
2814 rfpwr_offset);
2815 b43_ntab_write(dev, B43_NTAB32(27, 576 + i),
2816 rfpwr_offset);
2817 }
2818 }
2819 }
2820
2821 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
2822 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
2823 {
2824 struct b43_phy_n *nphy = dev->phy.n;
2825 enum ieee80211_band band;
2826 u16 tmp;
2827
2828 if (!enable) {
2829 nphy->rfctrl_intc1_save = b43_phy_read(dev,
2830 B43_NPHY_RFCTL_INTC1);
2831 nphy->rfctrl_intc2_save = b43_phy_read(dev,
2832 B43_NPHY_RFCTL_INTC2);
2833 band = b43_current_band(dev->wl);
2834 if (dev->phy.rev >= 3) {
2835 if (band == IEEE80211_BAND_5GHZ)
2836 tmp = 0x600;
2837 else
2838 tmp = 0x480;
2839 } else {
2840 if (band == IEEE80211_BAND_5GHZ)
2841 tmp = 0x180;
2842 else
2843 tmp = 0x120;
2844 }
2845 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2846 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2847 } else {
2848 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
2849 nphy->rfctrl_intc1_save);
2850 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
2851 nphy->rfctrl_intc2_save);
2852 }
2853 }
2854
2855 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
2856 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
2857 {
2858 u16 tmp;
2859
2860 if (dev->phy.rev >= 3) {
2861 if (b43_nphy_ipa(dev)) {
2862 tmp = 4;
2863 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
2864 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
2865 }
2866
2867 tmp = 1;
2868 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
2869 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
2870 }
2871 }
2872
2873 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
2874 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
2875 u16 samps, u8 time, bool wait)
2876 {
2877 int i;
2878 u16 tmp;
2879
2880 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
2881 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
2882 if (wait)
2883 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
2884 else
2885 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
2886
2887 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
2888
2889 for (i = 1000; i; i--) {
2890 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
2891 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
2892 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
2893 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
2894 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
2895 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
2896 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
2897 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
2898
2899 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
2900 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
2901 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
2902 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
2903 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
2904 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
2905 return;
2906 }
2907 udelay(10);
2908 }
2909 memset(est, 0, sizeof(*est));
2910 }
2911
2912 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
2913 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
2914 struct b43_phy_n_iq_comp *pcomp)
2915 {
2916 if (write) {
2917 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
2918 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
2919 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
2920 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
2921 } else {
2922 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
2923 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
2924 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
2925 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
2926 }
2927 }
2928
2929 #if 0
2930 /* Ready but not used anywhere */
2931 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
2932 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
2933 {
2934 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2935
2936 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
2937 if (core == 0) {
2938 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
2939 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2940 } else {
2941 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2942 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2943 }
2944 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
2945 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
2946 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
2947 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
2948 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
2949 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
2950 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2951 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2952 }
2953
2954 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
2955 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
2956 {
2957 u8 rxval, txval;
2958 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2959
2960 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2961 if (core == 0) {
2962 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2963 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2964 } else {
2965 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2966 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2967 }
2968 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2969 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2970 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
2971 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
2972 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
2973 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
2974 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2975 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2976
2977 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2978 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2979
2980 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2981 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
2982 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2983 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2984 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
2985 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
2986 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
2987 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
2988 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
2989
2990 if (core == 0) {
2991 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
2992 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
2993 } else {
2994 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
2995 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
2996 }
2997
2998 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
2999 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
3000 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3001
3002 if (core == 0) {
3003 rxval = 1;
3004 txval = 8;
3005 } else {
3006 rxval = 4;
3007 txval = 2;
3008 }
3009 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
3010 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
3011 }
3012 #endif
3013
3014 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
3015 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
3016 {
3017 int i;
3018 s32 iq;
3019 u32 ii;
3020 u32 qq;
3021 int iq_nbits, qq_nbits;
3022 int arsh, brsh;
3023 u16 tmp, a, b;
3024
3025 struct nphy_iq_est est;
3026 struct b43_phy_n_iq_comp old;
3027 struct b43_phy_n_iq_comp new = { };
3028 bool error = false;
3029
3030 if (mask == 0)
3031 return;
3032
3033 b43_nphy_rx_iq_coeffs(dev, false, &old);
3034 b43_nphy_rx_iq_coeffs(dev, true, &new);
3035 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
3036 new = old;
3037
3038 for (i = 0; i < 2; i++) {
3039 if (i == 0 && (mask & 1)) {
3040 iq = est.iq0_prod;
3041 ii = est.i0_pwr;
3042 qq = est.q0_pwr;
3043 } else if (i == 1 && (mask & 2)) {
3044 iq = est.iq1_prod;
3045 ii = est.i1_pwr;
3046 qq = est.q1_pwr;
3047 } else {
3048 continue;
3049 }
3050
3051 if (ii + qq < 2) {
3052 error = true;
3053 break;
3054 }
3055
3056 iq_nbits = fls(abs(iq));
3057 qq_nbits = fls(qq);
3058
3059 arsh = iq_nbits - 20;
3060 if (arsh >= 0) {
3061 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
3062 tmp = ii >> arsh;
3063 } else {
3064 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
3065 tmp = ii << -arsh;
3066 }
3067 if (tmp == 0) {
3068 error = true;
3069 break;
3070 }
3071 a /= tmp;
3072
3073 brsh = qq_nbits - 11;
3074 if (brsh >= 0) {
3075 b = (qq << (31 - qq_nbits));
3076 tmp = ii >> brsh;
3077 } else {
3078 b = (qq << (31 - qq_nbits));
3079 tmp = ii << -brsh;
3080 }
3081 if (tmp == 0) {
3082 error = true;
3083 break;
3084 }
3085 b = int_sqrt(b / tmp - a * a) - (1 << 10);
3086
3087 if (i == 0 && (mask & 0x1)) {
3088 if (dev->phy.rev >= 3) {
3089 new.a0 = a & 0x3FF;
3090 new.b0 = b & 0x3FF;
3091 } else {
3092 new.a0 = b & 0x3FF;
3093 new.b0 = a & 0x3FF;
3094 }
3095 } else if (i == 1 && (mask & 0x2)) {
3096 if (dev->phy.rev >= 3) {
3097 new.a1 = a & 0x3FF;
3098 new.b1 = b & 0x3FF;
3099 } else {
3100 new.a1 = b & 0x3FF;
3101 new.b1 = a & 0x3FF;
3102 }
3103 }
3104 }
3105
3106 if (error)
3107 new = old;
3108
3109 b43_nphy_rx_iq_coeffs(dev, true, &new);
3110 }
3111
3112 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
3113 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
3114 {
3115 u16 array[4];
3116 b43_ntab_read_bulk(dev, B43_NTAB16(0xF, 0x50), 4, array);
3117
3118 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
3119 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
3120 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
3121 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
3122 }
3123
3124 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
3125 static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3126 {
3127 struct b43_phy_n *nphy = dev->phy.n;
3128
3129 u8 channel = dev->phy.channel;
3130 int tone[2] = { 57, 58 };
3131 u32 noise[2] = { 0x3FF, 0x3FF };
3132
3133 B43_WARN_ON(dev->phy.rev < 3);
3134
3135 if (nphy->hang_avoid)
3136 b43_nphy_stay_in_carrier_search(dev, 1);
3137
3138 if (nphy->gband_spurwar_en) {
3139 /* TODO: N PHY Adjust Analog Pfbw (7) */
3140 if (channel == 11 && dev->phy.is_40mhz)
3141 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
3142 else
3143 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3144 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
3145 }
3146
3147 if (nphy->aband_spurwar_en) {
3148 if (channel == 54) {
3149 tone[0] = 0x20;
3150 noise[0] = 0x25F;
3151 } else if (channel == 38 || channel == 102 || channel == 118) {
3152 if (0 /* FIXME */) {
3153 tone[0] = 0x20;
3154 noise[0] = 0x21F;
3155 } else {
3156 tone[0] = 0;
3157 noise[0] = 0;
3158 }
3159 } else if (channel == 134) {
3160 tone[0] = 0x20;
3161 noise[0] = 0x21F;
3162 } else if (channel == 151) {
3163 tone[0] = 0x10;
3164 noise[0] = 0x23F;
3165 } else if (channel == 153 || channel == 161) {
3166 tone[0] = 0x30;
3167 noise[0] = 0x23F;
3168 } else {
3169 tone[0] = 0;
3170 noise[0] = 0;
3171 }
3172
3173 if (!tone[0] && !noise[0])
3174 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
3175 else
3176 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
3177 }
3178
3179 if (nphy->hang_avoid)
3180 b43_nphy_stay_in_carrier_search(dev, 0);
3181 }
3182
3183 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
3184 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
3185 {
3186 struct b43_phy_n *nphy = dev->phy.n;
3187 int i, j;
3188 u32 tmp;
3189 u32 cur_real, cur_imag, real_part, imag_part;
3190
3191 u16 buffer[7];
3192
3193 if (nphy->hang_avoid)
3194 b43_nphy_stay_in_carrier_search(dev, true);
3195
3196 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3197
3198 for (i = 0; i < 2; i++) {
3199 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
3200 (buffer[i * 2 + 1] & 0x3FF);
3201 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3202 (((i + 26) << 10) | 320));
3203 for (j = 0; j < 128; j++) {
3204 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3205 ((tmp >> 16) & 0xFFFF));
3206 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3207 (tmp & 0xFFFF));
3208 }
3209 }
3210
3211 for (i = 0; i < 2; i++) {
3212 tmp = buffer[5 + i];
3213 real_part = (tmp >> 8) & 0xFF;
3214 imag_part = (tmp & 0xFF);
3215 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
3216 (((i + 26) << 10) | 448));
3217
3218 if (dev->phy.rev >= 3) {
3219 cur_real = real_part;
3220 cur_imag = imag_part;
3221 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
3222 }
3223
3224 for (j = 0; j < 128; j++) {
3225 if (dev->phy.rev < 3) {
3226 cur_real = (real_part * loscale[j] + 128) >> 8;
3227 cur_imag = (imag_part * loscale[j] + 128) >> 8;
3228 tmp = ((cur_real & 0xFF) << 8) |
3229 (cur_imag & 0xFF);
3230 }
3231 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
3232 ((tmp >> 16) & 0xFFFF));
3233 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
3234 (tmp & 0xFFFF));
3235 }
3236 }
3237
3238 if (dev->phy.rev >= 3) {
3239 b43_shm_write16(dev, B43_SHM_SHARED,
3240 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
3241 b43_shm_write16(dev, B43_SHM_SHARED,
3242 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
3243 }
3244
3245 if (nphy->hang_avoid)
3246 b43_nphy_stay_in_carrier_search(dev, false);
3247 }
3248
3249 /*
3250 * Restore RSSI Calibration
3251 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
3252 */
3253 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
3254 {
3255 struct b43_phy_n *nphy = dev->phy.n;
3256
3257 u16 *rssical_radio_regs = NULL;
3258 u16 *rssical_phy_regs = NULL;
3259
3260 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3261 if (!nphy->rssical_chanspec_2G.center_freq)
3262 return;
3263 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
3264 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
3265 } else {
3266 if (!nphy->rssical_chanspec_5G.center_freq)
3267 return;
3268 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
3269 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
3270 }
3271
3272 /* TODO use some definitions */
3273 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
3274 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
3275
3276 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
3277 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
3278 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
3279 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
3280
3281 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
3282 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
3283 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
3284 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
3285
3286 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
3287 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
3288 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
3289 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
3290 }
3291
3292 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
3293 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3294 {
3295 struct b43_phy_n *nphy = dev->phy.n;
3296 u16 *save = nphy->tx_rx_cal_radio_saveregs;
3297 u16 tmp;
3298 u8 offset, i;
3299
3300 if (dev->phy.rev >= 3) {
3301 for (i = 0; i < 2; i++) {
3302 tmp = (i == 0) ? 0x2000 : 0x3000;
3303 offset = i * 11;
3304
3305 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
3306 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
3307 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
3308 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
3309 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
3310 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
3311 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
3312 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
3313 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
3314 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
3315 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
3316
3317 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3318 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3319 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3320 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3321 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3322 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3323 if (nphy->ipa5g_on) {
3324 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
3325 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
3326 } else {
3327 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3328 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
3329 }
3330 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3331 } else {
3332 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3333 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3334 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
3335 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
3336 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
3337 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
3338 if (nphy->ipa2g_on) {
3339 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
3340 b43_radio_write16(dev, tmp | B2055_XOCTL2,
3341 (dev->phy.rev < 5) ? 0x11 : 0x01);
3342 } else {
3343 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
3344 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
3345 }
3346 }
3347 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
3348 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
3349 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
3350 }
3351 } else {
3352 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
3353 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3354
3355 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
3356 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3357
3358 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
3359 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3360
3361 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
3362 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
3363
3364 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
3365 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
3366
3367 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
3368 B43_NPHY_BANDCTL_5GHZ)) {
3369 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
3370 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
3371 } else {
3372 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
3373 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
3374 }
3375
3376 if (dev->phy.rev < 2) {
3377 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
3378 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
3379 } else {
3380 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
3381 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
3382 }
3383 }
3384 }
3385
3386 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
3387 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
3388 {
3389 struct b43_phy_n *nphy = dev->phy.n;
3390 int i;
3391 u16 scale, entry;
3392
3393 u16 tmp = nphy->txcal_bbmult;
3394 if (core == 0)
3395 tmp >>= 8;
3396 tmp &= 0xff;
3397
3398 for (i = 0; i < 18; i++) {
3399 scale = (ladder_lo[i].percent * tmp) / 100;
3400 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
3401 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
3402
3403 scale = (ladder_iq[i].percent * tmp) / 100;
3404 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
3405 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
3406 }
3407 }
3408
3409 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
3410 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
3411 {
3412 int i;
3413 for (i = 0; i < 15; i++)
3414 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
3415 tbl_tx_filter_coef_rev4[2][i]);
3416 }
3417
3418 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
3419 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
3420 {
3421 int i, j;
3422 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
3423 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
3424
3425 for (i = 0; i < 3; i++)
3426 for (j = 0; j < 15; j++)
3427 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
3428 tbl_tx_filter_coef_rev4[i][j]);
3429
3430 if (dev->phy.is_40mhz) {
3431 for (j = 0; j < 15; j++)
3432 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3433 tbl_tx_filter_coef_rev4[3][j]);
3434 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3435 for (j = 0; j < 15; j++)
3436 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3437 tbl_tx_filter_coef_rev4[5][j]);
3438 }
3439
3440 if (dev->phy.channel == 14)
3441 for (j = 0; j < 15; j++)
3442 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
3443 tbl_tx_filter_coef_rev4[6][j]);
3444 }
3445
3446 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
3447 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
3448 {
3449 struct b43_phy_n *nphy = dev->phy.n;
3450
3451 u16 curr_gain[2];
3452 struct nphy_txgains target;
3453 const u32 *table = NULL;
3454
3455 if (!nphy->txpwrctrl) {
3456 int i;
3457
3458 if (nphy->hang_avoid)
3459 b43_nphy_stay_in_carrier_search(dev, true);
3460 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
3461 if (nphy->hang_avoid)
3462 b43_nphy_stay_in_carrier_search(dev, false);
3463
3464 for (i = 0; i < 2; ++i) {
3465 if (dev->phy.rev >= 3) {
3466 target.ipa[i] = curr_gain[i] & 0x000F;
3467 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
3468 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
3469 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
3470 } else {
3471 target.ipa[i] = curr_gain[i] & 0x0003;
3472 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
3473 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
3474 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
3475 }
3476 }
3477 } else {
3478 int i;
3479 u16 index[2];
3480 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
3481 B43_NPHY_TXPCTL_STAT_BIDX) >>
3482 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3483 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
3484 B43_NPHY_TXPCTL_STAT_BIDX) >>
3485 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
3486
3487 for (i = 0; i < 2; ++i) {
3488 table = b43_nphy_get_tx_gain_table(dev);
3489 if (dev->phy.rev >= 3) {
3490 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
3491 target.pad[i] = (table[index[i]] >> 20) & 0xF;
3492 target.pga[i] = (table[index[i]] >> 24) & 0xF;
3493 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
3494 } else {
3495 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
3496 target.pad[i] = (table[index[i]] >> 18) & 0x3;
3497 target.pga[i] = (table[index[i]] >> 20) & 0x7;
3498 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
3499 }
3500 }
3501 }
3502
3503 return target;
3504 }
3505
3506 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
3507 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
3508 {
3509 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3510
3511 if (dev->phy.rev >= 3) {
3512 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
3513 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
3514 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
3515 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
3516 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
3517 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
3518 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
3519 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
3520 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
3521 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
3522 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
3523 b43_nphy_reset_cca(dev);
3524 } else {
3525 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
3526 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
3527 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
3528 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
3529 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
3530 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
3531 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
3532 }
3533 }
3534
3535 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
3536 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
3537 {
3538 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
3539 u16 tmp;
3540
3541 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
3542 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
3543 if (dev->phy.rev >= 3) {
3544 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
3545 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
3546
3547 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
3548 regs[2] = tmp;
3549 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
3550
3551 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3552 regs[3] = tmp;
3553 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
3554
3555 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
3556 b43_phy_mask(dev, B43_NPHY_BBCFG,
3557 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
3558
3559 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
3560 regs[5] = tmp;
3561 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
3562
3563 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
3564 regs[6] = tmp;
3565 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
3566 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3567 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3568
3569 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
3570 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
3571 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
3572
3573 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
3574 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
3575 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
3576 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
3577 } else {
3578 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
3579 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
3580 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
3581 regs[2] = tmp;
3582 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
3583 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
3584 regs[3] = tmp;
3585 tmp |= 0x2000;
3586 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
3587 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
3588 regs[4] = tmp;
3589 tmp |= 0x2000;
3590 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
3591 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
3592 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
3593 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
3594 tmp = 0x0180;
3595 else
3596 tmp = 0x0120;
3597 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
3598 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
3599 }
3600 }
3601
3602 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
3603 static void b43_nphy_save_cal(struct b43_wldev *dev)
3604 {
3605 struct b43_phy_n *nphy = dev->phy.n;
3606
3607 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3608 u16 *txcal_radio_regs = NULL;
3609 struct b43_chanspec *iqcal_chanspec;
3610 u16 *table = NULL;
3611
3612 if (nphy->hang_avoid)
3613 b43_nphy_stay_in_carrier_search(dev, 1);
3614
3615 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3616 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3617 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3618 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
3619 table = nphy->cal_cache.txcal_coeffs_2G;
3620 } else {
3621 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3622 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3623 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
3624 table = nphy->cal_cache.txcal_coeffs_5G;
3625 }
3626
3627 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
3628 /* TODO use some definitions */
3629 if (dev->phy.rev >= 3) {
3630 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
3631 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
3632 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
3633 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
3634 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
3635 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
3636 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
3637 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
3638 } else {
3639 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
3640 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
3641 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
3642 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
3643 }
3644 iqcal_chanspec->center_freq = dev->phy.channel_freq;
3645 iqcal_chanspec->channel_type = dev->phy.channel_type;
3646 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
3647
3648 if (nphy->hang_avoid)
3649 b43_nphy_stay_in_carrier_search(dev, 0);
3650 }
3651
3652 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
3653 static void b43_nphy_restore_cal(struct b43_wldev *dev)
3654 {
3655 struct b43_phy_n *nphy = dev->phy.n;
3656
3657 u16 coef[4];
3658 u16 *loft = NULL;
3659 u16 *table = NULL;
3660
3661 int i;
3662 u16 *txcal_radio_regs = NULL;
3663 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
3664
3665 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3666 if (!nphy->iqcal_chanspec_2G.center_freq)
3667 return;
3668 table = nphy->cal_cache.txcal_coeffs_2G;
3669 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
3670 } else {
3671 if (!nphy->iqcal_chanspec_5G.center_freq)
3672 return;
3673 table = nphy->cal_cache.txcal_coeffs_5G;
3674 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
3675 }
3676
3677 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
3678
3679 for (i = 0; i < 4; i++) {
3680 if (dev->phy.rev >= 3)
3681 table[i] = coef[i];
3682 else
3683 coef[i] = 0;
3684 }
3685
3686 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
3687 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
3688 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
3689
3690 if (dev->phy.rev < 2)
3691 b43_nphy_tx_iq_workaround(dev);
3692
3693 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3694 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
3695 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
3696 } else {
3697 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
3698 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
3699 }
3700
3701 /* TODO use some definitions */
3702 if (dev->phy.rev >= 3) {
3703 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
3704 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
3705 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
3706 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
3707 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
3708 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
3709 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
3710 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
3711 } else {
3712 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
3713 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
3714 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
3715 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
3716 }
3717 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
3718 }
3719
3720 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
3721 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
3722 struct nphy_txgains target,
3723 bool full, bool mphase)
3724 {
3725 struct b43_phy_n *nphy = dev->phy.n;
3726 int i;
3727 int error = 0;
3728 int freq;
3729 bool avoid = false;
3730 u8 length;
3731 u16 tmp, core, type, count, max, numb, last = 0, cmd;
3732 const u16 *table;
3733 bool phy6or5x;
3734
3735 u16 buffer[11];
3736 u16 diq_start = 0;
3737 u16 save[2];
3738 u16 gain[2];
3739 struct nphy_iqcal_params params[2];
3740 bool updated[2] = { };
3741
3742 b43_nphy_stay_in_carrier_search(dev, true);
3743
3744 if (dev->phy.rev >= 4) {
3745 avoid = nphy->hang_avoid;
3746 nphy->hang_avoid = false;
3747 }
3748
3749 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3750
3751 for (i = 0; i < 2; i++) {
3752 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
3753 gain[i] = params[i].cal_gain;
3754 }
3755
3756 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
3757
3758 b43_nphy_tx_cal_radio_setup(dev);
3759 b43_nphy_tx_cal_phy_setup(dev);
3760
3761 phy6or5x = dev->phy.rev >= 6 ||
3762 (dev->phy.rev == 5 && nphy->ipa2g_on &&
3763 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
3764 if (phy6or5x) {
3765 if (dev->phy.is_40mhz) {
3766 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3767 tbl_tx_iqlo_cal_loft_ladder_40);
3768 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3769 tbl_tx_iqlo_cal_iqimb_ladder_40);
3770 } else {
3771 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
3772 tbl_tx_iqlo_cal_loft_ladder_20);
3773 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
3774 tbl_tx_iqlo_cal_iqimb_ladder_20);
3775 }
3776 }
3777
3778 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
3779
3780 if (!dev->phy.is_40mhz)
3781 freq = 2500;
3782 else
3783 freq = 5000;
3784
3785 if (nphy->mphase_cal_phase_id > 2)
3786 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
3787 0xFFFF, 0, true, false);
3788 else
3789 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
3790
3791 if (error == 0) {
3792 if (nphy->mphase_cal_phase_id > 2) {
3793 table = nphy->mphase_txcal_bestcoeffs;
3794 length = 11;
3795 if (dev->phy.rev < 3)
3796 length -= 2;
3797 } else {
3798 if (!full && nphy->txiqlocal_coeffsvalid) {
3799 table = nphy->txiqlocal_bestc;
3800 length = 11;
3801 if (dev->phy.rev < 3)
3802 length -= 2;
3803 } else {
3804 full = true;
3805 if (dev->phy.rev >= 3) {
3806 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
3807 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
3808 } else {
3809 table = tbl_tx_iqlo_cal_startcoefs;
3810 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
3811 }
3812 }
3813 }
3814
3815 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
3816
3817 if (full) {
3818 if (dev->phy.rev >= 3)
3819 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
3820 else
3821 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
3822 } else {
3823 if (dev->phy.rev >= 3)
3824 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
3825 else
3826 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
3827 }
3828
3829 if (mphase) {
3830 count = nphy->mphase_txcal_cmdidx;
3831 numb = min(max,
3832 (u16)(count + nphy->mphase_txcal_numcmds));
3833 } else {
3834 count = 0;
3835 numb = max;
3836 }
3837
3838 for (; count < numb; count++) {
3839 if (full) {
3840 if (dev->phy.rev >= 3)
3841 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
3842 else
3843 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
3844 } else {
3845 if (dev->phy.rev >= 3)
3846 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
3847 else
3848 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
3849 }
3850
3851 core = (cmd & 0x3000) >> 12;
3852 type = (cmd & 0x0F00) >> 8;
3853
3854 if (phy6or5x && updated[core] == 0) {
3855 b43_nphy_update_tx_cal_ladder(dev, core);
3856 updated[core] = true;
3857 }
3858
3859 tmp = (params[core].ncorr[type] << 8) | 0x66;
3860 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
3861
3862 if (type == 1 || type == 3 || type == 4) {
3863 buffer[0] = b43_ntab_read(dev,
3864 B43_NTAB16(15, 69 + core));
3865 diq_start = buffer[0];
3866 buffer[0] = 0;
3867 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
3868 0);
3869 }
3870
3871 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
3872 for (i = 0; i < 2000; i++) {
3873 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
3874 if (tmp & 0xC000)
3875 break;
3876 udelay(10);
3877 }
3878
3879 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3880 buffer);
3881 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
3882 buffer);
3883
3884 if (type == 1 || type == 3 || type == 4)
3885 buffer[0] = diq_start;
3886 }
3887
3888 if (mphase)
3889 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
3890
3891 last = (dev->phy.rev < 3) ? 6 : 7;
3892
3893 if (!mphase || nphy->mphase_cal_phase_id == last) {
3894 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
3895 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
3896 if (dev->phy.rev < 3) {
3897 buffer[0] = 0;
3898 buffer[1] = 0;
3899 buffer[2] = 0;
3900 buffer[3] = 0;
3901 }
3902 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3903 buffer);
3904 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
3905 buffer);
3906 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3907 buffer);
3908 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3909 buffer);
3910 length = 11;
3911 if (dev->phy.rev < 3)
3912 length -= 2;
3913 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3914 nphy->txiqlocal_bestc);
3915 nphy->txiqlocal_coeffsvalid = true;
3916 nphy->txiqlocal_chanspec.center_freq =
3917 dev->phy.channel_freq;
3918 nphy->txiqlocal_chanspec.channel_type =
3919 dev->phy.channel_type;
3920 } else {
3921 length = 11;
3922 if (dev->phy.rev < 3)
3923 length -= 2;
3924 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
3925 nphy->mphase_txcal_bestcoeffs);
3926 }
3927
3928 b43_nphy_stop_playback(dev);
3929 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
3930 }
3931
3932 b43_nphy_tx_cal_phy_cleanup(dev);
3933 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
3934
3935 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
3936 b43_nphy_tx_iq_workaround(dev);
3937
3938 if (dev->phy.rev >= 4)
3939 nphy->hang_avoid = avoid;
3940
3941 b43_nphy_stay_in_carrier_search(dev, false);
3942
3943 return error;
3944 }
3945
3946 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
3947 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
3948 {
3949 struct b43_phy_n *nphy = dev->phy.n;
3950 u8 i;
3951 u16 buffer[7];
3952 bool equal = true;
3953
3954 if (!nphy->txiqlocal_coeffsvalid ||
3955 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
3956 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
3957 return;
3958
3959 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
3960 for (i = 0; i < 4; i++) {
3961 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
3962 equal = false;
3963 break;
3964 }
3965 }
3966
3967 if (!equal) {
3968 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
3969 nphy->txiqlocal_bestc);
3970 for (i = 0; i < 4; i++)
3971 buffer[i] = 0;
3972 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
3973 buffer);
3974 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
3975 &nphy->txiqlocal_bestc[5]);
3976 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
3977 &nphy->txiqlocal_bestc[5]);
3978 }
3979 }
3980
3981 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
3982 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
3983 struct nphy_txgains target, u8 type, bool debug)
3984 {
3985 struct b43_phy_n *nphy = dev->phy.n;
3986 int i, j, index;
3987 u8 rfctl[2];
3988 u8 afectl_core;
3989 u16 tmp[6];
3990 u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna;
3991 u32 real, imag;
3992 enum ieee80211_band band;
3993
3994 u8 use;
3995 u16 cur_hpf;
3996 u16 lna[3] = { 3, 3, 1 };
3997 u16 hpf1[3] = { 7, 2, 0 };
3998 u16 hpf2[3] = { 2, 0, 0 };
3999 u32 power[3] = { };
4000 u16 gain_save[2];
4001 u16 cal_gain[2];
4002 struct nphy_iqcal_params cal_params[2];
4003 struct nphy_iq_est est;
4004 int ret = 0;
4005 bool playtone = true;
4006 int desired = 13;
4007
4008 b43_nphy_stay_in_carrier_search(dev, 1);
4009
4010 if (dev->phy.rev < 2)
4011 b43_nphy_reapply_tx_cal_coeffs(dev);
4012 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4013 for (i = 0; i < 2; i++) {
4014 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
4015 cal_gain[i] = cal_params[i].cal_gain;
4016 }
4017 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
4018
4019 for (i = 0; i < 2; i++) {
4020 if (i == 0) {
4021 rfctl[0] = B43_NPHY_RFCTL_INTC1;
4022 rfctl[1] = B43_NPHY_RFCTL_INTC2;
4023 afectl_core = B43_NPHY_AFECTL_C1;
4024 } else {
4025 rfctl[0] = B43_NPHY_RFCTL_INTC2;
4026 rfctl[1] = B43_NPHY_RFCTL_INTC1;
4027 afectl_core = B43_NPHY_AFECTL_C2;
4028 }
4029
4030 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
4031 tmp[2] = b43_phy_read(dev, afectl_core);
4032 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
4033 tmp[4] = b43_phy_read(dev, rfctl[0]);
4034 tmp[5] = b43_phy_read(dev, rfctl[1]);
4035
4036 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
4037 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
4038 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
4039 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
4040 (1 - i));
4041 b43_phy_set(dev, afectl_core, 0x0006);
4042 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
4043
4044 band = b43_current_band(dev->wl);
4045
4046 if (nphy->rxcalparams & 0xFF000000) {
4047 if (band == IEEE80211_BAND_5GHZ)
4048 b43_phy_write(dev, rfctl[0], 0x140);
4049 else
4050 b43_phy_write(dev, rfctl[0], 0x110);
4051 } else {
4052 if (band == IEEE80211_BAND_5GHZ)
4053 b43_phy_write(dev, rfctl[0], 0x180);
4054 else
4055 b43_phy_write(dev, rfctl[0], 0x120);
4056 }
4057
4058 if (band == IEEE80211_BAND_5GHZ)
4059 b43_phy_write(dev, rfctl[1], 0x148);
4060 else
4061 b43_phy_write(dev, rfctl[1], 0x114);
4062
4063 if (nphy->rxcalparams & 0x10000) {
4064 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
4065 (i + 1));
4066 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
4067 (2 - i));
4068 }
4069
4070 for (j = 0; j < 4; j++) {
4071 if (j < 3) {
4072 cur_lna = lna[j];
4073 cur_hpf1 = hpf1[j];
4074 cur_hpf2 = hpf2[j];
4075 } else {
4076 if (power[1] > 10000) {
4077 use = 1;
4078 cur_hpf = cur_hpf1;
4079 index = 2;
4080 } else {
4081 if (power[0] > 10000) {
4082 use = 1;
4083 cur_hpf = cur_hpf1;
4084 index = 1;
4085 } else {
4086 index = 0;
4087 use = 2;
4088 cur_hpf = cur_hpf2;
4089 }
4090 }
4091 cur_lna = lna[index];
4092 cur_hpf1 = hpf1[index];
4093 cur_hpf2 = hpf2[index];
4094 cur_hpf += desired - hweight32(power[index]);
4095 cur_hpf = clamp_val(cur_hpf, 0, 10);
4096 if (use == 1)
4097 cur_hpf1 = cur_hpf;
4098 else
4099 cur_hpf2 = cur_hpf;
4100 }
4101
4102 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
4103 (cur_lna << 2));
4104 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
4105 false);
4106 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4107 b43_nphy_stop_playback(dev);
4108
4109 if (playtone) {
4110 ret = b43_nphy_tx_tone(dev, 4000,
4111 (nphy->rxcalparams & 0xFFFF),
4112 false, false);
4113 playtone = false;
4114 } else {
4115 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
4116 false, false);
4117 }
4118
4119 if (ret == 0) {
4120 if (j < 3) {
4121 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
4122 false);
4123 if (i == 0) {
4124 real = est.i0_pwr;
4125 imag = est.q0_pwr;
4126 } else {
4127 real = est.i1_pwr;
4128 imag = est.q1_pwr;
4129 }
4130 power[i] = ((real + imag) / 1024) + 1;
4131 } else {
4132 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
4133 }
4134 b43_nphy_stop_playback(dev);
4135 }
4136
4137 if (ret != 0)
4138 break;
4139 }
4140
4141 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
4142 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
4143 b43_phy_write(dev, rfctl[1], tmp[5]);
4144 b43_phy_write(dev, rfctl[0], tmp[4]);
4145 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
4146 b43_phy_write(dev, afectl_core, tmp[2]);
4147 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
4148
4149 if (ret != 0)
4150 break;
4151 }
4152
4153 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
4154 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4155 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
4156
4157 b43_nphy_stay_in_carrier_search(dev, 0);
4158
4159 return ret;
4160 }
4161
4162 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
4163 struct nphy_txgains target, u8 type, bool debug)
4164 {
4165 return -1;
4166 }
4167
4168 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
4169 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
4170 struct nphy_txgains target, u8 type, bool debug)
4171 {
4172 if (dev->phy.rev >= 3)
4173 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
4174 else
4175 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
4176 }
4177
4178 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
4179 static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
4180 {
4181 struct b43_phy *phy = &dev->phy;
4182 struct b43_phy_n *nphy = phy->n;
4183 /* u16 buf[16]; it's rev3+ */
4184
4185 nphy->phyrxchain = mask;
4186
4187 if (0 /* FIXME clk */)
4188 return;
4189
4190 b43_mac_suspend(dev);
4191
4192 if (nphy->hang_avoid)
4193 b43_nphy_stay_in_carrier_search(dev, true);
4194
4195 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
4196 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
4197
4198 if ((mask & 0x3) != 0x3) {
4199 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
4200 if (dev->phy.rev >= 3) {
4201 /* TODO */
4202 }
4203 } else {
4204 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
4205 if (dev->phy.rev >= 3) {
4206 /* TODO */
4207 }
4208 }
4209
4210 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4211
4212 if (nphy->hang_avoid)
4213 b43_nphy_stay_in_carrier_search(dev, false);
4214
4215 b43_mac_enable(dev);
4216 }
4217
4218 /**************************************************
4219 * N-PHY init
4220 **************************************************/
4221
4222 /*
4223 * Upload the N-PHY tables.
4224 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
4225 */
4226 static void b43_nphy_tables_init(struct b43_wldev *dev)
4227 {
4228 if (dev->phy.rev < 3)
4229 b43_nphy_rev0_1_2_tables_init(dev);
4230 else
4231 b43_nphy_rev3plus_tables_init(dev);
4232 }
4233
4234 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
4235 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
4236 {
4237 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
4238
4239 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
4240 if (preamble == 1)
4241 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
4242 else
4243 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
4244
4245 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
4246 }
4247
4248 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
4249 static void b43_nphy_bphy_init(struct b43_wldev *dev)
4250 {
4251 unsigned int i;
4252 u16 val;
4253
4254 val = 0x1E1F;
4255 for (i = 0; i < 16; i++) {
4256 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
4257 val -= 0x202;
4258 }
4259 val = 0x3E3F;
4260 for (i = 0; i < 16; i++) {
4261 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
4262 val -= 0x202;
4263 }
4264 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
4265 }
4266
4267 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
4268 static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
4269 {
4270 if (dev->phy.rev >= 3) {
4271 if (!init)
4272 return;
4273 if (0 /* FIXME */) {
4274 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
4275 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
4276 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
4277 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
4278 }
4279 } else {
4280 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
4281 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
4282
4283 switch (dev->dev->bus_type) {
4284 #ifdef CONFIG_B43_BCMA
4285 case B43_BUS_BCMA:
4286 bcma_chipco_gpio_control(&dev->dev->bdev->bus->drv_cc,
4287 0xFC00, 0xFC00);
4288 break;
4289 #endif
4290 #ifdef CONFIG_B43_SSB
4291 case B43_BUS_SSB:
4292 ssb_chipco_gpio_control(&dev->dev->sdev->bus->chipco,
4293 0xFC00, 0xFC00);
4294 break;
4295 #endif
4296 }
4297
4298 b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_GPOUTSMSK, 0);
4299 b43_maskset16(dev, B43_MMIO_GPIO_MASK, ~0, 0xFC00);
4300 b43_maskset16(dev, B43_MMIO_GPIO_CONTROL, (~0xFC00 & 0xFFFF),
4301 0);
4302
4303 if (init) {
4304 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
4305 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
4306 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
4307 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
4308 }
4309 }
4310 }
4311
4312 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */
4313 int b43_phy_initn(struct b43_wldev *dev)
4314 {
4315 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4316 struct b43_phy *phy = &dev->phy;
4317 struct b43_phy_n *nphy = phy->n;
4318 u8 tx_pwr_state;
4319 struct nphy_txgains target;
4320 u16 tmp;
4321 enum ieee80211_band tmp2;
4322 bool do_rssi_cal;
4323
4324 u16 clip[2];
4325 bool do_cal = false;
4326
4327 if ((dev->phy.rev >= 3) &&
4328 (sprom->boardflags_lo & B43_BFL_EXTLNA) &&
4329 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
4330 switch (dev->dev->bus_type) {
4331 #ifdef CONFIG_B43_BCMA
4332 case B43_BUS_BCMA:
4333 bcma_cc_set32(&dev->dev->bdev->bus->drv_cc,
4334 BCMA_CC_CHIPCTL, 0x40);
4335 break;
4336 #endif
4337 #ifdef CONFIG_B43_SSB
4338 case B43_BUS_SSB:
4339 chipco_set32(&dev->dev->sdev->bus->chipco,
4340 SSB_CHIPCO_CHIPCTL, 0x40);
4341 break;
4342 #endif
4343 }
4344 }
4345 nphy->deaf_count = 0;
4346 b43_nphy_tables_init(dev);
4347 nphy->crsminpwr_adjusted = false;
4348 nphy->noisevars_adjusted = false;
4349
4350 /* Clear all overrides */
4351 if (dev->phy.rev >= 3) {
4352 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
4353 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4354 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
4355 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
4356 } else {
4357 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
4358 }
4359 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
4360 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
4361 if (dev->phy.rev < 6) {
4362 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
4363 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
4364 }
4365 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
4366 ~(B43_NPHY_RFSEQMODE_CAOVER |
4367 B43_NPHY_RFSEQMODE_TROVER));
4368 if (dev->phy.rev >= 3)
4369 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
4370 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
4371
4372 if (dev->phy.rev <= 2) {
4373 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
4374 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
4375 ~B43_NPHY_BPHY_CTL3_SCALE,
4376 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
4377 }
4378 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
4379 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
4380
4381 if (sprom->boardflags2_lo & B43_BFL2_SKWRKFEM_BRD ||
4382 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4383 dev->dev->board_type == 0x8B))
4384 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
4385 else
4386 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
4387 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
4388 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
4389 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
4390
4391 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4392 b43_nphy_update_txrx_chain(dev);
4393
4394 if (phy->rev < 2) {
4395 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
4396 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
4397 }
4398
4399 tmp2 = b43_current_band(dev->wl);
4400 if (b43_nphy_ipa(dev)) {
4401 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
4402 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
4403 nphy->papd_epsilon_offset[0] << 7);
4404 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
4405 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
4406 nphy->papd_epsilon_offset[1] << 7);
4407 b43_nphy_int_pa_set_tx_dig_filters(dev);
4408 } else if (phy->rev >= 5) {
4409 b43_nphy_ext_pa_set_tx_dig_filters(dev);
4410 }
4411
4412 b43_nphy_workarounds(dev);
4413
4414 /* Reset CCA, in init code it differs a little from standard way */
4415 b43_phy_force_clock(dev, 1);
4416 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
4417 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
4418 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
4419 b43_phy_force_clock(dev, 0);
4420
4421 b43_mac_phy_clock_set(dev, true);
4422
4423 b43_nphy_pa_override(dev, false);
4424 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
4425 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
4426 b43_nphy_pa_override(dev, true);
4427
4428 b43_nphy_classifier(dev, 0, 0);
4429 b43_nphy_read_clip_detection(dev, clip);
4430 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4431 b43_nphy_bphy_init(dev);
4432
4433 tx_pwr_state = nphy->txpwrctrl;
4434 b43_nphy_tx_power_ctrl(dev, false);
4435 b43_nphy_tx_power_fix(dev);
4436 b43_nphy_tx_power_ctl_idle_tssi(dev);
4437 b43_nphy_tx_power_ctl_setup(dev);
4438 b43_nphy_tx_gain_table_upload(dev);
4439
4440 if (nphy->phyrxchain != 3)
4441 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
4442 if (nphy->mphase_cal_phase_id > 0)
4443 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
4444
4445 do_rssi_cal = false;
4446 if (phy->rev >= 3) {
4447 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4448 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
4449 else
4450 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
4451
4452 if (do_rssi_cal)
4453 b43_nphy_rssi_cal(dev);
4454 else
4455 b43_nphy_restore_rssi_cal(dev);
4456 } else {
4457 b43_nphy_rssi_cal(dev);
4458 }
4459
4460 if (!((nphy->measure_hold & 0x6) != 0)) {
4461 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4462 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
4463 else
4464 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
4465
4466 if (nphy->mute)
4467 do_cal = false;
4468
4469 if (do_cal) {
4470 target = b43_nphy_get_tx_gains(dev);
4471
4472 if (nphy->antsel_type == 2)
4473 b43_nphy_superswitch_init(dev, true);
4474 if (nphy->perical != 2) {
4475 b43_nphy_rssi_cal(dev);
4476 if (phy->rev >= 3) {
4477 nphy->cal_orig_pwr_idx[0] =
4478 nphy->txpwrindex[0].index_internal;
4479 nphy->cal_orig_pwr_idx[1] =
4480 nphy->txpwrindex[1].index_internal;
4481 /* TODO N PHY Pre Calibrate TX Gain */
4482 target = b43_nphy_get_tx_gains(dev);
4483 }
4484 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false))
4485 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
4486 b43_nphy_save_cal(dev);
4487 } else if (nphy->mphase_cal_phase_id == 0)
4488 ;/* N PHY Periodic Calibration with arg 3 */
4489 } else {
4490 b43_nphy_restore_cal(dev);
4491 }
4492 }
4493
4494 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
4495 b43_nphy_tx_power_ctrl(dev, tx_pwr_state);
4496 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
4497 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
4498 if (phy->rev >= 3 && phy->rev <= 6)
4499 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
4500 b43_nphy_tx_lp_fbw(dev);
4501 if (phy->rev >= 3)
4502 b43_nphy_spur_workaround(dev);
4503
4504 return 0;
4505 }
4506
4507 /**************************************************
4508 * Channel switching ops.
4509 **************************************************/
4510
4511 static void b43_chantab_phy_upload(struct b43_wldev *dev,
4512 const struct b43_phy_n_sfo_cfg *e)
4513 {
4514 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
4515 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
4516 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
4517 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
4518 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
4519 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
4520 }
4521
4522 /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */
4523 static void b43_nphy_pmu_spur_avoid(struct b43_wldev *dev, bool avoid)
4524 {
4525 struct bcma_drv_cc __maybe_unused *cc;
4526 u32 __maybe_unused pmu_ctl;
4527
4528 switch (dev->dev->bus_type) {
4529 #ifdef CONFIG_B43_BCMA
4530 case B43_BUS_BCMA:
4531 cc = &dev->dev->bdev->bus->drv_cc;
4532 if (dev->dev->chip_id == 43224 || dev->dev->chip_id == 43225) {
4533 if (avoid) {
4534 bcma_chipco_pll_write(cc, 0x0, 0x11500010);
4535 bcma_chipco_pll_write(cc, 0x1, 0x000C0C06);
4536 bcma_chipco_pll_write(cc, 0x2, 0x0F600a08);
4537 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4538 bcma_chipco_pll_write(cc, 0x4, 0x2001E920);
4539 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4540 } else {
4541 bcma_chipco_pll_write(cc, 0x0, 0x11100010);
4542 bcma_chipco_pll_write(cc, 0x1, 0x000c0c06);
4543 bcma_chipco_pll_write(cc, 0x2, 0x03000a08);
4544 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4545 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4546 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4547 }
4548 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4549 } else if (dev->dev->chip_id == 0x4716) {
4550 if (avoid) {
4551 bcma_chipco_pll_write(cc, 0x0, 0x11500060);
4552 bcma_chipco_pll_write(cc, 0x1, 0x080C0C06);
4553 bcma_chipco_pll_write(cc, 0x2, 0x0F600000);
4554 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4555 bcma_chipco_pll_write(cc, 0x4, 0x2001E924);
4556 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4557 } else {
4558 bcma_chipco_pll_write(cc, 0x0, 0x11100060);
4559 bcma_chipco_pll_write(cc, 0x1, 0x080c0c06);
4560 bcma_chipco_pll_write(cc, 0x2, 0x03000000);
4561 bcma_chipco_pll_write(cc, 0x3, 0x00000000);
4562 bcma_chipco_pll_write(cc, 0x4, 0x200005c0);
4563 bcma_chipco_pll_write(cc, 0x5, 0x88888815);
4564 }
4565 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD |
4566 BCMA_CC_PMU_CTL_NOILPONW;
4567 } else if (dev->dev->chip_id == 0x4322 ||
4568 dev->dev->chip_id == 0x4340 ||
4569 dev->dev->chip_id == 0x4341) {
4570 bcma_chipco_pll_write(cc, 0x0, 0x11100070);
4571 bcma_chipco_pll_write(cc, 0x1, 0x1014140a);
4572 bcma_chipco_pll_write(cc, 0x5, 0x88888854);
4573 if (avoid)
4574 bcma_chipco_pll_write(cc, 0x2, 0x05201828);
4575 else
4576 bcma_chipco_pll_write(cc, 0x2, 0x05001828);
4577 pmu_ctl = BCMA_CC_PMU_CTL_PLL_UPD;
4578 } else {
4579 return;
4580 }
4581 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, pmu_ctl);
4582 break;
4583 #endif
4584 #ifdef CONFIG_B43_SSB
4585 case B43_BUS_SSB:
4586 /* FIXME */
4587 break;
4588 #endif
4589 }
4590 }
4591
4592 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
4593 static void b43_nphy_channel_setup(struct b43_wldev *dev,
4594 const struct b43_phy_n_sfo_cfg *e,
4595 struct ieee80211_channel *new_channel)
4596 {
4597 struct b43_phy *phy = &dev->phy;
4598 struct b43_phy_n *nphy = dev->phy.n;
4599 int ch = new_channel->hw_value;
4600
4601 u16 old_band_5ghz;
4602 u32 tmp32;
4603
4604 old_band_5ghz =
4605 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
4606 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
4607 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4608 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4609 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
4610 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4611 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
4612 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
4613 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
4614 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
4615 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
4616 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
4617 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
4618 }
4619
4620 b43_chantab_phy_upload(dev, e);
4621
4622 if (new_channel->hw_value == 14) {
4623 b43_nphy_classifier(dev, 2, 0);
4624 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
4625 } else {
4626 b43_nphy_classifier(dev, 2, 2);
4627 if (new_channel->band == IEEE80211_BAND_2GHZ)
4628 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
4629 }
4630
4631 if (!nphy->txpwrctrl)
4632 b43_nphy_tx_power_fix(dev);
4633
4634 if (dev->phy.rev < 3)
4635 b43_nphy_adjust_lna_gain_table(dev);
4636
4637 b43_nphy_tx_lp_fbw(dev);
4638
4639 if (dev->phy.rev >= 3 &&
4640 dev->phy.n->spur_avoid != B43_SPUR_AVOID_DISABLE) {
4641 bool avoid = false;
4642 if (dev->phy.n->spur_avoid == B43_SPUR_AVOID_FORCE) {
4643 avoid = true;
4644 } else if (!b43_channel_type_is_40mhz(phy->channel_type)) {
4645 if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14)
4646 avoid = true;
4647 } else { /* 40MHz */
4648 if (nphy->aband_spurwar_en &&
4649 (ch == 38 || ch == 102 || ch == 118))
4650 avoid = dev->dev->chip_id == 0x4716;
4651 }
4652
4653 b43_nphy_pmu_spur_avoid(dev, avoid);
4654
4655 if (dev->dev->chip_id == 43222 || dev->dev->chip_id == 43224 ||
4656 dev->dev->chip_id == 43225) {
4657 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_LOW,
4658 avoid ? 0x5341 : 0x8889);
4659 b43_write16(dev, B43_MMIO_TSF_CLK_FRAC_HIGH, 0x8);
4660 }
4661
4662 if (dev->phy.rev == 3 || dev->phy.rev == 4)
4663 ; /* TODO: reset PLL */
4664
4665 if (avoid)
4666 b43_phy_set(dev, B43_NPHY_BBCFG, B43_NPHY_BBCFG_RSTRX);
4667 else
4668 b43_phy_mask(dev, B43_NPHY_BBCFG,
4669 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
4670
4671 b43_nphy_reset_cca(dev);
4672
4673 /* wl sets useless phy_isspuravoid here */
4674 }
4675
4676 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
4677
4678 if (phy->rev >= 3)
4679 b43_nphy_spur_workaround(dev);
4680 }
4681
4682 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
4683 static int b43_nphy_set_channel(struct b43_wldev *dev,
4684 struct ieee80211_channel *channel,
4685 enum nl80211_channel_type channel_type)
4686 {
4687 struct b43_phy *phy = &dev->phy;
4688
4689 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2 = NULL;
4690 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3 = NULL;
4691
4692 u8 tmp;
4693
4694 if (dev->phy.rev >= 3) {
4695 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
4696 channel->center_freq);
4697 if (!tabent_r3)
4698 return -ESRCH;
4699 } else {
4700 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
4701 channel->hw_value);
4702 if (!tabent_r2)
4703 return -ESRCH;
4704 }
4705
4706 /* Channel is set later in common code, but we need to set it on our
4707 own to let this function's subcalls work properly. */
4708 phy->channel = channel->hw_value;
4709 phy->channel_freq = channel->center_freq;
4710
4711 if (b43_channel_type_is_40mhz(phy->channel_type) !=
4712 b43_channel_type_is_40mhz(channel_type))
4713 ; /* TODO: BMAC BW Set (channel_type) */
4714
4715 if (channel_type == NL80211_CHAN_HT40PLUS)
4716 b43_phy_set(dev, B43_NPHY_RXCTL,
4717 B43_NPHY_RXCTL_BSELU20);
4718 else if (channel_type == NL80211_CHAN_HT40MINUS)
4719 b43_phy_mask(dev, B43_NPHY_RXCTL,
4720 ~B43_NPHY_RXCTL_BSELU20);
4721
4722 if (dev->phy.rev >= 3) {
4723 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
4724 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
4725 b43_radio_2056_setup(dev, tabent_r3);
4726 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
4727 } else {
4728 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
4729 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
4730 b43_radio_2055_setup(dev, tabent_r2);
4731 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
4732 }
4733
4734 return 0;
4735 }
4736
4737 /**************************************************
4738 * Basic PHY ops.
4739 **************************************************/
4740
4741 static int b43_nphy_op_allocate(struct b43_wldev *dev)
4742 {
4743 struct b43_phy_n *nphy;
4744
4745 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
4746 if (!nphy)
4747 return -ENOMEM;
4748 dev->phy.n = nphy;
4749
4750 return 0;
4751 }
4752
4753 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
4754 {
4755 struct b43_phy *phy = &dev->phy;
4756 struct b43_phy_n *nphy = phy->n;
4757 struct ssb_sprom *sprom = dev->dev->bus_sprom;
4758
4759 memset(nphy, 0, sizeof(*nphy));
4760
4761 nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4);
4762 nphy->spur_avoid = (phy->rev >= 3) ?
4763 B43_SPUR_AVOID_AUTO : B43_SPUR_AVOID_DISABLE;
4764 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
4765 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
4766 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
4767 nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
4768 /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
4769 * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
4770 nphy->tx_pwr_idx[0] = 128;
4771 nphy->tx_pwr_idx[1] = 128;
4772
4773 /* Hardware TX power control and 5GHz power gain */
4774 nphy->txpwrctrl = false;
4775 nphy->pwg_gain_5ghz = false;
4776 if (dev->phy.rev >= 3 ||
4777 (dev->dev->board_vendor == PCI_VENDOR_ID_APPLE &&
4778 (dev->dev->core_rev == 11 || dev->dev->core_rev == 12))) {
4779 nphy->txpwrctrl = true;
4780 nphy->pwg_gain_5ghz = true;
4781 } else if (sprom->revision >= 4) {
4782 if (dev->phy.rev >= 2 &&
4783 (sprom->boardflags2_lo & B43_BFL2_TXPWRCTRL_EN)) {
4784 nphy->txpwrctrl = true;
4785 #ifdef CONFIG_B43_SSB
4786 if (dev->dev->bus_type == B43_BUS_SSB &&
4787 dev->dev->sdev->bus->bustype == SSB_BUSTYPE_PCI) {
4788 struct pci_dev *pdev =
4789 dev->dev->sdev->bus->host_pci;
4790 if (pdev->device == 0x4328 ||
4791 pdev->device == 0x432a)
4792 nphy->pwg_gain_5ghz = true;
4793 }
4794 #endif
4795 } else if (sprom->boardflags2_lo & B43_BFL2_5G_PWRGAIN) {
4796 nphy->pwg_gain_5ghz = true;
4797 }
4798 }
4799
4800 if (dev->phy.rev >= 3) {
4801 nphy->ipa2g_on = sprom->fem.ghz2.extpa_gain == 2;
4802 nphy->ipa5g_on = sprom->fem.ghz5.extpa_gain == 2;
4803 }
4804 }
4805
4806 static void b43_nphy_op_free(struct b43_wldev *dev)
4807 {
4808 struct b43_phy *phy = &dev->phy;
4809 struct b43_phy_n *nphy = phy->n;
4810
4811 kfree(nphy);
4812 phy->n = NULL;
4813 }
4814
4815 static int b43_nphy_op_init(struct b43_wldev *dev)
4816 {
4817 return b43_phy_initn(dev);
4818 }
4819
4820 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
4821 {
4822 #if B43_DEBUG
4823 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
4824 /* OFDM registers are onnly available on A/G-PHYs */
4825 b43err(dev->wl, "Invalid OFDM PHY access at "
4826 "0x%04X on N-PHY\n", offset);
4827 dump_stack();
4828 }
4829 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
4830 /* Ext-G registers are only available on G-PHYs */
4831 b43err(dev->wl, "Invalid EXT-G PHY access at "
4832 "0x%04X on N-PHY\n", offset);
4833 dump_stack();
4834 }
4835 #endif /* B43_DEBUG */
4836 }
4837
4838 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
4839 {
4840 check_phyreg(dev, reg);
4841 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4842 return b43_read16(dev, B43_MMIO_PHY_DATA);
4843 }
4844
4845 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
4846 {
4847 check_phyreg(dev, reg);
4848 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4849 b43_write16(dev, B43_MMIO_PHY_DATA, value);
4850 }
4851
4852 static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
4853 u16 set)
4854 {
4855 check_phyreg(dev, reg);
4856 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
4857 b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
4858 }
4859
4860 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
4861 {
4862 /* Register 1 is a 32-bit register. */
4863 B43_WARN_ON(reg == 1);
4864 /* N-PHY needs 0x100 for read access */
4865 reg |= 0x100;
4866
4867 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4868 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
4869 }
4870
4871 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
4872 {
4873 /* Register 1 is a 32-bit register. */
4874 B43_WARN_ON(reg == 1);
4875
4876 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
4877 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
4878 }
4879
4880 /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
4881 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
4882 bool blocked)
4883 {
4884 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
4885 b43err(dev->wl, "MAC not suspended\n");
4886
4887 if (blocked) {
4888 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
4889 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
4890 if (dev->phy.rev >= 3) {
4891 b43_radio_mask(dev, 0x09, ~0x2);
4892
4893 b43_radio_write(dev, 0x204D, 0);
4894 b43_radio_write(dev, 0x2053, 0);
4895 b43_radio_write(dev, 0x2058, 0);
4896 b43_radio_write(dev, 0x205E, 0);
4897 b43_radio_mask(dev, 0x2062, ~0xF0);
4898 b43_radio_write(dev, 0x2064, 0);
4899
4900 b43_radio_write(dev, 0x304D, 0);
4901 b43_radio_write(dev, 0x3053, 0);
4902 b43_radio_write(dev, 0x3058, 0);
4903 b43_radio_write(dev, 0x305E, 0);
4904 b43_radio_mask(dev, 0x3062, ~0xF0);
4905 b43_radio_write(dev, 0x3064, 0);
4906 }
4907 } else {
4908 if (dev->phy.rev >= 3) {
4909 b43_radio_init2056(dev);
4910 b43_switch_channel(dev, dev->phy.channel);
4911 } else {
4912 b43_radio_init2055(dev);
4913 }
4914 }
4915 }
4916
4917 /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */
4918 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
4919 {
4920 u16 override = on ? 0x0 : 0x7FFF;
4921 u16 core = on ? 0xD : 0x00FD;
4922
4923 if (dev->phy.rev >= 3) {
4924 if (on) {
4925 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4926 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4927 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4928 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4929 } else {
4930 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, override);
4931 b43_phy_write(dev, B43_NPHY_AFECTL_C1, core);
4932 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4933 b43_phy_write(dev, B43_NPHY_AFECTL_C2, core);
4934 }
4935 } else {
4936 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, override);
4937 }
4938 }
4939
4940 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
4941 unsigned int new_channel)
4942 {
4943 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
4944 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
4945
4946 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
4947 if ((new_channel < 1) || (new_channel > 14))
4948 return -EINVAL;
4949 } else {
4950 if (new_channel > 200)
4951 return -EINVAL;
4952 }
4953
4954 return b43_nphy_set_channel(dev, channel, channel_type);
4955 }
4956
4957 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
4958 {
4959 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
4960 return 1;
4961 return 36;
4962 }
4963
4964 const struct b43_phy_operations b43_phyops_n = {
4965 .allocate = b43_nphy_op_allocate,
4966 .free = b43_nphy_op_free,
4967 .prepare_structs = b43_nphy_op_prepare_structs,
4968 .init = b43_nphy_op_init,
4969 .phy_read = b43_nphy_op_read,
4970 .phy_write = b43_nphy_op_write,
4971 .phy_maskset = b43_nphy_op_maskset,
4972 .radio_read = b43_nphy_op_radio_read,
4973 .radio_write = b43_nphy_op_radio_write,
4974 .software_rfkill = b43_nphy_op_software_rfkill,
4975 .switch_analog = b43_nphy_op_switch_analog,
4976 .switch_channel = b43_nphy_op_switch_channel,
4977 .get_default_chan = b43_nphy_op_get_default_chan,
4978 .recalc_txpower = b43_nphy_op_recalc_txpower,
4979 .adjust_txpower = b43_nphy_op_adjust_txpower,
4980 };
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