drivers/net/wireless/b43legacy/b43legacy.h

   1 #ifndef B43legacy_H_
   2 #define B43legacy_H_
   3
   4 #include <linux/hw_random.h>
   5 #include <linux/kernel.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/stringify.h>
   9 #include <linux/netdevice.h>
  10 #include <linux/pci.h>
  11 #include <asm/atomic.h>
  12 #include <linux/io.h>
  13
  14 #include <linux/ssb/ssb.h>
  15 #include <linux/ssb/ssb_driver_chipcommon.h>
  16
  17 #include <linux/wireless.h>
  18 #include <net/mac80211.h>
  19
  20 #include "debugfs.h"
  21 #include "leds.h"
  22 #include "phy.h"
  23
  24
  25 #define B43legacy_IRQWAIT_MAX_RETRIES   100
  26
  27 #define B43legacy_RX_MAX_SSI            60 /* best guess at max ssi */
  28
  29 /* MMIO offsets */
  30 #define B43legacy_MMIO_DMA0_REASON      0x20
  31 #define B43legacy_MMIO_DMA0_IRQ_MASK    0x24
  32 #define B43legacy_MMIO_DMA1_REASON      0x28
  33 #define B43legacy_MMIO_DMA1_IRQ_MASK    0x2C
  34 #define B43legacy_MMIO_DMA2_REASON      0x30
  35 #define B43legacy_MMIO_DMA2_IRQ_MASK    0x34
  36 #define B43legacy_MMIO_DMA3_REASON      0x38
  37 #define B43legacy_MMIO_DMA3_IRQ_MASK    0x3C
  38 #define B43legacy_MMIO_DMA4_REASON      0x40
  39 #define B43legacy_MMIO_DMA4_IRQ_MASK    0x44
  40 #define B43legacy_MMIO_DMA5_REASON      0x48
  41 #define B43legacy_MMIO_DMA5_IRQ_MASK    0x4C
  42 #define B43legacy_MMIO_MACCTL           0x120
  43 #define B43legacy_MMIO_STATUS_BITFIELD  0x120
  44 #define B43legacy_MMIO_STATUS2_BITFIELD 0x124
  45 #define B43legacy_MMIO_GEN_IRQ_REASON   0x128
  46 #define B43legacy_MMIO_GEN_IRQ_MASK     0x12C
  47 #define B43legacy_MMIO_RAM_CONTROL      0x130
  48 #define B43legacy_MMIO_RAM_DATA         0x134
  49 #define B43legacy_MMIO_PS_STATUS                0x140
  50 #define B43legacy_MMIO_RADIO_HWENABLED_HI       0x158
  51 #define B43legacy_MMIO_SHM_CONTROL      0x160
  52 #define B43legacy_MMIO_SHM_DATA         0x164
  53 #define B43legacy_MMIO_SHM_DATA_UNALIGNED       0x166
  54 #define B43legacy_MMIO_XMITSTAT_0               0x170
  55 #define B43legacy_MMIO_XMITSTAT_1               0x174
  56 #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
  57 #define B43legacy_MMIO_REV3PLUS_TSF_HIGH        0x184 /* core rev >= 3 only */
  58
  59 /* 32-bit DMA */
  60 #define B43legacy_MMIO_DMA32_BASE0      0x200
  61 #define B43legacy_MMIO_DMA32_BASE1      0x220
  62 #define B43legacy_MMIO_DMA32_BASE2      0x240
  63 #define B43legacy_MMIO_DMA32_BASE3      0x260
  64 #define B43legacy_MMIO_DMA32_BASE4      0x280
  65 #define B43legacy_MMIO_DMA32_BASE5      0x2A0
  66 /* 64-bit DMA */
  67 #define B43legacy_MMIO_DMA64_BASE0      0x200
  68 #define B43legacy_MMIO_DMA64_BASE1      0x240
  69 #define B43legacy_MMIO_DMA64_BASE2      0x280
  70 #define B43legacy_MMIO_DMA64_BASE3      0x2C0
  71 #define B43legacy_MMIO_DMA64_BASE4      0x300
  72 #define B43legacy_MMIO_DMA64_BASE5      0x340
  73 /* PIO */
  74 #define B43legacy_MMIO_PIO1_BASE                0x300
  75 #define B43legacy_MMIO_PIO2_BASE                0x310
  76 #define B43legacy_MMIO_PIO3_BASE                0x320
  77 #define B43legacy_MMIO_PIO4_BASE                0x330
  78
  79 #define B43legacy_MMIO_PHY_VER          0x3E0
  80 #define B43legacy_MMIO_PHY_RADIO                0x3E2
  81 #define B43legacy_MMIO_PHY0             0x3E6
  82 #define B43legacy_MMIO_ANTENNA          0x3E8
  83 #define B43legacy_MMIO_CHANNEL          0x3F0
  84 #define B43legacy_MMIO_CHANNEL_EXT      0x3F4
  85 #define B43legacy_MMIO_RADIO_CONTROL    0x3F6
  86 #define B43legacy_MMIO_RADIO_DATA_HIGH  0x3F8
  87 #define B43legacy_MMIO_RADIO_DATA_LOW   0x3FA
  88 #define B43legacy_MMIO_PHY_CONTROL      0x3FC
  89 #define B43legacy_MMIO_PHY_DATA         0x3FE
  90 #define B43legacy_MMIO_MACFILTER_CONTROL        0x420
  91 #define B43legacy_MMIO_MACFILTER_DATA   0x422
  92 #define B43legacy_MMIO_RCMTA_COUNT      0x43C /* Receive Match Transmitter Addr */
  93 #define B43legacy_MMIO_RADIO_HWENABLED_LO       0x49A
  94 #define B43legacy_MMIO_GPIO_CONTROL     0x49C
  95 #define B43legacy_MMIO_GPIO_MASK                0x49E
  96 #define B43legacy_MMIO_TSF_0            0x632 /* core rev < 3 only */
  97 #define B43legacy_MMIO_TSF_1            0x634 /* core rev < 3 only */
  98 #define B43legacy_MMIO_TSF_2            0x636 /* core rev < 3 only */
  99 #define B43legacy_MMIO_TSF_3            0x638 /* core rev < 3 only */
 100 #define B43legacy_MMIO_RNG              0x65A
 101 #define B43legacy_MMIO_POWERUP_DELAY    0x6A8
 102
 103 /* SPROM boardflags_lo values */
 104 #define B43legacy_BFL_PACTRL            0x0002
 105 #define B43legacy_BFL_RSSI              0x0008
 106 #define B43legacy_BFL_EXTLNA            0x1000
 107
 108 /* GPIO register offset, in both ChipCommon and PCI core. */
 109 #define B43legacy_GPIO_CONTROL          0x6c
 110
 111 /* SHM Routing */
 112 #define B43legacy_SHM_SHARED            0x0001
 113 #define B43legacy_SHM_WIRELESS          0x0002
 114 #define B43legacy_SHM_HW                0x0004
 115 #define B43legacy_SHM_UCODE             0x0300
 116
 117 /* SHM Routing modifiers */
 118 #define B43legacy_SHM_AUTOINC_R         0x0200 /* Read Auto-increment */
 119 #define B43legacy_SHM_AUTOINC_W         0x0100 /* Write Auto-increment */
 120 #define B43legacy_SHM_AUTOINC_RW        (B43legacy_SHM_AUTOINC_R | \
 121                                          B43legacy_SHM_AUTOINC_W)
 122
 123 /* Misc SHM_SHARED offsets */
 124 #define B43legacy_SHM_SH_WLCOREREV      0x0016 /* 802.11 core revision */
 125 #define B43legacy_SHM_SH_HOSTFLO        0x005E /* Hostflags ucode opts (low) */
 126 #define B43legacy_SHM_SH_HOSTFHI        0x0060 /* Hostflags ucode opts (high) */
 127 /* SHM_SHARED crypto engine */
 128 #define B43legacy_SHM_SH_KEYIDXBLOCK    0x05D4 /* Key index/algorithm block */
 129 /* SHM_SHARED beacon variables */
 130 #define B43legacy_SHM_SH_BEACPHYCTL     0x0054 /* Beacon PHY TX control word */
 131 /* SHM_SHARED ACK/CTS control */
 132 #define B43legacy_SHM_SH_ACKCTSPHYCTL   0x0022 /* ACK/CTS PHY control word */
 133 /* SHM_SHARED probe response variables */
 134 #define B43legacy_SHM_SH_PRPHYCTL       0x0188 /* Probe Resp PHY TX control */
 135 #define B43legacy_SHM_SH_PRMAXTIME      0x0074 /* Probe Response max time */
 136 /* SHM_SHARED rate tables */
 137 /* SHM_SHARED microcode soft registers */
 138 #define B43legacy_SHM_SH_UCODEREV       0x0000 /* Microcode revision */
 139 #define B43legacy_SHM_SH_UCODEPATCH     0x0002 /* Microcode patchlevel */
 140 #define B43legacy_SHM_SH_UCODEDATE      0x0004 /* Microcode date */
 141 #define B43legacy_SHM_SH_UCODETIME      0x0006 /* Microcode time */
 142
 143 #define B43legacy_UCODEFLAGS_OFFSET     0x005E
 144
 145 /* Hardware Radio Enable masks */
 146 #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
 147 #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
 148
 149 /* HostFlags. See b43legacy_hf_read/write() */
 150 #define B43legacy_HF_SYMW               0x00000002 /* G-PHY SYM workaround */
 151 #define B43legacy_HF_GDCW               0x00000020 /* G-PHY DV cancel filter */
 152 #define B43legacy_HF_OFDMPABOOST        0x00000040 /* Enable PA boost OFDM */
 153 #define B43legacy_HF_EDCF               0x00000100 /* on if WME/MAC suspended */
 154
 155 /* MacFilter offsets. */
 156 #define B43legacy_MACFILTER_SELF        0x0000
 157 #define B43legacy_MACFILTER_BSSID       0x0003
 158 #define B43legacy_MACFILTER_MAC         0x0010
 159
 160 /* PHYVersioning */
 161 #define B43legacy_PHYTYPE_B             0x01
 162 #define B43legacy_PHYTYPE_G             0x02
 163
 164 /* PHYRegisters */
 165 #define B43legacy_PHY_G_LO_CONTROL      0x0810
 166 #define B43legacy_PHY_ILT_G_CTRL        0x0472
 167 #define B43legacy_PHY_ILT_G_DATA1       0x0473
 168 #define B43legacy_PHY_ILT_G_DATA2       0x0474
 169 #define B43legacy_PHY_G_PCTL            0x0029
 170 #define B43legacy_PHY_RADIO_BITFIELD    0x0401
 171 #define B43legacy_PHY_G_CRS             0x0429
 172 #define B43legacy_PHY_NRSSILT_CTRL      0x0803
 173 #define B43legacy_PHY_NRSSILT_DATA      0x0804
 174
 175 /* RadioRegisters */
 176 #define B43legacy_RADIOCTL_ID           0x01
 177
 178 /* MAC Control bitfield */
 179 #define B43legacy_MACCTL_IHR_ENABLED    0x00000400 /* IHR Region Enabled */
 180 #define B43legacy_MACCTL_INFRA          0x00020000 /* Infrastructure mode */
 181 #define B43legacy_MACCTL_AP             0x00040000 /* AccessPoint mode */
 182 #define B43legacy_MACCTL_BEACPROMISC    0x00100000 /* Beacon Promiscuous */
 183 #define B43legacy_MACCTL_KEEP_BADPLCP   0x00200000 /* Keep bad PLCP frames */
 184 #define B43legacy_MACCTL_KEEP_CTL       0x00400000 /* Keep control frames */
 185 #define B43legacy_MACCTL_KEEP_BAD       0x00800000 /* Keep bad frames (FCS) */
 186 #define B43legacy_MACCTL_PROMISC        0x01000000 /* Promiscuous mode */
 187 #define B43legacy_MACCTL_GMODE          0x80000000 /* G Mode */
 188
 189 /* StatusBitField */
 190 #define B43legacy_SBF_MAC_ENABLED       0x00000001
 191 #define B43legacy_SBF_CORE_READY        0x00000004
 192 #define B43legacy_SBF_400               0x00000400 /*FIXME: fix name*/
 193 #define B43legacy_SBF_XFER_REG_BYTESWAP 0x00010000
 194 #define B43legacy_SBF_MODE_NOTADHOC     0x00020000
 195 #define B43legacy_SBF_MODE_AP           0x00040000
 196 #define B43legacy_SBF_RADIOREG_LOCK     0x00080000
 197 #define B43legacy_SBF_MODE_MONITOR      0x00400000
 198 #define B43legacy_SBF_MODE_PROMISC      0x01000000
 199 #define B43legacy_SBF_PS1               0x02000000
 200 #define B43legacy_SBF_PS2               0x04000000
 201 #define B43legacy_SBF_NO_SSID_BCAST     0x08000000
 202 #define B43legacy_SBF_TIME_UPDATE       0x10000000
 203
 204 /* 802.11 core specific TM State Low flags */
 205 #define B43legacy_TMSLOW_GMODE          0x20000000 /* G Mode Enable */
 206 #define B43legacy_TMSLOW_PLLREFSEL      0x00200000 /* PLL Freq Ref Select */
 207 #define B43legacy_TMSLOW_MACPHYCLKEN    0x00100000 /* MAC PHY Clock Ctrl Enbl */
 208 #define B43legacy_TMSLOW_PHYRESET       0x00080000 /* PHY Reset */
 209 #define B43legacy_TMSLOW_PHYCLKEN       0x00040000 /* PHY Clock Enable */
 210
 211 /* 802.11 core specific TM State High flags */
 212 #define B43legacy_TMSHIGH_FCLOCK        0x00040000 /* Fast Clock Available */
 213 #define B43legacy_TMSHIGH_GPHY          0x00010000 /* G-PHY avail (rev >= 5) */
 214
 215 #define B43legacy_UCODEFLAG_AUTODIV       0x0001
 216
 217 /* Generic-Interrupt reasons. */
 218 #define B43legacy_IRQ_MAC_SUSPENDED     0x00000001
 219 #define B43legacy_IRQ_BEACON            0x00000002
 220 #define B43legacy_IRQ_TBTT_INDI         0x00000004 /* Target Beacon Transmit Time */
 221 #define B43legacy_IRQ_BEACON_TX_OK      0x00000008
 222 #define B43legacy_IRQ_BEACON_CANCEL     0x00000010
 223 #define B43legacy_IRQ_ATIM_END          0x00000020
 224 #define B43legacy_IRQ_PMQ               0x00000040
 225 #define B43legacy_IRQ_PIO_WORKAROUND    0x00000100
 226 #define B43legacy_IRQ_MAC_TXERR         0x00000200
 227 #define B43legacy_IRQ_PHY_TXERR         0x00000800
 228 #define B43legacy_IRQ_PMEVENT           0x00001000
 229 #define B43legacy_IRQ_TIMER0            0x00002000
 230 #define B43legacy_IRQ_TIMER1            0x00004000
 231 #define B43legacy_IRQ_DMA               0x00008000
 232 #define B43legacy_IRQ_TXFIFO_FLUSH_OK   0x00010000
 233 #define B43legacy_IRQ_CCA_MEASURE_OK    0x00020000
 234 #define B43legacy_IRQ_NOISESAMPLE_OK    0x00040000
 235 #define B43legacy_IRQ_UCODE_DEBUG       0x08000000
 236 #define B43legacy_IRQ_RFKILL            0x10000000
 237 #define B43legacy_IRQ_TX_OK             0x20000000
 238 #define B43legacy_IRQ_PHY_G_CHANGED     0x40000000
 239 #define B43legacy_IRQ_TIMEOUT           0x80000000
 240
 241 #define B43legacy_IRQ_ALL               0xFFFFFFFF
 242 #define B43legacy_IRQ_MASKTEMPLATE      (B43legacy_IRQ_MAC_SUSPENDED |  \
 243                                          B43legacy_IRQ_BEACON |         \
 244                                          B43legacy_IRQ_TBTT_INDI |      \
 245                                          B43legacy_IRQ_ATIM_END |       \
 246                                          B43legacy_IRQ_PMQ |            \
 247                                          B43legacy_IRQ_MAC_TXERR |      \
 248                                          B43legacy_IRQ_PHY_TXERR |      \
 249                                          B43legacy_IRQ_DMA |            \
 250                                          B43legacy_IRQ_TXFIFO_FLUSH_OK | \
 251                                          B43legacy_IRQ_NOISESAMPLE_OK | \
 252                                          B43legacy_IRQ_UCODE_DEBUG |    \
 253                                          B43legacy_IRQ_RFKILL |         \
 254                                          B43legacy_IRQ_TX_OK)
 255
 256 /* Device specific rate values.
 257  * The actual values defined here are (rate_in_mbps * 2).
 258  * Some code depends on this. Don't change it. */
 259 #define B43legacy_CCK_RATE_1MB          2
 260 #define B43legacy_CCK_RATE_2MB          4
 261 #define B43legacy_CCK_RATE_5MB          11
 262 #define B43legacy_CCK_RATE_11MB         22
 263 #define B43legacy_OFDM_RATE_6MB         12
 264 #define B43legacy_OFDM_RATE_9MB         18
 265 #define B43legacy_OFDM_RATE_12MB        24
 266 #define B43legacy_OFDM_RATE_18MB        36
 267 #define B43legacy_OFDM_RATE_24MB        48
 268 #define B43legacy_OFDM_RATE_36MB        72
 269 #define B43legacy_OFDM_RATE_48MB        96
 270 #define B43legacy_OFDM_RATE_54MB        108
 271 /* Convert a b43legacy rate value to a rate in 100kbps */
 272 #define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2)
 273
 274
 275 #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT     7
 276 #define B43legacy_DEFAULT_LONG_RETRY_LIMIT      4
 277
 278 /* Max size of a security key */
 279 #define B43legacy_SEC_KEYSIZE           16
 280 /* Security algorithms. */
 281 enum {
 282         B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
 283         B43legacy_SEC_ALGO_WEP40,
 284         B43legacy_SEC_ALGO_TKIP,
 285         B43legacy_SEC_ALGO_AES,
 286         B43legacy_SEC_ALGO_WEP104,
 287         B43legacy_SEC_ALGO_AES_LEGACY,
 288 };
 289
 290 /* Core Information Registers */
 291 #define B43legacy_CIR_BASE                0xf00
 292 #define B43legacy_CIR_SBTPSFLAG           (B43legacy_CIR_BASE + 0x18)
 293 #define B43legacy_CIR_SBIMSTATE           (B43legacy_CIR_BASE + 0x90)
 294 #define B43legacy_CIR_SBINTVEC            (B43legacy_CIR_BASE + 0x94)
 295 #define B43legacy_CIR_SBTMSTATELOW        (B43legacy_CIR_BASE + 0x98)
 296 #define B43legacy_CIR_SBTMSTATEHIGH       (B43legacy_CIR_BASE + 0x9c)
 297 #define B43legacy_CIR_SBIMCONFIGLOW       (B43legacy_CIR_BASE + 0xa8)
 298 #define B43legacy_CIR_SB_ID_HI            (B43legacy_CIR_BASE + 0xfc)
 299
 300 /* sbtmstatehigh state flags */
 301 #define B43legacy_SBTMSTATEHIGH_SERROR          0x00000001
 302 #define B43legacy_SBTMSTATEHIGH_BUSY            0x00000004
 303 #define B43legacy_SBTMSTATEHIGH_TIMEOUT         0x00000020
 304 #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL     0x00010000
 305 #define B43legacy_SBTMSTATEHIGH_COREFLAGS       0x1FFF0000
 306 #define B43legacy_SBTMSTATEHIGH_DMA64BIT        0x10000000
 307 #define B43legacy_SBTMSTATEHIGH_GATEDCLK        0x20000000
 308 #define B43legacy_SBTMSTATEHIGH_BISTFAILED      0x40000000
 309 #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE    0x80000000
 310
 311 /* sbimstate flags */
 312 #define B43legacy_SBIMSTATE_IB_ERROR            0x20000
 313 #define B43legacy_SBIMSTATE_TIMEOUT             0x40000
 314
 315 #define PFX             KBUILD_MODNAME ": "
 316 #ifdef assert
 317 # undef assert
 318 #endif
 319 #ifdef CONFIG_B43LEGACY_DEBUG
 320 # define B43legacy_WARN_ON(expr)                                        \
 321         do {                                                            \
 322                 if (unlikely((expr))) {                                 \
 323                         printk(KERN_INFO PFX "Test (%s) failed at:"     \
 324                                               " %s:%d:%s()\n",          \
 325                                               #expr, __FILE__,          \
 326                                               __LINE__, __FUNCTION__);  \
 327                 }                                                       \
 328         } while (0)
 329 # define B43legacy_BUG_ON(expr)                                         \
 330         do {                                                            \
 331                 if (unlikely((expr))) {                                 \
 332                         printk(KERN_INFO PFX "Test (%s) failed\n",      \
 333                                               #expr);                   \
 334                         BUG_ON(expr);                                   \
 335                 }                                                       \
 336         } while (0)
 337 # define B43legacy_DEBUG        1
 338 #else
 339 # define B43legacy_WARN_ON(x)   do { /* nothing */ } while (0)
 340 # define B43legacy_BUG_ON(x)    do { /* nothing */ } while (0)
 341 # define B43legacy_DEBUG        0
 342 #endif
 343
 344
 345 struct net_device;
 346 struct pci_dev;
 347 struct b43legacy_dmaring;
 348 struct b43legacy_pioqueue;
 349
 350 /* The firmware file header */
 351 #define B43legacy_FW_TYPE_UCODE 'u'
 352 #define B43legacy_FW_TYPE_PCM   'p'
 353 #define B43legacy_FW_TYPE_IV    'i'
 354 struct b43legacy_fw_header {
 355         /* File type */
 356         u8 type;
 357         /* File format version */
 358         u8 ver;
 359         u8 __padding[2];
 360         /* Size of the data. For ucode and PCM this is in bytes.
 361          * For IV this is number-of-ivs. */
 362         __be32 size;
 363 } __attribute__((__packed__));
 364
 365 /* Initial Value file format */
 366 #define B43legacy_IV_OFFSET_MASK        0x7FFF
 367 #define B43legacy_IV_32BIT              0x8000
 368 struct b43legacy_iv {
 369         __be16 offset_size;
 370         union {
 371                 __be16 d16;
 372                 __be32 d32;
 373         } data __attribute__((__packed__));
 374 } __attribute__((__packed__));
 375
 376 #define B43legacy_PHYMODE(phytype)      (1 << (phytype))
 377 #define B43legacy_PHYMODE_B             B43legacy_PHYMODE       \
 378                                         ((B43legacy_PHYTYPE_B))
 379 #define B43legacy_PHYMODE_G             B43legacy_PHYMODE       \
 380                                         ((B43legacy_PHYTYPE_G))
 381
 382 /* Value pair to measure the LocalOscillator. */
 383 struct b43legacy_lopair {
 384         s8 low;
 385         s8 high;
 386         u8 used:1;
 387 };
 388 #define B43legacy_LO_COUNT      (14*4)
 389
 390 struct b43legacy_phy {
 391         /* Possible PHYMODEs on this PHY */
 392         u8 possible_phymodes;
 393         /* GMODE bit enabled in MACCTL? */
 394         bool gmode;
 395         /* Possible ieee80211 subsystem hwmodes for this PHY.
 396          * Which mode is selected, depends on thr GMODE enabled bit */
 397 #define B43legacy_MAX_PHYHWMODES        2
 398         struct ieee80211_hw_mode hwmodes[B43legacy_MAX_PHYHWMODES];
 399
 400         /* Analog Type */
 401         u8 analog;
 402         /* B43legacy_PHYTYPE_ */
 403         u8 type;
 404         /* PHY revision number. */
 405         u8 rev;
 406
 407         u16 antenna_diversity;
 408         u16 savedpctlreg;
 409         /* Radio versioning */
 410         u16 radio_manuf;        /* Radio manufacturer */
 411         u16 radio_ver;          /* Radio version */
 412         u8 calibrated:1;
 413         u8 radio_rev;           /* Radio revision */
 414
 415         bool locked;            /* Only used in b43legacy_phy_{un}lock() */
 416         bool dyn_tssi_tbl;      /* tssi2dbm is kmalloc()ed. */
 417
 418         /* ACI (adjacent channel interference) flags. */
 419         bool aci_enable;
 420         bool aci_wlan_automatic;
 421         bool aci_hw_rssi;
 422
 423         /* Radio switched on/off */
 424         bool radio_on;
 425         struct {
 426                 /* Values saved when turning the radio off.
 427                  * They are needed when turning it on again. */
 428                 bool valid;
 429                 u16 rfover;
 430                 u16 rfoverval;
 431         } radio_off_context;
 432
 433         u16 minlowsig[2];
 434         u16 minlowsigpos[2];
 435
 436         /* LO Measurement Data.
 437          * Use b43legacy_get_lopair() to get a value.
 438          */
 439         struct b43legacy_lopair *_lo_pairs;
 440         /* TSSI to dBm table in use */
 441         const s8 *tssi2dbm;
 442         /* idle TSSI value */
 443         s8 idle_tssi;
 444         /* Target idle TSSI */
 445         int tgt_idle_tssi;
 446         /* Current idle TSSI */
 447         int cur_idle_tssi;
 448
 449         /* LocalOscillator control values. */
 450         struct b43legacy_txpower_lo_control *lo_control;
 451         /* Values from b43legacy_calc_loopback_gain() */
 452         s16 max_lb_gain;        /* Maximum Loopback gain in hdB */
 453         s16 trsw_rx_gain;       /* TRSW RX gain in hdB */
 454         s16 lna_lod_gain;       /* LNA lod */
 455         s16 lna_gain;           /* LNA */
 456         s16 pga_gain;           /* PGA */
 457
 458         /* PHY lock for core.rev < 3
 459          * This lock is only used by b43legacy_phy_{un}lock()
 460          */
 461         spinlock_t lock;
 462
 463         /* Desired TX power level (in dBm). This is set by the user and
 464          * adjusted in b43legacy_phy_xmitpower(). */
 465         u8 power_level;
 466
 467         /* Values from b43legacy_calc_loopback_gain() */
 468         u16 loopback_gain[2];
 469
 470         /* TX Power control values. */
 471         /* B/G PHY */
 472         struct {
 473                 /* Current Radio Attenuation for TXpower recalculation. */
 474                 u16 rfatt;
 475                 /* Current Baseband Attenuation for TXpower recalculation. */
 476                 u16 bbatt;
 477                 /* Current TXpower control value for TXpower recalculation. */
 478                 u16 txctl1;
 479                 u16 txctl2;
 480         };
 481         /* A PHY */
 482         struct {
 483                 u16 txpwr_offset;
 484         };
 485
 486 #ifdef CONFIG_B43LEGACY_DEBUG
 487         bool manual_txpower_control; /* Manual TX-power control enabled? */
 488 #endif
 489         /* Current Interference Mitigation mode */
 490         int interfmode;
 491         /* Stack of saved values from the Interference Mitigation code.
 492          * Each value in the stack is layed out as follows:
 493          * bit 0-11:  offset
 494          * bit 12-15: register ID
 495          * bit 16-32: value
 496          * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
 497          */
 498 #define B43legacy_INTERFSTACK_SIZE      26
 499         u32 interfstack[B43legacy_INTERFSTACK_SIZE];
 500
 501         /* Saved values from the NRSSI Slope calculation */
 502         s16 nrssi[2];
 503         s32 nrssislope;
 504         /* In memory nrssi lookup table. */
 505         s8 nrssi_lt[64];
 506
 507         /* current channel */
 508         u8 channel;
 509
 510         u16 lofcal;
 511
 512         u16 initval;
 513 };
 514
 515 /* Data structures for DMA transmission, per 80211 core. */
 516 struct b43legacy_dma {
 517         struct b43legacy_dmaring *tx_ring0;
 518         struct b43legacy_dmaring *tx_ring1;
 519         struct b43legacy_dmaring *tx_ring2;
 520         struct b43legacy_dmaring *tx_ring3;
 521         struct b43legacy_dmaring *tx_ring4;
 522         struct b43legacy_dmaring *tx_ring5;
 523
 524         struct b43legacy_dmaring *rx_ring0;
 525         struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */
 526 };
 527
 528 /* Data structures for PIO transmission, per 80211 core. */
 529 struct b43legacy_pio {
 530         struct b43legacy_pioqueue *queue0;
 531         struct b43legacy_pioqueue *queue1;
 532         struct b43legacy_pioqueue *queue2;
 533         struct b43legacy_pioqueue *queue3;
 534 };
 535
 536 /* Context information for a noise calculation (Link Quality). */
 537 struct b43legacy_noise_calculation {
 538         u8 channel_at_start;
 539         bool calculation_running;
 540         u8 nr_samples;
 541         s8 samples[8][4];
 542 };
 543
 544 struct b43legacy_stats {
 545         u8 link_noise;
 546         /* Store the last TX/RX times here for updating the leds. */
 547         unsigned long last_tx;
 548         unsigned long last_rx;
 549 };
 550
 551 struct b43legacy_key {
 552         void *keyconf;
 553         bool enabled;
 554         u8 algorithm;
 555 };
 556
 557 struct b43legacy_wldev;
 558
 559 /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */
 560 struct b43legacy_wl {
 561         /* Pointer to the active wireless device on this chip */
 562         struct b43legacy_wldev *current_dev;
 563         /* Pointer to the ieee80211 hardware data structure */
 564         struct ieee80211_hw *hw;
 565
 566         spinlock_t irq_lock;            /* locks IRQ */
 567         struct mutex mutex;             /* locks wireless core state */
 568         spinlock_t leds_lock;           /* lock for leds */
 569
 570         /* We can only have one operating interface (802.11 core)
 571          * at a time. General information about this interface follows.
 572          */
 573
 574         /* Opaque ID of the operating interface from the ieee80211
 575          * subsystem. Do not modify.
 576          */
 577         int if_id;
 578         /* MAC address (can be NULL). */
 579         u8 mac_addr[ETH_ALEN];
 580         /* Current BSSID (can be NULL). */
 581         u8 bssid[ETH_ALEN];
 582         /* Interface type. (IEEE80211_IF_TYPE_XXX) */
 583         int if_type;
 584         /* Is the card operating in AP, STA or IBSS mode? */
 585         bool operating;
 586         /* filter flags */
 587         unsigned int filter_flags;
 588         /* Stats about the wireless interface */
 589         struct ieee80211_low_level_stats ieee_stats;
 590
 591         struct hwrng rng;
 592         u8 rng_initialized;
 593         char rng_name[30 + 1];
 594
 595         /* List of all wireless devices on this chip */
 596         struct list_head devlist;
 597         u8 nr_devs;
 598 };
 599
 600 /* Pointers to the firmware data and meta information about it. */
 601 struct b43legacy_firmware {
 602         /* Microcode */
 603         const struct firmware *ucode;
 604         /* PCM code */
 605         const struct firmware *pcm;
 606         /* Initial MMIO values for the firmware */
 607         const struct firmware *initvals;
 608         /* Initial MMIO values for the firmware, band-specific */
 609         const struct firmware *initvals_band;
 610         /* Firmware revision */
 611         u16 rev;
 612         /* Firmware patchlevel */
 613         u16 patch;
 614 };
 615
 616 /* Device (802.11 core) initialization status. */
 617 enum {
 618         B43legacy_STAT_UNINIT           = 0, /* Uninitialized. */
 619         B43legacy_STAT_INITIALIZED      = 1, /* Initialized, not yet started. */
 620         B43legacy_STAT_STARTED  = 2, /* Up and running. */
 621 };
 622 #define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status)
 623 #define b43legacy_set_status(wldev, stat)       do {            \
 624                 atomic_set(&(wldev)->__init_status, (stat));    \
 625                 smp_wmb();                                      \
 626                                         } while (0)
 627
 628 /* *** ---   HOW LOCKING WORKS IN B43legacy   --- ***
 629  *
 630  * You should always acquire both, wl->mutex and wl->irq_lock unless:
 631  * - You don't need to acquire wl->irq_lock, if the interface is stopped.
 632  * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
 633  *   and packet TX path (and _ONLY_ there.)
 634  */
 635
 636 /* Data structure for one wireless device (802.11 core) */
 637 struct b43legacy_wldev {
 638         struct ssb_device *dev;
 639         struct b43legacy_wl *wl;
 640
 641         /* The device initialization status.
 642          * Use b43legacy_status() to query. */
 643         atomic_t __init_status;
 644         /* Saved init status for handling suspend. */
 645         int suspend_init_status;
 646
 647         bool __using_pio;       /* Using pio rather than dma. */
 648         bool bad_frames_preempt;/* Use "Bad Frames Preemption". */
 649         bool reg124_set_0x4;    /* Variable to keep track of IRQ. */
 650         bool short_preamble;    /* TRUE if using short preamble. */
 651         bool short_slot;        /* TRUE if using short slot timing. */
 652         bool radio_hw_enable;   /* State of radio hardware enable bit. */
 653
 654         /* PHY/Radio device. */
 655         struct b43legacy_phy phy;
 656         union {
 657                 /* DMA engines. */
 658                 struct b43legacy_dma dma;
 659                 /* PIO engines. */
 660                 struct b43legacy_pio pio;
 661         };
 662
 663         /* Various statistics about the physical device. */
 664         struct b43legacy_stats stats;
 665
 666 #define B43legacy_NR_LEDS               4
 667         struct b43legacy_led leds[B43legacy_NR_LEDS];
 668
 669         /* Reason code of the last interrupt. */
 670         u32 irq_reason;
 671         u32 dma_reason[6];
 672         /* saved irq enable/disable state bitfield. */
 673         u32 irq_savedstate;
 674         /* Link Quality calculation context. */
 675         struct b43legacy_noise_calculation noisecalc;
 676         /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
 677         int mac_suspended;
 678
 679         /* Interrupt Service Routine tasklet (bottom-half) */
 680         struct tasklet_struct isr_tasklet;
 681
 682         /* Periodic tasks */
 683         struct delayed_work periodic_work;
 684         unsigned int periodic_state;
 685
 686         struct work_struct restart_work;
 687
 688         /* encryption/decryption */
 689         u16 ktp; /* Key table pointer */
 690         u8 max_nr_keys;
 691         struct b43legacy_key key[58];
 692
 693         /* Cached beacon template while uploading the template. */
 694         struct sk_buff *cached_beacon;
 695
 696         /* Firmware data */
 697         struct b43legacy_firmware fw;
 698
 699         /* Devicelist in struct b43legacy_wl (all 802.11 cores) */
 700         struct list_head list;
 701
 702         /* Debugging stuff follows. */
 703 #ifdef CONFIG_B43LEGACY_DEBUG
 704         struct b43legacy_dfsentry *dfsentry;
 705 #endif
 706 };
 707
 708
 709 static inline
 710 struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw)
 711 {
 712         return hw->priv;
 713 }
 714
 715 /* Helper function, which returns a boolean.
 716  * TRUE, if PIO is used; FALSE, if DMA is used.
 717  */
 718 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
 719 static inline
 720 int b43legacy_using_pio(struct b43legacy_wldev *dev)
 721 {
 722         return dev->__using_pio;
 723 }
 724 #elif defined(CONFIG_B43LEGACY_DMA)
 725 static inline
 726 int b43legacy_using_pio(struct b43legacy_wldev *dev)
 727 {
 728         return 0;
 729 }
 730 #elif defined(CONFIG_B43LEGACY_PIO)
 731 static inline
 732 int b43legacy_using_pio(struct b43legacy_wldev *dev)
 733 {
 734         return 1;
 735 }
 736 #else
 737 # error "Using neither DMA nor PIO? Confused..."
 738 #endif
 739
 740
 741 static inline
 742 struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev)
 743 {
 744         struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 745         return ssb_get_drvdata(ssb_dev);
 746 }
 747
 748 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
 749 static inline
 750 int b43legacy_is_mode(struct b43legacy_wl *wl, int type)
 751 {
 752         return (wl->operating &&
 753                 wl->if_type == type);
 754 }
 755
 756 static inline
 757 bool is_bcm_board_vendor(struct b43legacy_wldev *dev)
 758 {
 759         return  (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM);
 760 }
 761
 762 static inline
 763 u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset)
 764 {
 765         return ssb_read16(dev->dev, offset);
 766 }
 767
 768 static inline
 769 void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value)
 770 {
 771         ssb_write16(dev->dev, offset, value);
 772 }
 773
 774 static inline
 775 u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset)
 776 {
 777         return ssb_read32(dev->dev, offset);
 778 }
 779
 780 static inline
 781 void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value)
 782 {
 783         ssb_write32(dev->dev, offset, value);
 784 }
 785
 786 static inline
 787 struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy,
 788                                               u16 radio_attenuation,
 789                                               u16 baseband_attenuation)
 790 {
 791         return phy->_lo_pairs + (radio_attenuation
 792                         + 14 * (baseband_attenuation / 2));
 793 }
 794
 795
 796
 797 /* Message printing */
 798 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
 799                 __attribute__((format(printf, 2, 3)));
 800 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
 801                 __attribute__((format(printf, 2, 3)));
 802 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
 803                 __attribute__((format(printf, 2, 3)));
 804 #if B43legacy_DEBUG
 805 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
 806                 __attribute__((format(printf, 2, 3)));
 807 #else /* DEBUG */
 808 # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)
 809 #endif /* DEBUG */
 810
 811
 812 /** Limit a value between two limits */
 813 #ifdef limit_value
 814 # undef limit_value
 815 #endif
 816 #define limit_value(value, min, max)  \
 817         ({                                              \
 818                 typeof(value) __value = (value);        \
 819                 typeof(value) __min = (min);            \
 820                 typeof(value) __max = (max);            \
 821                 if (__value < __min)                    \
 822                         __value = __min;                \
 823                 else if (__value > __max)               \
 824                         __value = __max;                \
 825                 __value;                                \
 826         })
 827
 828 /* Macros for printing a value in Q5.2 format */
 829 #define Q52_FMT         "%u.%u"
 830 #define Q52_ARG(q52)    ((q52) / 4), (((q52) & 3) * 100 / 4)
 831
 832 #endif /* B43legacy_H_ */