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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / wireless / b43legacy / dma.c
1 /*
2
3 Broadcom B43legacy wireless driver
4
5 DMA ringbuffer and descriptor allocation/management
6
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
12
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
17
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
22
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
27
28 */
29
30 #include "b43legacy.h"
31 #include "dma.h"
32 #include "main.h"
33 #include "debugfs.h"
34 #include "xmit.h"
35
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/slab.h>
41 #include <net/dst.h>
42
43 /* 32bit DMA ops. */
44 static
45 struct b43legacy_dmadesc_generic *op32_idx2desc(
46 struct b43legacy_dmaring *ring,
47 int slot,
48 struct b43legacy_dmadesc_meta **meta)
49 {
50 struct b43legacy_dmadesc32 *desc;
51
52 *meta = &(ring->meta[slot]);
53 desc = ring->descbase;
54 desc = &(desc[slot]);
55
56 return (struct b43legacy_dmadesc_generic *)desc;
57 }
58
59 static void op32_fill_descriptor(struct b43legacy_dmaring *ring,
60 struct b43legacy_dmadesc_generic *desc,
61 dma_addr_t dmaaddr, u16 bufsize,
62 int start, int end, int irq)
63 {
64 struct b43legacy_dmadesc32 *descbase = ring->descbase;
65 int slot;
66 u32 ctl;
67 u32 addr;
68 u32 addrext;
69
70 slot = (int)(&(desc->dma32) - descbase);
71 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
72
73 addr = (u32)(dmaaddr & ~SSB_DMA_TRANSLATION_MASK);
74 addrext = (u32)(dmaaddr & SSB_DMA_TRANSLATION_MASK)
75 >> SSB_DMA_TRANSLATION_SHIFT;
76 addr |= ssb_dma_translation(ring->dev->dev);
77 ctl = (bufsize - ring->frameoffset)
78 & B43legacy_DMA32_DCTL_BYTECNT;
79 if (slot == ring->nr_slots - 1)
80 ctl |= B43legacy_DMA32_DCTL_DTABLEEND;
81 if (start)
82 ctl |= B43legacy_DMA32_DCTL_FRAMESTART;
83 if (end)
84 ctl |= B43legacy_DMA32_DCTL_FRAMEEND;
85 if (irq)
86 ctl |= B43legacy_DMA32_DCTL_IRQ;
87 ctl |= (addrext << B43legacy_DMA32_DCTL_ADDREXT_SHIFT)
88 & B43legacy_DMA32_DCTL_ADDREXT_MASK;
89
90 desc->dma32.control = cpu_to_le32(ctl);
91 desc->dma32.address = cpu_to_le32(addr);
92 }
93
94 static void op32_poke_tx(struct b43legacy_dmaring *ring, int slot)
95 {
96 b43legacy_dma_write(ring, B43legacy_DMA32_TXINDEX,
97 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
98 }
99
100 static void op32_tx_suspend(struct b43legacy_dmaring *ring)
101 {
102 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
103 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
104 | B43legacy_DMA32_TXSUSPEND);
105 }
106
107 static void op32_tx_resume(struct b43legacy_dmaring *ring)
108 {
109 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
110 b43legacy_dma_read(ring, B43legacy_DMA32_TXCTL)
111 & ~B43legacy_DMA32_TXSUSPEND);
112 }
113
114 static int op32_get_current_rxslot(struct b43legacy_dmaring *ring)
115 {
116 u32 val;
117
118 val = b43legacy_dma_read(ring, B43legacy_DMA32_RXSTATUS);
119 val &= B43legacy_DMA32_RXDPTR;
120
121 return (val / sizeof(struct b43legacy_dmadesc32));
122 }
123
124 static void op32_set_current_rxslot(struct b43legacy_dmaring *ring,
125 int slot)
126 {
127 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
128 (u32)(slot * sizeof(struct b43legacy_dmadesc32)));
129 }
130
131 static const struct b43legacy_dma_ops dma32_ops = {
132 .idx2desc = op32_idx2desc,
133 .fill_descriptor = op32_fill_descriptor,
134 .poke_tx = op32_poke_tx,
135 .tx_suspend = op32_tx_suspend,
136 .tx_resume = op32_tx_resume,
137 .get_current_rxslot = op32_get_current_rxslot,
138 .set_current_rxslot = op32_set_current_rxslot,
139 };
140
141 /* 64bit DMA ops. */
142 static
143 struct b43legacy_dmadesc_generic *op64_idx2desc(
144 struct b43legacy_dmaring *ring,
145 int slot,
146 struct b43legacy_dmadesc_meta
147 **meta)
148 {
149 struct b43legacy_dmadesc64 *desc;
150
151 *meta = &(ring->meta[slot]);
152 desc = ring->descbase;
153 desc = &(desc[slot]);
154
155 return (struct b43legacy_dmadesc_generic *)desc;
156 }
157
158 static void op64_fill_descriptor(struct b43legacy_dmaring *ring,
159 struct b43legacy_dmadesc_generic *desc,
160 dma_addr_t dmaaddr, u16 bufsize,
161 int start, int end, int irq)
162 {
163 struct b43legacy_dmadesc64 *descbase = ring->descbase;
164 int slot;
165 u32 ctl0 = 0;
166 u32 ctl1 = 0;
167 u32 addrlo;
168 u32 addrhi;
169 u32 addrext;
170
171 slot = (int)(&(desc->dma64) - descbase);
172 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
173
174 addrlo = (u32)(dmaaddr & 0xFFFFFFFF);
175 addrhi = (((u64)dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK);
176 addrext = (((u64)dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK)
177 >> SSB_DMA_TRANSLATION_SHIFT;
178 addrhi |= ssb_dma_translation(ring->dev->dev);
179 if (slot == ring->nr_slots - 1)
180 ctl0 |= B43legacy_DMA64_DCTL0_DTABLEEND;
181 if (start)
182 ctl0 |= B43legacy_DMA64_DCTL0_FRAMESTART;
183 if (end)
184 ctl0 |= B43legacy_DMA64_DCTL0_FRAMEEND;
185 if (irq)
186 ctl0 |= B43legacy_DMA64_DCTL0_IRQ;
187 ctl1 |= (bufsize - ring->frameoffset)
188 & B43legacy_DMA64_DCTL1_BYTECNT;
189 ctl1 |= (addrext << B43legacy_DMA64_DCTL1_ADDREXT_SHIFT)
190 & B43legacy_DMA64_DCTL1_ADDREXT_MASK;
191
192 desc->dma64.control0 = cpu_to_le32(ctl0);
193 desc->dma64.control1 = cpu_to_le32(ctl1);
194 desc->dma64.address_low = cpu_to_le32(addrlo);
195 desc->dma64.address_high = cpu_to_le32(addrhi);
196 }
197
198 static void op64_poke_tx(struct b43legacy_dmaring *ring, int slot)
199 {
200 b43legacy_dma_write(ring, B43legacy_DMA64_TXINDEX,
201 (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
202 }
203
204 static void op64_tx_suspend(struct b43legacy_dmaring *ring)
205 {
206 b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
207 b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
208 | B43legacy_DMA64_TXSUSPEND);
209 }
210
211 static void op64_tx_resume(struct b43legacy_dmaring *ring)
212 {
213 b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
214 b43legacy_dma_read(ring, B43legacy_DMA64_TXCTL)
215 & ~B43legacy_DMA64_TXSUSPEND);
216 }
217
218 static int op64_get_current_rxslot(struct b43legacy_dmaring *ring)
219 {
220 u32 val;
221
222 val = b43legacy_dma_read(ring, B43legacy_DMA64_RXSTATUS);
223 val &= B43legacy_DMA64_RXSTATDPTR;
224
225 return (val / sizeof(struct b43legacy_dmadesc64));
226 }
227
228 static void op64_set_current_rxslot(struct b43legacy_dmaring *ring,
229 int slot)
230 {
231 b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
232 (u32)(slot * sizeof(struct b43legacy_dmadesc64)));
233 }
234
235 static const struct b43legacy_dma_ops dma64_ops = {
236 .idx2desc = op64_idx2desc,
237 .fill_descriptor = op64_fill_descriptor,
238 .poke_tx = op64_poke_tx,
239 .tx_suspend = op64_tx_suspend,
240 .tx_resume = op64_tx_resume,
241 .get_current_rxslot = op64_get_current_rxslot,
242 .set_current_rxslot = op64_set_current_rxslot,
243 };
244
245
246 static inline int free_slots(struct b43legacy_dmaring *ring)
247 {
248 return (ring->nr_slots - ring->used_slots);
249 }
250
251 static inline int next_slot(struct b43legacy_dmaring *ring, int slot)
252 {
253 B43legacy_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1));
254 if (slot == ring->nr_slots - 1)
255 return 0;
256 return slot + 1;
257 }
258
259 static inline int prev_slot(struct b43legacy_dmaring *ring, int slot)
260 {
261 B43legacy_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1));
262 if (slot == 0)
263 return ring->nr_slots - 1;
264 return slot - 1;
265 }
266
267 #ifdef CONFIG_B43LEGACY_DEBUG
268 static void update_max_used_slots(struct b43legacy_dmaring *ring,
269 int current_used_slots)
270 {
271 if (current_used_slots <= ring->max_used_slots)
272 return;
273 ring->max_used_slots = current_used_slots;
274 if (b43legacy_debug(ring->dev, B43legacy_DBG_DMAVERBOSE))
275 b43legacydbg(ring->dev->wl,
276 "max_used_slots increased to %d on %s ring %d\n",
277 ring->max_used_slots,
278 ring->tx ? "TX" : "RX",
279 ring->index);
280 }
281 #else
282 static inline
283 void update_max_used_slots(struct b43legacy_dmaring *ring,
284 int current_used_slots)
285 { }
286 #endif /* DEBUG */
287
288 /* Request a slot for usage. */
289 static inline
290 int request_slot(struct b43legacy_dmaring *ring)
291 {
292 int slot;
293
294 B43legacy_WARN_ON(!ring->tx);
295 B43legacy_WARN_ON(ring->stopped);
296 B43legacy_WARN_ON(free_slots(ring) == 0);
297
298 slot = next_slot(ring, ring->current_slot);
299 ring->current_slot = slot;
300 ring->used_slots++;
301
302 update_max_used_slots(ring, ring->used_slots);
303
304 return slot;
305 }
306
307 /* Mac80211-queue to b43legacy-ring mapping */
308 static struct b43legacy_dmaring *priority_to_txring(
309 struct b43legacy_wldev *dev,
310 int queue_priority)
311 {
312 struct b43legacy_dmaring *ring;
313
314 /*FIXME: For now we always run on TX-ring-1 */
315 return dev->dma.tx_ring1;
316
317 /* 0 = highest priority */
318 switch (queue_priority) {
319 default:
320 B43legacy_WARN_ON(1);
321 /* fallthrough */
322 case 0:
323 ring = dev->dma.tx_ring3;
324 break;
325 case 1:
326 ring = dev->dma.tx_ring2;
327 break;
328 case 2:
329 ring = dev->dma.tx_ring1;
330 break;
331 case 3:
332 ring = dev->dma.tx_ring0;
333 break;
334 case 4:
335 ring = dev->dma.tx_ring4;
336 break;
337 case 5:
338 ring = dev->dma.tx_ring5;
339 break;
340 }
341
342 return ring;
343 }
344
345 /* Bcm4301-ring to mac80211-queue mapping */
346 static inline int txring_to_priority(struct b43legacy_dmaring *ring)
347 {
348 static const u8 idx_to_prio[] =
349 { 3, 2, 1, 0, 4, 5, };
350
351 /*FIXME: have only one queue, for now */
352 return 0;
353
354 return idx_to_prio[ring->index];
355 }
356
357
358 static u16 b43legacy_dmacontroller_base(enum b43legacy_dmatype type,
359 int controller_idx)
360 {
361 static const u16 map64[] = {
362 B43legacy_MMIO_DMA64_BASE0,
363 B43legacy_MMIO_DMA64_BASE1,
364 B43legacy_MMIO_DMA64_BASE2,
365 B43legacy_MMIO_DMA64_BASE3,
366 B43legacy_MMIO_DMA64_BASE4,
367 B43legacy_MMIO_DMA64_BASE5,
368 };
369 static const u16 map32[] = {
370 B43legacy_MMIO_DMA32_BASE0,
371 B43legacy_MMIO_DMA32_BASE1,
372 B43legacy_MMIO_DMA32_BASE2,
373 B43legacy_MMIO_DMA32_BASE3,
374 B43legacy_MMIO_DMA32_BASE4,
375 B43legacy_MMIO_DMA32_BASE5,
376 };
377
378 if (type == B43legacy_DMA_64BIT) {
379 B43legacy_WARN_ON(!(controller_idx >= 0 &&
380 controller_idx < ARRAY_SIZE(map64)));
381 return map64[controller_idx];
382 }
383 B43legacy_WARN_ON(!(controller_idx >= 0 &&
384 controller_idx < ARRAY_SIZE(map32)));
385 return map32[controller_idx];
386 }
387
388 static inline
389 dma_addr_t map_descbuffer(struct b43legacy_dmaring *ring,
390 unsigned char *buf,
391 size_t len,
392 int tx)
393 {
394 dma_addr_t dmaaddr;
395
396 if (tx)
397 dmaaddr = ssb_dma_map_single(ring->dev->dev,
398 buf, len,
399 DMA_TO_DEVICE);
400 else
401 dmaaddr = ssb_dma_map_single(ring->dev->dev,
402 buf, len,
403 DMA_FROM_DEVICE);
404
405 return dmaaddr;
406 }
407
408 static inline
409 void unmap_descbuffer(struct b43legacy_dmaring *ring,
410 dma_addr_t addr,
411 size_t len,
412 int tx)
413 {
414 if (tx)
415 ssb_dma_unmap_single(ring->dev->dev,
416 addr, len,
417 DMA_TO_DEVICE);
418 else
419 ssb_dma_unmap_single(ring->dev->dev,
420 addr, len,
421 DMA_FROM_DEVICE);
422 }
423
424 static inline
425 void sync_descbuffer_for_cpu(struct b43legacy_dmaring *ring,
426 dma_addr_t addr,
427 size_t len)
428 {
429 B43legacy_WARN_ON(ring->tx);
430
431 ssb_dma_sync_single_for_cpu(ring->dev->dev,
432 addr, len, DMA_FROM_DEVICE);
433 }
434
435 static inline
436 void sync_descbuffer_for_device(struct b43legacy_dmaring *ring,
437 dma_addr_t addr,
438 size_t len)
439 {
440 B43legacy_WARN_ON(ring->tx);
441
442 ssb_dma_sync_single_for_device(ring->dev->dev,
443 addr, len, DMA_FROM_DEVICE);
444 }
445
446 static inline
447 void free_descriptor_buffer(struct b43legacy_dmaring *ring,
448 struct b43legacy_dmadesc_meta *meta,
449 int irq_context)
450 {
451 if (meta->skb) {
452 if (irq_context)
453 dev_kfree_skb_irq(meta->skb);
454 else
455 dev_kfree_skb(meta->skb);
456 meta->skb = NULL;
457 }
458 }
459
460 static int alloc_ringmemory(struct b43legacy_dmaring *ring)
461 {
462 /* GFP flags must match the flags in free_ringmemory()! */
463 ring->descbase = ssb_dma_alloc_consistent(ring->dev->dev,
464 B43legacy_DMA_RINGMEMSIZE,
465 &(ring->dmabase),
466 GFP_KERNEL);
467 if (!ring->descbase) {
468 b43legacyerr(ring->dev->wl, "DMA ringmemory allocation"
469 " failed\n");
470 return -ENOMEM;
471 }
472 memset(ring->descbase, 0, B43legacy_DMA_RINGMEMSIZE);
473
474 return 0;
475 }
476
477 static void free_ringmemory(struct b43legacy_dmaring *ring)
478 {
479 ssb_dma_free_consistent(ring->dev->dev, B43legacy_DMA_RINGMEMSIZE,
480 ring->descbase, ring->dmabase, GFP_KERNEL);
481 }
482
483 /* Reset the RX DMA channel */
484 static int b43legacy_dmacontroller_rx_reset(struct b43legacy_wldev *dev,
485 u16 mmio_base,
486 enum b43legacy_dmatype type)
487 {
488 int i;
489 u32 value;
490 u16 offset;
491
492 might_sleep();
493
494 offset = (type == B43legacy_DMA_64BIT) ?
495 B43legacy_DMA64_RXCTL : B43legacy_DMA32_RXCTL;
496 b43legacy_write32(dev, mmio_base + offset, 0);
497 for (i = 0; i < 10; i++) {
498 offset = (type == B43legacy_DMA_64BIT) ?
499 B43legacy_DMA64_RXSTATUS : B43legacy_DMA32_RXSTATUS;
500 value = b43legacy_read32(dev, mmio_base + offset);
501 if (type == B43legacy_DMA_64BIT) {
502 value &= B43legacy_DMA64_RXSTAT;
503 if (value == B43legacy_DMA64_RXSTAT_DISABLED) {
504 i = -1;
505 break;
506 }
507 } else {
508 value &= B43legacy_DMA32_RXSTATE;
509 if (value == B43legacy_DMA32_RXSTAT_DISABLED) {
510 i = -1;
511 break;
512 }
513 }
514 msleep(1);
515 }
516 if (i != -1) {
517 b43legacyerr(dev->wl, "DMA RX reset timed out\n");
518 return -ENODEV;
519 }
520
521 return 0;
522 }
523
524 /* Reset the RX DMA channel */
525 static int b43legacy_dmacontroller_tx_reset(struct b43legacy_wldev *dev,
526 u16 mmio_base,
527 enum b43legacy_dmatype type)
528 {
529 int i;
530 u32 value;
531 u16 offset;
532
533 might_sleep();
534
535 for (i = 0; i < 10; i++) {
536 offset = (type == B43legacy_DMA_64BIT) ?
537 B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
538 value = b43legacy_read32(dev, mmio_base + offset);
539 if (type == B43legacy_DMA_64BIT) {
540 value &= B43legacy_DMA64_TXSTAT;
541 if (value == B43legacy_DMA64_TXSTAT_DISABLED ||
542 value == B43legacy_DMA64_TXSTAT_IDLEWAIT ||
543 value == B43legacy_DMA64_TXSTAT_STOPPED)
544 break;
545 } else {
546 value &= B43legacy_DMA32_TXSTATE;
547 if (value == B43legacy_DMA32_TXSTAT_DISABLED ||
548 value == B43legacy_DMA32_TXSTAT_IDLEWAIT ||
549 value == B43legacy_DMA32_TXSTAT_STOPPED)
550 break;
551 }
552 msleep(1);
553 }
554 offset = (type == B43legacy_DMA_64BIT) ? B43legacy_DMA64_TXCTL :
555 B43legacy_DMA32_TXCTL;
556 b43legacy_write32(dev, mmio_base + offset, 0);
557 for (i = 0; i < 10; i++) {
558 offset = (type == B43legacy_DMA_64BIT) ?
559 B43legacy_DMA64_TXSTATUS : B43legacy_DMA32_TXSTATUS;
560 value = b43legacy_read32(dev, mmio_base + offset);
561 if (type == B43legacy_DMA_64BIT) {
562 value &= B43legacy_DMA64_TXSTAT;
563 if (value == B43legacy_DMA64_TXSTAT_DISABLED) {
564 i = -1;
565 break;
566 }
567 } else {
568 value &= B43legacy_DMA32_TXSTATE;
569 if (value == B43legacy_DMA32_TXSTAT_DISABLED) {
570 i = -1;
571 break;
572 }
573 }
574 msleep(1);
575 }
576 if (i != -1) {
577 b43legacyerr(dev->wl, "DMA TX reset timed out\n");
578 return -ENODEV;
579 }
580 /* ensure the reset is completed. */
581 msleep(1);
582
583 return 0;
584 }
585
586 /* Check if a DMA mapping address is invalid. */
587 static bool b43legacy_dma_mapping_error(struct b43legacy_dmaring *ring,
588 dma_addr_t addr,
589 size_t buffersize,
590 bool dma_to_device)
591 {
592 if (unlikely(ssb_dma_mapping_error(ring->dev->dev, addr)))
593 return 1;
594
595 switch (ring->type) {
596 case B43legacy_DMA_30BIT:
597 if ((u64)addr + buffersize > (1ULL << 30))
598 goto address_error;
599 break;
600 case B43legacy_DMA_32BIT:
601 if ((u64)addr + buffersize > (1ULL << 32))
602 goto address_error;
603 break;
604 case B43legacy_DMA_64BIT:
605 /* Currently we can't have addresses beyond 64 bits in the kernel. */
606 break;
607 }
608
609 /* The address is OK. */
610 return 0;
611
612 address_error:
613 /* We can't support this address. Unmap it again. */
614 unmap_descbuffer(ring, addr, buffersize, dma_to_device);
615
616 return 1;
617 }
618
619 static int setup_rx_descbuffer(struct b43legacy_dmaring *ring,
620 struct b43legacy_dmadesc_generic *desc,
621 struct b43legacy_dmadesc_meta *meta,
622 gfp_t gfp_flags)
623 {
624 struct b43legacy_rxhdr_fw3 *rxhdr;
625 struct b43legacy_hwtxstatus *txstat;
626 dma_addr_t dmaaddr;
627 struct sk_buff *skb;
628
629 B43legacy_WARN_ON(ring->tx);
630
631 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
632 if (unlikely(!skb))
633 return -ENOMEM;
634 dmaaddr = map_descbuffer(ring, skb->data,
635 ring->rx_buffersize, 0);
636 if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
637 /* ugh. try to realloc in zone_dma */
638 gfp_flags |= GFP_DMA;
639
640 dev_kfree_skb_any(skb);
641
642 skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
643 if (unlikely(!skb))
644 return -ENOMEM;
645 dmaaddr = map_descbuffer(ring, skb->data,
646 ring->rx_buffersize, 0);
647 }
648
649 if (b43legacy_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) {
650 dev_kfree_skb_any(skb);
651 return -EIO;
652 }
653
654 meta->skb = skb;
655 meta->dmaaddr = dmaaddr;
656 ring->ops->fill_descriptor(ring, desc, dmaaddr,
657 ring->rx_buffersize, 0, 0, 0);
658
659 rxhdr = (struct b43legacy_rxhdr_fw3 *)(skb->data);
660 rxhdr->frame_len = 0;
661 txstat = (struct b43legacy_hwtxstatus *)(skb->data);
662 txstat->cookie = 0;
663
664 return 0;
665 }
666
667 /* Allocate the initial descbuffers.
668 * This is used for an RX ring only.
669 */
670 static int alloc_initial_descbuffers(struct b43legacy_dmaring *ring)
671 {
672 int i;
673 int err = -ENOMEM;
674 struct b43legacy_dmadesc_generic *desc;
675 struct b43legacy_dmadesc_meta *meta;
676
677 for (i = 0; i < ring->nr_slots; i++) {
678 desc = ring->ops->idx2desc(ring, i, &meta);
679
680 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
681 if (err) {
682 b43legacyerr(ring->dev->wl,
683 "Failed to allocate initial descbuffers\n");
684 goto err_unwind;
685 }
686 }
687 mb(); /* all descbuffer setup before next line */
688 ring->used_slots = ring->nr_slots;
689 err = 0;
690 out:
691 return err;
692
693 err_unwind:
694 for (i--; i >= 0; i--) {
695 desc = ring->ops->idx2desc(ring, i, &meta);
696
697 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
698 dev_kfree_skb(meta->skb);
699 }
700 goto out;
701 }
702
703 /* Do initial setup of the DMA controller.
704 * Reset the controller, write the ring busaddress
705 * and switch the "enable" bit on.
706 */
707 static int dmacontroller_setup(struct b43legacy_dmaring *ring)
708 {
709 int err = 0;
710 u32 value;
711 u32 addrext;
712 u32 trans = ssb_dma_translation(ring->dev->dev);
713
714 if (ring->tx) {
715 if (ring->type == B43legacy_DMA_64BIT) {
716 u64 ringbase = (u64)(ring->dmabase);
717
718 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
719 >> SSB_DMA_TRANSLATION_SHIFT;
720 value = B43legacy_DMA64_TXENABLE;
721 value |= (addrext << B43legacy_DMA64_TXADDREXT_SHIFT)
722 & B43legacy_DMA64_TXADDREXT_MASK;
723 b43legacy_dma_write(ring, B43legacy_DMA64_TXCTL,
724 value);
725 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO,
726 (ringbase & 0xFFFFFFFF));
727 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI,
728 ((ringbase >> 32)
729 & ~SSB_DMA_TRANSLATION_MASK)
730 | trans);
731 } else {
732 u32 ringbase = (u32)(ring->dmabase);
733
734 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
735 >> SSB_DMA_TRANSLATION_SHIFT;
736 value = B43legacy_DMA32_TXENABLE;
737 value |= (addrext << B43legacy_DMA32_TXADDREXT_SHIFT)
738 & B43legacy_DMA32_TXADDREXT_MASK;
739 b43legacy_dma_write(ring, B43legacy_DMA32_TXCTL,
740 value);
741 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING,
742 (ringbase &
743 ~SSB_DMA_TRANSLATION_MASK)
744 | trans);
745 }
746 } else {
747 err = alloc_initial_descbuffers(ring);
748 if (err)
749 goto out;
750 if (ring->type == B43legacy_DMA_64BIT) {
751 u64 ringbase = (u64)(ring->dmabase);
752
753 addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK)
754 >> SSB_DMA_TRANSLATION_SHIFT;
755 value = (ring->frameoffset <<
756 B43legacy_DMA64_RXFROFF_SHIFT);
757 value |= B43legacy_DMA64_RXENABLE;
758 value |= (addrext << B43legacy_DMA64_RXADDREXT_SHIFT)
759 & B43legacy_DMA64_RXADDREXT_MASK;
760 b43legacy_dma_write(ring, B43legacy_DMA64_RXCTL,
761 value);
762 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO,
763 (ringbase & 0xFFFFFFFF));
764 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI,
765 ((ringbase >> 32) &
766 ~SSB_DMA_TRANSLATION_MASK) |
767 trans);
768 b43legacy_dma_write(ring, B43legacy_DMA64_RXINDEX,
769 200);
770 } else {
771 u32 ringbase = (u32)(ring->dmabase);
772
773 addrext = (ringbase & SSB_DMA_TRANSLATION_MASK)
774 >> SSB_DMA_TRANSLATION_SHIFT;
775 value = (ring->frameoffset <<
776 B43legacy_DMA32_RXFROFF_SHIFT);
777 value |= B43legacy_DMA32_RXENABLE;
778 value |= (addrext <<
779 B43legacy_DMA32_RXADDREXT_SHIFT)
780 & B43legacy_DMA32_RXADDREXT_MASK;
781 b43legacy_dma_write(ring, B43legacy_DMA32_RXCTL,
782 value);
783 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING,
784 (ringbase &
785 ~SSB_DMA_TRANSLATION_MASK)
786 | trans);
787 b43legacy_dma_write(ring, B43legacy_DMA32_RXINDEX,
788 200);
789 }
790 }
791
792 out:
793 return err;
794 }
795
796 /* Shutdown the DMA controller. */
797 static void dmacontroller_cleanup(struct b43legacy_dmaring *ring)
798 {
799 if (ring->tx) {
800 b43legacy_dmacontroller_tx_reset(ring->dev, ring->mmio_base,
801 ring->type);
802 if (ring->type == B43legacy_DMA_64BIT) {
803 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGLO, 0);
804 b43legacy_dma_write(ring, B43legacy_DMA64_TXRINGHI, 0);
805 } else
806 b43legacy_dma_write(ring, B43legacy_DMA32_TXRING, 0);
807 } else {
808 b43legacy_dmacontroller_rx_reset(ring->dev, ring->mmio_base,
809 ring->type);
810 if (ring->type == B43legacy_DMA_64BIT) {
811 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGLO, 0);
812 b43legacy_dma_write(ring, B43legacy_DMA64_RXRINGHI, 0);
813 } else
814 b43legacy_dma_write(ring, B43legacy_DMA32_RXRING, 0);
815 }
816 }
817
818 static void free_all_descbuffers(struct b43legacy_dmaring *ring)
819 {
820 struct b43legacy_dmadesc_generic *desc;
821 struct b43legacy_dmadesc_meta *meta;
822 int i;
823
824 if (!ring->used_slots)
825 return;
826 for (i = 0; i < ring->nr_slots; i++) {
827 desc = ring->ops->idx2desc(ring, i, &meta);
828
829 if (!meta->skb) {
830 B43legacy_WARN_ON(!ring->tx);
831 continue;
832 }
833 if (ring->tx)
834 unmap_descbuffer(ring, meta->dmaaddr,
835 meta->skb->len, 1);
836 else
837 unmap_descbuffer(ring, meta->dmaaddr,
838 ring->rx_buffersize, 0);
839 free_descriptor_buffer(ring, meta, 0);
840 }
841 }
842
843 static u64 supported_dma_mask(struct b43legacy_wldev *dev)
844 {
845 u32 tmp;
846 u16 mmio_base;
847
848 tmp = b43legacy_read32(dev, SSB_TMSHIGH);
849 if (tmp & SSB_TMSHIGH_DMA64)
850 return DMA_BIT_MASK(64);
851 mmio_base = b43legacy_dmacontroller_base(0, 0);
852 b43legacy_write32(dev,
853 mmio_base + B43legacy_DMA32_TXCTL,
854 B43legacy_DMA32_TXADDREXT_MASK);
855 tmp = b43legacy_read32(dev, mmio_base +
856 B43legacy_DMA32_TXCTL);
857 if (tmp & B43legacy_DMA32_TXADDREXT_MASK)
858 return DMA_BIT_MASK(32);
859
860 return DMA_BIT_MASK(30);
861 }
862
863 static enum b43legacy_dmatype dma_mask_to_engine_type(u64 dmamask)
864 {
865 if (dmamask == DMA_BIT_MASK(30))
866 return B43legacy_DMA_30BIT;
867 if (dmamask == DMA_BIT_MASK(32))
868 return B43legacy_DMA_32BIT;
869 if (dmamask == DMA_BIT_MASK(64))
870 return B43legacy_DMA_64BIT;
871 B43legacy_WARN_ON(1);
872 return B43legacy_DMA_30BIT;
873 }
874
875 /* Main initialization function. */
876 static
877 struct b43legacy_dmaring *b43legacy_setup_dmaring(struct b43legacy_wldev *dev,
878 int controller_index,
879 int for_tx,
880 enum b43legacy_dmatype type)
881 {
882 struct b43legacy_dmaring *ring;
883 int err;
884 int nr_slots;
885 dma_addr_t dma_test;
886
887 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
888 if (!ring)
889 goto out;
890 ring->type = type;
891 ring->dev = dev;
892
893 nr_slots = B43legacy_RXRING_SLOTS;
894 if (for_tx)
895 nr_slots = B43legacy_TXRING_SLOTS;
896
897 ring->meta = kcalloc(nr_slots, sizeof(struct b43legacy_dmadesc_meta),
898 GFP_KERNEL);
899 if (!ring->meta)
900 goto err_kfree_ring;
901 if (for_tx) {
902 ring->txhdr_cache = kcalloc(nr_slots,
903 sizeof(struct b43legacy_txhdr_fw3),
904 GFP_KERNEL);
905 if (!ring->txhdr_cache)
906 goto err_kfree_meta;
907
908 /* test for ability to dma to txhdr_cache */
909 dma_test = ssb_dma_map_single(dev->dev, ring->txhdr_cache,
910 sizeof(struct b43legacy_txhdr_fw3),
911 DMA_TO_DEVICE);
912
913 if (b43legacy_dma_mapping_error(ring, dma_test,
914 sizeof(struct b43legacy_txhdr_fw3), 1)) {
915 /* ugh realloc */
916 kfree(ring->txhdr_cache);
917 ring->txhdr_cache = kcalloc(nr_slots,
918 sizeof(struct b43legacy_txhdr_fw3),
919 GFP_KERNEL | GFP_DMA);
920 if (!ring->txhdr_cache)
921 goto err_kfree_meta;
922
923 dma_test = ssb_dma_map_single(dev->dev,
924 ring->txhdr_cache,
925 sizeof(struct b43legacy_txhdr_fw3),
926 DMA_TO_DEVICE);
927
928 if (b43legacy_dma_mapping_error(ring, dma_test,
929 sizeof(struct b43legacy_txhdr_fw3), 1))
930 goto err_kfree_txhdr_cache;
931 }
932
933 ssb_dma_unmap_single(dev->dev, dma_test,
934 sizeof(struct b43legacy_txhdr_fw3),
935 DMA_TO_DEVICE);
936 }
937
938 ring->nr_slots = nr_slots;
939 ring->mmio_base = b43legacy_dmacontroller_base(type, controller_index);
940 ring->index = controller_index;
941 if (type == B43legacy_DMA_64BIT)
942 ring->ops = &dma64_ops;
943 else
944 ring->ops = &dma32_ops;
945 if (for_tx) {
946 ring->tx = 1;
947 ring->current_slot = -1;
948 } else {
949 if (ring->index == 0) {
950 ring->rx_buffersize = B43legacy_DMA0_RX_BUFFERSIZE;
951 ring->frameoffset = B43legacy_DMA0_RX_FRAMEOFFSET;
952 } else if (ring->index == 3) {
953 ring->rx_buffersize = B43legacy_DMA3_RX_BUFFERSIZE;
954 ring->frameoffset = B43legacy_DMA3_RX_FRAMEOFFSET;
955 } else
956 B43legacy_WARN_ON(1);
957 }
958 spin_lock_init(&ring->lock);
959 #ifdef CONFIG_B43LEGACY_DEBUG
960 ring->last_injected_overflow = jiffies;
961 #endif
962
963 err = alloc_ringmemory(ring);
964 if (err)
965 goto err_kfree_txhdr_cache;
966 err = dmacontroller_setup(ring);
967 if (err)
968 goto err_free_ringmemory;
969
970 out:
971 return ring;
972
973 err_free_ringmemory:
974 free_ringmemory(ring);
975 err_kfree_txhdr_cache:
976 kfree(ring->txhdr_cache);
977 err_kfree_meta:
978 kfree(ring->meta);
979 err_kfree_ring:
980 kfree(ring);
981 ring = NULL;
982 goto out;
983 }
984
985 /* Main cleanup function. */
986 static void b43legacy_destroy_dmaring(struct b43legacy_dmaring *ring)
987 {
988 if (!ring)
989 return;
990
991 b43legacydbg(ring->dev->wl, "DMA-%u 0x%04X (%s) max used slots:"
992 " %d/%d\n", (unsigned int)(ring->type), ring->mmio_base,
993 (ring->tx) ? "TX" : "RX", ring->max_used_slots,
994 ring->nr_slots);
995 /* Device IRQs are disabled prior entering this function,
996 * so no need to take care of concurrency with rx handler stuff.
997 */
998 dmacontroller_cleanup(ring);
999 free_all_descbuffers(ring);
1000 free_ringmemory(ring);
1001
1002 kfree(ring->txhdr_cache);
1003 kfree(ring->meta);
1004 kfree(ring);
1005 }
1006
1007 void b43legacy_dma_free(struct b43legacy_wldev *dev)
1008 {
1009 struct b43legacy_dma *dma;
1010
1011 if (b43legacy_using_pio(dev))
1012 return;
1013 dma = &dev->dma;
1014
1015 b43legacy_destroy_dmaring(dma->rx_ring3);
1016 dma->rx_ring3 = NULL;
1017 b43legacy_destroy_dmaring(dma->rx_ring0);
1018 dma->rx_ring0 = NULL;
1019
1020 b43legacy_destroy_dmaring(dma->tx_ring5);
1021 dma->tx_ring5 = NULL;
1022 b43legacy_destroy_dmaring(dma->tx_ring4);
1023 dma->tx_ring4 = NULL;
1024 b43legacy_destroy_dmaring(dma->tx_ring3);
1025 dma->tx_ring3 = NULL;
1026 b43legacy_destroy_dmaring(dma->tx_ring2);
1027 dma->tx_ring2 = NULL;
1028 b43legacy_destroy_dmaring(dma->tx_ring1);
1029 dma->tx_ring1 = NULL;
1030 b43legacy_destroy_dmaring(dma->tx_ring0);
1031 dma->tx_ring0 = NULL;
1032 }
1033
1034 static int b43legacy_dma_set_mask(struct b43legacy_wldev *dev, u64 mask)
1035 {
1036 u64 orig_mask = mask;
1037 bool fallback = 0;
1038 int err;
1039
1040 /* Try to set the DMA mask. If it fails, try falling back to a
1041 * lower mask, as we can always also support a lower one. */
1042 while (1) {
1043 err = ssb_dma_set_mask(dev->dev, mask);
1044 if (!err)
1045 break;
1046 if (mask == DMA_BIT_MASK(64)) {
1047 mask = DMA_BIT_MASK(32);
1048 fallback = 1;
1049 continue;
1050 }
1051 if (mask == DMA_BIT_MASK(32)) {
1052 mask = DMA_BIT_MASK(30);
1053 fallback = 1;
1054 continue;
1055 }
1056 b43legacyerr(dev->wl, "The machine/kernel does not support "
1057 "the required %u-bit DMA mask\n",
1058 (unsigned int)dma_mask_to_engine_type(orig_mask));
1059 return -EOPNOTSUPP;
1060 }
1061 if (fallback) {
1062 b43legacyinfo(dev->wl, "DMA mask fallback from %u-bit to %u-"
1063 "bit\n",
1064 (unsigned int)dma_mask_to_engine_type(orig_mask),
1065 (unsigned int)dma_mask_to_engine_type(mask));
1066 }
1067
1068 return 0;
1069 }
1070
1071 int b43legacy_dma_init(struct b43legacy_wldev *dev)
1072 {
1073 struct b43legacy_dma *dma = &dev->dma;
1074 struct b43legacy_dmaring *ring;
1075 int err;
1076 u64 dmamask;
1077 enum b43legacy_dmatype type;
1078
1079 dmamask = supported_dma_mask(dev);
1080 type = dma_mask_to_engine_type(dmamask);
1081 err = b43legacy_dma_set_mask(dev, dmamask);
1082 if (err) {
1083 #ifdef CONFIG_B43LEGACY_PIO
1084 b43legacywarn(dev->wl, "DMA for this device not supported. "
1085 "Falling back to PIO\n");
1086 dev->__using_pio = 1;
1087 return -EAGAIN;
1088 #else
1089 b43legacyerr(dev->wl, "DMA for this device not supported and "
1090 "no PIO support compiled in\n");
1091 return -EOPNOTSUPP;
1092 #endif
1093 }
1094
1095 err = -ENOMEM;
1096 /* setup TX DMA channels. */
1097 ring = b43legacy_setup_dmaring(dev, 0, 1, type);
1098 if (!ring)
1099 goto out;
1100 dma->tx_ring0 = ring;
1101
1102 ring = b43legacy_setup_dmaring(dev, 1, 1, type);
1103 if (!ring)
1104 goto err_destroy_tx0;
1105 dma->tx_ring1 = ring;
1106
1107 ring = b43legacy_setup_dmaring(dev, 2, 1, type);
1108 if (!ring)
1109 goto err_destroy_tx1;
1110 dma->tx_ring2 = ring;
1111
1112 ring = b43legacy_setup_dmaring(dev, 3, 1, type);
1113 if (!ring)
1114 goto err_destroy_tx2;
1115 dma->tx_ring3 = ring;
1116
1117 ring = b43legacy_setup_dmaring(dev, 4, 1, type);
1118 if (!ring)
1119 goto err_destroy_tx3;
1120 dma->tx_ring4 = ring;
1121
1122 ring = b43legacy_setup_dmaring(dev, 5, 1, type);
1123 if (!ring)
1124 goto err_destroy_tx4;
1125 dma->tx_ring5 = ring;
1126
1127 /* setup RX DMA channels. */
1128 ring = b43legacy_setup_dmaring(dev, 0, 0, type);
1129 if (!ring)
1130 goto err_destroy_tx5;
1131 dma->rx_ring0 = ring;
1132
1133 if (dev->dev->id.revision < 5) {
1134 ring = b43legacy_setup_dmaring(dev, 3, 0, type);
1135 if (!ring)
1136 goto err_destroy_rx0;
1137 dma->rx_ring3 = ring;
1138 }
1139
1140 b43legacydbg(dev->wl, "%u-bit DMA initialized\n", (unsigned int)type);
1141 err = 0;
1142 out:
1143 return err;
1144
1145 err_destroy_rx0:
1146 b43legacy_destroy_dmaring(dma->rx_ring0);
1147 dma->rx_ring0 = NULL;
1148 err_destroy_tx5:
1149 b43legacy_destroy_dmaring(dma->tx_ring5);
1150 dma->tx_ring5 = NULL;
1151 err_destroy_tx4:
1152 b43legacy_destroy_dmaring(dma->tx_ring4);
1153 dma->tx_ring4 = NULL;
1154 err_destroy_tx3:
1155 b43legacy_destroy_dmaring(dma->tx_ring3);
1156 dma->tx_ring3 = NULL;
1157 err_destroy_tx2:
1158 b43legacy_destroy_dmaring(dma->tx_ring2);
1159 dma->tx_ring2 = NULL;
1160 err_destroy_tx1:
1161 b43legacy_destroy_dmaring(dma->tx_ring1);
1162 dma->tx_ring1 = NULL;
1163 err_destroy_tx0:
1164 b43legacy_destroy_dmaring(dma->tx_ring0);
1165 dma->tx_ring0 = NULL;
1166 goto out;
1167 }
1168
1169 /* Generate a cookie for the TX header. */
1170 static u16 generate_cookie(struct b43legacy_dmaring *ring,
1171 int slot)
1172 {
1173 u16 cookie = 0x1000;
1174
1175 /* Use the upper 4 bits of the cookie as
1176 * DMA controller ID and store the slot number
1177 * in the lower 12 bits.
1178 * Note that the cookie must never be 0, as this
1179 * is a special value used in RX path.
1180 */
1181 switch (ring->index) {
1182 case 0:
1183 cookie = 0xA000;
1184 break;
1185 case 1:
1186 cookie = 0xB000;
1187 break;
1188 case 2:
1189 cookie = 0xC000;
1190 break;
1191 case 3:
1192 cookie = 0xD000;
1193 break;
1194 case 4:
1195 cookie = 0xE000;
1196 break;
1197 case 5:
1198 cookie = 0xF000;
1199 break;
1200 }
1201 B43legacy_WARN_ON(!(((u16)slot & 0xF000) == 0x0000));
1202 cookie |= (u16)slot;
1203
1204 return cookie;
1205 }
1206
1207 /* Inspect a cookie and find out to which controller/slot it belongs. */
1208 static
1209 struct b43legacy_dmaring *parse_cookie(struct b43legacy_wldev *dev,
1210 u16 cookie, int *slot)
1211 {
1212 struct b43legacy_dma *dma = &dev->dma;
1213 struct b43legacy_dmaring *ring = NULL;
1214
1215 switch (cookie & 0xF000) {
1216 case 0xA000:
1217 ring = dma->tx_ring0;
1218 break;
1219 case 0xB000:
1220 ring = dma->tx_ring1;
1221 break;
1222 case 0xC000:
1223 ring = dma->tx_ring2;
1224 break;
1225 case 0xD000:
1226 ring = dma->tx_ring3;
1227 break;
1228 case 0xE000:
1229 ring = dma->tx_ring4;
1230 break;
1231 case 0xF000:
1232 ring = dma->tx_ring5;
1233 break;
1234 default:
1235 B43legacy_WARN_ON(1);
1236 }
1237 *slot = (cookie & 0x0FFF);
1238 B43legacy_WARN_ON(!(ring && *slot >= 0 && *slot < ring->nr_slots));
1239
1240 return ring;
1241 }
1242
1243 static int dma_tx_fragment(struct b43legacy_dmaring *ring,
1244 struct sk_buff **in_skb)
1245 {
1246 struct sk_buff *skb = *in_skb;
1247 const struct b43legacy_dma_ops *ops = ring->ops;
1248 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1249 u8 *header;
1250 int slot, old_top_slot, old_used_slots;
1251 int err;
1252 struct b43legacy_dmadesc_generic *desc;
1253 struct b43legacy_dmadesc_meta *meta;
1254 struct b43legacy_dmadesc_meta *meta_hdr;
1255 struct sk_buff *bounce_skb;
1256
1257 #define SLOTS_PER_PACKET 2
1258 B43legacy_WARN_ON(skb_shinfo(skb)->nr_frags != 0);
1259
1260 old_top_slot = ring->current_slot;
1261 old_used_slots = ring->used_slots;
1262
1263 /* Get a slot for the header. */
1264 slot = request_slot(ring);
1265 desc = ops->idx2desc(ring, slot, &meta_hdr);
1266 memset(meta_hdr, 0, sizeof(*meta_hdr));
1267
1268 header = &(ring->txhdr_cache[slot * sizeof(
1269 struct b43legacy_txhdr_fw3)]);
1270 err = b43legacy_generate_txhdr(ring->dev, header,
1271 skb->data, skb->len, info,
1272 generate_cookie(ring, slot));
1273 if (unlikely(err)) {
1274 ring->current_slot = old_top_slot;
1275 ring->used_slots = old_used_slots;
1276 return err;
1277 }
1278
1279 meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header,
1280 sizeof(struct b43legacy_txhdr_fw3), 1);
1281 if (b43legacy_dma_mapping_error(ring, meta_hdr->dmaaddr,
1282 sizeof(struct b43legacy_txhdr_fw3), 1)) {
1283 ring->current_slot = old_top_slot;
1284 ring->used_slots = old_used_slots;
1285 return -EIO;
1286 }
1287 ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr,
1288 sizeof(struct b43legacy_txhdr_fw3), 1, 0, 0);
1289
1290 /* Get a slot for the payload. */
1291 slot = request_slot(ring);
1292 desc = ops->idx2desc(ring, slot, &meta);
1293 memset(meta, 0, sizeof(*meta));
1294
1295 meta->skb = skb;
1296 meta->is_last_fragment = 1;
1297
1298 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1299 /* create a bounce buffer in zone_dma on mapping failure. */
1300 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1301 bounce_skb = __dev_alloc_skb(skb->len, GFP_ATOMIC | GFP_DMA);
1302 if (!bounce_skb) {
1303 ring->current_slot = old_top_slot;
1304 ring->used_slots = old_used_slots;
1305 err = -ENOMEM;
1306 goto out_unmap_hdr;
1307 }
1308
1309 memcpy(skb_put(bounce_skb, skb->len), skb->data, skb->len);
1310 memcpy(bounce_skb->cb, skb->cb, sizeof(skb->cb));
1311 bounce_skb->dev = skb->dev;
1312 skb_set_queue_mapping(bounce_skb, skb_get_queue_mapping(skb));
1313 info = IEEE80211_SKB_CB(bounce_skb);
1314
1315 dev_kfree_skb_any(skb);
1316 skb = bounce_skb;
1317 *in_skb = bounce_skb;
1318 meta->skb = skb;
1319 meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
1320 if (b43legacy_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) {
1321 ring->current_slot = old_top_slot;
1322 ring->used_slots = old_used_slots;
1323 err = -EIO;
1324 goto out_free_bounce;
1325 }
1326 }
1327
1328 ops->fill_descriptor(ring, desc, meta->dmaaddr,
1329 skb->len, 0, 1, 1);
1330
1331 wmb(); /* previous stuff MUST be done */
1332 /* Now transfer the whole frame. */
1333 ops->poke_tx(ring, next_slot(ring, slot));
1334 return 0;
1335
1336 out_free_bounce:
1337 dev_kfree_skb_any(skb);
1338 out_unmap_hdr:
1339 unmap_descbuffer(ring, meta_hdr->dmaaddr,
1340 sizeof(struct b43legacy_txhdr_fw3), 1);
1341 return err;
1342 }
1343
1344 static inline
1345 int should_inject_overflow(struct b43legacy_dmaring *ring)
1346 {
1347 #ifdef CONFIG_B43LEGACY_DEBUG
1348 if (unlikely(b43legacy_debug(ring->dev,
1349 B43legacy_DBG_DMAOVERFLOW))) {
1350 /* Check if we should inject another ringbuffer overflow
1351 * to test handling of this situation in the stack. */
1352 unsigned long next_overflow;
1353
1354 next_overflow = ring->last_injected_overflow + HZ;
1355 if (time_after(jiffies, next_overflow)) {
1356 ring->last_injected_overflow = jiffies;
1357 b43legacydbg(ring->dev->wl,
1358 "Injecting TX ring overflow on "
1359 "DMA controller %d\n", ring->index);
1360 return 1;
1361 }
1362 }
1363 #endif /* CONFIG_B43LEGACY_DEBUG */
1364 return 0;
1365 }
1366
1367 int b43legacy_dma_tx(struct b43legacy_wldev *dev,
1368 struct sk_buff *skb)
1369 {
1370 struct b43legacy_dmaring *ring;
1371 struct ieee80211_hdr *hdr;
1372 int err = 0;
1373 unsigned long flags;
1374 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1375
1376 ring = priority_to_txring(dev, skb_get_queue_mapping(skb));
1377 spin_lock_irqsave(&ring->lock, flags);
1378 B43legacy_WARN_ON(!ring->tx);
1379
1380 if (unlikely(ring->stopped)) {
1381 /* We get here only because of a bug in mac80211.
1382 * Because of a race, one packet may be queued after
1383 * the queue is stopped, thus we got called when we shouldn't.
1384 * For now, just refuse the transmit. */
1385 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1386 b43legacyerr(dev->wl, "Packet after queue stopped\n");
1387 err = -ENOSPC;
1388 goto out_unlock;
1389 }
1390
1391 if (unlikely(WARN_ON(free_slots(ring) < SLOTS_PER_PACKET))) {
1392 /* If we get here, we have a real error with the queue
1393 * full, but queues not stopped. */
1394 b43legacyerr(dev->wl, "DMA queue overflow\n");
1395 err = -ENOSPC;
1396 goto out_unlock;
1397 }
1398
1399 /* dma_tx_fragment might reallocate the skb, so invalidate pointers pointing
1400 * into the skb data or cb now. */
1401 hdr = NULL;
1402 info = NULL;
1403 err = dma_tx_fragment(ring, &skb);
1404 if (unlikely(err == -ENOKEY)) {
1405 /* Drop this packet, as we don't have the encryption key
1406 * anymore and must not transmit it unencrypted. */
1407 dev_kfree_skb_any(skb);
1408 err = 0;
1409 goto out_unlock;
1410 }
1411 if (unlikely(err)) {
1412 b43legacyerr(dev->wl, "DMA tx mapping failure\n");
1413 goto out_unlock;
1414 }
1415 if ((free_slots(ring) < SLOTS_PER_PACKET) ||
1416 should_inject_overflow(ring)) {
1417 /* This TX ring is full. */
1418 ieee80211_stop_queue(dev->wl->hw, txring_to_priority(ring));
1419 ring->stopped = 1;
1420 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1421 b43legacydbg(dev->wl, "Stopped TX ring %d\n",
1422 ring->index);
1423 }
1424 out_unlock:
1425 spin_unlock_irqrestore(&ring->lock, flags);
1426
1427 return err;
1428 }
1429
1430 void b43legacy_dma_handle_txstatus(struct b43legacy_wldev *dev,
1431 const struct b43legacy_txstatus *status)
1432 {
1433 const struct b43legacy_dma_ops *ops;
1434 struct b43legacy_dmaring *ring;
1435 struct b43legacy_dmadesc_generic *desc;
1436 struct b43legacy_dmadesc_meta *meta;
1437 int retry_limit;
1438 int slot;
1439
1440 ring = parse_cookie(dev, status->cookie, &slot);
1441 if (unlikely(!ring))
1442 return;
1443 B43legacy_WARN_ON(!irqs_disabled());
1444 spin_lock(&ring->lock);
1445
1446 B43legacy_WARN_ON(!ring->tx);
1447 ops = ring->ops;
1448 while (1) {
1449 B43legacy_WARN_ON(!(slot >= 0 && slot < ring->nr_slots));
1450 desc = ops->idx2desc(ring, slot, &meta);
1451
1452 if (meta->skb)
1453 unmap_descbuffer(ring, meta->dmaaddr,
1454 meta->skb->len, 1);
1455 else
1456 unmap_descbuffer(ring, meta->dmaaddr,
1457 sizeof(struct b43legacy_txhdr_fw3),
1458 1);
1459
1460 if (meta->is_last_fragment) {
1461 struct ieee80211_tx_info *info;
1462 BUG_ON(!meta->skb);
1463 info = IEEE80211_SKB_CB(meta->skb);
1464
1465 /* preserve the confiured retry limit before clearing the status
1466 * The xmit function has overwritten the rc's value with the actual
1467 * retry limit done by the hardware */
1468 retry_limit = info->status.rates[0].count;
1469 ieee80211_tx_info_clear_status(info);
1470
1471 if (status->acked)
1472 info->flags |= IEEE80211_TX_STAT_ACK;
1473
1474 if (status->rts_count > dev->wl->hw->conf.short_frame_max_tx_count) {
1475 /*
1476 * If the short retries (RTS, not data frame) have exceeded
1477 * the limit, the hw will not have tried the selected rate,
1478 * but will have used the fallback rate instead.
1479 * Don't let the rate control count attempts for the selected
1480 * rate in this case, otherwise the statistics will be off.
1481 */
1482 info->status.rates[0].count = 0;
1483 info->status.rates[1].count = status->frame_count;
1484 } else {
1485 if (status->frame_count > retry_limit) {
1486 info->status.rates[0].count = retry_limit;
1487 info->status.rates[1].count = status->frame_count -
1488 retry_limit;
1489
1490 } else {
1491 info->status.rates[0].count = status->frame_count;
1492 info->status.rates[1].idx = -1;
1493 }
1494 }
1495
1496 /* Call back to inform the ieee80211 subsystem about the
1497 * status of the transmission.
1498 * Some fields of txstat are already filled in dma_tx().
1499 */
1500 ieee80211_tx_status_irqsafe(dev->wl->hw, meta->skb);
1501 /* skb is freed by ieee80211_tx_status_irqsafe() */
1502 meta->skb = NULL;
1503 } else {
1504 /* No need to call free_descriptor_buffer here, as
1505 * this is only the txhdr, which is not allocated.
1506 */
1507 B43legacy_WARN_ON(meta->skb != NULL);
1508 }
1509
1510 /* Everything unmapped and free'd. So it's not used anymore. */
1511 ring->used_slots--;
1512
1513 if (meta->is_last_fragment)
1514 break;
1515 slot = next_slot(ring, slot);
1516 }
1517 dev->stats.last_tx = jiffies;
1518 if (ring->stopped) {
1519 B43legacy_WARN_ON(free_slots(ring) < SLOTS_PER_PACKET);
1520 ieee80211_wake_queue(dev->wl->hw, txring_to_priority(ring));
1521 ring->stopped = 0;
1522 if (b43legacy_debug(dev, B43legacy_DBG_DMAVERBOSE))
1523 b43legacydbg(dev->wl, "Woke up TX ring %d\n",
1524 ring->index);
1525 }
1526
1527 spin_unlock(&ring->lock);
1528 }
1529
1530 static void dma_rx(struct b43legacy_dmaring *ring,
1531 int *slot)
1532 {
1533 const struct b43legacy_dma_ops *ops = ring->ops;
1534 struct b43legacy_dmadesc_generic *desc;
1535 struct b43legacy_dmadesc_meta *meta;
1536 struct b43legacy_rxhdr_fw3 *rxhdr;
1537 struct sk_buff *skb;
1538 u16 len;
1539 int err;
1540 dma_addr_t dmaaddr;
1541
1542 desc = ops->idx2desc(ring, *slot, &meta);
1543
1544 sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1545 skb = meta->skb;
1546
1547 if (ring->index == 3) {
1548 /* We received an xmit status. */
1549 struct b43legacy_hwtxstatus *hw =
1550 (struct b43legacy_hwtxstatus *)skb->data;
1551 int i = 0;
1552
1553 while (hw->cookie == 0) {
1554 if (i > 100)
1555 break;
1556 i++;
1557 udelay(2);
1558 barrier();
1559 }
1560 b43legacy_handle_hwtxstatus(ring->dev, hw);
1561 /* recycle the descriptor buffer. */
1562 sync_descbuffer_for_device(ring, meta->dmaaddr,
1563 ring->rx_buffersize);
1564
1565 return;
1566 }
1567 rxhdr = (struct b43legacy_rxhdr_fw3 *)skb->data;
1568 len = le16_to_cpu(rxhdr->frame_len);
1569 if (len == 0) {
1570 int i = 0;
1571
1572 do {
1573 udelay(2);
1574 barrier();
1575 len = le16_to_cpu(rxhdr->frame_len);
1576 } while (len == 0 && i++ < 5);
1577 if (unlikely(len == 0)) {
1578 /* recycle the descriptor buffer. */
1579 sync_descbuffer_for_device(ring, meta->dmaaddr,
1580 ring->rx_buffersize);
1581 goto drop;
1582 }
1583 }
1584 if (unlikely(len > ring->rx_buffersize)) {
1585 /* The data did not fit into one descriptor buffer
1586 * and is split over multiple buffers.
1587 * This should never happen, as we try to allocate buffers
1588 * big enough. So simply ignore this packet.
1589 */
1590 int cnt = 0;
1591 s32 tmp = len;
1592
1593 while (1) {
1594 desc = ops->idx2desc(ring, *slot, &meta);
1595 /* recycle the descriptor buffer. */
1596 sync_descbuffer_for_device(ring, meta->dmaaddr,
1597 ring->rx_buffersize);
1598 *slot = next_slot(ring, *slot);
1599 cnt++;
1600 tmp -= ring->rx_buffersize;
1601 if (tmp <= 0)
1602 break;
1603 }
1604 b43legacyerr(ring->dev->wl, "DMA RX buffer too small "
1605 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1606 len, ring->rx_buffersize, cnt);
1607 goto drop;
1608 }
1609
1610 dmaaddr = meta->dmaaddr;
1611 err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1612 if (unlikely(err)) {
1613 b43legacydbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer()"
1614 " failed\n");
1615 sync_descbuffer_for_device(ring, dmaaddr,
1616 ring->rx_buffersize);
1617 goto drop;
1618 }
1619
1620 unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1621 skb_put(skb, len + ring->frameoffset);
1622 skb_pull(skb, ring->frameoffset);
1623
1624 b43legacy_rx(ring->dev, skb, rxhdr);
1625 drop:
1626 return;
1627 }
1628
1629 void b43legacy_dma_rx(struct b43legacy_dmaring *ring)
1630 {
1631 const struct b43legacy_dma_ops *ops = ring->ops;
1632 int slot;
1633 int current_slot;
1634 int used_slots = 0;
1635
1636 B43legacy_WARN_ON(ring->tx);
1637 current_slot = ops->get_current_rxslot(ring);
1638 B43legacy_WARN_ON(!(current_slot >= 0 && current_slot <
1639 ring->nr_slots));
1640
1641 slot = ring->current_slot;
1642 for (; slot != current_slot; slot = next_slot(ring, slot)) {
1643 dma_rx(ring, &slot);
1644 update_max_used_slots(ring, ++used_slots);
1645 }
1646 ops->set_current_rxslot(ring, slot);
1647 ring->current_slot = slot;
1648 }
1649
1650 static void b43legacy_dma_tx_suspend_ring(struct b43legacy_dmaring *ring)
1651 {
1652 unsigned long flags;
1653
1654 spin_lock_irqsave(&ring->lock, flags);
1655 B43legacy_WARN_ON(!ring->tx);
1656 ring->ops->tx_suspend(ring);
1657 spin_unlock_irqrestore(&ring->lock, flags);
1658 }
1659
1660 static void b43legacy_dma_tx_resume_ring(struct b43legacy_dmaring *ring)
1661 {
1662 unsigned long flags;
1663
1664 spin_lock_irqsave(&ring->lock, flags);
1665 B43legacy_WARN_ON(!ring->tx);
1666 ring->ops->tx_resume(ring);
1667 spin_unlock_irqrestore(&ring->lock, flags);
1668 }
1669
1670 void b43legacy_dma_tx_suspend(struct b43legacy_wldev *dev)
1671 {
1672 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1673 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring0);
1674 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring1);
1675 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring2);
1676 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring3);
1677 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring4);
1678 b43legacy_dma_tx_suspend_ring(dev->dma.tx_ring5);
1679 }
1680
1681 void b43legacy_dma_tx_resume(struct b43legacy_wldev *dev)
1682 {
1683 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring5);
1684 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring4);
1685 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring3);
1686 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring2);
1687 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring1);
1688 b43legacy_dma_tx_resume_ring(dev->dma.tx_ring0);
1689 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1690 }
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