]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/net/wireless/b43legacy/main.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
headers: remove sched.h from interrupt.h
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / b43legacy / main.c
1 /*
2 *
3 * Broadcom B43legacy wireless driver
4 *
5 * Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 * Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
7 * Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10 * Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
11 *
12 * Some parts of the code in this file are derived from the ipw2200
13 * driver Copyright(c) 2003 - 2004 Intel Corporation.
14
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING. If not, write to
27 * the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
28 * Boston, MA 02110-1301, USA.
29 *
30 */
31
32 #include <linux/delay.h>
33 #include <linux/init.h>
34 #include <linux/moduleparam.h>
35 #include <linux/if_arp.h>
36 #include <linux/etherdevice.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/dma-mapping.h>
43 #include <net/dst.h>
44 #include <asm/unaligned.h>
45
46 #include "b43legacy.h"
47 #include "main.h"
48 #include "debugfs.h"
49 #include "phy.h"
50 #include "dma.h"
51 #include "pio.h"
52 #include "sysfs.h"
53 #include "xmit.h"
54 #include "radio.h"
55
56
57 MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63 MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
64
65 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
66 static int modparam_pio;
67 module_param_named(pio, modparam_pio, int, 0444);
68 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
69 #elif defined(CONFIG_B43LEGACY_DMA)
70 # define modparam_pio 0
71 #elif defined(CONFIG_B43LEGACY_PIO)
72 # define modparam_pio 1
73 #endif
74
75 static int modparam_bad_frames_preempt;
76 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
77 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
78 " Preemption");
79
80 static char modparam_fwpostfix[16];
81 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
82 MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
83
84 /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
85 static const struct ssb_device_id b43legacy_ssb_tbl[] = {
86 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
87 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
88 SSB_DEVTABLE_END
89 };
90 MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
91
92
93 /* Channel and ratetables are shared for all devices.
94 * They can't be const, because ieee80211 puts some precalculated
95 * data in there. This data is the same for all devices, so we don't
96 * get concurrency issues */
97 #define RATETAB_ENT(_rateid, _flags) \
98 { \
99 .bitrate = B43legacy_RATE_TO_100KBPS(_rateid), \
100 .hw_value = (_rateid), \
101 .flags = (_flags), \
102 }
103 /*
104 * NOTE: When changing this, sync with xmit.c's
105 * b43legacy_plcp_get_bitrate_idx_* functions!
106 */
107 static struct ieee80211_rate __b43legacy_ratetable[] = {
108 RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
109 RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
110 RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
111 RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
112 RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
113 RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
114 RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
115 RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
116 RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
117 RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
118 RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
119 RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
120 };
121 #define b43legacy_b_ratetable (__b43legacy_ratetable + 0)
122 #define b43legacy_b_ratetable_size 4
123 #define b43legacy_g_ratetable (__b43legacy_ratetable + 0)
124 #define b43legacy_g_ratetable_size 12
125
126 #define CHANTAB_ENT(_chanid, _freq) \
127 { \
128 .center_freq = (_freq), \
129 .hw_value = (_chanid), \
130 }
131 static struct ieee80211_channel b43legacy_bg_chantable[] = {
132 CHANTAB_ENT(1, 2412),
133 CHANTAB_ENT(2, 2417),
134 CHANTAB_ENT(3, 2422),
135 CHANTAB_ENT(4, 2427),
136 CHANTAB_ENT(5, 2432),
137 CHANTAB_ENT(6, 2437),
138 CHANTAB_ENT(7, 2442),
139 CHANTAB_ENT(8, 2447),
140 CHANTAB_ENT(9, 2452),
141 CHANTAB_ENT(10, 2457),
142 CHANTAB_ENT(11, 2462),
143 CHANTAB_ENT(12, 2467),
144 CHANTAB_ENT(13, 2472),
145 CHANTAB_ENT(14, 2484),
146 };
147
148 static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
149 .channels = b43legacy_bg_chantable,
150 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
151 .bitrates = b43legacy_b_ratetable,
152 .n_bitrates = b43legacy_b_ratetable_size,
153 };
154
155 static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
156 .channels = b43legacy_bg_chantable,
157 .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
158 .bitrates = b43legacy_g_ratetable,
159 .n_bitrates = b43legacy_g_ratetable_size,
160 };
161
162 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
163 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
164 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
165 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
166
167
168 static int b43legacy_ratelimit(struct b43legacy_wl *wl)
169 {
170 if (!wl || !wl->current_dev)
171 return 1;
172 if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
173 return 1;
174 /* We are up and running.
175 * Ratelimit the messages to avoid DoS over the net. */
176 return net_ratelimit();
177 }
178
179 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
180 {
181 va_list args;
182
183 if (!b43legacy_ratelimit(wl))
184 return;
185 va_start(args, fmt);
186 printk(KERN_INFO "b43legacy-%s: ",
187 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
188 vprintk(fmt, args);
189 va_end(args);
190 }
191
192 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
193 {
194 va_list args;
195
196 if (!b43legacy_ratelimit(wl))
197 return;
198 va_start(args, fmt);
199 printk(KERN_ERR "b43legacy-%s ERROR: ",
200 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
201 vprintk(fmt, args);
202 va_end(args);
203 }
204
205 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
206 {
207 va_list args;
208
209 if (!b43legacy_ratelimit(wl))
210 return;
211 va_start(args, fmt);
212 printk(KERN_WARNING "b43legacy-%s warning: ",
213 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
214 vprintk(fmt, args);
215 va_end(args);
216 }
217
218 #if B43legacy_DEBUG
219 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
220 {
221 va_list args;
222
223 va_start(args, fmt);
224 printk(KERN_DEBUG "b43legacy-%s debug: ",
225 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
226 vprintk(fmt, args);
227 va_end(args);
228 }
229 #endif /* DEBUG */
230
231 static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
232 u32 val)
233 {
234 u32 status;
235
236 B43legacy_WARN_ON(offset % 4 != 0);
237
238 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
239 if (status & B43legacy_MACCTL_BE)
240 val = swab32(val);
241
242 b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
243 mmiowb();
244 b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
245 }
246
247 static inline
248 void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
249 u16 routing, u16 offset)
250 {
251 u32 control;
252
253 /* "offset" is the WORD offset. */
254
255 control = routing;
256 control <<= 16;
257 control |= offset;
258 b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
259 }
260
261 u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
262 u16 routing, u16 offset)
263 {
264 u32 ret;
265
266 if (routing == B43legacy_SHM_SHARED) {
267 B43legacy_WARN_ON((offset & 0x0001) != 0);
268 if (offset & 0x0003) {
269 /* Unaligned access */
270 b43legacy_shm_control_word(dev, routing, offset >> 2);
271 ret = b43legacy_read16(dev,
272 B43legacy_MMIO_SHM_DATA_UNALIGNED);
273 ret <<= 16;
274 b43legacy_shm_control_word(dev, routing,
275 (offset >> 2) + 1);
276 ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
277
278 return ret;
279 }
280 offset >>= 2;
281 }
282 b43legacy_shm_control_word(dev, routing, offset);
283 ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
284
285 return ret;
286 }
287
288 u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
289 u16 routing, u16 offset)
290 {
291 u16 ret;
292
293 if (routing == B43legacy_SHM_SHARED) {
294 B43legacy_WARN_ON((offset & 0x0001) != 0);
295 if (offset & 0x0003) {
296 /* Unaligned access */
297 b43legacy_shm_control_word(dev, routing, offset >> 2);
298 ret = b43legacy_read16(dev,
299 B43legacy_MMIO_SHM_DATA_UNALIGNED);
300
301 return ret;
302 }
303 offset >>= 2;
304 }
305 b43legacy_shm_control_word(dev, routing, offset);
306 ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
307
308 return ret;
309 }
310
311 void b43legacy_shm_write32(struct b43legacy_wldev *dev,
312 u16 routing, u16 offset,
313 u32 value)
314 {
315 if (routing == B43legacy_SHM_SHARED) {
316 B43legacy_WARN_ON((offset & 0x0001) != 0);
317 if (offset & 0x0003) {
318 /* Unaligned access */
319 b43legacy_shm_control_word(dev, routing, offset >> 2);
320 mmiowb();
321 b43legacy_write16(dev,
322 B43legacy_MMIO_SHM_DATA_UNALIGNED,
323 (value >> 16) & 0xffff);
324 mmiowb();
325 b43legacy_shm_control_word(dev, routing,
326 (offset >> 2) + 1);
327 mmiowb();
328 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
329 value & 0xffff);
330 return;
331 }
332 offset >>= 2;
333 }
334 b43legacy_shm_control_word(dev, routing, offset);
335 mmiowb();
336 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
337 }
338
339 void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
340 u16 value)
341 {
342 if (routing == B43legacy_SHM_SHARED) {
343 B43legacy_WARN_ON((offset & 0x0001) != 0);
344 if (offset & 0x0003) {
345 /* Unaligned access */
346 b43legacy_shm_control_word(dev, routing, offset >> 2);
347 mmiowb();
348 b43legacy_write16(dev,
349 B43legacy_MMIO_SHM_DATA_UNALIGNED,
350 value);
351 return;
352 }
353 offset >>= 2;
354 }
355 b43legacy_shm_control_word(dev, routing, offset);
356 mmiowb();
357 b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
358 }
359
360 /* Read HostFlags */
361 u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
362 {
363 u32 ret;
364
365 ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
366 B43legacy_SHM_SH_HOSTFHI);
367 ret <<= 16;
368 ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
369 B43legacy_SHM_SH_HOSTFLO);
370
371 return ret;
372 }
373
374 /* Write HostFlags */
375 void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
376 {
377 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
378 B43legacy_SHM_SH_HOSTFLO,
379 (value & 0x0000FFFF));
380 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
381 B43legacy_SHM_SH_HOSTFHI,
382 ((value & 0xFFFF0000) >> 16));
383 }
384
385 void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
386 {
387 /* We need to be careful. As we read the TSF from multiple
388 * registers, we should take care of register overflows.
389 * In theory, the whole tsf read process should be atomic.
390 * We try to be atomic here, by restaring the read process,
391 * if any of the high registers changed (overflew).
392 */
393 if (dev->dev->id.revision >= 3) {
394 u32 low;
395 u32 high;
396 u32 high2;
397
398 do {
399 high = b43legacy_read32(dev,
400 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
401 low = b43legacy_read32(dev,
402 B43legacy_MMIO_REV3PLUS_TSF_LOW);
403 high2 = b43legacy_read32(dev,
404 B43legacy_MMIO_REV3PLUS_TSF_HIGH);
405 } while (unlikely(high != high2));
406
407 *tsf = high;
408 *tsf <<= 32;
409 *tsf |= low;
410 } else {
411 u64 tmp;
412 u16 v0;
413 u16 v1;
414 u16 v2;
415 u16 v3;
416 u16 test1;
417 u16 test2;
418 u16 test3;
419
420 do {
421 v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
422 v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
423 v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
424 v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
425
426 test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
427 test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
428 test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
429 } while (v3 != test3 || v2 != test2 || v1 != test1);
430
431 *tsf = v3;
432 *tsf <<= 48;
433 tmp = v2;
434 tmp <<= 32;
435 *tsf |= tmp;
436 tmp = v1;
437 tmp <<= 16;
438 *tsf |= tmp;
439 *tsf |= v0;
440 }
441 }
442
443 static void b43legacy_time_lock(struct b43legacy_wldev *dev)
444 {
445 u32 status;
446
447 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
448 status |= B43legacy_MACCTL_TBTTHOLD;
449 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
450 mmiowb();
451 }
452
453 static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
454 {
455 u32 status;
456
457 status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
458 status &= ~B43legacy_MACCTL_TBTTHOLD;
459 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
460 }
461
462 static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
463 {
464 /* Be careful with the in-progress timer.
465 * First zero out the low register, so we have a full
466 * register-overflow duration to complete the operation.
467 */
468 if (dev->dev->id.revision >= 3) {
469 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
470 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
471
472 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
473 mmiowb();
474 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
475 hi);
476 mmiowb();
477 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
478 lo);
479 } else {
480 u16 v0 = (tsf & 0x000000000000FFFFULL);
481 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
482 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
483 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
484
485 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
486 mmiowb();
487 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
488 mmiowb();
489 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
490 mmiowb();
491 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
492 mmiowb();
493 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
494 }
495 }
496
497 void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
498 {
499 b43legacy_time_lock(dev);
500 b43legacy_tsf_write_locked(dev, tsf);
501 b43legacy_time_unlock(dev);
502 }
503
504 static
505 void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
506 u16 offset, const u8 *mac)
507 {
508 static const u8 zero_addr[ETH_ALEN] = { 0 };
509 u16 data;
510
511 if (!mac)
512 mac = zero_addr;
513
514 offset |= 0x0020;
515 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
516
517 data = mac[0];
518 data |= mac[1] << 8;
519 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
520 data = mac[2];
521 data |= mac[3] << 8;
522 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
523 data = mac[4];
524 data |= mac[5] << 8;
525 b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
526 }
527
528 static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
529 {
530 static const u8 zero_addr[ETH_ALEN] = { 0 };
531 const u8 *mac = dev->wl->mac_addr;
532 const u8 *bssid = dev->wl->bssid;
533 u8 mac_bssid[ETH_ALEN * 2];
534 int i;
535 u32 tmp;
536
537 if (!bssid)
538 bssid = zero_addr;
539 if (!mac)
540 mac = zero_addr;
541
542 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
543
544 memcpy(mac_bssid, mac, ETH_ALEN);
545 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
546
547 /* Write our MAC address and BSSID to template ram */
548 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
549 tmp = (u32)(mac_bssid[i + 0]);
550 tmp |= (u32)(mac_bssid[i + 1]) << 8;
551 tmp |= (u32)(mac_bssid[i + 2]) << 16;
552 tmp |= (u32)(mac_bssid[i + 3]) << 24;
553 b43legacy_ram_write(dev, 0x20 + i, tmp);
554 b43legacy_ram_write(dev, 0x78 + i, tmp);
555 b43legacy_ram_write(dev, 0x478 + i, tmp);
556 }
557 }
558
559 static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
560 {
561 b43legacy_write_mac_bssid_templates(dev);
562 b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
563 dev->wl->mac_addr);
564 }
565
566 static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
567 u16 slot_time)
568 {
569 /* slot_time is in usec. */
570 if (dev->phy.type != B43legacy_PHYTYPE_G)
571 return;
572 b43legacy_write16(dev, 0x684, 510 + slot_time);
573 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
574 slot_time);
575 }
576
577 static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
578 {
579 b43legacy_set_slot_time(dev, 9);
580 }
581
582 static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
583 {
584 b43legacy_set_slot_time(dev, 20);
585 }
586
587 /* Synchronize IRQ top- and bottom-half.
588 * IRQs must be masked before calling this.
589 * This must not be called with the irq_lock held.
590 */
591 static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
592 {
593 synchronize_irq(dev->dev->irq);
594 tasklet_kill(&dev->isr_tasklet);
595 }
596
597 /* DummyTransmission function, as documented on
598 * http://bcm-specs.sipsolutions.net/DummyTransmission
599 */
600 void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
601 {
602 struct b43legacy_phy *phy = &dev->phy;
603 unsigned int i;
604 unsigned int max_loop;
605 u16 value;
606 u32 buffer[5] = {
607 0x00000000,
608 0x00D40000,
609 0x00000000,
610 0x01000000,
611 0x00000000,
612 };
613
614 switch (phy->type) {
615 case B43legacy_PHYTYPE_B:
616 case B43legacy_PHYTYPE_G:
617 max_loop = 0xFA;
618 buffer[0] = 0x000B846E;
619 break;
620 default:
621 B43legacy_BUG_ON(1);
622 return;
623 }
624
625 for (i = 0; i < 5; i++)
626 b43legacy_ram_write(dev, i * 4, buffer[i]);
627
628 /* dummy read follows */
629 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
630
631 b43legacy_write16(dev, 0x0568, 0x0000);
632 b43legacy_write16(dev, 0x07C0, 0x0000);
633 b43legacy_write16(dev, 0x050C, 0x0000);
634 b43legacy_write16(dev, 0x0508, 0x0000);
635 b43legacy_write16(dev, 0x050A, 0x0000);
636 b43legacy_write16(dev, 0x054C, 0x0000);
637 b43legacy_write16(dev, 0x056A, 0x0014);
638 b43legacy_write16(dev, 0x0568, 0x0826);
639 b43legacy_write16(dev, 0x0500, 0x0000);
640 b43legacy_write16(dev, 0x0502, 0x0030);
641
642 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
643 b43legacy_radio_write16(dev, 0x0051, 0x0017);
644 for (i = 0x00; i < max_loop; i++) {
645 value = b43legacy_read16(dev, 0x050E);
646 if (value & 0x0080)
647 break;
648 udelay(10);
649 }
650 for (i = 0x00; i < 0x0A; i++) {
651 value = b43legacy_read16(dev, 0x050E);
652 if (value & 0x0400)
653 break;
654 udelay(10);
655 }
656 for (i = 0x00; i < 0x0A; i++) {
657 value = b43legacy_read16(dev, 0x0690);
658 if (!(value & 0x0100))
659 break;
660 udelay(10);
661 }
662 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
663 b43legacy_radio_write16(dev, 0x0051, 0x0037);
664 }
665
666 /* Turn the Analog ON/OFF */
667 static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
668 {
669 b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
670 }
671
672 void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
673 {
674 u32 tmslow;
675 u32 macctl;
676
677 flags |= B43legacy_TMSLOW_PHYCLKEN;
678 flags |= B43legacy_TMSLOW_PHYRESET;
679 ssb_device_enable(dev->dev, flags);
680 msleep(2); /* Wait for the PLL to turn on. */
681
682 /* Now take the PHY out of Reset again */
683 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
684 tmslow |= SSB_TMSLOW_FGC;
685 tmslow &= ~B43legacy_TMSLOW_PHYRESET;
686 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
687 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
688 msleep(1);
689 tmslow &= ~SSB_TMSLOW_FGC;
690 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
691 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
692 msleep(1);
693
694 /* Turn Analog ON */
695 b43legacy_switch_analog(dev, 1);
696
697 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
698 macctl &= ~B43legacy_MACCTL_GMODE;
699 if (flags & B43legacy_TMSLOW_GMODE) {
700 macctl |= B43legacy_MACCTL_GMODE;
701 dev->phy.gmode = 1;
702 } else
703 dev->phy.gmode = 0;
704 macctl |= B43legacy_MACCTL_IHR_ENABLED;
705 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
706 }
707
708 static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
709 {
710 u32 v0;
711 u32 v1;
712 u16 tmp;
713 struct b43legacy_txstatus stat;
714
715 while (1) {
716 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
717 if (!(v0 & 0x00000001))
718 break;
719 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
720
721 stat.cookie = (v0 >> 16);
722 stat.seq = (v1 & 0x0000FFFF);
723 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
724 tmp = (v0 & 0x0000FFFF);
725 stat.frame_count = ((tmp & 0xF000) >> 12);
726 stat.rts_count = ((tmp & 0x0F00) >> 8);
727 stat.supp_reason = ((tmp & 0x001C) >> 2);
728 stat.pm_indicated = !!(tmp & 0x0080);
729 stat.intermediate = !!(tmp & 0x0040);
730 stat.for_ampdu = !!(tmp & 0x0020);
731 stat.acked = !!(tmp & 0x0002);
732
733 b43legacy_handle_txstatus(dev, &stat);
734 }
735 }
736
737 static void drain_txstatus_queue(struct b43legacy_wldev *dev)
738 {
739 u32 dummy;
740
741 if (dev->dev->id.revision < 5)
742 return;
743 /* Read all entries from the microcode TXstatus FIFO
744 * and throw them away.
745 */
746 while (1) {
747 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
748 if (!(dummy & 0x00000001))
749 break;
750 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
751 }
752 }
753
754 static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
755 {
756 u32 val = 0;
757
758 val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
759 val <<= 16;
760 val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
761
762 return val;
763 }
764
765 static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
766 {
767 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
768 (jssi & 0x0000FFFF));
769 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
770 (jssi & 0xFFFF0000) >> 16);
771 }
772
773 static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
774 {
775 b43legacy_jssi_write(dev, 0x7F7F7F7F);
776 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
777 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
778 | B43legacy_MACCMD_BGNOISE);
779 B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
780 dev->phy.channel);
781 }
782
783 static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
784 {
785 /* Top half of Link Quality calculation. */
786
787 if (dev->noisecalc.calculation_running)
788 return;
789 dev->noisecalc.channel_at_start = dev->phy.channel;
790 dev->noisecalc.calculation_running = 1;
791 dev->noisecalc.nr_samples = 0;
792
793 b43legacy_generate_noise_sample(dev);
794 }
795
796 static void handle_irq_noise(struct b43legacy_wldev *dev)
797 {
798 struct b43legacy_phy *phy = &dev->phy;
799 u16 tmp;
800 u8 noise[4];
801 u8 i;
802 u8 j;
803 s32 average;
804
805 /* Bottom half of Link Quality calculation. */
806
807 B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
808 if (dev->noisecalc.channel_at_start != phy->channel)
809 goto drop_calculation;
810 *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
811 if (noise[0] == 0x7F || noise[1] == 0x7F ||
812 noise[2] == 0x7F || noise[3] == 0x7F)
813 goto generate_new;
814
815 /* Get the noise samples. */
816 B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
817 i = dev->noisecalc.nr_samples;
818 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
819 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
820 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
821 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
822 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
823 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
824 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
825 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
826 dev->noisecalc.nr_samples++;
827 if (dev->noisecalc.nr_samples == 8) {
828 /* Calculate the Link Quality by the noise samples. */
829 average = 0;
830 for (i = 0; i < 8; i++) {
831 for (j = 0; j < 4; j++)
832 average += dev->noisecalc.samples[i][j];
833 }
834 average /= (8 * 4);
835 average *= 125;
836 average += 64;
837 average /= 128;
838 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
839 0x40C);
840 tmp = (tmp / 128) & 0x1F;
841 if (tmp >= 8)
842 average += 2;
843 else
844 average -= 25;
845 if (tmp == 8)
846 average -= 72;
847 else
848 average -= 48;
849
850 dev->stats.link_noise = average;
851 drop_calculation:
852 dev->noisecalc.calculation_running = 0;
853 return;
854 }
855 generate_new:
856 b43legacy_generate_noise_sample(dev);
857 }
858
859 static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
860 {
861 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
862 /* TODO: PS TBTT */
863 } else {
864 if (1/*FIXME: the last PSpoll frame was sent successfully */)
865 b43legacy_power_saving_ctl_bits(dev, -1, -1);
866 }
867 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
868 dev->dfq_valid = 1;
869 }
870
871 static void handle_irq_atim_end(struct b43legacy_wldev *dev)
872 {
873 if (dev->dfq_valid) {
874 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
875 b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
876 | B43legacy_MACCMD_DFQ_VALID);
877 dev->dfq_valid = 0;
878 }
879 }
880
881 static void handle_irq_pmq(struct b43legacy_wldev *dev)
882 {
883 u32 tmp;
884
885 /* TODO: AP mode. */
886
887 while (1) {
888 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
889 if (!(tmp & 0x00000008))
890 break;
891 }
892 /* 16bit write is odd, but correct. */
893 b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
894 }
895
896 static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
897 const u8 *data, u16 size,
898 u16 ram_offset,
899 u16 shm_size_offset, u8 rate)
900 {
901 u32 i;
902 u32 tmp;
903 struct b43legacy_plcp_hdr4 plcp;
904
905 plcp.data = 0;
906 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
907 b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
908 ram_offset += sizeof(u32);
909 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
910 * So leave the first two bytes of the next write blank.
911 */
912 tmp = (u32)(data[0]) << 16;
913 tmp |= (u32)(data[1]) << 24;
914 b43legacy_ram_write(dev, ram_offset, tmp);
915 ram_offset += sizeof(u32);
916 for (i = 2; i < size; i += sizeof(u32)) {
917 tmp = (u32)(data[i + 0]);
918 if (i + 1 < size)
919 tmp |= (u32)(data[i + 1]) << 8;
920 if (i + 2 < size)
921 tmp |= (u32)(data[i + 2]) << 16;
922 if (i + 3 < size)
923 tmp |= (u32)(data[i + 3]) << 24;
924 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
925 }
926 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
927 size + sizeof(struct b43legacy_plcp_hdr6));
928 }
929
930 /* Convert a b43legacy antenna number value to the PHY TX control value. */
931 static u16 b43legacy_antenna_to_phyctl(int antenna)
932 {
933 switch (antenna) {
934 case B43legacy_ANTENNA0:
935 return B43legacy_TX4_PHY_ANT0;
936 case B43legacy_ANTENNA1:
937 return B43legacy_TX4_PHY_ANT1;
938 }
939 return B43legacy_TX4_PHY_ANTLAST;
940 }
941
942 static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
943 u16 ram_offset,
944 u16 shm_size_offset)
945 {
946
947 unsigned int i, len, variable_len;
948 const struct ieee80211_mgmt *bcn;
949 const u8 *ie;
950 bool tim_found = 0;
951 unsigned int rate;
952 u16 ctl;
953 int antenna;
954 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
955
956 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
957 len = min((size_t)dev->wl->current_beacon->len,
958 0x200 - sizeof(struct b43legacy_plcp_hdr6));
959 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
960
961 b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
962 shm_size_offset, rate);
963
964 /* Write the PHY TX control parameters. */
965 antenna = B43legacy_ANTENNA_DEFAULT;
966 antenna = b43legacy_antenna_to_phyctl(antenna);
967 ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
968 B43legacy_SHM_SH_BEACPHYCTL);
969 /* We can't send beacons with short preamble. Would get PHY errors. */
970 ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
971 ctl &= ~B43legacy_TX4_PHY_ANT;
972 ctl &= ~B43legacy_TX4_PHY_ENC;
973 ctl |= antenna;
974 ctl |= B43legacy_TX4_PHY_ENC_CCK;
975 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
976 B43legacy_SHM_SH_BEACPHYCTL, ctl);
977
978 /* Find the position of the TIM and the DTIM_period value
979 * and write them to SHM. */
980 ie = bcn->u.beacon.variable;
981 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
982 for (i = 0; i < variable_len - 2; ) {
983 uint8_t ie_id, ie_len;
984
985 ie_id = ie[i];
986 ie_len = ie[i + 1];
987 if (ie_id == 5) {
988 u16 tim_position;
989 u16 dtim_period;
990 /* This is the TIM Information Element */
991
992 /* Check whether the ie_len is in the beacon data range. */
993 if (variable_len < ie_len + 2 + i)
994 break;
995 /* A valid TIM is at least 4 bytes long. */
996 if (ie_len < 4)
997 break;
998 tim_found = 1;
999
1000 tim_position = sizeof(struct b43legacy_plcp_hdr6);
1001 tim_position += offsetof(struct ieee80211_mgmt,
1002 u.beacon.variable);
1003 tim_position += i;
1004
1005 dtim_period = ie[i + 3];
1006
1007 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1008 B43legacy_SHM_SH_TIMPOS, tim_position);
1009 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1010 B43legacy_SHM_SH_DTIMP, dtim_period);
1011 break;
1012 }
1013 i += ie_len + 2;
1014 }
1015 if (!tim_found) {
1016 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1017 "beacon template packet. AP or IBSS operation "
1018 "may be broken.\n");
1019 } else
1020 b43legacydbg(dev->wl, "Updated beacon template\n");
1021 }
1022
1023 static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1024 u16 shm_offset, u16 size,
1025 struct ieee80211_rate *rate)
1026 {
1027 struct b43legacy_plcp_hdr4 plcp;
1028 u32 tmp;
1029 __le16 dur;
1030
1031 plcp.data = 0;
1032 b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1033 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1034 dev->wl->vif,
1035 size,
1036 rate);
1037 /* Write PLCP in two parts and timing for packet transfer */
1038 tmp = le32_to_cpu(plcp.data);
1039 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1040 tmp & 0xFFFF);
1041 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1042 tmp >> 16);
1043 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1044 le16_to_cpu(dur));
1045 }
1046
1047 /* Instead of using custom probe response template, this function
1048 * just patches custom beacon template by:
1049 * 1) Changing packet type
1050 * 2) Patching duration field
1051 * 3) Stripping TIM
1052 */
1053 static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1054 u16 *dest_size,
1055 struct ieee80211_rate *rate)
1056 {
1057 const u8 *src_data;
1058 u8 *dest_data;
1059 u16 src_size, elem_size, src_pos, dest_pos;
1060 __le16 dur;
1061 struct ieee80211_hdr *hdr;
1062 size_t ie_start;
1063
1064 src_size = dev->wl->current_beacon->len;
1065 src_data = (const u8 *)dev->wl->current_beacon->data;
1066
1067 /* Get the start offset of the variable IEs in the packet. */
1068 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1069 B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1070 u.beacon.variable));
1071
1072 if (B43legacy_WARN_ON(src_size < ie_start))
1073 return NULL;
1074
1075 dest_data = kmalloc(src_size, GFP_ATOMIC);
1076 if (unlikely(!dest_data))
1077 return NULL;
1078
1079 /* Copy the static data and all Information Elements, except the TIM. */
1080 memcpy(dest_data, src_data, ie_start);
1081 src_pos = ie_start;
1082 dest_pos = ie_start;
1083 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1084 elem_size = src_data[src_pos + 1] + 2;
1085 if (src_data[src_pos] == 5) {
1086 /* This is the TIM. */
1087 continue;
1088 }
1089 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1090 dest_pos += elem_size;
1091 }
1092 *dest_size = dest_pos;
1093 hdr = (struct ieee80211_hdr *)dest_data;
1094
1095 /* Set the frame control. */
1096 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1097 IEEE80211_STYPE_PROBE_RESP);
1098 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1099 dev->wl->vif,
1100 *dest_size,
1101 rate);
1102 hdr->duration_id = dur;
1103
1104 return dest_data;
1105 }
1106
1107 static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1108 u16 ram_offset,
1109 u16 shm_size_offset,
1110 struct ieee80211_rate *rate)
1111 {
1112 const u8 *probe_resp_data;
1113 u16 size;
1114
1115 size = dev->wl->current_beacon->len;
1116 probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1117 if (unlikely(!probe_resp_data))
1118 return;
1119
1120 /* Looks like PLCP headers plus packet timings are stored for
1121 * all possible basic rates
1122 */
1123 b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
1124 &b43legacy_b_ratetable[0]);
1125 b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
1126 &b43legacy_b_ratetable[1]);
1127 b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
1128 &b43legacy_b_ratetable[2]);
1129 b43legacy_write_probe_resp_plcp(dev, 0x350, size,
1130 &b43legacy_b_ratetable[3]);
1131
1132 size = min((size_t)size,
1133 0x200 - sizeof(struct b43legacy_plcp_hdr6));
1134 b43legacy_write_template_common(dev, probe_resp_data,
1135 size, ram_offset,
1136 shm_size_offset, rate->hw_value);
1137 kfree(probe_resp_data);
1138 }
1139
1140 static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1141 {
1142 struct b43legacy_wl *wl = dev->wl;
1143
1144 if (wl->beacon0_uploaded)
1145 return;
1146 b43legacy_write_beacon_template(dev, 0x68, 0x18);
1147 /* FIXME: Probe resp upload doesn't really belong here,
1148 * but we don't use that feature anyway. */
1149 b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1150 &__b43legacy_ratetable[3]);
1151 wl->beacon0_uploaded = 1;
1152 }
1153
1154 static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1155 {
1156 struct b43legacy_wl *wl = dev->wl;
1157
1158 if (wl->beacon1_uploaded)
1159 return;
1160 b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1161 wl->beacon1_uploaded = 1;
1162 }
1163
1164 static void handle_irq_beacon(struct b43legacy_wldev *dev)
1165 {
1166 struct b43legacy_wl *wl = dev->wl;
1167 u32 cmd, beacon0_valid, beacon1_valid;
1168
1169 if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1170 return;
1171
1172 /* This is the bottom half of the asynchronous beacon update. */
1173
1174 /* Ignore interrupt in the future. */
1175 dev->irq_mask &= ~B43legacy_IRQ_BEACON;
1176
1177 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1178 beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1179 beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1180
1181 /* Schedule interrupt manually, if busy. */
1182 if (beacon0_valid && beacon1_valid) {
1183 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
1184 dev->irq_mask |= B43legacy_IRQ_BEACON;
1185 return;
1186 }
1187
1188 if (unlikely(wl->beacon_templates_virgin)) {
1189 /* We never uploaded a beacon before.
1190 * Upload both templates now, but only mark one valid. */
1191 wl->beacon_templates_virgin = 0;
1192 b43legacy_upload_beacon0(dev);
1193 b43legacy_upload_beacon1(dev);
1194 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1195 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1196 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1197 } else {
1198 if (!beacon0_valid) {
1199 b43legacy_upload_beacon0(dev);
1200 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1201 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1202 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1203 } else if (!beacon1_valid) {
1204 b43legacy_upload_beacon1(dev);
1205 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1206 cmd |= B43legacy_MACCMD_BEACON1_VALID;
1207 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1208 }
1209 }
1210 }
1211
1212 static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1213 {
1214 struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1215 beacon_update_trigger);
1216 struct b43legacy_wldev *dev;
1217
1218 mutex_lock(&wl->mutex);
1219 dev = wl->current_dev;
1220 if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
1221 spin_lock_irq(&wl->irq_lock);
1222 /* Update beacon right away or defer to IRQ. */
1223 handle_irq_beacon(dev);
1224 /* The handler might have updated the IRQ mask. */
1225 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1226 dev->irq_mask);
1227 mmiowb();
1228 spin_unlock_irq(&wl->irq_lock);
1229 }
1230 mutex_unlock(&wl->mutex);
1231 }
1232
1233 /* Asynchronously update the packet templates in template RAM.
1234 * Locking: Requires wl->irq_lock to be locked. */
1235 static void b43legacy_update_templates(struct b43legacy_wl *wl)
1236 {
1237 struct sk_buff *beacon;
1238 /* This is the top half of the ansynchronous beacon update. The bottom
1239 * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1240 * sending an invalid beacon. This can happen for example, if the
1241 * firmware transmits a beacon while we are updating it. */
1242
1243 /* We could modify the existing beacon and set the aid bit in the TIM
1244 * field, but that would probably require resizing and moving of data
1245 * within the beacon template. Simply request a new beacon and let
1246 * mac80211 do the hard work. */
1247 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1248 if (unlikely(!beacon))
1249 return;
1250
1251 if (wl->current_beacon)
1252 dev_kfree_skb_any(wl->current_beacon);
1253 wl->current_beacon = beacon;
1254 wl->beacon0_uploaded = 0;
1255 wl->beacon1_uploaded = 0;
1256 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1257 }
1258
1259 static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1260 u16 beacon_int)
1261 {
1262 b43legacy_time_lock(dev);
1263 if (dev->dev->id.revision >= 3) {
1264 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1265 (beacon_int << 16));
1266 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1267 (beacon_int << 10));
1268 } else {
1269 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1270 b43legacy_write16(dev, 0x610, beacon_int);
1271 }
1272 b43legacy_time_unlock(dev);
1273 b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1274 }
1275
1276 static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1277 {
1278 }
1279
1280 /* Interrupt handler bottom-half */
1281 static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1282 {
1283 u32 reason;
1284 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1285 u32 merged_dma_reason = 0;
1286 int i;
1287 unsigned long flags;
1288
1289 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1290
1291 B43legacy_WARN_ON(b43legacy_status(dev) <
1292 B43legacy_STAT_INITIALIZED);
1293
1294 reason = dev->irq_reason;
1295 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1296 dma_reason[i] = dev->dma_reason[i];
1297 merged_dma_reason |= dma_reason[i];
1298 }
1299
1300 if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1301 b43legacyerr(dev->wl, "MAC transmission error\n");
1302
1303 if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
1304 b43legacyerr(dev->wl, "PHY transmission error\n");
1305 rmb();
1306 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1307 b43legacyerr(dev->wl, "Too many PHY TX errors, "
1308 "restarting the controller\n");
1309 b43legacy_controller_restart(dev, "PHY TX errors");
1310 }
1311 }
1312
1313 if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1314 B43legacy_DMAIRQ_NONFATALMASK))) {
1315 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1316 b43legacyerr(dev->wl, "Fatal DMA error: "
1317 "0x%08X, 0x%08X, 0x%08X, "
1318 "0x%08X, 0x%08X, 0x%08X\n",
1319 dma_reason[0], dma_reason[1],
1320 dma_reason[2], dma_reason[3],
1321 dma_reason[4], dma_reason[5]);
1322 b43legacy_controller_restart(dev, "DMA error");
1323 mmiowb();
1324 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1325 return;
1326 }
1327 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1328 b43legacyerr(dev->wl, "DMA error: "
1329 "0x%08X, 0x%08X, 0x%08X, "
1330 "0x%08X, 0x%08X, 0x%08X\n",
1331 dma_reason[0], dma_reason[1],
1332 dma_reason[2], dma_reason[3],
1333 dma_reason[4], dma_reason[5]);
1334 }
1335
1336 if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1337 handle_irq_ucode_debug(dev);
1338 if (reason & B43legacy_IRQ_TBTT_INDI)
1339 handle_irq_tbtt_indication(dev);
1340 if (reason & B43legacy_IRQ_ATIM_END)
1341 handle_irq_atim_end(dev);
1342 if (reason & B43legacy_IRQ_BEACON)
1343 handle_irq_beacon(dev);
1344 if (reason & B43legacy_IRQ_PMQ)
1345 handle_irq_pmq(dev);
1346 if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1347 ;/*TODO*/
1348 if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1349 handle_irq_noise(dev);
1350
1351 /* Check the DMA reason registers for received data. */
1352 if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1353 if (b43legacy_using_pio(dev))
1354 b43legacy_pio_rx(dev->pio.queue0);
1355 else
1356 b43legacy_dma_rx(dev->dma.rx_ring0);
1357 }
1358 B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1359 B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1360 if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1361 if (b43legacy_using_pio(dev))
1362 b43legacy_pio_rx(dev->pio.queue3);
1363 else
1364 b43legacy_dma_rx(dev->dma.rx_ring3);
1365 }
1366 B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1367 B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1368
1369 if (reason & B43legacy_IRQ_TX_OK)
1370 handle_irq_transmit_status(dev);
1371
1372 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1373 mmiowb();
1374 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1375 }
1376
1377 static void pio_irq_workaround(struct b43legacy_wldev *dev,
1378 u16 base, int queueidx)
1379 {
1380 u16 rxctl;
1381
1382 rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1383 if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1384 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1385 else
1386 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1387 }
1388
1389 static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1390 {
1391 if (b43legacy_using_pio(dev) &&
1392 (dev->dev->id.revision < 3) &&
1393 (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1394 /* Apply a PIO specific workaround to the dma_reasons */
1395 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1396 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1397 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1398 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1399 }
1400
1401 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1402
1403 b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1404 dev->dma_reason[0]);
1405 b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1406 dev->dma_reason[1]);
1407 b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1408 dev->dma_reason[2]);
1409 b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1410 dev->dma_reason[3]);
1411 b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1412 dev->dma_reason[4]);
1413 b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1414 dev->dma_reason[5]);
1415 }
1416
1417 /* Interrupt handler top-half */
1418 static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1419 {
1420 irqreturn_t ret = IRQ_NONE;
1421 struct b43legacy_wldev *dev = dev_id;
1422 u32 reason;
1423
1424 B43legacy_WARN_ON(!dev);
1425
1426 spin_lock(&dev->wl->irq_lock);
1427
1428 if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
1429 /* This can only happen on shared IRQ lines. */
1430 goto out;
1431 reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1432 if (reason == 0xffffffff) /* shared IRQ */
1433 goto out;
1434 ret = IRQ_HANDLED;
1435 reason &= dev->irq_mask;
1436 if (!reason)
1437 goto out;
1438
1439 dev->dma_reason[0] = b43legacy_read32(dev,
1440 B43legacy_MMIO_DMA0_REASON)
1441 & 0x0001DC00;
1442 dev->dma_reason[1] = b43legacy_read32(dev,
1443 B43legacy_MMIO_DMA1_REASON)
1444 & 0x0000DC00;
1445 dev->dma_reason[2] = b43legacy_read32(dev,
1446 B43legacy_MMIO_DMA2_REASON)
1447 & 0x0000DC00;
1448 dev->dma_reason[3] = b43legacy_read32(dev,
1449 B43legacy_MMIO_DMA3_REASON)
1450 & 0x0001DC00;
1451 dev->dma_reason[4] = b43legacy_read32(dev,
1452 B43legacy_MMIO_DMA4_REASON)
1453 & 0x0000DC00;
1454 dev->dma_reason[5] = b43legacy_read32(dev,
1455 B43legacy_MMIO_DMA5_REASON)
1456 & 0x0000DC00;
1457
1458 b43legacy_interrupt_ack(dev, reason);
1459 /* Disable all IRQs. They are enabled again in the bottom half. */
1460 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1461 /* Save the reason code and call our bottom half. */
1462 dev->irq_reason = reason;
1463 tasklet_schedule(&dev->isr_tasklet);
1464 out:
1465 mmiowb();
1466 spin_unlock(&dev->wl->irq_lock);
1467
1468 return ret;
1469 }
1470
1471 static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1472 {
1473 release_firmware(dev->fw.ucode);
1474 dev->fw.ucode = NULL;
1475 release_firmware(dev->fw.pcm);
1476 dev->fw.pcm = NULL;
1477 release_firmware(dev->fw.initvals);
1478 dev->fw.initvals = NULL;
1479 release_firmware(dev->fw.initvals_band);
1480 dev->fw.initvals_band = NULL;
1481 }
1482
1483 static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1484 {
1485 b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
1486 "Drivers/b43#devicefirmware "
1487 "and download the correct firmware (version 3).\n");
1488 }
1489
1490 static int do_request_fw(struct b43legacy_wldev *dev,
1491 const char *name,
1492 const struct firmware **fw)
1493 {
1494 char path[sizeof(modparam_fwpostfix) + 32];
1495 struct b43legacy_fw_header *hdr;
1496 u32 size;
1497 int err;
1498
1499 if (!name)
1500 return 0;
1501
1502 snprintf(path, ARRAY_SIZE(path),
1503 "b43legacy%s/%s.fw",
1504 modparam_fwpostfix, name);
1505 err = request_firmware(fw, path, dev->dev->dev);
1506 if (err) {
1507 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1508 "or load failed.\n", path);
1509 return err;
1510 }
1511 if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1512 goto err_format;
1513 hdr = (struct b43legacy_fw_header *)((*fw)->data);
1514 switch (hdr->type) {
1515 case B43legacy_FW_TYPE_UCODE:
1516 case B43legacy_FW_TYPE_PCM:
1517 size = be32_to_cpu(hdr->size);
1518 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1519 goto err_format;
1520 /* fallthrough */
1521 case B43legacy_FW_TYPE_IV:
1522 if (hdr->ver != 1)
1523 goto err_format;
1524 break;
1525 default:
1526 goto err_format;
1527 }
1528
1529 return err;
1530
1531 err_format:
1532 b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1533 return -EPROTO;
1534 }
1535
1536 static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1537 {
1538 struct b43legacy_firmware *fw = &dev->fw;
1539 const u8 rev = dev->dev->id.revision;
1540 const char *filename;
1541 u32 tmshigh;
1542 int err;
1543
1544 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1545 if (!fw->ucode) {
1546 if (rev == 2)
1547 filename = "ucode2";
1548 else if (rev == 4)
1549 filename = "ucode4";
1550 else
1551 filename = "ucode5";
1552 err = do_request_fw(dev, filename, &fw->ucode);
1553 if (err)
1554 goto err_load;
1555 }
1556 if (!fw->pcm) {
1557 if (rev < 5)
1558 filename = "pcm4";
1559 else
1560 filename = "pcm5";
1561 err = do_request_fw(dev, filename, &fw->pcm);
1562 if (err)
1563 goto err_load;
1564 }
1565 if (!fw->initvals) {
1566 switch (dev->phy.type) {
1567 case B43legacy_PHYTYPE_B:
1568 case B43legacy_PHYTYPE_G:
1569 if ((rev >= 5) && (rev <= 10))
1570 filename = "b0g0initvals5";
1571 else if (rev == 2 || rev == 4)
1572 filename = "b0g0initvals2";
1573 else
1574 goto err_no_initvals;
1575 break;
1576 default:
1577 goto err_no_initvals;
1578 }
1579 err = do_request_fw(dev, filename, &fw->initvals);
1580 if (err)
1581 goto err_load;
1582 }
1583 if (!fw->initvals_band) {
1584 switch (dev->phy.type) {
1585 case B43legacy_PHYTYPE_B:
1586 case B43legacy_PHYTYPE_G:
1587 if ((rev >= 5) && (rev <= 10))
1588 filename = "b0g0bsinitvals5";
1589 else if (rev >= 11)
1590 filename = NULL;
1591 else if (rev == 2 || rev == 4)
1592 filename = NULL;
1593 else
1594 goto err_no_initvals;
1595 break;
1596 default:
1597 goto err_no_initvals;
1598 }
1599 err = do_request_fw(dev, filename, &fw->initvals_band);
1600 if (err)
1601 goto err_load;
1602 }
1603
1604 return 0;
1605
1606 err_load:
1607 b43legacy_print_fw_helptext(dev->wl);
1608 goto error;
1609
1610 err_no_initvals:
1611 err = -ENODEV;
1612 b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1613 "core rev %u\n", dev->phy.type, rev);
1614 goto error;
1615
1616 error:
1617 b43legacy_release_firmware(dev);
1618 return err;
1619 }
1620
1621 static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1622 {
1623 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1624 const __be32 *data;
1625 unsigned int i;
1626 unsigned int len;
1627 u16 fwrev;
1628 u16 fwpatch;
1629 u16 fwdate;
1630 u16 fwtime;
1631 u32 tmp, macctl;
1632 int err = 0;
1633
1634 /* Jump the microcode PSM to offset 0 */
1635 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1636 B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1637 macctl |= B43legacy_MACCTL_PSM_JMP0;
1638 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1639 /* Zero out all microcode PSM registers and shared memory. */
1640 for (i = 0; i < 64; i++)
1641 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1642 for (i = 0; i < 4096; i += 2)
1643 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1644
1645 /* Upload Microcode. */
1646 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1647 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1648 b43legacy_shm_control_word(dev,
1649 B43legacy_SHM_UCODE |
1650 B43legacy_SHM_AUTOINC_W,
1651 0x0000);
1652 for (i = 0; i < len; i++) {
1653 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1654 be32_to_cpu(data[i]));
1655 udelay(10);
1656 }
1657
1658 if (dev->fw.pcm) {
1659 /* Upload PCM data. */
1660 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1661 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1662 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1663 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1664 /* No need for autoinc bit in SHM_HW */
1665 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1666 for (i = 0; i < len; i++) {
1667 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1668 be32_to_cpu(data[i]));
1669 udelay(10);
1670 }
1671 }
1672
1673 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1674 B43legacy_IRQ_ALL);
1675
1676 /* Start the microcode PSM */
1677 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1678 macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1679 macctl |= B43legacy_MACCTL_PSM_RUN;
1680 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1681
1682 /* Wait for the microcode to load and respond */
1683 i = 0;
1684 while (1) {
1685 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1686 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1687 break;
1688 i++;
1689 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1690 b43legacyerr(dev->wl, "Microcode not responding\n");
1691 b43legacy_print_fw_helptext(dev->wl);
1692 err = -ENODEV;
1693 goto error;
1694 }
1695 msleep_interruptible(50);
1696 if (signal_pending(current)) {
1697 err = -EINTR;
1698 goto error;
1699 }
1700 }
1701 /* dummy read follows */
1702 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1703
1704 /* Get and check the revisions. */
1705 fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1706 B43legacy_SHM_SH_UCODEREV);
1707 fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1708 B43legacy_SHM_SH_UCODEPATCH);
1709 fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1710 B43legacy_SHM_SH_UCODEDATE);
1711 fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1712 B43legacy_SHM_SH_UCODETIME);
1713
1714 if (fwrev > 0x128) {
1715 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1716 " Only firmware from binary drivers version 3.x"
1717 " is supported. You must change your firmware"
1718 " files.\n");
1719 b43legacy_print_fw_helptext(dev->wl);
1720 err = -EOPNOTSUPP;
1721 goto error;
1722 }
1723 b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1724 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1725 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1726 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1727 fwtime & 0x1F);
1728
1729 dev->fw.rev = fwrev;
1730 dev->fw.patch = fwpatch;
1731
1732 return 0;
1733
1734 error:
1735 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1736 macctl &= ~B43legacy_MACCTL_PSM_RUN;
1737 macctl |= B43legacy_MACCTL_PSM_JMP0;
1738 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1739
1740 return err;
1741 }
1742
1743 static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1744 const struct b43legacy_iv *ivals,
1745 size_t count,
1746 size_t array_size)
1747 {
1748 const struct b43legacy_iv *iv;
1749 u16 offset;
1750 size_t i;
1751 bool bit32;
1752
1753 BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1754 iv = ivals;
1755 for (i = 0; i < count; i++) {
1756 if (array_size < sizeof(iv->offset_size))
1757 goto err_format;
1758 array_size -= sizeof(iv->offset_size);
1759 offset = be16_to_cpu(iv->offset_size);
1760 bit32 = !!(offset & B43legacy_IV_32BIT);
1761 offset &= B43legacy_IV_OFFSET_MASK;
1762 if (offset >= 0x1000)
1763 goto err_format;
1764 if (bit32) {
1765 u32 value;
1766
1767 if (array_size < sizeof(iv->data.d32))
1768 goto err_format;
1769 array_size -= sizeof(iv->data.d32);
1770
1771 value = get_unaligned_be32(&iv->data.d32);
1772 b43legacy_write32(dev, offset, value);
1773
1774 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1775 sizeof(__be16) +
1776 sizeof(__be32));
1777 } else {
1778 u16 value;
1779
1780 if (array_size < sizeof(iv->data.d16))
1781 goto err_format;
1782 array_size -= sizeof(iv->data.d16);
1783
1784 value = be16_to_cpu(iv->data.d16);
1785 b43legacy_write16(dev, offset, value);
1786
1787 iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1788 sizeof(__be16) +
1789 sizeof(__be16));
1790 }
1791 }
1792 if (array_size)
1793 goto err_format;
1794
1795 return 0;
1796
1797 err_format:
1798 b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1799 b43legacy_print_fw_helptext(dev->wl);
1800
1801 return -EPROTO;
1802 }
1803
1804 static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1805 {
1806 const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1807 const struct b43legacy_fw_header *hdr;
1808 struct b43legacy_firmware *fw = &dev->fw;
1809 const struct b43legacy_iv *ivals;
1810 size_t count;
1811 int err;
1812
1813 hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1814 ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1815 count = be32_to_cpu(hdr->size);
1816 err = b43legacy_write_initvals(dev, ivals, count,
1817 fw->initvals->size - hdr_len);
1818 if (err)
1819 goto out;
1820 if (fw->initvals_band) {
1821 hdr = (const struct b43legacy_fw_header *)
1822 (fw->initvals_band->data);
1823 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1824 + hdr_len);
1825 count = be32_to_cpu(hdr->size);
1826 err = b43legacy_write_initvals(dev, ivals, count,
1827 fw->initvals_band->size - hdr_len);
1828 if (err)
1829 goto out;
1830 }
1831 out:
1832
1833 return err;
1834 }
1835
1836 /* Initialize the GPIOs
1837 * http://bcm-specs.sipsolutions.net/GPIO
1838 */
1839 static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1840 {
1841 struct ssb_bus *bus = dev->dev->bus;
1842 struct ssb_device *gpiodev, *pcidev = NULL;
1843 u32 mask;
1844 u32 set;
1845
1846 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1847 b43legacy_read32(dev,
1848 B43legacy_MMIO_MACCTL)
1849 & 0xFFFF3FFF);
1850
1851 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1852 b43legacy_read16(dev,
1853 B43legacy_MMIO_GPIO_MASK)
1854 | 0x000F);
1855
1856 mask = 0x0000001F;
1857 set = 0x0000000F;
1858 if (dev->dev->bus->chip_id == 0x4301) {
1859 mask |= 0x0060;
1860 set |= 0x0060;
1861 }
1862 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
1863 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1864 b43legacy_read16(dev,
1865 B43legacy_MMIO_GPIO_MASK)
1866 | 0x0200);
1867 mask |= 0x0200;
1868 set |= 0x0200;
1869 }
1870 if (dev->dev->id.revision >= 2)
1871 mask |= 0x0010; /* FIXME: This is redundant. */
1872
1873 #ifdef CONFIG_SSB_DRIVER_PCICORE
1874 pcidev = bus->pcicore.dev;
1875 #endif
1876 gpiodev = bus->chipco.dev ? : pcidev;
1877 if (!gpiodev)
1878 return 0;
1879 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1880 (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1881 & mask) | set);
1882
1883 return 0;
1884 }
1885
1886 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1887 static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1888 {
1889 struct ssb_bus *bus = dev->dev->bus;
1890 struct ssb_device *gpiodev, *pcidev = NULL;
1891
1892 #ifdef CONFIG_SSB_DRIVER_PCICORE
1893 pcidev = bus->pcicore.dev;
1894 #endif
1895 gpiodev = bus->chipco.dev ? : pcidev;
1896 if (!gpiodev)
1897 return;
1898 ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1899 }
1900
1901 /* http://bcm-specs.sipsolutions.net/EnableMac */
1902 void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1903 {
1904 dev->mac_suspended--;
1905 B43legacy_WARN_ON(dev->mac_suspended < 0);
1906 B43legacy_WARN_ON(irqs_disabled());
1907 if (dev->mac_suspended == 0) {
1908 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1909 b43legacy_read32(dev,
1910 B43legacy_MMIO_MACCTL)
1911 | B43legacy_MACCTL_ENABLED);
1912 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1913 B43legacy_IRQ_MAC_SUSPENDED);
1914 /* the next two are dummy reads */
1915 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1916 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1917 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1918
1919 /* Re-enable IRQs. */
1920 spin_lock_irq(&dev->wl->irq_lock);
1921 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1922 dev->irq_mask);
1923 spin_unlock_irq(&dev->wl->irq_lock);
1924 }
1925 }
1926
1927 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1928 void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1929 {
1930 int i;
1931 u32 tmp;
1932
1933 might_sleep();
1934 B43legacy_WARN_ON(irqs_disabled());
1935 B43legacy_WARN_ON(dev->mac_suspended < 0);
1936
1937 if (dev->mac_suspended == 0) {
1938 /* Mask IRQs before suspending MAC. Otherwise
1939 * the MAC stays busy and won't suspend. */
1940 spin_lock_irq(&dev->wl->irq_lock);
1941 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1942 spin_unlock_irq(&dev->wl->irq_lock);
1943 b43legacy_synchronize_irq(dev);
1944
1945 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1946 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1947 b43legacy_read32(dev,
1948 B43legacy_MMIO_MACCTL)
1949 & ~B43legacy_MACCTL_ENABLED);
1950 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1951 for (i = 40; i; i--) {
1952 tmp = b43legacy_read32(dev,
1953 B43legacy_MMIO_GEN_IRQ_REASON);
1954 if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1955 goto out;
1956 msleep(1);
1957 }
1958 b43legacyerr(dev->wl, "MAC suspend failed\n");
1959 }
1960 out:
1961 dev->mac_suspended++;
1962 }
1963
1964 static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1965 {
1966 struct b43legacy_wl *wl = dev->wl;
1967 u32 ctl;
1968 u16 cfp_pretbtt;
1969
1970 ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1971 /* Reset status to STA infrastructure mode. */
1972 ctl &= ~B43legacy_MACCTL_AP;
1973 ctl &= ~B43legacy_MACCTL_KEEP_CTL;
1974 ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
1975 ctl &= ~B43legacy_MACCTL_KEEP_BAD;
1976 ctl &= ~B43legacy_MACCTL_PROMISC;
1977 ctl &= ~B43legacy_MACCTL_BEACPROMISC;
1978 ctl |= B43legacy_MACCTL_INFRA;
1979
1980 if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1981 ctl |= B43legacy_MACCTL_AP;
1982 else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
1983 ctl &= ~B43legacy_MACCTL_INFRA;
1984
1985 if (wl->filter_flags & FIF_CONTROL)
1986 ctl |= B43legacy_MACCTL_KEEP_CTL;
1987 if (wl->filter_flags & FIF_FCSFAIL)
1988 ctl |= B43legacy_MACCTL_KEEP_BAD;
1989 if (wl->filter_flags & FIF_PLCPFAIL)
1990 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
1991 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
1992 ctl |= B43legacy_MACCTL_PROMISC;
1993 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
1994 ctl |= B43legacy_MACCTL_BEACPROMISC;
1995
1996 /* Workaround: On old hardware the HW-MAC-address-filter
1997 * doesn't work properly, so always run promisc in filter
1998 * it in software. */
1999 if (dev->dev->id.revision <= 4)
2000 ctl |= B43legacy_MACCTL_PROMISC;
2001
2002 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2003
2004 cfp_pretbtt = 2;
2005 if ((ctl & B43legacy_MACCTL_INFRA) &&
2006 !(ctl & B43legacy_MACCTL_AP)) {
2007 if (dev->dev->bus->chip_id == 0x4306 &&
2008 dev->dev->bus->chip_rev == 3)
2009 cfp_pretbtt = 100;
2010 else
2011 cfp_pretbtt = 50;
2012 }
2013 b43legacy_write16(dev, 0x612, cfp_pretbtt);
2014 }
2015
2016 static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2017 u16 rate,
2018 int is_ofdm)
2019 {
2020 u16 offset;
2021
2022 if (is_ofdm) {
2023 offset = 0x480;
2024 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2025 } else {
2026 offset = 0x4C0;
2027 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2028 }
2029 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2030 b43legacy_shm_read16(dev,
2031 B43legacy_SHM_SHARED, offset));
2032 }
2033
2034 static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2035 {
2036 switch (dev->phy.type) {
2037 case B43legacy_PHYTYPE_G:
2038 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2039 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2040 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2041 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2042 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2043 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2044 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2045 /* fallthrough */
2046 case B43legacy_PHYTYPE_B:
2047 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2048 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2049 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2050 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2051 break;
2052 default:
2053 B43legacy_BUG_ON(1);
2054 }
2055 }
2056
2057 /* Set the TX-Antenna for management frames sent by firmware. */
2058 static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2059 int antenna)
2060 {
2061 u16 ant = 0;
2062 u16 tmp;
2063
2064 switch (antenna) {
2065 case B43legacy_ANTENNA0:
2066 ant |= B43legacy_TX4_PHY_ANT0;
2067 break;
2068 case B43legacy_ANTENNA1:
2069 ant |= B43legacy_TX4_PHY_ANT1;
2070 break;
2071 case B43legacy_ANTENNA_AUTO:
2072 ant |= B43legacy_TX4_PHY_ANTLAST;
2073 break;
2074 default:
2075 B43legacy_BUG_ON(1);
2076 }
2077
2078 /* FIXME We also need to set the other flags of the PHY control
2079 * field somewhere. */
2080
2081 /* For Beacons */
2082 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2083 B43legacy_SHM_SH_BEACPHYCTL);
2084 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2085 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2086 B43legacy_SHM_SH_BEACPHYCTL, tmp);
2087 /* For ACK/CTS */
2088 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2089 B43legacy_SHM_SH_ACKCTSPHYCTL);
2090 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2091 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2092 B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2093 /* For Probe Resposes */
2094 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2095 B43legacy_SHM_SH_PRPHYCTL);
2096 tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2097 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2098 B43legacy_SHM_SH_PRPHYCTL, tmp);
2099 }
2100
2101 /* This is the opposite of b43legacy_chip_init() */
2102 static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2103 {
2104 b43legacy_radio_turn_off(dev, 1);
2105 b43legacy_gpio_cleanup(dev);
2106 /* firmware is released later */
2107 }
2108
2109 /* Initialize the chip
2110 * http://bcm-specs.sipsolutions.net/ChipInit
2111 */
2112 static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2113 {
2114 struct b43legacy_phy *phy = &dev->phy;
2115 int err;
2116 int tmp;
2117 u32 value32, macctl;
2118 u16 value16;
2119
2120 /* Initialize the MAC control */
2121 macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2122 if (dev->phy.gmode)
2123 macctl |= B43legacy_MACCTL_GMODE;
2124 macctl |= B43legacy_MACCTL_INFRA;
2125 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
2126
2127 err = b43legacy_request_firmware(dev);
2128 if (err)
2129 goto out;
2130 err = b43legacy_upload_microcode(dev);
2131 if (err)
2132 goto out; /* firmware is released later */
2133
2134 err = b43legacy_gpio_init(dev);
2135 if (err)
2136 goto out; /* firmware is released later */
2137
2138 err = b43legacy_upload_initvals(dev);
2139 if (err)
2140 goto err_gpio_clean;
2141 b43legacy_radio_turn_on(dev);
2142
2143 b43legacy_write16(dev, 0x03E6, 0x0000);
2144 err = b43legacy_phy_init(dev);
2145 if (err)
2146 goto err_radio_off;
2147
2148 /* Select initial Interference Mitigation. */
2149 tmp = phy->interfmode;
2150 phy->interfmode = B43legacy_INTERFMODE_NONE;
2151 b43legacy_radio_set_interference_mitigation(dev, tmp);
2152
2153 b43legacy_phy_set_antenna_diversity(dev);
2154 b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2155
2156 if (phy->type == B43legacy_PHYTYPE_B) {
2157 value16 = b43legacy_read16(dev, 0x005E);
2158 value16 |= 0x0004;
2159 b43legacy_write16(dev, 0x005E, value16);
2160 }
2161 b43legacy_write32(dev, 0x0100, 0x01000000);
2162 if (dev->dev->id.revision < 5)
2163 b43legacy_write32(dev, 0x010C, 0x01000000);
2164
2165 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2166 value32 &= ~B43legacy_MACCTL_INFRA;
2167 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2168 value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2169 value32 |= B43legacy_MACCTL_INFRA;
2170 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2171
2172 if (b43legacy_using_pio(dev)) {
2173 b43legacy_write32(dev, 0x0210, 0x00000100);
2174 b43legacy_write32(dev, 0x0230, 0x00000100);
2175 b43legacy_write32(dev, 0x0250, 0x00000100);
2176 b43legacy_write32(dev, 0x0270, 0x00000100);
2177 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2178 0x0000);
2179 }
2180
2181 /* Probe Response Timeout value */
2182 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2183 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2184
2185 /* Initially set the wireless operation mode. */
2186 b43legacy_adjust_opmode(dev);
2187
2188 if (dev->dev->id.revision < 3) {
2189 b43legacy_write16(dev, 0x060E, 0x0000);
2190 b43legacy_write16(dev, 0x0610, 0x8000);
2191 b43legacy_write16(dev, 0x0604, 0x0000);
2192 b43legacy_write16(dev, 0x0606, 0x0200);
2193 } else {
2194 b43legacy_write32(dev, 0x0188, 0x80000000);
2195 b43legacy_write32(dev, 0x018C, 0x02000000);
2196 }
2197 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2198 b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2199 b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2200 b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2201 b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2202 b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2203 b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2204
2205 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2206 value32 |= 0x00100000;
2207 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2208
2209 b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2210 dev->dev->bus->chipco.fast_pwrup_delay);
2211
2212 /* PHY TX errors counter. */
2213 atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2214
2215 B43legacy_WARN_ON(err != 0);
2216 b43legacydbg(dev->wl, "Chip initialized\n");
2217 out:
2218 return err;
2219
2220 err_radio_off:
2221 b43legacy_radio_turn_off(dev, 1);
2222 err_gpio_clean:
2223 b43legacy_gpio_cleanup(dev);
2224 goto out;
2225 }
2226
2227 static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2228 {
2229 struct b43legacy_phy *phy = &dev->phy;
2230
2231 if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2232 return;
2233
2234 b43legacy_mac_suspend(dev);
2235 b43legacy_phy_lo_g_measure(dev);
2236 b43legacy_mac_enable(dev);
2237 }
2238
2239 static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2240 {
2241 b43legacy_phy_lo_mark_all_unused(dev);
2242 if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
2243 b43legacy_mac_suspend(dev);
2244 b43legacy_calc_nrssi_slope(dev);
2245 b43legacy_mac_enable(dev);
2246 }
2247 }
2248
2249 static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2250 {
2251 /* Update device statistics. */
2252 b43legacy_calculate_link_quality(dev);
2253 }
2254
2255 static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2256 {
2257 b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
2258
2259 atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2260 wmb();
2261 }
2262
2263 static void do_periodic_work(struct b43legacy_wldev *dev)
2264 {
2265 unsigned int state;
2266
2267 state = dev->periodic_state;
2268 if (state % 8 == 0)
2269 b43legacy_periodic_every120sec(dev);
2270 if (state % 4 == 0)
2271 b43legacy_periodic_every60sec(dev);
2272 if (state % 2 == 0)
2273 b43legacy_periodic_every30sec(dev);
2274 b43legacy_periodic_every15sec(dev);
2275 }
2276
2277 /* Periodic work locking policy:
2278 * The whole periodic work handler is protected by
2279 * wl->mutex. If another lock is needed somewhere in the
2280 * pwork callchain, it's aquired in-place, where it's needed.
2281 */
2282 static void b43legacy_periodic_work_handler(struct work_struct *work)
2283 {
2284 struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2285 periodic_work.work);
2286 struct b43legacy_wl *wl = dev->wl;
2287 unsigned long delay;
2288
2289 mutex_lock(&wl->mutex);
2290
2291 if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2292 goto out;
2293 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2294 goto out_requeue;
2295
2296 do_periodic_work(dev);
2297
2298 dev->periodic_state++;
2299 out_requeue:
2300 if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2301 delay = msecs_to_jiffies(50);
2302 else
2303 delay = round_jiffies_relative(HZ * 15);
2304 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2305 out:
2306 mutex_unlock(&wl->mutex);
2307 }
2308
2309 static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2310 {
2311 struct delayed_work *work = &dev->periodic_work;
2312
2313 dev->periodic_state = 0;
2314 INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2315 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2316 }
2317
2318 /* Validate access to the chip (SHM) */
2319 static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2320 {
2321 u32 value;
2322 u32 shm_backup;
2323
2324 shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2325 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2326 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2327 0xAA5555AA)
2328 goto error;
2329 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2330 if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2331 0x55AAAA55)
2332 goto error;
2333 b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2334
2335 value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2336 if ((value | B43legacy_MACCTL_GMODE) !=
2337 (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2338 goto error;
2339
2340 value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2341 if (value)
2342 goto error;
2343
2344 return 0;
2345 error:
2346 b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2347 return -ENODEV;
2348 }
2349
2350 static void b43legacy_security_init(struct b43legacy_wldev *dev)
2351 {
2352 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2353 B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2354 dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2355 0x0056);
2356 /* KTP is a word address, but we address SHM bytewise.
2357 * So multiply by two.
2358 */
2359 dev->ktp *= 2;
2360 if (dev->dev->id.revision >= 5)
2361 /* Number of RCMTA address slots */
2362 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2363 dev->max_nr_keys - 8);
2364 }
2365
2366 #ifdef CONFIG_B43LEGACY_HWRNG
2367 static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2368 {
2369 struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2370 unsigned long flags;
2371
2372 /* Don't take wl->mutex here, as it could deadlock with
2373 * hwrng internal locking. It's not needed to take
2374 * wl->mutex here, anyway. */
2375
2376 spin_lock_irqsave(&wl->irq_lock, flags);
2377 *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2378 spin_unlock_irqrestore(&wl->irq_lock, flags);
2379
2380 return (sizeof(u16));
2381 }
2382 #endif
2383
2384 static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2385 {
2386 #ifdef CONFIG_B43LEGACY_HWRNG
2387 if (wl->rng_initialized)
2388 hwrng_unregister(&wl->rng);
2389 #endif
2390 }
2391
2392 static int b43legacy_rng_init(struct b43legacy_wl *wl)
2393 {
2394 int err = 0;
2395
2396 #ifdef CONFIG_B43LEGACY_HWRNG
2397 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2398 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2399 wl->rng.name = wl->rng_name;
2400 wl->rng.data_read = b43legacy_rng_read;
2401 wl->rng.priv = (unsigned long)wl;
2402 wl->rng_initialized = 1;
2403 err = hwrng_register(&wl->rng);
2404 if (err) {
2405 wl->rng_initialized = 0;
2406 b43legacyerr(wl, "Failed to register the random "
2407 "number generator (%d)\n", err);
2408 }
2409
2410 #endif
2411 return err;
2412 }
2413
2414 static int b43legacy_op_tx(struct ieee80211_hw *hw,
2415 struct sk_buff *skb)
2416 {
2417 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2418 struct b43legacy_wldev *dev = wl->current_dev;
2419 int err = -ENODEV;
2420 unsigned long flags;
2421
2422 if (unlikely(!dev))
2423 goto out;
2424 if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2425 goto out;
2426 /* DMA-TX is done without a global lock. */
2427 if (b43legacy_using_pio(dev)) {
2428 spin_lock_irqsave(&wl->irq_lock, flags);
2429 err = b43legacy_pio_tx(dev, skb);
2430 spin_unlock_irqrestore(&wl->irq_lock, flags);
2431 } else
2432 err = b43legacy_dma_tx(dev, skb);
2433 out:
2434 if (unlikely(err)) {
2435 /* Drop the packet. */
2436 dev_kfree_skb_any(skb);
2437 }
2438 return NETDEV_TX_OK;
2439 }
2440
2441 static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
2442 const struct ieee80211_tx_queue_params *params)
2443 {
2444 return 0;
2445 }
2446
2447 static int b43legacy_op_get_tx_stats(struct ieee80211_hw *hw,
2448 struct ieee80211_tx_queue_stats *stats)
2449 {
2450 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2451 struct b43legacy_wldev *dev = wl->current_dev;
2452 unsigned long flags;
2453 int err = -ENODEV;
2454
2455 if (!dev)
2456 goto out;
2457 spin_lock_irqsave(&wl->irq_lock, flags);
2458 if (likely(b43legacy_status(dev) >= B43legacy_STAT_STARTED)) {
2459 if (b43legacy_using_pio(dev))
2460 b43legacy_pio_get_tx_stats(dev, stats);
2461 else
2462 b43legacy_dma_get_tx_stats(dev, stats);
2463 err = 0;
2464 }
2465 spin_unlock_irqrestore(&wl->irq_lock, flags);
2466 out:
2467 return err;
2468 }
2469
2470 static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2471 struct ieee80211_low_level_stats *stats)
2472 {
2473 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2474 unsigned long flags;
2475
2476 spin_lock_irqsave(&wl->irq_lock, flags);
2477 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2478 spin_unlock_irqrestore(&wl->irq_lock, flags);
2479
2480 return 0;
2481 }
2482
2483 static const char *phymode_to_string(unsigned int phymode)
2484 {
2485 switch (phymode) {
2486 case B43legacy_PHYMODE_B:
2487 return "B";
2488 case B43legacy_PHYMODE_G:
2489 return "G";
2490 default:
2491 B43legacy_BUG_ON(1);
2492 }
2493 return "";
2494 }
2495
2496 static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2497 unsigned int phymode,
2498 struct b43legacy_wldev **dev,
2499 bool *gmode)
2500 {
2501 struct b43legacy_wldev *d;
2502
2503 list_for_each_entry(d, &wl->devlist, list) {
2504 if (d->phy.possible_phymodes & phymode) {
2505 /* Ok, this device supports the PHY-mode.
2506 * Set the gmode bit. */
2507 *gmode = 1;
2508 *dev = d;
2509
2510 return 0;
2511 }
2512 }
2513
2514 return -ESRCH;
2515 }
2516
2517 static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2518 {
2519 struct ssb_device *sdev = dev->dev;
2520 u32 tmslow;
2521
2522 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2523 tmslow &= ~B43legacy_TMSLOW_GMODE;
2524 tmslow |= B43legacy_TMSLOW_PHYRESET;
2525 tmslow |= SSB_TMSLOW_FGC;
2526 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2527 msleep(1);
2528
2529 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2530 tmslow &= ~SSB_TMSLOW_FGC;
2531 tmslow |= B43legacy_TMSLOW_PHYRESET;
2532 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2533 msleep(1);
2534 }
2535
2536 /* Expects wl->mutex locked */
2537 static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2538 unsigned int new_mode)
2539 {
2540 struct b43legacy_wldev *uninitialized_var(up_dev);
2541 struct b43legacy_wldev *down_dev;
2542 int err;
2543 bool gmode = 0;
2544 int prev_status;
2545
2546 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2547 if (err) {
2548 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2549 phymode_to_string(new_mode));
2550 return err;
2551 }
2552 if ((up_dev == wl->current_dev) &&
2553 (!!wl->current_dev->phy.gmode == !!gmode))
2554 /* This device is already running. */
2555 return 0;
2556 b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2557 phymode_to_string(new_mode));
2558 down_dev = wl->current_dev;
2559
2560 prev_status = b43legacy_status(down_dev);
2561 /* Shutdown the currently running core. */
2562 if (prev_status >= B43legacy_STAT_STARTED)
2563 b43legacy_wireless_core_stop(down_dev);
2564 if (prev_status >= B43legacy_STAT_INITIALIZED)
2565 b43legacy_wireless_core_exit(down_dev);
2566
2567 if (down_dev != up_dev)
2568 /* We switch to a different core, so we put PHY into
2569 * RESET on the old core. */
2570 b43legacy_put_phy_into_reset(down_dev);
2571
2572 /* Now start the new core. */
2573 up_dev->phy.gmode = gmode;
2574 if (prev_status >= B43legacy_STAT_INITIALIZED) {
2575 err = b43legacy_wireless_core_init(up_dev);
2576 if (err) {
2577 b43legacyerr(wl, "Fatal: Could not initialize device"
2578 " for newly selected %s-PHY mode\n",
2579 phymode_to_string(new_mode));
2580 goto init_failure;
2581 }
2582 }
2583 if (prev_status >= B43legacy_STAT_STARTED) {
2584 err = b43legacy_wireless_core_start(up_dev);
2585 if (err) {
2586 b43legacyerr(wl, "Fatal: Coult not start device for "
2587 "newly selected %s-PHY mode\n",
2588 phymode_to_string(new_mode));
2589 b43legacy_wireless_core_exit(up_dev);
2590 goto init_failure;
2591 }
2592 }
2593 B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2594
2595 b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2596
2597 wl->current_dev = up_dev;
2598
2599 return 0;
2600 init_failure:
2601 /* Whoops, failed to init the new core. No core is operating now. */
2602 wl->current_dev = NULL;
2603 return err;
2604 }
2605
2606 /* Write the short and long frame retry limit values. */
2607 static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2608 unsigned int short_retry,
2609 unsigned int long_retry)
2610 {
2611 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2612 * the chip-internal counter. */
2613 short_retry = min(short_retry, (unsigned int)0xF);
2614 long_retry = min(long_retry, (unsigned int)0xF);
2615
2616 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2617 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2618 }
2619
2620 static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2621 u32 changed)
2622 {
2623 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2624 struct b43legacy_wldev *dev;
2625 struct b43legacy_phy *phy;
2626 struct ieee80211_conf *conf = &hw->conf;
2627 unsigned long flags;
2628 unsigned int new_phymode = 0xFFFF;
2629 int antenna_tx;
2630 int antenna_rx;
2631 int err = 0;
2632
2633 antenna_tx = B43legacy_ANTENNA_DEFAULT;
2634 antenna_rx = B43legacy_ANTENNA_DEFAULT;
2635
2636 mutex_lock(&wl->mutex);
2637 dev = wl->current_dev;
2638 phy = &dev->phy;
2639
2640 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2641 b43legacy_set_retry_limits(dev,
2642 conf->short_frame_max_tx_count,
2643 conf->long_frame_max_tx_count);
2644 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2645 if (!changed)
2646 goto out_unlock_mutex;
2647
2648 /* Switch the PHY mode (if necessary). */
2649 switch (conf->channel->band) {
2650 case IEEE80211_BAND_2GHZ:
2651 if (phy->type == B43legacy_PHYTYPE_B)
2652 new_phymode = B43legacy_PHYMODE_B;
2653 else
2654 new_phymode = B43legacy_PHYMODE_G;
2655 break;
2656 default:
2657 B43legacy_WARN_ON(1);
2658 }
2659 err = b43legacy_switch_phymode(wl, new_phymode);
2660 if (err)
2661 goto out_unlock_mutex;
2662
2663 /* Disable IRQs while reconfiguring the device.
2664 * This makes it possible to drop the spinlock throughout
2665 * the reconfiguration process. */
2666 spin_lock_irqsave(&wl->irq_lock, flags);
2667 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2668 spin_unlock_irqrestore(&wl->irq_lock, flags);
2669 goto out_unlock_mutex;
2670 }
2671 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2672 spin_unlock_irqrestore(&wl->irq_lock, flags);
2673 b43legacy_synchronize_irq(dev);
2674
2675 /* Switch to the requested channel.
2676 * The firmware takes care of races with the TX handler. */
2677 if (conf->channel->hw_value != phy->channel)
2678 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
2679
2680 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2681
2682 /* Adjust the desired TX power level. */
2683 if (conf->power_level != 0) {
2684 if (conf->power_level != phy->power_level) {
2685 phy->power_level = conf->power_level;
2686 b43legacy_phy_xmitpower(dev);
2687 }
2688 }
2689
2690 /* Antennas for RX and management frame TX. */
2691 b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2692
2693 if (wl->radio_enabled != phy->radio_on) {
2694 if (wl->radio_enabled) {
2695 b43legacy_radio_turn_on(dev);
2696 b43legacyinfo(dev->wl, "Radio turned on by software\n");
2697 if (!dev->radio_hw_enable)
2698 b43legacyinfo(dev->wl, "The hardware RF-kill"
2699 " button still turns the radio"
2700 " physically off. Press the"
2701 " button to turn it on.\n");
2702 } else {
2703 b43legacy_radio_turn_off(dev, 0);
2704 b43legacyinfo(dev->wl, "Radio turned off by"
2705 " software\n");
2706 }
2707 }
2708
2709 spin_lock_irqsave(&wl->irq_lock, flags);
2710 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2711 mmiowb();
2712 spin_unlock_irqrestore(&wl->irq_lock, flags);
2713 out_unlock_mutex:
2714 mutex_unlock(&wl->mutex);
2715
2716 return err;
2717 }
2718
2719 static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
2720 {
2721 struct ieee80211_supported_band *sband =
2722 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2723 struct ieee80211_rate *rate;
2724 int i;
2725 u16 basic, direct, offset, basic_offset, rateptr;
2726
2727 for (i = 0; i < sband->n_bitrates; i++) {
2728 rate = &sband->bitrates[i];
2729
2730 if (b43legacy_is_cck_rate(rate->hw_value)) {
2731 direct = B43legacy_SHM_SH_CCKDIRECT;
2732 basic = B43legacy_SHM_SH_CCKBASIC;
2733 offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2734 offset &= 0xF;
2735 } else {
2736 direct = B43legacy_SHM_SH_OFDMDIRECT;
2737 basic = B43legacy_SHM_SH_OFDMBASIC;
2738 offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2739 offset &= 0xF;
2740 }
2741
2742 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2743
2744 if (b43legacy_is_cck_rate(rate->hw_value)) {
2745 basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2746 basic_offset &= 0xF;
2747 } else {
2748 basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2749 basic_offset &= 0xF;
2750 }
2751
2752 /*
2753 * Get the pointer that we need to point to
2754 * from the direct map
2755 */
2756 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2757 direct + 2 * basic_offset);
2758 /* and write it to the basic map */
2759 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2760 basic + 2 * offset, rateptr);
2761 }
2762 }
2763
2764 static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2765 struct ieee80211_vif *vif,
2766 struct ieee80211_bss_conf *conf,
2767 u32 changed)
2768 {
2769 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2770 struct b43legacy_wldev *dev;
2771 struct b43legacy_phy *phy;
2772 unsigned long flags;
2773
2774 mutex_lock(&wl->mutex);
2775 B43legacy_WARN_ON(wl->vif != vif);
2776
2777 dev = wl->current_dev;
2778 phy = &dev->phy;
2779
2780 /* Disable IRQs while reconfiguring the device.
2781 * This makes it possible to drop the spinlock throughout
2782 * the reconfiguration process. */
2783 spin_lock_irqsave(&wl->irq_lock, flags);
2784 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2785 spin_unlock_irqrestore(&wl->irq_lock, flags);
2786 goto out_unlock_mutex;
2787 }
2788 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2789
2790 if (changed & BSS_CHANGED_BSSID) {
2791 b43legacy_synchronize_irq(dev);
2792
2793 if (conf->bssid)
2794 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2795 else
2796 memset(wl->bssid, 0, ETH_ALEN);
2797 }
2798
2799 if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2800 if (changed & BSS_CHANGED_BEACON &&
2801 (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2802 b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2803 b43legacy_update_templates(wl);
2804
2805 if (changed & BSS_CHANGED_BSSID)
2806 b43legacy_write_mac_bssid_templates(dev);
2807 }
2808 spin_unlock_irqrestore(&wl->irq_lock, flags);
2809
2810 b43legacy_mac_suspend(dev);
2811
2812 if (changed & BSS_CHANGED_BEACON_INT &&
2813 (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2814 b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2815 b43legacy_set_beacon_int(dev, conf->beacon_int);
2816
2817 if (changed & BSS_CHANGED_BASIC_RATES)
2818 b43legacy_update_basic_rates(dev, conf->basic_rates);
2819
2820 if (changed & BSS_CHANGED_ERP_SLOT) {
2821 if (conf->use_short_slot)
2822 b43legacy_short_slot_timing_enable(dev);
2823 else
2824 b43legacy_short_slot_timing_disable(dev);
2825 }
2826
2827 b43legacy_mac_enable(dev);
2828
2829 spin_lock_irqsave(&wl->irq_lock, flags);
2830 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2831 /* XXX: why? */
2832 mmiowb();
2833 spin_unlock_irqrestore(&wl->irq_lock, flags);
2834 out_unlock_mutex:
2835 mutex_unlock(&wl->mutex);
2836 }
2837
2838 static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2839 unsigned int changed,
2840 unsigned int *fflags,u64 multicast)
2841 {
2842 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2843 struct b43legacy_wldev *dev = wl->current_dev;
2844 unsigned long flags;
2845
2846 if (!dev) {
2847 *fflags = 0;
2848 return;
2849 }
2850
2851 spin_lock_irqsave(&wl->irq_lock, flags);
2852 *fflags &= FIF_PROMISC_IN_BSS |
2853 FIF_ALLMULTI |
2854 FIF_FCSFAIL |
2855 FIF_PLCPFAIL |
2856 FIF_CONTROL |
2857 FIF_OTHER_BSS |
2858 FIF_BCN_PRBRESP_PROMISC;
2859
2860 changed &= FIF_PROMISC_IN_BSS |
2861 FIF_ALLMULTI |
2862 FIF_FCSFAIL |
2863 FIF_PLCPFAIL |
2864 FIF_CONTROL |
2865 FIF_OTHER_BSS |
2866 FIF_BCN_PRBRESP_PROMISC;
2867
2868 wl->filter_flags = *fflags;
2869
2870 if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2871 b43legacy_adjust_opmode(dev);
2872 spin_unlock_irqrestore(&wl->irq_lock, flags);
2873 }
2874
2875 /* Locking: wl->mutex */
2876 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2877 {
2878 struct b43legacy_wl *wl = dev->wl;
2879 unsigned long flags;
2880
2881 if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2882 return;
2883
2884 /* Disable and sync interrupts. We must do this before than
2885 * setting the status to INITIALIZED, as the interrupt handler
2886 * won't care about IRQs then. */
2887 spin_lock_irqsave(&wl->irq_lock, flags);
2888 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2889 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2890 spin_unlock_irqrestore(&wl->irq_lock, flags);
2891 b43legacy_synchronize_irq(dev);
2892
2893 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2894
2895 mutex_unlock(&wl->mutex);
2896 /* Must unlock as it would otherwise deadlock. No races here.
2897 * Cancel the possibly running self-rearming periodic work. */
2898 cancel_delayed_work_sync(&dev->periodic_work);
2899 mutex_lock(&wl->mutex);
2900
2901 ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2902
2903 b43legacy_mac_suspend(dev);
2904 free_irq(dev->dev->irq, dev);
2905 b43legacydbg(wl, "Wireless interface stopped\n");
2906 }
2907
2908 /* Locking: wl->mutex */
2909 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2910 {
2911 int err;
2912
2913 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2914
2915 drain_txstatus_queue(dev);
2916 err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2917 IRQF_SHARED, KBUILD_MODNAME, dev);
2918 if (err) {
2919 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2920 dev->dev->irq);
2921 goto out;
2922 }
2923 /* We are ready to run. */
2924 b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2925
2926 /* Start data flow (TX/RX) */
2927 b43legacy_mac_enable(dev);
2928 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2929
2930 /* Start maintenance work */
2931 b43legacy_periodic_tasks_setup(dev);
2932
2933 b43legacydbg(dev->wl, "Wireless interface started\n");
2934 out:
2935 return err;
2936 }
2937
2938 /* Get PHY and RADIO versioning numbers */
2939 static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2940 {
2941 struct b43legacy_phy *phy = &dev->phy;
2942 u32 tmp;
2943 u8 analog_type;
2944 u8 phy_type;
2945 u8 phy_rev;
2946 u16 radio_manuf;
2947 u16 radio_ver;
2948 u16 radio_rev;
2949 int unsupported = 0;
2950
2951 /* Get PHY versioning */
2952 tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2953 analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2954 >> B43legacy_PHYVER_ANALOG_SHIFT;
2955 phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2956 phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2957 switch (phy_type) {
2958 case B43legacy_PHYTYPE_B:
2959 if (phy_rev != 2 && phy_rev != 4
2960 && phy_rev != 6 && phy_rev != 7)
2961 unsupported = 1;
2962 break;
2963 case B43legacy_PHYTYPE_G:
2964 if (phy_rev > 8)
2965 unsupported = 1;
2966 break;
2967 default:
2968 unsupported = 1;
2969 };
2970 if (unsupported) {
2971 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2972 "(Analog %u, Type %u, Revision %u)\n",
2973 analog_type, phy_type, phy_rev);
2974 return -EOPNOTSUPP;
2975 }
2976 b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2977 analog_type, phy_type, phy_rev);
2978
2979
2980 /* Get RADIO versioning */
2981 if (dev->dev->bus->chip_id == 0x4317) {
2982 if (dev->dev->bus->chip_rev == 0)
2983 tmp = 0x3205017F;
2984 else if (dev->dev->bus->chip_rev == 1)
2985 tmp = 0x4205017F;
2986 else
2987 tmp = 0x5205017F;
2988 } else {
2989 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2990 B43legacy_RADIOCTL_ID);
2991 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
2992 tmp <<= 16;
2993 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2994 B43legacy_RADIOCTL_ID);
2995 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
2996 }
2997 radio_manuf = (tmp & 0x00000FFF);
2998 radio_ver = (tmp & 0x0FFFF000) >> 12;
2999 radio_rev = (tmp & 0xF0000000) >> 28;
3000 switch (phy_type) {
3001 case B43legacy_PHYTYPE_B:
3002 if ((radio_ver & 0xFFF0) != 0x2050)
3003 unsupported = 1;
3004 break;
3005 case B43legacy_PHYTYPE_G:
3006 if (radio_ver != 0x2050)
3007 unsupported = 1;
3008 break;
3009 default:
3010 B43legacy_BUG_ON(1);
3011 }
3012 if (unsupported) {
3013 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
3014 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3015 radio_manuf, radio_ver, radio_rev);
3016 return -EOPNOTSUPP;
3017 }
3018 b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
3019 " Revision %u\n", radio_manuf, radio_ver, radio_rev);
3020
3021
3022 phy->radio_manuf = radio_manuf;
3023 phy->radio_ver = radio_ver;
3024 phy->radio_rev = radio_rev;
3025
3026 phy->analog = analog_type;
3027 phy->type = phy_type;
3028 phy->rev = phy_rev;
3029
3030 return 0;
3031 }
3032
3033 static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
3034 struct b43legacy_phy *phy)
3035 {
3036 struct b43legacy_lopair *lo;
3037 int i;
3038
3039 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3040 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3041
3042 /* Assume the radio is enabled. If it's not enabled, the state will
3043 * immediately get fixed on the first periodic work run. */
3044 dev->radio_hw_enable = 1;
3045
3046 phy->savedpctlreg = 0xFFFF;
3047 phy->aci_enable = 0;
3048 phy->aci_wlan_automatic = 0;
3049 phy->aci_hw_rssi = 0;
3050
3051 lo = phy->_lo_pairs;
3052 if (lo)
3053 memset(lo, 0, sizeof(struct b43legacy_lopair) *
3054 B43legacy_LO_COUNT);
3055 phy->max_lb_gain = 0;
3056 phy->trsw_rx_gain = 0;
3057
3058 /* Set default attenuation values. */
3059 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3060 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3061 phy->txctl1 = b43legacy_default_txctl1(dev);
3062 phy->txpwr_offset = 0;
3063
3064 /* NRSSI */
3065 phy->nrssislope = 0;
3066 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3067 phy->nrssi[i] = -1000;
3068 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3069 phy->nrssi_lt[i] = i;
3070
3071 phy->lofcal = 0xFFFF;
3072 phy->initval = 0xFFFF;
3073
3074 phy->interfmode = B43legacy_INTERFMODE_NONE;
3075 phy->channel = 0xFF;
3076 }
3077
3078 static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
3079 {
3080 /* Flags */
3081 dev->dfq_valid = 0;
3082
3083 /* Stats */
3084 memset(&dev->stats, 0, sizeof(dev->stats));
3085
3086 setup_struct_phy_for_init(dev, &dev->phy);
3087
3088 /* IRQ related flags */
3089 dev->irq_reason = 0;
3090 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3091 dev->irq_mask = B43legacy_IRQ_MASKTEMPLATE;
3092
3093 dev->mac_suspended = 1;
3094
3095 /* Noise calculation context */
3096 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3097 }
3098
3099 static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
3100 {
3101 #ifdef CONFIG_SSB_DRIVER_PCICORE
3102 struct ssb_bus *bus = dev->dev->bus;
3103 u32 tmp;
3104
3105 if (bus->pcicore.dev &&
3106 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3107 bus->pcicore.dev->id.revision <= 5) {
3108 /* IMCFGLO timeouts workaround. */
3109 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3110 switch (bus->bustype) {
3111 case SSB_BUSTYPE_PCI:
3112 case SSB_BUSTYPE_PCMCIA:
3113 tmp &= ~SSB_IMCFGLO_REQTO;
3114 tmp &= ~SSB_IMCFGLO_SERTO;
3115 tmp |= 0x32;
3116 break;
3117 case SSB_BUSTYPE_SSB:
3118 tmp &= ~SSB_IMCFGLO_REQTO;
3119 tmp &= ~SSB_IMCFGLO_SERTO;
3120 tmp |= 0x53;
3121 break;
3122 default:
3123 break;
3124 }
3125 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3126 }
3127 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3128 }
3129
3130 static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,
3131 bool idle) {
3132 u16 pu_delay = 1050;
3133
3134 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3135 pu_delay = 500;
3136 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3137 pu_delay = max(pu_delay, (u16)2400);
3138
3139 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3140 B43legacy_SHM_SH_SPUWKUP, pu_delay);
3141 }
3142
3143 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3144 static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev)
3145 {
3146 u16 pretbtt;
3147
3148 /* The time value is in microseconds. */
3149 if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3150 pretbtt = 2;
3151 else
3152 pretbtt = 250;
3153 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3154 B43legacy_SHM_SH_PRETBTT, pretbtt);
3155 b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt);
3156 }
3157
3158 /* Shutdown a wireless core */
3159 /* Locking: wl->mutex */
3160 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
3161 {
3162 struct b43legacy_phy *phy = &dev->phy;
3163 u32 macctl;
3164
3165 B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
3166 if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
3167 return;
3168 b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3169
3170 /* Stop the microcode PSM. */
3171 macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3172 macctl &= ~B43legacy_MACCTL_PSM_RUN;
3173 macctl |= B43legacy_MACCTL_PSM_JMP0;
3174 b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3175
3176 b43legacy_leds_exit(dev);
3177 b43legacy_rng_exit(dev->wl);
3178 b43legacy_pio_free(dev);
3179 b43legacy_dma_free(dev);
3180 b43legacy_chip_exit(dev);
3181 b43legacy_radio_turn_off(dev, 1);
3182 b43legacy_switch_analog(dev, 0);
3183 if (phy->dyn_tssi_tbl)
3184 kfree(phy->tssi2dbm);
3185 kfree(phy->lo_control);
3186 phy->lo_control = NULL;
3187 if (dev->wl->current_beacon) {
3188 dev_kfree_skb_any(dev->wl->current_beacon);
3189 dev->wl->current_beacon = NULL;
3190 }
3191
3192 ssb_device_disable(dev->dev, 0);
3193 ssb_bus_may_powerdown(dev->dev->bus);
3194 }
3195
3196 static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3197 {
3198 struct b43legacy_phy *phy = &dev->phy;
3199 int i;
3200
3201 /* Set default attenuation values. */
3202 phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3203 phy->rfatt = b43legacy_default_radio_attenuation(dev);
3204 phy->txctl1 = b43legacy_default_txctl1(dev);
3205 phy->txctl2 = 0xFFFF;
3206 phy->txpwr_offset = 0;
3207
3208 /* NRSSI */
3209 phy->nrssislope = 0;
3210 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3211 phy->nrssi[i] = -1000;
3212 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3213 phy->nrssi_lt[i] = i;
3214
3215 phy->lofcal = 0xFFFF;
3216 phy->initval = 0xFFFF;
3217
3218 phy->aci_enable = 0;
3219 phy->aci_wlan_automatic = 0;
3220 phy->aci_hw_rssi = 0;
3221
3222 phy->antenna_diversity = 0xFFFF;
3223 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3224 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3225
3226 /* Flags */
3227 phy->calibrated = 0;
3228
3229 if (phy->_lo_pairs)
3230 memset(phy->_lo_pairs, 0,
3231 sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3232 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3233 }
3234
3235 /* Initialize a wireless core */
3236 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3237 {
3238 struct b43legacy_wl *wl = dev->wl;
3239 struct ssb_bus *bus = dev->dev->bus;
3240 struct b43legacy_phy *phy = &dev->phy;
3241 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3242 int err;
3243 u32 hf;
3244 u32 tmp;
3245
3246 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3247
3248 err = ssb_bus_powerup(bus, 0);
3249 if (err)
3250 goto out;
3251 if (!ssb_device_is_enabled(dev->dev)) {
3252 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3253 b43legacy_wireless_core_reset(dev, tmp);
3254 }
3255
3256 if ((phy->type == B43legacy_PHYTYPE_B) ||
3257 (phy->type == B43legacy_PHYTYPE_G)) {
3258 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3259 * B43legacy_LO_COUNT,
3260 GFP_KERNEL);
3261 if (!phy->_lo_pairs)
3262 return -ENOMEM;
3263 }
3264 setup_struct_wldev_for_init(dev);
3265
3266 err = b43legacy_phy_init_tssi2dbm_table(dev);
3267 if (err)
3268 goto err_kfree_lo_control;
3269
3270 /* Enable IRQ routing to this device. */
3271 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3272
3273 b43legacy_imcfglo_timeouts_workaround(dev);
3274 prepare_phy_data_for_init(dev);
3275 b43legacy_phy_calibrate(dev);
3276 err = b43legacy_chip_init(dev);
3277 if (err)
3278 goto err_kfree_tssitbl;
3279 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3280 B43legacy_SHM_SH_WLCOREREV,
3281 dev->dev->id.revision);
3282 hf = b43legacy_hf_read(dev);
3283 if (phy->type == B43legacy_PHYTYPE_G) {
3284 hf |= B43legacy_HF_SYMW;
3285 if (phy->rev == 1)
3286 hf |= B43legacy_HF_GDCW;
3287 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
3288 hf |= B43legacy_HF_OFDMPABOOST;
3289 } else if (phy->type == B43legacy_PHYTYPE_B) {
3290 hf |= B43legacy_HF_SYMW;
3291 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3292 hf &= ~B43legacy_HF_GDCW;
3293 }
3294 b43legacy_hf_write(dev, hf);
3295
3296 b43legacy_set_retry_limits(dev,
3297 B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3298 B43legacy_DEFAULT_LONG_RETRY_LIMIT);
3299
3300 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3301 0x0044, 3);
3302 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3303 0x0046, 2);
3304
3305 /* Disable sending probe responses from firmware.
3306 * Setting the MaxTime to one usec will always trigger
3307 * a timeout, so we never send any probe resp.
3308 * A timeout of zero is infinite. */
3309 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3310 B43legacy_SHM_SH_PRMAXTIME, 1);
3311
3312 b43legacy_rate_memory_init(dev);
3313
3314 /* Minimum Contention Window */
3315 if (phy->type == B43legacy_PHYTYPE_B)
3316 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3317 0x0003, 31);
3318 else
3319 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3320 0x0003, 15);
3321 /* Maximum Contention Window */
3322 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3323 0x0004, 1023);
3324
3325 do {
3326 if (b43legacy_using_pio(dev))
3327 err = b43legacy_pio_init(dev);
3328 else {
3329 err = b43legacy_dma_init(dev);
3330 if (!err)
3331 b43legacy_qos_init(dev);
3332 }
3333 } while (err == -EAGAIN);
3334 if (err)
3335 goto err_chip_exit;
3336
3337 b43legacy_set_synth_pu_delay(dev, 1);
3338
3339 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3340 b43legacy_upload_card_macaddress(dev);
3341 b43legacy_security_init(dev);
3342 b43legacy_rng_init(wl);
3343
3344 b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3345
3346 b43legacy_leds_init(dev);
3347 out:
3348 return err;
3349
3350 err_chip_exit:
3351 b43legacy_chip_exit(dev);
3352 err_kfree_tssitbl:
3353 if (phy->dyn_tssi_tbl)
3354 kfree(phy->tssi2dbm);
3355 err_kfree_lo_control:
3356 kfree(phy->lo_control);
3357 phy->lo_control = NULL;
3358 ssb_bus_may_powerdown(bus);
3359 B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3360 return err;
3361 }
3362
3363 static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
3364 struct ieee80211_if_init_conf *conf)
3365 {
3366 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3367 struct b43legacy_wldev *dev;
3368 unsigned long flags;
3369 int err = -EOPNOTSUPP;
3370
3371 /* TODO: allow WDS/AP devices to coexist */
3372
3373 if (conf->type != NL80211_IFTYPE_AP &&
3374 conf->type != NL80211_IFTYPE_STATION &&
3375 conf->type != NL80211_IFTYPE_WDS &&
3376 conf->type != NL80211_IFTYPE_ADHOC)
3377 return -EOPNOTSUPP;
3378
3379 mutex_lock(&wl->mutex);
3380 if (wl->operating)
3381 goto out_mutex_unlock;
3382
3383 b43legacydbg(wl, "Adding Interface type %d\n", conf->type);
3384
3385 dev = wl->current_dev;
3386 wl->operating = 1;
3387 wl->vif = conf->vif;
3388 wl->if_type = conf->type;
3389 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3390
3391 spin_lock_irqsave(&wl->irq_lock, flags);
3392 b43legacy_adjust_opmode(dev);
3393 b43legacy_set_pretbtt(dev);
3394 b43legacy_set_synth_pu_delay(dev, 0);
3395 b43legacy_upload_card_macaddress(dev);
3396 spin_unlock_irqrestore(&wl->irq_lock, flags);
3397
3398 err = 0;
3399 out_mutex_unlock:
3400 mutex_unlock(&wl->mutex);
3401
3402 return err;
3403 }
3404
3405 static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
3406 struct ieee80211_if_init_conf *conf)
3407 {
3408 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3409 struct b43legacy_wldev *dev = wl->current_dev;
3410 unsigned long flags;
3411
3412 b43legacydbg(wl, "Removing Interface type %d\n", conf->type);
3413
3414 mutex_lock(&wl->mutex);
3415
3416 B43legacy_WARN_ON(!wl->operating);
3417 B43legacy_WARN_ON(wl->vif != conf->vif);
3418 wl->vif = NULL;
3419
3420 wl->operating = 0;
3421
3422 spin_lock_irqsave(&wl->irq_lock, flags);
3423 b43legacy_adjust_opmode(dev);
3424 memset(wl->mac_addr, 0, ETH_ALEN);
3425 b43legacy_upload_card_macaddress(dev);
3426 spin_unlock_irqrestore(&wl->irq_lock, flags);
3427
3428 mutex_unlock(&wl->mutex);
3429 }
3430
3431 static int b43legacy_op_start(struct ieee80211_hw *hw)
3432 {
3433 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3434 struct b43legacy_wldev *dev = wl->current_dev;
3435 int did_init = 0;
3436 int err = 0;
3437
3438 /* Kill all old instance specific information to make sure
3439 * the card won't use it in the short timeframe between start
3440 * and mac80211 reconfiguring it. */
3441 memset(wl->bssid, 0, ETH_ALEN);
3442 memset(wl->mac_addr, 0, ETH_ALEN);
3443 wl->filter_flags = 0;
3444 wl->beacon0_uploaded = 0;
3445 wl->beacon1_uploaded = 0;
3446 wl->beacon_templates_virgin = 1;
3447 wl->radio_enabled = 1;
3448
3449 mutex_lock(&wl->mutex);
3450
3451 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
3452 err = b43legacy_wireless_core_init(dev);
3453 if (err)
3454 goto out_mutex_unlock;
3455 did_init = 1;
3456 }
3457
3458 if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
3459 err = b43legacy_wireless_core_start(dev);
3460 if (err) {
3461 if (did_init)
3462 b43legacy_wireless_core_exit(dev);
3463 goto out_mutex_unlock;
3464 }
3465 }
3466
3467 wiphy_rfkill_start_polling(hw->wiphy);
3468
3469 out_mutex_unlock:
3470 mutex_unlock(&wl->mutex);
3471
3472 return err;
3473 }
3474
3475 static void b43legacy_op_stop(struct ieee80211_hw *hw)
3476 {
3477 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3478 struct b43legacy_wldev *dev = wl->current_dev;
3479
3480 cancel_work_sync(&(wl->beacon_update_trigger));
3481
3482 mutex_lock(&wl->mutex);
3483 if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
3484 b43legacy_wireless_core_stop(dev);
3485 b43legacy_wireless_core_exit(dev);
3486 wl->radio_enabled = 0;
3487 mutex_unlock(&wl->mutex);
3488 }
3489
3490 static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw,
3491 struct ieee80211_sta *sta, bool set)
3492 {
3493 struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3494 unsigned long flags;
3495
3496 spin_lock_irqsave(&wl->irq_lock, flags);
3497 b43legacy_update_templates(wl);
3498 spin_unlock_irqrestore(&wl->irq_lock, flags);
3499
3500 return 0;
3501 }
3502
3503 static const struct ieee80211_ops b43legacy_hw_ops = {
3504 .tx = b43legacy_op_tx,
3505 .conf_tx = b43legacy_op_conf_tx,
3506 .add_interface = b43legacy_op_add_interface,
3507 .remove_interface = b43legacy_op_remove_interface,
3508 .config = b43legacy_op_dev_config,
3509 .bss_info_changed = b43legacy_op_bss_info_changed,
3510 .configure_filter = b43legacy_op_configure_filter,
3511 .get_stats = b43legacy_op_get_stats,
3512 .get_tx_stats = b43legacy_op_get_tx_stats,
3513 .start = b43legacy_op_start,
3514 .stop = b43legacy_op_stop,
3515 .set_tim = b43legacy_op_beacon_set_tim,
3516 .rfkill_poll = b43legacy_rfkill_poll,
3517 };
3518
3519 /* Hard-reset the chip. Do not call this directly.
3520 * Use b43legacy_controller_restart()
3521 */
3522 static void b43legacy_chip_reset(struct work_struct *work)
3523 {
3524 struct b43legacy_wldev *dev =
3525 container_of(work, struct b43legacy_wldev, restart_work);
3526 struct b43legacy_wl *wl = dev->wl;
3527 int err = 0;
3528 int prev_status;
3529
3530 mutex_lock(&wl->mutex);
3531
3532 prev_status = b43legacy_status(dev);
3533 /* Bring the device down... */
3534 if (prev_status >= B43legacy_STAT_STARTED)
3535 b43legacy_wireless_core_stop(dev);
3536 if (prev_status >= B43legacy_STAT_INITIALIZED)
3537 b43legacy_wireless_core_exit(dev);
3538
3539 /* ...and up again. */
3540 if (prev_status >= B43legacy_STAT_INITIALIZED) {
3541 err = b43legacy_wireless_core_init(dev);
3542 if (err)
3543 goto out;
3544 }
3545 if (prev_status >= B43legacy_STAT_STARTED) {
3546 err = b43legacy_wireless_core_start(dev);
3547 if (err) {
3548 b43legacy_wireless_core_exit(dev);
3549 goto out;
3550 }
3551 }
3552 out:
3553 if (err)
3554 wl->current_dev = NULL; /* Failed to init the dev. */
3555 mutex_unlock(&wl->mutex);
3556 if (err)
3557 b43legacyerr(wl, "Controller restart FAILED\n");
3558 else
3559 b43legacyinfo(wl, "Controller restarted\n");
3560 }
3561
3562 static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
3563 int have_bphy,
3564 int have_gphy)
3565 {
3566 struct ieee80211_hw *hw = dev->wl->hw;
3567 struct b43legacy_phy *phy = &dev->phy;
3568
3569 phy->possible_phymodes = 0;
3570 if (have_bphy) {
3571 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3572 &b43legacy_band_2GHz_BPHY;
3573 phy->possible_phymodes |= B43legacy_PHYMODE_B;
3574 }
3575
3576 if (have_gphy) {
3577 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3578 &b43legacy_band_2GHz_GPHY;
3579 phy->possible_phymodes |= B43legacy_PHYMODE_G;
3580 }
3581
3582 return 0;
3583 }
3584
3585 static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
3586 {
3587 /* We release firmware that late to not be required to re-request
3588 * is all the time when we reinit the core. */
3589 b43legacy_release_firmware(dev);
3590 }
3591
3592 static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
3593 {
3594 struct b43legacy_wl *wl = dev->wl;
3595 struct ssb_bus *bus = dev->dev->bus;
3596 struct pci_dev *pdev = bus->host_pci;
3597 int err;
3598 int have_bphy = 0;
3599 int have_gphy = 0;
3600 u32 tmp;
3601
3602 /* Do NOT do any device initialization here.
3603 * Do it in wireless_core_init() instead.
3604 * This function is for gathering basic information about the HW, only.
3605 * Also some structs may be set up here. But most likely you want to
3606 * have that in core_init(), too.
3607 */
3608
3609 err = ssb_bus_powerup(bus, 0);
3610 if (err) {
3611 b43legacyerr(wl, "Bus powerup failed\n");
3612 goto out;
3613 }
3614 /* Get the PHY type. */
3615 if (dev->dev->id.revision >= 5) {
3616 u32 tmshigh;
3617
3618 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3619 have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
3620 if (!have_gphy)
3621 have_bphy = 1;
3622 } else if (dev->dev->id.revision == 4)
3623 have_gphy = 1;
3624 else
3625 have_bphy = 1;
3626
3627 dev->phy.gmode = (have_gphy || have_bphy);
3628 dev->phy.radio_on = 1;
3629 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3630 b43legacy_wireless_core_reset(dev, tmp);
3631
3632 err = b43legacy_phy_versioning(dev);
3633 if (err)
3634 goto err_powerdown;
3635 /* Check if this device supports multiband. */
3636 if (!pdev ||
3637 (pdev->device != 0x4312 &&
3638 pdev->device != 0x4319 &&
3639 pdev->device != 0x4324)) {
3640 /* No multiband support. */
3641 have_bphy = 0;
3642 have_gphy = 0;
3643 switch (dev->phy.type) {
3644 case B43legacy_PHYTYPE_B:
3645 have_bphy = 1;
3646 break;
3647 case B43legacy_PHYTYPE_G:
3648 have_gphy = 1;
3649 break;
3650 default:
3651 B43legacy_BUG_ON(1);
3652 }
3653 }
3654 dev->phy.gmode = (have_gphy || have_bphy);
3655 tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3656 b43legacy_wireless_core_reset(dev, tmp);
3657
3658 err = b43legacy_validate_chipaccess(dev);
3659 if (err)
3660 goto err_powerdown;
3661 err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
3662 if (err)
3663 goto err_powerdown;
3664
3665 /* Now set some default "current_dev" */
3666 if (!wl->current_dev)
3667 wl->current_dev = dev;
3668 INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
3669
3670 b43legacy_radio_turn_off(dev, 1);
3671 b43legacy_switch_analog(dev, 0);
3672 ssb_device_disable(dev->dev, 0);
3673 ssb_bus_may_powerdown(bus);
3674
3675 out:
3676 return err;
3677
3678 err_powerdown:
3679 ssb_bus_may_powerdown(bus);
3680 return err;
3681 }
3682
3683 static void b43legacy_one_core_detach(struct ssb_device *dev)
3684 {
3685 struct b43legacy_wldev *wldev;
3686 struct b43legacy_wl *wl;
3687
3688 /* Do not cancel ieee80211-workqueue based work here.
3689 * See comment in b43legacy_remove(). */
3690
3691 wldev = ssb_get_drvdata(dev);
3692 wl = wldev->wl;
3693 b43legacy_debugfs_remove_device(wldev);
3694 b43legacy_wireless_core_detach(wldev);
3695 list_del(&wldev->list);
3696 wl->nr_devs--;
3697 ssb_set_drvdata(dev, NULL);
3698 kfree(wldev);
3699 }
3700
3701 static int b43legacy_one_core_attach(struct ssb_device *dev,
3702 struct b43legacy_wl *wl)
3703 {
3704 struct b43legacy_wldev *wldev;
3705 struct pci_dev *pdev;
3706 int err = -ENOMEM;
3707
3708 if (!list_empty(&wl->devlist)) {
3709 /* We are not the first core on this chip. */
3710 pdev = dev->bus->host_pci;
3711 /* Only special chips support more than one wireless
3712 * core, although some of the other chips have more than
3713 * one wireless core as well. Check for this and
3714 * bail out early.
3715 */
3716 if (!pdev ||
3717 ((pdev->device != 0x4321) &&
3718 (pdev->device != 0x4313) &&
3719 (pdev->device != 0x431A))) {
3720 b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
3721 return -ENODEV;
3722 }
3723 }
3724
3725 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3726 if (!wldev)
3727 goto out;
3728
3729 wldev->dev = dev;
3730 wldev->wl = wl;
3731 b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
3732 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3733 tasklet_init(&wldev->isr_tasklet,
3734 (void (*)(unsigned long))b43legacy_interrupt_tasklet,
3735 (unsigned long)wldev);
3736 if (modparam_pio)
3737 wldev->__using_pio = 1;
3738 INIT_LIST_HEAD(&wldev->list);
3739
3740 err = b43legacy_wireless_core_attach(wldev);
3741 if (err)
3742 goto err_kfree_wldev;
3743
3744 list_add(&wldev->list, &wl->devlist);
3745 wl->nr_devs++;
3746 ssb_set_drvdata(dev, wldev);
3747 b43legacy_debugfs_add_device(wldev);
3748 out:
3749 return err;
3750
3751 err_kfree_wldev:
3752 kfree(wldev);
3753 return err;
3754 }
3755
3756 static void b43legacy_sprom_fixup(struct ssb_bus *bus)
3757 {
3758 /* boardflags workarounds */
3759 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3760 bus->boardinfo.type == 0x4E &&
3761 bus->boardinfo.rev > 0x40)
3762 bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
3763 }
3764
3765 static void b43legacy_wireless_exit(struct ssb_device *dev,
3766 struct b43legacy_wl *wl)
3767 {
3768 struct ieee80211_hw *hw = wl->hw;
3769
3770 ssb_set_devtypedata(dev, NULL);
3771 ieee80211_free_hw(hw);
3772 }
3773
3774 static int b43legacy_wireless_init(struct ssb_device *dev)
3775 {
3776 struct ssb_sprom *sprom = &dev->bus->sprom;
3777 struct ieee80211_hw *hw;
3778 struct b43legacy_wl *wl;
3779 int err = -ENOMEM;
3780
3781 b43legacy_sprom_fixup(dev->bus);
3782
3783 hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
3784 if (!hw) {
3785 b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
3786 goto out;
3787 }
3788
3789 /* fill hw info */
3790 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3791 IEEE80211_HW_SIGNAL_DBM |
3792 IEEE80211_HW_NOISE_DBM;
3793 hw->wiphy->interface_modes =
3794 BIT(NL80211_IFTYPE_AP) |
3795 BIT(NL80211_IFTYPE_STATION) |
3796 BIT(NL80211_IFTYPE_WDS) |
3797 BIT(NL80211_IFTYPE_ADHOC);
3798 hw->queues = 1; /* FIXME: hardware has more queues */
3799 hw->max_rates = 2;
3800 SET_IEEE80211_DEV(hw, dev->dev);
3801 if (is_valid_ether_addr(sprom->et1mac))
3802 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3803 else
3804 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3805
3806 /* Get and initialize struct b43legacy_wl */
3807 wl = hw_to_b43legacy_wl(hw);
3808 memset(wl, 0, sizeof(*wl));
3809 wl->hw = hw;
3810 spin_lock_init(&wl->irq_lock);
3811 spin_lock_init(&wl->leds_lock);
3812 mutex_init(&wl->mutex);
3813 INIT_LIST_HEAD(&wl->devlist);
3814 INIT_WORK(&wl->beacon_update_trigger, b43legacy_beacon_update_trigger_work);
3815
3816 ssb_set_devtypedata(dev, wl);
3817 b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3818 err = 0;
3819 out:
3820 return err;
3821 }
3822
3823 static int b43legacy_probe(struct ssb_device *dev,
3824 const struct ssb_device_id *id)
3825 {
3826 struct b43legacy_wl *wl;
3827 int err;
3828 int first = 0;
3829
3830 wl = ssb_get_devtypedata(dev);
3831 if (!wl) {
3832 /* Probing the first core - setup common struct b43legacy_wl */
3833 first = 1;
3834 err = b43legacy_wireless_init(dev);
3835 if (err)
3836 goto out;
3837 wl = ssb_get_devtypedata(dev);
3838 B43legacy_WARN_ON(!wl);
3839 }
3840 err = b43legacy_one_core_attach(dev, wl);
3841 if (err)
3842 goto err_wireless_exit;
3843
3844 if (first) {
3845 err = ieee80211_register_hw(wl->hw);
3846 if (err)
3847 goto err_one_core_detach;
3848 }
3849
3850 out:
3851 return err;
3852
3853 err_one_core_detach:
3854 b43legacy_one_core_detach(dev);
3855 err_wireless_exit:
3856 if (first)
3857 b43legacy_wireless_exit(dev, wl);
3858 return err;
3859 }
3860
3861 static void b43legacy_remove(struct ssb_device *dev)
3862 {
3863 struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
3864 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3865
3866 /* We must cancel any work here before unregistering from ieee80211,
3867 * as the ieee80211 unreg will destroy the workqueue. */
3868 cancel_work_sync(&wldev->restart_work);
3869
3870 B43legacy_WARN_ON(!wl);
3871 if (wl->current_dev == wldev)
3872 ieee80211_unregister_hw(wl->hw);
3873
3874 b43legacy_one_core_detach(dev);
3875
3876 if (list_empty(&wl->devlist))
3877 /* Last core on the chip unregistered.
3878 * We can destroy common struct b43legacy_wl.
3879 */
3880 b43legacy_wireless_exit(dev, wl);
3881 }
3882
3883 /* Perform a hardware reset. This can be called from any context. */
3884 void b43legacy_controller_restart(struct b43legacy_wldev *dev,
3885 const char *reason)
3886 {
3887 /* Must avoid requeueing, if we are in shutdown. */
3888 if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
3889 return;
3890 b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
3891 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
3892 }
3893
3894 #ifdef CONFIG_PM
3895
3896 static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
3897 {
3898 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3899 struct b43legacy_wl *wl = wldev->wl;
3900
3901 b43legacydbg(wl, "Suspending...\n");
3902
3903 mutex_lock(&wl->mutex);
3904 wldev->suspend_init_status = b43legacy_status(wldev);
3905 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
3906 b43legacy_wireless_core_stop(wldev);
3907 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
3908 b43legacy_wireless_core_exit(wldev);
3909 mutex_unlock(&wl->mutex);
3910
3911 b43legacydbg(wl, "Device suspended.\n");
3912
3913 return 0;
3914 }
3915
3916 static int b43legacy_resume(struct ssb_device *dev)
3917 {
3918 struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3919 struct b43legacy_wl *wl = wldev->wl;
3920 int err = 0;
3921
3922 b43legacydbg(wl, "Resuming...\n");
3923
3924 mutex_lock(&wl->mutex);
3925 if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
3926 err = b43legacy_wireless_core_init(wldev);
3927 if (err) {
3928 b43legacyerr(wl, "Resume failed at core init\n");
3929 goto out;
3930 }
3931 }
3932 if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
3933 err = b43legacy_wireless_core_start(wldev);
3934 if (err) {
3935 b43legacy_wireless_core_exit(wldev);
3936 b43legacyerr(wl, "Resume failed at core start\n");
3937 goto out;
3938 }
3939 }
3940
3941 b43legacydbg(wl, "Device resumed.\n");
3942 out:
3943 mutex_unlock(&wl->mutex);
3944 return err;
3945 }
3946
3947 #else /* CONFIG_PM */
3948 # define b43legacy_suspend NULL
3949 # define b43legacy_resume NULL
3950 #endif /* CONFIG_PM */
3951
3952 static struct ssb_driver b43legacy_ssb_driver = {
3953 .name = KBUILD_MODNAME,
3954 .id_table = b43legacy_ssb_tbl,
3955 .probe = b43legacy_probe,
3956 .remove = b43legacy_remove,
3957 .suspend = b43legacy_suspend,
3958 .resume = b43legacy_resume,
3959 };
3960
3961 static void b43legacy_print_driverinfo(void)
3962 {
3963 const char *feat_pci = "", *feat_leds = "", *feat_rfkill = "",
3964 *feat_pio = "", *feat_dma = "";
3965
3966 #ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
3967 feat_pci = "P";
3968 #endif
3969 #ifdef CONFIG_B43LEGACY_LEDS
3970 feat_leds = "L";
3971 #endif
3972 #ifdef CONFIG_B43LEGACY_RFKILL
3973 feat_rfkill = "R";
3974 #endif
3975 #ifdef CONFIG_B43LEGACY_PIO
3976 feat_pio = "I";
3977 #endif
3978 #ifdef CONFIG_B43LEGACY_DMA
3979 feat_dma = "D";
3980 #endif
3981 printk(KERN_INFO "Broadcom 43xx-legacy driver loaded "
3982 "[ Features: %s%s%s%s%s, Firmware-ID: "
3983 B43legacy_SUPPORTED_FIRMWARE_ID " ]\n",
3984 feat_pci, feat_leds, feat_rfkill, feat_pio, feat_dma);
3985 }
3986
3987 static int __init b43legacy_init(void)
3988 {
3989 int err;
3990
3991 b43legacy_debugfs_init();
3992
3993 err = ssb_driver_register(&b43legacy_ssb_driver);
3994 if (err)
3995 goto err_dfs_exit;
3996
3997 b43legacy_print_driverinfo();
3998
3999 return err;
4000
4001 err_dfs_exit:
4002 b43legacy_debugfs_exit();
4003 return err;
4004 }
4005
4006 static void __exit b43legacy_exit(void)
4007 {
4008 ssb_driver_unregister(&b43legacy_ssb_driver);
4009 b43legacy_debugfs_exit();
4010 }
4011
4012 module_init(b43legacy_init)
4013 module_exit(b43legacy_exit)
Ubuntu Artful kernel mirror