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Merge branch 'upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/vitb/linux...
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / bcm43xx / bcm43xx_main.c
1 /*
2
3 Broadcom BCM43xx wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <net/iw_handler.h>
43
44 #include "bcm43xx.h"
45 #include "bcm43xx_main.h"
46 #include "bcm43xx_debugfs.h"
47 #include "bcm43xx_radio.h"
48 #include "bcm43xx_phy.h"
49 #include "bcm43xx_dma.h"
50 #include "bcm43xx_pio.h"
51 #include "bcm43xx_power.h"
52 #include "bcm43xx_wx.h"
53 #include "bcm43xx_ethtool.h"
54 #include "bcm43xx_xmit.h"
55 #include "bcm43xx_sysfs.h"
56
57
58 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
59 MODULE_AUTHOR("Martin Langer");
60 MODULE_AUTHOR("Stefano Brivio");
61 MODULE_AUTHOR("Michael Buesch");
62 MODULE_LICENSE("GPL");
63
64 #ifdef CONFIG_BCM947XX
65 extern char *nvram_get(char *name);
66 #endif
67
68 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
69 static int modparam_pio;
70 module_param_named(pio, modparam_pio, int, 0444);
71 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
72 #elif defined(CONFIG_BCM43XX_DMA)
73 # define modparam_pio 0
74 #elif defined(CONFIG_BCM43XX_PIO)
75 # define modparam_pio 1
76 #endif
77
78 static int modparam_bad_frames_preempt;
79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
81
82 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
83 module_param_named(short_retry, modparam_short_retry, int, 0444);
84 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
85
86 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
87 module_param_named(long_retry, modparam_long_retry, int, 0444);
88 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
89
90 static int modparam_locale = -1;
91 module_param_named(locale, modparam_locale, int, 0444);
92 MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
93
94 static int modparam_noleds;
95 module_param_named(noleds, modparam_noleds, int, 0444);
96 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
97
98 #ifdef CONFIG_BCM43XX_DEBUG
99 static char modparam_fwpostfix[64];
100 module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
101 MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
102 #else
103 # define modparam_fwpostfix ""
104 #endif /* CONFIG_BCM43XX_DEBUG*/
105
106
107 /* If you want to debug with just a single device, enable this,
108 * where the string is the pci device ID (as given by the kernel's
109 * pci_name function) of the device to be used.
110 */
111 //#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
112
113 /* If you want to enable printing of each MMIO access, enable this. */
114 //#define DEBUG_ENABLE_MMIO_PRINT
115
116 /* If you want to enable printing of MMIO access within
117 * ucode/pcm upload, initvals write, enable this.
118 */
119 //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
120
121 /* If you want to enable printing of PCI Config Space access, enable this */
122 //#define DEBUG_ENABLE_PCILOG
123
124
125 /* Detailed list maintained at:
126 * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
127 */
128 static struct pci_device_id bcm43xx_pci_tbl[] = {
129 /* Broadcom 4303 802.11b */
130 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 /* Broadcom 4307 802.11b */
132 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 /* Broadcom 4318 802.11b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4319 802.11a/b/g */
136 { PCI_VENDOR_ID_BROADCOM, 0x4319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 /* Broadcom 4306 802.11b/g */
138 { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 /* Broadcom 4306 802.11a */
140 // { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 /* Broadcom 4309 802.11a/b/g */
142 { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 /* Broadcom 43XG 802.11b/g */
144 { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 #ifdef CONFIG_BCM947XX
146 /* SB bus on BCM947xx */
147 { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
148 #endif
149 { 0 },
150 };
151 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
152
153 static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
154 {
155 u32 status;
156
157 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
158 if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
159 val = swab32(val);
160
161 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
162 mmiowb();
163 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
164 }
165
166 static inline
167 void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
168 u16 routing, u16 offset)
169 {
170 u32 control;
171
172 /* "offset" is the WORD offset. */
173
174 control = routing;
175 control <<= 16;
176 control |= offset;
177 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
178 }
179
180 u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
181 u16 routing, u16 offset)
182 {
183 u32 ret;
184
185 if (routing == BCM43xx_SHM_SHARED) {
186 if (offset & 0x0003) {
187 /* Unaligned access */
188 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
189 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
190 ret <<= 16;
191 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
192 ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
193
194 return ret;
195 }
196 offset >>= 2;
197 }
198 bcm43xx_shm_control_word(bcm, routing, offset);
199 ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
200
201 return ret;
202 }
203
204 u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
205 u16 routing, u16 offset)
206 {
207 u16 ret;
208
209 if (routing == BCM43xx_SHM_SHARED) {
210 if (offset & 0x0003) {
211 /* Unaligned access */
212 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
213 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
214
215 return ret;
216 }
217 offset >>= 2;
218 }
219 bcm43xx_shm_control_word(bcm, routing, offset);
220 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
221
222 return ret;
223 }
224
225 void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
226 u16 routing, u16 offset,
227 u32 value)
228 {
229 if (routing == BCM43xx_SHM_SHARED) {
230 if (offset & 0x0003) {
231 /* Unaligned access */
232 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
233 mmiowb();
234 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
235 (value >> 16) & 0xffff);
236 mmiowb();
237 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
238 mmiowb();
239 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
240 value & 0xffff);
241 return;
242 }
243 offset >>= 2;
244 }
245 bcm43xx_shm_control_word(bcm, routing, offset);
246 mmiowb();
247 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
248 }
249
250 void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
251 u16 routing, u16 offset,
252 u16 value)
253 {
254 if (routing == BCM43xx_SHM_SHARED) {
255 if (offset & 0x0003) {
256 /* Unaligned access */
257 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
258 mmiowb();
259 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
260 value);
261 return;
262 }
263 offset >>= 2;
264 }
265 bcm43xx_shm_control_word(bcm, routing, offset);
266 mmiowb();
267 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
268 }
269
270 void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
271 {
272 /* We need to be careful. As we read the TSF from multiple
273 * registers, we should take care of register overflows.
274 * In theory, the whole tsf read process should be atomic.
275 * We try to be atomic here, by restaring the read process,
276 * if any of the high registers changed (overflew).
277 */
278 if (bcm->current_core->rev >= 3) {
279 u32 low, high, high2;
280
281 do {
282 high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
283 low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
284 high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
285 } while (unlikely(high != high2));
286
287 *tsf = high;
288 *tsf <<= 32;
289 *tsf |= low;
290 } else {
291 u64 tmp;
292 u16 v0, v1, v2, v3;
293 u16 test1, test2, test3;
294
295 do {
296 v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
297 v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
298 v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
299 v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
300
301 test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
302 test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
303 test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
304 } while (v3 != test3 || v2 != test2 || v1 != test1);
305
306 *tsf = v3;
307 *tsf <<= 48;
308 tmp = v2;
309 tmp <<= 32;
310 *tsf |= tmp;
311 tmp = v1;
312 tmp <<= 16;
313 *tsf |= tmp;
314 *tsf |= v0;
315 }
316 }
317
318 void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
319 {
320 u32 status;
321
322 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
323 status |= BCM43xx_SBF_TIME_UPDATE;
324 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
325 mmiowb();
326
327 /* Be careful with the in-progress timer.
328 * First zero out the low register, so we have a full
329 * register-overflow duration to complete the operation.
330 */
331 if (bcm->current_core->rev >= 3) {
332 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
333 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
334
335 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
336 mmiowb();
337 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
338 mmiowb();
339 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
340 } else {
341 u16 v0 = (tsf & 0x000000000000FFFFULL);
342 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
343 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
344 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
345
346 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
347 mmiowb();
348 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
349 mmiowb();
350 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
351 mmiowb();
352 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
353 mmiowb();
354 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
355 }
356
357 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
358 status &= ~BCM43xx_SBF_TIME_UPDATE;
359 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
360 }
361
362 static
363 void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
364 u16 offset,
365 const u8 *mac)
366 {
367 u16 data;
368
369 offset |= 0x0020;
370 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
371
372 data = mac[0];
373 data |= mac[1] << 8;
374 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
375 data = mac[2];
376 data |= mac[3] << 8;
377 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
378 data = mac[4];
379 data |= mac[5] << 8;
380 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
381 }
382
383 static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
384 u16 offset)
385 {
386 const u8 zero_addr[ETH_ALEN] = { 0 };
387
388 bcm43xx_macfilter_set(bcm, offset, zero_addr);
389 }
390
391 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
392 {
393 const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
394 const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
395 u8 mac_bssid[ETH_ALEN * 2];
396 int i;
397
398 memcpy(mac_bssid, mac, ETH_ALEN);
399 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
400
401 /* Write our MAC address and BSSID to template ram */
402 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
403 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
404 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
405 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
406 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
407 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
408 }
409
410 //FIXME: Well, we should probably call them from somewhere.
411 #if 0
412 static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
413 {
414 /* slot_time is in usec. */
415 if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
416 return;
417 bcm43xx_write16(bcm, 0x684, 510 + slot_time);
418 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
419 }
420
421 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
422 {
423 bcm43xx_set_slot_time(bcm, 9);
424 }
425
426 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
427 {
428 bcm43xx_set_slot_time(bcm, 20);
429 }
430 #endif
431
432 /* FIXME: To get the MAC-filter working, we need to implement the
433 * following functions (and rename them :)
434 */
435 #if 0
436 static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
437 {
438 bcm43xx_mac_suspend(bcm);
439 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
440
441 bcm43xx_ram_write(bcm, 0x0026, 0x0000);
442 bcm43xx_ram_write(bcm, 0x0028, 0x0000);
443 bcm43xx_ram_write(bcm, 0x007E, 0x0000);
444 bcm43xx_ram_write(bcm, 0x0080, 0x0000);
445 bcm43xx_ram_write(bcm, 0x047E, 0x0000);
446 bcm43xx_ram_write(bcm, 0x0480, 0x0000);
447
448 if (bcm->current_core->rev < 3) {
449 bcm43xx_write16(bcm, 0x0610, 0x8000);
450 bcm43xx_write16(bcm, 0x060E, 0x0000);
451 } else
452 bcm43xx_write32(bcm, 0x0188, 0x80000000);
453
454 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
455
456 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
457 ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
458 bcm43xx_short_slot_timing_enable(bcm);
459
460 bcm43xx_mac_enable(bcm);
461 }
462
463 static void bcm43xx_associate(struct bcm43xx_private *bcm,
464 const u8 *mac)
465 {
466 memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
467
468 bcm43xx_mac_suspend(bcm);
469 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
470 bcm43xx_write_mac_bssid_templates(bcm);
471 bcm43xx_mac_enable(bcm);
472 }
473 #endif
474
475 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
476 * Returns the _previously_ enabled IRQ mask.
477 */
478 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
479 {
480 u32 old_mask;
481
482 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
483 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
484
485 return old_mask;
486 }
487
488 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
489 * Returns the _previously_ enabled IRQ mask.
490 */
491 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
492 {
493 u32 old_mask;
494
495 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
496 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
497
498 return old_mask;
499 }
500
501 /* Synchronize IRQ top- and bottom-half.
502 * IRQs must be masked before calling this.
503 * This must not be called with the irq_lock held.
504 */
505 static void bcm43xx_synchronize_irq(struct bcm43xx_private *bcm)
506 {
507 synchronize_irq(bcm->irq);
508 tasklet_disable(&bcm->isr_tasklet);
509 }
510
511 /* Make sure we don't receive more data from the device. */
512 static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm)
513 {
514 unsigned long flags;
515
516 spin_lock_irqsave(&bcm->irq_lock, flags);
517 if (unlikely(bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)) {
518 spin_unlock_irqrestore(&bcm->irq_lock, flags);
519 return -EBUSY;
520 }
521 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
522 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK); /* flush */
523 spin_unlock_irqrestore(&bcm->irq_lock, flags);
524 bcm43xx_synchronize_irq(bcm);
525
526 return 0;
527 }
528
529 static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
530 {
531 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
532 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
533 u32 radio_id;
534 u16 manufact;
535 u16 version;
536 u8 revision;
537
538 if (bcm->chip_id == 0x4317) {
539 if (bcm->chip_rev == 0x00)
540 radio_id = 0x3205017F;
541 else if (bcm->chip_rev == 0x01)
542 radio_id = 0x4205017F;
543 else
544 radio_id = 0x5205017F;
545 } else {
546 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
547 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
548 radio_id <<= 16;
549 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
550 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
551 }
552
553 manufact = (radio_id & 0x00000FFF);
554 version = (radio_id & 0x0FFFF000) >> 12;
555 revision = (radio_id & 0xF0000000) >> 28;
556
557 dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
558 radio_id, manufact, version, revision);
559
560 switch (phy->type) {
561 case BCM43xx_PHYTYPE_A:
562 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
563 goto err_unsupported_radio;
564 break;
565 case BCM43xx_PHYTYPE_B:
566 if ((version & 0xFFF0) != 0x2050)
567 goto err_unsupported_radio;
568 break;
569 case BCM43xx_PHYTYPE_G:
570 if (version != 0x2050)
571 goto err_unsupported_radio;
572 break;
573 }
574
575 radio->manufact = manufact;
576 radio->version = version;
577 radio->revision = revision;
578
579 if (phy->type == BCM43xx_PHYTYPE_A)
580 radio->txpower_desired = bcm->sprom.maxpower_aphy;
581 else
582 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
583
584 return 0;
585
586 err_unsupported_radio:
587 printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
588 return -ENODEV;
589 }
590
591 static const char * bcm43xx_locale_iso(u8 locale)
592 {
593 /* ISO 3166-1 country codes.
594 * Note that there aren't ISO 3166-1 codes for
595 * all or locales. (Not all locales are countries)
596 */
597 switch (locale) {
598 case BCM43xx_LOCALE_WORLD:
599 case BCM43xx_LOCALE_ALL:
600 return "XX";
601 case BCM43xx_LOCALE_THAILAND:
602 return "TH";
603 case BCM43xx_LOCALE_ISRAEL:
604 return "IL";
605 case BCM43xx_LOCALE_JORDAN:
606 return "JO";
607 case BCM43xx_LOCALE_CHINA:
608 return "CN";
609 case BCM43xx_LOCALE_JAPAN:
610 case BCM43xx_LOCALE_JAPAN_HIGH:
611 return "JP";
612 case BCM43xx_LOCALE_USA_CANADA_ANZ:
613 case BCM43xx_LOCALE_USA_LOW:
614 return "US";
615 case BCM43xx_LOCALE_EUROPE:
616 return "EU";
617 case BCM43xx_LOCALE_NONE:
618 return " ";
619 }
620 assert(0);
621 return " ";
622 }
623
624 static const char * bcm43xx_locale_string(u8 locale)
625 {
626 switch (locale) {
627 case BCM43xx_LOCALE_WORLD:
628 return "World";
629 case BCM43xx_LOCALE_THAILAND:
630 return "Thailand";
631 case BCM43xx_LOCALE_ISRAEL:
632 return "Israel";
633 case BCM43xx_LOCALE_JORDAN:
634 return "Jordan";
635 case BCM43xx_LOCALE_CHINA:
636 return "China";
637 case BCM43xx_LOCALE_JAPAN:
638 return "Japan";
639 case BCM43xx_LOCALE_USA_CANADA_ANZ:
640 return "USA/Canada/ANZ";
641 case BCM43xx_LOCALE_EUROPE:
642 return "Europe";
643 case BCM43xx_LOCALE_USA_LOW:
644 return "USAlow";
645 case BCM43xx_LOCALE_JAPAN_HIGH:
646 return "JapanHigh";
647 case BCM43xx_LOCALE_ALL:
648 return "All";
649 case BCM43xx_LOCALE_NONE:
650 return "None";
651 }
652 assert(0);
653 return "";
654 }
655
656 static inline u8 bcm43xx_crc8(u8 crc, u8 data)
657 {
658 static const u8 t[] = {
659 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
660 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
661 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
662 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
663 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
664 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
665 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
666 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
667 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
668 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
669 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
670 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
671 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
672 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
673 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
674 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
675 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
676 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
677 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
678 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
679 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
680 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
681 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
682 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
683 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
684 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
685 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
686 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
687 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
688 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
689 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
690 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
691 };
692 return t[crc ^ data];
693 }
694
695 static u8 bcm43xx_sprom_crc(const u16 *sprom)
696 {
697 int word;
698 u8 crc = 0xFF;
699
700 for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
701 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
702 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
703 }
704 crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
705 crc ^= 0xFF;
706
707 return crc;
708 }
709
710 int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
711 {
712 int i;
713 u8 crc, expected_crc;
714
715 for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
716 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
717 /* CRC-8 check. */
718 crc = bcm43xx_sprom_crc(sprom);
719 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
720 if (crc != expected_crc) {
721 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
722 "(0x%02X, expected: 0x%02X)\n",
723 crc, expected_crc);
724 return -EINVAL;
725 }
726
727 return 0;
728 }
729
730 int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
731 {
732 int i, err;
733 u8 crc, expected_crc;
734 u32 spromctl;
735
736 /* CRC-8 validation of the input data. */
737 crc = bcm43xx_sprom_crc(sprom);
738 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
739 if (crc != expected_crc) {
740 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
741 return -EINVAL;
742 }
743
744 printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
745 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
746 if (err)
747 goto err_ctlreg;
748 spromctl |= 0x10; /* SPROM WRITE enable. */
749 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
750 if (err)
751 goto err_ctlreg;
752 /* We must burn lots of CPU cycles here, but that does not
753 * really matter as one does not write the SPROM every other minute...
754 */
755 printk(KERN_INFO PFX "[ 0%%");
756 mdelay(500);
757 for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
758 if (i == 16)
759 printk("25%%");
760 else if (i == 32)
761 printk("50%%");
762 else if (i == 48)
763 printk("75%%");
764 else if (i % 2)
765 printk(".");
766 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
767 mmiowb();
768 mdelay(20);
769 }
770 spromctl &= ~0x10; /* SPROM WRITE enable. */
771 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
772 if (err)
773 goto err_ctlreg;
774 mdelay(500);
775 printk("100%% ]\n");
776 printk(KERN_INFO PFX "SPROM written.\n");
777 bcm43xx_controller_restart(bcm, "SPROM update");
778
779 return 0;
780 err_ctlreg:
781 printk(KERN_ERR PFX "Could not access SPROM control register.\n");
782 return -ENODEV;
783 }
784
785 static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
786 {
787 u16 value;
788 u16 *sprom;
789 #ifdef CONFIG_BCM947XX
790 char *c;
791 #endif
792
793 sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
794 GFP_KERNEL);
795 if (!sprom) {
796 printk(KERN_ERR PFX "sprom_extract OOM\n");
797 return -ENOMEM;
798 }
799 #ifdef CONFIG_BCM947XX
800 sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
801 sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
802
803 if ((c = nvram_get("il0macaddr")) != NULL)
804 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
805
806 if ((c = nvram_get("et1macaddr")) != NULL)
807 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
808
809 sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
810 sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
811 sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
812
813 sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
814 sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
815 sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
816
817 sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
818 #else
819 bcm43xx_sprom_read(bcm, sprom);
820 #endif
821
822 /* boardflags2 */
823 value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
824 bcm->sprom.boardflags2 = value;
825
826 /* il0macaddr */
827 value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
828 *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
829 value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
830 *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
831 value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
832 *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
833
834 /* et0macaddr */
835 value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
836 *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
837 value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
838 *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
839 value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
840 *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
841
842 /* et1macaddr */
843 value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
844 *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
845 value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
846 *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
847 value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
848 *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
849
850 /* ethernet phy settings */
851 value = sprom[BCM43xx_SPROM_ETHPHY];
852 bcm->sprom.et0phyaddr = (value & 0x001F);
853 bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
854 bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
855 bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
856
857 /* boardrev, antennas, locale */
858 value = sprom[BCM43xx_SPROM_BOARDREV];
859 bcm->sprom.boardrev = (value & 0x00FF);
860 bcm->sprom.locale = (value & 0x0F00) >> 8;
861 bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
862 bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
863 if (modparam_locale != -1) {
864 if (modparam_locale >= 0 && modparam_locale <= 11) {
865 bcm->sprom.locale = modparam_locale;
866 printk(KERN_WARNING PFX "Operating with modified "
867 "LocaleCode %u (%s)\n",
868 bcm->sprom.locale,
869 bcm43xx_locale_string(bcm->sprom.locale));
870 } else {
871 printk(KERN_WARNING PFX "Module parameter \"locale\" "
872 "invalid value. (0 - 11)\n");
873 }
874 }
875
876 /* pa0b* */
877 value = sprom[BCM43xx_SPROM_PA0B0];
878 bcm->sprom.pa0b0 = value;
879 value = sprom[BCM43xx_SPROM_PA0B1];
880 bcm->sprom.pa0b1 = value;
881 value = sprom[BCM43xx_SPROM_PA0B2];
882 bcm->sprom.pa0b2 = value;
883
884 /* wl0gpio* */
885 value = sprom[BCM43xx_SPROM_WL0GPIO0];
886 if (value == 0x0000)
887 value = 0xFFFF;
888 bcm->sprom.wl0gpio0 = value & 0x00FF;
889 bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
890 value = sprom[BCM43xx_SPROM_WL0GPIO2];
891 if (value == 0x0000)
892 value = 0xFFFF;
893 bcm->sprom.wl0gpio2 = value & 0x00FF;
894 bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
895
896 /* maxpower */
897 value = sprom[BCM43xx_SPROM_MAXPWR];
898 bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
899 bcm->sprom.maxpower_bgphy = value & 0x00FF;
900
901 /* pa1b* */
902 value = sprom[BCM43xx_SPROM_PA1B0];
903 bcm->sprom.pa1b0 = value;
904 value = sprom[BCM43xx_SPROM_PA1B1];
905 bcm->sprom.pa1b1 = value;
906 value = sprom[BCM43xx_SPROM_PA1B2];
907 bcm->sprom.pa1b2 = value;
908
909 /* idle tssi target */
910 value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
911 bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
912 bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
913
914 /* boardflags */
915 value = sprom[BCM43xx_SPROM_BOARDFLAGS];
916 if (value == 0xFFFF)
917 value = 0x0000;
918 bcm->sprom.boardflags = value;
919 /* boardflags workarounds */
920 if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
921 bcm->chip_id == 0x4301 &&
922 bcm->board_revision == 0x74)
923 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
924 if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
925 bcm->board_type == 0x4E &&
926 bcm->board_revision > 0x40)
927 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
928
929 /* antenna gain */
930 value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
931 if (value == 0x0000 || value == 0xFFFF)
932 value = 0x0202;
933 /* convert values to Q5.2 */
934 bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
935 bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
936
937 kfree(sprom);
938
939 return 0;
940 }
941
942 static int bcm43xx_geo_init(struct bcm43xx_private *bcm)
943 {
944 struct ieee80211_geo *geo;
945 struct ieee80211_channel *chan;
946 int have_a = 0, have_bg = 0;
947 int i;
948 u8 channel;
949 struct bcm43xx_phyinfo *phy;
950 const char *iso_country;
951
952 geo = kzalloc(sizeof(*geo), GFP_KERNEL);
953 if (!geo)
954 return -ENOMEM;
955
956 for (i = 0; i < bcm->nr_80211_available; i++) {
957 phy = &(bcm->core_80211_ext[i].phy);
958 switch (phy->type) {
959 case BCM43xx_PHYTYPE_B:
960 case BCM43xx_PHYTYPE_G:
961 have_bg = 1;
962 break;
963 case BCM43xx_PHYTYPE_A:
964 have_a = 1;
965 break;
966 default:
967 assert(0);
968 }
969 }
970 iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
971
972 if (have_a) {
973 for (i = 0, channel = IEEE80211_52GHZ_MIN_CHANNEL;
974 channel <= IEEE80211_52GHZ_MAX_CHANNEL; channel++) {
975 chan = &geo->a[i++];
976 chan->freq = bcm43xx_channel_to_freq_a(channel);
977 chan->channel = channel;
978 }
979 geo->a_channels = i;
980 }
981 if (have_bg) {
982 for (i = 0, channel = IEEE80211_24GHZ_MIN_CHANNEL;
983 channel <= IEEE80211_24GHZ_MAX_CHANNEL; channel++) {
984 chan = &geo->bg[i++];
985 chan->freq = bcm43xx_channel_to_freq_bg(channel);
986 chan->channel = channel;
987 }
988 geo->bg_channels = i;
989 }
990 memcpy(geo->name, iso_country, 2);
991 if (0 /*TODO: Outdoor use only */)
992 geo->name[2] = 'O';
993 else if (0 /*TODO: Indoor use only */)
994 geo->name[2] = 'I';
995 else
996 geo->name[2] = ' ';
997 geo->name[3] = '\0';
998
999 ieee80211_set_geo(bcm->ieee, geo);
1000 kfree(geo);
1001
1002 return 0;
1003 }
1004
1005 /* DummyTransmission function, as documented on
1006 * http://bcm-specs.sipsolutions.net/DummyTransmission
1007 */
1008 void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
1009 {
1010 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1011 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1012 unsigned int i, max_loop;
1013 u16 value = 0;
1014 u32 buffer[5] = {
1015 0x00000000,
1016 0x0000D400,
1017 0x00000000,
1018 0x00000001,
1019 0x00000000,
1020 };
1021
1022 switch (phy->type) {
1023 case BCM43xx_PHYTYPE_A:
1024 max_loop = 0x1E;
1025 buffer[0] = 0xCC010200;
1026 break;
1027 case BCM43xx_PHYTYPE_B:
1028 case BCM43xx_PHYTYPE_G:
1029 max_loop = 0xFA;
1030 buffer[0] = 0x6E840B00;
1031 break;
1032 default:
1033 assert(0);
1034 return;
1035 }
1036
1037 for (i = 0; i < 5; i++)
1038 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1039
1040 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1041
1042 bcm43xx_write16(bcm, 0x0568, 0x0000);
1043 bcm43xx_write16(bcm, 0x07C0, 0x0000);
1044 bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
1045 bcm43xx_write16(bcm, 0x0508, 0x0000);
1046 bcm43xx_write16(bcm, 0x050A, 0x0000);
1047 bcm43xx_write16(bcm, 0x054C, 0x0000);
1048 bcm43xx_write16(bcm, 0x056A, 0x0014);
1049 bcm43xx_write16(bcm, 0x0568, 0x0826);
1050 bcm43xx_write16(bcm, 0x0500, 0x0000);
1051 bcm43xx_write16(bcm, 0x0502, 0x0030);
1052
1053 if (radio->version == 0x2050 && radio->revision <= 0x5)
1054 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
1055 for (i = 0x00; i < max_loop; i++) {
1056 value = bcm43xx_read16(bcm, 0x050E);
1057 if (value & 0x0080)
1058 break;
1059 udelay(10);
1060 }
1061 for (i = 0x00; i < 0x0A; i++) {
1062 value = bcm43xx_read16(bcm, 0x050E);
1063 if (value & 0x0400)
1064 break;
1065 udelay(10);
1066 }
1067 for (i = 0x00; i < 0x0A; i++) {
1068 value = bcm43xx_read16(bcm, 0x0690);
1069 if (!(value & 0x0100))
1070 break;
1071 udelay(10);
1072 }
1073 if (radio->version == 0x2050 && radio->revision <= 0x5)
1074 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
1075 }
1076
1077 static void key_write(struct bcm43xx_private *bcm,
1078 u8 index, u8 algorithm, const u16 *key)
1079 {
1080 unsigned int i, basic_wep = 0;
1081 u32 offset;
1082 u16 value;
1083
1084 /* Write associated key information */
1085 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1086 ((index << 4) | (algorithm & 0x0F)));
1087
1088 /* The first 4 WEP keys need extra love */
1089 if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1090 (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1091 basic_wep = 1;
1092
1093 /* Write key payload, 8 little endian words */
1094 offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1095 for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1096 value = cpu_to_le16(key[i]);
1097 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1098 offset + (i * 2), value);
1099
1100 if (!basic_wep)
1101 continue;
1102
1103 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1104 offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1105 value);
1106 }
1107 }
1108
1109 static void keymac_write(struct bcm43xx_private *bcm,
1110 u8 index, const u32 *addr)
1111 {
1112 /* for keys 0-3 there is no associated mac address */
1113 if (index < 4)
1114 return;
1115
1116 index -= 4;
1117 if (bcm->current_core->rev >= 5) {
1118 bcm43xx_shm_write32(bcm,
1119 BCM43xx_SHM_HWMAC,
1120 index * 2,
1121 cpu_to_be32(*addr));
1122 bcm43xx_shm_write16(bcm,
1123 BCM43xx_SHM_HWMAC,
1124 (index * 2) + 1,
1125 cpu_to_be16(*((u16 *)(addr + 1))));
1126 } else {
1127 if (index < 8) {
1128 TODO(); /* Put them in the macaddress filter */
1129 } else {
1130 TODO();
1131 /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1132 Keep in mind to update the count of keymacs in 0x003E as well! */
1133 }
1134 }
1135 }
1136
1137 static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1138 u8 index, u8 algorithm,
1139 const u8 *_key, int key_len,
1140 const u8 *mac_addr)
1141 {
1142 u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1143
1144 if (index >= ARRAY_SIZE(bcm->key))
1145 return -EINVAL;
1146 if (key_len > ARRAY_SIZE(key))
1147 return -EINVAL;
1148 if (algorithm < 1 || algorithm > 5)
1149 return -EINVAL;
1150
1151 memcpy(key, _key, key_len);
1152 key_write(bcm, index, algorithm, (const u16 *)key);
1153 keymac_write(bcm, index, (const u32 *)mac_addr);
1154
1155 bcm->key[index].algorithm = algorithm;
1156
1157 return 0;
1158 }
1159
1160 static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1161 {
1162 static const u32 zero_mac[2] = { 0 };
1163 unsigned int i,j, nr_keys = 54;
1164 u16 offset;
1165
1166 if (bcm->current_core->rev < 5)
1167 nr_keys = 16;
1168 assert(nr_keys <= ARRAY_SIZE(bcm->key));
1169
1170 for (i = 0; i < nr_keys; i++) {
1171 bcm->key[i].enabled = 0;
1172 /* returns for i < 4 immediately */
1173 keymac_write(bcm, i, zero_mac);
1174 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1175 0x100 + (i * 2), 0x0000);
1176 for (j = 0; j < 8; j++) {
1177 offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1178 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1179 offset, 0x0000);
1180 }
1181 }
1182 dprintk(KERN_INFO PFX "Keys cleared\n");
1183 }
1184
1185 /* Lowlevel core-switch function. This is only to be used in
1186 * bcm43xx_switch_core() and bcm43xx_probe_cores()
1187 */
1188 static int _switch_core(struct bcm43xx_private *bcm, int core)
1189 {
1190 int err;
1191 int attempts = 0;
1192 u32 current_core;
1193
1194 assert(core >= 0);
1195 while (1) {
1196 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1197 (core * 0x1000) + 0x18000000);
1198 if (unlikely(err))
1199 goto error;
1200 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1201 &current_core);
1202 if (unlikely(err))
1203 goto error;
1204 current_core = (current_core - 0x18000000) / 0x1000;
1205 if (current_core == core)
1206 break;
1207
1208 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1209 goto error;
1210 udelay(10);
1211 }
1212 #ifdef CONFIG_BCM947XX
1213 if (bcm->pci_dev->bus->number == 0)
1214 bcm->current_core_offset = 0x1000 * core;
1215 else
1216 bcm->current_core_offset = 0;
1217 #endif
1218
1219 return 0;
1220 error:
1221 printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1222 return -ENODEV;
1223 }
1224
1225 int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1226 {
1227 int err;
1228
1229 if (unlikely(!new_core))
1230 return 0;
1231 if (!new_core->available)
1232 return -ENODEV;
1233 if (bcm->current_core == new_core)
1234 return 0;
1235 err = _switch_core(bcm, new_core->index);
1236 if (unlikely(err))
1237 goto out;
1238
1239 bcm->current_core = new_core;
1240 out:
1241 return err;
1242 }
1243
1244 static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
1245 {
1246 u32 value;
1247
1248 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1249 value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1250 | BCM43xx_SBTMSTATELOW_REJECT;
1251
1252 return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1253 }
1254
1255 /* disable current core */
1256 static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1257 {
1258 u32 sbtmstatelow;
1259 u32 sbtmstatehigh;
1260 int i;
1261
1262 /* fetch sbtmstatelow from core information registers */
1263 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1264
1265 /* core is already in reset */
1266 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1267 goto out;
1268
1269 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1270 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1271 BCM43xx_SBTMSTATELOW_REJECT;
1272 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1273
1274 for (i = 0; i < 1000; i++) {
1275 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1276 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1277 i = -1;
1278 break;
1279 }
1280 udelay(10);
1281 }
1282 if (i != -1) {
1283 printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1284 return -EBUSY;
1285 }
1286
1287 for (i = 0; i < 1000; i++) {
1288 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1289 if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1290 i = -1;
1291 break;
1292 }
1293 udelay(10);
1294 }
1295 if (i != -1) {
1296 printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1297 return -EBUSY;
1298 }
1299
1300 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1301 BCM43xx_SBTMSTATELOW_REJECT |
1302 BCM43xx_SBTMSTATELOW_RESET |
1303 BCM43xx_SBTMSTATELOW_CLOCK |
1304 core_flags;
1305 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1306 udelay(10);
1307 }
1308
1309 sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1310 BCM43xx_SBTMSTATELOW_REJECT |
1311 core_flags;
1312 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1313
1314 out:
1315 bcm->current_core->enabled = 0;
1316
1317 return 0;
1318 }
1319
1320 /* enable (reset) current core */
1321 static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1322 {
1323 u32 sbtmstatelow;
1324 u32 sbtmstatehigh;
1325 u32 sbimstate;
1326 int err;
1327
1328 err = bcm43xx_core_disable(bcm, core_flags);
1329 if (err)
1330 goto out;
1331
1332 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1333 BCM43xx_SBTMSTATELOW_RESET |
1334 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1335 core_flags;
1336 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1337 udelay(1);
1338
1339 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1340 if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1341 sbtmstatehigh = 0x00000000;
1342 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1343 }
1344
1345 sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1346 if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1347 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1348 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1349 }
1350
1351 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1352 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1353 core_flags;
1354 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1355 udelay(1);
1356
1357 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1358 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1359 udelay(1);
1360
1361 bcm->current_core->enabled = 1;
1362 assert(err == 0);
1363 out:
1364 return err;
1365 }
1366
1367 /* http://bcm-specs.sipsolutions.net/80211CoreReset */
1368 void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1369 {
1370 u32 flags = 0x00040000;
1371
1372 if ((bcm43xx_core_enabled(bcm)) &&
1373 !bcm43xx_using_pio(bcm)) {
1374 //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1375 #if 0
1376 #ifndef CONFIG_BCM947XX
1377 /* reset all used DMA controllers. */
1378 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1379 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1380 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1381 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1382 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1383 if (bcm->current_core->rev < 5)
1384 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1385 #endif
1386 #endif
1387 }
1388 if (bcm43xx_status(bcm) == BCM43xx_STAT_SHUTTINGDOWN) {
1389 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1390 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1391 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1392 } else {
1393 if (connect_phy)
1394 flags |= 0x20000000;
1395 bcm43xx_phy_connect(bcm, connect_phy);
1396 bcm43xx_core_enable(bcm, flags);
1397 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1398 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1399 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1400 | BCM43xx_SBF_400);
1401 }
1402 }
1403
1404 static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1405 {
1406 bcm43xx_radio_turn_off(bcm);
1407 bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1408 bcm43xx_core_disable(bcm, 0);
1409 }
1410
1411 /* Mark the current 80211 core inactive. */
1412 static void bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm)
1413 {
1414 u32 sbtmstatelow;
1415
1416 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1417 bcm43xx_radio_turn_off(bcm);
1418 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1419 sbtmstatelow &= 0xDFF5FFFF;
1420 sbtmstatelow |= 0x000A0000;
1421 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1422 udelay(1);
1423 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1424 sbtmstatelow &= 0xFFF5FFFF;
1425 sbtmstatelow |= 0x00080000;
1426 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1427 udelay(1);
1428 }
1429
1430 static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
1431 {
1432 u32 v0, v1;
1433 u16 tmp;
1434 struct bcm43xx_xmitstatus stat;
1435
1436 while (1) {
1437 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1438 if (!v0)
1439 break;
1440 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1441
1442 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1443 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1444 stat.flags = tmp & 0xFF;
1445 stat.cnt1 = (tmp & 0x0F00) >> 8;
1446 stat.cnt2 = (tmp & 0xF000) >> 12;
1447 stat.seq = (u16)(v1 & 0xFFFF);
1448 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1449
1450 bcm43xx_debugfs_log_txstat(bcm, &stat);
1451
1452 if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
1453 continue;
1454 if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
1455 //TODO: packet was not acked (was lost)
1456 }
1457 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1458
1459 if (bcm43xx_using_pio(bcm))
1460 bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1461 else
1462 bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1463 }
1464 }
1465
1466 static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
1467 {
1468 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1469 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1470 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1471 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1472 assert(bcm->noisecalc.core_at_start == bcm->current_core);
1473 assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
1474 }
1475
1476 static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1477 {
1478 /* Top half of Link Quality calculation. */
1479
1480 if (bcm->noisecalc.calculation_running)
1481 return;
1482 bcm->noisecalc.core_at_start = bcm->current_core;
1483 bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
1484 bcm->noisecalc.calculation_running = 1;
1485 bcm->noisecalc.nr_samples = 0;
1486
1487 bcm43xx_generate_noise_sample(bcm);
1488 }
1489
1490 static void handle_irq_noise(struct bcm43xx_private *bcm)
1491 {
1492 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1493 u16 tmp;
1494 u8 noise[4];
1495 u8 i, j;
1496 s32 average;
1497
1498 /* Bottom half of Link Quality calculation. */
1499
1500 assert(bcm->noisecalc.calculation_running);
1501 if (bcm->noisecalc.core_at_start != bcm->current_core ||
1502 bcm->noisecalc.channel_at_start != radio->channel)
1503 goto drop_calculation;
1504 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1505 noise[0] = (tmp & 0x00FF);
1506 noise[1] = (tmp & 0xFF00) >> 8;
1507 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1508 noise[2] = (tmp & 0x00FF);
1509 noise[3] = (tmp & 0xFF00) >> 8;
1510 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1511 noise[2] == 0x7F || noise[3] == 0x7F)
1512 goto generate_new;
1513
1514 /* Get the noise samples. */
1515 assert(bcm->noisecalc.nr_samples < 8);
1516 i = bcm->noisecalc.nr_samples;
1517 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1518 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1519 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1520 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1521 bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1522 bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1523 bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1524 bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1525 bcm->noisecalc.nr_samples++;
1526 if (bcm->noisecalc.nr_samples == 8) {
1527 /* Calculate the Link Quality by the noise samples. */
1528 average = 0;
1529 for (i = 0; i < 8; i++) {
1530 for (j = 0; j < 4; j++)
1531 average += bcm->noisecalc.samples[i][j];
1532 }
1533 average /= (8 * 4);
1534 average *= 125;
1535 average += 64;
1536 average /= 128;
1537
1538 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1539 tmp = (tmp / 128) & 0x1F;
1540 if (tmp >= 8)
1541 average += 2;
1542 else
1543 average -= 25;
1544 if (tmp == 8)
1545 average -= 72;
1546 else
1547 average -= 48;
1548
1549 bcm->stats.noise = average;
1550 drop_calculation:
1551 bcm->noisecalc.calculation_running = 0;
1552 return;
1553 }
1554 generate_new:
1555 bcm43xx_generate_noise_sample(bcm);
1556 }
1557
1558 static void handle_irq_ps(struct bcm43xx_private *bcm)
1559 {
1560 if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1561 ///TODO: PS TBTT
1562 } else {
1563 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1564 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1565 }
1566 if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1567 bcm->reg124_set_0x4 = 1;
1568 //FIXME else set to false?
1569 }
1570
1571 static void handle_irq_reg124(struct bcm43xx_private *bcm)
1572 {
1573 if (!bcm->reg124_set_0x4)
1574 return;
1575 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1576 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1577 | 0x4);
1578 //FIXME: reset reg124_set_0x4 to false?
1579 }
1580
1581 static void handle_irq_pmq(struct bcm43xx_private *bcm)
1582 {
1583 u32 tmp;
1584
1585 //TODO: AP mode.
1586
1587 while (1) {
1588 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1589 if (!(tmp & 0x00000008))
1590 break;
1591 }
1592 /* 16bit write is odd, but correct. */
1593 bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1594 }
1595
1596 static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1597 u16 ram_offset, u16 shm_size_offset)
1598 {
1599 u32 value;
1600 u16 size = 0;
1601
1602 /* Timestamp. */
1603 //FIXME: assumption: The chip sets the timestamp
1604 value = 0;
1605 bcm43xx_ram_write(bcm, ram_offset++, value);
1606 bcm43xx_ram_write(bcm, ram_offset++, value);
1607 size += 8;
1608
1609 /* Beacon Interval / Capability Information */
1610 value = 0x0000;//FIXME: Which interval?
1611 value |= (1 << 0) << 16; /* ESS */
1612 value |= (1 << 2) << 16; /* CF Pollable */ //FIXME?
1613 value |= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
1614 if (!bcm->ieee->open_wep)
1615 value |= (1 << 4) << 16; /* Privacy */
1616 bcm43xx_ram_write(bcm, ram_offset++, value);
1617 size += 4;
1618
1619 /* SSID */
1620 //TODO
1621
1622 /* FH Parameter Set */
1623 //TODO
1624
1625 /* DS Parameter Set */
1626 //TODO
1627
1628 /* CF Parameter Set */
1629 //TODO
1630
1631 /* TIM */
1632 //TODO
1633
1634 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1635 }
1636
1637 static void handle_irq_beacon(struct bcm43xx_private *bcm)
1638 {
1639 u32 status;
1640
1641 bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1642 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1643
1644 if ((status & 0x1) && (status & 0x2)) {
1645 /* ACK beacon IRQ. */
1646 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1647 BCM43xx_IRQ_BEACON);
1648 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1649 return;
1650 }
1651 if (!(status & 0x1)) {
1652 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1653 status |= 0x1;
1654 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1655 }
1656 if (!(status & 0x2)) {
1657 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1658 status |= 0x2;
1659 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1660 }
1661 }
1662
1663 /* Interrupt handler bottom-half */
1664 static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1665 {
1666 u32 reason;
1667 u32 dma_reason[6];
1668 u32 merged_dma_reason = 0;
1669 int i, activity = 0;
1670 unsigned long flags;
1671
1672 #ifdef CONFIG_BCM43XX_DEBUG
1673 u32 _handled = 0x00000000;
1674 # define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
1675 #else
1676 # define bcmirq_handled(irq) do { /* nothing */ } while (0)
1677 #endif /* CONFIG_BCM43XX_DEBUG*/
1678
1679 spin_lock_irqsave(&bcm->irq_lock, flags);
1680 reason = bcm->irq_reason;
1681 for (i = 5; i >= 0; i--) {
1682 dma_reason[i] = bcm->dma_reason[i];
1683 merged_dma_reason |= dma_reason[i];
1684 }
1685
1686 if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1687 /* TX error. We get this when Template Ram is written in wrong endianess
1688 * in dummy_tx(). We also get this if something is wrong with the TX header
1689 * on DMA or PIO queues.
1690 * Maybe we get this in other error conditions, too.
1691 */
1692 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
1693 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1694 }
1695 if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_FATALMASK)) {
1696 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1697 "0x%08X, 0x%08X, 0x%08X, "
1698 "0x%08X, 0x%08X, 0x%08X\n",
1699 dma_reason[0], dma_reason[1],
1700 dma_reason[2], dma_reason[3],
1701 dma_reason[4], dma_reason[5]);
1702 bcm43xx_controller_restart(bcm, "DMA error");
1703 mmiowb();
1704 spin_unlock_irqrestore(&bcm->irq_lock, flags);
1705 return;
1706 }
1707 if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_NONFATALMASK)) {
1708 printkl(KERN_ERR PFX "DMA error: "
1709 "0x%08X, 0x%08X, 0x%08X, "
1710 "0x%08X, 0x%08X, 0x%08X\n",
1711 dma_reason[0], dma_reason[1],
1712 dma_reason[2], dma_reason[3],
1713 dma_reason[4], dma_reason[5]);
1714 }
1715
1716 if (reason & BCM43xx_IRQ_PS) {
1717 handle_irq_ps(bcm);
1718 bcmirq_handled(BCM43xx_IRQ_PS);
1719 }
1720
1721 if (reason & BCM43xx_IRQ_REG124) {
1722 handle_irq_reg124(bcm);
1723 bcmirq_handled(BCM43xx_IRQ_REG124);
1724 }
1725
1726 if (reason & BCM43xx_IRQ_BEACON) {
1727 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1728 handle_irq_beacon(bcm);
1729 bcmirq_handled(BCM43xx_IRQ_BEACON);
1730 }
1731
1732 if (reason & BCM43xx_IRQ_PMQ) {
1733 handle_irq_pmq(bcm);
1734 bcmirq_handled(BCM43xx_IRQ_PMQ);
1735 }
1736
1737 if (reason & BCM43xx_IRQ_SCAN) {
1738 /*TODO*/
1739 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1740 }
1741
1742 if (reason & BCM43xx_IRQ_NOISE) {
1743 handle_irq_noise(bcm);
1744 bcmirq_handled(BCM43xx_IRQ_NOISE);
1745 }
1746
1747 /* Check the DMA reason registers for received data. */
1748 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1749 if (bcm43xx_using_pio(bcm))
1750 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
1751 else
1752 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
1753 /* We intentionally don't set "activity" to 1, here. */
1754 }
1755 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1756 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1757 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1758 if (bcm43xx_using_pio(bcm))
1759 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
1760 else
1761 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring3);
1762 activity = 1;
1763 }
1764 assert(!(dma_reason[4] & BCM43xx_DMAIRQ_RX_DONE));
1765 assert(!(dma_reason[5] & BCM43xx_DMAIRQ_RX_DONE));
1766 bcmirq_handled(BCM43xx_IRQ_RX);
1767
1768 if (reason & BCM43xx_IRQ_XMIT_STATUS) {
1769 handle_irq_transmit_status(bcm);
1770 activity = 1;
1771 //TODO: In AP mode, this also causes sending of powersave responses.
1772 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1773 }
1774
1775 /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1776 bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1777 #ifdef CONFIG_BCM43XX_DEBUG
1778 if (unlikely(reason & ~_handled)) {
1779 printkl(KERN_WARNING PFX
1780 "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
1781 "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1782 reason, (reason & ~_handled),
1783 dma_reason[0], dma_reason[1],
1784 dma_reason[2], dma_reason[3]);
1785 }
1786 #endif
1787 #undef bcmirq_handled
1788
1789 if (!modparam_noleds)
1790 bcm43xx_leds_update(bcm, activity);
1791 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
1792 mmiowb();
1793 spin_unlock_irqrestore(&bcm->irq_lock, flags);
1794 }
1795
1796 static void pio_irq_workaround(struct bcm43xx_private *bcm,
1797 u16 base, int queueidx)
1798 {
1799 u16 rxctl;
1800
1801 rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
1802 if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1803 bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1804 else
1805 bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1806 }
1807
1808 static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
1809 {
1810 if (bcm43xx_using_pio(bcm) &&
1811 (bcm->current_core->rev < 3) &&
1812 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1813 /* Apply a PIO specific workaround to the dma_reasons */
1814 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
1815 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
1816 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
1817 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
1818 }
1819
1820 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
1821
1822 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_REASON,
1823 bcm->dma_reason[0]);
1824 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
1825 bcm->dma_reason[1]);
1826 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
1827 bcm->dma_reason[2]);
1828 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
1829 bcm->dma_reason[3]);
1830 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1831 bcm->dma_reason[4]);
1832 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_REASON,
1833 bcm->dma_reason[5]);
1834 }
1835
1836 /* Interrupt handler top-half */
1837 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
1838 {
1839 irqreturn_t ret = IRQ_HANDLED;
1840 struct bcm43xx_private *bcm = dev_id;
1841 u32 reason;
1842
1843 if (!bcm)
1844 return IRQ_NONE;
1845
1846 spin_lock(&bcm->irq_lock);
1847
1848 assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
1849 assert(bcm->current_core->id == BCM43xx_COREID_80211);
1850
1851 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1852 if (reason == 0xffffffff) {
1853 /* irq not for us (shared irq) */
1854 ret = IRQ_NONE;
1855 goto out;
1856 }
1857 reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1858 if (!reason)
1859 goto out;
1860
1861 bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA0_REASON)
1862 & 0x0001DC00;
1863 bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1864 & 0x0000DC00;
1865 bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1866 & 0x0000DC00;
1867 bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1868 & 0x0001DC00;
1869 bcm->dma_reason[4] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1870 & 0x0000DC00;
1871 bcm->dma_reason[5] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA5_REASON)
1872 & 0x0000DC00;
1873
1874 bcm43xx_interrupt_ack(bcm, reason);
1875
1876 /* disable all IRQs. They are enabled again in the bottom half. */
1877 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1878 /* save the reason code and call our bottom half. */
1879 bcm->irq_reason = reason;
1880 tasklet_schedule(&bcm->isr_tasklet);
1881
1882 out:
1883 mmiowb();
1884 spin_unlock(&bcm->irq_lock);
1885
1886 return ret;
1887 }
1888
1889 static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
1890 {
1891 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1892
1893 if (bcm->firmware_norelease && !force)
1894 return; /* Suspending or controller reset. */
1895 release_firmware(phy->ucode);
1896 phy->ucode = NULL;
1897 release_firmware(phy->pcm);
1898 phy->pcm = NULL;
1899 release_firmware(phy->initvals0);
1900 phy->initvals0 = NULL;
1901 release_firmware(phy->initvals1);
1902 phy->initvals1 = NULL;
1903 }
1904
1905 static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1906 {
1907 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1908 u8 rev = bcm->current_core->rev;
1909 int err = 0;
1910 int nr;
1911 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1912
1913 if (!phy->ucode) {
1914 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1915 (rev >= 5 ? 5 : rev),
1916 modparam_fwpostfix);
1917 err = request_firmware(&phy->ucode, buf, &bcm->pci_dev->dev);
1918 if (err) {
1919 printk(KERN_ERR PFX
1920 "Error: Microcode \"%s\" not available or load failed.\n",
1921 buf);
1922 goto error;
1923 }
1924 }
1925
1926 if (!phy->pcm) {
1927 snprintf(buf, ARRAY_SIZE(buf),
1928 "bcm43xx_pcm%d%s.fw",
1929 (rev < 5 ? 4 : 5),
1930 modparam_fwpostfix);
1931 err = request_firmware(&phy->pcm, buf, &bcm->pci_dev->dev);
1932 if (err) {
1933 printk(KERN_ERR PFX
1934 "Error: PCM \"%s\" not available or load failed.\n",
1935 buf);
1936 goto error;
1937 }
1938 }
1939
1940 if (!phy->initvals0) {
1941 if (rev == 2 || rev == 4) {
1942 switch (phy->type) {
1943 case BCM43xx_PHYTYPE_A:
1944 nr = 3;
1945 break;
1946 case BCM43xx_PHYTYPE_B:
1947 case BCM43xx_PHYTYPE_G:
1948 nr = 1;
1949 break;
1950 default:
1951 goto err_noinitval;
1952 }
1953
1954 } else if (rev >= 5) {
1955 switch (phy->type) {
1956 case BCM43xx_PHYTYPE_A:
1957 nr = 7;
1958 break;
1959 case BCM43xx_PHYTYPE_B:
1960 case BCM43xx_PHYTYPE_G:
1961 nr = 5;
1962 break;
1963 default:
1964 goto err_noinitval;
1965 }
1966 } else
1967 goto err_noinitval;
1968 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1969 nr, modparam_fwpostfix);
1970
1971 err = request_firmware(&phy->initvals0, buf, &bcm->pci_dev->dev);
1972 if (err) {
1973 printk(KERN_ERR PFX
1974 "Error: InitVals \"%s\" not available or load failed.\n",
1975 buf);
1976 goto error;
1977 }
1978 if (phy->initvals0->size % sizeof(struct bcm43xx_initval)) {
1979 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1980 goto error;
1981 }
1982 }
1983
1984 if (!phy->initvals1) {
1985 if (rev >= 5) {
1986 u32 sbtmstatehigh;
1987
1988 switch (phy->type) {
1989 case BCM43xx_PHYTYPE_A:
1990 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1991 if (sbtmstatehigh & 0x00010000)
1992 nr = 9;
1993 else
1994 nr = 10;
1995 break;
1996 case BCM43xx_PHYTYPE_B:
1997 case BCM43xx_PHYTYPE_G:
1998 nr = 6;
1999 break;
2000 default:
2001 goto err_noinitval;
2002 }
2003 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2004 nr, modparam_fwpostfix);
2005
2006 err = request_firmware(&phy->initvals1, buf, &bcm->pci_dev->dev);
2007 if (err) {
2008 printk(KERN_ERR PFX
2009 "Error: InitVals \"%s\" not available or load failed.\n",
2010 buf);
2011 goto error;
2012 }
2013 if (phy->initvals1->size % sizeof(struct bcm43xx_initval)) {
2014 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2015 goto error;
2016 }
2017 }
2018 }
2019
2020 out:
2021 return err;
2022 error:
2023 bcm43xx_release_firmware(bcm, 1);
2024 goto out;
2025 err_noinitval:
2026 printk(KERN_ERR PFX "Error: No InitVals available!\n");
2027 err = -ENOENT;
2028 goto error;
2029 }
2030
2031 static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2032 {
2033 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2034 const u32 *data;
2035 unsigned int i, len;
2036
2037 /* Upload Microcode. */
2038 data = (u32 *)(phy->ucode->data);
2039 len = phy->ucode->size / sizeof(u32);
2040 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2041 for (i = 0; i < len; i++) {
2042 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2043 be32_to_cpu(data[i]));
2044 udelay(10);
2045 }
2046
2047 /* Upload PCM data. */
2048 data = (u32 *)(phy->pcm->data);
2049 len = phy->pcm->size / sizeof(u32);
2050 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2051 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2052 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2053 for (i = 0; i < len; i++) {
2054 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2055 be32_to_cpu(data[i]));
2056 udelay(10);
2057 }
2058 }
2059
2060 static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2061 const struct bcm43xx_initval *data,
2062 const unsigned int len)
2063 {
2064 u16 offset, size;
2065 u32 value;
2066 unsigned int i;
2067
2068 for (i = 0; i < len; i++) {
2069 offset = be16_to_cpu(data[i].offset);
2070 size = be16_to_cpu(data[i].size);
2071 value = be32_to_cpu(data[i].value);
2072
2073 if (unlikely(offset >= 0x1000))
2074 goto err_format;
2075 if (size == 2) {
2076 if (unlikely(value & 0xFFFF0000))
2077 goto err_format;
2078 bcm43xx_write16(bcm, offset, (u16)value);
2079 } else if (size == 4) {
2080 bcm43xx_write32(bcm, offset, value);
2081 } else
2082 goto err_format;
2083 }
2084
2085 return 0;
2086
2087 err_format:
2088 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2089 "Please fix your bcm43xx firmware files.\n");
2090 return -EPROTO;
2091 }
2092
2093 static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
2094 {
2095 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2096 int err;
2097
2098 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals0->data,
2099 phy->initvals0->size / sizeof(struct bcm43xx_initval));
2100 if (err)
2101 goto out;
2102 if (phy->initvals1) {
2103 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals1->data,
2104 phy->initvals1->size / sizeof(struct bcm43xx_initval));
2105 if (err)
2106 goto out;
2107 }
2108 out:
2109 return err;
2110 }
2111
2112 #ifdef CONFIG_BCM947XX
2113 static struct pci_device_id bcm43xx_47xx_ids[] = {
2114 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
2115 { 0 }
2116 };
2117 #endif
2118
2119 static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2120 {
2121 int err;
2122
2123 bcm->irq = bcm->pci_dev->irq;
2124 #ifdef CONFIG_BCM947XX
2125 if (bcm->pci_dev->bus->number == 0) {
2126 struct pci_dev *d;
2127 struct pci_device_id *id;
2128 for (id = bcm43xx_47xx_ids; id->vendor; id++) {
2129 d = pci_get_device(id->vendor, id->device, NULL);
2130 if (d != NULL) {
2131 bcm->irq = d->irq;
2132 pci_dev_put(d);
2133 break;
2134 }
2135 }
2136 }
2137 #endif
2138 err = request_irq(bcm->irq, bcm43xx_interrupt_handler,
2139 IRQF_SHARED, KBUILD_MODNAME, bcm);
2140 if (err)
2141 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
2142
2143 return err;
2144 }
2145
2146 /* Switch to the core used to write the GPIO register.
2147 * This is either the ChipCommon, or the PCI core.
2148 */
2149 static int switch_to_gpio_core(struct bcm43xx_private *bcm)
2150 {
2151 int err;
2152
2153 /* Where to find the GPIO register depends on the chipset.
2154 * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2155 * control register. Otherwise the register at offset 0x6c in the
2156 * PCI core is the GPIO control register.
2157 */
2158 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2159 if (err == -ENODEV) {
2160 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2161 if (unlikely(err == -ENODEV)) {
2162 printk(KERN_ERR PFX "gpio error: "
2163 "Neither ChipCommon nor PCI core available!\n");
2164 }
2165 }
2166
2167 return err;
2168 }
2169
2170 /* Initialize the GPIOs
2171 * http://bcm-specs.sipsolutions.net/GPIO
2172 */
2173 static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2174 {
2175 struct bcm43xx_coreinfo *old_core;
2176 int err;
2177 u32 mask, set;
2178
2179 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2180 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2181 & 0xFFFF3FFF);
2182
2183 bcm43xx_leds_switch_all(bcm, 0);
2184 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2185 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2186
2187 mask = 0x0000001F;
2188 set = 0x0000000F;
2189 if (bcm->chip_id == 0x4301) {
2190 mask |= 0x0060;
2191 set |= 0x0060;
2192 }
2193 if (0 /* FIXME: conditional unknown */) {
2194 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2195 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2196 | 0x0100);
2197 mask |= 0x0180;
2198 set |= 0x0180;
2199 }
2200 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
2201 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2202 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2203 | 0x0200);
2204 mask |= 0x0200;
2205 set |= 0x0200;
2206 }
2207 if (bcm->current_core->rev >= 2)
2208 mask |= 0x0010; /* FIXME: This is redundant. */
2209
2210 old_core = bcm->current_core;
2211 err = switch_to_gpio_core(bcm);
2212 if (err)
2213 goto out;
2214 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
2215 (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
2216 err = bcm43xx_switch_core(bcm, old_core);
2217 out:
2218 return err;
2219 }
2220
2221 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2222 static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2223 {
2224 struct bcm43xx_coreinfo *old_core;
2225 int err;
2226
2227 old_core = bcm->current_core;
2228 err = switch_to_gpio_core(bcm);
2229 if (err)
2230 return err;
2231 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2232 err = bcm43xx_switch_core(bcm, old_core);
2233 assert(err == 0);
2234
2235 return 0;
2236 }
2237
2238 /* http://bcm-specs.sipsolutions.net/EnableMac */
2239 void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2240 {
2241 bcm->mac_suspended--;
2242 assert(bcm->mac_suspended >= 0);
2243 if (bcm->mac_suspended == 0) {
2244 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2245 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2246 | BCM43xx_SBF_MAC_ENABLED);
2247 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2248 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2249 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2250 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2251 }
2252 }
2253
2254 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2255 void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2256 {
2257 int i;
2258 u32 tmp;
2259
2260 assert(bcm->mac_suspended >= 0);
2261 if (bcm->mac_suspended == 0) {
2262 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2263 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2264 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2265 & ~BCM43xx_SBF_MAC_ENABLED);
2266 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2267 for (i = 10000; i; i--) {
2268 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2269 if (tmp & BCM43xx_IRQ_READY)
2270 goto out;
2271 udelay(1);
2272 }
2273 printkl(KERN_ERR PFX "MAC suspend failed\n");
2274 }
2275 out:
2276 bcm->mac_suspended++;
2277 }
2278
2279 void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2280 int iw_mode)
2281 {
2282 unsigned long flags;
2283 struct net_device *net_dev = bcm->net_dev;
2284 u32 status;
2285 u16 value;
2286
2287 spin_lock_irqsave(&bcm->ieee->lock, flags);
2288 bcm->ieee->iw_mode = iw_mode;
2289 spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2290 if (iw_mode == IW_MODE_MONITOR)
2291 net_dev->type = ARPHRD_IEEE80211;
2292 else
2293 net_dev->type = ARPHRD_ETHER;
2294
2295 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2296 /* Reset status to infrastructured mode */
2297 status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
2298 status &= ~BCM43xx_SBF_MODE_PROMISC;
2299 status |= BCM43xx_SBF_MODE_NOTADHOC;
2300
2301 /* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
2302 status |= BCM43xx_SBF_MODE_PROMISC;
2303
2304 switch (iw_mode) {
2305 case IW_MODE_MONITOR:
2306 status |= BCM43xx_SBF_MODE_MONITOR;
2307 status |= BCM43xx_SBF_MODE_PROMISC;
2308 break;
2309 case IW_MODE_ADHOC:
2310 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2311 break;
2312 case IW_MODE_MASTER:
2313 status |= BCM43xx_SBF_MODE_AP;
2314 break;
2315 case IW_MODE_SECOND:
2316 case IW_MODE_REPEAT:
2317 TODO(); /* TODO */
2318 break;
2319 case IW_MODE_INFRA:
2320 /* nothing to be done here... */
2321 break;
2322 default:
2323 dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
2324 }
2325 if (net_dev->flags & IFF_PROMISC)
2326 status |= BCM43xx_SBF_MODE_PROMISC;
2327 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
2328
2329 value = 0x0002;
2330 if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2331 if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
2332 value = 0x0064;
2333 else
2334 value = 0x0032;
2335 }
2336 bcm43xx_write16(bcm, 0x0612, value);
2337 }
2338
2339 /* This is the opposite of bcm43xx_chip_init() */
2340 static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2341 {
2342 bcm43xx_radio_turn_off(bcm);
2343 if (!modparam_noleds)
2344 bcm43xx_leds_exit(bcm);
2345 bcm43xx_gpio_cleanup(bcm);
2346 bcm43xx_release_firmware(bcm, 0);
2347 }
2348
2349 /* Initialize the chip
2350 * http://bcm-specs.sipsolutions.net/ChipInit
2351 */
2352 static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2353 {
2354 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2355 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2356 int err;
2357 int i, tmp;
2358 u32 value32;
2359 u16 value16;
2360
2361 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2362 BCM43xx_SBF_CORE_READY
2363 | BCM43xx_SBF_400);
2364
2365 err = bcm43xx_request_firmware(bcm);
2366 if (err)
2367 goto out;
2368 bcm43xx_upload_microcode(bcm);
2369
2370 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xFFFFFFFF);
2371 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2372 i = 0;
2373 while (1) {
2374 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2375 if (value32 == BCM43xx_IRQ_READY)
2376 break;
2377 i++;
2378 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2379 printk(KERN_ERR PFX "IRQ_READY timeout\n");
2380 err = -ENODEV;
2381 goto err_release_fw;
2382 }
2383 udelay(10);
2384 }
2385 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2386
2387 value16 = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2388 BCM43xx_UCODE_REVISION);
2389
2390 dprintk(KERN_INFO PFX "Microcode rev 0x%x, pl 0x%x "
2391 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", value16,
2392 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2393 BCM43xx_UCODE_PATCHLEVEL),
2394 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2395 BCM43xx_UCODE_DATE) >> 12) & 0xf,
2396 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2397 BCM43xx_UCODE_DATE) >> 8) & 0xf,
2398 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2399 BCM43xx_UCODE_DATE) & 0xff,
2400 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2401 BCM43xx_UCODE_TIME) >> 11) & 0x1f,
2402 (bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2403 BCM43xx_UCODE_TIME) >> 5) & 0x3f,
2404 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
2405 BCM43xx_UCODE_TIME) & 0x1f);
2406
2407 if ( value16 > 0x128 ) {
2408 dprintk(KERN_ERR PFX
2409 "Firmware: no support for microcode rev > 0x128\n");
2410 err = -1;
2411 goto err_release_fw;
2412 }
2413
2414 err = bcm43xx_gpio_init(bcm);
2415 if (err)
2416 goto err_release_fw;
2417
2418 err = bcm43xx_upload_initvals(bcm);
2419 if (err)
2420 goto err_gpio_cleanup;
2421 bcm43xx_radio_turn_on(bcm);
2422
2423 bcm43xx_write16(bcm, 0x03E6, 0x0000);
2424 err = bcm43xx_phy_init(bcm);
2425 if (err)
2426 goto err_radio_off;
2427
2428 /* Select initial Interference Mitigation. */
2429 tmp = radio->interfmode;
2430 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2431 bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2432
2433 bcm43xx_phy_set_antenna_diversity(bcm);
2434 bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
2435 if (phy->type == BCM43xx_PHYTYPE_B) {
2436 value16 = bcm43xx_read16(bcm, 0x005E);
2437 value16 |= 0x0004;
2438 bcm43xx_write16(bcm, 0x005E, value16);
2439 }
2440 bcm43xx_write32(bcm, 0x0100, 0x01000000);
2441 if (bcm->current_core->rev < 5)
2442 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2443
2444 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2445 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2446 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2447 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2448 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2449 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2450
2451 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2452 value32 |= 0x100000;
2453 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2454
2455 if (bcm43xx_using_pio(bcm)) {
2456 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2457 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2458 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2459 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2460 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2461 }
2462
2463 /* Probe Response Timeout value */
2464 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2465 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2466
2467 /* Initially set the wireless operation mode. */
2468 bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
2469
2470 if (bcm->current_core->rev < 3) {
2471 bcm43xx_write16(bcm, 0x060E, 0x0000);
2472 bcm43xx_write16(bcm, 0x0610, 0x8000);
2473 bcm43xx_write16(bcm, 0x0604, 0x0000);
2474 bcm43xx_write16(bcm, 0x0606, 0x0200);
2475 } else {
2476 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2477 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2478 }
2479 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2480 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2481 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2482 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2483 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2484 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2485 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2486
2487 value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2488 value32 |= 0x00100000;
2489 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2490
2491 bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2492
2493 assert(err == 0);
2494 dprintk(KERN_INFO PFX "Chip initialized\n");
2495 out:
2496 return err;
2497
2498 err_radio_off:
2499 bcm43xx_radio_turn_off(bcm);
2500 err_gpio_cleanup:
2501 bcm43xx_gpio_cleanup(bcm);
2502 err_release_fw:
2503 bcm43xx_release_firmware(bcm, 1);
2504 goto out;
2505 }
2506
2507 /* Validate chip access
2508 * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2509 static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2510 {
2511 u32 value;
2512 u32 shm_backup;
2513
2514 shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2515 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
2516 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2517 goto error;
2518 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
2519 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2520 goto error;
2521 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2522
2523 value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2524 if ((value | 0x80000000) != 0x80000400)
2525 goto error;
2526
2527 value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2528 if (value != 0x00000000)
2529 goto error;
2530
2531 return 0;
2532 error:
2533 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2534 return -ENODEV;
2535 }
2536
2537 static void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
2538 {
2539 /* Initialize a "phyinfo" structure. The structure is already
2540 * zeroed out.
2541 * This is called on insmod time to initialize members.
2542 */
2543 phy->savedpctlreg = 0xFFFF;
2544 spin_lock_init(&phy->lock);
2545 }
2546
2547 static void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
2548 {
2549 /* Initialize a "radioinfo" structure. The structure is already
2550 * zeroed out.
2551 * This is called on insmod time to initialize members.
2552 */
2553 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2554 radio->channel = 0xFF;
2555 radio->initial_channel = 0xFF;
2556 }
2557
2558 static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2559 {
2560 int err, i;
2561 int current_core;
2562 u32 core_vendor, core_id, core_rev;
2563 u32 sb_id_hi, chip_id_32 = 0;
2564 u16 pci_device, chip_id_16;
2565 u8 core_count;
2566
2567 memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2568 memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
2569 memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2570 * BCM43xx_MAX_80211_CORES);
2571 memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2572 * BCM43xx_MAX_80211_CORES);
2573 bcm->nr_80211_available = 0;
2574 bcm->current_core = NULL;
2575 bcm->active_80211_core = NULL;
2576
2577 /* map core 0 */
2578 err = _switch_core(bcm, 0);
2579 if (err)
2580 goto out;
2581
2582 /* fetch sb_id_hi from core information registers */
2583 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2584
2585 core_id = (sb_id_hi & 0xFFF0) >> 4;
2586 core_rev = (sb_id_hi & 0xF);
2587 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2588
2589 /* if present, chipcommon is always core 0; read the chipid from it */
2590 if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2591 chip_id_32 = bcm43xx_read32(bcm, 0);
2592 chip_id_16 = chip_id_32 & 0xFFFF;
2593 bcm->core_chipcommon.available = 1;
2594 bcm->core_chipcommon.id = core_id;
2595 bcm->core_chipcommon.rev = core_rev;
2596 bcm->core_chipcommon.index = 0;
2597 /* While we are at it, also read the capabilities. */
2598 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2599 } else {
2600 /* without a chipCommon, use a hard coded table. */
2601 pci_device = bcm->pci_dev->device;
2602 if (pci_device == 0x4301)
2603 chip_id_16 = 0x4301;
2604 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2605 chip_id_16 = 0x4307;
2606 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2607 chip_id_16 = 0x4402;
2608 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2609 chip_id_16 = 0x4610;
2610 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2611 chip_id_16 = 0x4710;
2612 #ifdef CONFIG_BCM947XX
2613 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2614 chip_id_16 = 0x4309;
2615 #endif
2616 else {
2617 printk(KERN_ERR PFX "Could not determine Chip ID\n");
2618 return -ENODEV;
2619 }
2620 }
2621
2622 /* ChipCommon with Core Rev >=4 encodes number of cores,
2623 * otherwise consult hardcoded table */
2624 if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2625 core_count = (chip_id_32 & 0x0F000000) >> 24;
2626 } else {
2627 switch (chip_id_16) {
2628 case 0x4610:
2629 case 0x4704:
2630 case 0x4710:
2631 core_count = 9;
2632 break;
2633 case 0x4310:
2634 core_count = 8;
2635 break;
2636 case 0x5365:
2637 core_count = 7;
2638 break;
2639 case 0x4306:
2640 core_count = 6;
2641 break;
2642 case 0x4301:
2643 case 0x4307:
2644 core_count = 5;
2645 break;
2646 case 0x4402:
2647 core_count = 3;
2648 break;
2649 default:
2650 /* SOL if we get here */
2651 assert(0);
2652 core_count = 1;
2653 }
2654 }
2655
2656 bcm->chip_id = chip_id_16;
2657 bcm->chip_rev = (chip_id_32 & 0x000F0000) >> 16;
2658 bcm->chip_package = (chip_id_32 & 0x00F00000) >> 20;
2659
2660 dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2661 bcm->chip_id, bcm->chip_rev);
2662 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2663 if (bcm->core_chipcommon.available) {
2664 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2665 core_id, core_rev, core_vendor,
2666 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
2667 }
2668
2669 if (bcm->core_chipcommon.available)
2670 current_core = 1;
2671 else
2672 current_core = 0;
2673 for ( ; current_core < core_count; current_core++) {
2674 struct bcm43xx_coreinfo *core;
2675 struct bcm43xx_coreinfo_80211 *ext_80211;
2676
2677 err = _switch_core(bcm, current_core);
2678 if (err)
2679 goto out;
2680 /* Gather information */
2681 /* fetch sb_id_hi from core information registers */
2682 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2683
2684 /* extract core_id, core_rev, core_vendor */
2685 core_id = (sb_id_hi & 0xFFF0) >> 4;
2686 core_rev = (sb_id_hi & 0xF);
2687 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2688
2689 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2690 current_core, core_id, core_rev, core_vendor,
2691 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
2692
2693 core = NULL;
2694 switch (core_id) {
2695 case BCM43xx_COREID_PCI:
2696 core = &bcm->core_pci;
2697 if (core->available) {
2698 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2699 continue;
2700 }
2701 break;
2702 case BCM43xx_COREID_80211:
2703 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2704 core = &(bcm->core_80211[i]);
2705 ext_80211 = &(bcm->core_80211_ext[i]);
2706 if (!core->available)
2707 break;
2708 core = NULL;
2709 }
2710 if (!core) {
2711 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2712 BCM43xx_MAX_80211_CORES);
2713 continue;
2714 }
2715 if (i != 0) {
2716 /* More than one 80211 core is only supported
2717 * by special chips.
2718 * There are chips with two 80211 cores, but with
2719 * dangling pins on the second core. Be careful
2720 * and ignore these cores here.
2721 */
2722 if (bcm->pci_dev->device != 0x4324) {
2723 dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
2724 continue;
2725 }
2726 }
2727 switch (core_rev) {
2728 case 2:
2729 case 4:
2730 case 5:
2731 case 6:
2732 case 7:
2733 case 9:
2734 break;
2735 default:
2736 printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
2737 core_rev);
2738 err = -ENODEV;
2739 goto out;
2740 }
2741 bcm->nr_80211_available++;
2742 core->priv = ext_80211;
2743 bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2744 bcm43xx_init_struct_radioinfo(&ext_80211->radio);
2745 break;
2746 case BCM43xx_COREID_CHIPCOMMON:
2747 printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2748 break;
2749 }
2750 if (core) {
2751 core->available = 1;
2752 core->id = core_id;
2753 core->rev = core_rev;
2754 core->index = current_core;
2755 }
2756 }
2757
2758 if (!bcm->core_80211[0].available) {
2759 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2760 err = -ENODEV;
2761 goto out;
2762 }
2763
2764 err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2765
2766 assert(err == 0);
2767 out:
2768 return err;
2769 }
2770
2771 static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2772 {
2773 const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2774 u8 *bssid = bcm->ieee->bssid;
2775
2776 switch (bcm->ieee->iw_mode) {
2777 case IW_MODE_ADHOC:
2778 random_ether_addr(bssid);
2779 break;
2780 case IW_MODE_MASTER:
2781 case IW_MODE_INFRA:
2782 case IW_MODE_REPEAT:
2783 case IW_MODE_SECOND:
2784 case IW_MODE_MONITOR:
2785 memcpy(bssid, mac, ETH_ALEN);
2786 break;
2787 default:
2788 assert(0);
2789 }
2790 }
2791
2792 static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2793 u16 rate,
2794 int is_ofdm)
2795 {
2796 u16 offset;
2797
2798 if (is_ofdm) {
2799 offset = 0x480;
2800 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2801 }
2802 else {
2803 offset = 0x4C0;
2804 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2805 }
2806 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2807 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2808 }
2809
2810 static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2811 {
2812 switch (bcm43xx_current_phy(bcm)->type) {
2813 case BCM43xx_PHYTYPE_A:
2814 case BCM43xx_PHYTYPE_G:
2815 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2816 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2817 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2818 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2819 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2820 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2821 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2822 case BCM43xx_PHYTYPE_B:
2823 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2824 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2825 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2826 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2827 break;
2828 default:
2829 assert(0);
2830 }
2831 }
2832
2833 static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2834 {
2835 bcm43xx_chip_cleanup(bcm);
2836 bcm43xx_pio_free(bcm);
2837 bcm43xx_dma_free(bcm);
2838
2839 bcm->current_core->initialized = 0;
2840 }
2841
2842 /* http://bcm-specs.sipsolutions.net/80211Init */
2843 static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm,
2844 int active_wlcore)
2845 {
2846 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2847 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2848 u32 ucodeflags;
2849 int err;
2850 u32 sbimconfiglow;
2851 u8 limit;
2852
2853 if (bcm->chip_rev < 5) {
2854 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2855 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2856 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2857 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2858 sbimconfiglow |= 0x32;
2859 else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
2860 sbimconfiglow |= 0x53;
2861 else
2862 assert(0);
2863 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2864 }
2865
2866 bcm43xx_phy_calibrate(bcm);
2867 err = bcm43xx_chip_init(bcm);
2868 if (err)
2869 goto out;
2870
2871 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2872 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2873
2874 if (0 /*FIXME: which condition has to be used here? */)
2875 ucodeflags |= 0x00000010;
2876
2877 /* HW decryption needs to be set now */
2878 ucodeflags |= 0x40000000;
2879
2880 if (phy->type == BCM43xx_PHYTYPE_G) {
2881 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2882 if (phy->rev == 1)
2883 ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2884 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2885 ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
2886 } else if (phy->type == BCM43xx_PHYTYPE_B) {
2887 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2888 if (phy->rev >= 2 && radio->version == 0x2050)
2889 ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2890 }
2891
2892 if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2893 BCM43xx_UCODEFLAGS_OFFSET)) {
2894 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2895 BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2896 }
2897
2898 /* Short/Long Retry Limit.
2899 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2900 * the chip-internal counter.
2901 */
2902 limit = limit_value(modparam_short_retry, 0, 0xF);
2903 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2904 limit = limit_value(modparam_long_retry, 0, 0xF);
2905 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2906
2907 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2908 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2909
2910 bcm43xx_rate_memory_init(bcm);
2911
2912 /* Minimum Contention Window */
2913 if (phy->type == BCM43xx_PHYTYPE_B)
2914 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2915 else
2916 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2917 /* Maximum Contention Window */
2918 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2919
2920 bcm43xx_gen_bssid(bcm);
2921 bcm43xx_write_mac_bssid_templates(bcm);
2922
2923 if (bcm->current_core->rev >= 5)
2924 bcm43xx_write16(bcm, 0x043C, 0x000C);
2925
2926 if (active_wlcore) {
2927 if (bcm43xx_using_pio(bcm))
2928 err = bcm43xx_pio_init(bcm);
2929 else
2930 err = bcm43xx_dma_init(bcm);
2931 if (err)
2932 goto err_chip_cleanup;
2933 }
2934 bcm43xx_write16(bcm, 0x0612, 0x0050);
2935 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2936 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2937
2938 if (active_wlcore) {
2939 if (radio->initial_channel != 0xFF)
2940 bcm43xx_radio_selectchannel(bcm, radio->initial_channel, 0);
2941 }
2942
2943 /* Don't enable MAC/IRQ here, as it will race with the IRQ handler.
2944 * We enable it later.
2945 */
2946 bcm->current_core->initialized = 1;
2947 out:
2948 return err;
2949
2950 err_chip_cleanup:
2951 bcm43xx_chip_cleanup(bcm);
2952 goto out;
2953 }
2954
2955 static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2956 {
2957 int err;
2958 u16 pci_status;
2959
2960 err = bcm43xx_pctl_set_crystal(bcm, 1);
2961 if (err)
2962 goto out;
2963 bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2964 bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
2965
2966 out:
2967 return err;
2968 }
2969
2970 static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
2971 {
2972 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
2973 bcm43xx_pctl_set_crystal(bcm, 0);
2974 }
2975
2976 static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
2977 u32 address,
2978 u32 data)
2979 {
2980 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
2981 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
2982 }
2983
2984 static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
2985 {
2986 int err;
2987 struct bcm43xx_coreinfo *old_core;
2988
2989 old_core = bcm->current_core;
2990 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2991 if (err)
2992 goto out;
2993
2994 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
2995
2996 bcm43xx_switch_core(bcm, old_core);
2997 assert(err == 0);
2998 out:
2999 return err;
3000 }
3001
3002 /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
3003 * To enable core 0, pass a core_mask of 1<<0
3004 */
3005 static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
3006 u32 core_mask)
3007 {
3008 u32 backplane_flag_nr;
3009 u32 value;
3010 struct bcm43xx_coreinfo *old_core;
3011 int err = 0;
3012
3013 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
3014 backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
3015
3016 old_core = bcm->current_core;
3017 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3018 if (err)
3019 goto out;
3020
3021 if (bcm->core_pci.rev < 6) {
3022 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
3023 value |= (1 << backplane_flag_nr);
3024 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
3025 } else {
3026 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
3027 if (err) {
3028 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3029 goto out_switch_back;
3030 }
3031 value |= core_mask << 8;
3032 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
3033 if (err) {
3034 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3035 goto out_switch_back;
3036 }
3037 }
3038
3039 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3040 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3041 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3042
3043 if (bcm->core_pci.rev < 5) {
3044 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3045 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3046 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3047 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3048 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3049 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3050 err = bcm43xx_pcicore_commit_settings(bcm);
3051 assert(err == 0);
3052 }
3053
3054 out_switch_back:
3055 err = bcm43xx_switch_core(bcm, old_core);
3056 out:
3057 return err;
3058 }
3059
3060 static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
3061 {
3062 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3063
3064 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3065 return;
3066
3067 bcm43xx_mac_suspend(bcm);
3068 bcm43xx_phy_lo_g_measure(bcm);
3069 bcm43xx_mac_enable(bcm);
3070 }
3071
3072 static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
3073 {
3074 bcm43xx_phy_lo_mark_all_unused(bcm);
3075 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3076 bcm43xx_mac_suspend(bcm);
3077 bcm43xx_calc_nrssi_slope(bcm);
3078 bcm43xx_mac_enable(bcm);
3079 }
3080 }
3081
3082 static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
3083 {
3084 /* Update device statistics. */
3085 bcm43xx_calculate_link_quality(bcm);
3086 }
3087
3088 static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3089 {
3090 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3091 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
3092
3093 if (phy->type == BCM43xx_PHYTYPE_G) {
3094 //TODO: update_aci_moving_average
3095 if (radio->aci_enable && radio->aci_wlan_automatic) {
3096 bcm43xx_mac_suspend(bcm);
3097 if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3098 if (0 /*TODO: bunch of conditions*/) {
3099 bcm43xx_radio_set_interference_mitigation(bcm,
3100 BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3101 }
3102 } else if (1/*TODO*/) {
3103 /*
3104 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3105 bcm43xx_radio_set_interference_mitigation(bcm,
3106 BCM43xx_RADIO_INTERFMODE_NONE);
3107 }
3108 */
3109 }
3110 bcm43xx_mac_enable(bcm);
3111 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3112 phy->rev == 1) {
3113 //TODO: implement rev1 workaround
3114 }
3115 }
3116 bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3117 //TODO for APHY (temperature?)
3118 }
3119
3120 static void do_periodic_work(struct bcm43xx_private *bcm)
3121 {
3122 unsigned int state;
3123
3124 state = bcm->periodic_state;
3125 if (state % 8 == 0)
3126 bcm43xx_periodic_every120sec(bcm);
3127 if (state % 4 == 0)
3128 bcm43xx_periodic_every60sec(bcm);
3129 if (state % 2 == 0)
3130 bcm43xx_periodic_every30sec(bcm);
3131 if (state % 1 == 0)
3132 bcm43xx_periodic_every15sec(bcm);
3133 bcm->periodic_state = state + 1;
3134
3135 schedule_delayed_work(&bcm->periodic_work, HZ * 15);
3136 }
3137
3138 /* Estimate a "Badness" value based on the periodic work
3139 * state-machine state. "Badness" is worse (bigger), if the
3140 * periodic work will take longer.
3141 */
3142 static int estimate_periodic_work_badness(unsigned int state)
3143 {
3144 int badness = 0;
3145
3146 if (state % 8 == 0) /* every 120 sec */
3147 badness += 10;
3148 if (state % 4 == 0) /* every 60 sec */
3149 badness += 5;
3150 if (state % 2 == 0) /* every 30 sec */
3151 badness += 1;
3152 if (state % 1 == 0) /* every 15 sec */
3153 badness += 1;
3154
3155 #define BADNESS_LIMIT 4
3156 return badness;
3157 }
3158
3159 static void bcm43xx_periodic_work_handler(void *d)
3160 {
3161 struct bcm43xx_private *bcm = d;
3162 unsigned long flags;
3163 u32 savedirqs = 0;
3164 int badness;
3165
3166 badness = estimate_periodic_work_badness(bcm->periodic_state);
3167 if (badness > BADNESS_LIMIT) {
3168 /* Periodic work will take a long time, so we want it to
3169 * be preemtible.
3170 */
3171 mutex_lock(&bcm->mutex);
3172 netif_stop_queue(bcm->net_dev);
3173 synchronize_net();
3174 spin_lock_irqsave(&bcm->irq_lock, flags);
3175 bcm43xx_mac_suspend(bcm);
3176 if (bcm43xx_using_pio(bcm))
3177 bcm43xx_pio_freeze_txqueues(bcm);
3178 savedirqs = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3179 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3180 bcm43xx_synchronize_irq(bcm);
3181 } else {
3182 /* Periodic work should take short time, so we want low
3183 * locking overhead.
3184 */
3185 mutex_lock(&bcm->mutex);
3186 spin_lock_irqsave(&bcm->irq_lock, flags);
3187 }
3188
3189 do_periodic_work(bcm);
3190
3191 if (badness > BADNESS_LIMIT) {
3192 spin_lock_irqsave(&bcm->irq_lock, flags);
3193 tasklet_enable(&bcm->isr_tasklet);
3194 bcm43xx_interrupt_enable(bcm, savedirqs);
3195 if (bcm43xx_using_pio(bcm))
3196 bcm43xx_pio_thaw_txqueues(bcm);
3197 bcm43xx_mac_enable(bcm);
3198 netif_wake_queue(bcm->net_dev);
3199 }
3200 mmiowb();
3201 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3202 mutex_unlock(&bcm->mutex);
3203 }
3204
3205 void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
3206 {
3207 cancel_rearming_delayed_work(&bcm->periodic_work);
3208 }
3209
3210 void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
3211 {
3212 struct work_struct *work = &(bcm->periodic_work);
3213
3214 assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
3215 INIT_WORK(work, bcm43xx_periodic_work_handler, bcm);
3216 schedule_work(work);
3217 }
3218
3219 static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3220 {
3221 bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3222 0x0056) * 2;
3223 bcm43xx_clear_keys(bcm);
3224 }
3225
3226 static int bcm43xx_rng_read(struct hwrng *rng, u32 *data)
3227 {
3228 struct bcm43xx_private *bcm = (struct bcm43xx_private *)rng->priv;
3229 unsigned long flags;
3230
3231 spin_lock_irqsave(&(bcm)->irq_lock, flags);
3232 *data = bcm43xx_read16(bcm, BCM43xx_MMIO_RNG);
3233 spin_unlock_irqrestore(&(bcm)->irq_lock, flags);
3234
3235 return (sizeof(u16));
3236 }
3237
3238 static void bcm43xx_rng_exit(struct bcm43xx_private *bcm)
3239 {
3240 hwrng_unregister(&bcm->rng);
3241 }
3242
3243 static int bcm43xx_rng_init(struct bcm43xx_private *bcm)
3244 {
3245 int err;
3246
3247 snprintf(bcm->rng_name, ARRAY_SIZE(bcm->rng_name),
3248 "%s_%s", KBUILD_MODNAME, bcm->net_dev->name);
3249 bcm->rng.name = bcm->rng_name;
3250 bcm->rng.data_read = bcm43xx_rng_read;
3251 bcm->rng.priv = (unsigned long)bcm;
3252 err = hwrng_register(&bcm->rng);
3253 if (err)
3254 printk(KERN_ERR PFX "RNG init failed (%d)\n", err);
3255
3256 return err;
3257 }
3258
3259 static int bcm43xx_shutdown_all_wireless_cores(struct bcm43xx_private *bcm)
3260 {
3261 int ret = 0;
3262 int i, err;
3263 struct bcm43xx_coreinfo *core;
3264
3265 bcm43xx_set_status(bcm, BCM43xx_STAT_SHUTTINGDOWN);
3266 for (i = 0; i < bcm->nr_80211_available; i++) {
3267 core = &(bcm->core_80211[i]);
3268 assert(core->available);
3269 if (!core->initialized)
3270 continue;
3271 err = bcm43xx_switch_core(bcm, core);
3272 if (err) {
3273 dprintk(KERN_ERR PFX "shutdown_all_wireless_cores "
3274 "switch_core failed (%d)\n", err);
3275 ret = err;
3276 continue;
3277 }
3278 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3279 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
3280 bcm43xx_wireless_core_cleanup(bcm);
3281 if (core == bcm->active_80211_core)
3282 bcm->active_80211_core = NULL;
3283 }
3284 free_irq(bcm->irq, bcm);
3285 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3286
3287 return ret;
3288 }
3289
3290 /* This is the opposite of bcm43xx_init_board() */
3291 static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3292 {
3293 bcm43xx_rng_exit(bcm);
3294 bcm43xx_sysfs_unregister(bcm);
3295 bcm43xx_periodic_tasks_delete(bcm);
3296
3297 mutex_lock(&(bcm)->mutex);
3298 bcm43xx_shutdown_all_wireless_cores(bcm);
3299 bcm43xx_pctl_set_crystal(bcm, 0);
3300 mutex_unlock(&(bcm)->mutex);
3301 }
3302
3303 static void prepare_phydata_for_init(struct bcm43xx_phyinfo *phy)
3304 {
3305 phy->antenna_diversity = 0xFFFF;
3306 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3307 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3308
3309 /* Flags */
3310 phy->calibrated = 0;
3311 phy->is_locked = 0;
3312
3313 if (phy->_lo_pairs) {
3314 memset(phy->_lo_pairs, 0,
3315 sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT);
3316 }
3317 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3318 }
3319
3320 static void prepare_radiodata_for_init(struct bcm43xx_private *bcm,
3321 struct bcm43xx_radioinfo *radio)
3322 {
3323 int i;
3324
3325 /* Set default attenuation values. */
3326 radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
3327 radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
3328 radio->txctl1 = bcm43xx_default_txctl1(bcm);
3329 radio->txctl2 = 0xFFFF;
3330 radio->txpwr_offset = 0;
3331
3332 /* NRSSI */
3333 radio->nrssislope = 0;
3334 for (i = 0; i < ARRAY_SIZE(radio->nrssi); i++)
3335 radio->nrssi[i] = -1000;
3336 for (i = 0; i < ARRAY_SIZE(radio->nrssi_lt); i++)
3337 radio->nrssi_lt[i] = i;
3338
3339 radio->lofcal = 0xFFFF;
3340 radio->initval = 0xFFFF;
3341
3342 radio->aci_enable = 0;
3343 radio->aci_wlan_automatic = 0;
3344 radio->aci_hw_rssi = 0;
3345 }
3346
3347 static void prepare_priv_for_init(struct bcm43xx_private *bcm)
3348 {
3349 int i;
3350 struct bcm43xx_coreinfo *core;
3351 struct bcm43xx_coreinfo_80211 *wlext;
3352
3353 assert(!bcm->active_80211_core);
3354
3355 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3356
3357 /* Flags */
3358 bcm->was_initialized = 0;
3359 bcm->reg124_set_0x4 = 0;
3360
3361 /* Stats */
3362 memset(&bcm->stats, 0, sizeof(bcm->stats));
3363
3364 /* Wireless core data */
3365 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3366 core = &(bcm->core_80211[i]);
3367 wlext = core->priv;
3368
3369 if (!core->available)
3370 continue;
3371 assert(wlext == &(bcm->core_80211_ext[i]));
3372
3373 prepare_phydata_for_init(&wlext->phy);
3374 prepare_radiodata_for_init(bcm, &wlext->radio);
3375 }
3376
3377 /* IRQ related flags */
3378 bcm->irq_reason = 0;
3379 memset(bcm->dma_reason, 0, sizeof(bcm->dma_reason));
3380 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3381
3382 bcm->mac_suspended = 1;
3383
3384 /* Noise calculation context */
3385 memset(&bcm->noisecalc, 0, sizeof(bcm->noisecalc));
3386
3387 /* Periodic work context */
3388 bcm->periodic_state = 0;
3389 }
3390
3391 static int wireless_core_up(struct bcm43xx_private *bcm,
3392 int active_wlcore)
3393 {
3394 int err;
3395
3396 if (!bcm43xx_core_enabled(bcm))
3397 bcm43xx_wireless_core_reset(bcm, 1);
3398 if (!active_wlcore)
3399 bcm43xx_wireless_core_mark_inactive(bcm);
3400 err = bcm43xx_wireless_core_init(bcm, active_wlcore);
3401 if (err)
3402 goto out;
3403 if (!active_wlcore)
3404 bcm43xx_radio_turn_off(bcm);
3405 out:
3406 return err;
3407 }
3408
3409 /* Select and enable the "to be used" wireless core.
3410 * Locking: bcm->mutex must be aquired before calling this.
3411 * bcm->irq_lock must not be aquired.
3412 */
3413 int bcm43xx_select_wireless_core(struct bcm43xx_private *bcm,
3414 int phytype)
3415 {
3416 int i, err;
3417 struct bcm43xx_coreinfo *active_core = NULL;
3418 struct bcm43xx_coreinfo_80211 *active_wlext = NULL;
3419 struct bcm43xx_coreinfo *core;
3420 struct bcm43xx_coreinfo_80211 *wlext;
3421 int adjust_active_sbtmstatelow = 0;
3422
3423 might_sleep();
3424
3425 if (phytype < 0) {
3426 /* If no phytype is requested, select the first core. */
3427 assert(bcm->core_80211[0].available);
3428 wlext = bcm->core_80211[0].priv;
3429 phytype = wlext->phy.type;
3430 }
3431 /* Find the requested core. */
3432 for (i = 0; i < bcm->nr_80211_available; i++) {
3433 core = &(bcm->core_80211[i]);
3434 wlext = core->priv;
3435 if (wlext->phy.type == phytype) {
3436 active_core = core;
3437 active_wlext = wlext;
3438 break;
3439 }
3440 }
3441 if (!active_core)
3442 return -ESRCH; /* No such PHYTYPE on this board. */
3443
3444 if (bcm->active_80211_core) {
3445 /* We already selected a wl core in the past.
3446 * So first clean up everything.
3447 */
3448 dprintk(KERN_INFO PFX "select_wireless_core: cleanup\n");
3449 ieee80211softmac_stop(bcm->net_dev);
3450 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3451 err = bcm43xx_disable_interrupts_sync(bcm);
3452 assert(!err);
3453 tasklet_enable(&bcm->isr_tasklet);
3454 err = bcm43xx_shutdown_all_wireless_cores(bcm);
3455 if (err)
3456 goto error;
3457 /* Ok, everything down, continue to re-initialize. */
3458 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3459 }
3460
3461 /* Reset all data structures. */
3462 prepare_priv_for_init(bcm);
3463
3464 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3465 if (err)
3466 goto error;
3467
3468 /* Mark all unused cores "inactive". */
3469 for (i = 0; i < bcm->nr_80211_available; i++) {
3470 core = &(bcm->core_80211[i]);
3471 wlext = core->priv;
3472
3473 if (core == active_core)
3474 continue;
3475 err = bcm43xx_switch_core(bcm, core);
3476 if (err) {
3477 dprintk(KERN_ERR PFX "Could not switch to inactive "
3478 "802.11 core (%d)\n", err);
3479 goto error;
3480 }
3481 err = wireless_core_up(bcm, 0);
3482 if (err) {
3483 dprintk(KERN_ERR PFX "core_up for inactive 802.11 core "
3484 "failed (%d)\n", err);
3485 goto error;
3486 }
3487 adjust_active_sbtmstatelow = 1;
3488 }
3489
3490 /* Now initialize the active 802.11 core. */
3491 err = bcm43xx_switch_core(bcm, active_core);
3492 if (err) {
3493 dprintk(KERN_ERR PFX "Could not switch to active "
3494 "802.11 core (%d)\n", err);
3495 goto error;
3496 }
3497 if (adjust_active_sbtmstatelow &&
3498 active_wlext->phy.type == BCM43xx_PHYTYPE_G) {
3499 u32 sbtmstatelow;
3500
3501 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
3502 sbtmstatelow |= 0x20000000;
3503 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
3504 }
3505 err = wireless_core_up(bcm, 1);
3506 if (err) {
3507 dprintk(KERN_ERR PFX "core_up for active 802.11 core "
3508 "failed (%d)\n", err);
3509 goto error;
3510 }
3511 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
3512 if (err)
3513 goto error;
3514 bcm->active_80211_core = active_core;
3515
3516 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3517 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
3518 bcm43xx_security_init(bcm);
3519 ieee80211softmac_start(bcm->net_dev);
3520
3521 /* Let's go! Be careful after enabling the IRQs.
3522 * Don't switch cores, for example.
3523 */
3524 bcm43xx_mac_enable(bcm);
3525 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3526 err = bcm43xx_initialize_irq(bcm);
3527 if (err)
3528 goto error;
3529 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
3530
3531 dprintk(KERN_INFO PFX "Selected 802.11 core (phytype %d)\n",
3532 active_wlext->phy.type);
3533
3534 return 0;
3535
3536 error:
3537 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3538 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
3539 return err;
3540 }
3541
3542 static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3543 {
3544 int err;
3545
3546 mutex_lock(&(bcm)->mutex);
3547
3548 tasklet_enable(&bcm->isr_tasklet);
3549 err = bcm43xx_pctl_set_crystal(bcm, 1);
3550 if (err)
3551 goto err_tasklet;
3552 err = bcm43xx_pctl_init(bcm);
3553 if (err)
3554 goto err_crystal_off;
3555 err = bcm43xx_select_wireless_core(bcm, -1);
3556 if (err)
3557 goto err_crystal_off;
3558 err = bcm43xx_sysfs_register(bcm);
3559 if (err)
3560 goto err_wlshutdown;
3561 err = bcm43xx_rng_init(bcm);
3562 if (err)
3563 goto err_sysfs_unreg;
3564 bcm43xx_periodic_tasks_setup(bcm);
3565
3566 /*FIXME: This should be handled by softmac instead. */
3567 schedule_work(&bcm->softmac->associnfo.work);
3568
3569 out:
3570 mutex_unlock(&(bcm)->mutex);
3571
3572 return err;
3573
3574 err_sysfs_unreg:
3575 bcm43xx_sysfs_unregister(bcm);
3576 err_wlshutdown:
3577 bcm43xx_shutdown_all_wireless_cores(bcm);
3578 err_crystal_off:
3579 bcm43xx_pctl_set_crystal(bcm, 0);
3580 err_tasklet:
3581 tasklet_disable(&bcm->isr_tasklet);
3582 goto out;
3583 }
3584
3585 static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3586 {
3587 struct pci_dev *pci_dev = bcm->pci_dev;
3588 int i;
3589
3590 bcm43xx_chipset_detach(bcm);
3591 /* Do _not_ access the chip, after it is detached. */
3592 pci_iounmap(pci_dev, bcm->mmio_addr);
3593 pci_release_regions(pci_dev);
3594 pci_disable_device(pci_dev);
3595
3596 /* Free allocated structures/fields */
3597 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3598 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3599 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3600 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3601 }
3602 }
3603
3604 static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3605 {
3606 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3607 u16 value;
3608 u8 phy_version;
3609 u8 phy_type;
3610 u8 phy_rev;
3611 int phy_rev_ok = 1;
3612 void *p;
3613
3614 value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3615
3616 phy_version = (value & 0xF000) >> 12;
3617 phy_type = (value & 0x0F00) >> 8;
3618 phy_rev = (value & 0x000F);
3619
3620 dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
3621 phy_version, phy_type, phy_rev);
3622
3623 switch (phy_type) {
3624 case BCM43xx_PHYTYPE_A:
3625 if (phy_rev >= 4)
3626 phy_rev_ok = 0;
3627 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3628 * if we switch 80211 cores after init is done.
3629 * As we do not implement on the fly switching between
3630 * wireless cores, I will leave this as a future task.
3631 */
3632 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3633 bcm->ieee->mode = IEEE_A;
3634 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3635 IEEE80211_24GHZ_BAND;
3636 break;
3637 case BCM43xx_PHYTYPE_B:
3638 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3639 phy_rev_ok = 0;
3640 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3641 bcm->ieee->mode = IEEE_B;
3642 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3643 break;
3644 case BCM43xx_PHYTYPE_G:
3645 if (phy_rev > 7)
3646 phy_rev_ok = 0;
3647 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3648 IEEE80211_CCK_MODULATION;
3649 bcm->ieee->mode = IEEE_G;
3650 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3651 break;
3652 default:
3653 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3654 phy_type);
3655 return -ENODEV;
3656 };
3657 if (!phy_rev_ok) {
3658 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3659 phy_rev);
3660 }
3661
3662 phy->version = phy_version;
3663 phy->type = phy_type;
3664 phy->rev = phy_rev;
3665 if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3666 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3667 GFP_KERNEL);
3668 if (!p)
3669 return -ENOMEM;
3670 phy->_lo_pairs = p;
3671 }
3672
3673 return 0;
3674 }
3675
3676 static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3677 {
3678 struct pci_dev *pci_dev = bcm->pci_dev;
3679 struct net_device *net_dev = bcm->net_dev;
3680 int err;
3681 int i;
3682 u32 coremask;
3683
3684 err = pci_enable_device(pci_dev);
3685 if (err) {
3686 printk(KERN_ERR PFX "pci_enable_device() failed\n");
3687 goto out;
3688 }
3689 err = pci_request_regions(pci_dev, KBUILD_MODNAME);
3690 if (err) {
3691 printk(KERN_ERR PFX "pci_request_regions() failed\n");
3692 goto err_pci_disable;
3693 }
3694 /* enable PCI bus-mastering */
3695 pci_set_master(pci_dev);
3696 bcm->mmio_addr = pci_iomap(pci_dev, 0, ~0UL);
3697 if (!bcm->mmio_addr) {
3698 printk(KERN_ERR PFX "pci_iomap() failed\n");
3699 err = -EIO;
3700 goto err_pci_release;
3701 }
3702 net_dev->base_addr = (unsigned long)bcm->mmio_addr;
3703
3704 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3705 &bcm->board_vendor);
3706 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3707 &bcm->board_type);
3708 bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3709 &bcm->board_revision);
3710
3711 err = bcm43xx_chipset_attach(bcm);
3712 if (err)
3713 goto err_iounmap;
3714 err = bcm43xx_pctl_init(bcm);
3715 if (err)
3716 goto err_chipset_detach;
3717 err = bcm43xx_probe_cores(bcm);
3718 if (err)
3719 goto err_chipset_detach;
3720
3721 /* Attach all IO cores to the backplane. */
3722 coremask = 0;
3723 for (i = 0; i < bcm->nr_80211_available; i++)
3724 coremask |= (1 << bcm->core_80211[i].index);
3725 //FIXME: Also attach some non80211 cores?
3726 err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3727 if (err) {
3728 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3729 goto err_chipset_detach;
3730 }
3731
3732 err = bcm43xx_sprom_extract(bcm);
3733 if (err)
3734 goto err_chipset_detach;
3735 err = bcm43xx_leds_init(bcm);
3736 if (err)
3737 goto err_chipset_detach;
3738
3739 for (i = 0; i < bcm->nr_80211_available; i++) {
3740 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3741 assert(err != -ENODEV);
3742 if (err)
3743 goto err_80211_unwind;
3744
3745 /* Enable the selected wireless core.
3746 * Connect PHY only on the first core.
3747 */
3748 bcm43xx_wireless_core_reset(bcm, (i == 0));
3749
3750 err = bcm43xx_read_phyinfo(bcm);
3751 if (err && (i == 0))
3752 goto err_80211_unwind;
3753
3754 err = bcm43xx_read_radioinfo(bcm);
3755 if (err && (i == 0))
3756 goto err_80211_unwind;
3757
3758 err = bcm43xx_validate_chip(bcm);
3759 if (err && (i == 0))
3760 goto err_80211_unwind;
3761
3762 bcm43xx_radio_turn_off(bcm);
3763 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3764 if (err)
3765 goto err_80211_unwind;
3766 bcm43xx_wireless_core_disable(bcm);
3767 }
3768 err = bcm43xx_geo_init(bcm);
3769 if (err)
3770 goto err_80211_unwind;
3771 bcm43xx_pctl_set_crystal(bcm, 0);
3772
3773 /* Set the MAC address in the networking subsystem */
3774 if (is_valid_ether_addr(bcm->sprom.et1macaddr))
3775 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3776 else
3777 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3778
3779 snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3780 "Broadcom %04X", bcm->chip_id);
3781
3782 assert(err == 0);
3783 out:
3784 return err;
3785
3786 err_80211_unwind:
3787 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3788 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3789 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3790 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3791 }
3792 err_chipset_detach:
3793 bcm43xx_chipset_detach(bcm);
3794 err_iounmap:
3795 pci_iounmap(pci_dev, bcm->mmio_addr);
3796 err_pci_release:
3797 pci_release_regions(pci_dev);
3798 err_pci_disable:
3799 pci_disable_device(pci_dev);
3800 goto out;
3801 }
3802
3803 /* Do the Hardware IO operations to send the txb */
3804 static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3805 struct ieee80211_txb *txb)
3806 {
3807 int err = -ENODEV;
3808
3809 if (bcm43xx_using_pio(bcm))
3810 err = bcm43xx_pio_tx(bcm, txb);
3811 else
3812 err = bcm43xx_dma_tx(bcm, txb);
3813 bcm->net_dev->trans_start = jiffies;
3814
3815 return err;
3816 }
3817
3818 static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3819 u8 channel)
3820 {
3821 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3822 struct bcm43xx_radioinfo *radio;
3823 unsigned long flags;
3824
3825 mutex_lock(&bcm->mutex);
3826 spin_lock_irqsave(&bcm->irq_lock, flags);
3827 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
3828 bcm43xx_mac_suspend(bcm);
3829 bcm43xx_radio_selectchannel(bcm, channel, 0);
3830 bcm43xx_mac_enable(bcm);
3831 } else {
3832 radio = bcm43xx_current_radio(bcm);
3833 radio->initial_channel = channel;
3834 }
3835 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3836 mutex_unlock(&bcm->mutex);
3837 }
3838
3839 /* set_security() callback in struct ieee80211_device */
3840 static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3841 struct ieee80211_security *sec)
3842 {
3843 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3844 struct ieee80211_security *secinfo = &bcm->ieee->sec;
3845 unsigned long flags;
3846 int keyidx;
3847
3848 dprintk(KERN_INFO PFX "set security called");
3849
3850 mutex_lock(&bcm->mutex);
3851 spin_lock_irqsave(&bcm->irq_lock, flags);
3852
3853 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3854 if (sec->flags & (1<<keyidx)) {
3855 secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3856 secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3857 memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3858 }
3859
3860 if (sec->flags & SEC_ACTIVE_KEY) {
3861 secinfo->active_key = sec->active_key;
3862 dprintk(", .active_key = %d", sec->active_key);
3863 }
3864 if (sec->flags & SEC_UNICAST_GROUP) {
3865 secinfo->unicast_uses_group = sec->unicast_uses_group;
3866 dprintk(", .unicast_uses_group = %d", sec->unicast_uses_group);
3867 }
3868 if (sec->flags & SEC_LEVEL) {
3869 secinfo->level = sec->level;
3870 dprintk(", .level = %d", sec->level);
3871 }
3872 if (sec->flags & SEC_ENABLED) {
3873 secinfo->enabled = sec->enabled;
3874 dprintk(", .enabled = %d", sec->enabled);
3875 }
3876 if (sec->flags & SEC_ENCRYPT) {
3877 secinfo->encrypt = sec->encrypt;
3878 dprintk(", .encrypt = %d", sec->encrypt);
3879 }
3880 if (sec->flags & SEC_AUTH_MODE) {
3881 secinfo->auth_mode = sec->auth_mode;
3882 dprintk(", .auth_mode = %d", sec->auth_mode);
3883 }
3884 dprintk("\n");
3885 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED &&
3886 !bcm->ieee->host_encrypt) {
3887 if (secinfo->enabled) {
3888 /* upload WEP keys to hardware */
3889 char null_address[6] = { 0 };
3890 u8 algorithm = 0;
3891 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
3892 if (!(sec->flags & (1<<keyidx)))
3893 continue;
3894 switch (sec->encode_alg[keyidx]) {
3895 case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
3896 case SEC_ALG_WEP:
3897 algorithm = BCM43xx_SEC_ALGO_WEP;
3898 if (secinfo->key_sizes[keyidx] == 13)
3899 algorithm = BCM43xx_SEC_ALGO_WEP104;
3900 break;
3901 case SEC_ALG_TKIP:
3902 FIXME();
3903 algorithm = BCM43xx_SEC_ALGO_TKIP;
3904 break;
3905 case SEC_ALG_CCMP:
3906 FIXME();
3907 algorithm = BCM43xx_SEC_ALGO_AES;
3908 break;
3909 default:
3910 assert(0);
3911 break;
3912 }
3913 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
3914 bcm->key[keyidx].enabled = 1;
3915 bcm->key[keyidx].algorithm = algorithm;
3916 }
3917 } else
3918 bcm43xx_clear_keys(bcm);
3919 }
3920 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3921 mutex_unlock(&bcm->mutex);
3922 }
3923
3924 /* hard_start_xmit() callback in struct ieee80211_device */
3925 static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
3926 struct net_device *net_dev,
3927 int pri)
3928 {
3929 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3930 int err = -ENODEV;
3931 unsigned long flags;
3932
3933 spin_lock_irqsave(&bcm->irq_lock, flags);
3934 if (likely(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED))
3935 err = bcm43xx_tx(bcm, txb);
3936 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3937
3938 if (unlikely(err))
3939 return NETDEV_TX_BUSY;
3940 return NETDEV_TX_OK;
3941 }
3942
3943 static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
3944 {
3945 return &(bcm43xx_priv(net_dev)->ieee->stats);
3946 }
3947
3948 static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
3949 {
3950 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3951 unsigned long flags;
3952
3953 spin_lock_irqsave(&bcm->irq_lock, flags);
3954 bcm43xx_controller_restart(bcm, "TX timeout");
3955 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3956 }
3957
3958 #ifdef CONFIG_NET_POLL_CONTROLLER
3959 static void bcm43xx_net_poll_controller(struct net_device *net_dev)
3960 {
3961 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3962 unsigned long flags;
3963
3964 local_irq_save(flags);
3965 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED)
3966 bcm43xx_interrupt_handler(bcm->irq, bcm, NULL);
3967 local_irq_restore(flags);
3968 }
3969 #endif /* CONFIG_NET_POLL_CONTROLLER */
3970
3971 static int bcm43xx_net_open(struct net_device *net_dev)
3972 {
3973 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3974
3975 return bcm43xx_init_board(bcm);
3976 }
3977
3978 static int bcm43xx_net_stop(struct net_device *net_dev)
3979 {
3980 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3981 int err;
3982
3983 ieee80211softmac_stop(net_dev);
3984 err = bcm43xx_disable_interrupts_sync(bcm);
3985 assert(!err);
3986 bcm43xx_free_board(bcm);
3987 flush_scheduled_work();
3988
3989 return 0;
3990 }
3991
3992 static int bcm43xx_init_private(struct bcm43xx_private *bcm,
3993 struct net_device *net_dev,
3994 struct pci_dev *pci_dev)
3995 {
3996 int err;
3997
3998 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3999 bcm->ieee = netdev_priv(net_dev);
4000 bcm->softmac = ieee80211_priv(net_dev);
4001 bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
4002
4003 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
4004 bcm->mac_suspended = 1;
4005 bcm->pci_dev = pci_dev;
4006 bcm->net_dev = net_dev;
4007 bcm->bad_frames_preempt = modparam_bad_frames_preempt;
4008 spin_lock_init(&bcm->irq_lock);
4009 spin_lock_init(&bcm->leds_lock);
4010 mutex_init(&bcm->mutex);
4011 tasklet_init(&bcm->isr_tasklet,
4012 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
4013 (unsigned long)bcm);
4014 tasklet_disable_nosync(&bcm->isr_tasklet);
4015 if (modparam_pio) {
4016 bcm->__using_pio = 1;
4017 } else {
4018 err = pci_set_dma_mask(pci_dev, DMA_30BIT_MASK);
4019 err |= pci_set_consistent_dma_mask(pci_dev, DMA_30BIT_MASK);
4020 if (err) {
4021 #ifdef CONFIG_BCM43XX_PIO
4022 printk(KERN_WARNING PFX "DMA not supported. Falling back to PIO.\n");
4023 bcm->__using_pio = 1;
4024 #else
4025 printk(KERN_ERR PFX "FATAL: DMA not supported and PIO not configured. "
4026 "Recompile the driver with PIO support, please.\n");
4027 return -ENODEV;
4028 #endif /* CONFIG_BCM43XX_PIO */
4029 }
4030 }
4031 bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
4032
4033 /* default to sw encryption for now */
4034 bcm->ieee->host_build_iv = 0;
4035 bcm->ieee->host_encrypt = 1;
4036 bcm->ieee->host_decrypt = 1;
4037
4038 bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
4039 bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
4040 bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
4041 bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
4042
4043 return 0;
4044 }
4045
4046 static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
4047 const struct pci_device_id *ent)
4048 {
4049 struct net_device *net_dev;
4050 struct bcm43xx_private *bcm;
4051 int err;
4052
4053 #ifdef CONFIG_BCM947XX
4054 if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
4055 return -ENODEV;
4056 #endif
4057
4058 #ifdef DEBUG_SINGLE_DEVICE_ONLY
4059 if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
4060 return -ENODEV;
4061 #endif
4062
4063 net_dev = alloc_ieee80211softmac(sizeof(*bcm));
4064 if (!net_dev) {
4065 printk(KERN_ERR PFX
4066 "could not allocate ieee80211 device %s\n",
4067 pci_name(pdev));
4068 err = -ENOMEM;
4069 goto out;
4070 }
4071 /* initialize the net_device struct */
4072 SET_MODULE_OWNER(net_dev);
4073 SET_NETDEV_DEV(net_dev, &pdev->dev);
4074
4075 net_dev->open = bcm43xx_net_open;
4076 net_dev->stop = bcm43xx_net_stop;
4077 net_dev->get_stats = bcm43xx_net_get_stats;
4078 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
4079 #ifdef CONFIG_NET_POLL_CONTROLLER
4080 net_dev->poll_controller = bcm43xx_net_poll_controller;
4081 #endif
4082 net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
4083 net_dev->irq = pdev->irq;
4084 SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
4085
4086 /* initialize the bcm43xx_private struct */
4087 bcm = bcm43xx_priv(net_dev);
4088 memset(bcm, 0, sizeof(*bcm));
4089 err = bcm43xx_init_private(bcm, net_dev, pdev);
4090 if (err)
4091 goto err_free_netdev;
4092
4093 pci_set_drvdata(pdev, net_dev);
4094
4095 err = bcm43xx_attach_board(bcm);
4096 if (err)
4097 goto err_free_netdev;
4098
4099 err = register_netdev(net_dev);
4100 if (err) {
4101 printk(KERN_ERR PFX "Cannot register net device, "
4102 "aborting.\n");
4103 err = -ENOMEM;
4104 goto err_detach_board;
4105 }
4106
4107 bcm43xx_debugfs_add_device(bcm);
4108
4109 assert(err == 0);
4110 out:
4111 return err;
4112
4113 err_detach_board:
4114 bcm43xx_detach_board(bcm);
4115 err_free_netdev:
4116 free_ieee80211softmac(net_dev);
4117 goto out;
4118 }
4119
4120 static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
4121 {
4122 struct net_device *net_dev = pci_get_drvdata(pdev);
4123 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4124
4125 bcm43xx_debugfs_remove_device(bcm);
4126 unregister_netdev(net_dev);
4127 bcm43xx_detach_board(bcm);
4128 free_ieee80211softmac(net_dev);
4129 }
4130
4131 /* Hard-reset the chip. Do not call this directly.
4132 * Use bcm43xx_controller_restart()
4133 */
4134 static void bcm43xx_chip_reset(void *_bcm)
4135 {
4136 struct bcm43xx_private *bcm = _bcm;
4137 struct bcm43xx_phyinfo *phy;
4138 int err = -ENODEV;
4139
4140 mutex_lock(&(bcm)->mutex);
4141 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
4142 bcm43xx_periodic_tasks_delete(bcm);
4143 phy = bcm43xx_current_phy(bcm);
4144 err = bcm43xx_select_wireless_core(bcm, phy->type);
4145 if (!err)
4146 bcm43xx_periodic_tasks_setup(bcm);
4147 }
4148 mutex_unlock(&(bcm)->mutex);
4149
4150 printk(KERN_ERR PFX "Controller restart%s\n",
4151 (err == 0) ? "ed" : " failed");
4152 }
4153
4154 /* Hard-reset the chip.
4155 * This can be called from interrupt or process context.
4156 * bcm->irq_lock must be locked.
4157 */
4158 void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
4159 {
4160 if (bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)
4161 return;
4162 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
4163 INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
4164 schedule_work(&bcm->restart_work);
4165 }
4166
4167 #ifdef CONFIG_PM
4168
4169 static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
4170 {
4171 struct net_device *net_dev = pci_get_drvdata(pdev);
4172 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4173 int err;
4174
4175 dprintk(KERN_INFO PFX "Suspending...\n");
4176
4177 netif_device_detach(net_dev);
4178 bcm->was_initialized = 0;
4179 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
4180 bcm->was_initialized = 1;
4181 ieee80211softmac_stop(net_dev);
4182 err = bcm43xx_disable_interrupts_sync(bcm);
4183 if (unlikely(err)) {
4184 dprintk(KERN_ERR PFX "Suspend failed.\n");
4185 return -EAGAIN;
4186 }
4187 bcm->firmware_norelease = 1;
4188 bcm43xx_free_board(bcm);
4189 bcm->firmware_norelease = 0;
4190 }
4191 bcm43xx_chipset_detach(bcm);
4192
4193 pci_save_state(pdev);
4194 pci_disable_device(pdev);
4195 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4196
4197 dprintk(KERN_INFO PFX "Device suspended.\n");
4198
4199 return 0;
4200 }
4201
4202 static int bcm43xx_resume(struct pci_dev *pdev)
4203 {
4204 struct net_device *net_dev = pci_get_drvdata(pdev);
4205 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4206 int err = 0;
4207
4208 dprintk(KERN_INFO PFX "Resuming...\n");
4209
4210 pci_set_power_state(pdev, 0);
4211 pci_enable_device(pdev);
4212 pci_restore_state(pdev);
4213
4214 bcm43xx_chipset_attach(bcm);
4215 if (bcm->was_initialized)
4216 err = bcm43xx_init_board(bcm);
4217 if (err) {
4218 printk(KERN_ERR PFX "Resume failed!\n");
4219 return err;
4220 }
4221 netif_device_attach(net_dev);
4222
4223 dprintk(KERN_INFO PFX "Device resumed.\n");
4224
4225 return 0;
4226 }
4227
4228 #endif /* CONFIG_PM */
4229
4230 static struct pci_driver bcm43xx_pci_driver = {
4231 .name = KBUILD_MODNAME,
4232 .id_table = bcm43xx_pci_tbl,
4233 .probe = bcm43xx_init_one,
4234 .remove = __devexit_p(bcm43xx_remove_one),
4235 #ifdef CONFIG_PM
4236 .suspend = bcm43xx_suspend,
4237 .resume = bcm43xx_resume,
4238 #endif /* CONFIG_PM */
4239 };
4240
4241 static int __init bcm43xx_init(void)
4242 {
4243 printk(KERN_INFO KBUILD_MODNAME " driver\n");
4244 bcm43xx_debugfs_init();
4245 return pci_register_driver(&bcm43xx_pci_driver);
4246 }
4247
4248 static void __exit bcm43xx_exit(void)
4249 {
4250 pci_unregister_driver(&bcm43xx_pci_driver);
4251 bcm43xx_debugfs_exit();
4252 }
4253
4254 module_init(bcm43xx_init)
4255 module_exit(bcm43xx_exit)
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