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brcmsmac: Reduce number of entries in tx DMA rings
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1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
24 #include <aiutils.h>
25 #include <chipcommon.h>
26 #include "rate.h"
27 #include "scb.h"
28 #include "phy/phy_hal.h"
29 #include "channel.h"
30 #include "antsel.h"
31 #include "stf.h"
32 #include "ampdu.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
35 #include "main.h"
36 #include "soc.h"
37 #include "dma.h"
38
39 /* watchdog timer, in unit of ms */
40 #define TIMER_INTERVAL_WATCHDOG 1000
41 /* radio monitor timer, in unit of ms */
42 #define TIMER_INTERVAL_RADIOCHK 800
43
44 /* beacon interval, in unit of 1024TU */
45 #define BEACON_INTERVAL_DEFAULT 100
46
47 /* n-mode support capability */
48 /* 2x2 includes both 1x1 & 2x2 devices
49 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
50 * control it independently
51 */
52 #define WL_11N_2x2 1
53 #define WL_11N_3x3 3
54 #define WL_11N_4x4 4
55
56 #define EDCF_ACI_MASK 0x60
57 #define EDCF_ACI_SHIFT 5
58 #define EDCF_ECWMIN_MASK 0x0f
59 #define EDCF_ECWMAX_SHIFT 4
60 #define EDCF_AIFSN_MASK 0x0f
61 #define EDCF_AIFSN_MAX 15
62 #define EDCF_ECWMAX_MASK 0xf0
63
64 #define EDCF_AC_BE_TXOP_STA 0x0000
65 #define EDCF_AC_BK_TXOP_STA 0x0000
66 #define EDCF_AC_VO_ACI_STA 0x62
67 #define EDCF_AC_VO_ECW_STA 0x32
68 #define EDCF_AC_VI_ACI_STA 0x42
69 #define EDCF_AC_VI_ECW_STA 0x43
70 #define EDCF_AC_BK_ECW_STA 0xA4
71 #define EDCF_AC_VI_TXOP_STA 0x005e
72 #define EDCF_AC_VO_TXOP_STA 0x002f
73 #define EDCF_AC_BE_ACI_STA 0x03
74 #define EDCF_AC_BE_ECW_STA 0xA4
75 #define EDCF_AC_BK_ACI_STA 0x27
76 #define EDCF_AC_VO_TXOP_AP 0x002f
77
78 #define EDCF_TXOP2USEC(txop) ((txop) << 5)
79 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
80
81 #define APHY_SYMBOL_TIME 4
82 #define APHY_PREAMBLE_TIME 16
83 #define APHY_SIGNAL_TIME 4
84 #define APHY_SIFS_TIME 16
85 #define APHY_SERVICE_NBITS 16
86 #define APHY_TAIL_NBITS 6
87 #define BPHY_SIFS_TIME 10
88 #define BPHY_PLCP_SHORT_TIME 96
89
90 #define PREN_PREAMBLE 24
91 #define PREN_MM_EXT 12
92 #define PREN_PREAMBLE_EXT 4
93
94 #define DOT11_MAC_HDR_LEN 24
95 #define DOT11_ACK_LEN 10
96 #define DOT11_BA_LEN 4
97 #define DOT11_OFDM_SIGNAL_EXTENSION 6
98 #define DOT11_MIN_FRAG_LEN 256
99 #define DOT11_RTS_LEN 16
100 #define DOT11_CTS_LEN 10
101 #define DOT11_BA_BITMAP_LEN 128
102 #define DOT11_MIN_BEACON_PERIOD 1
103 #define DOT11_MAX_BEACON_PERIOD 0xFFFF
104 #define DOT11_MAXNUMFRAGS 16
105 #define DOT11_MAX_FRAG_LEN 2346
106
107 #define BPHY_PLCP_TIME 192
108 #define RIFS_11N_TIME 2
109
110 /* length of the BCN template area */
111 #define BCN_TMPL_LEN 512
112
113 /* brcms_bss_info flag bit values */
114 #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
115
116 /* chip rx buffer offset */
117 #define BRCMS_HWRXOFF 38
118
119 /* rfdisable delay timer 500 ms, runs of ALP clock */
120 #define RFDISABLE_DEFAULT 10000000
121
122 #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
123
124 /* precedences numbers for wlc queues. These are twice as may levels as
125 * 802.1D priorities.
126 * Odd numbers are used for HI priority traffic at same precedence levels
127 * These constants are used ONLY by wlc_prio2prec_map. Do not use them
128 * elsewhere.
129 */
130 #define _BRCMS_PREC_NONE 0 /* None = - */
131 #define _BRCMS_PREC_BK 2 /* BK - Background */
132 #define _BRCMS_PREC_BE 4 /* BE - Best-effort */
133 #define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */
134 #define _BRCMS_PREC_CL 8 /* CL - Controlled Load */
135 #define _BRCMS_PREC_VI 10 /* Vi - Video */
136 #define _BRCMS_PREC_VO 12 /* Vo - Voice */
137 #define _BRCMS_PREC_NC 14 /* NC - Network Control */
138
139 /* synthpu_dly times in us */
140 #define SYNTHPU_DLY_APHY_US 3700
141 #define SYNTHPU_DLY_BPHY_US 1050
142 #define SYNTHPU_DLY_NPHY_US 2048
143 #define SYNTHPU_DLY_LPPHY_US 300
144
145 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
146
147 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
148 #define EDCF_SHORT_S 0
149 #define EDCF_SFB_S 4
150 #define EDCF_LONG_S 8
151 #define EDCF_LFB_S 12
152 #define EDCF_SHORT_M BITFIELD_MASK(4)
153 #define EDCF_SFB_M BITFIELD_MASK(4)
154 #define EDCF_LONG_M BITFIELD_MASK(4)
155 #define EDCF_LFB_M BITFIELD_MASK(4)
156
157 #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
158 #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
159 #define RETRY_LONG_DEF 4 /* Default Long retry count */
160 #define RETRY_SHORT_FB 3 /* Short count for fb rate */
161 #define RETRY_LONG_FB 2 /* Long count for fb rate */
162
163 #define APHY_CWMIN 15
164 #define PHY_CWMAX 1023
165
166 #define EDCF_AIFSN_MIN 1
167
168 #define FRAGNUM_MASK 0xF
169
170 #define APHY_SLOT_TIME 9
171 #define BPHY_SLOT_TIME 20
172
173 #define WL_SPURAVOID_OFF 0
174 #define WL_SPURAVOID_ON1 1
175 #define WL_SPURAVOID_ON2 2
176
177 /* invalid core flags, use the saved coreflags */
178 #define BRCMS_USE_COREFLAGS 0xffffffff
179
180 /* values for PLCPHdr_override */
181 #define BRCMS_PLCP_AUTO -1
182 #define BRCMS_PLCP_SHORT 0
183 #define BRCMS_PLCP_LONG 1
184
185 /* values for g_protection_override and n_protection_override */
186 #define BRCMS_PROTECTION_AUTO -1
187 #define BRCMS_PROTECTION_OFF 0
188 #define BRCMS_PROTECTION_ON 1
189 #define BRCMS_PROTECTION_MMHDR_ONLY 2
190 #define BRCMS_PROTECTION_CTS_ONLY 3
191
192 /* values for g_protection_control and n_protection_control */
193 #define BRCMS_PROTECTION_CTL_OFF 0
194 #define BRCMS_PROTECTION_CTL_LOCAL 1
195 #define BRCMS_PROTECTION_CTL_OVERLAP 2
196
197 /* values for n_protection */
198 #define BRCMS_N_PROTECTION_OFF 0
199 #define BRCMS_N_PROTECTION_OPTIONAL 1
200 #define BRCMS_N_PROTECTION_20IN40 2
201 #define BRCMS_N_PROTECTION_MIXEDMODE 3
202
203 /* values for band specific 40MHz capabilities */
204 #define BRCMS_N_BW_20ALL 0
205 #define BRCMS_N_BW_40ALL 1
206 #define BRCMS_N_BW_20IN2G_40IN5G 2
207
208 /* bitflags for SGI support (sgi_rx iovar) */
209 #define BRCMS_N_SGI_20 0x01
210 #define BRCMS_N_SGI_40 0x02
211
212 /* defines used by the nrate iovar */
213 /* MSC in use,indicates b0-6 holds an mcs */
214 #define NRATE_MCS_INUSE 0x00000080
215 /* rate/mcs value */
216 #define NRATE_RATE_MASK 0x0000007f
217 /* stf mode mask: siso, cdd, stbc, sdm */
218 #define NRATE_STF_MASK 0x0000ff00
219 /* stf mode shift */
220 #define NRATE_STF_SHIFT 8
221 /* bit indicate to override mcs only */
222 #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
223 #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
224 #define NRATE_SGI_SHIFT 23 /* sgi mode */
225 #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
226 #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
227
228 #define NRATE_STF_SISO 0 /* stf mode SISO */
229 #define NRATE_STF_CDD 1 /* stf mode CDD */
230 #define NRATE_STF_STBC 2 /* stf mode STBC */
231 #define NRATE_STF_SDM 3 /* stf mode SDM */
232
233 #define MAX_DMA_SEGS 4
234
235 /* # of entries in Tx FIFO */
236 #define NTXD 64
237 /* Max # of entries in Rx FIFO based on 4kb page size */
238 #define NRXD 256
239
240 /* Amount of headroom to leave in Tx FIFO */
241 #define TX_HEADROOM 4
242
243 /* try to keep this # rbufs posted to the chip */
244 #define NRXBUFPOST 32
245
246 /* max # frames to process in brcms_c_recv() */
247 #define RXBND 8
248 /* max # tx status to process in wlc_txstatus() */
249 #define TXSBND 8
250
251 /* brcmu_format_flags() bit description structure */
252 struct brcms_c_bit_desc {
253 u32 bit;
254 const char *name;
255 };
256
257 /*
258 * The following table lists the buffer memory allocated to xmt fifos in HW.
259 * the size is in units of 256bytes(one block), total size is HW dependent
260 * ucode has default fifo partition, sw can overwrite if necessary
261 *
262 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
263 * the twiki is updated before making changes.
264 */
265
266 /* Starting corerev for the fifo size table */
267 #define XMTFIFOTBL_STARTREV 17
268
269 struct d11init {
270 __le16 addr;
271 __le16 size;
272 __le32 value;
273 };
274
275 struct edcf_acparam {
276 u8 ACI;
277 u8 ECW;
278 u16 TXOP;
279 } __packed;
280
281 /* debug/trace */
282 uint brcm_msg_level =
283 #if defined(DEBUG)
284 LOG_ERROR_VAL;
285 #else
286 0;
287 #endif /* DEBUG */
288
289 /* TX FIFO number to WME/802.1E Access Category */
290 static const u8 wme_fifo2ac[] = {
291 IEEE80211_AC_BK,
292 IEEE80211_AC_BE,
293 IEEE80211_AC_VI,
294 IEEE80211_AC_VO,
295 IEEE80211_AC_BE,
296 IEEE80211_AC_BE
297 };
298
299 /* ieee80211 Access Category to TX FIFO number */
300 static const u8 wme_ac2fifo[] = {
301 TX_AC_VO_FIFO,
302 TX_AC_VI_FIFO,
303 TX_AC_BE_FIFO,
304 TX_AC_BK_FIFO
305 };
306
307 /* 802.1D Priority to precedence queue mapping */
308 const u8 wlc_prio2prec_map[] = {
309 _BRCMS_PREC_BE, /* 0 BE - Best-effort */
310 _BRCMS_PREC_BK, /* 1 BK - Background */
311 _BRCMS_PREC_NONE, /* 2 None = - */
312 _BRCMS_PREC_EE, /* 3 EE - Excellent-effort */
313 _BRCMS_PREC_CL, /* 4 CL - Controlled Load */
314 _BRCMS_PREC_VI, /* 5 Vi - Video */
315 _BRCMS_PREC_VO, /* 6 Vo - Voice */
316 _BRCMS_PREC_NC, /* 7 NC - Network Control */
317 };
318
319 static const u16 xmtfifo_sz[][NFIFO] = {
320 /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
321 {20, 192, 192, 21, 17, 5},
322 /* corerev 18: */
323 {0, 0, 0, 0, 0, 0},
324 /* corerev 19: */
325 {0, 0, 0, 0, 0, 0},
326 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
327 {20, 192, 192, 21, 17, 5},
328 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
329 {9, 58, 22, 14, 14, 5},
330 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
331 {20, 192, 192, 21, 17, 5},
332 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
333 {20, 192, 192, 21, 17, 5},
334 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
335 {9, 58, 22, 14, 14, 5},
336 /* corerev 25: */
337 {0, 0, 0, 0, 0, 0},
338 /* corerev 26: */
339 {0, 0, 0, 0, 0, 0},
340 /* corerev 27: */
341 {0, 0, 0, 0, 0, 0},
342 /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
343 {9, 58, 22, 14, 14, 5},
344 };
345
346 #ifdef DEBUG
347 static const char * const fifo_names[] = {
348 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
349 #else
350 static const char fifo_names[6][0];
351 #endif
352
353 #ifdef DEBUG
354 /* pointer to most recently allocated wl/wlc */
355 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
356 #endif
357
358 /* Mapping of ieee80211 AC numbers to tx fifos */
359 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
360 [IEEE80211_AC_VO] = TX_AC_VO_FIFO,
361 [IEEE80211_AC_VI] = TX_AC_VI_FIFO,
362 [IEEE80211_AC_BE] = TX_AC_BE_FIFO,
363 [IEEE80211_AC_BK] = TX_AC_BK_FIFO,
364 };
365
366 /* Mapping of tx fifos to ieee80211 AC numbers */
367 static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
368 [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
369 [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
370 [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
371 [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
372 };
373
374 static u8 brcms_ac_to_fifo(u8 ac)
375 {
376 if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
377 return TX_AC_BE_FIFO;
378 return ac_to_fifo_mapping[ac];
379 }
380
381 static u8 brcms_fifo_to_ac(u8 fifo)
382 {
383 if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
384 return IEEE80211_AC_BE;
385 return fifo_to_ac_mapping[fifo];
386 }
387
388 /* Find basic rate for a given rate */
389 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
390 {
391 if (is_mcs_rate(rspec))
392 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
393 .leg_ofdm];
394 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
395 }
396
397 static u16 frametype(u32 rspec, u8 mimoframe)
398 {
399 if (is_mcs_rate(rspec))
400 return mimoframe;
401 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
402 }
403
404 /* currently the best mechanism for determining SIFS is the band in use */
405 static u16 get_sifs(struct brcms_band *band)
406 {
407 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
408 BPHY_SIFS_TIME;
409 }
410
411 /*
412 * Detect Card removed.
413 * Even checking an sbconfig register read will not false trigger when the core
414 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
415 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
416 * reg with fixed 0/1 pattern (some platforms return all 0).
417 * If clocks are present, call the sb routine which will figure out if the
418 * device is removed.
419 */
420 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
421 {
422 u32 macctrl;
423
424 if (!wlc->hw->clk)
425 return ai_deviceremoved(wlc->hw->sih);
426 macctrl = bcma_read32(wlc->hw->d11core,
427 D11REGOFFS(maccontrol));
428 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
429 }
430
431 /* sum the individual fifo tx pending packet counts */
432 static int brcms_txpktpendtot(struct brcms_c_info *wlc)
433 {
434 int i;
435 int pending = 0;
436
437 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
438 if (wlc->hw->di[i])
439 pending += dma_txpending(wlc->hw->di[i]);
440 return pending;
441 }
442
443 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
444 {
445 return wlc->pub->_nbands > 1 && !wlc->bandlocked;
446 }
447
448 static int brcms_chspec_bw(u16 chanspec)
449 {
450 if (CHSPEC_IS40(chanspec))
451 return BRCMS_40_MHZ;
452 if (CHSPEC_IS20(chanspec))
453 return BRCMS_20_MHZ;
454
455 return BRCMS_10_MHZ;
456 }
457
458 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
459 {
460 if (cfg == NULL)
461 return;
462
463 kfree(cfg->current_bss);
464 kfree(cfg);
465 }
466
467 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
468 {
469 if (wlc == NULL)
470 return;
471
472 brcms_c_bsscfg_mfree(wlc->bsscfg);
473 kfree(wlc->pub);
474 kfree(wlc->modulecb);
475 kfree(wlc->default_bss);
476 kfree(wlc->protection);
477 kfree(wlc->stf);
478 kfree(wlc->bandstate[0]);
479 kfree(wlc->corestate->macstat_snapshot);
480 kfree(wlc->corestate);
481 kfree(wlc->hw->bandstate[0]);
482 kfree(wlc->hw);
483
484 /* free the wlc */
485 kfree(wlc);
486 wlc = NULL;
487 }
488
489 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
490 {
491 struct brcms_bss_cfg *cfg;
492
493 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
494 if (cfg == NULL)
495 goto fail;
496
497 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
498 if (cfg->current_bss == NULL)
499 goto fail;
500
501 return cfg;
502
503 fail:
504 brcms_c_bsscfg_mfree(cfg);
505 return NULL;
506 }
507
508 static struct brcms_c_info *
509 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
510 {
511 struct brcms_c_info *wlc;
512
513 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
514 if (wlc == NULL) {
515 *err = 1002;
516 goto fail;
517 }
518
519 /* allocate struct brcms_c_pub state structure */
520 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
521 if (wlc->pub == NULL) {
522 *err = 1003;
523 goto fail;
524 }
525 wlc->pub->wlc = wlc;
526
527 /* allocate struct brcms_hardware state structure */
528
529 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
530 if (wlc->hw == NULL) {
531 *err = 1005;
532 goto fail;
533 }
534 wlc->hw->wlc = wlc;
535
536 wlc->hw->bandstate[0] =
537 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
538 if (wlc->hw->bandstate[0] == NULL) {
539 *err = 1006;
540 goto fail;
541 } else {
542 int i;
543
544 for (i = 1; i < MAXBANDS; i++)
545 wlc->hw->bandstate[i] = (struct brcms_hw_band *)
546 ((unsigned long)wlc->hw->bandstate[0] +
547 (sizeof(struct brcms_hw_band) * i));
548 }
549
550 wlc->modulecb =
551 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
552 if (wlc->modulecb == NULL) {
553 *err = 1009;
554 goto fail;
555 }
556
557 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
558 if (wlc->default_bss == NULL) {
559 *err = 1010;
560 goto fail;
561 }
562
563 wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
564 if (wlc->bsscfg == NULL) {
565 *err = 1011;
566 goto fail;
567 }
568
569 wlc->protection = kzalloc(sizeof(struct brcms_protection),
570 GFP_ATOMIC);
571 if (wlc->protection == NULL) {
572 *err = 1016;
573 goto fail;
574 }
575
576 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
577 if (wlc->stf == NULL) {
578 *err = 1017;
579 goto fail;
580 }
581
582 wlc->bandstate[0] =
583 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
584 if (wlc->bandstate[0] == NULL) {
585 *err = 1025;
586 goto fail;
587 } else {
588 int i;
589
590 for (i = 1; i < MAXBANDS; i++)
591 wlc->bandstate[i] = (struct brcms_band *)
592 ((unsigned long)wlc->bandstate[0]
593 + (sizeof(struct brcms_band)*i));
594 }
595
596 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
597 if (wlc->corestate == NULL) {
598 *err = 1026;
599 goto fail;
600 }
601
602 wlc->corestate->macstat_snapshot =
603 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
604 if (wlc->corestate->macstat_snapshot == NULL) {
605 *err = 1027;
606 goto fail;
607 }
608
609 return wlc;
610
611 fail:
612 brcms_c_detach_mfree(wlc);
613 return NULL;
614 }
615
616 /*
617 * Update the slot timing for standard 11b/g (20us slots)
618 * or shortslot 11g (9us slots)
619 * The PSM needs to be suspended for this call.
620 */
621 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
622 bool shortslot)
623 {
624 struct bcma_device *core = wlc_hw->d11core;
625
626 if (shortslot) {
627 /* 11g short slot: 11a timing */
628 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
629 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
630 } else {
631 /* 11g long slot: 11b timing */
632 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
633 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
634 }
635 }
636
637 /*
638 * calculate frame duration of a given rate and length, return
639 * time in usec unit
640 */
641 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
642 u8 preamble_type, uint mac_len)
643 {
644 uint nsyms, dur = 0, Ndps, kNdps;
645 uint rate = rspec2rate(ratespec);
646
647 if (rate == 0) {
648 wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n",
649 wlc->pub->unit);
650 rate = BRCM_RATE_1M;
651 }
652
653 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
654 wlc->pub->unit, ratespec, preamble_type, mac_len);
655
656 if (is_mcs_rate(ratespec)) {
657 uint mcs = ratespec & RSPEC_RATE_MASK;
658 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
659
660 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
661 if (preamble_type == BRCMS_MM_PREAMBLE)
662 dur += PREN_MM_EXT;
663 /* 1000Ndbps = kbps * 4 */
664 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
665 rspec_issgi(ratespec)) * 4;
666
667 if (rspec_stc(ratespec) == 0)
668 nsyms =
669 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
670 APHY_TAIL_NBITS) * 1000, kNdps);
671 else
672 /* STBC needs to have even number of symbols */
673 nsyms =
674 2 *
675 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
676 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
677
678 dur += APHY_SYMBOL_TIME * nsyms;
679 if (wlc->band->bandtype == BRCM_BAND_2G)
680 dur += DOT11_OFDM_SIGNAL_EXTENSION;
681 } else if (is_ofdm_rate(rate)) {
682 dur = APHY_PREAMBLE_TIME;
683 dur += APHY_SIGNAL_TIME;
684 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
685 Ndps = rate * 2;
686 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
687 nsyms =
688 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
689 Ndps);
690 dur += APHY_SYMBOL_TIME * nsyms;
691 if (wlc->band->bandtype == BRCM_BAND_2G)
692 dur += DOT11_OFDM_SIGNAL_EXTENSION;
693 } else {
694 /*
695 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
696 * will divide out
697 */
698 mac_len = mac_len * 8 * 2;
699 /* calc ceiling of bits/rate = microseconds of air time */
700 dur = (mac_len + rate - 1) / rate;
701 if (preamble_type & BRCMS_SHORT_PREAMBLE)
702 dur += BPHY_PLCP_SHORT_TIME;
703 else
704 dur += BPHY_PLCP_TIME;
705 }
706 return dur;
707 }
708
709 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
710 const struct d11init *inits)
711 {
712 struct bcma_device *core = wlc_hw->d11core;
713 int i;
714 uint offset;
715 u16 size;
716 u32 value;
717
718 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
719
720 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
721 size = le16_to_cpu(inits[i].size);
722 offset = le16_to_cpu(inits[i].addr);
723 value = le32_to_cpu(inits[i].value);
724 if (size == 2)
725 bcma_write16(core, offset, value);
726 else if (size == 4)
727 bcma_write32(core, offset, value);
728 else
729 break;
730 }
731 }
732
733 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
734 {
735 u8 idx;
736 u16 addr[] = {
737 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
738 M_HOST_FLAGS5
739 };
740
741 for (idx = 0; idx < MHFMAX; idx++)
742 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
743 }
744
745 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
746 {
747 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
748 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
749
750 /* init microcode host flags */
751 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
752
753 /* do band-specific ucode IHR, SHM, and SCR inits */
754 if (D11REV_IS(wlc_hw->corerev, 23)) {
755 if (BRCMS_ISNPHY(wlc_hw->band))
756 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
757 else
758 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
759 " %d\n", __func__, wlc_hw->unit,
760 wlc_hw->corerev);
761 } else {
762 if (D11REV_IS(wlc_hw->corerev, 24)) {
763 if (BRCMS_ISLCNPHY(wlc_hw->band))
764 brcms_c_write_inits(wlc_hw,
765 ucode->d11lcn0bsinitvals24);
766 else
767 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
768 " core rev %d\n", __func__,
769 wlc_hw->unit, wlc_hw->corerev);
770 } else {
771 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
772 __func__, wlc_hw->unit, wlc_hw->corerev);
773 }
774 }
775 }
776
777 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
778 {
779 struct bcma_device *core = wlc_hw->d11core;
780 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
781
782 bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
783 }
784
785 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
786 {
787 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
788
789 wlc_hw->phyclk = clk;
790
791 if (OFF == clk) { /* clear gmode bit, put phy into reset */
792
793 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
794 (SICF_PRST | SICF_FGC));
795 udelay(1);
796 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
797 udelay(1);
798
799 } else { /* take phy out of reset */
800
801 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
802 udelay(1);
803 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
804 udelay(1);
805
806 }
807 }
808
809 /* low-level band switch utility routine */
810 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
811 {
812 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
813 bandunit);
814
815 wlc_hw->band = wlc_hw->bandstate[bandunit];
816
817 /*
818 * BMAC_NOTE:
819 * until we eliminate need for wlc->band refs in low level code
820 */
821 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
822
823 /* set gmode core flag */
824 if (wlc_hw->sbclk && !wlc_hw->noreset) {
825 u32 gmode = 0;
826
827 if (bandunit == 0)
828 gmode = SICF_GMODE;
829
830 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
831 }
832 }
833
834 /* switch to new band but leave it inactive */
835 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
836 {
837 struct brcms_hardware *wlc_hw = wlc->hw;
838 u32 macintmask;
839 u32 macctrl;
840
841 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
842 macctrl = bcma_read32(wlc_hw->d11core,
843 D11REGOFFS(maccontrol));
844 WARN_ON((macctrl & MCTL_EN_MAC) != 0);
845
846 /* disable interrupts */
847 macintmask = brcms_intrsoff(wlc->wl);
848
849 /* radio off */
850 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
851
852 brcms_b_core_phy_clk(wlc_hw, OFF);
853
854 brcms_c_setxband(wlc_hw, bandunit);
855
856 return macintmask;
857 }
858
859 /* process an individual struct tx_status */
860 static bool
861 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
862 {
863 struct sk_buff *p = NULL;
864 uint queue = NFIFO;
865 struct dma_pub *dma = NULL;
866 struct d11txh *txh;
867 struct scb *scb = NULL;
868 bool free_pdu;
869 int tx_rts, tx_frame_count, tx_rts_count;
870 uint totlen, supr_status;
871 bool lastframe;
872 struct ieee80211_hdr *h;
873 u16 mcl;
874 struct ieee80211_tx_info *tx_info;
875 struct ieee80211_tx_rate *txrate;
876 int i;
877 bool fatal = true;
878
879 /* discard intermediate indications for ucode with one legitimate case:
880 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
881 * but the subsequent tx of DATA failed. so it will start rts/cts
882 * from the beginning (resetting the rts transmission count)
883 */
884 if (!(txs->status & TX_STATUS_AMPDU)
885 && (txs->status & TX_STATUS_INTERMEDIATE)) {
886 BCMMSG(wlc->wiphy, "INTERMEDIATE but not AMPDU\n");
887 fatal = false;
888 goto out;
889 }
890
891 queue = txs->frameid & TXFID_QUEUE_MASK;
892 if (queue >= NFIFO)
893 goto out;
894
895 dma = wlc->hw->di[queue];
896
897 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
898 if (p == NULL)
899 goto out;
900
901 txh = (struct d11txh *) (p->data);
902 mcl = le16_to_cpu(txh->MacTxControlLow);
903
904 if (txs->phyerr) {
905 if (brcm_msg_level & LOG_ERROR_VAL) {
906 wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n",
907 txs->phyerr, txh->MainRates);
908 brcms_c_print_txdesc(txh);
909 }
910 brcms_c_print_txstatus(txs);
911 }
912
913 if (txs->frameid != le16_to_cpu(txh->TxFrameID))
914 goto out;
915 tx_info = IEEE80211_SKB_CB(p);
916 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
917
918 if (tx_info->rate_driver_data[0])
919 scb = &wlc->pri_scb;
920
921 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
922 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
923 fatal = false;
924 goto out;
925 }
926
927 supr_status = txs->status & TX_STATUS_SUPR_MASK;
928 if (supr_status == TX_STATUS_SUPR_BADCH)
929 BCMMSG(wlc->wiphy,
930 "%s: Pkt tx suppressed, possibly channel %d\n",
931 __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
932
933 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
934 tx_frame_count =
935 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
936 tx_rts_count =
937 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
938
939 lastframe = !ieee80211_has_morefrags(h->frame_control);
940
941 if (!lastframe) {
942 wiphy_err(wlc->wiphy, "Not last frame!\n");
943 } else {
944 /*
945 * Set information to be consumed by Minstrel ht.
946 *
947 * The "fallback limit" is the number of tx attempts a given
948 * MPDU is sent at the "primary" rate. Tx attempts beyond that
949 * limit are sent at the "secondary" rate.
950 * A 'short frame' does not exceed RTS treshold.
951 */
952 u16 sfbl, /* Short Frame Rate Fallback Limit */
953 lfbl, /* Long Frame Rate Fallback Limit */
954 fbl;
955
956 if (queue < IEEE80211_NUM_ACS) {
957 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
958 EDCF_SFB);
959 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
960 EDCF_LFB);
961 } else {
962 sfbl = wlc->SFBL;
963 lfbl = wlc->LFBL;
964 }
965
966 txrate = tx_info->status.rates;
967 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
968 fbl = lfbl;
969 else
970 fbl = sfbl;
971
972 ieee80211_tx_info_clear_status(tx_info);
973
974 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
975 /*
976 * rate selection requested a fallback rate
977 * and we used it
978 */
979 txrate[0].count = fbl;
980 txrate[1].count = tx_frame_count - fbl;
981 } else {
982 /*
983 * rate selection did not request fallback rate, or
984 * we didn't need it
985 */
986 txrate[0].count = tx_frame_count;
987 /*
988 * rc80211_minstrel.c:minstrel_tx_status() expects
989 * unused rates to be marked with idx = -1
990 */
991 txrate[1].idx = -1;
992 txrate[1].count = 0;
993 }
994
995 /* clear the rest of the rates */
996 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
997 txrate[i].idx = -1;
998 txrate[i].count = 0;
999 }
1000
1001 if (txs->status & TX_STATUS_ACK_RCV)
1002 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1003 }
1004
1005 totlen = p->len;
1006 free_pdu = true;
1007
1008 if (lastframe) {
1009 /* remove PLCP & Broadcom tx descriptor header */
1010 skb_pull(p, D11_PHY_HDR_LEN);
1011 skb_pull(p, D11_TXH_LEN);
1012 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
1013 } else {
1014 wiphy_err(wlc->wiphy, "%s: Not last frame => not calling "
1015 "tx_status\n", __func__);
1016 }
1017
1018 fatal = false;
1019
1020 out:
1021 if (fatal && p)
1022 brcmu_pkt_buf_free_skb(p);
1023
1024 if (dma && queue < NFIFO) {
1025 u16 ac_queue = brcms_fifo_to_ac(queue);
1026 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1027 ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1028 ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1029 dma_kick_tx(dma);
1030 }
1031
1032 return fatal;
1033 }
1034
1035 /* process tx completion events in BMAC
1036 * Return true if more tx status need to be processed. false otherwise.
1037 */
1038 static bool
1039 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1040 {
1041 bool morepending = false;
1042 struct brcms_c_info *wlc = wlc_hw->wlc;
1043 struct bcma_device *core;
1044 struct tx_status txstatus, *txs;
1045 u32 s1, s2;
1046 uint n = 0;
1047 /*
1048 * Param 'max_tx_num' indicates max. # tx status to process before
1049 * break out.
1050 */
1051 uint max_tx_num = bound ? TXSBND : -1;
1052
1053 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
1054
1055 txs = &txstatus;
1056 core = wlc_hw->d11core;
1057 *fatal = false;
1058 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1059 while (!(*fatal)
1060 && (s1 & TXS_V)) {
1061
1062 if (s1 == 0xffffffff) {
1063 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
1064 wlc_hw->unit, __func__);
1065 return morepending;
1066 }
1067 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1068
1069 txs->status = s1 & TXS_STATUS_MASK;
1070 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1071 txs->sequence = s2 & TXS_SEQ_MASK;
1072 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1073 txs->lasttxtime = 0;
1074
1075 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1076
1077 /* !give others some time to run! */
1078 if (++n >= max_tx_num)
1079 break;
1080 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1081 }
1082
1083 if (*fatal)
1084 return 0;
1085
1086 if (n >= max_tx_num)
1087 morepending = true;
1088
1089 return morepending;
1090 }
1091
1092 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1093 {
1094 if (!wlc->bsscfg->BSS)
1095 /*
1096 * DirFrmQ is now valid...defer setting until end
1097 * of ATIM window
1098 */
1099 wlc->qvalid |= MCMD_DIRFRMQVAL;
1100 }
1101
1102 /* set initial host flags value */
1103 static void
1104 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1105 {
1106 struct brcms_hardware *wlc_hw = wlc->hw;
1107
1108 memset(mhfs, 0, MHFMAX * sizeof(u16));
1109
1110 mhfs[MHF2] |= mhf2_init;
1111
1112 /* prohibit use of slowclock on multifunction boards */
1113 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1114 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1115
1116 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1117 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1118 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1119 }
1120 }
1121
1122 static uint
1123 dmareg(uint direction, uint fifonum)
1124 {
1125 if (direction == DMA_TX)
1126 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1127 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1128 }
1129
1130 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1131 {
1132 uint i;
1133 char name[8];
1134 /*
1135 * ucode host flag 2 needed for pio mode, independent of band and fifo
1136 */
1137 u16 pio_mhf2 = 0;
1138 struct brcms_hardware *wlc_hw = wlc->hw;
1139 uint unit = wlc_hw->unit;
1140 struct wiphy *wiphy = wlc->wiphy;
1141
1142 /* name and offsets for dma_attach */
1143 snprintf(name, sizeof(name), "wl%d", unit);
1144
1145 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
1146 int dma_attach_err = 0;
1147
1148 /*
1149 * FIFO 0
1150 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1151 * RX: RX_FIFO (RX data packets)
1152 */
1153 wlc_hw->di[0] = dma_attach(name, wlc,
1154 (wme ? dmareg(DMA_TX, 0) : 0),
1155 dmareg(DMA_RX, 0),
1156 (wme ? NTXD : 0), NRXD,
1157 RXBUFSZ, -1, NRXBUFPOST,
1158 BRCMS_HWRXOFF, &brcm_msg_level);
1159 dma_attach_err |= (NULL == wlc_hw->di[0]);
1160
1161 /*
1162 * FIFO 1
1163 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1164 * (legacy) TX_DATA_FIFO (TX data packets)
1165 * RX: UNUSED
1166 */
1167 wlc_hw->di[1] = dma_attach(name, wlc,
1168 dmareg(DMA_TX, 1), 0,
1169 NTXD, 0, 0, -1, 0, 0,
1170 &brcm_msg_level);
1171 dma_attach_err |= (NULL == wlc_hw->di[1]);
1172
1173 /*
1174 * FIFO 2
1175 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1176 * RX: UNUSED
1177 */
1178 wlc_hw->di[2] = dma_attach(name, wlc,
1179 dmareg(DMA_TX, 2), 0,
1180 NTXD, 0, 0, -1, 0, 0,
1181 &brcm_msg_level);
1182 dma_attach_err |= (NULL == wlc_hw->di[2]);
1183 /*
1184 * FIFO 3
1185 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1186 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1187 */
1188 wlc_hw->di[3] = dma_attach(name, wlc,
1189 dmareg(DMA_TX, 3),
1190 0, NTXD, 0, 0, -1,
1191 0, 0, &brcm_msg_level);
1192 dma_attach_err |= (NULL == wlc_hw->di[3]);
1193 /* Cleaner to leave this as if with AP defined */
1194
1195 if (dma_attach_err) {
1196 wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
1197 "\n", unit);
1198 return false;
1199 }
1200
1201 /* get pointer to dma engine tx flow control variable */
1202 for (i = 0; i < NFIFO; i++)
1203 if (wlc_hw->di[i])
1204 wlc_hw->txavail[i] =
1205 (uint *) dma_getvar(wlc_hw->di[i],
1206 "&txavail");
1207 }
1208
1209 /* initial ucode host flags */
1210 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1211
1212 return true;
1213 }
1214
1215 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1216 {
1217 uint j;
1218
1219 for (j = 0; j < NFIFO; j++) {
1220 if (wlc_hw->di[j]) {
1221 dma_detach(wlc_hw->di[j]);
1222 wlc_hw->di[j] = NULL;
1223 }
1224 }
1225 }
1226
1227 /*
1228 * Initialize brcms_c_info default values ...
1229 * may get overrides later in this function
1230 * BMAC_NOTES, move low out and resolve the dangling ones
1231 */
1232 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1233 {
1234 struct brcms_c_info *wlc = wlc_hw->wlc;
1235
1236 /* set default sw macintmask value */
1237 wlc->defmacintmask = DEF_MACINTMASK;
1238
1239 /* various 802.11g modes */
1240 wlc_hw->shortslot = false;
1241
1242 wlc_hw->SFBL = RETRY_SHORT_FB;
1243 wlc_hw->LFBL = RETRY_LONG_FB;
1244
1245 /* default mac retry limits */
1246 wlc_hw->SRL = RETRY_SHORT_DEF;
1247 wlc_hw->LRL = RETRY_LONG_DEF;
1248 wlc_hw->chanspec = ch20mhz_chspec(1);
1249 }
1250
1251 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1252 {
1253 /* delay before first read of ucode state */
1254 udelay(40);
1255
1256 /* wait until ucode is no longer asleep */
1257 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1258 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1259 }
1260
1261 /* control chip clock to save power, enable dynamic clock or force fast clock */
1262 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1263 {
1264 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1265 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1266 * on backplane, but mac core will still run on ALP(not HT) when
1267 * it enters powersave mode, which means the FCA bit may not be
1268 * set. Should wakeup mac if driver wants it to run on HT.
1269 */
1270
1271 if (wlc_hw->clk) {
1272 if (mode == BCMA_CLKMODE_FAST) {
1273 bcma_set32(wlc_hw->d11core,
1274 D11REGOFFS(clk_ctl_st),
1275 CCS_FORCEHT);
1276
1277 udelay(64);
1278
1279 SPINWAIT(
1280 ((bcma_read32(wlc_hw->d11core,
1281 D11REGOFFS(clk_ctl_st)) &
1282 CCS_HTAVAIL) == 0),
1283 PMU_MAX_TRANSITION_DLY);
1284 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1285 D11REGOFFS(clk_ctl_st)) &
1286 CCS_HTAVAIL));
1287 } else {
1288 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1289 (bcma_read32(wlc_hw->d11core,
1290 D11REGOFFS(clk_ctl_st)) &
1291 (CCS_FORCEHT | CCS_HTAREQ)))
1292 SPINWAIT(
1293 ((bcma_read32(wlc_hw->d11core,
1294 offsetof(struct d11regs,
1295 clk_ctl_st)) &
1296 CCS_HTAVAIL) == 0),
1297 PMU_MAX_TRANSITION_DLY);
1298 bcma_mask32(wlc_hw->d11core,
1299 D11REGOFFS(clk_ctl_st),
1300 ~CCS_FORCEHT);
1301 }
1302 }
1303 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1304 } else {
1305
1306 /* old chips w/o PMU, force HT through cc,
1307 * then use FCA to verify mac is running fast clock
1308 */
1309
1310 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1311
1312 /* check fast clock is available (if core is not in reset) */
1313 if (wlc_hw->forcefastclk && wlc_hw->clk)
1314 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1315 SISF_FCLKA));
1316
1317 /*
1318 * keep the ucode wake bit on if forcefastclk is on since we
1319 * do not want ucode to put us back to slow clock when it dozes
1320 * for PM mode. Code below matches the wake override bit with
1321 * current forcefastclk state. Only setting bit in wake_override
1322 * instead of waking ucode immediately since old code had this
1323 * behavior. Older code set wlc->forcefastclk but only had the
1324 * wake happen if the wakup_ucode work (protected by an up
1325 * check) was executed just below.
1326 */
1327 if (wlc_hw->forcefastclk)
1328 mboolset(wlc_hw->wake_override,
1329 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1330 else
1331 mboolclr(wlc_hw->wake_override,
1332 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1333 }
1334 }
1335
1336 /* set or clear ucode host flag bits
1337 * it has an optimization for no-change write
1338 * it only writes through shared memory when the core has clock;
1339 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1340 *
1341 *
1342 * bands values are: BRCM_BAND_AUTO <--- Current band only
1343 * BRCM_BAND_5G <--- 5G band only
1344 * BRCM_BAND_2G <--- 2G band only
1345 * BRCM_BAND_ALL <--- All bands
1346 */
1347 void
1348 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1349 int bands)
1350 {
1351 u16 save;
1352 u16 addr[MHFMAX] = {
1353 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1354 M_HOST_FLAGS5
1355 };
1356 struct brcms_hw_band *band;
1357
1358 if ((val & ~mask) || idx >= MHFMAX)
1359 return; /* error condition */
1360
1361 switch (bands) {
1362 /* Current band only or all bands,
1363 * then set the band to current band
1364 */
1365 case BRCM_BAND_AUTO:
1366 case BRCM_BAND_ALL:
1367 band = wlc_hw->band;
1368 break;
1369 case BRCM_BAND_5G:
1370 band = wlc_hw->bandstate[BAND_5G_INDEX];
1371 break;
1372 case BRCM_BAND_2G:
1373 band = wlc_hw->bandstate[BAND_2G_INDEX];
1374 break;
1375 default:
1376 band = NULL; /* error condition */
1377 }
1378
1379 if (band) {
1380 save = band->mhfs[idx];
1381 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1382
1383 /* optimization: only write through if changed, and
1384 * changed band is the current band
1385 */
1386 if (wlc_hw->clk && (band->mhfs[idx] != save)
1387 && (band == wlc_hw->band))
1388 brcms_b_write_shm(wlc_hw, addr[idx],
1389 (u16) band->mhfs[idx]);
1390 }
1391
1392 if (bands == BRCM_BAND_ALL) {
1393 wlc_hw->bandstate[0]->mhfs[idx] =
1394 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1395 wlc_hw->bandstate[1]->mhfs[idx] =
1396 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1397 }
1398 }
1399
1400 /* set the maccontrol register to desired reset state and
1401 * initialize the sw cache of the register
1402 */
1403 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1404 {
1405 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1406 wlc_hw->maccontrol = 0;
1407 wlc_hw->suspended_fifos = 0;
1408 wlc_hw->wake_override = 0;
1409 wlc_hw->mute_override = 0;
1410 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1411 }
1412
1413 /*
1414 * write the software state of maccontrol and
1415 * overrides to the maccontrol register
1416 */
1417 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1418 {
1419 u32 maccontrol = wlc_hw->maccontrol;
1420
1421 /* OR in the wake bit if overridden */
1422 if (wlc_hw->wake_override)
1423 maccontrol |= MCTL_WAKE;
1424
1425 /* set AP and INFRA bits for mute if needed */
1426 if (wlc_hw->mute_override) {
1427 maccontrol &= ~(MCTL_AP);
1428 maccontrol |= MCTL_INFRA;
1429 }
1430
1431 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1432 maccontrol);
1433 }
1434
1435 /* set or clear maccontrol bits */
1436 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1437 {
1438 u32 maccontrol;
1439 u32 new_maccontrol;
1440
1441 if (val & ~mask)
1442 return; /* error condition */
1443 maccontrol = wlc_hw->maccontrol;
1444 new_maccontrol = (maccontrol & ~mask) | val;
1445
1446 /* if the new maccontrol value is the same as the old, nothing to do */
1447 if (new_maccontrol == maccontrol)
1448 return;
1449
1450 /* something changed, cache the new value */
1451 wlc_hw->maccontrol = new_maccontrol;
1452
1453 /* write the new values with overrides applied */
1454 brcms_c_mctrl_write(wlc_hw);
1455 }
1456
1457 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1458 u32 override_bit)
1459 {
1460 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1461 mboolset(wlc_hw->wake_override, override_bit);
1462 return;
1463 }
1464
1465 mboolset(wlc_hw->wake_override, override_bit);
1466
1467 brcms_c_mctrl_write(wlc_hw);
1468 brcms_b_wait_for_wake(wlc_hw);
1469 }
1470
1471 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1472 u32 override_bit)
1473 {
1474 mboolclr(wlc_hw->wake_override, override_bit);
1475
1476 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1477 return;
1478
1479 brcms_c_mctrl_write(wlc_hw);
1480 }
1481
1482 /* When driver needs ucode to stop beaconing, it has to make sure that
1483 * MCTL_AP is clear and MCTL_INFRA is set
1484 * Mode MCTL_AP MCTL_INFRA
1485 * AP 1 1
1486 * STA 0 1 <--- This will ensure no beacons
1487 * IBSS 0 0
1488 */
1489 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1490 {
1491 wlc_hw->mute_override = 1;
1492
1493 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1494 * override, then there is no change to write
1495 */
1496 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1497 return;
1498
1499 brcms_c_mctrl_write(wlc_hw);
1500 }
1501
1502 /* Clear the override on AP and INFRA bits */
1503 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1504 {
1505 if (wlc_hw->mute_override == 0)
1506 return;
1507
1508 wlc_hw->mute_override = 0;
1509
1510 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1511 * override, then there is no change to write
1512 */
1513 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1514 return;
1515
1516 brcms_c_mctrl_write(wlc_hw);
1517 }
1518
1519 /*
1520 * Write a MAC address to the given match reg offset in the RXE match engine.
1521 */
1522 static void
1523 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1524 const u8 *addr)
1525 {
1526 struct bcma_device *core = wlc_hw->d11core;
1527 u16 mac_l;
1528 u16 mac_m;
1529 u16 mac_h;
1530
1531 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
1532 wlc_hw->unit);
1533
1534 mac_l = addr[0] | (addr[1] << 8);
1535 mac_m = addr[2] | (addr[3] << 8);
1536 mac_h = addr[4] | (addr[5] << 8);
1537
1538 /* enter the MAC addr into the RXE match registers */
1539 bcma_write16(core, D11REGOFFS(rcm_ctl),
1540 RCM_INC_DATA | match_reg_offset);
1541 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1542 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1543 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1544 }
1545
1546 void
1547 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1548 void *buf)
1549 {
1550 struct bcma_device *core = wlc_hw->d11core;
1551 u32 word;
1552 __le32 word_le;
1553 __be32 word_be;
1554 bool be_bit;
1555 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1556
1557 bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1558
1559 /* if MCTL_BIGEND bit set in mac control register,
1560 * the chip swaps data in fifo, as well as data in
1561 * template ram
1562 */
1563 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1564
1565 while (len > 0) {
1566 memcpy(&word, buf, sizeof(u32));
1567
1568 if (be_bit) {
1569 word_be = cpu_to_be32(word);
1570 word = *(u32 *)&word_be;
1571 } else {
1572 word_le = cpu_to_le32(word);
1573 word = *(u32 *)&word_le;
1574 }
1575
1576 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1577
1578 buf = (u8 *) buf + sizeof(u32);
1579 len -= sizeof(u32);
1580 }
1581 }
1582
1583 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1584 {
1585 wlc_hw->band->CWmin = newmin;
1586
1587 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1588 OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1589 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1590 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1591 }
1592
1593 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1594 {
1595 wlc_hw->band->CWmax = newmax;
1596
1597 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1598 OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1599 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1600 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1601 }
1602
1603 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1604 {
1605 bool fastclk;
1606
1607 /* request FAST clock if not on */
1608 fastclk = wlc_hw->forcefastclk;
1609 if (!fastclk)
1610 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1611
1612 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1613
1614 brcms_b_phy_reset(wlc_hw);
1615 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1616
1617 /* restore the clk */
1618 if (!fastclk)
1619 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1620 }
1621
1622 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1623 {
1624 u16 v;
1625 struct brcms_c_info *wlc = wlc_hw->wlc;
1626 /* update SYNTHPU_DLY */
1627
1628 if (BRCMS_ISLCNPHY(wlc->band))
1629 v = SYNTHPU_DLY_LPPHY_US;
1630 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1631 v = SYNTHPU_DLY_NPHY_US;
1632 else
1633 v = SYNTHPU_DLY_BPHY_US;
1634
1635 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1636 }
1637
1638 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1639 {
1640 u16 phyctl;
1641 u16 phytxant = wlc_hw->bmac_phytxant;
1642 u16 mask = PHY_TXC_ANT_MASK;
1643
1644 /* set the Probe Response frame phy control word */
1645 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1646 phyctl = (phyctl & ~mask) | phytxant;
1647 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1648
1649 /* set the Response (ACK/CTS) frame phy control word */
1650 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1651 phyctl = (phyctl & ~mask) | phytxant;
1652 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1653 }
1654
1655 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1656 u8 rate)
1657 {
1658 uint i;
1659 u8 plcp_rate = 0;
1660 struct plcp_signal_rate_lookup {
1661 u8 rate;
1662 u8 signal_rate;
1663 };
1664 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1665 const struct plcp_signal_rate_lookup rate_lookup[] = {
1666 {BRCM_RATE_6M, 0xB},
1667 {BRCM_RATE_9M, 0xF},
1668 {BRCM_RATE_12M, 0xA},
1669 {BRCM_RATE_18M, 0xE},
1670 {BRCM_RATE_24M, 0x9},
1671 {BRCM_RATE_36M, 0xD},
1672 {BRCM_RATE_48M, 0x8},
1673 {BRCM_RATE_54M, 0xC}
1674 };
1675
1676 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1677 if (rate == rate_lookup[i].rate) {
1678 plcp_rate = rate_lookup[i].signal_rate;
1679 break;
1680 }
1681 }
1682
1683 /* Find the SHM pointer to the rate table entry by looking in the
1684 * Direct-map Table
1685 */
1686 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1687 }
1688
1689 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1690 {
1691 u8 rate;
1692 u8 rates[8] = {
1693 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1694 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1695 };
1696 u16 entry_ptr;
1697 u16 pctl1;
1698 uint i;
1699
1700 if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1701 return;
1702
1703 /* walk the phy rate table and update the entries */
1704 for (i = 0; i < ARRAY_SIZE(rates); i++) {
1705 rate = rates[i];
1706
1707 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1708
1709 /* read the SHM Rate Table entry OFDM PCTL1 values */
1710 pctl1 =
1711 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1712
1713 /* modify the value */
1714 pctl1 &= ~PHY_TXC1_MODE_MASK;
1715 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1716
1717 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1718 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1719 pctl1);
1720 }
1721 }
1722
1723 /* band-specific init */
1724 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1725 {
1726 struct brcms_hardware *wlc_hw = wlc->hw;
1727
1728 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1729 wlc_hw->band->bandunit);
1730
1731 brcms_c_ucode_bsinit(wlc_hw);
1732
1733 wlc_phy_init(wlc_hw->band->pi, chanspec);
1734
1735 brcms_c_ucode_txant_set(wlc_hw);
1736
1737 /*
1738 * cwmin is band-specific, update hardware
1739 * with value for current band
1740 */
1741 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1742 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1743
1744 brcms_b_update_slot_timing(wlc_hw,
1745 wlc_hw->band->bandtype == BRCM_BAND_5G ?
1746 true : wlc_hw->shortslot);
1747
1748 /* write phytype and phyvers */
1749 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1750 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1751
1752 /*
1753 * initialize the txphyctl1 rate table since
1754 * shmem is shared between bands
1755 */
1756 brcms_upd_ofdm_pctl1_table(wlc_hw);
1757
1758 brcms_b_upd_synthpu(wlc_hw);
1759 }
1760
1761 /* Perform a soft reset of the PHY PLL */
1762 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1763 {
1764 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1765
1766 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1767 ~0, 0);
1768 udelay(1);
1769 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1770 0x4, 0);
1771 udelay(1);
1772 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1773 0x4, 4);
1774 udelay(1);
1775 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1776 0x4, 0);
1777 udelay(1);
1778 }
1779
1780 /* light way to turn on phy clock without reset for NPHY only
1781 * refer to brcms_b_core_phy_clk for full version
1782 */
1783 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1784 {
1785 /* support(necessary for NPHY and HYPHY) only */
1786 if (!BRCMS_ISNPHY(wlc_hw->band))
1787 return;
1788
1789 if (ON == clk)
1790 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1791 else
1792 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1793
1794 }
1795
1796 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1797 {
1798 if (ON == clk)
1799 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1800 else
1801 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1802 }
1803
1804 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1805 {
1806 struct brcms_phy_pub *pih = wlc_hw->band->pi;
1807 u32 phy_bw_clkbits;
1808 bool phy_in_reset = false;
1809
1810 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1811
1812 if (pih == NULL)
1813 return;
1814
1815 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1816
1817 /* Specific reset sequence required for NPHY rev 3 and 4 */
1818 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1819 NREV_LE(wlc_hw->band->phyrev, 4)) {
1820 /* Set the PHY bandwidth */
1821 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1822
1823 udelay(1);
1824
1825 /* Perform a soft reset of the PHY PLL */
1826 brcms_b_core_phypll_reset(wlc_hw);
1827
1828 /* reset the PHY */
1829 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1830 (SICF_PRST | SICF_PCLKE));
1831 phy_in_reset = true;
1832 } else {
1833 brcms_b_core_ioctl(wlc_hw,
1834 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1835 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1836 }
1837
1838 udelay(2);
1839 brcms_b_core_phy_clk(wlc_hw, ON);
1840
1841 if (pih)
1842 wlc_phy_anacore(pih, ON);
1843 }
1844
1845 /* switch to and initialize new band */
1846 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1847 u16 chanspec) {
1848 struct brcms_c_info *wlc = wlc_hw->wlc;
1849 u32 macintmask;
1850
1851 /* Enable the d11 core before accessing it */
1852 if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1853 bcma_core_enable(wlc_hw->d11core, 0);
1854 brcms_c_mctrl_reset(wlc_hw);
1855 }
1856
1857 macintmask = brcms_c_setband_inact(wlc, bandunit);
1858
1859 if (!wlc_hw->up)
1860 return;
1861
1862 brcms_b_core_phy_clk(wlc_hw, ON);
1863
1864 /* band-specific initializations */
1865 brcms_b_bsinit(wlc, chanspec);
1866
1867 /*
1868 * If there are any pending software interrupt bits,
1869 * then replace these with a harmless nonzero value
1870 * so brcms_c_dpc() will re-enable interrupts when done.
1871 */
1872 if (wlc->macintstatus)
1873 wlc->macintstatus = MI_DMAINT;
1874
1875 /* restore macintmask */
1876 brcms_intrsrestore(wlc->wl, macintmask);
1877
1878 /* ucode should still be suspended.. */
1879 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1880 MCTL_EN_MAC) != 0);
1881 }
1882
1883 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1884 {
1885
1886 /* reject unsupported corerev */
1887 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1888 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1889 wlc_hw->corerev);
1890 return false;
1891 }
1892
1893 return true;
1894 }
1895
1896 /* Validate some board info parameters */
1897 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1898 {
1899 uint boardrev = wlc_hw->boardrev;
1900
1901 /* 4 bits each for board type, major, minor, and tiny version */
1902 uint brt = (boardrev & 0xf000) >> 12;
1903 uint b0 = (boardrev & 0xf00) >> 8;
1904 uint b1 = (boardrev & 0xf0) >> 4;
1905 uint b2 = boardrev & 0xf;
1906
1907 /* voards from other vendors are always considered valid */
1908 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1909 return true;
1910
1911 /* do some boardrev sanity checks when boardvendor is Broadcom */
1912 if (boardrev == 0)
1913 return false;
1914
1915 if (boardrev <= 0xff)
1916 return true;
1917
1918 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1919 || (b2 > 9))
1920 return false;
1921
1922 return true;
1923 }
1924
1925 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1926 {
1927 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1928
1929 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1930 if (!is_zero_ether_addr(sprom->il0mac)) {
1931 memcpy(etheraddr, sprom->il0mac, 6);
1932 return;
1933 }
1934
1935 if (wlc_hw->_nbands > 1)
1936 memcpy(etheraddr, sprom->et1mac, 6);
1937 else
1938 memcpy(etheraddr, sprom->il0mac, 6);
1939 }
1940
1941 /* power both the pll and external oscillator on/off */
1942 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1943 {
1944 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
1945
1946 /*
1947 * dont power down if plldown is false or
1948 * we must poll hw radio disable
1949 */
1950 if (!want && wlc_hw->pllreq)
1951 return;
1952
1953 wlc_hw->sbclk = want;
1954 if (!wlc_hw->sbclk) {
1955 wlc_hw->clk = false;
1956 if (wlc_hw->band && wlc_hw->band->pi)
1957 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1958 }
1959 }
1960
1961 /*
1962 * Return true if radio is disabled, otherwise false.
1963 * hw radio disable signal is an external pin, users activate it asynchronously
1964 * this function could be called when driver is down and w/o clock
1965 * it operates on different registers depending on corerev and boardflag.
1966 */
1967 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1968 {
1969 bool v, clk, xtal;
1970 u32 flags = 0;
1971
1972 xtal = wlc_hw->sbclk;
1973 if (!xtal)
1974 brcms_b_xtal(wlc_hw, ON);
1975
1976 /* may need to take core out of reset first */
1977 clk = wlc_hw->clk;
1978 if (!clk) {
1979 /*
1980 * mac no longer enables phyclk automatically when driver
1981 * accesses phyreg throughput mac. This can be skipped since
1982 * only mac reg is accessed below
1983 */
1984 if (D11REV_GE(wlc_hw->corerev, 18))
1985 flags |= SICF_PCLKE;
1986
1987 /*
1988 * TODO: test suspend/resume
1989 *
1990 * AI chip doesn't restore bar0win2 on
1991 * hibernation/resume, need sw fixup
1992 */
1993
1994 bcma_core_enable(wlc_hw->d11core, flags);
1995 brcms_c_mctrl_reset(wlc_hw);
1996 }
1997
1998 v = ((bcma_read32(wlc_hw->d11core,
1999 D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
2000
2001 /* put core back into reset */
2002 if (!clk)
2003 bcma_core_disable(wlc_hw->d11core, 0);
2004
2005 if (!xtal)
2006 brcms_b_xtal(wlc_hw, OFF);
2007
2008 return v;
2009 }
2010
2011 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
2012 {
2013 struct dma_pub *di = wlc_hw->di[fifo];
2014 return dma_rxreset(di);
2015 }
2016
2017 /* d11 core reset
2018 * ensure fask clock during reset
2019 * reset dma
2020 * reset d11(out of reset)
2021 * reset phy(out of reset)
2022 * clear software macintstatus for fresh new start
2023 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2024 */
2025 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
2026 {
2027 uint i;
2028 bool fastclk;
2029
2030 if (flags == BRCMS_USE_COREFLAGS)
2031 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2032
2033 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2034
2035 /* request FAST clock if not on */
2036 fastclk = wlc_hw->forcefastclk;
2037 if (!fastclk)
2038 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2039
2040 /* reset the dma engines except first time thru */
2041 if (bcma_core_is_enabled(wlc_hw->d11core)) {
2042 for (i = 0; i < NFIFO; i++)
2043 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2044 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2045 "dma_txreset[%d]: cannot stop dma\n",
2046 wlc_hw->unit, __func__, i);
2047
2048 if ((wlc_hw->di[RX_FIFO])
2049 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2050 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2051 "[%d]: cannot stop dma\n",
2052 wlc_hw->unit, __func__, RX_FIFO);
2053 }
2054 /* if noreset, just stop the psm and return */
2055 if (wlc_hw->noreset) {
2056 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2057 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2058 return;
2059 }
2060
2061 /*
2062 * mac no longer enables phyclk automatically when driver accesses
2063 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2064 * band->pi is invalid. need to enable PHY CLK
2065 */
2066 if (D11REV_GE(wlc_hw->corerev, 18))
2067 flags |= SICF_PCLKE;
2068
2069 /*
2070 * reset the core
2071 * In chips with PMU, the fastclk request goes through d11 core
2072 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2073 *
2074 * This adds some delay and we can optimize it by also requesting
2075 * fastclk through chipcommon during this period if necessary. But
2076 * that has to work coordinate with other driver like mips/arm since
2077 * they may touch chipcommon as well.
2078 */
2079 wlc_hw->clk = false;
2080 bcma_core_enable(wlc_hw->d11core, flags);
2081 wlc_hw->clk = true;
2082 if (wlc_hw->band && wlc_hw->band->pi)
2083 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2084
2085 brcms_c_mctrl_reset(wlc_hw);
2086
2087 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2088 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2089
2090 brcms_b_phy_reset(wlc_hw);
2091
2092 /* turn on PHY_PLL */
2093 brcms_b_core_phypll_ctl(wlc_hw, true);
2094
2095 /* clear sw intstatus */
2096 wlc_hw->wlc->macintstatus = 0;
2097
2098 /* restore the clk setting */
2099 if (!fastclk)
2100 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2101 }
2102
2103 /* txfifo sizes needs to be modified(increased) since the newer cores
2104 * have more memory.
2105 */
2106 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2107 {
2108 struct bcma_device *core = wlc_hw->d11core;
2109 u16 fifo_nu;
2110 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2111 u16 txfifo_def, txfifo_def1;
2112 u16 txfifo_cmd;
2113
2114 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2115 txfifo_startblk = TXFIFO_START_BLK;
2116
2117 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2118 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2119
2120 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2121 txfifo_def = (txfifo_startblk & 0xff) |
2122 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2123 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2124 ((((txfifo_endblk -
2125 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2126 txfifo_cmd =
2127 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2128
2129 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2130 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2131 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2132
2133 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2134
2135 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2136 }
2137 /*
2138 * need to propagate to shm location to be in sync since ucode/hw won't
2139 * do this
2140 */
2141 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2142 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2143 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2144 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2145 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2146 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2147 xmtfifo_sz[TX_AC_BK_FIFO]));
2148 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2149 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2150 xmtfifo_sz[TX_BCMC_FIFO]));
2151 }
2152
2153 /* This function is used for changing the tsf frac register
2154 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2155 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2156 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2157 * HTPHY Formula is 2^26/freq(MHz) e.g.
2158 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2159 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2160 * For spuron: 123MHz -> 2^26/123 = 545600.5
2161 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2162 * For spur off: 120MHz -> 2^26/120 = 559240.5
2163 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2164 */
2165
2166 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2167 {
2168 struct bcma_device *core = wlc_hw->d11core;
2169
2170 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2171 (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2172 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2173 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2174 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2175 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2176 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2177 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2178 } else { /* 120Mhz */
2179 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2180 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2181 }
2182 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2183 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2184 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2185 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2186 } else { /* 80Mhz */
2187 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2188 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2189 }
2190 }
2191 }
2192
2193 /* Initialize GPIOs that are controlled by D11 core */
2194 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2195 {
2196 struct brcms_hardware *wlc_hw = wlc->hw;
2197 u32 gc, gm;
2198
2199 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2200 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2201
2202 /*
2203 * Common GPIO setup:
2204 * G0 = LED 0 = WLAN Activity
2205 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2206 * G2 = LED 2 = WLAN 5 GHz Radio State
2207 * G4 = radio disable input (HI enabled, LO disabled)
2208 */
2209
2210 gc = gm = 0;
2211
2212 /* Allocate GPIOs for mimo antenna diversity feature */
2213 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2214 /* Enable antenna diversity, use 2x3 mode */
2215 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2216 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2217 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2218 MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2219
2220 /* init superswitch control */
2221 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2222
2223 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2224 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2225 /*
2226 * The board itself is powered by these GPIOs
2227 * (when not sending pattern) so set them high
2228 */
2229 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2230 (BOARD_GPIO_12 | BOARD_GPIO_13));
2231 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2232 (BOARD_GPIO_12 | BOARD_GPIO_13));
2233
2234 /* Enable antenna diversity, use 2x4 mode */
2235 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2236 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2237 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2238 BRCM_BAND_ALL);
2239
2240 /* Configure the desired clock to be 4Mhz */
2241 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2242 ANTSEL_CLKDIV_4MHZ);
2243 }
2244
2245 /*
2246 * gpio 9 controls the PA. ucode is responsible
2247 * for wiggling out and oe
2248 */
2249 if (wlc_hw->boardflags & BFL_PACTRL)
2250 gm |= gc |= BOARD_GPIO_PACTRL;
2251
2252 /* apply to gpiocontrol register */
2253 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2254 }
2255
2256 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2257 const __le32 ucode[], const size_t nbytes)
2258 {
2259 struct bcma_device *core = wlc_hw->d11core;
2260 uint i;
2261 uint count;
2262
2263 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2264
2265 count = (nbytes / sizeof(u32));
2266
2267 bcma_write32(core, D11REGOFFS(objaddr),
2268 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2269 (void)bcma_read32(core, D11REGOFFS(objaddr));
2270 for (i = 0; i < count; i++)
2271 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2272
2273 }
2274
2275 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2276 {
2277 struct brcms_c_info *wlc;
2278 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2279
2280 wlc = wlc_hw->wlc;
2281
2282 if (wlc_hw->ucode_loaded)
2283 return;
2284
2285 if (D11REV_IS(wlc_hw->corerev, 23)) {
2286 if (BRCMS_ISNPHY(wlc_hw->band)) {
2287 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2288 ucode->bcm43xx_16_mimosz);
2289 wlc_hw->ucode_loaded = true;
2290 } else
2291 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2292 "corerev %d\n",
2293 __func__, wlc_hw->unit, wlc_hw->corerev);
2294 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2295 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2296 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2297 ucode->bcm43xx_24_lcnsz);
2298 wlc_hw->ucode_loaded = true;
2299 } else {
2300 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2301 "corerev %d\n",
2302 __func__, wlc_hw->unit, wlc_hw->corerev);
2303 }
2304 }
2305 }
2306
2307 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2308 {
2309 /* update sw state */
2310 wlc_hw->bmac_phytxant = phytxant;
2311
2312 /* push to ucode if up */
2313 if (!wlc_hw->up)
2314 return;
2315 brcms_c_ucode_txant_set(wlc_hw);
2316
2317 }
2318
2319 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2320 {
2321 return (u16) wlc_hw->wlc->stf->txant;
2322 }
2323
2324 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2325 {
2326 wlc_hw->antsel_type = antsel_type;
2327
2328 /* Update the antsel type for phy module to use */
2329 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2330 }
2331
2332 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2333 {
2334 bool fatal = false;
2335 uint unit;
2336 uint intstatus, idx;
2337 struct bcma_device *core = wlc_hw->d11core;
2338 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2339
2340 unit = wlc_hw->unit;
2341
2342 for (idx = 0; idx < NFIFO; idx++) {
2343 /* read intstatus register and ignore any non-error bits */
2344 intstatus =
2345 bcma_read32(core,
2346 D11REGOFFS(intctrlregs[idx].intstatus)) &
2347 I_ERRORS;
2348 if (!intstatus)
2349 continue;
2350
2351 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2352 unit, idx, intstatus);
2353
2354 if (intstatus & I_RO) {
2355 wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2356 "overflow\n", unit, idx);
2357 fatal = true;
2358 }
2359
2360 if (intstatus & I_PC) {
2361 wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2362 unit, idx);
2363 fatal = true;
2364 }
2365
2366 if (intstatus & I_PD) {
2367 wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2368 idx);
2369 fatal = true;
2370 }
2371
2372 if (intstatus & I_DE) {
2373 wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2374 "error\n", unit, idx);
2375 fatal = true;
2376 }
2377
2378 if (intstatus & I_RU)
2379 wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2380 "underflow\n", idx, unit);
2381
2382 if (intstatus & I_XU) {
2383 wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2384 "underflow\n", idx, unit);
2385 fatal = true;
2386 }
2387
2388 if (fatal) {
2389 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2390 break;
2391 } else
2392 bcma_write32(core,
2393 D11REGOFFS(intctrlregs[idx].intstatus),
2394 intstatus);
2395 }
2396 }
2397
2398 void brcms_c_intrson(struct brcms_c_info *wlc)
2399 {
2400 struct brcms_hardware *wlc_hw = wlc->hw;
2401 wlc->macintmask = wlc->defmacintmask;
2402 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2403 }
2404
2405 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2406 {
2407 struct brcms_hardware *wlc_hw = wlc->hw;
2408 u32 macintmask;
2409
2410 if (!wlc_hw->clk)
2411 return 0;
2412
2413 macintmask = wlc->macintmask; /* isr can still happen */
2414
2415 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2416 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2417 udelay(1); /* ensure int line is no longer driven */
2418 wlc->macintmask = 0;
2419
2420 /* return previous macintmask; resolve race between us and our isr */
2421 return wlc->macintstatus ? 0 : macintmask;
2422 }
2423
2424 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2425 {
2426 struct brcms_hardware *wlc_hw = wlc->hw;
2427 if (!wlc_hw->clk)
2428 return;
2429
2430 wlc->macintmask = macintmask;
2431 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2432 }
2433
2434 /* assumes that the d11 MAC is enabled */
2435 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2436 uint tx_fifo)
2437 {
2438 u8 fifo = 1 << tx_fifo;
2439
2440 /* Two clients of this code, 11h Quiet period and scanning. */
2441
2442 /* only suspend if not already suspended */
2443 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2444 return;
2445
2446 /* force the core awake only if not already */
2447 if (wlc_hw->suspended_fifos == 0)
2448 brcms_c_ucode_wake_override_set(wlc_hw,
2449 BRCMS_WAKE_OVERRIDE_TXFIFO);
2450
2451 wlc_hw->suspended_fifos |= fifo;
2452
2453 if (wlc_hw->di[tx_fifo]) {
2454 /*
2455 * Suspending AMPDU transmissions in the middle can cause
2456 * underflow which may result in mismatch between ucode and
2457 * driver so suspend the mac before suspending the FIFO
2458 */
2459 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2460 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2461
2462 dma_txsuspend(wlc_hw->di[tx_fifo]);
2463
2464 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2465 brcms_c_enable_mac(wlc_hw->wlc);
2466 }
2467 }
2468
2469 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2470 uint tx_fifo)
2471 {
2472 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2473 * but need to be done here for PIO otherwise the watchdog will catch
2474 * the inconsistency and fire
2475 */
2476 /* Two clients of this code, 11h Quiet period and scanning. */
2477 if (wlc_hw->di[tx_fifo])
2478 dma_txresume(wlc_hw->di[tx_fifo]);
2479
2480 /* allow core to sleep again */
2481 if (wlc_hw->suspended_fifos == 0)
2482 return;
2483 else {
2484 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2485 if (wlc_hw->suspended_fifos == 0)
2486 brcms_c_ucode_wake_override_clear(wlc_hw,
2487 BRCMS_WAKE_OVERRIDE_TXFIFO);
2488 }
2489 }
2490
2491 /* precondition: requires the mac core to be enabled */
2492 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2493 {
2494 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2495
2496 if (mute_tx) {
2497 /* suspend tx fifos */
2498 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2499 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2500 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2501 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2502
2503 /* zero the address match register so we do not send ACKs */
2504 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2505 null_ether_addr);
2506 } else {
2507 /* resume tx fifos */
2508 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2509 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2510 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2511 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2512
2513 /* Restore address */
2514 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2515 wlc_hw->etheraddr);
2516 }
2517
2518 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2519
2520 if (mute_tx)
2521 brcms_c_ucode_mute_override_set(wlc_hw);
2522 else
2523 brcms_c_ucode_mute_override_clear(wlc_hw);
2524 }
2525
2526 void
2527 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2528 {
2529 brcms_b_mute(wlc->hw, mute_tx);
2530 }
2531
2532 /*
2533 * Read and clear macintmask and macintstatus and intstatus registers.
2534 * This routine should be called with interrupts off
2535 * Return:
2536 * -1 if brcms_deviceremoved(wlc) evaluates to true;
2537 * 0 if the interrupt is not for us, or we are in some special cases;
2538 * device interrupt status bits otherwise.
2539 */
2540 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2541 {
2542 struct brcms_hardware *wlc_hw = wlc->hw;
2543 struct bcma_device *core = wlc_hw->d11core;
2544 u32 macintstatus;
2545
2546 /* macintstatus includes a DMA interrupt summary bit */
2547 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2548
2549 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2550 macintstatus);
2551
2552 /* detect cardbus removed, in power down(suspend) and in reset */
2553 if (brcms_deviceremoved(wlc))
2554 return -1;
2555
2556 /* brcms_deviceremoved() succeeds even when the core is still resetting,
2557 * handle that case here.
2558 */
2559 if (macintstatus == 0xffffffff)
2560 return 0;
2561
2562 /* defer unsolicited interrupts */
2563 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2564
2565 /* if not for us */
2566 if (macintstatus == 0)
2567 return 0;
2568
2569 /* interrupts are already turned off for CFE build
2570 * Caution: For CFE Turning off the interrupts again has some undesired
2571 * consequences
2572 */
2573 /* turn off the interrupts */
2574 bcma_write32(core, D11REGOFFS(macintmask), 0);
2575 (void)bcma_read32(core, D11REGOFFS(macintmask));
2576 wlc->macintmask = 0;
2577
2578 /* clear device interrupts */
2579 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2580
2581 /* MI_DMAINT is indication of non-zero intstatus */
2582 if (macintstatus & MI_DMAINT)
2583 /*
2584 * only fifo interrupt enabled is I_RI in
2585 * RX_FIFO. If MI_DMAINT is set, assume it
2586 * is set and clear the interrupt.
2587 */
2588 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2589 DEF_RXINTMASK);
2590
2591 return macintstatus;
2592 }
2593
2594 /* Update wlc->macintstatus and wlc->intstatus[]. */
2595 /* Return true if they are updated successfully. false otherwise */
2596 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2597 {
2598 u32 macintstatus;
2599
2600 /* read and clear macintstatus and intstatus registers */
2601 macintstatus = wlc_intstatus(wlc, false);
2602
2603 /* device is removed */
2604 if (macintstatus == 0xffffffff)
2605 return false;
2606
2607 /* update interrupt status in software */
2608 wlc->macintstatus |= macintstatus;
2609
2610 return true;
2611 }
2612
2613 /*
2614 * First-level interrupt processing.
2615 * Return true if this was our interrupt, false otherwise.
2616 * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
2617 * false otherwise.
2618 */
2619 bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc)
2620 {
2621 struct brcms_hardware *wlc_hw = wlc->hw;
2622 u32 macintstatus;
2623
2624 *wantdpc = false;
2625
2626 if (!wlc_hw->up || !wlc->macintmask)
2627 return false;
2628
2629 /* read and clear macintstatus and intstatus registers */
2630 macintstatus = wlc_intstatus(wlc, true);
2631
2632 if (macintstatus == 0xffffffff)
2633 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2634 " path\n");
2635
2636 /* it is not for us */
2637 if (macintstatus == 0)
2638 return false;
2639
2640 *wantdpc = true;
2641
2642 /* save interrupt status bits */
2643 wlc->macintstatus = macintstatus;
2644
2645 return true;
2646
2647 }
2648
2649 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2650 {
2651 struct brcms_hardware *wlc_hw = wlc->hw;
2652 struct bcma_device *core = wlc_hw->d11core;
2653 u32 mc, mi;
2654 struct wiphy *wiphy = wlc->wiphy;
2655
2656 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2657 wlc_hw->band->bandunit);
2658
2659 /*
2660 * Track overlapping suspend requests
2661 */
2662 wlc_hw->mac_suspend_depth++;
2663 if (wlc_hw->mac_suspend_depth > 1)
2664 return;
2665
2666 /* force the core awake */
2667 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2668
2669 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2670
2671 if (mc == 0xffffffff) {
2672 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2673 __func__);
2674 brcms_down(wlc->wl);
2675 return;
2676 }
2677 WARN_ON(mc & MCTL_PSM_JMP_0);
2678 WARN_ON(!(mc & MCTL_PSM_RUN));
2679 WARN_ON(!(mc & MCTL_EN_MAC));
2680
2681 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2682 if (mi == 0xffffffff) {
2683 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2684 __func__);
2685 brcms_down(wlc->wl);
2686 return;
2687 }
2688 WARN_ON(mi & MI_MACSSPNDD);
2689
2690 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2691
2692 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2693 BRCMS_MAX_MAC_SUSPEND);
2694
2695 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2696 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2697 " and MI_MACSSPNDD is still not on.\n",
2698 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2699 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2700 "psm_brc 0x%04x\n", wlc_hw->unit,
2701 bcma_read32(core, D11REGOFFS(psmdebug)),
2702 bcma_read32(core, D11REGOFFS(phydebug)),
2703 bcma_read16(core, D11REGOFFS(psm_brc)));
2704 }
2705
2706 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2707 if (mc == 0xffffffff) {
2708 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2709 __func__);
2710 brcms_down(wlc->wl);
2711 return;
2712 }
2713 WARN_ON(mc & MCTL_PSM_JMP_0);
2714 WARN_ON(!(mc & MCTL_PSM_RUN));
2715 WARN_ON(mc & MCTL_EN_MAC);
2716 }
2717
2718 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2719 {
2720 struct brcms_hardware *wlc_hw = wlc->hw;
2721 struct bcma_device *core = wlc_hw->d11core;
2722 u32 mc, mi;
2723
2724 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2725 wlc->band->bandunit);
2726
2727 /*
2728 * Track overlapping suspend requests
2729 */
2730 wlc_hw->mac_suspend_depth--;
2731 if (wlc_hw->mac_suspend_depth > 0)
2732 return;
2733
2734 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2735 WARN_ON(mc & MCTL_PSM_JMP_0);
2736 WARN_ON(mc & MCTL_EN_MAC);
2737 WARN_ON(!(mc & MCTL_PSM_RUN));
2738
2739 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2740 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2741
2742 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2743 WARN_ON(mc & MCTL_PSM_JMP_0);
2744 WARN_ON(!(mc & MCTL_EN_MAC));
2745 WARN_ON(!(mc & MCTL_PSM_RUN));
2746
2747 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2748 WARN_ON(mi & MI_MACSSPNDD);
2749
2750 brcms_c_ucode_wake_override_clear(wlc_hw,
2751 BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2752 }
2753
2754 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2755 {
2756 wlc_hw->hw_stf_ss_opmode = stf_mode;
2757
2758 if (wlc_hw->clk)
2759 brcms_upd_ofdm_pctl1_table(wlc_hw);
2760 }
2761
2762 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2763 {
2764 struct bcma_device *core = wlc_hw->d11core;
2765 u32 w, val;
2766 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2767
2768 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
2769
2770 /* Validate dchip register access */
2771
2772 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2773 (void)bcma_read32(core, D11REGOFFS(objaddr));
2774 w = bcma_read32(core, D11REGOFFS(objdata));
2775
2776 /* Can we write and read back a 32bit register? */
2777 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2778 (void)bcma_read32(core, D11REGOFFS(objaddr));
2779 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2780
2781 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2782 (void)bcma_read32(core, D11REGOFFS(objaddr));
2783 val = bcma_read32(core, D11REGOFFS(objdata));
2784 if (val != (u32) 0xaa5555aa) {
2785 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2786 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2787 return false;
2788 }
2789
2790 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2791 (void)bcma_read32(core, D11REGOFFS(objaddr));
2792 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2793
2794 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2795 (void)bcma_read32(core, D11REGOFFS(objaddr));
2796 val = bcma_read32(core, D11REGOFFS(objdata));
2797 if (val != (u32) 0x55aaaa55) {
2798 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2799 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2800 return false;
2801 }
2802
2803 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2804 (void)bcma_read32(core, D11REGOFFS(objaddr));
2805 bcma_write32(core, D11REGOFFS(objdata), w);
2806
2807 /* clear CFPStart */
2808 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2809
2810 w = bcma_read32(core, D11REGOFFS(maccontrol));
2811 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2812 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2813 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2814 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2815 (MCTL_IHR_EN | MCTL_WAKE),
2816 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2817 return false;
2818 }
2819
2820 return true;
2821 }
2822
2823 #define PHYPLL_WAIT_US 100000
2824
2825 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2826 {
2827 struct bcma_device *core = wlc_hw->d11core;
2828 u32 tmp;
2829
2830 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2831
2832 tmp = 0;
2833
2834 if (on) {
2835 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2836 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2837 CCS_ERSRC_REQ_HT |
2838 CCS_ERSRC_REQ_D11PLL |
2839 CCS_ERSRC_REQ_PHYPLL);
2840 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2841 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2842 PHYPLL_WAIT_US);
2843
2844 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2845 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2846 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
2847 " PLL failed\n", __func__);
2848 } else {
2849 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2850 tmp | CCS_ERSRC_REQ_D11PLL |
2851 CCS_ERSRC_REQ_PHYPLL);
2852 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2853 (CCS_ERSRC_AVAIL_D11PLL |
2854 CCS_ERSRC_AVAIL_PHYPLL)) !=
2855 (CCS_ERSRC_AVAIL_D11PLL |
2856 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2857
2858 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2859 if ((tmp &
2860 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2861 !=
2862 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2863 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
2864 "PHY PLL failed\n", __func__);
2865 }
2866 } else {
2867 /*
2868 * Since the PLL may be shared, other cores can still
2869 * be requesting it; so we'll deassert the request but
2870 * not wait for status to comply.
2871 */
2872 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2873 ~CCS_ERSRC_REQ_PHYPLL);
2874 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2875 }
2876 }
2877
2878 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2879 {
2880 bool dev_gone;
2881
2882 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2883
2884 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2885
2886 if (dev_gone)
2887 return;
2888
2889 if (wlc_hw->noreset)
2890 return;
2891
2892 /* radio off */
2893 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2894
2895 /* turn off analog core */
2896 wlc_phy_anacore(wlc_hw->band->pi, OFF);
2897
2898 /* turn off PHYPLL to save power */
2899 brcms_b_core_phypll_ctl(wlc_hw, false);
2900
2901 wlc_hw->clk = false;
2902 bcma_core_disable(wlc_hw->d11core, 0);
2903 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2904 }
2905
2906 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2907 {
2908 struct brcms_hardware *wlc_hw = wlc->hw;
2909 uint i;
2910
2911 /* free any posted tx packets */
2912 for (i = 0; i < NFIFO; i++) {
2913 if (wlc_hw->di[i]) {
2914 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2915 if (i < TX_BCMC_FIFO)
2916 ieee80211_wake_queue(wlc->pub->ieee_hw,
2917 brcms_fifo_to_ac(i));
2918 }
2919 }
2920
2921 /* free any posted rx packets */
2922 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2923 }
2924
2925 static u16
2926 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2927 {
2928 struct bcma_device *core = wlc_hw->d11core;
2929 u16 objoff = D11REGOFFS(objdata);
2930
2931 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2932 (void)bcma_read32(core, D11REGOFFS(objaddr));
2933 if (offset & 2)
2934 objoff += 2;
2935
2936 return bcma_read16(core, objoff);
2937 }
2938
2939 static void
2940 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2941 u32 sel)
2942 {
2943 struct bcma_device *core = wlc_hw->d11core;
2944 u16 objoff = D11REGOFFS(objdata);
2945
2946 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2947 (void)bcma_read32(core, D11REGOFFS(objaddr));
2948 if (offset & 2)
2949 objoff += 2;
2950
2951 bcma_write16(core, objoff, v);
2952 }
2953
2954 /*
2955 * Read a single u16 from shared memory.
2956 * SHM 'offset' needs to be an even address
2957 */
2958 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2959 {
2960 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2961 }
2962
2963 /*
2964 * Write a single u16 to shared memory.
2965 * SHM 'offset' needs to be an even address
2966 */
2967 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2968 {
2969 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2970 }
2971
2972 /*
2973 * Copy a buffer to shared memory of specified type .
2974 * SHM 'offset' needs to be an even address and
2975 * Buffer length 'len' must be an even number of bytes
2976 * 'sel' selects the type of memory
2977 */
2978 void
2979 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2980 const void *buf, int len, u32 sel)
2981 {
2982 u16 v;
2983 const u8 *p = (const u8 *)buf;
2984 int i;
2985
2986 if (len <= 0 || (offset & 1) || (len & 1))
2987 return;
2988
2989 for (i = 0; i < len; i += 2) {
2990 v = p[i] | (p[i + 1] << 8);
2991 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2992 }
2993 }
2994
2995 /*
2996 * Copy a piece of shared memory of specified type to a buffer .
2997 * SHM 'offset' needs to be an even address and
2998 * Buffer length 'len' must be an even number of bytes
2999 * 'sel' selects the type of memory
3000 */
3001 void
3002 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
3003 int len, u32 sel)
3004 {
3005 u16 v;
3006 u8 *p = (u8 *) buf;
3007 int i;
3008
3009 if (len <= 0 || (offset & 1) || (len & 1))
3010 return;
3011
3012 for (i = 0; i < len; i += 2) {
3013 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
3014 p[i] = v & 0xFF;
3015 p[i + 1] = (v >> 8) & 0xFF;
3016 }
3017 }
3018
3019 /* Copy a buffer to shared memory.
3020 * SHM 'offset' needs to be an even address and
3021 * Buffer length 'len' must be an even number of bytes
3022 */
3023 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
3024 const void *buf, int len)
3025 {
3026 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
3027 }
3028
3029 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3030 u16 SRL, u16 LRL)
3031 {
3032 wlc_hw->SRL = SRL;
3033 wlc_hw->LRL = LRL;
3034
3035 /* write retry limit to SCR, shouldn't need to suspend */
3036 if (wlc_hw->up) {
3037 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3038 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3039 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3040 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3041 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3042 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3043 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3044 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3045 }
3046 }
3047
3048 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3049 {
3050 if (set) {
3051 if (mboolisset(wlc_hw->pllreq, req_bit))
3052 return;
3053
3054 mboolset(wlc_hw->pllreq, req_bit);
3055
3056 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3057 if (!wlc_hw->sbclk)
3058 brcms_b_xtal(wlc_hw, ON);
3059 }
3060 } else {
3061 if (!mboolisset(wlc_hw->pllreq, req_bit))
3062 return;
3063
3064 mboolclr(wlc_hw->pllreq, req_bit);
3065
3066 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3067 if (wlc_hw->sbclk)
3068 brcms_b_xtal(wlc_hw, OFF);
3069 }
3070 }
3071 }
3072
3073 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3074 {
3075 wlc_hw->antsel_avail = antsel_avail;
3076 }
3077
3078 /*
3079 * conditions under which the PM bit should be set in outgoing frames
3080 * and STAY_AWAKE is meaningful
3081 */
3082 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3083 {
3084 struct brcms_bss_cfg *cfg = wlc->bsscfg;
3085
3086 /* disallow PS when one of the following global conditions meets */
3087 if (!wlc->pub->associated)
3088 return false;
3089
3090 /* disallow PS when one of these meets when not scanning */
3091 if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3092 return false;
3093
3094 if (cfg->associated) {
3095 /*
3096 * disallow PS when one of the following
3097 * bsscfg specific conditions meets
3098 */
3099 if (!cfg->BSS)
3100 return false;
3101
3102 return false;
3103 }
3104
3105 return true;
3106 }
3107
3108 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3109 {
3110 int i;
3111 struct macstat macstats;
3112 #ifdef DEBUG
3113 u16 delta;
3114 u16 rxf0ovfl;
3115 u16 txfunfl[NFIFO];
3116 #endif /* DEBUG */
3117
3118 /* if driver down, make no sense to update stats */
3119 if (!wlc->pub->up)
3120 return;
3121
3122 #ifdef DEBUG
3123 /* save last rx fifo 0 overflow count */
3124 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3125
3126 /* save last tx fifo underflow count */
3127 for (i = 0; i < NFIFO; i++)
3128 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3129 #endif /* DEBUG */
3130
3131 /* Read mac stats from contiguous shared memory */
3132 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3133 sizeof(struct macstat), OBJADDR_SHM_SEL);
3134
3135 #ifdef DEBUG
3136 /* check for rx fifo 0 overflow */
3137 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3138 if (delta)
3139 wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n",
3140 wlc->pub->unit, delta);
3141
3142 /* check for tx fifo underflows */
3143 for (i = 0; i < NFIFO; i++) {
3144 delta =
3145 (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3146 txfunfl[i]);
3147 if (delta)
3148 wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
3149 "\n", wlc->pub->unit, delta, i);
3150 }
3151 #endif /* DEBUG */
3152
3153 /* merge counters from dma module */
3154 for (i = 0; i < NFIFO; i++) {
3155 if (wlc->hw->di[i])
3156 dma_counterreset(wlc->hw->di[i]);
3157 }
3158 }
3159
3160 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3161 {
3162 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3163
3164 /* reset the core */
3165 if (!brcms_deviceremoved(wlc_hw->wlc))
3166 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3167
3168 /* purge the dma rings */
3169 brcms_c_flushqueues(wlc_hw->wlc);
3170 }
3171
3172 void brcms_c_reset(struct brcms_c_info *wlc)
3173 {
3174 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3175
3176 /* slurp up hw mac counters before core reset */
3177 brcms_c_statsupd(wlc);
3178
3179 /* reset our snapshot of macstat counters */
3180 memset((char *)wlc->core->macstat_snapshot, 0,
3181 sizeof(struct macstat));
3182
3183 brcms_b_reset(wlc->hw);
3184 }
3185
3186 void brcms_c_init_scb(struct scb *scb)
3187 {
3188 int i;
3189
3190 memset(scb, 0, sizeof(struct scb));
3191 scb->flags = SCB_WMECAP | SCB_HTCAP;
3192 for (i = 0; i < NUMPRIO; i++) {
3193 scb->seqnum[i] = 0;
3194 scb->seqctl[i] = 0xFFFF;
3195 }
3196
3197 scb->seqctl_nonqos = 0xFFFF;
3198 scb->magic = SCB_MAGIC;
3199 }
3200
3201 /* d11 core init
3202 * reset PSM
3203 * download ucode/PCM
3204 * let ucode run to suspended
3205 * download ucode inits
3206 * config other core registers
3207 * init dma
3208 */
3209 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3210 {
3211 struct brcms_hardware *wlc_hw = wlc->hw;
3212 struct bcma_device *core = wlc_hw->d11core;
3213 u32 sflags;
3214 u32 bcnint_us;
3215 uint i = 0;
3216 bool fifosz_fixup = false;
3217 int err = 0;
3218 u16 buf[NFIFO];
3219 struct wiphy *wiphy = wlc->wiphy;
3220 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3221
3222 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3223
3224 /* reset PSM */
3225 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3226
3227 brcms_ucode_download(wlc_hw);
3228 /*
3229 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3230 */
3231 fifosz_fixup = true;
3232
3233 /* let the PSM run to the suspended state, set mode to BSS STA */
3234 bcma_write32(core, D11REGOFFS(macintstatus), -1);
3235 brcms_b_mctrl(wlc_hw, ~0,
3236 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3237
3238 /* wait for ucode to self-suspend after auto-init */
3239 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3240 MI_MACSSPNDD) == 0), 1000 * 1000);
3241 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3242 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
3243 "suspend!\n", wlc_hw->unit);
3244
3245 brcms_c_gpio_init(wlc);
3246
3247 sflags = bcma_aread32(core, BCMA_IOST);
3248
3249 if (D11REV_IS(wlc_hw->corerev, 23)) {
3250 if (BRCMS_ISNPHY(wlc_hw->band))
3251 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3252 else
3253 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3254 " %d\n", __func__, wlc_hw->unit,
3255 wlc_hw->corerev);
3256 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3257 if (BRCMS_ISLCNPHY(wlc_hw->band))
3258 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3259 else
3260 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3261 " %d\n", __func__, wlc_hw->unit,
3262 wlc_hw->corerev);
3263 } else {
3264 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
3265 __func__, wlc_hw->unit, wlc_hw->corerev);
3266 }
3267
3268 /* For old ucode, txfifo sizes needs to be modified(increased) */
3269 if (fifosz_fixup)
3270 brcms_b_corerev_fifofixup(wlc_hw);
3271
3272 /* check txfifo allocations match between ucode and driver */
3273 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3274 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3275 i = TX_AC_BE_FIFO;
3276 err = -1;
3277 }
3278 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3279 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3280 i = TX_AC_VI_FIFO;
3281 err = -1;
3282 }
3283 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3284 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3285 buf[TX_AC_BK_FIFO] &= 0xff;
3286 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3287 i = TX_AC_BK_FIFO;
3288 err = -1;
3289 }
3290 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3291 i = TX_AC_VO_FIFO;
3292 err = -1;
3293 }
3294 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3295 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3296 buf[TX_BCMC_FIFO] &= 0xff;
3297 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3298 i = TX_BCMC_FIFO;
3299 err = -1;
3300 }
3301 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3302 i = TX_ATIM_FIFO;
3303 err = -1;
3304 }
3305 if (err != 0)
3306 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
3307 " driver size %d index %d\n", buf[i],
3308 wlc_hw->xmtfifo_sz[i], i);
3309
3310 /* make sure we can still talk to the mac */
3311 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3312
3313 /* band-specific inits done by wlc_bsinit() */
3314
3315 /* Set up frame burst size and antenna swap threshold init values */
3316 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3317 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3318
3319 /* enable one rx interrupt per received frame */
3320 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3321
3322 /* set the station mode (BSS STA) */
3323 brcms_b_mctrl(wlc_hw,
3324 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3325 (MCTL_INFRA | MCTL_DISCARD_PMQ));
3326
3327 /* set up Beacon interval */
3328 bcnint_us = 0x8000 << 10;
3329 bcma_write32(core, D11REGOFFS(tsf_cfprep),
3330 (bcnint_us << CFPREP_CBI_SHIFT));
3331 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3332 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3333
3334 /* write interrupt mask */
3335 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3336 DEF_RXINTMASK);
3337
3338 /* allow the MAC to control the PHY clock (dynamic on/off) */
3339 brcms_b_macphyclk_set(wlc_hw, ON);
3340
3341 /* program dynamic clock control fast powerup delay register */
3342 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3343 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3344
3345 /* tell the ucode the corerev */
3346 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3347
3348 /* tell the ucode MAC capabilities */
3349 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3350 (u16) (wlc_hw->machwcap & 0xffff));
3351 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3352 (u16) ((wlc_hw->
3353 machwcap >> 16) & 0xffff));
3354
3355 /* write retry limits to SCR, this done after PSM init */
3356 bcma_write32(core, D11REGOFFS(objaddr),
3357 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3358 (void)bcma_read32(core, D11REGOFFS(objaddr));
3359 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3360 bcma_write32(core, D11REGOFFS(objaddr),
3361 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3362 (void)bcma_read32(core, D11REGOFFS(objaddr));
3363 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3364
3365 /* write rate fallback retry limits */
3366 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3367 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3368
3369 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3370 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3371
3372 /* init the tx dma engines */
3373 for (i = 0; i < NFIFO; i++) {
3374 if (wlc_hw->di[i])
3375 dma_txinit(wlc_hw->di[i]);
3376 }
3377
3378 /* init the rx dma engine(s) and post receive buffers */
3379 dma_rxinit(wlc_hw->di[RX_FIFO]);
3380 dma_rxfill(wlc_hw->di[RX_FIFO]);
3381 }
3382
3383 void
3384 static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3385 u32 macintmask;
3386 bool fastclk;
3387 struct brcms_c_info *wlc = wlc_hw->wlc;
3388
3389 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3390
3391 /* request FAST clock if not on */
3392 fastclk = wlc_hw->forcefastclk;
3393 if (!fastclk)
3394 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3395
3396 /* disable interrupts */
3397 macintmask = brcms_intrsoff(wlc->wl);
3398
3399 /* set up the specified band and chanspec */
3400 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3401 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3402
3403 /* do one-time phy inits and calibration */
3404 wlc_phy_cal_init(wlc_hw->band->pi);
3405
3406 /* core-specific initialization */
3407 brcms_b_coreinit(wlc);
3408
3409 /* band-specific inits */
3410 brcms_b_bsinit(wlc, chanspec);
3411
3412 /* restore macintmask */
3413 brcms_intrsrestore(wlc->wl, macintmask);
3414
3415 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3416 * is suspended and brcms_c_enable_mac() will clear this override bit.
3417 */
3418 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3419
3420 /*
3421 * initialize mac_suspend_depth to 1 to match ucode
3422 * initial suspended state
3423 */
3424 wlc_hw->mac_suspend_depth = 1;
3425
3426 /* restore the clk */
3427 if (!fastclk)
3428 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3429 }
3430
3431 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3432 u16 chanspec)
3433 {
3434 /* Save our copy of the chanspec */
3435 wlc->chanspec = chanspec;
3436
3437 /* Set the chanspec and power limits for this locale */
3438 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3439
3440 if (wlc->stf->ss_algosel_auto)
3441 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3442 chanspec);
3443
3444 brcms_c_stf_ss_update(wlc, wlc->band);
3445 }
3446
3447 static void
3448 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3449 {
3450 brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3451 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3452 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3453 brcms_chspec_bw(wlc->default_bss->chanspec),
3454 wlc->stf->txstreams);
3455 }
3456
3457 /* derive wlc->band->basic_rate[] table from 'rateset' */
3458 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3459 struct brcms_c_rateset *rateset)
3460 {
3461 u8 rate;
3462 u8 mandatory;
3463 u8 cck_basic = 0;
3464 u8 ofdm_basic = 0;
3465 u8 *br = wlc->band->basic_rate;
3466 uint i;
3467
3468 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3469 memset(br, 0, BRCM_MAXRATE + 1);
3470
3471 /* For each basic rate in the rates list, make an entry in the
3472 * best basic lookup.
3473 */
3474 for (i = 0; i < rateset->count; i++) {
3475 /* only make an entry for a basic rate */
3476 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3477 continue;
3478
3479 /* mask off basic bit */
3480 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3481
3482 if (rate > BRCM_MAXRATE) {
3483 wiphy_err(wlc->wiphy, "brcms_c_rate_lookup_init: "
3484 "invalid rate 0x%X in rate set\n",
3485 rateset->rates[i]);
3486 continue;
3487 }
3488
3489 br[rate] = rate;
3490 }
3491
3492 /* The rate lookup table now has non-zero entries for each
3493 * basic rate, equal to the basic rate: br[basicN] = basicN
3494 *
3495 * To look up the best basic rate corresponding to any
3496 * particular rate, code can use the basic_rate table
3497 * like this
3498 *
3499 * basic_rate = wlc->band->basic_rate[tx_rate]
3500 *
3501 * Make sure there is a best basic rate entry for
3502 * every rate by walking up the table from low rates
3503 * to high, filling in holes in the lookup table
3504 */
3505
3506 for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3507 rate = wlc->band->hw_rateset.rates[i];
3508
3509 if (br[rate] != 0) {
3510 /* This rate is a basic rate.
3511 * Keep track of the best basic rate so far by
3512 * modulation type.
3513 */
3514 if (is_ofdm_rate(rate))
3515 ofdm_basic = rate;
3516 else
3517 cck_basic = rate;
3518
3519 continue;
3520 }
3521
3522 /* This rate is not a basic rate so figure out the
3523 * best basic rate less than this rate and fill in
3524 * the hole in the table
3525 */
3526
3527 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3528
3529 if (br[rate] != 0)
3530 continue;
3531
3532 if (is_ofdm_rate(rate)) {
3533 /*
3534 * In 11g and 11a, the OFDM mandatory rates
3535 * are 6, 12, and 24 Mbps
3536 */
3537 if (rate >= BRCM_RATE_24M)
3538 mandatory = BRCM_RATE_24M;
3539 else if (rate >= BRCM_RATE_12M)
3540 mandatory = BRCM_RATE_12M;
3541 else
3542 mandatory = BRCM_RATE_6M;
3543 } else {
3544 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3545 mandatory = rate;
3546 }
3547
3548 br[rate] = mandatory;
3549 }
3550 }
3551
3552 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3553 u16 chanspec)
3554 {
3555 struct brcms_c_rateset default_rateset;
3556 uint parkband;
3557 uint i, band_order[2];
3558
3559 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3560 /*
3561 * We might have been bandlocked during down and the chip
3562 * power-cycled (hibernate). Figure out the right band to park on
3563 */
3564 if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3565 /* updated in brcms_c_bandlock() */
3566 parkband = wlc->band->bandunit;
3567 band_order[0] = band_order[1] = parkband;
3568 } else {
3569 /* park on the band of the specified chanspec */
3570 parkband = chspec_bandunit(chanspec);
3571
3572 /* order so that parkband initialize last */
3573 band_order[0] = parkband ^ 1;
3574 band_order[1] = parkband;
3575 }
3576
3577 /* make each band operational, software state init */
3578 for (i = 0; i < wlc->pub->_nbands; i++) {
3579 uint j = band_order[i];
3580
3581 wlc->band = wlc->bandstate[j];
3582
3583 brcms_default_rateset(wlc, &default_rateset);
3584
3585 /* fill in hw_rate */
3586 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3587 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3588 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3589
3590 /* init basic rate lookup */
3591 brcms_c_rate_lookup_init(wlc, &default_rateset);
3592 }
3593
3594 /* sync up phy/radio chanspec */
3595 brcms_c_set_phy_chanspec(wlc, chanspec);
3596 }
3597
3598 /*
3599 * Set or clear filtering related maccontrol bits based on
3600 * specified filter flags
3601 */
3602 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3603 {
3604 u32 promisc_bits = 0;
3605
3606 wlc->filter_flags = filter_flags;
3607
3608 if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3609 promisc_bits |= MCTL_PROMISC;
3610
3611 if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3612 promisc_bits |= MCTL_BCNS_PROMISC;
3613
3614 if (filter_flags & FIF_FCSFAIL)
3615 promisc_bits |= MCTL_KEEPBADFCS;
3616
3617 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3618 promisc_bits |= MCTL_KEEPCONTROL;
3619
3620 brcms_b_mctrl(wlc->hw,
3621 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3622 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3623 promisc_bits);
3624 }
3625
3626 /*
3627 * ucode, hwmac update
3628 * Channel dependent updates for ucode and hw
3629 */
3630 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3631 {
3632 /* enable or disable any active IBSSs depending on whether or not
3633 * we are on the home channel
3634 */
3635 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3636 if (wlc->pub->associated) {
3637 /*
3638 * BMAC_NOTE: This is something that should be fixed
3639 * in ucode inits. I think that the ucode inits set
3640 * up the bcn templates and shm values with a bogus
3641 * beacon. This should not be done in the inits. If
3642 * ucode needs to set up a beacon for testing, the
3643 * test routines should write it down, not expect the
3644 * inits to populate a bogus beacon.
3645 */
3646 if (BRCMS_PHY_11N_CAP(wlc->band))
3647 brcms_b_write_shm(wlc->hw,
3648 M_BCN_TXTSF_OFFSET, 0);
3649 }
3650 } else {
3651 /* disable an active IBSS if we are not on the home channel */
3652 }
3653 }
3654
3655 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3656 u8 basic_rate)
3657 {
3658 u8 phy_rate, index;
3659 u8 basic_phy_rate, basic_index;
3660 u16 dir_table, basic_table;
3661 u16 basic_ptr;
3662
3663 /* Shared memory address for the table we are reading */
3664 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3665
3666 /* Shared memory address for the table we are writing */
3667 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3668
3669 /*
3670 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3671 * the index into the rate table.
3672 */
3673 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3674 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3675 index = phy_rate & 0xf;
3676 basic_index = basic_phy_rate & 0xf;
3677
3678 /* Find the SHM pointer to the ACK rate entry by looking in the
3679 * Direct-map Table
3680 */
3681 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3682
3683 /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3684 * to the correct basic rate for the given incoming rate
3685 */
3686 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3687 }
3688
3689 static const struct brcms_c_rateset *
3690 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3691 {
3692 const struct brcms_c_rateset *rs_dflt;
3693
3694 if (BRCMS_PHY_11N_CAP(wlc->band)) {
3695 if (wlc->band->bandtype == BRCM_BAND_5G)
3696 rs_dflt = &ofdm_mimo_rates;
3697 else
3698 rs_dflt = &cck_ofdm_mimo_rates;
3699 } else if (wlc->band->gmode)
3700 rs_dflt = &cck_ofdm_rates;
3701 else
3702 rs_dflt = &cck_rates;
3703
3704 return rs_dflt;
3705 }
3706
3707 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3708 {
3709 const struct brcms_c_rateset *rs_dflt;
3710 struct brcms_c_rateset rs;
3711 u8 rate, basic_rate;
3712 uint i;
3713
3714 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3715
3716 brcms_c_rateset_copy(rs_dflt, &rs);
3717 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3718
3719 /* walk the phy rate table and update SHM basic rate lookup table */
3720 for (i = 0; i < rs.count; i++) {
3721 rate = rs.rates[i] & BRCMS_RATE_MASK;
3722
3723 /* for a given rate brcms_basic_rate returns the rate at
3724 * which a response ACK/CTS should be sent.
3725 */
3726 basic_rate = brcms_basic_rate(wlc, rate);
3727 if (basic_rate == 0)
3728 /* This should only happen if we are using a
3729 * restricted rateset.
3730 */
3731 basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3732
3733 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3734 }
3735 }
3736
3737 /* band-specific init */
3738 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3739 {
3740 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n",
3741 wlc->pub->unit, wlc->band->bandunit);
3742
3743 /* write ucode ACK/CTS rate table */
3744 brcms_c_set_ratetable(wlc);
3745
3746 /* update some band specific mac configuration */
3747 brcms_c_ucode_mac_upd(wlc);
3748
3749 /* init antenna selection */
3750 brcms_c_antsel_init(wlc->asi);
3751
3752 }
3753
3754 /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3755 static int
3756 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3757 bool writeToShm)
3758 {
3759 int idle_busy_ratio_x_16 = 0;
3760 uint offset =
3761 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3762 M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3763 if (duty_cycle > 100 || duty_cycle < 0) {
3764 wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n",
3765 wlc->pub->unit);
3766 return -EINVAL;
3767 }
3768 if (duty_cycle)
3769 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3770 /* Only write to shared memory when wl is up */
3771 if (writeToShm)
3772 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3773
3774 if (isOFDM)
3775 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3776 else
3777 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3778
3779 return 0;
3780 }
3781
3782 /* push sw hps and wake state through hardware */
3783 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3784 {
3785 u32 v1, v2;
3786 bool hps;
3787 bool awake_before;
3788
3789 hps = brcms_c_ps_allowed(wlc);
3790
3791 BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
3792
3793 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3794 v2 = MCTL_WAKE;
3795 if (hps)
3796 v2 |= MCTL_HPS;
3797
3798 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3799
3800 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3801
3802 if (!awake_before)
3803 brcms_b_wait_for_wake(wlc->hw);
3804 }
3805
3806 /*
3807 * Write this BSS config's MAC address to core.
3808 * Updates RXE match engine.
3809 */
3810 static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3811 {
3812 int err = 0;
3813 struct brcms_c_info *wlc = bsscfg->wlc;
3814
3815 /* enter the MAC addr into the RXE match registers */
3816 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
3817
3818 brcms_c_ampdu_macaddr_upd(wlc);
3819
3820 return err;
3821 }
3822
3823 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3824 * Updates RXE match engine.
3825 */
3826 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3827 {
3828 /* we need to update BSSID in RXE match registers */
3829 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3830 }
3831
3832 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3833 {
3834 wlc_hw->shortslot = shortslot;
3835
3836 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3837 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3838 brcms_b_update_slot_timing(wlc_hw, shortslot);
3839 brcms_c_enable_mac(wlc_hw->wlc);
3840 }
3841 }
3842
3843 /*
3844 * Suspend the the MAC and update the slot timing
3845 * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3846 */
3847 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3848 {
3849 /* use the override if it is set */
3850 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3851 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3852
3853 if (wlc->shortslot == shortslot)
3854 return;
3855
3856 wlc->shortslot = shortslot;
3857
3858 brcms_b_set_shortslot(wlc->hw, shortslot);
3859 }
3860
3861 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3862 {
3863 if (wlc->home_chanspec != chanspec) {
3864 wlc->home_chanspec = chanspec;
3865
3866 if (wlc->bsscfg->associated)
3867 wlc->bsscfg->current_bss->chanspec = chanspec;
3868 }
3869 }
3870
3871 void
3872 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3873 bool mute_tx, struct txpwr_limits *txpwr)
3874 {
3875 uint bandunit;
3876
3877 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
3878
3879 wlc_hw->chanspec = chanspec;
3880
3881 /* Switch bands if necessary */
3882 if (wlc_hw->_nbands > 1) {
3883 bandunit = chspec_bandunit(chanspec);
3884 if (wlc_hw->band->bandunit != bandunit) {
3885 /* brcms_b_setband disables other bandunit,
3886 * use light band switch if not up yet
3887 */
3888 if (wlc_hw->up) {
3889 wlc_phy_chanspec_radio_set(wlc_hw->
3890 bandstate[bandunit]->
3891 pi, chanspec);
3892 brcms_b_setband(wlc_hw, bandunit, chanspec);
3893 } else {
3894 brcms_c_setxband(wlc_hw, bandunit);
3895 }
3896 }
3897 }
3898
3899 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3900
3901 if (!wlc_hw->up) {
3902 if (wlc_hw->clk)
3903 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3904 chanspec);
3905 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3906 } else {
3907 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3908 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3909
3910 /* Update muting of the channel */
3911 brcms_b_mute(wlc_hw, mute_tx);
3912 }
3913 }
3914
3915 /* switch to and initialize new band */
3916 static void brcms_c_setband(struct brcms_c_info *wlc,
3917 uint bandunit)
3918 {
3919 wlc->band = wlc->bandstate[bandunit];
3920
3921 if (!wlc->pub->up)
3922 return;
3923
3924 /* wait for at least one beacon before entering sleeping state */
3925 brcms_c_set_ps_ctrl(wlc);
3926
3927 /* band-specific initializations */
3928 brcms_c_bsinit(wlc);
3929 }
3930
3931 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3932 {
3933 uint bandunit;
3934 bool switchband = false;
3935 u16 old_chanspec = wlc->chanspec;
3936
3937 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3938 wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n",
3939 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3940 return;
3941 }
3942
3943 /* Switch bands if necessary */
3944 if (wlc->pub->_nbands > 1) {
3945 bandunit = chspec_bandunit(chanspec);
3946 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3947 switchband = true;
3948 if (wlc->bandlocked) {
3949 wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d "
3950 "band is locked!\n",
3951 wlc->pub->unit, __func__,
3952 CHSPEC_CHANNEL(chanspec));
3953 return;
3954 }
3955 /*
3956 * should the setband call come after the
3957 * brcms_b_chanspec() ? if the setband updates
3958 * (brcms_c_bsinit) use low level calls to inspect and
3959 * set state, the state inspected may be from the wrong
3960 * band, or the following brcms_b_set_chanspec() may
3961 * undo the work.
3962 */
3963 brcms_c_setband(wlc, bandunit);
3964 }
3965 }
3966
3967 /* sync up phy/radio chanspec */
3968 brcms_c_set_phy_chanspec(wlc, chanspec);
3969
3970 /* init antenna selection */
3971 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3972 brcms_c_antsel_init(wlc->asi);
3973
3974 /* Fix the hardware rateset based on bw.
3975 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3976 */
3977 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3978 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3979 }
3980
3981 /* update some mac configuration since chanspec changed */
3982 brcms_c_ucode_mac_upd(wlc);
3983 }
3984
3985 /*
3986 * This function changes the phytxctl for beacon based on current
3987 * beacon ratespec AND txant setting as per this table:
3988 * ratespec CCK ant = wlc->stf->txant
3989 * OFDM ant = 3
3990 */
3991 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3992 u32 bcn_rspec)
3993 {
3994 u16 phyctl;
3995 u16 phytxant = wlc->stf->phytxant;
3996 u16 mask = PHY_TXC_ANT_MASK;
3997
3998 /* for non-siso rates or default setting, use the available chains */
3999 if (BRCMS_PHY_11N_CAP(wlc->band))
4000 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
4001
4002 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
4003 phyctl = (phyctl & ~mask) | phytxant;
4004 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
4005 }
4006
4007 /*
4008 * centralized protection config change function to simplify debugging, no
4009 * consistency checking this should be called only on changes to avoid overhead
4010 * in periodic function
4011 */
4012 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
4013 {
4014 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
4015
4016 switch (idx) {
4017 case BRCMS_PROT_G_SPEC:
4018 wlc->protection->_g = (bool) val;
4019 break;
4020 case BRCMS_PROT_G_OVR:
4021 wlc->protection->g_override = (s8) val;
4022 break;
4023 case BRCMS_PROT_G_USER:
4024 wlc->protection->gmode_user = (u8) val;
4025 break;
4026 case BRCMS_PROT_OVERLAP:
4027 wlc->protection->overlap = (s8) val;
4028 break;
4029 case BRCMS_PROT_N_USER:
4030 wlc->protection->nmode_user = (s8) val;
4031 break;
4032 case BRCMS_PROT_N_CFG:
4033 wlc->protection->n_cfg = (s8) val;
4034 break;
4035 case BRCMS_PROT_N_CFG_OVR:
4036 wlc->protection->n_cfg_override = (s8) val;
4037 break;
4038 case BRCMS_PROT_N_NONGF:
4039 wlc->protection->nongf = (bool) val;
4040 break;
4041 case BRCMS_PROT_N_NONGF_OVR:
4042 wlc->protection->nongf_override = (s8) val;
4043 break;
4044 case BRCMS_PROT_N_PAM_OVR:
4045 wlc->protection->n_pam_override = (s8) val;
4046 break;
4047 case BRCMS_PROT_N_OBSS:
4048 wlc->protection->n_obss = (bool) val;
4049 break;
4050
4051 default:
4052 break;
4053 }
4054
4055 }
4056
4057 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4058 {
4059 if (wlc->pub->up) {
4060 brcms_c_update_beacon(wlc);
4061 brcms_c_update_probe_resp(wlc, true);
4062 }
4063 }
4064
4065 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4066 {
4067 wlc->stf->ldpc = val;
4068
4069 if (wlc->pub->up) {
4070 brcms_c_update_beacon(wlc);
4071 brcms_c_update_probe_resp(wlc, true);
4072 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4073 }
4074 }
4075
4076 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4077 const struct ieee80211_tx_queue_params *params,
4078 bool suspend)
4079 {
4080 int i;
4081 struct shm_acparams acp_shm;
4082 u16 *shm_entry;
4083
4084 /* Only apply params if the core is out of reset and has clocks */
4085 if (!wlc->clk) {
4086 wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit,
4087 __func__);
4088 return;
4089 }
4090
4091 memset((char *)&acp_shm, 0, sizeof(struct shm_acparams));
4092 /* fill in shm ac params struct */
4093 acp_shm.txop = params->txop;
4094 /* convert from units of 32us to us for ucode */
4095 wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4096 EDCF_TXOP2USEC(acp_shm.txop);
4097 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4098
4099 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4100 && acp_shm.aifs < EDCF_AIFSN_MAX)
4101 acp_shm.aifs++;
4102
4103 if (acp_shm.aifs < EDCF_AIFSN_MIN
4104 || acp_shm.aifs > EDCF_AIFSN_MAX) {
4105 wiphy_err(wlc->wiphy, "wl%d: edcf_setparams: bad "
4106 "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4107 } else {
4108 acp_shm.cwmin = params->cw_min;
4109 acp_shm.cwmax = params->cw_max;
4110 acp_shm.cwcur = acp_shm.cwmin;
4111 acp_shm.bslots =
4112 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4113 acp_shm.cwcur;
4114 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4115 /* Indicate the new params to the ucode */
4116 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4117 wme_ac2fifo[aci] *
4118 M_EDCF_QLEN +
4119 M_EDCF_STATUS_OFF));
4120 acp_shm.status |= WME_STATUS_NEWAC;
4121
4122 /* Fill in shm acparam table */
4123 shm_entry = (u16 *) &acp_shm;
4124 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4125 brcms_b_write_shm(wlc->hw,
4126 M_EDCF_QINFO +
4127 wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4128 *shm_entry++);
4129 }
4130
4131 if (suspend) {
4132 brcms_c_suspend_mac_and_wait(wlc);
4133 brcms_c_enable_mac(wlc);
4134 }
4135 }
4136
4137 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4138 {
4139 u16 aci;
4140 int i_ac;
4141 struct ieee80211_tx_queue_params txq_pars;
4142 static const struct edcf_acparam default_edcf_acparams[] = {
4143 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4144 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4145 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4146 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4147 }; /* ucode needs these parameters during its initialization */
4148 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4149
4150 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4151 /* find out which ac this set of params applies to */
4152 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4153
4154 /* fill in shm ac params struct */
4155 txq_pars.txop = edcf_acp->TXOP;
4156 txq_pars.aifs = edcf_acp->ACI;
4157
4158 /* CWmin = 2^(ECWmin) - 1 */
4159 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4160 /* CWmax = 2^(ECWmax) - 1 */
4161 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4162 >> EDCF_ECWMAX_SHIFT);
4163 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4164 }
4165
4166 if (suspend) {
4167 brcms_c_suspend_mac_and_wait(wlc);
4168 brcms_c_enable_mac(wlc);
4169 }
4170 }
4171
4172 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4173 {
4174 /* Don't start the timer if HWRADIO feature is disabled */
4175 if (wlc->radio_monitor)
4176 return;
4177
4178 wlc->radio_monitor = true;
4179 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4180 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4181 }
4182
4183 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4184 {
4185 if (!wlc->radio_monitor)
4186 return true;
4187
4188 wlc->radio_monitor = false;
4189 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4190 return brcms_del_timer(wlc->radio_timer);
4191 }
4192
4193 /* read hwdisable state and propagate to wlc flag */
4194 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4195 {
4196 if (wlc->pub->hw_off)
4197 return;
4198
4199 if (brcms_b_radio_read_hwdisabled(wlc->hw))
4200 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4201 else
4202 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4203 }
4204
4205 /* update hwradio status and return it */
4206 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4207 {
4208 brcms_c_radio_hwdisable_upd(wlc);
4209
4210 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4211 true : false;
4212 }
4213
4214 /* periodical query hw radio button while driver is "down" */
4215 static void brcms_c_radio_timer(void *arg)
4216 {
4217 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4218
4219 if (brcms_deviceremoved(wlc)) {
4220 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4221 __func__);
4222 brcms_down(wlc->wl);
4223 return;
4224 }
4225
4226 brcms_c_radio_hwdisable_upd(wlc);
4227 }
4228
4229 /* common low-level watchdog code */
4230 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4231 {
4232 struct brcms_hardware *wlc_hw = wlc->hw;
4233
4234 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
4235
4236 if (!wlc_hw->up)
4237 return;
4238
4239 /* increment second count */
4240 wlc_hw->now++;
4241
4242 /* Check for FIFO error interrupts */
4243 brcms_b_fifoerrors(wlc_hw);
4244
4245 /* make sure RX dma has buffers */
4246 dma_rxfill(wlc->hw->di[RX_FIFO]);
4247
4248 wlc_phy_watchdog(wlc_hw->band->pi);
4249 }
4250
4251 /* common watchdog code */
4252 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4253 {
4254 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
4255
4256 if (!wlc->pub->up)
4257 return;
4258
4259 if (brcms_deviceremoved(wlc)) {
4260 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4261 __func__);
4262 brcms_down(wlc->wl);
4263 return;
4264 }
4265
4266 /* increment second count */
4267 wlc->pub->now++;
4268
4269 brcms_c_radio_hwdisable_upd(wlc);
4270 /* if radio is disable, driver may be down, quit here */
4271 if (wlc->pub->radio_disabled)
4272 return;
4273
4274 brcms_b_watchdog(wlc);
4275
4276 /*
4277 * occasionally sample mac stat counters to
4278 * detect 16-bit counter wrap
4279 */
4280 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4281 brcms_c_statsupd(wlc);
4282
4283 if (BRCMS_ISNPHY(wlc->band) &&
4284 ((wlc->pub->now - wlc->tempsense_lasttime) >=
4285 BRCMS_TEMPSENSE_PERIOD)) {
4286 wlc->tempsense_lasttime = wlc->pub->now;
4287 brcms_c_tempsense_upd(wlc);
4288 }
4289 }
4290
4291 static void brcms_c_watchdog_by_timer(void *arg)
4292 {
4293 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4294
4295 brcms_c_watchdog(wlc);
4296 }
4297
4298 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4299 {
4300 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4301 wlc, "watchdog");
4302 if (!wlc->wdtimer) {
4303 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
4304 "failed\n", unit);
4305 goto fail;
4306 }
4307
4308 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4309 wlc, "radio");
4310 if (!wlc->radio_timer) {
4311 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
4312 "failed\n", unit);
4313 goto fail;
4314 }
4315
4316 return true;
4317
4318 fail:
4319 return false;
4320 }
4321
4322 /*
4323 * Initialize brcms_c_info default values ...
4324 * may get overrides later in this function
4325 */
4326 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4327 {
4328 int i;
4329
4330 /* Save our copy of the chanspec */
4331 wlc->chanspec = ch20mhz_chspec(1);
4332
4333 /* various 802.11g modes */
4334 wlc->shortslot = false;
4335 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4336
4337 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4338 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4339
4340 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4341 BRCMS_PROTECTION_AUTO);
4342 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4343 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4344 BRCMS_PROTECTION_AUTO);
4345 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4346 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4347
4348 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4349 BRCMS_PROTECTION_CTL_OVERLAP);
4350
4351 /* 802.11g draft 4.0 NonERP elt advertisement */
4352 wlc->include_legacy_erp = true;
4353
4354 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4355 wlc->stf->txant = ANT_TX_DEF;
4356
4357 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4358
4359 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4360 for (i = 0; i < NFIFO; i++)
4361 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4362 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4363
4364 /* default rate fallback retry limits */
4365 wlc->SFBL = RETRY_SHORT_FB;
4366 wlc->LFBL = RETRY_LONG_FB;
4367
4368 /* default mac retry limits */
4369 wlc->SRL = RETRY_SHORT_DEF;
4370 wlc->LRL = RETRY_LONG_DEF;
4371
4372 /* WME QoS mode is Auto by default */
4373 wlc->pub->_ampdu = AMPDU_AGG_HOST;
4374 wlc->pub->bcmerror = 0;
4375 }
4376
4377 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4378 {
4379 uint err = 0;
4380 uint unit;
4381 unit = wlc->pub->unit;
4382
4383 wlc->asi = brcms_c_antsel_attach(wlc);
4384 if (wlc->asi == NULL) {
4385 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4386 "failed\n", unit);
4387 err = 44;
4388 goto fail;
4389 }
4390
4391 wlc->ampdu = brcms_c_ampdu_attach(wlc);
4392 if (wlc->ampdu == NULL) {
4393 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4394 "failed\n", unit);
4395 err = 50;
4396 goto fail;
4397 }
4398
4399 if ((brcms_c_stf_attach(wlc) != 0)) {
4400 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4401 "failed\n", unit);
4402 err = 68;
4403 goto fail;
4404 }
4405 fail:
4406 return err;
4407 }
4408
4409 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4410 {
4411 return wlc->pub;
4412 }
4413
4414 /* low level attach
4415 * run backplane attach, init nvram
4416 * run phy attach
4417 * initialize software state for each core and band
4418 * put the whole chip in reset(driver down state), no clock
4419 */
4420 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4421 uint unit, bool piomode)
4422 {
4423 struct brcms_hardware *wlc_hw;
4424 uint err = 0;
4425 uint j;
4426 bool wme = false;
4427 struct shared_phy_params sha_params;
4428 struct wiphy *wiphy = wlc->wiphy;
4429 struct pci_dev *pcidev = core->bus->host_pci;
4430 struct ssb_sprom *sprom = &core->bus->sprom;
4431
4432 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4433 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
4434 pcidev->vendor,
4435 pcidev->device);
4436 else
4437 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
4438 core->bus->boardinfo.vendor,
4439 core->bus->boardinfo.type);
4440
4441 wme = true;
4442
4443 wlc_hw = wlc->hw;
4444 wlc_hw->wlc = wlc;
4445 wlc_hw->unit = unit;
4446 wlc_hw->band = wlc_hw->bandstate[0];
4447 wlc_hw->_piomode = piomode;
4448
4449 /* populate struct brcms_hardware with default values */
4450 brcms_b_info_init(wlc_hw);
4451
4452 /*
4453 * Do the hardware portion of the attach. Also initialize software
4454 * state that depends on the particular hardware we are running.
4455 */
4456 wlc_hw->sih = ai_attach(core->bus);
4457 if (wlc_hw->sih == NULL) {
4458 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4459 unit);
4460 err = 11;
4461 goto fail;
4462 }
4463
4464 /* verify again the device is supported */
4465 if (!brcms_c_chipmatch(core)) {
4466 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4467 unit);
4468 err = 12;
4469 goto fail;
4470 }
4471
4472 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4473 wlc_hw->vendorid = pcidev->vendor;
4474 wlc_hw->deviceid = pcidev->device;
4475 } else {
4476 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4477 wlc_hw->deviceid = core->bus->boardinfo.type;
4478 }
4479
4480 wlc_hw->d11core = core;
4481 wlc_hw->corerev = core->id.rev;
4482
4483 /* validate chip, chiprev and corerev */
4484 if (!brcms_c_isgoodchip(wlc_hw)) {
4485 err = 13;
4486 goto fail;
4487 }
4488
4489 /* initialize power control registers */
4490 ai_clkctl_init(wlc_hw->sih);
4491
4492 /* request fastclock and force fastclock for the rest of attach
4493 * bring the d11 core out of reset.
4494 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4495 * is still false; But it will be called again inside wlc_corereset,
4496 * after d11 is out of reset.
4497 */
4498 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4499 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4500
4501 if (!brcms_b_validate_chip_access(wlc_hw)) {
4502 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4503 "failed\n", unit);
4504 err = 14;
4505 goto fail;
4506 }
4507
4508 /* get the board rev, used just below */
4509 j = sprom->board_rev;
4510 /* promote srom boardrev of 0xFF to 1 */
4511 if (j == BOARDREV_PROMOTABLE)
4512 j = BOARDREV_PROMOTED;
4513 wlc_hw->boardrev = (u16) j;
4514 if (!brcms_c_validboardtype(wlc_hw)) {
4515 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4516 "board type (0x%x)" " or revision level (0x%x)\n",
4517 unit, ai_get_boardtype(wlc_hw->sih),
4518 wlc_hw->boardrev);
4519 err = 15;
4520 goto fail;
4521 }
4522 wlc_hw->sromrev = sprom->revision;
4523 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4524 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4525
4526 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4527 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4528
4529 /* check device id(srom, nvram etc.) to set bands */
4530 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4531 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1)
4532 /* Dualband boards */
4533 wlc_hw->_nbands = 2;
4534 else
4535 wlc_hw->_nbands = 1;
4536
4537 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4538 wlc_hw->_nbands = 1;
4539
4540 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4541 * unconditionally does the init of these values
4542 */
4543 wlc->vendorid = wlc_hw->vendorid;
4544 wlc->deviceid = wlc_hw->deviceid;
4545 wlc->pub->sih = wlc_hw->sih;
4546 wlc->pub->corerev = wlc_hw->corerev;
4547 wlc->pub->sromrev = wlc_hw->sromrev;
4548 wlc->pub->boardrev = wlc_hw->boardrev;
4549 wlc->pub->boardflags = wlc_hw->boardflags;
4550 wlc->pub->boardflags2 = wlc_hw->boardflags2;
4551 wlc->pub->_nbands = wlc_hw->_nbands;
4552
4553 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4554
4555 if (wlc_hw->physhim == NULL) {
4556 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4557 "failed\n", unit);
4558 err = 25;
4559 goto fail;
4560 }
4561
4562 /* pass all the parameters to wlc_phy_shared_attach in one struct */
4563 sha_params.sih = wlc_hw->sih;
4564 sha_params.physhim = wlc_hw->physhim;
4565 sha_params.unit = unit;
4566 sha_params.corerev = wlc_hw->corerev;
4567 sha_params.vid = wlc_hw->vendorid;
4568 sha_params.did = wlc_hw->deviceid;
4569 sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4570 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4571 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4572 sha_params.sromrev = wlc_hw->sromrev;
4573 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4574 sha_params.boardrev = wlc_hw->boardrev;
4575 sha_params.boardflags = wlc_hw->boardflags;
4576 sha_params.boardflags2 = wlc_hw->boardflags2;
4577
4578 /* alloc and save pointer to shared phy state area */
4579 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4580 if (!wlc_hw->phy_sh) {
4581 err = 16;
4582 goto fail;
4583 }
4584
4585 /* initialize software state for each core and band */
4586 for (j = 0; j < wlc_hw->_nbands; j++) {
4587 /*
4588 * band0 is always 2.4Ghz
4589 * band1, if present, is 5Ghz
4590 */
4591
4592 brcms_c_setxband(wlc_hw, j);
4593
4594 wlc_hw->band->bandunit = j;
4595 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4596 wlc->band->bandunit = j;
4597 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4598 wlc->core->coreidx = core->core_index;
4599
4600 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4601 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4602
4603 /* init tx fifo size */
4604 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
4605 (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4606 ARRAY_SIZE(xmtfifo_sz));
4607 wlc_hw->xmtfifo_sz =
4608 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4609 WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4610
4611 /* Get a phy for this band */
4612 wlc_hw->band->pi =
4613 wlc_phy_attach(wlc_hw->phy_sh, core,
4614 wlc_hw->band->bandtype,
4615 wlc->wiphy);
4616 if (wlc_hw->band->pi == NULL) {
4617 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4618 "attach failed\n", unit);
4619 err = 17;
4620 goto fail;
4621 }
4622
4623 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4624
4625 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4626 &wlc_hw->band->phyrev,
4627 &wlc_hw->band->radioid,
4628 &wlc_hw->band->radiorev);
4629 wlc_hw->band->abgphy_encore =
4630 wlc_phy_get_encore(wlc_hw->band->pi);
4631 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4632 wlc_hw->band->core_flags =
4633 wlc_phy_get_coreflags(wlc_hw->band->pi);
4634
4635 /* verify good phy_type & supported phy revision */
4636 if (BRCMS_ISNPHY(wlc_hw->band)) {
4637 if (NCONF_HAS(wlc_hw->band->phyrev))
4638 goto good_phy;
4639 else
4640 goto bad_phy;
4641 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4642 if (LCNCONF_HAS(wlc_hw->band->phyrev))
4643 goto good_phy;
4644 else
4645 goto bad_phy;
4646 } else {
4647 bad_phy:
4648 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4649 "phy type/rev (%d/%d)\n", unit,
4650 wlc_hw->band->phytype, wlc_hw->band->phyrev);
4651 err = 18;
4652 goto fail;
4653 }
4654
4655 good_phy:
4656 /*
4657 * BMAC_NOTE: wlc->band->pi should not be set below and should
4658 * be done in the high level attach. However we can not make
4659 * that change until all low level access is changed to
4660 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4661 * keeping wlc_hw->band->pi as well for incremental update of
4662 * low level fns, and cut over low only init when all fns
4663 * updated.
4664 */
4665 wlc->band->pi = wlc_hw->band->pi;
4666 wlc->band->phytype = wlc_hw->band->phytype;
4667 wlc->band->phyrev = wlc_hw->band->phyrev;
4668 wlc->band->radioid = wlc_hw->band->radioid;
4669 wlc->band->radiorev = wlc_hw->band->radiorev;
4670
4671 /* default contention windows size limits */
4672 wlc_hw->band->CWmin = APHY_CWMIN;
4673 wlc_hw->band->CWmax = PHY_CWMAX;
4674
4675 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4676 err = 19;
4677 goto fail;
4678 }
4679 }
4680
4681 /* disable core to match driver "down" state */
4682 brcms_c_coredisable(wlc_hw);
4683
4684 /* Match driver "down" state */
4685 ai_pci_down(wlc_hw->sih);
4686
4687 /* turn off pll and xtal to match driver "down" state */
4688 brcms_b_xtal(wlc_hw, OFF);
4689
4690 /* *******************************************************************
4691 * The hardware is in the DOWN state at this point. D11 core
4692 * or cores are in reset with clocks off, and the board PLLs
4693 * are off if possible.
4694 *
4695 * Beyond this point, wlc->sbclk == false and chip registers
4696 * should not be touched.
4697 *********************************************************************
4698 */
4699
4700 /* init etheraddr state variables */
4701 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4702
4703 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4704 is_zero_ether_addr(wlc_hw->etheraddr)) {
4705 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4706 unit);
4707 err = 22;
4708 goto fail;
4709 }
4710
4711 BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x\n",
4712 wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih));
4713
4714 return err;
4715
4716 fail:
4717 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4718 err);
4719 return err;
4720 }
4721
4722 static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4723 {
4724 uint unit;
4725 unit = wlc->pub->unit;
4726
4727 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4728 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4729 wlc->band->antgain = 8;
4730 } else if (wlc->band->antgain == -1) {
4731 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4732 " srom, using 2dB\n", unit, __func__);
4733 wlc->band->antgain = 8;
4734 } else {
4735 s8 gain, fract;
4736 /* Older sroms specified gain in whole dbm only. In order
4737 * be able to specify qdbm granularity and remain backward
4738 * compatible the whole dbms are now encoded in only
4739 * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4740 * 6 bit signed number ranges from -32 - 31.
4741 *
4742 * Examples:
4743 * 0x1 = 1 db,
4744 * 0xc1 = 1.75 db (1 + 3 quarters),
4745 * 0x3f = -1 (-1 + 0 quarters),
4746 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4747 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4748 */
4749 gain = wlc->band->antgain & 0x3f;
4750 gain <<= 2; /* Sign extend */
4751 gain >>= 2;
4752 fract = (wlc->band->antgain & 0xc0) >> 6;
4753 wlc->band->antgain = 4 * gain + fract;
4754 }
4755 }
4756
4757 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4758 {
4759 int aa;
4760 uint unit;
4761 int bandtype;
4762 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4763
4764 unit = wlc->pub->unit;
4765 bandtype = wlc->band->bandtype;
4766
4767 /* get antennas available */
4768 if (bandtype == BRCM_BAND_5G)
4769 aa = sprom->ant_available_a;
4770 else
4771 aa = sprom->ant_available_bg;
4772
4773 if ((aa < 1) || (aa > 15)) {
4774 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4775 " srom (0x%x), using 3\n", unit, __func__, aa);
4776 aa = 3;
4777 }
4778
4779 /* reset the defaults if we have a single antenna */
4780 if (aa == 1) {
4781 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4782 wlc->stf->txant = ANT_TX_FORCE_0;
4783 } else if (aa == 2) {
4784 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4785 wlc->stf->txant = ANT_TX_FORCE_1;
4786 } else {
4787 }
4788
4789 /* Compute Antenna Gain */
4790 if (bandtype == BRCM_BAND_5G)
4791 wlc->band->antgain = sprom->antenna_gain.a1;
4792 else
4793 wlc->band->antgain = sprom->antenna_gain.a0;
4794
4795 brcms_c_attach_antgain_init(wlc);
4796
4797 return true;
4798 }
4799
4800 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4801 {
4802 u16 chanspec;
4803 struct brcms_band *band;
4804 struct brcms_bss_info *bi = wlc->default_bss;
4805
4806 /* init default and target BSS with some sane initial values */
4807 memset((char *)(bi), 0, sizeof(struct brcms_bss_info));
4808 bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4809
4810 /* fill the default channel as the first valid channel
4811 * starting from the 2G channels
4812 */
4813 chanspec = ch20mhz_chspec(1);
4814 wlc->home_chanspec = bi->chanspec = chanspec;
4815
4816 /* find the band of our default channel */
4817 band = wlc->band;
4818 if (wlc->pub->_nbands > 1 &&
4819 band->bandunit != chspec_bandunit(chanspec))
4820 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4821
4822 /* init bss rates to the band specific default rate set */
4823 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4824 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4825 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4826 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4827
4828 if (wlc->pub->_n_enab & SUPPORT_11N)
4829 bi->flags |= BRCMS_BSS_HT;
4830 }
4831
4832 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4833 {
4834 uint i;
4835 struct brcms_band *band;
4836
4837 for (i = 0; i < wlc->pub->_nbands; i++) {
4838 band = wlc->bandstate[i];
4839 if (band->bandtype == BRCM_BAND_5G) {
4840 if ((bwcap == BRCMS_N_BW_40ALL)
4841 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4842 band->mimo_cap_40 = true;
4843 else
4844 band->mimo_cap_40 = false;
4845 } else {
4846 if (bwcap == BRCMS_N_BW_40ALL)
4847 band->mimo_cap_40 = true;
4848 else
4849 band->mimo_cap_40 = false;
4850 }
4851 }
4852 }
4853
4854 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4855 {
4856 /* free timer state */
4857 if (wlc->wdtimer) {
4858 brcms_free_timer(wlc->wdtimer);
4859 wlc->wdtimer = NULL;
4860 }
4861 if (wlc->radio_timer) {
4862 brcms_free_timer(wlc->radio_timer);
4863 wlc->radio_timer = NULL;
4864 }
4865 }
4866
4867 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4868 {
4869 if (wlc->asi) {
4870 brcms_c_antsel_detach(wlc->asi);
4871 wlc->asi = NULL;
4872 }
4873
4874 if (wlc->ampdu) {
4875 brcms_c_ampdu_detach(wlc->ampdu);
4876 wlc->ampdu = NULL;
4877 }
4878
4879 brcms_c_stf_detach(wlc);
4880 }
4881
4882 /*
4883 * low level detach
4884 */
4885 static int brcms_b_detach(struct brcms_c_info *wlc)
4886 {
4887 uint i;
4888 struct brcms_hw_band *band;
4889 struct brcms_hardware *wlc_hw = wlc->hw;
4890 int callbacks;
4891
4892 callbacks = 0;
4893
4894 brcms_b_detach_dmapio(wlc_hw);
4895
4896 band = wlc_hw->band;
4897 for (i = 0; i < wlc_hw->_nbands; i++) {
4898 if (band->pi) {
4899 /* Detach this band's phy */
4900 wlc_phy_detach(band->pi);
4901 band->pi = NULL;
4902 }
4903 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4904 }
4905
4906 /* Free shared phy state */
4907 kfree(wlc_hw->phy_sh);
4908
4909 wlc_phy_shim_detach(wlc_hw->physhim);
4910
4911 if (wlc_hw->sih) {
4912 ai_detach(wlc_hw->sih);
4913 wlc_hw->sih = NULL;
4914 }
4915
4916 return callbacks;
4917
4918 }
4919
4920 /*
4921 * Return a count of the number of driver callbacks still pending.
4922 *
4923 * General policy is that brcms_c_detach can only dealloc/free software states.
4924 * It can NOT touch hardware registers since the d11core may be in reset and
4925 * clock may not be available.
4926 * One exception is sb register access, which is possible if crystal is turned
4927 * on after "down" state, driver should avoid software timer with the exception
4928 * of radio_monitor.
4929 */
4930 uint brcms_c_detach(struct brcms_c_info *wlc)
4931 {
4932 uint callbacks = 0;
4933
4934 if (wlc == NULL)
4935 return 0;
4936
4937 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
4938
4939 callbacks += brcms_b_detach(wlc);
4940
4941 /* delete software timers */
4942 if (!brcms_c_radio_monitor_stop(wlc))
4943 callbacks++;
4944
4945 brcms_c_channel_mgr_detach(wlc->cmi);
4946
4947 brcms_c_timers_deinit(wlc);
4948
4949 brcms_c_detach_module(wlc);
4950
4951 brcms_c_detach_mfree(wlc);
4952 return callbacks;
4953 }
4954
4955 /* update state that depends on the current value of "ap" */
4956 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
4957 {
4958 /* STA-BSS; short capable */
4959 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
4960 }
4961
4962 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4963 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4964 {
4965 if (wlc_hw->wlc->pub->hw_up)
4966 return;
4967
4968 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
4969
4970 /*
4971 * Enable pll and xtal, initialize the power control registers,
4972 * and force fastclock for the remainder of brcms_c_up().
4973 */
4974 brcms_b_xtal(wlc_hw, ON);
4975 ai_clkctl_init(wlc_hw->sih);
4976 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4977
4978 /*
4979 * TODO: test suspend/resume
4980 *
4981 * AI chip doesn't restore bar0win2 on
4982 * hibernation/resume, need sw fixup
4983 */
4984
4985 /*
4986 * Inform phy that a POR reset has occurred so
4987 * it does a complete phy init
4988 */
4989 wlc_phy_por_inform(wlc_hw->band->pi);
4990
4991 wlc_hw->ucode_loaded = false;
4992 wlc_hw->wlc->pub->hw_up = true;
4993
4994 if ((wlc_hw->boardflags & BFL_FEM)
4995 && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
4996 if (!
4997 (wlc_hw->boardrev >= 0x1250
4998 && (wlc_hw->boardflags & BFL_FEM_BT)))
4999 ai_epa_4313war(wlc_hw->sih);
5000 }
5001 }
5002
5003 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
5004 {
5005 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5006
5007 /*
5008 * Enable pll and xtal, initialize the power control registers,
5009 * and force fastclock for the remainder of brcms_c_up().
5010 */
5011 brcms_b_xtal(wlc_hw, ON);
5012 ai_clkctl_init(wlc_hw->sih);
5013 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5014
5015 /*
5016 * Configure pci/pcmcia here instead of in brcms_c_attach()
5017 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
5018 */
5019 bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
5020 true);
5021
5022 /*
5023 * Need to read the hwradio status here to cover the case where the
5024 * system is loaded with the hw radio disabled. We do not want to
5025 * bring the driver up in this case.
5026 */
5027 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
5028 /* put SB PCI in down state again */
5029 ai_pci_down(wlc_hw->sih);
5030 brcms_b_xtal(wlc_hw, OFF);
5031 return -ENOMEDIUM;
5032 }
5033
5034 ai_pci_up(wlc_hw->sih);
5035
5036 /* reset the d11 core */
5037 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5038
5039 return 0;
5040 }
5041
5042 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5043 {
5044 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5045
5046 wlc_hw->up = true;
5047 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5048
5049 /* FULLY enable dynamic power control and d11 core interrupt */
5050 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5051 brcms_intrson(wlc_hw->wlc->wl);
5052 return 0;
5053 }
5054
5055 /*
5056 * Write WME tunable parameters for retransmit/max rate
5057 * from wlc struct to ucode
5058 */
5059 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5060 {
5061 int ac;
5062
5063 /* Need clock to do this */
5064 if (!wlc->clk)
5065 return;
5066
5067 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5068 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5069 wlc->wme_retries[ac]);
5070 }
5071
5072 /* make interface operational */
5073 int brcms_c_up(struct brcms_c_info *wlc)
5074 {
5075 struct ieee80211_channel *ch;
5076
5077 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5078
5079 /* HW is turned off so don't try to access it */
5080 if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5081 return -ENOMEDIUM;
5082
5083 if (!wlc->pub->hw_up) {
5084 brcms_b_hw_up(wlc->hw);
5085 wlc->pub->hw_up = true;
5086 }
5087
5088 if ((wlc->pub->boardflags & BFL_FEM)
5089 && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5090 if (wlc->pub->boardrev >= 0x1250
5091 && (wlc->pub->boardflags & BFL_FEM_BT))
5092 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5093 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5094 else
5095 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5096 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5097 }
5098
5099 /*
5100 * Need to read the hwradio status here to cover the case where the
5101 * system is loaded with the hw radio disabled. We do not want to bring
5102 * the driver up in this case. If radio is disabled, abort up, lower
5103 * power, start radio timer and return 0(for NDIS) don't call
5104 * radio_update to avoid looping brcms_c_up.
5105 *
5106 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5107 */
5108 if (!wlc->pub->radio_disabled) {
5109 int status = brcms_b_up_prep(wlc->hw);
5110 if (status == -ENOMEDIUM) {
5111 if (!mboolisset
5112 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5113 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5114 mboolset(wlc->pub->radio_disabled,
5115 WL_RADIO_HW_DISABLE);
5116
5117 if (bsscfg->enable && bsscfg->BSS)
5118 wiphy_err(wlc->wiphy, "wl%d: up"
5119 ": rfdisable -> "
5120 "bsscfg_disable()\n",
5121 wlc->pub->unit);
5122 }
5123 }
5124 }
5125
5126 if (wlc->pub->radio_disabled) {
5127 brcms_c_radio_monitor_start(wlc);
5128 return 0;
5129 }
5130
5131 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5132 wlc->clk = true;
5133
5134 brcms_c_radio_monitor_stop(wlc);
5135
5136 /* Set EDCF hostflags */
5137 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5138
5139 brcms_init(wlc->wl);
5140 wlc->pub->up = true;
5141
5142 if (wlc->bandinit_pending) {
5143 ch = wlc->pub->ieee_hw->conf.channel;
5144 brcms_c_suspend_mac_and_wait(wlc);
5145 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5146 wlc->bandinit_pending = false;
5147 brcms_c_enable_mac(wlc);
5148 }
5149
5150 brcms_b_up_finish(wlc->hw);
5151
5152 /* Program the TX wme params with the current settings */
5153 brcms_c_wme_retries_write(wlc);
5154
5155 /* start one second watchdog timer */
5156 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5157 wlc->WDarmed = true;
5158
5159 /* ensure antenna config is up to date */
5160 brcms_c_stf_phy_txant_upd(wlc);
5161 /* ensure LDPC config is in sync */
5162 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5163
5164 return 0;
5165 }
5166
5167 static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5168 {
5169 uint callbacks = 0;
5170
5171 return callbacks;
5172 }
5173
5174 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5175 {
5176 bool dev_gone;
5177 uint callbacks = 0;
5178
5179 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5180
5181 if (!wlc_hw->up)
5182 return callbacks;
5183
5184 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5185
5186 /* disable interrupts */
5187 if (dev_gone)
5188 wlc_hw->wlc->macintmask = 0;
5189 else {
5190 /* now disable interrupts */
5191 brcms_intrsoff(wlc_hw->wlc->wl);
5192
5193 /* ensure we're running on the pll clock again */
5194 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5195 }
5196 /* down phy at the last of this stage */
5197 callbacks += wlc_phy_down(wlc_hw->band->pi);
5198
5199 return callbacks;
5200 }
5201
5202 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5203 {
5204 uint callbacks = 0;
5205 bool dev_gone;
5206
5207 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5208
5209 if (!wlc_hw->up)
5210 return callbacks;
5211
5212 wlc_hw->up = false;
5213 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5214
5215 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5216
5217 if (dev_gone) {
5218 wlc_hw->sbclk = false;
5219 wlc_hw->clk = false;
5220 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5221
5222 /* reclaim any posted packets */
5223 brcms_c_flushqueues(wlc_hw->wlc);
5224 } else {
5225
5226 /* Reset and disable the core */
5227 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5228 if (bcma_read32(wlc_hw->d11core,
5229 D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5230 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5231 callbacks += brcms_reset(wlc_hw->wlc->wl);
5232 brcms_c_coredisable(wlc_hw);
5233 }
5234
5235 /* turn off primary xtal and pll */
5236 if (!wlc_hw->noreset) {
5237 ai_pci_down(wlc_hw->sih);
5238 brcms_b_xtal(wlc_hw, OFF);
5239 }
5240 }
5241
5242 return callbacks;
5243 }
5244
5245 /*
5246 * Mark the interface nonoperational, stop the software mechanisms,
5247 * disable the hardware, free any transient buffer state.
5248 * Return a count of the number of driver callbacks still pending.
5249 */
5250 uint brcms_c_down(struct brcms_c_info *wlc)
5251 {
5252
5253 uint callbacks = 0;
5254 int i;
5255 bool dev_gone = false;
5256
5257 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5258
5259 /* check if we are already in the going down path */
5260 if (wlc->going_down) {
5261 wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return"
5262 "\n", wlc->pub->unit, __func__);
5263 return 0;
5264 }
5265 if (!wlc->pub->up)
5266 return callbacks;
5267
5268 wlc->going_down = true;
5269
5270 callbacks += brcms_b_bmac_down_prep(wlc->hw);
5271
5272 dev_gone = brcms_deviceremoved(wlc);
5273
5274 /* Call any registered down handlers */
5275 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5276 if (wlc->modulecb[i].down_fn)
5277 callbacks +=
5278 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5279 }
5280
5281 /* cancel the watchdog timer */
5282 if (wlc->WDarmed) {
5283 if (!brcms_del_timer(wlc->wdtimer))
5284 callbacks++;
5285 wlc->WDarmed = false;
5286 }
5287 /* cancel all other timers */
5288 callbacks += brcms_c_down_del_timer(wlc);
5289
5290 wlc->pub->up = false;
5291
5292 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5293
5294 callbacks += brcms_b_down_finish(wlc->hw);
5295
5296 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5297 wlc->clk = false;
5298
5299 wlc->going_down = false;
5300 return callbacks;
5301 }
5302
5303 /* Set the current gmode configuration */
5304 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5305 {
5306 int ret = 0;
5307 uint i;
5308 struct brcms_c_rateset rs;
5309 /* Default to 54g Auto */
5310 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5311 s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5312 bool shortslot_restrict = false; /* Restrict association to stations
5313 * that support shortslot
5314 */
5315 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
5316 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5317 int preamble = BRCMS_PLCP_LONG;
5318 bool preamble_restrict = false; /* Restrict association to stations
5319 * that support short preambles
5320 */
5321 struct brcms_band *band;
5322
5323 /* if N-support is enabled, allow Gmode set as long as requested
5324 * Gmode is not GMODE_LEGACY_B
5325 */
5326 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5327 return -ENOTSUPP;
5328
5329 /* verify that we are dealing with 2G band and grab the band pointer */
5330 if (wlc->band->bandtype == BRCM_BAND_2G)
5331 band = wlc->band;
5332 else if ((wlc->pub->_nbands > 1) &&
5333 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5334 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5335 else
5336 return -EINVAL;
5337
5338 /* update configuration value */
5339 if (config)
5340 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5341
5342 /* Clear rateset override */
5343 memset(&rs, 0, sizeof(struct brcms_c_rateset));
5344
5345 switch (gmode) {
5346 case GMODE_LEGACY_B:
5347 shortslot = BRCMS_SHORTSLOT_OFF;
5348 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5349
5350 break;
5351
5352 case GMODE_LRS:
5353 break;
5354
5355 case GMODE_AUTO:
5356 /* Accept defaults */
5357 break;
5358
5359 case GMODE_ONLY:
5360 ofdm_basic = true;
5361 preamble = BRCMS_PLCP_SHORT;
5362 preamble_restrict = true;
5363 break;
5364
5365 case GMODE_PERFORMANCE:
5366 shortslot = BRCMS_SHORTSLOT_ON;
5367 shortslot_restrict = true;
5368 ofdm_basic = true;
5369 preamble = BRCMS_PLCP_SHORT;
5370 preamble_restrict = true;
5371 break;
5372
5373 default:
5374 /* Error */
5375 wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n",
5376 wlc->pub->unit, __func__, gmode);
5377 return -ENOTSUPP;
5378 }
5379
5380 band->gmode = gmode;
5381
5382 wlc->shortslot_override = shortslot;
5383
5384 /* Use the default 11g rateset */
5385 if (!rs.count)
5386 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5387
5388 if (ofdm_basic) {
5389 for (i = 0; i < rs.count; i++) {
5390 if (rs.rates[i] == BRCM_RATE_6M
5391 || rs.rates[i] == BRCM_RATE_12M
5392 || rs.rates[i] == BRCM_RATE_24M)
5393 rs.rates[i] |= BRCMS_RATE_FLAG;
5394 }
5395 }
5396
5397 /* Set default bss rateset */
5398 wlc->default_bss->rateset.count = rs.count;
5399 memcpy(wlc->default_bss->rateset.rates, rs.rates,
5400 sizeof(wlc->default_bss->rateset.rates));
5401
5402 return ret;
5403 }
5404
5405 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5406 {
5407 uint i;
5408 s32 nmode = AUTO;
5409
5410 if (wlc->stf->txstreams == WL_11N_3x3)
5411 nmode = WL_11N_3x3;
5412 else
5413 nmode = WL_11N_2x2;
5414
5415 /* force GMODE_AUTO if NMODE is ON */
5416 brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5417 if (nmode == WL_11N_3x3)
5418 wlc->pub->_n_enab = SUPPORT_HT;
5419 else
5420 wlc->pub->_n_enab = SUPPORT_11N;
5421 wlc->default_bss->flags |= BRCMS_BSS_HT;
5422 /* add the mcs rates to the default and hw ratesets */
5423 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5424 wlc->stf->txstreams);
5425 for (i = 0; i < wlc->pub->_nbands; i++)
5426 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5427 wlc->default_bss->rateset.mcs, MCSSET_LEN);
5428
5429 return 0;
5430 }
5431
5432 static int
5433 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5434 struct brcms_c_rateset *rs_arg)
5435 {
5436 struct brcms_c_rateset rs, new;
5437 uint bandunit;
5438
5439 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5440
5441 /* check for bad count value */
5442 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5443 return -EINVAL;
5444
5445 /* try the current band */
5446 bandunit = wlc->band->bandunit;
5447 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5448 if (brcms_c_rate_hwrs_filter_sort_validate
5449 (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5450 wlc->stf->txstreams))
5451 goto good;
5452
5453 /* try the other band */
5454 if (brcms_is_mband_unlocked(wlc)) {
5455 bandunit = OTHERBANDUNIT(wlc);
5456 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5457 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5458 &wlc->
5459 bandstate[bandunit]->
5460 hw_rateset, true,
5461 wlc->stf->txstreams))
5462 goto good;
5463 }
5464
5465 return -EBADE;
5466
5467 good:
5468 /* apply new rateset */
5469 memcpy(&wlc->default_bss->rateset, &new,
5470 sizeof(struct brcms_c_rateset));
5471 memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5472 sizeof(struct brcms_c_rateset));
5473 return 0;
5474 }
5475
5476 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5477 {
5478 u8 r;
5479 bool war = false;
5480
5481 if (wlc->bsscfg->associated)
5482 r = wlc->bsscfg->current_bss->rateset.rates[0];
5483 else
5484 r = wlc->default_bss->rateset.rates[0];
5485
5486 wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5487 }
5488
5489 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5490 {
5491 u16 chspec = ch20mhz_chspec(channel);
5492
5493 if (channel < 0 || channel > MAXCHANNEL)
5494 return -EINVAL;
5495
5496 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5497 return -EINVAL;
5498
5499
5500 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5501 if (wlc->band->bandunit != chspec_bandunit(chspec))
5502 wlc->bandinit_pending = true;
5503 else
5504 wlc->bandinit_pending = false;
5505 }
5506
5507 wlc->default_bss->chanspec = chspec;
5508 /* brcms_c_BSSinit() will sanitize the rateset before
5509 * using it.. */
5510 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5511 brcms_c_set_home_chanspec(wlc, chspec);
5512 brcms_c_suspend_mac_and_wait(wlc);
5513 brcms_c_set_chanspec(wlc, chspec);
5514 brcms_c_enable_mac(wlc);
5515 }
5516 return 0;
5517 }
5518
5519 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5520 {
5521 int ac;
5522
5523 if (srl < 1 || srl > RETRY_SHORT_MAX ||
5524 lrl < 1 || lrl > RETRY_SHORT_MAX)
5525 return -EINVAL;
5526
5527 wlc->SRL = srl;
5528 wlc->LRL = lrl;
5529
5530 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5531
5532 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5533 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5534 EDCF_SHORT, wlc->SRL);
5535 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5536 EDCF_LONG, wlc->LRL);
5537 }
5538 brcms_c_wme_retries_write(wlc);
5539
5540 return 0;
5541 }
5542
5543 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5544 struct brcm_rateset *currs)
5545 {
5546 struct brcms_c_rateset *rs;
5547
5548 if (wlc->pub->associated)
5549 rs = &wlc->bsscfg->current_bss->rateset;
5550 else
5551 rs = &wlc->default_bss->rateset;
5552
5553 /* Copy only legacy rateset section */
5554 currs->count = rs->count;
5555 memcpy(&currs->rates, &rs->rates, rs->count);
5556 }
5557
5558 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5559 {
5560 struct brcms_c_rateset internal_rs;
5561 int bcmerror;
5562
5563 if (rs->count > BRCMS_NUMRATES)
5564 return -ENOBUFS;
5565
5566 memset(&internal_rs, 0, sizeof(struct brcms_c_rateset));
5567
5568 /* Copy only legacy rateset section */
5569 internal_rs.count = rs->count;
5570 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5571
5572 /* merge rateset coming in with the current mcsset */
5573 if (wlc->pub->_n_enab & SUPPORT_11N) {
5574 struct brcms_bss_info *mcsset_bss;
5575 if (wlc->bsscfg->associated)
5576 mcsset_bss = wlc->bsscfg->current_bss;
5577 else
5578 mcsset_bss = wlc->default_bss;
5579 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5580 MCSSET_LEN);
5581 }
5582
5583 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5584 if (!bcmerror)
5585 brcms_c_ofdm_rateset_war(wlc);
5586
5587 return bcmerror;
5588 }
5589
5590 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5591 {
5592 if (period < DOT11_MIN_BEACON_PERIOD ||
5593 period > DOT11_MAX_BEACON_PERIOD)
5594 return -EINVAL;
5595
5596 wlc->default_bss->beacon_period = period;
5597 return 0;
5598 }
5599
5600 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5601 {
5602 return wlc->band->phytype;
5603 }
5604
5605 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5606 {
5607 wlc->shortslot_override = sslot_override;
5608
5609 /*
5610 * shortslot is an 11g feature, so no more work if we are
5611 * currently on the 5G band
5612 */
5613 if (wlc->band->bandtype == BRCM_BAND_5G)
5614 return;
5615
5616 if (wlc->pub->up && wlc->pub->associated) {
5617 /* let watchdog or beacon processing update shortslot */
5618 } else if (wlc->pub->up) {
5619 /* unassociated shortslot is off */
5620 brcms_c_switch_shortslot(wlc, false);
5621 } else {
5622 /* driver is down, so just update the brcms_c_info
5623 * value */
5624 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5625 wlc->shortslot = false;
5626 else
5627 wlc->shortslot =
5628 (wlc->shortslot_override ==
5629 BRCMS_SHORTSLOT_ON);
5630 }
5631 }
5632
5633 /*
5634 * register watchdog and down handlers.
5635 */
5636 int brcms_c_module_register(struct brcms_pub *pub,
5637 const char *name, struct brcms_info *hdl,
5638 int (*d_fn)(void *handle))
5639 {
5640 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5641 int i;
5642
5643 /* find an empty entry and just add, no duplication check! */
5644 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5645 if (wlc->modulecb[i].name[0] == '\0') {
5646 strncpy(wlc->modulecb[i].name, name,
5647 sizeof(wlc->modulecb[i].name) - 1);
5648 wlc->modulecb[i].hdl = hdl;
5649 wlc->modulecb[i].down_fn = d_fn;
5650 return 0;
5651 }
5652 }
5653
5654 return -ENOSR;
5655 }
5656
5657 /* unregister module callbacks */
5658 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5659 struct brcms_info *hdl)
5660 {
5661 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5662 int i;
5663
5664 if (wlc == NULL)
5665 return -ENODATA;
5666
5667 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5668 if (!strcmp(wlc->modulecb[i].name, name) &&
5669 (wlc->modulecb[i].hdl == hdl)) {
5670 memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
5671 return 0;
5672 }
5673 }
5674
5675 /* table not found! */
5676 return -ENODATA;
5677 }
5678
5679 void brcms_c_print_txstatus(struct tx_status *txs)
5680 {
5681 pr_debug("\ntxpkt (MPDU) Complete\n");
5682
5683 pr_debug("FrameID: %04x TxStatus: %04x\n", txs->frameid, txs->status);
5684
5685 pr_debug("[15:12] %d frame attempts\n",
5686 (txs->status & TX_STATUS_FRM_RTX_MASK) >>
5687 TX_STATUS_FRM_RTX_SHIFT);
5688 pr_debug(" [11:8] %d rts attempts\n",
5689 (txs->status & TX_STATUS_RTS_RTX_MASK) >>
5690 TX_STATUS_RTS_RTX_SHIFT);
5691 pr_debug(" [7] %d PM mode indicated\n",
5692 txs->status & TX_STATUS_PMINDCTD ? 1 : 0);
5693 pr_debug(" [6] %d intermediate status\n",
5694 txs->status & TX_STATUS_INTERMEDIATE ? 1 : 0);
5695 pr_debug(" [5] %d AMPDU\n",
5696 txs->status & TX_STATUS_AMPDU ? 1 : 0);
5697 pr_debug(" [4:2] %d Frame Suppressed Reason (%s)\n",
5698 (txs->status & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT,
5699 (const char *[]) {
5700 "None",
5701 "PMQ Entry",
5702 "Flush request",
5703 "Previous frag failure",
5704 "Channel mismatch",
5705 "Lifetime Expiry",
5706 "Underflow"
5707 } [(txs->status & TX_STATUS_SUPR_MASK) >>
5708 TX_STATUS_SUPR_SHIFT]);
5709 pr_debug(" [1] %d acked\n",
5710 txs->status & TX_STATUS_ACK_RCV ? 1 : 0);
5711
5712 pr_debug("LastTxTime: %04x Seq: %04x PHYTxStatus: %04x RxAckRSSI: %04x RxAckSQ: %04x\n",
5713 txs->lasttxtime, txs->sequence, txs->phyerr,
5714 (txs->ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT,
5715 (txs->ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
5716 }
5717
5718 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5719 {
5720 struct pci_dev *pcidev = core->bus->host_pci;
5721 u16 vendor = pcidev->vendor;
5722 u16 device = pcidev->device;
5723
5724 if (vendor != PCI_VENDOR_ID_BROADCOM) {
5725 pr_err("unknown vendor id %04x\n", vendor);
5726 return false;
5727 }
5728
5729 if (device == BCM43224_D11N_ID_VEN1)
5730 return true;
5731 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5732 return true;
5733 if (device == BCM4313_D11N2G_ID)
5734 return true;
5735 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5736 return true;
5737
5738 pr_err("unknown device id %04x\n", device);
5739 return false;
5740 }
5741
5742 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5743 {
5744 struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5745
5746 if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5747 return true;
5748
5749 pr_err("unknown chip id %04x\n", chipinfo->id);
5750 return false;
5751 }
5752
5753 bool brcms_c_chipmatch(struct bcma_device *core)
5754 {
5755 switch (core->bus->hosttype) {
5756 case BCMA_HOSTTYPE_PCI:
5757 return brcms_c_chipmatch_pci(core);
5758 case BCMA_HOSTTYPE_SOC:
5759 return brcms_c_chipmatch_soc(core);
5760 default:
5761 pr_err("unknown host type: %i\n", core->bus->hosttype);
5762 return false;
5763 }
5764 }
5765
5766 #if defined(DEBUG)
5767 void brcms_c_print_txdesc(struct d11txh *txh)
5768 {
5769 u16 mtcl = le16_to_cpu(txh->MacTxControlLow);
5770 u16 mtch = le16_to_cpu(txh->MacTxControlHigh);
5771 u16 mfc = le16_to_cpu(txh->MacFrameControl);
5772 u16 tfest = le16_to_cpu(txh->TxFesTimeNormal);
5773 u16 ptcw = le16_to_cpu(txh->PhyTxControlWord);
5774 u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1);
5775 u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr);
5776 u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts);
5777 u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts);
5778 u16 mainrates = le16_to_cpu(txh->MainRates);
5779 u16 xtraft = le16_to_cpu(txh->XtraFrameTypes);
5780 u8 *iv = txh->IV;
5781 u8 *ra = txh->TxFrameRA;
5782 u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback);
5783 u8 *rtspfb = txh->RTSPLCPFallback;
5784 u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback);
5785 u8 *fragpfb = txh->FragPLCPFallback;
5786 u16 fragdfb = le16_to_cpu(txh->FragDurFallback);
5787 u16 mmodelen = le16_to_cpu(txh->MModeLen);
5788 u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen);
5789 u16 tfid = le16_to_cpu(txh->TxFrameID);
5790 u16 txs = le16_to_cpu(txh->TxStatus);
5791 u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus);
5792 u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT);
5793 u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR);
5794 u16 mmbyte = le16_to_cpu(txh->MinMBytes);
5795
5796 u8 *rtsph = txh->RTSPhyHeader;
5797 struct ieee80211_rts rts = txh->rts_frame;
5798
5799 /* add plcp header along with txh descriptor */
5800 brcmu_dbg_hex_dump(txh, sizeof(struct d11txh) + 48,
5801 "Raw TxDesc + plcp header:\n");
5802
5803 pr_debug("TxCtlLow: %04x ", mtcl);
5804 pr_debug("TxCtlHigh: %04x ", mtch);
5805 pr_debug("FC: %04x ", mfc);
5806 pr_debug("FES Time: %04x\n", tfest);
5807 pr_debug("PhyCtl: %04x%s ", ptcw,
5808 (ptcw & PHY_TXC_SHORT_HDR) ? " short" : "");
5809 pr_debug("PhyCtl_1: %04x ", ptcw_1);
5810 pr_debug("PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
5811 pr_debug("PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
5812 pr_debug("PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
5813 pr_debug("MainRates: %04x ", mainrates);
5814 pr_debug("XtraFrameTypes: %04x ", xtraft);
5815 pr_debug("\n");
5816
5817 print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV));
5818 print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET,
5819 ra, sizeof(txh->TxFrameRA));
5820
5821 pr_debug("Fb FES Time: %04x ", tfestfb);
5822 print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET,
5823 rtspfb, sizeof(txh->RTSPLCPFallback));
5824 pr_debug("RTS DUR: %04x ", rtsdfb);
5825 print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET,
5826 fragpfb, sizeof(txh->FragPLCPFallback));
5827 pr_debug("DUR: %04x", fragdfb);
5828 pr_debug("\n");
5829
5830 pr_debug("MModeLen: %04x ", mmodelen);
5831 pr_debug("MModeFbrLen: %04x\n", mmodefbrlen);
5832
5833 pr_debug("FrameID: %04x\n", tfid);
5834 pr_debug("TxStatus: %04x\n", txs);
5835
5836 pr_debug("MaxNumMpdu: %04x\n", mnmpdu);
5837 pr_debug("MaxAggbyte: %04x\n", mabyte);
5838 pr_debug("MaxAggbyte_fb: %04x\n", mabyte_f);
5839 pr_debug("MinByte: %04x\n", mmbyte);
5840
5841 print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET,
5842 rtsph, sizeof(txh->RTSPhyHeader));
5843 print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET,
5844 (u8 *)&rts, sizeof(txh->rts_frame));
5845 pr_debug("\n");
5846 }
5847 #endif /* defined(DEBUG) */
5848
5849 #if defined(DEBUG)
5850 static int
5851 brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf,
5852 int len)
5853 {
5854 int i;
5855 char *p = buf;
5856 char hexstr[16];
5857 int slen = 0, nlen = 0;
5858 u32 bit;
5859 const char *name;
5860
5861 if (len < 2 || !buf)
5862 return 0;
5863
5864 buf[0] = '\0';
5865
5866 for (i = 0; flags != 0; i++) {
5867 bit = bd[i].bit;
5868 name = bd[i].name;
5869 if (bit == 0 && flags != 0) {
5870 /* print any unnamed bits */
5871 snprintf(hexstr, 16, "0x%X", flags);
5872 name = hexstr;
5873 flags = 0; /* exit loop */
5874 } else if ((flags & bit) == 0)
5875 continue;
5876 flags &= ~bit;
5877 nlen = strlen(name);
5878 slen += nlen;
5879 /* count btwn flag space */
5880 if (flags != 0)
5881 slen += 1;
5882 /* need NULL char as well */
5883 if (len <= slen)
5884 break;
5885 /* copy NULL char but don't count it */
5886 strncpy(p, name, nlen + 1);
5887 p += nlen;
5888 /* copy btwn flag space and NULL char */
5889 if (flags != 0)
5890 p += snprintf(p, 2, " ");
5891 len -= slen;
5892 }
5893
5894 /* indicate the str was too short */
5895 if (flags != 0) {
5896 if (len < 2)
5897 p -= 2 - len; /* overwrite last char */
5898 p += snprintf(p, 2, ">");
5899 }
5900
5901 return (int)(p - buf);
5902 }
5903 #endif /* defined(DEBUG) */
5904
5905 #if defined(DEBUG)
5906 void brcms_c_print_rxh(struct d11rxhdr *rxh)
5907 {
5908 u16 len = rxh->RxFrameSize;
5909 u16 phystatus_0 = rxh->PhyRxStatus_0;
5910 u16 phystatus_1 = rxh->PhyRxStatus_1;
5911 u16 phystatus_2 = rxh->PhyRxStatus_2;
5912 u16 phystatus_3 = rxh->PhyRxStatus_3;
5913 u16 macstatus1 = rxh->RxStatus1;
5914 u16 macstatus2 = rxh->RxStatus2;
5915 char flagstr[64];
5916 char lenbuf[20];
5917 static const struct brcms_c_bit_desc macstat_flags[] = {
5918 {RXS_FCSERR, "FCSErr"},
5919 {RXS_RESPFRAMETX, "Reply"},
5920 {RXS_PBPRES, "PADDING"},
5921 {RXS_DECATMPT, "DeCr"},
5922 {RXS_DECERR, "DeCrErr"},
5923 {RXS_BCNSENT, "Bcn"},
5924 {0, NULL}
5925 };
5926
5927 brcmu_dbg_hex_dump(rxh, sizeof(struct d11rxhdr), "Raw RxDesc:\n");
5928
5929 brcms_c_format_flags(macstat_flags, macstatus1, flagstr, 64);
5930
5931 snprintf(lenbuf, sizeof(lenbuf), "0x%x", len);
5932
5933 pr_debug("RxFrameSize: %6s (%d)%s\n", lenbuf, len,
5934 (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : "");
5935 pr_debug("RxPHYStatus: %04x %04x %04x %04x\n",
5936 phystatus_0, phystatus_1, phystatus_2, phystatus_3);
5937 pr_debug("RxMACStatus: %x %s\n", macstatus1, flagstr);
5938 pr_debug("RXMACaggtype: %x\n",
5939 (macstatus2 & RXS_AGGTYPE_MASK));
5940 pr_debug("RxTSFTime: %04x\n", rxh->RxTSFTime);
5941 }
5942 #endif /* defined(DEBUG) */
5943
5944 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5945 {
5946 u16 table_ptr;
5947 u8 phy_rate, index;
5948
5949 /* get the phy specific rate encoding for the PLCP SIGNAL field */
5950 if (is_ofdm_rate(rate))
5951 table_ptr = M_RT_DIRMAP_A;
5952 else
5953 table_ptr = M_RT_DIRMAP_B;
5954
5955 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5956 * the index into the rate table.
5957 */
5958 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5959 index = phy_rate & 0xf;
5960
5961 /* Find the SHM pointer to the rate table entry by looking in the
5962 * Direct-map Table
5963 */
5964 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
5965 }
5966
5967 /*
5968 * bcmc_fid_generate:
5969 * Generate frame ID for a BCMC packet. The frag field is not used
5970 * for MC frames so is used as part of the sequence number.
5971 */
5972 static inline u16
5973 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
5974 struct d11txh *txh)
5975 {
5976 u16 frameid;
5977
5978 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
5979 TXFID_QUEUE_MASK);
5980 frameid |=
5981 (((wlc->
5982 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
5983 TX_BCMC_FIFO;
5984
5985 return frameid;
5986 }
5987
5988 static uint
5989 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
5990 u8 preamble_type)
5991 {
5992 uint dur = 0;
5993
5994 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n",
5995 wlc->pub->unit, rspec, preamble_type);
5996 /*
5997 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5998 * is less than or equal to the rate of the immediately previous
5999 * frame in the FES
6000 */
6001 rspec = brcms_basic_rate(wlc, rspec);
6002 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
6003 dur =
6004 brcms_c_calc_frame_time(wlc, rspec, preamble_type,
6005 (DOT11_ACK_LEN + FCS_LEN));
6006 return dur;
6007 }
6008
6009 static uint
6010 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
6011 u8 preamble_type)
6012 {
6013 BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n",
6014 wlc->pub->unit, rspec, preamble_type);
6015 return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
6016 }
6017
6018 static uint
6019 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
6020 u8 preamble_type)
6021 {
6022 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, "
6023 "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type);
6024 /*
6025 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
6026 * is less than or equal to the rate of the immediately previous
6027 * frame in the FES
6028 */
6029 rspec = brcms_basic_rate(wlc, rspec);
6030 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
6031 return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
6032 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
6033 FCS_LEN));
6034 }
6035
6036 /* brcms_c_compute_frame_dur()
6037 *
6038 * Calculate the 802.11 MAC header DUR field for MPDU
6039 * DUR for a single frame = 1 SIFS + 1 ACK
6040 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
6041 *
6042 * rate MPDU rate in unit of 500kbps
6043 * next_frag_len next MPDU length in bytes
6044 * preamble_type use short/GF or long/MM PLCP header
6045 */
6046 static u16
6047 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
6048 u8 preamble_type, uint next_frag_len)
6049 {
6050 u16 dur, sifs;
6051
6052 sifs = get_sifs(wlc->band);
6053
6054 dur = sifs;
6055 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
6056
6057 if (next_frag_len) {
6058 /* Double the current DUR to get 2 SIFS + 2 ACKs */
6059 dur *= 2;
6060 /* add another SIFS and the frag time */
6061 dur += sifs;
6062 dur +=
6063 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
6064 next_frag_len);
6065 }
6066 return dur;
6067 }
6068
6069 /* The opposite of brcms_c_calc_frame_time */
6070 static uint
6071 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
6072 u8 preamble_type, uint dur)
6073 {
6074 uint nsyms, mac_len, Ndps, kNdps;
6075 uint rate = rspec2rate(ratespec);
6076
6077 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n",
6078 wlc->pub->unit, ratespec, preamble_type, dur);
6079
6080 if (is_mcs_rate(ratespec)) {
6081 uint mcs = ratespec & RSPEC_RATE_MASK;
6082 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
6083 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
6084 /* payload calculation matches that of regular ofdm */
6085 if (wlc->band->bandtype == BRCM_BAND_2G)
6086 dur -= DOT11_OFDM_SIGNAL_EXTENSION;
6087 /* kNdbps = kbps * 4 */
6088 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
6089 rspec_issgi(ratespec)) * 4;
6090 nsyms = dur / APHY_SYMBOL_TIME;
6091 mac_len =
6092 ((nsyms * kNdps) -
6093 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
6094 } else if (is_ofdm_rate(ratespec)) {
6095 dur -= APHY_PREAMBLE_TIME;
6096 dur -= APHY_SIGNAL_TIME;
6097 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
6098 Ndps = rate * 2;
6099 nsyms = dur / APHY_SYMBOL_TIME;
6100 mac_len =
6101 ((nsyms * Ndps) -
6102 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
6103 } else {
6104 if (preamble_type & BRCMS_SHORT_PREAMBLE)
6105 dur -= BPHY_PLCP_SHORT_TIME;
6106 else
6107 dur -= BPHY_PLCP_TIME;
6108 mac_len = dur * rate;
6109 /* divide out factor of 2 in rate (1/2 mbps) */
6110 mac_len = mac_len / 8 / 2;
6111 }
6112 return mac_len;
6113 }
6114
6115 /*
6116 * Return true if the specified rate is supported by the specified band.
6117 * BRCM_BAND_AUTO indicates the current band.
6118 */
6119 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
6120 bool verbose)
6121 {
6122 struct brcms_c_rateset *hw_rateset;
6123 uint i;
6124
6125 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
6126 hw_rateset = &wlc->band->hw_rateset;
6127 else if (wlc->pub->_nbands > 1)
6128 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
6129 else
6130 /* other band specified and we are a single band device */
6131 return false;
6132
6133 /* check if this is a mimo rate */
6134 if (is_mcs_rate(rspec)) {
6135 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
6136 goto error;
6137
6138 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
6139 }
6140
6141 for (i = 0; i < hw_rateset->count; i++)
6142 if (hw_rateset->rates[i] == rspec2rate(rspec))
6143 return true;
6144 error:
6145 if (verbose)
6146 wiphy_err(wlc->wiphy, "wl%d: valid_rate: rate spec 0x%x "
6147 "not in hw_rateset\n", wlc->pub->unit, rspec);
6148
6149 return false;
6150 }
6151
6152 static u32
6153 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
6154 u32 int_val)
6155 {
6156 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
6157 u8 rate = int_val & NRATE_RATE_MASK;
6158 u32 rspec;
6159 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
6160 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
6161 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
6162 == NRATE_OVERRIDE_MCS_ONLY);
6163 int bcmerror = 0;
6164
6165 if (!ismcs)
6166 return (u32) rate;
6167
6168 /* validate the combination of rate/mcs/stf is allowed */
6169 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
6170 /* mcs only allowed when nmode */
6171 if (stf > PHY_TXC1_MODE_SDM) {
6172 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n",
6173 wlc->pub->unit, __func__);
6174 bcmerror = -EINVAL;
6175 goto done;
6176 }
6177
6178 /* mcs 32 is a special case, DUP mode 40 only */
6179 if (rate == 32) {
6180 if (!CHSPEC_IS40(wlc->home_chanspec) ||
6181 ((stf != PHY_TXC1_MODE_SISO)
6182 && (stf != PHY_TXC1_MODE_CDD))) {
6183 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs "
6184 "32\n", wlc->pub->unit, __func__);
6185 bcmerror = -EINVAL;
6186 goto done;
6187 }
6188 /* mcs > 7 must use stf SDM */
6189 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
6190 /* mcs > 7 must use stf SDM */
6191 if (stf != PHY_TXC1_MODE_SDM) {
6192 BCMMSG(wlc->wiphy, "wl%d: enabling "
6193 "SDM mode for mcs %d\n",
6194 wlc->pub->unit, rate);
6195 stf = PHY_TXC1_MODE_SDM;
6196 }
6197 } else {
6198 /*
6199 * MCS 0-7 may use SISO, CDD, and for
6200 * phy_rev >= 3 STBC
6201 */
6202 if ((stf > PHY_TXC1_MODE_STBC) ||
6203 (!BRCMS_STBC_CAP_PHY(wlc)
6204 && (stf == PHY_TXC1_MODE_STBC))) {
6205 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC"
6206 "\n", wlc->pub->unit, __func__);
6207 bcmerror = -EINVAL;
6208 goto done;
6209 }
6210 }
6211 } else if (is_ofdm_rate(rate)) {
6212 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
6213 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n",
6214 wlc->pub->unit, __func__);
6215 bcmerror = -EINVAL;
6216 goto done;
6217 }
6218 } else if (is_cck_rate(rate)) {
6219 if ((cur_band->bandtype != BRCM_BAND_2G)
6220 || (stf != PHY_TXC1_MODE_SISO)) {
6221 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n",
6222 wlc->pub->unit, __func__);
6223 bcmerror = -EINVAL;
6224 goto done;
6225 }
6226 } else {
6227 wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n",
6228 wlc->pub->unit, __func__);
6229 bcmerror = -EINVAL;
6230 goto done;
6231 }
6232 /* make sure multiple antennae are available for non-siso rates */
6233 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
6234 wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO "
6235 "request\n", wlc->pub->unit, __func__);
6236 bcmerror = -EINVAL;
6237 goto done;
6238 }
6239
6240 rspec = rate;
6241 if (ismcs) {
6242 rspec |= RSPEC_MIMORATE;
6243 /* For STBC populate the STC field of the ratespec */
6244 if (stf == PHY_TXC1_MODE_STBC) {
6245 u8 stc;
6246 stc = 1; /* Nss for single stream is always 1 */
6247 rspec |= (stc << RSPEC_STC_SHIFT);
6248 }
6249 }
6250
6251 rspec |= (stf << RSPEC_STF_SHIFT);
6252
6253 if (override_mcs_only)
6254 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
6255
6256 if (issgi)
6257 rspec |= RSPEC_SHORT_GI;
6258
6259 if ((rate != 0)
6260 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
6261 return rate;
6262
6263 return rspec;
6264 done:
6265 return rate;
6266 }
6267
6268 /*
6269 * Compute PLCP, but only requires actual rate and length of pkt.
6270 * Rate is given in the driver standard multiple of 500 kbps.
6271 * le is set for 11 Mbps rate if necessary.
6272 * Broken out for PRQ.
6273 */
6274
6275 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
6276 uint length, u8 *plcp)
6277 {
6278 u16 usec = 0;
6279 u8 le = 0;
6280
6281 switch (rate_500) {
6282 case BRCM_RATE_1M:
6283 usec = length << 3;
6284 break;
6285 case BRCM_RATE_2M:
6286 usec = length << 2;
6287 break;
6288 case BRCM_RATE_5M5:
6289 usec = (length << 4) / 11;
6290 if ((length << 4) - (usec * 11) > 0)
6291 usec++;
6292 break;
6293 case BRCM_RATE_11M:
6294 usec = (length << 3) / 11;
6295 if ((length << 3) - (usec * 11) > 0) {
6296 usec++;
6297 if ((usec * 11) - (length << 3) >= 8)
6298 le = D11B_PLCP_SIGNAL_LE;
6299 }
6300 break;
6301
6302 default:
6303 wiphy_err(wlc->wiphy,
6304 "brcms_c_cck_plcp_set: unsupported rate %d\n",
6305 rate_500);
6306 rate_500 = BRCM_RATE_1M;
6307 usec = length << 3;
6308 break;
6309 }
6310 /* PLCP signal byte */
6311 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
6312 /* PLCP service byte */
6313 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
6314 /* PLCP length u16, little endian */
6315 plcp[2] = usec & 0xff;
6316 plcp[3] = (usec >> 8) & 0xff;
6317 /* PLCP CRC16 */
6318 plcp[4] = 0;
6319 plcp[5] = 0;
6320 }
6321
6322 /* Rate: 802.11 rate code, length: PSDU length in octets */
6323 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
6324 {
6325 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6326 plcp[0] = mcs;
6327 if (rspec_is40mhz(rspec) || (mcs == 32))
6328 plcp[0] |= MIMO_PLCP_40MHZ;
6329 BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6330 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6331 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6332 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6333 plcp[5] = 0;
6334 }
6335
6336 /* Rate: 802.11 rate code, length: PSDU length in octets */
6337 static void
6338 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6339 {
6340 u8 rate_signal;
6341 u32 tmp = 0;
6342 int rate = rspec2rate(rspec);
6343
6344 /*
6345 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6346 * transmitted first
6347 */
6348 rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6349 memset(plcp, 0, D11_PHY_HDR_LEN);
6350 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6351
6352 tmp = (length & 0xfff) << 5;
6353 plcp[2] |= (tmp >> 16) & 0xff;
6354 plcp[1] |= (tmp >> 8) & 0xff;
6355 plcp[0] |= tmp & 0xff;
6356 }
6357
6358 /* Rate: 802.11 rate code, length: PSDU length in octets */
6359 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6360 uint length, u8 *plcp)
6361 {
6362 int rate = rspec2rate(rspec);
6363
6364 brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6365 }
6366
6367 static void
6368 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6369 uint length, u8 *plcp)
6370 {
6371 if (is_mcs_rate(rspec))
6372 brcms_c_compute_mimo_plcp(rspec, length, plcp);
6373 else if (is_ofdm_rate(rspec))
6374 brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6375 else
6376 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6377 }
6378
6379 /* brcms_c_compute_rtscts_dur()
6380 *
6381 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6382 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6383 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
6384 *
6385 * cts cts-to-self or rts/cts
6386 * rts_rate rts or cts rate in unit of 500kbps
6387 * rate next MPDU rate in unit of 500kbps
6388 * frame_len next MPDU frame length in bytes
6389 */
6390 u16
6391 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6392 u32 rts_rate,
6393 u32 frame_rate, u8 rts_preamble_type,
6394 u8 frame_preamble_type, uint frame_len, bool ba)
6395 {
6396 u16 dur, sifs;
6397
6398 sifs = get_sifs(wlc->band);
6399
6400 if (!cts_only) {
6401 /* RTS/CTS */
6402 dur = 3 * sifs;
6403 dur +=
6404 (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6405 rts_preamble_type);
6406 } else {
6407 /* CTS-TO-SELF */
6408 dur = 2 * sifs;
6409 }
6410
6411 dur +=
6412 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6413 frame_len);
6414 if (ba)
6415 dur +=
6416 (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6417 BRCMS_SHORT_PREAMBLE);
6418 else
6419 dur +=
6420 (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6421 frame_preamble_type);
6422 return dur;
6423 }
6424
6425 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6426 {
6427 u16 phyctl1 = 0;
6428 u16 bw;
6429
6430 if (BRCMS_ISLCNPHY(wlc->band)) {
6431 bw = PHY_TXC1_BW_20MHZ;
6432 } else {
6433 bw = rspec_get_bw(rspec);
6434 /* 10Mhz is not supported yet */
6435 if (bw < PHY_TXC1_BW_20MHZ) {
6436 wiphy_err(wlc->wiphy, "phytxctl1_calc: bw %d is "
6437 "not supported yet, set to 20L\n", bw);
6438 bw = PHY_TXC1_BW_20MHZ;
6439 }
6440 }
6441
6442 if (is_mcs_rate(rspec)) {
6443 uint mcs = rspec & RSPEC_RATE_MASK;
6444
6445 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6446 phyctl1 = rspec_phytxbyte2(rspec);
6447 /* set the upper byte of phyctl1 */
6448 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6449 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6450 && !BRCMS_ISSSLPNPHY(wlc->band)) {
6451 /*
6452 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6453 * Data Rate. Eventually MIMOPHY would also be converted to
6454 * this format
6455 */
6456 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6457 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6458 } else { /* legacy OFDM/CCK */
6459 s16 phycfg;
6460 /* get the phyctl byte from rate phycfg table */
6461 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6462 if (phycfg == -1) {
6463 wiphy_err(wlc->wiphy, "phytxctl1_calc: wrong "
6464 "legacy OFDM/CCK rate\n");
6465 phycfg = 0;
6466 }
6467 /* set the upper byte of phyctl1 */
6468 phyctl1 =
6469 (bw | (phycfg << 8) |
6470 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6471 }
6472 return phyctl1;
6473 }
6474
6475 /*
6476 * Add struct d11txh, struct cck_phy_hdr.
6477 *
6478 * 'p' data must start with 802.11 MAC header
6479 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6480 *
6481 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6482 *
6483 */
6484 static u16
6485 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6486 struct sk_buff *p, struct scb *scb, uint frag,
6487 uint nfrags, uint queue, uint next_frag_len)
6488 {
6489 struct ieee80211_hdr *h;
6490 struct d11txh *txh;
6491 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6492 int len, phylen, rts_phylen;
6493 u16 mch, phyctl, xfts, mainrates;
6494 u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6495 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6496 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6497 bool use_rts = false;
6498 bool use_cts = false;
6499 bool use_rifs = false;
6500 bool short_preamble[2] = { false, false };
6501 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6502 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6503 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6504 struct ieee80211_rts *rts = NULL;
6505 bool qos;
6506 uint ac;
6507 bool hwtkmic = false;
6508 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6509 #define ANTCFG_NONE 0xFF
6510 u8 antcfg = ANTCFG_NONE;
6511 u8 fbantcfg = ANTCFG_NONE;
6512 uint phyctl1_stf = 0;
6513 u16 durid = 0;
6514 struct ieee80211_tx_rate *txrate[2];
6515 int k;
6516 struct ieee80211_tx_info *tx_info;
6517 bool is_mcs;
6518 u16 mimo_txbw;
6519 u8 mimo_preamble_type;
6520
6521 /* locate 802.11 MAC header */
6522 h = (struct ieee80211_hdr *)(p->data);
6523 qos = ieee80211_is_data_qos(h->frame_control);
6524
6525 /* compute length of frame in bytes for use in PLCP computations */
6526 len = p->len;
6527 phylen = len + FCS_LEN;
6528
6529 /* Get tx_info */
6530 tx_info = IEEE80211_SKB_CB(p);
6531
6532 /* add PLCP */
6533 plcp = skb_push(p, D11_PHY_HDR_LEN);
6534
6535 /* add Broadcom tx descriptor header */
6536 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6537 memset(txh, 0, D11_TXH_LEN);
6538
6539 /* setup frameid */
6540 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6541 /* non-AP STA should never use BCMC queue */
6542 if (queue == TX_BCMC_FIFO) {
6543 wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == "
6544 "TX_BCMC!\n", wlc->pub->unit, __func__);
6545 frameid = bcmc_fid_generate(wlc, NULL, txh);
6546 } else {
6547 /* Increment the counter for first fragment */
6548 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6549 scb->seqnum[p->priority]++;
6550
6551 /* extract fragment number from frame first */
6552 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6553 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6554 h->seq_ctrl = cpu_to_le16(seq);
6555
6556 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6557 (queue & TXFID_QUEUE_MASK);
6558 }
6559 }
6560 frameid |= queue & TXFID_QUEUE_MASK;
6561
6562 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6563 if (ieee80211_is_beacon(h->frame_control))
6564 mcl |= TXC_IGNOREPMQ;
6565
6566 txrate[0] = tx_info->control.rates;
6567 txrate[1] = txrate[0] + 1;
6568
6569 /*
6570 * if rate control algorithm didn't give us a fallback
6571 * rate, use the primary rate
6572 */
6573 if (txrate[1]->idx < 0)
6574 txrate[1] = txrate[0];
6575
6576 for (k = 0; k < hw->max_rates; k++) {
6577 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6578 if (!is_mcs) {
6579 if ((txrate[k]->idx >= 0)
6580 && (txrate[k]->idx <
6581 hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6582 rspec[k] =
6583 hw->wiphy->bands[tx_info->band]->
6584 bitrates[txrate[k]->idx].hw_value;
6585 short_preamble[k] =
6586 txrate[k]->
6587 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
6588 true : false;
6589 } else {
6590 rspec[k] = BRCM_RATE_1M;
6591 }
6592 } else {
6593 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6594 NRATE_MCS_INUSE | txrate[k]->idx);
6595 }
6596
6597 /*
6598 * Currently only support same setting for primay and
6599 * fallback rates. Unify flags for each rate into a
6600 * single value for the frame
6601 */
6602 use_rts |=
6603 txrate[k]->
6604 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6605 use_cts |=
6606 txrate[k]->
6607 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6608
6609
6610 /*
6611 * (1) RATE:
6612 * determine and validate primary rate
6613 * and fallback rates
6614 */
6615 if (!rspec_active(rspec[k])) {
6616 rspec[k] = BRCM_RATE_1M;
6617 } else {
6618 if (!is_multicast_ether_addr(h->addr1)) {
6619 /* set tx antenna config */
6620 brcms_c_antsel_antcfg_get(wlc->asi, false,
6621 false, 0, 0, &antcfg, &fbantcfg);
6622 }
6623 }
6624 }
6625
6626 phyctl1_stf = wlc->stf->ss_opmode;
6627
6628 if (wlc->pub->_n_enab & SUPPORT_11N) {
6629 for (k = 0; k < hw->max_rates; k++) {
6630 /*
6631 * apply siso/cdd to single stream mcs's or ofdm
6632 * if rspec is auto selected
6633 */
6634 if (((is_mcs_rate(rspec[k]) &&
6635 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6636 is_ofdm_rate(rspec[k]))
6637 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6638 || !(rspec[k] & RSPEC_OVERRIDE))) {
6639 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6640
6641 /* For SISO MCS use STBC if possible */
6642 if (is_mcs_rate(rspec[k])
6643 && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6644 u8 stc;
6645
6646 /* Nss for single stream is always 1 */
6647 stc = 1;
6648 rspec[k] |= (PHY_TXC1_MODE_STBC <<
6649 RSPEC_STF_SHIFT) |
6650 (stc << RSPEC_STC_SHIFT);
6651 } else
6652 rspec[k] |=
6653 (phyctl1_stf << RSPEC_STF_SHIFT);
6654 }
6655
6656 /*
6657 * Is the phy configured to use 40MHZ frames? If
6658 * so then pick the desired txbw
6659 */
6660 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6661 /* default txbw is 20in40 SB */
6662 mimo_ctlchbw = mimo_txbw =
6663 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6664 wlc->band->pi))
6665 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6666
6667 if (is_mcs_rate(rspec[k])) {
6668 /* mcs 32 must be 40b/w DUP */
6669 if ((rspec[k] & RSPEC_RATE_MASK)
6670 == 32) {
6671 mimo_txbw =
6672 PHY_TXC1_BW_40MHZ_DUP;
6673 /* use override */
6674 } else if (wlc->mimo_40txbw != AUTO)
6675 mimo_txbw = wlc->mimo_40txbw;
6676 /* else check if dst is using 40 Mhz */
6677 else if (scb->flags & SCB_IS40)
6678 mimo_txbw = PHY_TXC1_BW_40MHZ;
6679 } else if (is_ofdm_rate(rspec[k])) {
6680 if (wlc->ofdm_40txbw != AUTO)
6681 mimo_txbw = wlc->ofdm_40txbw;
6682 } else if (wlc->cck_40txbw != AUTO) {
6683 mimo_txbw = wlc->cck_40txbw;
6684 }
6685 } else {
6686 /*
6687 * mcs32 is 40 b/w only.
6688 * This is possible for probe packets on
6689 * a STA during SCAN
6690 */
6691 if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6692 /* mcs 0 */
6693 rspec[k] = RSPEC_MIMORATE;
6694
6695 mimo_txbw = PHY_TXC1_BW_20MHZ;
6696 }
6697
6698 /* Set channel width */
6699 rspec[k] &= ~RSPEC_BW_MASK;
6700 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6701 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6702 else
6703 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6704
6705 /* Disable short GI, not supported yet */
6706 rspec[k] &= ~RSPEC_SHORT_GI;
6707
6708 mimo_preamble_type = BRCMS_MM_PREAMBLE;
6709 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6710 mimo_preamble_type = BRCMS_GF_PREAMBLE;
6711
6712 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6713 && (!is_mcs_rate(rspec[k]))) {
6714 wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_"
6715 "RC_MCS != is_mcs_rate(rspec)\n",
6716 wlc->pub->unit, __func__);
6717 }
6718
6719 if (is_mcs_rate(rspec[k])) {
6720 preamble_type[k] = mimo_preamble_type;
6721
6722 /*
6723 * if SGI is selected, then forced mm
6724 * for single stream
6725 */
6726 if ((rspec[k] & RSPEC_SHORT_GI)
6727 && is_single_stream(rspec[k] &
6728 RSPEC_RATE_MASK))
6729 preamble_type[k] = BRCMS_MM_PREAMBLE;
6730 }
6731
6732 /* should be better conditionalized */
6733 if (!is_mcs_rate(rspec[0])
6734 && (tx_info->control.rates[0].
6735 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6736 preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6737 }
6738 } else {
6739 for (k = 0; k < hw->max_rates; k++) {
6740 /* Set ctrlchbw as 20Mhz */
6741 rspec[k] &= ~RSPEC_BW_MASK;
6742 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6743
6744 /* for nphy, stf of ofdm frames must follow policies */
6745 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6746 rspec[k] &= ~RSPEC_STF_MASK;
6747 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6748 }
6749 }
6750 }
6751
6752 /* Reset these for use with AMPDU's */
6753 txrate[0]->count = 0;
6754 txrate[1]->count = 0;
6755
6756 /* (2) PROTECTION, may change rspec */
6757 if ((ieee80211_is_data(h->frame_control) ||
6758 ieee80211_is_mgmt(h->frame_control)) &&
6759 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6760 use_rts = true;
6761
6762 /* (3) PLCP: determine PLCP header and MAC duration,
6763 * fill struct d11txh */
6764 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6765 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6766 memcpy(&txh->FragPLCPFallback,
6767 plcp_fallback, sizeof(txh->FragPLCPFallback));
6768
6769 /* Length field now put in CCK FBR CRC field */
6770 if (is_cck_rate(rspec[1])) {
6771 txh->FragPLCPFallback[4] = phylen & 0xff;
6772 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6773 }
6774
6775 /* MIMO-RATE: need validation ?? */
6776 mainrates = is_ofdm_rate(rspec[0]) ?
6777 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6778 plcp[0];
6779
6780 /* DUR field for main rate */
6781 if (!ieee80211_is_pspoll(h->frame_control) &&
6782 !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6783 durid =
6784 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6785 next_frag_len);
6786 h->duration_id = cpu_to_le16(durid);
6787 } else if (use_rifs) {
6788 /* NAV protect to end of next max packet size */
6789 durid =
6790 (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6791 preamble_type[0],
6792 DOT11_MAX_FRAG_LEN);
6793 durid += RIFS_11N_TIME;
6794 h->duration_id = cpu_to_le16(durid);
6795 }
6796
6797 /* DUR field for fallback rate */
6798 if (ieee80211_is_pspoll(h->frame_control))
6799 txh->FragDurFallback = h->duration_id;
6800 else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6801 txh->FragDurFallback = 0;
6802 else {
6803 durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6804 preamble_type[1], next_frag_len);
6805 txh->FragDurFallback = cpu_to_le16(durid);
6806 }
6807
6808 /* (4) MAC-HDR: MacTxControlLow */
6809 if (frag == 0)
6810 mcl |= TXC_STARTMSDU;
6811
6812 if (!is_multicast_ether_addr(h->addr1))
6813 mcl |= TXC_IMMEDACK;
6814
6815 if (wlc->band->bandtype == BRCM_BAND_5G)
6816 mcl |= TXC_FREQBAND_5G;
6817
6818 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6819 mcl |= TXC_BW_40;
6820
6821 /* set AMIC bit if using hardware TKIP MIC */
6822 if (hwtkmic)
6823 mcl |= TXC_AMIC;
6824
6825 txh->MacTxControlLow = cpu_to_le16(mcl);
6826
6827 /* MacTxControlHigh */
6828 mch = 0;
6829
6830 /* Set fallback rate preamble type */
6831 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6832 (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6833 if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6834 mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6835 }
6836
6837 /* MacFrameControl */
6838 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6839 txh->TxFesTimeNormal = cpu_to_le16(0);
6840
6841 txh->TxFesTimeFallback = cpu_to_le16(0);
6842
6843 /* TxFrameRA */
6844 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6845
6846 /* TxFrameID */
6847 txh->TxFrameID = cpu_to_le16(frameid);
6848
6849 /*
6850 * TxStatus, Note the case of recreating the first frag of a suppressed
6851 * frame then we may need to reset the retry cnt's via the status reg
6852 */
6853 txh->TxStatus = cpu_to_le16(status);
6854
6855 /*
6856 * extra fields for ucode AMPDU aggregation, the new fields are added to
6857 * the END of previous structure so that it's compatible in driver.
6858 */
6859 txh->MaxNMpdus = cpu_to_le16(0);
6860 txh->MaxABytes_MRT = cpu_to_le16(0);
6861 txh->MaxABytes_FBR = cpu_to_le16(0);
6862 txh->MinMBytes = cpu_to_le16(0);
6863
6864 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6865 * furnish struct d11txh */
6866 /* RTS PLCP header and RTS frame */
6867 if (use_rts || use_cts) {
6868 if (use_rts && use_cts)
6869 use_cts = false;
6870
6871 for (k = 0; k < 2; k++) {
6872 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6873 false,
6874 mimo_ctlchbw);
6875 }
6876
6877 if (!is_ofdm_rate(rts_rspec[0]) &&
6878 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
6879 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6880 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
6881 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
6882 }
6883
6884 if (!is_ofdm_rate(rts_rspec[1]) &&
6885 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
6886 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6887 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
6888 mch |= TXC_PREAMBLE_RTS_FB_SHORT;
6889 }
6890
6891 /* RTS/CTS additions to MacTxControlLow */
6892 if (use_cts) {
6893 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
6894 } else {
6895 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
6896 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
6897 }
6898
6899 /* RTS PLCP header */
6900 rts_plcp = txh->RTSPhyHeader;
6901 if (use_cts)
6902 rts_phylen = DOT11_CTS_LEN + FCS_LEN;
6903 else
6904 rts_phylen = DOT11_RTS_LEN + FCS_LEN;
6905
6906 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
6907
6908 /* fallback rate version of RTS PLCP header */
6909 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
6910 rts_plcp_fallback);
6911 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
6912 sizeof(txh->RTSPLCPFallback));
6913
6914 /* RTS frame fields... */
6915 rts = (struct ieee80211_rts *)&txh->rts_frame;
6916
6917 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
6918 rspec[0], rts_preamble_type[0],
6919 preamble_type[0], phylen, false);
6920 rts->duration = cpu_to_le16(durid);
6921 /* fallback rate version of RTS DUR field */
6922 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
6923 rts_rspec[1], rspec[1],
6924 rts_preamble_type[1],
6925 preamble_type[1], phylen, false);
6926 txh->RTSDurFallback = cpu_to_le16(durid);
6927
6928 if (use_cts) {
6929 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6930 IEEE80211_STYPE_CTS);
6931
6932 memcpy(&rts->ra, &h->addr2, ETH_ALEN);
6933 } else {
6934 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
6935 IEEE80211_STYPE_RTS);
6936
6937 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
6938 }
6939
6940 /* mainrate
6941 * low 8 bits: main frag rate/mcs,
6942 * high 8 bits: rts/cts rate/mcs
6943 */
6944 mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
6945 D11A_PHY_HDR_GRATE(
6946 (struct ofdm_phy_hdr *) rts_plcp) :
6947 rts_plcp[0]) << 8;
6948 } else {
6949 memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
6950 memset((char *)&txh->rts_frame, 0,
6951 sizeof(struct ieee80211_rts));
6952 memset((char *)txh->RTSPLCPFallback, 0,
6953 sizeof(txh->RTSPLCPFallback));
6954 txh->RTSDurFallback = 0;
6955 }
6956
6957 #ifdef SUPPORT_40MHZ
6958 /* add null delimiter count */
6959 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
6960 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
6961 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
6962
6963 #endif
6964
6965 /*
6966 * Now that RTS/RTS FB preamble types are updated, write
6967 * the final value
6968 */
6969 txh->MacTxControlHigh = cpu_to_le16(mch);
6970
6971 /*
6972 * MainRates (both the rts and frag plcp rates have
6973 * been calculated now)
6974 */
6975 txh->MainRates = cpu_to_le16(mainrates);
6976
6977 /* XtraFrameTypes */
6978 xfts = frametype(rspec[1], wlc->mimoft);
6979 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
6980 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
6981 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
6982 XFTS_CHANNEL_SHIFT;
6983 txh->XtraFrameTypes = cpu_to_le16(xfts);
6984
6985 /* PhyTxControlWord */
6986 phyctl = frametype(rspec[0], wlc->mimoft);
6987 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
6988 (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
6989 if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
6990 phyctl |= PHY_TXC_SHORT_HDR;
6991 }
6992
6993 /* phytxant is properly bit shifted */
6994 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
6995 txh->PhyTxControlWord = cpu_to_le16(phyctl);
6996
6997 /* PhyTxControlWord_1 */
6998 if (BRCMS_PHY_11N_CAP(wlc->band)) {
6999 u16 phyctl1 = 0;
7000
7001 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
7002 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
7003 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
7004 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
7005
7006 if (use_rts || use_cts) {
7007 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
7008 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
7009 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
7010 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
7011 }
7012
7013 /*
7014 * For mcs frames, if mixedmode(overloaded with long preamble)
7015 * is going to be set, fill in non-zero MModeLen and/or
7016 * MModeFbrLen it will be unnecessary if they are separated
7017 */
7018 if (is_mcs_rate(rspec[0]) &&
7019 (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
7020 u16 mmodelen =
7021 brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
7022 txh->MModeLen = cpu_to_le16(mmodelen);
7023 }
7024
7025 if (is_mcs_rate(rspec[1]) &&
7026 (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
7027 u16 mmodefbrlen =
7028 brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
7029 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
7030 }
7031 }
7032
7033 ac = skb_get_queue_mapping(p);
7034 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
7035 uint frag_dur, dur, dur_fallback;
7036
7037 /* WME: Update TXOP threshold */
7038 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
7039 frag_dur =
7040 brcms_c_calc_frame_time(wlc, rspec[0],
7041 preamble_type[0], phylen);
7042
7043 if (rts) {
7044 /* 1 RTS or CTS-to-self frame */
7045 dur =
7046 brcms_c_calc_cts_time(wlc, rts_rspec[0],
7047 rts_preamble_type[0]);
7048 dur_fallback =
7049 brcms_c_calc_cts_time(wlc, rts_rspec[1],
7050 rts_preamble_type[1]);
7051 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
7052 dur += le16_to_cpu(rts->duration);
7053 dur_fallback +=
7054 le16_to_cpu(txh->RTSDurFallback);
7055 } else if (use_rifs) {
7056 dur = frag_dur;
7057 dur_fallback = 0;
7058 } else {
7059 /* frame + SIFS + ACK */
7060 dur = frag_dur;
7061 dur +=
7062 brcms_c_compute_frame_dur(wlc, rspec[0],
7063 preamble_type[0], 0);
7064
7065 dur_fallback =
7066 brcms_c_calc_frame_time(wlc, rspec[1],
7067 preamble_type[1],
7068 phylen);
7069 dur_fallback +=
7070 brcms_c_compute_frame_dur(wlc, rspec[1],
7071 preamble_type[1], 0);
7072 }
7073 /* NEED to set TxFesTimeNormal (hard) */
7074 txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
7075 /*
7076 * NEED to set fallback rate version of
7077 * TxFesTimeNormal (hard)
7078 */
7079 txh->TxFesTimeFallback =
7080 cpu_to_le16((u16) dur_fallback);
7081
7082 /*
7083 * update txop byte threshold (txop minus intraframe
7084 * overhead)
7085 */
7086 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
7087 uint newfragthresh;
7088
7089 newfragthresh =
7090 brcms_c_calc_frame_len(wlc,
7091 rspec[0], preamble_type[0],
7092 (wlc->edcf_txop[ac] -
7093 (dur - frag_dur)));
7094 /* range bound the fragthreshold */
7095 if (newfragthresh < DOT11_MIN_FRAG_LEN)
7096 newfragthresh =
7097 DOT11_MIN_FRAG_LEN;
7098 else if (newfragthresh >
7099 wlc->usr_fragthresh)
7100 newfragthresh =
7101 wlc->usr_fragthresh;
7102 /* update the fragthresh and do txc update */
7103 if (wlc->fragthresh[queue] !=
7104 (u16) newfragthresh)
7105 wlc->fragthresh[queue] =
7106 (u16) newfragthresh;
7107 } else {
7108 wiphy_err(wlc->wiphy, "wl%d: %s txop invalid "
7109 "for rate %d\n",
7110 wlc->pub->unit, fifo_names[queue],
7111 rspec2rate(rspec[0]));
7112 }
7113
7114 if (dur > wlc->edcf_txop[ac])
7115 wiphy_err(wlc->wiphy, "wl%d: %s: %s txop "
7116 "exceeded phylen %d/%d dur %d/%d\n",
7117 wlc->pub->unit, __func__,
7118 fifo_names[queue],
7119 phylen, wlc->fragthresh[queue],
7120 dur, wlc->edcf_txop[ac]);
7121 }
7122 }
7123
7124 return 0;
7125 }
7126
7127 static int brcms_c_tx(struct brcms_c_info *wlc, struct sk_buff *skb)
7128 {
7129 struct dma_pub *dma;
7130 int fifo, ret = -ENOSPC;
7131 struct d11txh *txh;
7132 u16 frameid = INVALIDFID;
7133
7134 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(skb));
7135 dma = wlc->hw->di[fifo];
7136 txh = (struct d11txh *)(skb->data);
7137
7138 if (dma->txavail == 0) {
7139 /*
7140 * We sometimes get a frame from mac80211 after stopping
7141 * the queues. This only ever seems to be a single frame
7142 * and is seems likely to be a race. TX_HEADROOM should
7143 * ensure that we have enough space to handle these stray
7144 * packets, so warn if there isn't. If we're out of space
7145 * in the tx ring and the tx queue isn't stopped then
7146 * we've really got a bug; warn loudly if that happens.
7147 */
7148 wiphy_warn(wlc->wiphy,
7149 "Received frame for tx with no space in DMA ring\n");
7150 WARN_ON(!ieee80211_queue_stopped(wlc->pub->ieee_hw,
7151 skb_get_queue_mapping(skb)));
7152 return -ENOSPC;
7153 }
7154
7155 /* When a BC/MC frame is being committed to the BCMC fifo
7156 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
7157 */
7158 if (fifo == TX_BCMC_FIFO)
7159 frameid = le16_to_cpu(txh->TxFrameID);
7160
7161 /* Commit BCMC sequence number in the SHM frame ID location */
7162 if (frameid != INVALIDFID) {
7163 /*
7164 * To inform the ucode of the last mcast frame posted
7165 * so that it can clear moredata bit
7166 */
7167 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
7168 }
7169
7170 ret = brcms_c_txfifo(wlc, fifo, skb);
7171 /*
7172 * The only reason for brcms_c_txfifo to fail is because
7173 * there weren't any DMA descriptors, but we've already
7174 * checked for that. So if it does fail yell loudly.
7175 */
7176 WARN_ON_ONCE(ret);
7177
7178 return ret;
7179 }
7180
7181 void brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
7182 struct ieee80211_hw *hw)
7183 {
7184 uint fifo;
7185 struct scb *scb = &wlc->pri_scb;
7186
7187 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
7188 if (brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0))
7189 return;
7190 if (brcms_c_tx(wlc, sdu))
7191 dev_kfree_skb_any(sdu);
7192 }
7193
7194 int
7195 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p)
7196 {
7197 struct dma_pub *dma = wlc->hw->di[fifo];
7198 int ret;
7199 u16 queue;
7200
7201 ret = dma_txfast(wlc, dma, p);
7202 if (ret < 0)
7203 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
7204
7205 /*
7206 * Stop queue if DMA ring is full. Reserve some free descriptors,
7207 * as we sometimes receive a frame from mac80211 after the queues
7208 * are stopped.
7209 */
7210 queue = skb_get_queue_mapping(p);
7211 if (dma->txavail <= TX_HEADROOM && fifo < TX_BCMC_FIFO &&
7212 !ieee80211_queue_stopped(wlc->pub->ieee_hw, queue))
7213 ieee80211_stop_queue(wlc->pub->ieee_hw, queue);
7214
7215 return ret;
7216 }
7217
7218 u32
7219 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
7220 bool use_rspec, u16 mimo_ctlchbw)
7221 {
7222 u32 rts_rspec = 0;
7223
7224 if (use_rspec)
7225 /* use frame rate as rts rate */
7226 rts_rspec = rspec;
7227 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
7228 /* Use 11Mbps as the g protection RTS target rate and fallback.
7229 * Use the brcms_basic_rate() lookup to find the best basic rate
7230 * under the target in case 11 Mbps is not Basic.
7231 * 6 and 9 Mbps are not usually selected by rate selection, but
7232 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
7233 * is more robust.
7234 */
7235 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
7236 else
7237 /* calculate RTS rate and fallback rate based on the frame rate
7238 * RTS must be sent at a basic rate since it is a
7239 * control frame, sec 9.6 of 802.11 spec
7240 */
7241 rts_rspec = brcms_basic_rate(wlc, rspec);
7242
7243 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7244 /* set rts txbw to correct side band */
7245 rts_rspec &= ~RSPEC_BW_MASK;
7246
7247 /*
7248 * if rspec/rspec_fallback is 40MHz, then send RTS on both
7249 * 20MHz channel (DUP), otherwise send RTS on control channel
7250 */
7251 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
7252 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
7253 else
7254 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
7255
7256 /* pick siso/cdd as default for ofdm */
7257 if (is_ofdm_rate(rts_rspec)) {
7258 rts_rspec &= ~RSPEC_STF_MASK;
7259 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
7260 }
7261 }
7262 return rts_rspec;
7263 }
7264
7265 /* Update beacon listen interval in shared memory */
7266 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
7267 {
7268 /* wake up every DTIM is the default */
7269 if (wlc->bcn_li_dtim == 1)
7270 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
7271 else
7272 brcms_b_write_shm(wlc->hw, M_BCN_LI,
7273 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
7274 }
7275
7276 static void
7277 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7278 u32 *tsf_h_ptr)
7279 {
7280 struct bcma_device *core = wlc_hw->d11core;
7281
7282 /* read the tsf timer low, then high to get an atomic read */
7283 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
7284 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
7285 }
7286
7287 /*
7288 * recover 64bit TSF value from the 16bit TSF value in the rx header
7289 * given the assumption that the TSF passed in header is within 65ms
7290 * of the current tsf.
7291 *
7292 * 6 5 4 4 3 2 1
7293 * 3.......6.......8.......0.......2.......4.......6.......8......0
7294 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7295 *
7296 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7297 * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7298 * receive call sequence after rx interrupt. Only the higher 16 bits
7299 * are used. Finally, the tsf_h is read from the tsf register.
7300 */
7301 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
7302 struct d11rxhdr *rxh)
7303 {
7304 u32 tsf_h, tsf_l;
7305 u16 rx_tsf_0_15, rx_tsf_16_31;
7306
7307 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7308
7309 rx_tsf_16_31 = (u16)(tsf_l >> 16);
7310 rx_tsf_0_15 = rxh->RxTSFTime;
7311
7312 /*
7313 * a greater tsf time indicates the low 16 bits of
7314 * tsf_l wrapped, so decrement the high 16 bits.
7315 */
7316 if ((u16)tsf_l < rx_tsf_0_15) {
7317 rx_tsf_16_31 -= 1;
7318 if (rx_tsf_16_31 == 0xffff)
7319 tsf_h -= 1;
7320 }
7321
7322 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
7323 }
7324
7325 static void
7326 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7327 struct sk_buff *p,
7328 struct ieee80211_rx_status *rx_status)
7329 {
7330 int preamble;
7331 int channel;
7332 u32 rspec;
7333 unsigned char *plcp;
7334
7335 /* fill in TSF and flag its presence */
7336 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7337 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
7338
7339 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7340
7341 rx_status->band =
7342 channel > 14 ? IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
7343 rx_status->freq =
7344 ieee80211_channel_to_frequency(channel, rx_status->band);
7345
7346 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7347
7348 /* noise */
7349 /* qual */
7350 rx_status->antenna =
7351 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7352
7353 plcp = p->data;
7354
7355 rspec = brcms_c_compute_rspec(rxh, plcp);
7356 if (is_mcs_rate(rspec)) {
7357 rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7358 rx_status->flag |= RX_FLAG_HT;
7359 if (rspec_is40mhz(rspec))
7360 rx_status->flag |= RX_FLAG_40MHZ;
7361 } else {
7362 switch (rspec2rate(rspec)) {
7363 case BRCM_RATE_1M:
7364 rx_status->rate_idx = 0;
7365 break;
7366 case BRCM_RATE_2M:
7367 rx_status->rate_idx = 1;
7368 break;
7369 case BRCM_RATE_5M5:
7370 rx_status->rate_idx = 2;
7371 break;
7372 case BRCM_RATE_11M:
7373 rx_status->rate_idx = 3;
7374 break;
7375 case BRCM_RATE_6M:
7376 rx_status->rate_idx = 4;
7377 break;
7378 case BRCM_RATE_9M:
7379 rx_status->rate_idx = 5;
7380 break;
7381 case BRCM_RATE_12M:
7382 rx_status->rate_idx = 6;
7383 break;
7384 case BRCM_RATE_18M:
7385 rx_status->rate_idx = 7;
7386 break;
7387 case BRCM_RATE_24M:
7388 rx_status->rate_idx = 8;
7389 break;
7390 case BRCM_RATE_36M:
7391 rx_status->rate_idx = 9;
7392 break;
7393 case BRCM_RATE_48M:
7394 rx_status->rate_idx = 10;
7395 break;
7396 case BRCM_RATE_54M:
7397 rx_status->rate_idx = 11;
7398 break;
7399 default:
7400 wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__);
7401 }
7402
7403 /*
7404 * For 5GHz, we should decrease the index as it is
7405 * a subset of the 2.4G rates. See bitrates field
7406 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7407 */
7408 if (rx_status->band == IEEE80211_BAND_5GHZ)
7409 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7410
7411 /* Determine short preamble and rate_idx */
7412 preamble = 0;
7413 if (is_cck_rate(rspec)) {
7414 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7415 rx_status->flag |= RX_FLAG_SHORTPRE;
7416 } else if (is_ofdm_rate(rspec)) {
7417 rx_status->flag |= RX_FLAG_SHORTPRE;
7418 } else {
7419 wiphy_err(wlc->wiphy, "%s: Unknown modulation\n",
7420 __func__);
7421 }
7422 }
7423
7424 if (plcp3_issgi(plcp[3]))
7425 rx_status->flag |= RX_FLAG_SHORT_GI;
7426
7427 if (rxh->RxStatus1 & RXS_DECERR) {
7428 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7429 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
7430 __func__);
7431 }
7432 if (rxh->RxStatus1 & RXS_FCSERR) {
7433 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7434 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n",
7435 __func__);
7436 }
7437 }
7438
7439 static void
7440 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7441 struct sk_buff *p)
7442 {
7443 int len_mpdu;
7444 struct ieee80211_rx_status rx_status;
7445 struct ieee80211_hdr *hdr;
7446
7447 memset(&rx_status, 0, sizeof(rx_status));
7448 prep_mac80211_status(wlc, rxh, p, &rx_status);
7449
7450 /* mac header+body length, exclude CRC and plcp header */
7451 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7452 skb_pull(p, D11_PHY_HDR_LEN);
7453 __skb_trim(p, len_mpdu);
7454
7455 /* unmute transmit */
7456 if (wlc->hw->suspended_fifos) {
7457 hdr = (struct ieee80211_hdr *)p->data;
7458 if (ieee80211_is_beacon(hdr->frame_control))
7459 brcms_b_mute(wlc->hw, false);
7460 }
7461
7462 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7463 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7464 }
7465
7466 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7467 * number of bytes goes in the length field
7468 *
7469 * Formula given by HT PHY Spec v 1.13
7470 * len = 3(nsyms + nstream + 3) - 3
7471 */
7472 u16
7473 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7474 uint mac_len)
7475 {
7476 uint nsyms, len = 0, kNdps;
7477
7478 BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n",
7479 wlc->pub->unit, rspec2rate(ratespec), mac_len);
7480
7481 if (is_mcs_rate(ratespec)) {
7482 uint mcs = ratespec & RSPEC_RATE_MASK;
7483 int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7484 rspec_stc(ratespec);
7485
7486 /*
7487 * the payload duration calculation matches that
7488 * of regular ofdm
7489 */
7490 /* 1000Ndbps = kbps * 4 */
7491 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7492 rspec_issgi(ratespec)) * 4;
7493
7494 if (rspec_stc(ratespec) == 0)
7495 nsyms =
7496 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7497 APHY_TAIL_NBITS) * 1000, kNdps);
7498 else
7499 /* STBC needs to have even number of symbols */
7500 nsyms =
7501 2 *
7502 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7503 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7504
7505 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7506 nsyms += (tot_streams + 3);
7507 /*
7508 * 3 bytes/symbol @ legacy 6Mbps rate
7509 * (-3) excluding service bits and tail bits
7510 */
7511 len = (3 * nsyms) - 3;
7512 }
7513
7514 return (u16) len;
7515 }
7516
7517 static void
7518 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7519 {
7520 const struct brcms_c_rateset *rs_dflt;
7521 struct brcms_c_rateset rs;
7522 u8 rate;
7523 u16 entry_ptr;
7524 u8 plcp[D11_PHY_HDR_LEN];
7525 u16 dur, sifs;
7526 uint i;
7527
7528 sifs = get_sifs(wlc->band);
7529
7530 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7531
7532 brcms_c_rateset_copy(rs_dflt, &rs);
7533 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7534
7535 /*
7536 * walk the phy rate table and update MAC core SHM
7537 * basic rate table entries
7538 */
7539 for (i = 0; i < rs.count; i++) {
7540 rate = rs.rates[i] & BRCMS_RATE_MASK;
7541
7542 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7543
7544 /* Calculate the Probe Response PLCP for the given rate */
7545 brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7546
7547 /*
7548 * Calculate the duration of the Probe Response
7549 * frame plus SIFS for the MAC
7550 */
7551 dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7552 BRCMS_LONG_PREAMBLE, frame_len);
7553 dur += sifs;
7554
7555 /* Update the SHM Rate Table entry Probe Response values */
7556 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7557 (u16) (plcp[0] + (plcp[1] << 8)));
7558 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7559 (u16) (plcp[2] + (plcp[3] << 8)));
7560 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7561 }
7562 }
7563
7564 /* Max buffering needed for beacon template/prb resp template is 142 bytes.
7565 *
7566 * PLCP header is 6 bytes.
7567 * 802.11 A3 header is 24 bytes.
7568 * Max beacon frame body template length is 112 bytes.
7569 * Max probe resp frame body template length is 110 bytes.
7570 *
7571 * *len on input contains the max length of the packet available.
7572 *
7573 * The *len value is set to the number of bytes in buf used, and starts
7574 * with the PLCP and included up to, but not including, the 4 byte FCS.
7575 */
7576 static void
7577 brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
7578 u32 bcn_rspec,
7579 struct brcms_bss_cfg *cfg, u16 *buf, int *len)
7580 {
7581 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
7582 struct cck_phy_hdr *plcp;
7583 struct ieee80211_mgmt *h;
7584 int hdr_len, body_len;
7585
7586 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
7587
7588 /* calc buffer size provided for frame body */
7589 body_len = *len - hdr_len;
7590 /* return actual size */
7591 *len = hdr_len + body_len;
7592
7593 /* format PHY and MAC headers */
7594 memset((char *)buf, 0, hdr_len);
7595
7596 plcp = (struct cck_phy_hdr *) buf;
7597
7598 /*
7599 * PLCP for Probe Response frames are filled in from
7600 * core's rate table
7601 */
7602 if (type == IEEE80211_STYPE_BEACON)
7603 /* fill in PLCP */
7604 brcms_c_compute_plcp(wlc, bcn_rspec,
7605 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
7606 (u8 *) plcp);
7607
7608 /* "Regular" and 16 MBSS but not for 4 MBSS */
7609 /* Update the phytxctl for the beacon based on the rspec */
7610 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
7611
7612 h = (struct ieee80211_mgmt *)&plcp[1];
7613
7614 /* fill in 802.11 header */
7615 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
7616
7617 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
7618 /* A1 filled in by MAC for prb resp, broadcast for bcn */
7619 if (type == IEEE80211_STYPE_BEACON)
7620 memcpy(&h->da, &ether_bcast, ETH_ALEN);
7621 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
7622 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
7623
7624 /* SEQ filled in by MAC */
7625 }
7626
7627 int brcms_c_get_header_len(void)
7628 {
7629 return TXOFF;
7630 }
7631
7632 /*
7633 * Update all beacons for the system.
7634 */
7635 void brcms_c_update_beacon(struct brcms_c_info *wlc)
7636 {
7637 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7638
7639 if (bsscfg->up && !bsscfg->BSS)
7640 /* Clear the soft intmask */
7641 wlc->defmacintmask &= ~MI_BCNTPL;
7642 }
7643
7644 /* Write ssid into shared memory */
7645 static void
7646 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7647 {
7648 u8 *ssidptr = cfg->SSID;
7649 u16 base = M_SSID;
7650 u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7651
7652 /* padding the ssid with zero and copy it into shm */
7653 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7654 memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7655
7656 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7657 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7658 }
7659
7660 static void
7661 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7662 struct brcms_bss_cfg *cfg,
7663 bool suspend)
7664 {
7665 u16 prb_resp[BCN_TMPL_LEN / 2];
7666 int len = BCN_TMPL_LEN;
7667
7668 /*
7669 * write the probe response to hardware, or save in
7670 * the config structure
7671 */
7672
7673 /* create the probe response template */
7674 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
7675 cfg, prb_resp, &len);
7676
7677 if (suspend)
7678 brcms_c_suspend_mac_and_wait(wlc);
7679
7680 /* write the probe response into the template region */
7681 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7682 (len + 3) & ~3, prb_resp);
7683
7684 /* write the length of the probe response frame (+PLCP/-FCS) */
7685 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7686
7687 /* write the SSID and SSID length */
7688 brcms_c_shm_ssid_upd(wlc, cfg);
7689
7690 /*
7691 * Write PLCP headers and durations for probe response frames
7692 * at all rates. Use the actual frame length covered by the
7693 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7694 * by subtracting the PLCP len and adding the FCS.
7695 */
7696 len += (-D11_PHY_HDR_LEN + FCS_LEN);
7697 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
7698
7699 if (suspend)
7700 brcms_c_enable_mac(wlc);
7701 }
7702
7703 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7704 {
7705 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7706
7707 /* update AP or IBSS probe responses */
7708 if (bsscfg->up && !bsscfg->BSS)
7709 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
7710 }
7711
7712 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7713 uint *blocks)
7714 {
7715 if (fifo >= NFIFO)
7716 return -EINVAL;
7717
7718 *blocks = wlc_hw->xmtfifo_sz[fifo];
7719
7720 return 0;
7721 }
7722
7723 void
7724 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7725 const u8 *addr)
7726 {
7727 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7728 if (match_reg_offset == RCM_BSSID_OFFSET)
7729 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7730 }
7731
7732 /*
7733 * Flag 'scan in progress' to withhold dynamic phy calibration
7734 */
7735 void brcms_c_scan_start(struct brcms_c_info *wlc)
7736 {
7737 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7738 }
7739
7740 void brcms_c_scan_stop(struct brcms_c_info *wlc)
7741 {
7742 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7743 }
7744
7745 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7746 {
7747 wlc->pub->associated = state;
7748 wlc->bsscfg->associated = state;
7749 }
7750
7751 /*
7752 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7753 * AMPDU traffic, packets pending in hardware have to be invalidated so that
7754 * when later on hardware releases them, they can be handled appropriately.
7755 */
7756 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7757 struct ieee80211_sta *sta,
7758 void (*dma_callback_fn))
7759 {
7760 struct dma_pub *dmah;
7761 int i;
7762 for (i = 0; i < NFIFO; i++) {
7763 dmah = hw->di[i];
7764 if (dmah != NULL)
7765 dma_walk_packets(dmah, dma_callback_fn, sta);
7766 }
7767 }
7768
7769 int brcms_c_get_curband(struct brcms_c_info *wlc)
7770 {
7771 return wlc->band->bandunit;
7772 }
7773
7774 void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop)
7775 {
7776 int timeout = 20;
7777 int i;
7778
7779 /* Kick DMA to send any pending AMPDU */
7780 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
7781 if (wlc->hw->di[i])
7782 dma_txflush(wlc->hw->di[i]);
7783
7784 /* wait for queue and DMA fifos to run dry */
7785 while (brcms_txpktpendtot(wlc) > 0) {
7786 brcms_msleep(wlc->wl, 1);
7787
7788 if (--timeout == 0)
7789 break;
7790 }
7791
7792 WARN_ON_ONCE(timeout == 0);
7793 }
7794
7795 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7796 {
7797 wlc->bcn_li_bcn = interval;
7798 if (wlc->pub->up)
7799 brcms_c_bcn_li_upd(wlc);
7800 }
7801
7802 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7803 {
7804 uint qdbm;
7805
7806 /* Remove override bit and clip to max qdbm value */
7807 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7808 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7809 }
7810
7811 int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7812 {
7813 uint qdbm;
7814 bool override;
7815
7816 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7817
7818 /* Return qdbm units */
7819 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
7820 }
7821
7822 /* Process received frames */
7823 /*
7824 * Return true if more frames need to be processed. false otherwise.
7825 * Param 'bound' indicates max. # frames to process before break out.
7826 */
7827 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
7828 {
7829 struct d11rxhdr *rxh;
7830 struct ieee80211_hdr *h;
7831 uint len;
7832 bool is_amsdu;
7833
7834 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
7835
7836 /* frame starts with rxhdr */
7837 rxh = (struct d11rxhdr *) (p->data);
7838
7839 /* strip off rxhdr */
7840 skb_pull(p, BRCMS_HWRXOFF);
7841
7842 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7843 if (rxh->RxStatus1 & RXS_PBPRES) {
7844 if (p->len < 2) {
7845 wiphy_err(wlc->wiphy, "wl%d: recv: rcvd runt of "
7846 "len %d\n", wlc->pub->unit, p->len);
7847 goto toss;
7848 }
7849 skb_pull(p, 2);
7850 }
7851
7852 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
7853 len = p->len;
7854
7855 if (rxh->RxStatus1 & RXS_FCSERR) {
7856 if (!(wlc->filter_flags & FIF_FCSFAIL))
7857 goto toss;
7858 }
7859
7860 /* check received pkt has at least frame control field */
7861 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
7862 goto toss;
7863
7864 /* not supporting A-MSDU */
7865 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
7866 if (is_amsdu)
7867 goto toss;
7868
7869 brcms_c_recvctl(wlc, rxh, p);
7870 return;
7871
7872 toss:
7873 brcmu_pkt_buf_free_skb(p);
7874 }
7875
7876 /* Process received frames */
7877 /*
7878 * Return true if more frames need to be processed. false otherwise.
7879 * Param 'bound' indicates max. # frames to process before break out.
7880 */
7881 static bool
7882 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
7883 {
7884 struct sk_buff *p;
7885 struct sk_buff *next = NULL;
7886 struct sk_buff_head recv_frames;
7887
7888 uint n = 0;
7889 uint bound_limit = bound ? RXBND : -1;
7890
7891 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
7892 skb_queue_head_init(&recv_frames);
7893
7894 /* gather received frames */
7895 while (dma_rx(wlc_hw->di[fifo], &recv_frames)) {
7896
7897 /* !give others some time to run! */
7898 if (++n >= bound_limit)
7899 break;
7900 }
7901
7902 /* post more rbufs */
7903 dma_rxfill(wlc_hw->di[fifo]);
7904
7905 /* process each frame */
7906 skb_queue_walk_safe(&recv_frames, p, next) {
7907 struct d11rxhdr_le *rxh_le;
7908 struct d11rxhdr *rxh;
7909
7910 skb_unlink(p, &recv_frames);
7911 rxh_le = (struct d11rxhdr_le *)p->data;
7912 rxh = (struct d11rxhdr *)p->data;
7913
7914 /* fixup rx header endianness */
7915 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
7916 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
7917 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
7918 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
7919 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
7920 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
7921 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
7922 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
7923 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
7924 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
7925 rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
7926
7927 brcms_c_recv(wlc_hw->wlc, p);
7928 }
7929
7930 return n >= bound_limit;
7931 }
7932
7933 /* second-level interrupt processing
7934 * Return true if another dpc needs to be re-scheduled. false otherwise.
7935 * Param 'bounded' indicates if applicable loops should be bounded.
7936 */
7937 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
7938 {
7939 u32 macintstatus;
7940 struct brcms_hardware *wlc_hw = wlc->hw;
7941 struct bcma_device *core = wlc_hw->d11core;
7942 struct wiphy *wiphy = wlc->wiphy;
7943
7944 if (brcms_deviceremoved(wlc)) {
7945 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
7946 __func__);
7947 brcms_down(wlc->wl);
7948 return false;
7949 }
7950
7951 /* grab and clear the saved software intstatus bits */
7952 macintstatus = wlc->macintstatus;
7953 wlc->macintstatus = 0;
7954
7955 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
7956 wlc_hw->unit, macintstatus);
7957
7958 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
7959
7960 /* tx status */
7961 if (macintstatus & MI_TFS) {
7962 bool fatal;
7963 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
7964 wlc->macintstatus |= MI_TFS;
7965 if (fatal) {
7966 wiphy_err(wiphy, "MI_TFS: fatal\n");
7967 goto fatal;
7968 }
7969 }
7970
7971 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
7972 brcms_c_tbtt(wlc);
7973
7974 /* ATIM window end */
7975 if (macintstatus & MI_ATIMWINEND) {
7976 BCMMSG(wlc->wiphy, "end of ATIM window\n");
7977 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
7978 wlc->qvalid = 0;
7979 }
7980
7981 /*
7982 * received data or control frame, MI_DMAINT is
7983 * indication of RX_FIFO interrupt
7984 */
7985 if (macintstatus & MI_DMAINT)
7986 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
7987 wlc->macintstatus |= MI_DMAINT;
7988
7989 /* noise sample collected */
7990 if (macintstatus & MI_BG_NOISE)
7991 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
7992
7993 if (macintstatus & MI_GP0) {
7994 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
7995 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
7996
7997 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
7998 __func__, ai_get_chip_id(wlc_hw->sih),
7999 ai_get_chiprev(wlc_hw->sih));
8000 brcms_fatal_error(wlc_hw->wlc->wl);
8001 }
8002
8003 /* gptimer timeout */
8004 if (macintstatus & MI_TO)
8005 bcma_write32(core, D11REGOFFS(gptimer), 0);
8006
8007 if (macintstatus & MI_RFDISABLE) {
8008 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
8009 " RF Disable Input\n", wlc_hw->unit);
8010 brcms_rfkill_set_hw_state(wlc->wl);
8011 }
8012
8013 /* it isn't done and needs to be resched if macintstatus is non-zero */
8014 return wlc->macintstatus != 0;
8015
8016 fatal:
8017 brcms_fatal_error(wlc_hw->wlc->wl);
8018 return wlc->macintstatus != 0;
8019 }
8020
8021 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
8022 {
8023 struct bcma_device *core = wlc->hw->d11core;
8024 struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
8025 u16 chanspec;
8026
8027 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
8028
8029 chanspec = ch20mhz_chspec(ch->hw_value);
8030
8031 brcms_b_init(wlc->hw, chanspec);
8032
8033 /* update beacon listen interval */
8034 brcms_c_bcn_li_upd(wlc);
8035
8036 /* write ethernet address to core */
8037 brcms_c_set_mac(wlc->bsscfg);
8038 brcms_c_set_bssid(wlc->bsscfg);
8039
8040 /* Update tsf_cfprep if associated and up */
8041 if (wlc->pub->associated && wlc->bsscfg->up) {
8042 u32 bi;
8043
8044 /* get beacon period and convert to uS */
8045 bi = wlc->bsscfg->current_bss->beacon_period << 10;
8046 /*
8047 * update since init path would reset
8048 * to default value
8049 */
8050 bcma_write32(core, D11REGOFFS(tsf_cfprep),
8051 bi << CFPREP_CBI_SHIFT);
8052
8053 /* Update maccontrol PM related bits */
8054 brcms_c_set_ps_ctrl(wlc);
8055 }
8056
8057 brcms_c_bandinit_ordered(wlc, chanspec);
8058
8059 /* init probe response timeout */
8060 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
8061
8062 /* init max burst txop (framebursting) */
8063 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
8064 (wlc->
8065 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
8066
8067 /* initialize maximum allowed duty cycle */
8068 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
8069 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
8070
8071 /*
8072 * Update some shared memory locations related to
8073 * max AMPDU size allowed to received
8074 */
8075 brcms_c_ampdu_shm_upd(wlc->ampdu);
8076
8077 /* band-specific inits */
8078 brcms_c_bsinit(wlc);
8079
8080 /* Enable EDCF mode (while the MAC is suspended) */
8081 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
8082 brcms_c_edcf_setparams(wlc, false);
8083
8084 /* read the ucode version if we have not yet done so */
8085 if (wlc->ucode_rev == 0) {
8086 wlc->ucode_rev =
8087 brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16);
8088 wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
8089 }
8090
8091 /* ..now really unleash hell (allow the MAC out of suspend) */
8092 brcms_c_enable_mac(wlc);
8093
8094 /* suspend the tx fifos and mute the phy for preism cac time */
8095 if (mute_tx)
8096 brcms_b_mute(wlc->hw, true);
8097
8098 /* enable the RF Disable Delay timer */
8099 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
8100
8101 /*
8102 * Initialize WME parameters; if they haven't been set by some other
8103 * mechanism (IOVar, etc) then read them from the hardware.
8104 */
8105 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
8106 /* Uninitialized; read from HW */
8107 int ac;
8108
8109 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
8110 wlc->wme_retries[ac] =
8111 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
8112 }
8113 }
8114
8115 /*
8116 * The common driver entry routine. Error codes should be unique
8117 */
8118 struct brcms_c_info *
8119 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
8120 bool piomode, uint *perr)
8121 {
8122 struct brcms_c_info *wlc;
8123 uint err = 0;
8124 uint i, j;
8125 struct brcms_pub *pub;
8126
8127 /* allocate struct brcms_c_info state and its substructures */
8128 wlc = brcms_c_attach_malloc(unit, &err, 0);
8129 if (wlc == NULL)
8130 goto fail;
8131 wlc->wiphy = wl->wiphy;
8132 pub = wlc->pub;
8133
8134 #if defined(DEBUG)
8135 wlc_info_dbg = wlc;
8136 #endif
8137
8138 wlc->band = wlc->bandstate[0];
8139 wlc->core = wlc->corestate;
8140 wlc->wl = wl;
8141 pub->unit = unit;
8142 pub->_piomode = piomode;
8143 wlc->bandinit_pending = false;
8144
8145 /* populate struct brcms_c_info with default values */
8146 brcms_c_info_init(wlc, unit);
8147
8148 /* update sta/ap related parameters */
8149 brcms_c_ap_upd(wlc);
8150
8151 /*
8152 * low level attach steps(all hw accesses go
8153 * inside, no more in rest of the attach)
8154 */
8155 err = brcms_b_attach(wlc, core, unit, piomode);
8156 if (err)
8157 goto fail;
8158
8159 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
8160
8161 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
8162
8163 /* disable allowed duty cycle */
8164 wlc->tx_duty_cycle_ofdm = 0;
8165 wlc->tx_duty_cycle_cck = 0;
8166
8167 brcms_c_stf_phy_chain_calc(wlc);
8168
8169 /* txchain 1: txant 0, txchain 2: txant 1 */
8170 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
8171 wlc->stf->txant = wlc->stf->hw_txchain - 1;
8172
8173 /* push to BMAC driver */
8174 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
8175 wlc->stf->hw_rxchain);
8176
8177 /* pull up some info resulting from the low attach */
8178 for (i = 0; i < NFIFO; i++)
8179 wlc->core->txavail[i] = wlc->hw->txavail[i];
8180
8181 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8182 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8183
8184 for (j = 0; j < wlc->pub->_nbands; j++) {
8185 wlc->band = wlc->bandstate[j];
8186
8187 if (!brcms_c_attach_stf_ant_init(wlc)) {
8188 err = 24;
8189 goto fail;
8190 }
8191
8192 /* default contention windows size limits */
8193 wlc->band->CWmin = APHY_CWMIN;
8194 wlc->band->CWmax = PHY_CWMAX;
8195
8196 /* init gmode value */
8197 if (wlc->band->bandtype == BRCM_BAND_2G) {
8198 wlc->band->gmode = GMODE_AUTO;
8199 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
8200 wlc->band->gmode);
8201 }
8202
8203 /* init _n_enab supported mode */
8204 if (BRCMS_PHY_11N_CAP(wlc->band)) {
8205 pub->_n_enab = SUPPORT_11N;
8206 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
8207 ((pub->_n_enab ==
8208 SUPPORT_11N) ? WL_11N_2x2 :
8209 WL_11N_3x3));
8210 }
8211
8212 /* init per-band default rateset, depend on band->gmode */
8213 brcms_default_rateset(wlc, &wlc->band->defrateset);
8214
8215 /* fill in hw_rateset */
8216 brcms_c_rateset_filter(&wlc->band->defrateset,
8217 &wlc->band->hw_rateset, false,
8218 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
8219 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
8220 }
8221
8222 /*
8223 * update antenna config due to
8224 * wlc->stf->txant/txchain/ant_rx_ovr change
8225 */
8226 brcms_c_stf_phy_txant_upd(wlc);
8227
8228 /* attach each modules */
8229 err = brcms_c_attach_module(wlc);
8230 if (err != 0)
8231 goto fail;
8232
8233 if (!brcms_c_timers_init(wlc, unit)) {
8234 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
8235 __func__);
8236 err = 32;
8237 goto fail;
8238 }
8239
8240 /* depend on rateset, gmode */
8241 wlc->cmi = brcms_c_channel_mgr_attach(wlc);
8242 if (!wlc->cmi) {
8243 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
8244 "\n", unit, __func__);
8245 err = 33;
8246 goto fail;
8247 }
8248
8249 /* init default when all parameters are ready, i.e. ->rateset */
8250 brcms_c_bss_default_init(wlc);
8251
8252 /*
8253 * Complete the wlc default state initializations..
8254 */
8255
8256 wlc->bsscfg->wlc = wlc;
8257
8258 wlc->mimoft = FT_HT;
8259 wlc->mimo_40txbw = AUTO;
8260 wlc->ofdm_40txbw = AUTO;
8261 wlc->cck_40txbw = AUTO;
8262 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
8263
8264 /* Set default values of SGI */
8265 if (BRCMS_SGI_CAP_PHY(wlc)) {
8266 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8267 BRCMS_N_SGI_40));
8268 } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
8269 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8270 BRCMS_N_SGI_40));
8271 } else {
8272 brcms_c_ht_update_sgi_rx(wlc, 0);
8273 }
8274
8275 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8276
8277 if (perr)
8278 *perr = 0;
8279
8280 return wlc;
8281
8282 fail:
8283 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8284 unit, __func__, err);
8285 if (wlc)
8286 brcms_c_detach(wlc);
8287
8288 if (perr)
8289 *perr = err;
8290 return NULL;
8291 }