2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
25 #include <chipcommon.h>
28 #include "phy/phy_hal.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
40 /* watchdog timer, in unit of ms */
41 #define TIMER_INTERVAL_WATCHDOG 1000
42 /* radio monitor timer, in unit of ms */
43 #define TIMER_INTERVAL_RADIOCHK 800
45 /* beacon interval, in unit of 1024TU */
46 #define BEACON_INTERVAL_DEFAULT 100
48 /* n-mode support capability */
49 /* 2x2 includes both 1x1 & 2x2 devices
50 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
51 * control it independently
57 #define EDCF_ACI_MASK 0x60
58 #define EDCF_ACI_SHIFT 5
59 #define EDCF_ECWMIN_MASK 0x0f
60 #define EDCF_ECWMAX_SHIFT 4
61 #define EDCF_AIFSN_MASK 0x0f
62 #define EDCF_AIFSN_MAX 15
63 #define EDCF_ECWMAX_MASK 0xf0
65 #define EDCF_AC_BE_TXOP_STA 0x0000
66 #define EDCF_AC_BK_TXOP_STA 0x0000
67 #define EDCF_AC_VO_ACI_STA 0x62
68 #define EDCF_AC_VO_ECW_STA 0x32
69 #define EDCF_AC_VI_ACI_STA 0x42
70 #define EDCF_AC_VI_ECW_STA 0x43
71 #define EDCF_AC_BK_ECW_STA 0xA4
72 #define EDCF_AC_VI_TXOP_STA 0x005e
73 #define EDCF_AC_VO_TXOP_STA 0x002f
74 #define EDCF_AC_BE_ACI_STA 0x03
75 #define EDCF_AC_BE_ECW_STA 0xA4
76 #define EDCF_AC_BK_ACI_STA 0x27
77 #define EDCF_AC_VO_TXOP_AP 0x002f
79 #define EDCF_TXOP2USEC(txop) ((txop) << 5)
80 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
82 #define APHY_SYMBOL_TIME 4
83 #define APHY_PREAMBLE_TIME 16
84 #define APHY_SIGNAL_TIME 4
85 #define APHY_SIFS_TIME 16
86 #define APHY_SERVICE_NBITS 16
87 #define APHY_TAIL_NBITS 6
88 #define BPHY_SIFS_TIME 10
89 #define BPHY_PLCP_SHORT_TIME 96
91 #define PREN_PREAMBLE 24
92 #define PREN_MM_EXT 12
93 #define PREN_PREAMBLE_EXT 4
95 #define DOT11_MAC_HDR_LEN 24
96 #define DOT11_ACK_LEN 10
97 #define DOT11_BA_LEN 4
98 #define DOT11_OFDM_SIGNAL_EXTENSION 6
99 #define DOT11_MIN_FRAG_LEN 256
100 #define DOT11_RTS_LEN 16
101 #define DOT11_CTS_LEN 10
102 #define DOT11_BA_BITMAP_LEN 128
103 #define DOT11_MIN_BEACON_PERIOD 1
104 #define DOT11_MAX_BEACON_PERIOD 0xFFFF
105 #define DOT11_MAXNUMFRAGS 16
106 #define DOT11_MAX_FRAG_LEN 2346
108 #define BPHY_PLCP_TIME 192
109 #define RIFS_11N_TIME 2
111 /* length of the BCN template area */
112 #define BCN_TMPL_LEN 512
114 /* brcms_bss_info flag bit values */
115 #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
117 /* chip rx buffer offset */
118 #define BRCMS_HWRXOFF 38
120 /* rfdisable delay timer 500 ms, runs of ALP clock */
121 #define RFDISABLE_DEFAULT 10000000
123 #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
125 /* precedences numbers for wlc queues. These are twice as may levels as
127 * Odd numbers are used for HI priority traffic at same precedence levels
128 * These constants are used ONLY by wlc_prio2prec_map. Do not use them
131 #define _BRCMS_PREC_NONE 0 /* None = - */
132 #define _BRCMS_PREC_BK 2 /* BK - Background */
133 #define _BRCMS_PREC_BE 4 /* BE - Best-effort */
134 #define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */
135 #define _BRCMS_PREC_CL 8 /* CL - Controlled Load */
136 #define _BRCMS_PREC_VI 10 /* Vi - Video */
137 #define _BRCMS_PREC_VO 12 /* Vo - Voice */
138 #define _BRCMS_PREC_NC 14 /* NC - Network Control */
140 /* synthpu_dly times in us */
141 #define SYNTHPU_DLY_APHY_US 3700
142 #define SYNTHPU_DLY_BPHY_US 1050
143 #define SYNTHPU_DLY_NPHY_US 2048
144 #define SYNTHPU_DLY_LPPHY_US 300
146 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
148 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
149 #define EDCF_SHORT_S 0
151 #define EDCF_LONG_S 8
152 #define EDCF_LFB_S 12
153 #define EDCF_SHORT_M BITFIELD_MASK(4)
154 #define EDCF_SFB_M BITFIELD_MASK(4)
155 #define EDCF_LONG_M BITFIELD_MASK(4)
156 #define EDCF_LFB_M BITFIELD_MASK(4)
158 #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
159 #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
160 #define RETRY_LONG_DEF 4 /* Default Long retry count */
161 #define RETRY_SHORT_FB 3 /* Short count for fb rate */
162 #define RETRY_LONG_FB 2 /* Long count for fb rate */
164 #define APHY_CWMIN 15
165 #define PHY_CWMAX 1023
167 #define EDCF_AIFSN_MIN 1
169 #define FRAGNUM_MASK 0xF
171 #define APHY_SLOT_TIME 9
172 #define BPHY_SLOT_TIME 20
174 #define WL_SPURAVOID_OFF 0
175 #define WL_SPURAVOID_ON1 1
176 #define WL_SPURAVOID_ON2 2
178 /* invalid core flags, use the saved coreflags */
179 #define BRCMS_USE_COREFLAGS 0xffffffff
181 /* values for PLCPHdr_override */
182 #define BRCMS_PLCP_AUTO -1
183 #define BRCMS_PLCP_SHORT 0
184 #define BRCMS_PLCP_LONG 1
186 /* values for g_protection_override and n_protection_override */
187 #define BRCMS_PROTECTION_AUTO -1
188 #define BRCMS_PROTECTION_OFF 0
189 #define BRCMS_PROTECTION_ON 1
190 #define BRCMS_PROTECTION_MMHDR_ONLY 2
191 #define BRCMS_PROTECTION_CTS_ONLY 3
193 /* values for g_protection_control and n_protection_control */
194 #define BRCMS_PROTECTION_CTL_OFF 0
195 #define BRCMS_PROTECTION_CTL_LOCAL 1
196 #define BRCMS_PROTECTION_CTL_OVERLAP 2
198 /* values for n_protection */
199 #define BRCMS_N_PROTECTION_OFF 0
200 #define BRCMS_N_PROTECTION_OPTIONAL 1
201 #define BRCMS_N_PROTECTION_20IN40 2
202 #define BRCMS_N_PROTECTION_MIXEDMODE 3
204 /* values for band specific 40MHz capabilities */
205 #define BRCMS_N_BW_20ALL 0
206 #define BRCMS_N_BW_40ALL 1
207 #define BRCMS_N_BW_20IN2G_40IN5G 2
209 /* bitflags for SGI support (sgi_rx iovar) */
210 #define BRCMS_N_SGI_20 0x01
211 #define BRCMS_N_SGI_40 0x02
213 /* defines used by the nrate iovar */
214 /* MSC in use,indicates b0-6 holds an mcs */
215 #define NRATE_MCS_INUSE 0x00000080
217 #define NRATE_RATE_MASK 0x0000007f
218 /* stf mode mask: siso, cdd, stbc, sdm */
219 #define NRATE_STF_MASK 0x0000ff00
221 #define NRATE_STF_SHIFT 8
222 /* bit indicate to override mcs only */
223 #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
224 #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
225 #define NRATE_SGI_SHIFT 23 /* sgi mode */
226 #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
227 #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
229 #define NRATE_STF_SISO 0 /* stf mode SISO */
230 #define NRATE_STF_CDD 1 /* stf mode CDD */
231 #define NRATE_STF_STBC 2 /* stf mode STBC */
232 #define NRATE_STF_SDM 3 /* stf mode SDM */
234 #define MAX_DMA_SEGS 4
236 /* # of entries in Tx FIFO */
238 /* Max # of entries in Rx FIFO based on 4kb page size */
241 /* Amount of headroom to leave in Tx FIFO */
242 #define TX_HEADROOM 4
244 /* try to keep this # rbufs posted to the chip */
245 #define NRXBUFPOST 32
247 /* max # frames to process in brcms_c_recv() */
249 /* max # tx status to process in wlc_txstatus() */
252 /* brcmu_format_flags() bit description structure */
253 struct brcms_c_bit_desc
{
259 * The following table lists the buffer memory allocated to xmt fifos in HW.
260 * the size is in units of 256bytes(one block), total size is HW dependent
261 * ucode has default fifo partition, sw can overwrite if necessary
263 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
264 * the twiki is updated before making changes.
267 /* Starting corerev for the fifo size table */
268 #define XMTFIFOTBL_STARTREV 17
276 struct edcf_acparam
{
285 /* TX FIFO number to WME/802.1E Access Category */
286 static const u8 wme_fifo2ac
[] = {
295 /* ieee80211 Access Category to TX FIFO number */
296 static const u8 wme_ac2fifo
[] = {
303 /* 802.1D Priority to precedence queue mapping */
304 const u8 wlc_prio2prec_map
[] = {
305 _BRCMS_PREC_BE
, /* 0 BE - Best-effort */
306 _BRCMS_PREC_BK
, /* 1 BK - Background */
307 _BRCMS_PREC_NONE
, /* 2 None = - */
308 _BRCMS_PREC_EE
, /* 3 EE - Excellent-effort */
309 _BRCMS_PREC_CL
, /* 4 CL - Controlled Load */
310 _BRCMS_PREC_VI
, /* 5 Vi - Video */
311 _BRCMS_PREC_VO
, /* 6 Vo - Voice */
312 _BRCMS_PREC_NC
, /* 7 NC - Network Control */
315 static const u16 xmtfifo_sz
[][NFIFO
] = {
316 /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
317 {20, 192, 192, 21, 17, 5},
322 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
323 {20, 192, 192, 21, 17, 5},
324 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
325 {9, 58, 22, 14, 14, 5},
326 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
327 {20, 192, 192, 21, 17, 5},
328 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
329 {20, 192, 192, 21, 17, 5},
330 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
331 {9, 58, 22, 14, 14, 5},
338 /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
339 {9, 58, 22, 14, 14, 5},
343 static const char * const fifo_names
[] = {
344 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
346 static const char fifo_names
[6][0];
350 /* pointer to most recently allocated wl/wlc */
351 static struct brcms_c_info
*wlc_info_dbg
= (struct brcms_c_info
*) (NULL
);
354 /* Mapping of ieee80211 AC numbers to tx fifos */
355 static const u8 ac_to_fifo_mapping
[IEEE80211_NUM_ACS
] = {
356 [IEEE80211_AC_VO
] = TX_AC_VO_FIFO
,
357 [IEEE80211_AC_VI
] = TX_AC_VI_FIFO
,
358 [IEEE80211_AC_BE
] = TX_AC_BE_FIFO
,
359 [IEEE80211_AC_BK
] = TX_AC_BK_FIFO
,
362 /* Mapping of tx fifos to ieee80211 AC numbers */
363 static const u8 fifo_to_ac_mapping
[IEEE80211_NUM_ACS
] = {
364 [TX_AC_BK_FIFO
] = IEEE80211_AC_BK
,
365 [TX_AC_BE_FIFO
] = IEEE80211_AC_BE
,
366 [TX_AC_VI_FIFO
] = IEEE80211_AC_VI
,
367 [TX_AC_VO_FIFO
] = IEEE80211_AC_VO
,
370 static u8
brcms_ac_to_fifo(u8 ac
)
372 if (ac
>= ARRAY_SIZE(ac_to_fifo_mapping
))
373 return TX_AC_BE_FIFO
;
374 return ac_to_fifo_mapping
[ac
];
377 static u8
brcms_fifo_to_ac(u8 fifo
)
379 if (fifo
>= ARRAY_SIZE(fifo_to_ac_mapping
))
380 return IEEE80211_AC_BE
;
381 return fifo_to_ac_mapping
[fifo
];
384 /* Find basic rate for a given rate */
385 static u8
brcms_basic_rate(struct brcms_c_info
*wlc
, u32 rspec
)
387 if (is_mcs_rate(rspec
))
388 return wlc
->band
->basic_rate
[mcs_table
[rspec
& RSPEC_RATE_MASK
]
390 return wlc
->band
->basic_rate
[rspec
& RSPEC_RATE_MASK
];
393 static u16
frametype(u32 rspec
, u8 mimoframe
)
395 if (is_mcs_rate(rspec
))
397 return is_cck_rate(rspec
) ? FT_CCK
: FT_OFDM
;
400 /* currently the best mechanism for determining SIFS is the band in use */
401 static u16
get_sifs(struct brcms_band
*band
)
403 return band
->bandtype
== BRCM_BAND_5G
? APHY_SIFS_TIME
:
408 * Detect Card removed.
409 * Even checking an sbconfig register read will not false trigger when the core
410 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
411 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
412 * reg with fixed 0/1 pattern (some platforms return all 0).
413 * If clocks are present, call the sb routine which will figure out if the
416 static bool brcms_deviceremoved(struct brcms_c_info
*wlc
)
421 return ai_deviceremoved(wlc
->hw
->sih
);
422 macctrl
= bcma_read32(wlc
->hw
->d11core
,
423 D11REGOFFS(maccontrol
));
424 return (macctrl
& (MCTL_PSM_JMP_0
| MCTL_IHR_EN
)) != MCTL_IHR_EN
;
427 /* sum the individual fifo tx pending packet counts */
428 static int brcms_txpktpendtot(struct brcms_c_info
*wlc
)
433 for (i
= 0; i
< ARRAY_SIZE(wlc
->hw
->di
); i
++)
435 pending
+= dma_txpending(wlc
->hw
->di
[i
]);
439 static bool brcms_is_mband_unlocked(struct brcms_c_info
*wlc
)
441 return wlc
->pub
->_nbands
> 1 && !wlc
->bandlocked
;
444 static int brcms_chspec_bw(u16 chanspec
)
446 if (CHSPEC_IS40(chanspec
))
448 if (CHSPEC_IS20(chanspec
))
454 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg
*cfg
)
459 kfree(cfg
->current_bss
);
463 static void brcms_c_detach_mfree(struct brcms_c_info
*wlc
)
468 brcms_c_bsscfg_mfree(wlc
->bsscfg
);
470 kfree(wlc
->modulecb
);
471 kfree(wlc
->default_bss
);
472 kfree(wlc
->protection
);
474 kfree(wlc
->bandstate
[0]);
475 kfree(wlc
->corestate
->macstat_snapshot
);
476 kfree(wlc
->corestate
);
477 kfree(wlc
->hw
->bandstate
[0]);
485 static struct brcms_bss_cfg
*brcms_c_bsscfg_malloc(uint unit
)
487 struct brcms_bss_cfg
*cfg
;
489 cfg
= kzalloc(sizeof(struct brcms_bss_cfg
), GFP_ATOMIC
);
493 cfg
->current_bss
= kzalloc(sizeof(struct brcms_bss_info
), GFP_ATOMIC
);
494 if (cfg
->current_bss
== NULL
)
500 brcms_c_bsscfg_mfree(cfg
);
504 static struct brcms_c_info
*
505 brcms_c_attach_malloc(uint unit
, uint
*err
, uint devid
)
507 struct brcms_c_info
*wlc
;
509 wlc
= kzalloc(sizeof(struct brcms_c_info
), GFP_ATOMIC
);
515 /* allocate struct brcms_c_pub state structure */
516 wlc
->pub
= kzalloc(sizeof(struct brcms_pub
), GFP_ATOMIC
);
517 if (wlc
->pub
== NULL
) {
523 /* allocate struct brcms_hardware state structure */
525 wlc
->hw
= kzalloc(sizeof(struct brcms_hardware
), GFP_ATOMIC
);
526 if (wlc
->hw
== NULL
) {
532 wlc
->hw
->bandstate
[0] =
533 kzalloc(sizeof(struct brcms_hw_band
) * MAXBANDS
, GFP_ATOMIC
);
534 if (wlc
->hw
->bandstate
[0] == NULL
) {
540 for (i
= 1; i
< MAXBANDS
; i
++)
541 wlc
->hw
->bandstate
[i
] = (struct brcms_hw_band
*)
542 ((unsigned long)wlc
->hw
->bandstate
[0] +
543 (sizeof(struct brcms_hw_band
) * i
));
547 kzalloc(sizeof(struct modulecb
) * BRCMS_MAXMODULES
, GFP_ATOMIC
);
548 if (wlc
->modulecb
== NULL
) {
553 wlc
->default_bss
= kzalloc(sizeof(struct brcms_bss_info
), GFP_ATOMIC
);
554 if (wlc
->default_bss
== NULL
) {
559 wlc
->bsscfg
= brcms_c_bsscfg_malloc(unit
);
560 if (wlc
->bsscfg
== NULL
) {
565 wlc
->protection
= kzalloc(sizeof(struct brcms_protection
),
567 if (wlc
->protection
== NULL
) {
572 wlc
->stf
= kzalloc(sizeof(struct brcms_stf
), GFP_ATOMIC
);
573 if (wlc
->stf
== NULL
) {
579 kzalloc(sizeof(struct brcms_band
)*MAXBANDS
, GFP_ATOMIC
);
580 if (wlc
->bandstate
[0] == NULL
) {
586 for (i
= 1; i
< MAXBANDS
; i
++)
587 wlc
->bandstate
[i
] = (struct brcms_band
*)
588 ((unsigned long)wlc
->bandstate
[0]
589 + (sizeof(struct brcms_band
)*i
));
592 wlc
->corestate
= kzalloc(sizeof(struct brcms_core
), GFP_ATOMIC
);
593 if (wlc
->corestate
== NULL
) {
598 wlc
->corestate
->macstat_snapshot
=
599 kzalloc(sizeof(struct macstat
), GFP_ATOMIC
);
600 if (wlc
->corestate
->macstat_snapshot
== NULL
) {
608 brcms_c_detach_mfree(wlc
);
613 * Update the slot timing for standard 11b/g (20us slots)
614 * or shortslot 11g (9us slots)
615 * The PSM needs to be suspended for this call.
617 static void brcms_b_update_slot_timing(struct brcms_hardware
*wlc_hw
,
620 struct bcma_device
*core
= wlc_hw
->d11core
;
623 /* 11g short slot: 11a timing */
624 bcma_write16(core
, D11REGOFFS(ifs_slot
), 0x0207);
625 brcms_b_write_shm(wlc_hw
, M_DOT11_SLOT
, APHY_SLOT_TIME
);
627 /* 11g long slot: 11b timing */
628 bcma_write16(core
, D11REGOFFS(ifs_slot
), 0x0212);
629 brcms_b_write_shm(wlc_hw
, M_DOT11_SLOT
, BPHY_SLOT_TIME
);
634 * calculate frame duration of a given rate and length, return
637 static uint
brcms_c_calc_frame_time(struct brcms_c_info
*wlc
, u32 ratespec
,
638 u8 preamble_type
, uint mac_len
)
640 uint nsyms
, dur
= 0, Ndps
, kNdps
;
641 uint rate
= rspec2rate(ratespec
);
644 brcms_err(wlc
->hw
->d11core
, "wl%d: WAR: using rate of 1 mbps\n",
649 brcms_dbg_mac80211(wlc
->hw
->d11core
,
650 "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
651 wlc
->pub
->unit
, ratespec
, preamble_type
, mac_len
);
653 if (is_mcs_rate(ratespec
)) {
654 uint mcs
= ratespec
& RSPEC_RATE_MASK
;
655 int tot_streams
= mcs_2_txstreams(mcs
) + rspec_stc(ratespec
);
657 dur
= PREN_PREAMBLE
+ (tot_streams
* PREN_PREAMBLE_EXT
);
658 if (preamble_type
== BRCMS_MM_PREAMBLE
)
660 /* 1000Ndbps = kbps * 4 */
661 kNdps
= mcs_2_rate(mcs
, rspec_is40mhz(ratespec
),
662 rspec_issgi(ratespec
)) * 4;
664 if (rspec_stc(ratespec
) == 0)
666 CEIL((APHY_SERVICE_NBITS
+ 8 * mac_len
+
667 APHY_TAIL_NBITS
) * 1000, kNdps
);
669 /* STBC needs to have even number of symbols */
672 CEIL((APHY_SERVICE_NBITS
+ 8 * mac_len
+
673 APHY_TAIL_NBITS
) * 1000, 2 * kNdps
);
675 dur
+= APHY_SYMBOL_TIME
* nsyms
;
676 if (wlc
->band
->bandtype
== BRCM_BAND_2G
)
677 dur
+= DOT11_OFDM_SIGNAL_EXTENSION
;
678 } else if (is_ofdm_rate(rate
)) {
679 dur
= APHY_PREAMBLE_TIME
;
680 dur
+= APHY_SIGNAL_TIME
;
681 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
683 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
685 CEIL((APHY_SERVICE_NBITS
+ 8 * mac_len
+ APHY_TAIL_NBITS
),
687 dur
+= APHY_SYMBOL_TIME
* nsyms
;
688 if (wlc
->band
->bandtype
== BRCM_BAND_2G
)
689 dur
+= DOT11_OFDM_SIGNAL_EXTENSION
;
692 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
695 mac_len
= mac_len
* 8 * 2;
696 /* calc ceiling of bits/rate = microseconds of air time */
697 dur
= (mac_len
+ rate
- 1) / rate
;
698 if (preamble_type
& BRCMS_SHORT_PREAMBLE
)
699 dur
+= BPHY_PLCP_SHORT_TIME
;
701 dur
+= BPHY_PLCP_TIME
;
706 static void brcms_c_write_inits(struct brcms_hardware
*wlc_hw
,
707 const struct d11init
*inits
)
709 struct bcma_device
*core
= wlc_hw
->d11core
;
715 brcms_dbg_info(wlc_hw
->d11core
, "wl%d\n", wlc_hw
->unit
);
717 for (i
= 0; inits
[i
].addr
!= cpu_to_le16(0xffff); i
++) {
718 size
= le16_to_cpu(inits
[i
].size
);
719 offset
= le16_to_cpu(inits
[i
].addr
);
720 value
= le32_to_cpu(inits
[i
].value
);
722 bcma_write16(core
, offset
, value
);
724 bcma_write32(core
, offset
, value
);
730 static void brcms_c_write_mhf(struct brcms_hardware
*wlc_hw
, u16
*mhfs
)
734 M_HOST_FLAGS1
, M_HOST_FLAGS2
, M_HOST_FLAGS3
, M_HOST_FLAGS4
,
738 for (idx
= 0; idx
< MHFMAX
; idx
++)
739 brcms_b_write_shm(wlc_hw
, addr
[idx
], mhfs
[idx
]);
742 static void brcms_c_ucode_bsinit(struct brcms_hardware
*wlc_hw
)
744 struct brcms_ucode
*ucode
= &wlc_hw
->wlc
->wl
->ucode
;
746 /* init microcode host flags */
747 brcms_c_write_mhf(wlc_hw
, wlc_hw
->band
->mhfs
);
749 /* do band-specific ucode IHR, SHM, and SCR inits */
750 if (D11REV_IS(wlc_hw
->corerev
, 23)) {
751 if (BRCMS_ISNPHY(wlc_hw
->band
))
752 brcms_c_write_inits(wlc_hw
, ucode
->d11n0bsinitvals16
);
754 brcms_err(wlc_hw
->d11core
,
755 "%s: wl%d: unsupported phy in corerev %d\n",
756 __func__
, wlc_hw
->unit
,
759 if (D11REV_IS(wlc_hw
->corerev
, 24)) {
760 if (BRCMS_ISLCNPHY(wlc_hw
->band
))
761 brcms_c_write_inits(wlc_hw
,
762 ucode
->d11lcn0bsinitvals24
);
764 brcms_err(wlc_hw
->d11core
,
765 "%s: wl%d: unsupported phy in core rev %d\n",
766 __func__
, wlc_hw
->unit
,
769 brcms_err(wlc_hw
->d11core
,
770 "%s: wl%d: unsupported corerev %d\n",
771 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
776 static void brcms_b_core_ioctl(struct brcms_hardware
*wlc_hw
, u32 m
, u32 v
)
778 struct bcma_device
*core
= wlc_hw
->d11core
;
779 u32 ioctl
= bcma_aread32(core
, BCMA_IOCTL
) & ~m
;
781 bcma_awrite32(core
, BCMA_IOCTL
, ioctl
| v
);
784 static void brcms_b_core_phy_clk(struct brcms_hardware
*wlc_hw
, bool clk
)
786 brcms_dbg_info(wlc_hw
->d11core
, "wl%d: clk %d\n", wlc_hw
->unit
, clk
);
788 wlc_hw
->phyclk
= clk
;
790 if (OFF
== clk
) { /* clear gmode bit, put phy into reset */
792 brcms_b_core_ioctl(wlc_hw
, (SICF_PRST
| SICF_FGC
| SICF_GMODE
),
793 (SICF_PRST
| SICF_FGC
));
795 brcms_b_core_ioctl(wlc_hw
, (SICF_PRST
| SICF_FGC
), SICF_PRST
);
798 } else { /* take phy out of reset */
800 brcms_b_core_ioctl(wlc_hw
, (SICF_PRST
| SICF_FGC
), SICF_FGC
);
802 brcms_b_core_ioctl(wlc_hw
, SICF_FGC
, 0);
808 /* low-level band switch utility routine */
809 static void brcms_c_setxband(struct brcms_hardware
*wlc_hw
, uint bandunit
)
811 brcms_dbg_mac80211(wlc_hw
->d11core
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
814 wlc_hw
->band
= wlc_hw
->bandstate
[bandunit
];
818 * until we eliminate need for wlc->band refs in low level code
820 wlc_hw
->wlc
->band
= wlc_hw
->wlc
->bandstate
[bandunit
];
822 /* set gmode core flag */
823 if (wlc_hw
->sbclk
&& !wlc_hw
->noreset
) {
829 brcms_b_core_ioctl(wlc_hw
, SICF_GMODE
, gmode
);
833 /* switch to new band but leave it inactive */
834 static u32
brcms_c_setband_inact(struct brcms_c_info
*wlc
, uint bandunit
)
836 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
840 brcms_dbg_mac80211(wlc_hw
->d11core
, "wl%d\n", wlc_hw
->unit
);
841 macctrl
= bcma_read32(wlc_hw
->d11core
,
842 D11REGOFFS(maccontrol
));
843 WARN_ON((macctrl
& MCTL_EN_MAC
) != 0);
845 /* disable interrupts */
846 macintmask
= brcms_intrsoff(wlc
->wl
);
849 wlc_phy_switch_radio(wlc_hw
->band
->pi
, OFF
);
851 brcms_b_core_phy_clk(wlc_hw
, OFF
);
853 brcms_c_setxband(wlc_hw
, bandunit
);
858 /* process an individual struct tx_status */
860 brcms_c_dotxstatus(struct brcms_c_info
*wlc
, struct tx_status
*txs
)
862 struct sk_buff
*p
= NULL
;
864 struct dma_pub
*dma
= NULL
;
866 struct scb
*scb
= NULL
;
868 int tx_rts
, tx_frame_count
, tx_rts_count
;
869 uint totlen
, supr_status
;
871 struct ieee80211_hdr
*h
;
873 struct ieee80211_tx_info
*tx_info
;
874 struct ieee80211_tx_rate
*txrate
;
878 /* discard intermediate indications for ucode with one legitimate case:
879 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
880 * but the subsequent tx of DATA failed. so it will start rts/cts
881 * from the beginning (resetting the rts transmission count)
883 if (!(txs
->status
& TX_STATUS_AMPDU
)
884 && (txs
->status
& TX_STATUS_INTERMEDIATE
)) {
885 brcms_dbg_tx(wlc
->hw
->d11core
, "INTERMEDIATE but not AMPDU\n");
890 queue
= txs
->frameid
& TXFID_QUEUE_MASK
;
894 dma
= wlc
->hw
->di
[queue
];
896 p
= dma_getnexttxp(wlc
->hw
->di
[queue
], DMA_RANGE_TRANSMITTED
);
900 txh
= (struct d11txh
*) (p
->data
);
901 mcl
= le16_to_cpu(txh
->MacTxControlLow
);
904 if (brcm_msg_level
& BRCM_DL_INFO
) {
905 brcms_err(wlc
->hw
->d11core
, "phyerr 0x%x, rate 0x%x\n",
906 txs
->phyerr
, txh
->MainRates
);
907 brcms_c_print_txdesc(txh
);
909 brcms_c_print_txstatus(txs
);
912 if (txs
->frameid
!= le16_to_cpu(txh
->TxFrameID
))
914 tx_info
= IEEE80211_SKB_CB(p
);
915 h
= (struct ieee80211_hdr
*)((u8
*) (txh
+ 1) + D11_PHY_HDR_LEN
);
917 if (tx_info
->rate_driver_data
[0])
920 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
921 brcms_c_ampdu_dotxstatus(wlc
->ampdu
, scb
, p
, txs
);
926 supr_status
= txs
->status
& TX_STATUS_SUPR_MASK
;
927 if (supr_status
== TX_STATUS_SUPR_BADCH
)
928 brcms_dbg_tx(wlc
->hw
->d11core
,
929 "Pkt tx suppressed, possibly channel %d\n",
930 CHSPEC_CHANNEL(wlc
->default_bss
->chanspec
));
932 tx_rts
= le16_to_cpu(txh
->MacTxControlLow
) & TXC_SENDRTS
;
934 (txs
->status
& TX_STATUS_FRM_RTX_MASK
) >> TX_STATUS_FRM_RTX_SHIFT
;
936 (txs
->status
& TX_STATUS_RTS_RTX_MASK
) >> TX_STATUS_RTS_RTX_SHIFT
;
938 lastframe
= !ieee80211_has_morefrags(h
->frame_control
);
941 brcms_err(wlc
->hw
->d11core
, "Not last frame!\n");
944 * Set information to be consumed by Minstrel ht.
946 * The "fallback limit" is the number of tx attempts a given
947 * MPDU is sent at the "primary" rate. Tx attempts beyond that
948 * limit are sent at the "secondary" rate.
949 * A 'short frame' does not exceed RTS treshold.
951 u16 sfbl
, /* Short Frame Rate Fallback Limit */
952 lfbl
, /* Long Frame Rate Fallback Limit */
955 if (queue
< IEEE80211_NUM_ACS
) {
956 sfbl
= GFIELD(wlc
->wme_retries
[wme_fifo2ac
[queue
]],
958 lfbl
= GFIELD(wlc
->wme_retries
[wme_fifo2ac
[queue
]],
965 txrate
= tx_info
->status
.rates
;
966 if (txrate
[0].flags
& IEEE80211_TX_RC_USE_RTS_CTS
)
971 ieee80211_tx_info_clear_status(tx_info
);
973 if ((tx_frame_count
> fbl
) && (txrate
[1].idx
>= 0)) {
975 * rate selection requested a fallback rate
978 txrate
[0].count
= fbl
;
979 txrate
[1].count
= tx_frame_count
- fbl
;
982 * rate selection did not request fallback rate, or
985 txrate
[0].count
= tx_frame_count
;
987 * rc80211_minstrel.c:minstrel_tx_status() expects
988 * unused rates to be marked with idx = -1
994 /* clear the rest of the rates */
995 for (i
= 2; i
< IEEE80211_TX_MAX_RATES
; i
++) {
1000 if (txs
->status
& TX_STATUS_ACK_RCV
)
1001 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
1008 /* remove PLCP & Broadcom tx descriptor header */
1009 skb_pull(p
, D11_PHY_HDR_LEN
);
1010 skb_pull(p
, D11_TXH_LEN
);
1011 ieee80211_tx_status_irqsafe(wlc
->pub
->ieee_hw
, p
);
1013 brcms_err(wlc
->hw
->d11core
,
1014 "%s: Not last frame => not calling tx_status\n",
1022 brcmu_pkt_buf_free_skb(p
);
1024 if (dma
&& queue
< NFIFO
) {
1025 u16 ac_queue
= brcms_fifo_to_ac(queue
);
1026 if (dma
->txavail
> TX_HEADROOM
&& queue
< TX_BCMC_FIFO
&&
1027 ieee80211_queue_stopped(wlc
->pub
->ieee_hw
, ac_queue
))
1028 ieee80211_wake_queue(wlc
->pub
->ieee_hw
, ac_queue
);
1035 /* process tx completion events in BMAC
1036 * Return true if more tx status need to be processed. false otherwise.
1039 brcms_b_txstatus(struct brcms_hardware
*wlc_hw
, bool bound
, bool *fatal
)
1041 bool morepending
= false;
1042 struct bcma_device
*core
;
1043 struct tx_status txstatus
, *txs
;
1047 * Param 'max_tx_num' indicates max. # tx status to process before
1050 uint max_tx_num
= bound
? TXSBND
: -1;
1052 brcms_dbg_tx(core
, "wl%d\n", wlc_hw
->unit
);
1055 core
= wlc_hw
->d11core
;
1057 s1
= bcma_read32(core
, D11REGOFFS(frmtxstatus
));
1061 if (s1
== 0xffffffff) {
1062 brcms_err(core
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
1066 s2
= bcma_read32(core
, D11REGOFFS(frmtxstatus2
));
1068 txs
->status
= s1
& TXS_STATUS_MASK
;
1069 txs
->frameid
= (s1
& TXS_FID_MASK
) >> TXS_FID_SHIFT
;
1070 txs
->sequence
= s2
& TXS_SEQ_MASK
;
1071 txs
->phyerr
= (s2
& TXS_PTX_MASK
) >> TXS_PTX_SHIFT
;
1072 txs
->lasttxtime
= 0;
1074 *fatal
= brcms_c_dotxstatus(wlc_hw
->wlc
, txs
);
1076 /* !give others some time to run! */
1077 if (++n
>= max_tx_num
)
1079 s1
= bcma_read32(core
, D11REGOFFS(frmtxstatus
));
1085 if (n
>= max_tx_num
)
1091 static void brcms_c_tbtt(struct brcms_c_info
*wlc
)
1093 if (!wlc
->bsscfg
->BSS
)
1095 * DirFrmQ is now valid...defer setting until end
1098 wlc
->qvalid
|= MCMD_DIRFRMQVAL
;
1101 /* set initial host flags value */
1103 brcms_c_mhfdef(struct brcms_c_info
*wlc
, u16
*mhfs
, u16 mhf2_init
)
1105 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
1107 memset(mhfs
, 0, MHFMAX
* sizeof(u16
));
1109 mhfs
[MHF2
] |= mhf2_init
;
1111 /* prohibit use of slowclock on multifunction boards */
1112 if (wlc_hw
->boardflags
& BFL_NOPLLDOWN
)
1113 mhfs
[MHF1
] |= MHF1_FORCEFASTCLK
;
1115 if (BRCMS_ISNPHY(wlc_hw
->band
) && NREV_LT(wlc_hw
->band
->phyrev
, 2)) {
1116 mhfs
[MHF2
] |= MHF2_NPHY40MHZ_WAR
;
1117 mhfs
[MHF1
] |= MHF1_IQSWAP_WAR
;
1122 dmareg(uint direction
, uint fifonum
)
1124 if (direction
== DMA_TX
)
1125 return offsetof(struct d11regs
, fifo64regs
[fifonum
].dmaxmt
);
1126 return offsetof(struct d11regs
, fifo64regs
[fifonum
].dmarcv
);
1129 static bool brcms_b_attach_dmapio(struct brcms_c_info
*wlc
, uint j
, bool wme
)
1134 * ucode host flag 2 needed for pio mode, independent of band and fifo
1137 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
1138 uint unit
= wlc_hw
->unit
;
1140 /* name and offsets for dma_attach */
1141 snprintf(name
, sizeof(name
), "wl%d", unit
);
1143 if (wlc_hw
->di
[0] == NULL
) { /* Init FIFOs */
1144 int dma_attach_err
= 0;
1148 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1149 * RX: RX_FIFO (RX data packets)
1151 wlc_hw
->di
[0] = dma_attach(name
, wlc
,
1152 (wme
? dmareg(DMA_TX
, 0) : 0),
1154 (wme
? NTXD
: 0), NRXD
,
1155 RXBUFSZ
, -1, NRXBUFPOST
,
1156 BRCMS_HWRXOFF
, &brcm_msg_level
);
1157 dma_attach_err
|= (NULL
== wlc_hw
->di
[0]);
1161 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1162 * (legacy) TX_DATA_FIFO (TX data packets)
1165 wlc_hw
->di
[1] = dma_attach(name
, wlc
,
1166 dmareg(DMA_TX
, 1), 0,
1167 NTXD
, 0, 0, -1, 0, 0,
1169 dma_attach_err
|= (NULL
== wlc_hw
->di
[1]);
1173 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1176 wlc_hw
->di
[2] = dma_attach(name
, wlc
,
1177 dmareg(DMA_TX
, 2), 0,
1178 NTXD
, 0, 0, -1, 0, 0,
1180 dma_attach_err
|= (NULL
== wlc_hw
->di
[2]);
1183 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1184 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1186 wlc_hw
->di
[3] = dma_attach(name
, wlc
,
1189 0, 0, &brcm_msg_level
);
1190 dma_attach_err
|= (NULL
== wlc_hw
->di
[3]);
1191 /* Cleaner to leave this as if with AP defined */
1193 if (dma_attach_err
) {
1194 brcms_err(wlc_hw
->d11core
,
1195 "wl%d: wlc_attach: dma_attach failed\n",
1200 /* get pointer to dma engine tx flow control variable */
1201 for (i
= 0; i
< NFIFO
; i
++)
1203 wlc_hw
->txavail
[i
] =
1204 (uint
*) dma_getvar(wlc_hw
->di
[i
],
1208 /* initial ucode host flags */
1209 brcms_c_mhfdef(wlc
, wlc_hw
->band
->mhfs
, pio_mhf2
);
1214 static void brcms_b_detach_dmapio(struct brcms_hardware
*wlc_hw
)
1218 for (j
= 0; j
< NFIFO
; j
++) {
1219 if (wlc_hw
->di
[j
]) {
1220 dma_detach(wlc_hw
->di
[j
]);
1221 wlc_hw
->di
[j
] = NULL
;
1227 * Initialize brcms_c_info default values ...
1228 * may get overrides later in this function
1229 * BMAC_NOTES, move low out and resolve the dangling ones
1231 static void brcms_b_info_init(struct brcms_hardware
*wlc_hw
)
1233 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
1235 /* set default sw macintmask value */
1236 wlc
->defmacintmask
= DEF_MACINTMASK
;
1238 /* various 802.11g modes */
1239 wlc_hw
->shortslot
= false;
1241 wlc_hw
->SFBL
= RETRY_SHORT_FB
;
1242 wlc_hw
->LFBL
= RETRY_LONG_FB
;
1244 /* default mac retry limits */
1245 wlc_hw
->SRL
= RETRY_SHORT_DEF
;
1246 wlc_hw
->LRL
= RETRY_LONG_DEF
;
1247 wlc_hw
->chanspec
= ch20mhz_chspec(1);
1250 static void brcms_b_wait_for_wake(struct brcms_hardware
*wlc_hw
)
1252 /* delay before first read of ucode state */
1255 /* wait until ucode is no longer asleep */
1256 SPINWAIT((brcms_b_read_shm(wlc_hw
, M_UCODE_DBGST
) ==
1257 DBGST_ASLEEP
), wlc_hw
->wlc
->fastpwrup_dly
);
1260 /* control chip clock to save power, enable dynamic clock or force fast clock */
1261 static void brcms_b_clkctl_clk(struct brcms_hardware
*wlc_hw
, enum bcma_clkmode mode
)
1263 if (ai_get_cccaps(wlc_hw
->sih
) & CC_CAP_PMU
) {
1264 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1265 * on backplane, but mac core will still run on ALP(not HT) when
1266 * it enters powersave mode, which means the FCA bit may not be
1267 * set. Should wakeup mac if driver wants it to run on HT.
1271 if (mode
== BCMA_CLKMODE_FAST
) {
1272 bcma_set32(wlc_hw
->d11core
,
1273 D11REGOFFS(clk_ctl_st
),
1279 ((bcma_read32(wlc_hw
->d11core
,
1280 D11REGOFFS(clk_ctl_st
)) &
1282 PMU_MAX_TRANSITION_DLY
);
1283 WARN_ON(!(bcma_read32(wlc_hw
->d11core
,
1284 D11REGOFFS(clk_ctl_st
)) &
1287 if ((ai_get_pmurev(wlc_hw
->sih
) == 0) &&
1288 (bcma_read32(wlc_hw
->d11core
,
1289 D11REGOFFS(clk_ctl_st
)) &
1290 (CCS_FORCEHT
| CCS_HTAREQ
)))
1292 ((bcma_read32(wlc_hw
->d11core
,
1293 offsetof(struct d11regs
,
1296 PMU_MAX_TRANSITION_DLY
);
1297 bcma_mask32(wlc_hw
->d11core
,
1298 D11REGOFFS(clk_ctl_st
),
1302 wlc_hw
->forcefastclk
= (mode
== BCMA_CLKMODE_FAST
);
1305 /* old chips w/o PMU, force HT through cc,
1306 * then use FCA to verify mac is running fast clock
1309 wlc_hw
->forcefastclk
= ai_clkctl_cc(wlc_hw
->sih
, mode
);
1311 /* check fast clock is available (if core is not in reset) */
1312 if (wlc_hw
->forcefastclk
&& wlc_hw
->clk
)
1313 WARN_ON(!(bcma_aread32(wlc_hw
->d11core
, BCMA_IOST
) &
1317 * keep the ucode wake bit on if forcefastclk is on since we
1318 * do not want ucode to put us back to slow clock when it dozes
1319 * for PM mode. Code below matches the wake override bit with
1320 * current forcefastclk state. Only setting bit in wake_override
1321 * instead of waking ucode immediately since old code had this
1322 * behavior. Older code set wlc->forcefastclk but only had the
1323 * wake happen if the wakup_ucode work (protected by an up
1324 * check) was executed just below.
1326 if (wlc_hw
->forcefastclk
)
1327 mboolset(wlc_hw
->wake_override
,
1328 BRCMS_WAKE_OVERRIDE_FORCEFAST
);
1330 mboolclr(wlc_hw
->wake_override
,
1331 BRCMS_WAKE_OVERRIDE_FORCEFAST
);
1335 /* set or clear ucode host flag bits
1336 * it has an optimization for no-change write
1337 * it only writes through shared memory when the core has clock;
1338 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1341 * bands values are: BRCM_BAND_AUTO <--- Current band only
1342 * BRCM_BAND_5G <--- 5G band only
1343 * BRCM_BAND_2G <--- 2G band only
1344 * BRCM_BAND_ALL <--- All bands
1347 brcms_b_mhf(struct brcms_hardware
*wlc_hw
, u8 idx
, u16 mask
, u16 val
,
1351 u16 addr
[MHFMAX
] = {
1352 M_HOST_FLAGS1
, M_HOST_FLAGS2
, M_HOST_FLAGS3
, M_HOST_FLAGS4
,
1355 struct brcms_hw_band
*band
;
1357 if ((val
& ~mask
) || idx
>= MHFMAX
)
1358 return; /* error condition */
1361 /* Current band only or all bands,
1362 * then set the band to current band
1364 case BRCM_BAND_AUTO
:
1366 band
= wlc_hw
->band
;
1369 band
= wlc_hw
->bandstate
[BAND_5G_INDEX
];
1372 band
= wlc_hw
->bandstate
[BAND_2G_INDEX
];
1375 band
= NULL
; /* error condition */
1379 save
= band
->mhfs
[idx
];
1380 band
->mhfs
[idx
] = (band
->mhfs
[idx
] & ~mask
) | val
;
1382 /* optimization: only write through if changed, and
1383 * changed band is the current band
1385 if (wlc_hw
->clk
&& (band
->mhfs
[idx
] != save
)
1386 && (band
== wlc_hw
->band
))
1387 brcms_b_write_shm(wlc_hw
, addr
[idx
],
1388 (u16
) band
->mhfs
[idx
]);
1391 if (bands
== BRCM_BAND_ALL
) {
1392 wlc_hw
->bandstate
[0]->mhfs
[idx
] =
1393 (wlc_hw
->bandstate
[0]->mhfs
[idx
] & ~mask
) | val
;
1394 wlc_hw
->bandstate
[1]->mhfs
[idx
] =
1395 (wlc_hw
->bandstate
[1]->mhfs
[idx
] & ~mask
) | val
;
1399 /* set the maccontrol register to desired reset state and
1400 * initialize the sw cache of the register
1402 static void brcms_c_mctrl_reset(struct brcms_hardware
*wlc_hw
)
1404 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1405 wlc_hw
->maccontrol
= 0;
1406 wlc_hw
->suspended_fifos
= 0;
1407 wlc_hw
->wake_override
= 0;
1408 wlc_hw
->mute_override
= 0;
1409 brcms_b_mctrl(wlc_hw
, ~0, MCTL_IHR_EN
| MCTL_WAKE
);
1413 * write the software state of maccontrol and
1414 * overrides to the maccontrol register
1416 static void brcms_c_mctrl_write(struct brcms_hardware
*wlc_hw
)
1418 u32 maccontrol
= wlc_hw
->maccontrol
;
1420 /* OR in the wake bit if overridden */
1421 if (wlc_hw
->wake_override
)
1422 maccontrol
|= MCTL_WAKE
;
1424 /* set AP and INFRA bits for mute if needed */
1425 if (wlc_hw
->mute_override
) {
1426 maccontrol
&= ~(MCTL_AP
);
1427 maccontrol
|= MCTL_INFRA
;
1430 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(maccontrol
),
1434 /* set or clear maccontrol bits */
1435 void brcms_b_mctrl(struct brcms_hardware
*wlc_hw
, u32 mask
, u32 val
)
1441 return; /* error condition */
1442 maccontrol
= wlc_hw
->maccontrol
;
1443 new_maccontrol
= (maccontrol
& ~mask
) | val
;
1445 /* if the new maccontrol value is the same as the old, nothing to do */
1446 if (new_maccontrol
== maccontrol
)
1449 /* something changed, cache the new value */
1450 wlc_hw
->maccontrol
= new_maccontrol
;
1452 /* write the new values with overrides applied */
1453 brcms_c_mctrl_write(wlc_hw
);
1456 void brcms_c_ucode_wake_override_set(struct brcms_hardware
*wlc_hw
,
1459 if (wlc_hw
->wake_override
|| (wlc_hw
->maccontrol
& MCTL_WAKE
)) {
1460 mboolset(wlc_hw
->wake_override
, override_bit
);
1464 mboolset(wlc_hw
->wake_override
, override_bit
);
1466 brcms_c_mctrl_write(wlc_hw
);
1467 brcms_b_wait_for_wake(wlc_hw
);
1470 void brcms_c_ucode_wake_override_clear(struct brcms_hardware
*wlc_hw
,
1473 mboolclr(wlc_hw
->wake_override
, override_bit
);
1475 if (wlc_hw
->wake_override
|| (wlc_hw
->maccontrol
& MCTL_WAKE
))
1478 brcms_c_mctrl_write(wlc_hw
);
1481 /* When driver needs ucode to stop beaconing, it has to make sure that
1482 * MCTL_AP is clear and MCTL_INFRA is set
1483 * Mode MCTL_AP MCTL_INFRA
1485 * STA 0 1 <--- This will ensure no beacons
1488 static void brcms_c_ucode_mute_override_set(struct brcms_hardware
*wlc_hw
)
1490 wlc_hw
->mute_override
= 1;
1492 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1493 * override, then there is no change to write
1495 if ((wlc_hw
->maccontrol
& (MCTL_AP
| MCTL_INFRA
)) == MCTL_INFRA
)
1498 brcms_c_mctrl_write(wlc_hw
);
1501 /* Clear the override on AP and INFRA bits */
1502 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware
*wlc_hw
)
1504 if (wlc_hw
->mute_override
== 0)
1507 wlc_hw
->mute_override
= 0;
1509 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1510 * override, then there is no change to write
1512 if ((wlc_hw
->maccontrol
& (MCTL_AP
| MCTL_INFRA
)) == MCTL_INFRA
)
1515 brcms_c_mctrl_write(wlc_hw
);
1519 * Write a MAC address to the given match reg offset in the RXE match engine.
1522 brcms_b_set_addrmatch(struct brcms_hardware
*wlc_hw
, int match_reg_offset
,
1525 struct bcma_device
*core
= wlc_hw
->d11core
;
1530 brcms_dbg_rx(core
, "wl%d: brcms_b_set_addrmatch\n", wlc_hw
->unit
);
1532 mac_l
= addr
[0] | (addr
[1] << 8);
1533 mac_m
= addr
[2] | (addr
[3] << 8);
1534 mac_h
= addr
[4] | (addr
[5] << 8);
1536 /* enter the MAC addr into the RXE match registers */
1537 bcma_write16(core
, D11REGOFFS(rcm_ctl
),
1538 RCM_INC_DATA
| match_reg_offset
);
1539 bcma_write16(core
, D11REGOFFS(rcm_mat_data
), mac_l
);
1540 bcma_write16(core
, D11REGOFFS(rcm_mat_data
), mac_m
);
1541 bcma_write16(core
, D11REGOFFS(rcm_mat_data
), mac_h
);
1545 brcms_b_write_template_ram(struct brcms_hardware
*wlc_hw
, int offset
, int len
,
1548 struct bcma_device
*core
= wlc_hw
->d11core
;
1553 brcms_dbg_info(core
, "wl%d\n", wlc_hw
->unit
);
1555 bcma_write32(core
, D11REGOFFS(tplatewrptr
), offset
);
1557 /* if MCTL_BIGEND bit set in mac control register,
1558 * the chip swaps data in fifo, as well as data in
1561 be_bit
= (bcma_read32(core
, D11REGOFFS(maccontrol
)) & MCTL_BIGEND
) != 0;
1564 memcpy(&word
, buf
, sizeof(u32
));
1567 word_be
= cpu_to_be32(word
);
1568 word
= *(u32
*)&word_be
;
1570 word_le
= cpu_to_le32(word
);
1571 word
= *(u32
*)&word_le
;
1574 bcma_write32(core
, D11REGOFFS(tplatewrdata
), word
);
1576 buf
= (u8
*) buf
+ sizeof(u32
);
1581 static void brcms_b_set_cwmin(struct brcms_hardware
*wlc_hw
, u16 newmin
)
1583 wlc_hw
->band
->CWmin
= newmin
;
1585 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objaddr
),
1586 OBJADDR_SCR_SEL
| S_DOT11_CWMIN
);
1587 (void)bcma_read32(wlc_hw
->d11core
, D11REGOFFS(objaddr
));
1588 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objdata
), newmin
);
1591 static void brcms_b_set_cwmax(struct brcms_hardware
*wlc_hw
, u16 newmax
)
1593 wlc_hw
->band
->CWmax
= newmax
;
1595 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objaddr
),
1596 OBJADDR_SCR_SEL
| S_DOT11_CWMAX
);
1597 (void)bcma_read32(wlc_hw
->d11core
, D11REGOFFS(objaddr
));
1598 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objdata
), newmax
);
1601 void brcms_b_bw_set(struct brcms_hardware
*wlc_hw
, u16 bw
)
1605 /* request FAST clock if not on */
1606 fastclk
= wlc_hw
->forcefastclk
;
1608 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
1610 wlc_phy_bw_state_set(wlc_hw
->band
->pi
, bw
);
1612 brcms_b_phy_reset(wlc_hw
);
1613 wlc_phy_init(wlc_hw
->band
->pi
, wlc_phy_chanspec_get(wlc_hw
->band
->pi
));
1615 /* restore the clk */
1617 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_DYNAMIC
);
1620 static void brcms_b_upd_synthpu(struct brcms_hardware
*wlc_hw
)
1623 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
1624 /* update SYNTHPU_DLY */
1626 if (BRCMS_ISLCNPHY(wlc
->band
))
1627 v
= SYNTHPU_DLY_LPPHY_US
;
1628 else if (BRCMS_ISNPHY(wlc
->band
) && (NREV_GE(wlc
->band
->phyrev
, 3)))
1629 v
= SYNTHPU_DLY_NPHY_US
;
1631 v
= SYNTHPU_DLY_BPHY_US
;
1633 brcms_b_write_shm(wlc_hw
, M_SYNTHPU_DLY
, v
);
1636 static void brcms_c_ucode_txant_set(struct brcms_hardware
*wlc_hw
)
1639 u16 phytxant
= wlc_hw
->bmac_phytxant
;
1640 u16 mask
= PHY_TXC_ANT_MASK
;
1642 /* set the Probe Response frame phy control word */
1643 phyctl
= brcms_b_read_shm(wlc_hw
, M_CTXPRS_BLK
+ C_CTX_PCTLWD_POS
);
1644 phyctl
= (phyctl
& ~mask
) | phytxant
;
1645 brcms_b_write_shm(wlc_hw
, M_CTXPRS_BLK
+ C_CTX_PCTLWD_POS
, phyctl
);
1647 /* set the Response (ACK/CTS) frame phy control word */
1648 phyctl
= brcms_b_read_shm(wlc_hw
, M_RSP_PCTLWD
);
1649 phyctl
= (phyctl
& ~mask
) | phytxant
;
1650 brcms_b_write_shm(wlc_hw
, M_RSP_PCTLWD
, phyctl
);
1653 static u16
brcms_b_ofdm_ratetable_offset(struct brcms_hardware
*wlc_hw
,
1658 struct plcp_signal_rate_lookup
{
1662 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1663 const struct plcp_signal_rate_lookup rate_lookup
[] = {
1664 {BRCM_RATE_6M
, 0xB},
1665 {BRCM_RATE_9M
, 0xF},
1666 {BRCM_RATE_12M
, 0xA},
1667 {BRCM_RATE_18M
, 0xE},
1668 {BRCM_RATE_24M
, 0x9},
1669 {BRCM_RATE_36M
, 0xD},
1670 {BRCM_RATE_48M
, 0x8},
1671 {BRCM_RATE_54M
, 0xC}
1674 for (i
= 0; i
< ARRAY_SIZE(rate_lookup
); i
++) {
1675 if (rate
== rate_lookup
[i
].rate
) {
1676 plcp_rate
= rate_lookup
[i
].signal_rate
;
1681 /* Find the SHM pointer to the rate table entry by looking in the
1684 return 2 * brcms_b_read_shm(wlc_hw
, M_RT_DIRMAP_A
+ (plcp_rate
* 2));
1687 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware
*wlc_hw
)
1691 BRCM_RATE_6M
, BRCM_RATE_9M
, BRCM_RATE_12M
, BRCM_RATE_18M
,
1692 BRCM_RATE_24M
, BRCM_RATE_36M
, BRCM_RATE_48M
, BRCM_RATE_54M
1698 if (!BRCMS_PHY_11N_CAP(wlc_hw
->band
))
1701 /* walk the phy rate table and update the entries */
1702 for (i
= 0; i
< ARRAY_SIZE(rates
); i
++) {
1705 entry_ptr
= brcms_b_ofdm_ratetable_offset(wlc_hw
, rate
);
1707 /* read the SHM Rate Table entry OFDM PCTL1 values */
1709 brcms_b_read_shm(wlc_hw
, entry_ptr
+ M_RT_OFDM_PCTL1_POS
);
1711 /* modify the value */
1712 pctl1
&= ~PHY_TXC1_MODE_MASK
;
1713 pctl1
|= (wlc_hw
->hw_stf_ss_opmode
<< PHY_TXC1_MODE_SHIFT
);
1715 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1716 brcms_b_write_shm(wlc_hw
, entry_ptr
+ M_RT_OFDM_PCTL1_POS
,
1721 /* band-specific init */
1722 static void brcms_b_bsinit(struct brcms_c_info
*wlc
, u16 chanspec
)
1724 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
1726 brcms_dbg_mac80211(wlc_hw
->d11core
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
1727 wlc_hw
->band
->bandunit
);
1729 brcms_c_ucode_bsinit(wlc_hw
);
1731 wlc_phy_init(wlc_hw
->band
->pi
, chanspec
);
1733 brcms_c_ucode_txant_set(wlc_hw
);
1736 * cwmin is band-specific, update hardware
1737 * with value for current band
1739 brcms_b_set_cwmin(wlc_hw
, wlc_hw
->band
->CWmin
);
1740 brcms_b_set_cwmax(wlc_hw
, wlc_hw
->band
->CWmax
);
1742 brcms_b_update_slot_timing(wlc_hw
,
1743 wlc_hw
->band
->bandtype
== BRCM_BAND_5G
?
1744 true : wlc_hw
->shortslot
);
1746 /* write phytype and phyvers */
1747 brcms_b_write_shm(wlc_hw
, M_PHYTYPE
, (u16
) wlc_hw
->band
->phytype
);
1748 brcms_b_write_shm(wlc_hw
, M_PHYVER
, (u16
) wlc_hw
->band
->phyrev
);
1751 * initialize the txphyctl1 rate table since
1752 * shmem is shared between bands
1754 brcms_upd_ofdm_pctl1_table(wlc_hw
);
1756 brcms_b_upd_synthpu(wlc_hw
);
1759 /* Perform a soft reset of the PHY PLL */
1760 void brcms_b_core_phypll_reset(struct brcms_hardware
*wlc_hw
)
1762 ai_cc_reg(wlc_hw
->sih
, offsetof(struct chipcregs
, chipcontrol_addr
),
1765 ai_cc_reg(wlc_hw
->sih
, offsetof(struct chipcregs
, chipcontrol_data
),
1768 ai_cc_reg(wlc_hw
->sih
, offsetof(struct chipcregs
, chipcontrol_data
),
1771 ai_cc_reg(wlc_hw
->sih
, offsetof(struct chipcregs
, chipcontrol_data
),
1776 /* light way to turn on phy clock without reset for NPHY only
1777 * refer to brcms_b_core_phy_clk for full version
1779 void brcms_b_phyclk_fgc(struct brcms_hardware
*wlc_hw
, bool clk
)
1781 /* support(necessary for NPHY and HYPHY) only */
1782 if (!BRCMS_ISNPHY(wlc_hw
->band
))
1786 brcms_b_core_ioctl(wlc_hw
, SICF_FGC
, SICF_FGC
);
1788 brcms_b_core_ioctl(wlc_hw
, SICF_FGC
, 0);
1792 void brcms_b_macphyclk_set(struct brcms_hardware
*wlc_hw
, bool clk
)
1795 brcms_b_core_ioctl(wlc_hw
, SICF_MPCLKE
, SICF_MPCLKE
);
1797 brcms_b_core_ioctl(wlc_hw
, SICF_MPCLKE
, 0);
1800 void brcms_b_phy_reset(struct brcms_hardware
*wlc_hw
)
1802 struct brcms_phy_pub
*pih
= wlc_hw
->band
->pi
;
1804 bool phy_in_reset
= false;
1806 brcms_dbg_info(wlc_hw
->d11core
, "wl%d: reset phy\n", wlc_hw
->unit
);
1811 phy_bw_clkbits
= wlc_phy_clk_bwbits(wlc_hw
->band
->pi
);
1813 /* Specific reset sequence required for NPHY rev 3 and 4 */
1814 if (BRCMS_ISNPHY(wlc_hw
->band
) && NREV_GE(wlc_hw
->band
->phyrev
, 3) &&
1815 NREV_LE(wlc_hw
->band
->phyrev
, 4)) {
1816 /* Set the PHY bandwidth */
1817 brcms_b_core_ioctl(wlc_hw
, SICF_BWMASK
, phy_bw_clkbits
);
1821 /* Perform a soft reset of the PHY PLL */
1822 brcms_b_core_phypll_reset(wlc_hw
);
1825 brcms_b_core_ioctl(wlc_hw
, (SICF_PRST
| SICF_PCLKE
),
1826 (SICF_PRST
| SICF_PCLKE
));
1827 phy_in_reset
= true;
1829 brcms_b_core_ioctl(wlc_hw
,
1830 (SICF_PRST
| SICF_PCLKE
| SICF_BWMASK
),
1831 (SICF_PRST
| SICF_PCLKE
| phy_bw_clkbits
));
1835 brcms_b_core_phy_clk(wlc_hw
, ON
);
1838 wlc_phy_anacore(pih
, ON
);
1841 /* switch to and initialize new band */
1842 static void brcms_b_setband(struct brcms_hardware
*wlc_hw
, uint bandunit
,
1844 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
1847 /* Enable the d11 core before accessing it */
1848 if (!bcma_core_is_enabled(wlc_hw
->d11core
)) {
1849 bcma_core_enable(wlc_hw
->d11core
, 0);
1850 brcms_c_mctrl_reset(wlc_hw
);
1853 macintmask
= brcms_c_setband_inact(wlc
, bandunit
);
1858 brcms_b_core_phy_clk(wlc_hw
, ON
);
1860 /* band-specific initializations */
1861 brcms_b_bsinit(wlc
, chanspec
);
1864 * If there are any pending software interrupt bits,
1865 * then replace these with a harmless nonzero value
1866 * so brcms_c_dpc() will re-enable interrupts when done.
1868 if (wlc
->macintstatus
)
1869 wlc
->macintstatus
= MI_DMAINT
;
1871 /* restore macintmask */
1872 brcms_intrsrestore(wlc
->wl
, macintmask
);
1874 /* ucode should still be suspended.. */
1875 WARN_ON((bcma_read32(wlc_hw
->d11core
, D11REGOFFS(maccontrol
)) &
1879 static bool brcms_c_isgoodchip(struct brcms_hardware
*wlc_hw
)
1882 /* reject unsupported corerev */
1883 if (!CONF_HAS(D11CONF
, wlc_hw
->corerev
)) {
1884 wiphy_err(wlc_hw
->wlc
->wiphy
, "unsupported core rev %d\n",
1892 /* Validate some board info parameters */
1893 static bool brcms_c_validboardtype(struct brcms_hardware
*wlc_hw
)
1895 uint boardrev
= wlc_hw
->boardrev
;
1897 /* 4 bits each for board type, major, minor, and tiny version */
1898 uint brt
= (boardrev
& 0xf000) >> 12;
1899 uint b0
= (boardrev
& 0xf00) >> 8;
1900 uint b1
= (boardrev
& 0xf0) >> 4;
1901 uint b2
= boardrev
& 0xf;
1903 /* voards from other vendors are always considered valid */
1904 if (ai_get_boardvendor(wlc_hw
->sih
) != PCI_VENDOR_ID_BROADCOM
)
1907 /* do some boardrev sanity checks when boardvendor is Broadcom */
1911 if (boardrev
<= 0xff)
1914 if ((brt
> 2) || (brt
== 0) || (b0
> 9) || (b0
== 0) || (b1
> 9)
1921 static void brcms_c_get_macaddr(struct brcms_hardware
*wlc_hw
, u8 etheraddr
[ETH_ALEN
])
1923 struct ssb_sprom
*sprom
= &wlc_hw
->d11core
->bus
->sprom
;
1925 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1926 if (!is_zero_ether_addr(sprom
->il0mac
)) {
1927 memcpy(etheraddr
, sprom
->il0mac
, 6);
1931 if (wlc_hw
->_nbands
> 1)
1932 memcpy(etheraddr
, sprom
->et1mac
, 6);
1934 memcpy(etheraddr
, sprom
->il0mac
, 6);
1937 /* power both the pll and external oscillator on/off */
1938 static void brcms_b_xtal(struct brcms_hardware
*wlc_hw
, bool want
)
1940 brcms_dbg_info(wlc_hw
->d11core
, "wl%d: want %d\n", wlc_hw
->unit
, want
);
1943 * dont power down if plldown is false or
1944 * we must poll hw radio disable
1946 if (!want
&& wlc_hw
->pllreq
)
1949 wlc_hw
->sbclk
= want
;
1950 if (!wlc_hw
->sbclk
) {
1951 wlc_hw
->clk
= false;
1952 if (wlc_hw
->band
&& wlc_hw
->band
->pi
)
1953 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
1958 * Return true if radio is disabled, otherwise false.
1959 * hw radio disable signal is an external pin, users activate it asynchronously
1960 * this function could be called when driver is down and w/o clock
1961 * it operates on different registers depending on corerev and boardflag.
1963 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware
*wlc_hw
)
1968 xtal
= wlc_hw
->sbclk
;
1970 brcms_b_xtal(wlc_hw
, ON
);
1972 /* may need to take core out of reset first */
1976 * mac no longer enables phyclk automatically when driver
1977 * accesses phyreg throughput mac. This can be skipped since
1978 * only mac reg is accessed below
1980 if (D11REV_GE(wlc_hw
->corerev
, 18))
1981 flags
|= SICF_PCLKE
;
1984 * TODO: test suspend/resume
1986 * AI chip doesn't restore bar0win2 on
1987 * hibernation/resume, need sw fixup
1990 bcma_core_enable(wlc_hw
->d11core
, flags
);
1991 brcms_c_mctrl_reset(wlc_hw
);
1994 v
= ((bcma_read32(wlc_hw
->d11core
,
1995 D11REGOFFS(phydebug
)) & PDBG_RFD
) != 0);
1997 /* put core back into reset */
1999 bcma_core_disable(wlc_hw
->d11core
, 0);
2002 brcms_b_xtal(wlc_hw
, OFF
);
2007 static bool wlc_dma_rxreset(struct brcms_hardware
*wlc_hw
, uint fifo
)
2009 struct dma_pub
*di
= wlc_hw
->di
[fifo
];
2010 return dma_rxreset(di
);
2014 * ensure fask clock during reset
2016 * reset d11(out of reset)
2017 * reset phy(out of reset)
2018 * clear software macintstatus for fresh new start
2019 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2021 void brcms_b_corereset(struct brcms_hardware
*wlc_hw
, u32 flags
)
2026 if (flags
== BRCMS_USE_COREFLAGS
)
2027 flags
= (wlc_hw
->band
->pi
? wlc_hw
->band
->core_flags
: 0);
2029 brcms_dbg_info(wlc_hw
->d11core
, "wl%d: core reset\n", wlc_hw
->unit
);
2031 /* request FAST clock if not on */
2032 fastclk
= wlc_hw
->forcefastclk
;
2034 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
2036 /* reset the dma engines except first time thru */
2037 if (bcma_core_is_enabled(wlc_hw
->d11core
)) {
2038 for (i
= 0; i
< NFIFO
; i
++)
2039 if ((wlc_hw
->di
[i
]) && (!dma_txreset(wlc_hw
->di
[i
])))
2040 brcms_err(wlc_hw
->d11core
, "wl%d: %s: "
2041 "dma_txreset[%d]: cannot stop dma\n",
2042 wlc_hw
->unit
, __func__
, i
);
2044 if ((wlc_hw
->di
[RX_FIFO
])
2045 && (!wlc_dma_rxreset(wlc_hw
, RX_FIFO
)))
2046 brcms_err(wlc_hw
->d11core
, "wl%d: %s: dma_rxreset"
2047 "[%d]: cannot stop dma\n",
2048 wlc_hw
->unit
, __func__
, RX_FIFO
);
2050 /* if noreset, just stop the psm and return */
2051 if (wlc_hw
->noreset
) {
2052 wlc_hw
->wlc
->macintstatus
= 0; /* skip wl_dpc after down */
2053 brcms_b_mctrl(wlc_hw
, MCTL_PSM_RUN
| MCTL_EN_MAC
, 0);
2058 * mac no longer enables phyclk automatically when driver accesses
2059 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2060 * band->pi is invalid. need to enable PHY CLK
2062 if (D11REV_GE(wlc_hw
->corerev
, 18))
2063 flags
|= SICF_PCLKE
;
2067 * In chips with PMU, the fastclk request goes through d11 core
2068 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2070 * This adds some delay and we can optimize it by also requesting
2071 * fastclk through chipcommon during this period if necessary. But
2072 * that has to work coordinate with other driver like mips/arm since
2073 * they may touch chipcommon as well.
2075 wlc_hw
->clk
= false;
2076 bcma_core_enable(wlc_hw
->d11core
, flags
);
2078 if (wlc_hw
->band
&& wlc_hw
->band
->pi
)
2079 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, true);
2081 brcms_c_mctrl_reset(wlc_hw
);
2083 if (ai_get_cccaps(wlc_hw
->sih
) & CC_CAP_PMU
)
2084 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
2086 brcms_b_phy_reset(wlc_hw
);
2088 /* turn on PHY_PLL */
2089 brcms_b_core_phypll_ctl(wlc_hw
, true);
2091 /* clear sw intstatus */
2092 wlc_hw
->wlc
->macintstatus
= 0;
2094 /* restore the clk setting */
2096 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_DYNAMIC
);
2099 /* txfifo sizes needs to be modified(increased) since the newer cores
2102 static void brcms_b_corerev_fifofixup(struct brcms_hardware
*wlc_hw
)
2104 struct bcma_device
*core
= wlc_hw
->d11core
;
2106 u16 txfifo_startblk
= TXFIFO_START_BLK
, txfifo_endblk
;
2107 u16 txfifo_def
, txfifo_def1
;
2110 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2111 txfifo_startblk
= TXFIFO_START_BLK
;
2113 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2114 for (fifo_nu
= 0; fifo_nu
< NFIFO
; fifo_nu
++) {
2116 txfifo_endblk
= txfifo_startblk
+ wlc_hw
->xmtfifo_sz
[fifo_nu
];
2117 txfifo_def
= (txfifo_startblk
& 0xff) |
2118 (((txfifo_endblk
- 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT
);
2119 txfifo_def1
= ((txfifo_startblk
>> 8) & 0x1) |
2121 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT
);
2123 TXFIFOCMD_RESET_MASK
| (fifo_nu
<< TXFIFOCMD_FIFOSEL_SHIFT
);
2125 bcma_write16(core
, D11REGOFFS(xmtfifocmd
), txfifo_cmd
);
2126 bcma_write16(core
, D11REGOFFS(xmtfifodef
), txfifo_def
);
2127 bcma_write16(core
, D11REGOFFS(xmtfifodef1
), txfifo_def1
);
2129 bcma_write16(core
, D11REGOFFS(xmtfifocmd
), txfifo_cmd
);
2131 txfifo_startblk
+= wlc_hw
->xmtfifo_sz
[fifo_nu
];
2134 * need to propagate to shm location to be in sync since ucode/hw won't
2137 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE0
,
2138 wlc_hw
->xmtfifo_sz
[TX_AC_BE_FIFO
]);
2139 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE1
,
2140 wlc_hw
->xmtfifo_sz
[TX_AC_VI_FIFO
]);
2141 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE2
,
2142 ((wlc_hw
->xmtfifo_sz
[TX_AC_VO_FIFO
] << 8) | wlc_hw
->
2143 xmtfifo_sz
[TX_AC_BK_FIFO
]));
2144 brcms_b_write_shm(wlc_hw
, M_FIFOSIZE3
,
2145 ((wlc_hw
->xmtfifo_sz
[TX_ATIM_FIFO
] << 8) | wlc_hw
->
2146 xmtfifo_sz
[TX_BCMC_FIFO
]));
2149 /* This function is used for changing the tsf frac register
2150 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2151 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2152 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2153 * HTPHY Formula is 2^26/freq(MHz) e.g.
2154 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2155 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2156 * For spuron: 123MHz -> 2^26/123 = 545600.5
2157 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2158 * For spur off: 120MHz -> 2^26/120 = 559240.5
2159 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2162 void brcms_b_switch_macfreq(struct brcms_hardware
*wlc_hw
, u8 spurmode
)
2164 struct bcma_device
*core
= wlc_hw
->d11core
;
2166 if ((ai_get_chip_id(wlc_hw
->sih
) == BCMA_CHIP_ID_BCM43224
) ||
2167 (ai_get_chip_id(wlc_hw
->sih
) == BCMA_CHIP_ID_BCM43225
)) {
2168 if (spurmode
== WL_SPURAVOID_ON2
) { /* 126Mhz */
2169 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_l
), 0x2082);
2170 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_h
), 0x8);
2171 } else if (spurmode
== WL_SPURAVOID_ON1
) { /* 123Mhz */
2172 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_l
), 0x5341);
2173 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_h
), 0x8);
2174 } else { /* 120Mhz */
2175 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_l
), 0x8889);
2176 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_h
), 0x8);
2178 } else if (BRCMS_ISLCNPHY(wlc_hw
->band
)) {
2179 if (spurmode
== WL_SPURAVOID_ON1
) { /* 82Mhz */
2180 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_l
), 0x7CE0);
2181 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_h
), 0xC);
2182 } else { /* 80Mhz */
2183 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_l
), 0xCCCD);
2184 bcma_write16(core
, D11REGOFFS(tsf_clk_frac_h
), 0xC);
2189 /* Initialize GPIOs that are controlled by D11 core */
2190 static void brcms_c_gpio_init(struct brcms_c_info
*wlc
)
2192 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2195 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2196 brcms_b_mctrl(wlc_hw
, MCTL_GPOUT_SEL_MASK
, 0);
2199 * Common GPIO setup:
2200 * G0 = LED 0 = WLAN Activity
2201 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2202 * G2 = LED 2 = WLAN 5 GHz Radio State
2203 * G4 = radio disable input (HI enabled, LO disabled)
2208 /* Allocate GPIOs for mimo antenna diversity feature */
2209 if (wlc_hw
->antsel_type
== ANTSEL_2x3
) {
2210 /* Enable antenna diversity, use 2x3 mode */
2211 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_EN
,
2212 MHF3_ANTSEL_EN
, BRCM_BAND_ALL
);
2213 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_MODE
,
2214 MHF3_ANTSEL_MODE
, BRCM_BAND_ALL
);
2216 /* init superswitch control */
2217 wlc_phy_antsel_init(wlc_hw
->band
->pi
, false);
2219 } else if (wlc_hw
->antsel_type
== ANTSEL_2x4
) {
2220 gm
|= gc
|= (BOARD_GPIO_12
| BOARD_GPIO_13
);
2222 * The board itself is powered by these GPIOs
2223 * (when not sending pattern) so set them high
2225 bcma_set16(wlc_hw
->d11core
, D11REGOFFS(psm_gpio_oe
),
2226 (BOARD_GPIO_12
| BOARD_GPIO_13
));
2227 bcma_set16(wlc_hw
->d11core
, D11REGOFFS(psm_gpio_out
),
2228 (BOARD_GPIO_12
| BOARD_GPIO_13
));
2230 /* Enable antenna diversity, use 2x4 mode */
2231 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_EN
,
2232 MHF3_ANTSEL_EN
, BRCM_BAND_ALL
);
2233 brcms_b_mhf(wlc_hw
, MHF3
, MHF3_ANTSEL_MODE
, 0,
2236 /* Configure the desired clock to be 4Mhz */
2237 brcms_b_write_shm(wlc_hw
, M_ANTSEL_CLKDIV
,
2238 ANTSEL_CLKDIV_4MHZ
);
2242 * gpio 9 controls the PA. ucode is responsible
2243 * for wiggling out and oe
2245 if (wlc_hw
->boardflags
& BFL_PACTRL
)
2246 gm
|= gc
|= BOARD_GPIO_PACTRL
;
2248 /* apply to gpiocontrol register */
2249 bcma_chipco_gpio_control(&wlc_hw
->d11core
->bus
->drv_cc
, gm
, gc
);
2252 static void brcms_ucode_write(struct brcms_hardware
*wlc_hw
,
2253 const __le32 ucode
[], const size_t nbytes
)
2255 struct bcma_device
*core
= wlc_hw
->d11core
;
2259 brcms_dbg_info(wlc_hw
->d11core
, "wl%d\n", wlc_hw
->unit
);
2261 count
= (nbytes
/ sizeof(u32
));
2263 bcma_write32(core
, D11REGOFFS(objaddr
),
2264 OBJADDR_AUTO_INC
| OBJADDR_UCM_SEL
);
2265 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2266 for (i
= 0; i
< count
; i
++)
2267 bcma_write32(core
, D11REGOFFS(objdata
), le32_to_cpu(ucode
[i
]));
2271 static void brcms_ucode_download(struct brcms_hardware
*wlc_hw
)
2273 struct brcms_c_info
*wlc
;
2274 struct brcms_ucode
*ucode
= &wlc_hw
->wlc
->wl
->ucode
;
2278 if (wlc_hw
->ucode_loaded
)
2281 if (D11REV_IS(wlc_hw
->corerev
, 23)) {
2282 if (BRCMS_ISNPHY(wlc_hw
->band
)) {
2283 brcms_ucode_write(wlc_hw
, ucode
->bcm43xx_16_mimo
,
2284 ucode
->bcm43xx_16_mimosz
);
2285 wlc_hw
->ucode_loaded
= true;
2287 brcms_err(wlc_hw
->d11core
,
2288 "%s: wl%d: unsupported phy in corerev %d\n",
2289 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
2290 } else if (D11REV_IS(wlc_hw
->corerev
, 24)) {
2291 if (BRCMS_ISLCNPHY(wlc_hw
->band
)) {
2292 brcms_ucode_write(wlc_hw
, ucode
->bcm43xx_24_lcn
,
2293 ucode
->bcm43xx_24_lcnsz
);
2294 wlc_hw
->ucode_loaded
= true;
2296 brcms_err(wlc_hw
->d11core
,
2297 "%s: wl%d: unsupported phy in corerev %d\n",
2298 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
2303 void brcms_b_txant_set(struct brcms_hardware
*wlc_hw
, u16 phytxant
)
2305 /* update sw state */
2306 wlc_hw
->bmac_phytxant
= phytxant
;
2308 /* push to ucode if up */
2311 brcms_c_ucode_txant_set(wlc_hw
);
2315 u16
brcms_b_get_txant(struct brcms_hardware
*wlc_hw
)
2317 return (u16
) wlc_hw
->wlc
->stf
->txant
;
2320 void brcms_b_antsel_type_set(struct brcms_hardware
*wlc_hw
, u8 antsel_type
)
2322 wlc_hw
->antsel_type
= antsel_type
;
2324 /* Update the antsel type for phy module to use */
2325 wlc_phy_antsel_type_set(wlc_hw
->band
->pi
, antsel_type
);
2328 static void brcms_b_fifoerrors(struct brcms_hardware
*wlc_hw
)
2332 uint intstatus
, idx
;
2333 struct bcma_device
*core
= wlc_hw
->d11core
;
2335 unit
= wlc_hw
->unit
;
2337 for (idx
= 0; idx
< NFIFO
; idx
++) {
2338 /* read intstatus register and ignore any non-error bits */
2341 D11REGOFFS(intctrlregs
[idx
].intstatus
)) &
2346 BCMMSG(wlc_hw
->wlc
->wiphy
, "wl%d: intstatus%d 0x%x\n",
2347 unit
, idx
, intstatus
);
2349 if (intstatus
& I_RO
) {
2350 brcms_err(core
, "wl%d: fifo %d: receive fifo "
2351 "overflow\n", unit
, idx
);
2355 if (intstatus
& I_PC
) {
2356 brcms_err(core
, "wl%d: fifo %d: descriptor error\n",
2361 if (intstatus
& I_PD
) {
2362 brcms_err(core
, "wl%d: fifo %d: data error\n", unit
,
2367 if (intstatus
& I_DE
) {
2368 brcms_err(core
, "wl%d: fifo %d: descriptor protocol "
2369 "error\n", unit
, idx
);
2373 if (intstatus
& I_RU
)
2374 brcms_err(core
, "wl%d: fifo %d: receive descriptor "
2375 "underflow\n", idx
, unit
);
2377 if (intstatus
& I_XU
) {
2378 brcms_err(core
, "wl%d: fifo %d: transmit fifo "
2379 "underflow\n", idx
, unit
);
2384 brcms_fatal_error(wlc_hw
->wlc
->wl
); /* big hammer */
2388 D11REGOFFS(intctrlregs
[idx
].intstatus
),
2393 void brcms_c_intrson(struct brcms_c_info
*wlc
)
2395 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2396 wlc
->macintmask
= wlc
->defmacintmask
;
2397 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(macintmask
), wlc
->macintmask
);
2400 u32
brcms_c_intrsoff(struct brcms_c_info
*wlc
)
2402 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2408 macintmask
= wlc
->macintmask
; /* isr can still happen */
2410 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(macintmask
), 0);
2411 (void)bcma_read32(wlc_hw
->d11core
, D11REGOFFS(macintmask
));
2412 udelay(1); /* ensure int line is no longer driven */
2413 wlc
->macintmask
= 0;
2415 /* return previous macintmask; resolve race between us and our isr */
2416 return wlc
->macintstatus
? 0 : macintmask
;
2419 void brcms_c_intrsrestore(struct brcms_c_info
*wlc
, u32 macintmask
)
2421 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2425 wlc
->macintmask
= macintmask
;
2426 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(macintmask
), wlc
->macintmask
);
2429 /* assumes that the d11 MAC is enabled */
2430 static void brcms_b_tx_fifo_suspend(struct brcms_hardware
*wlc_hw
,
2433 u8 fifo
= 1 << tx_fifo
;
2435 /* Two clients of this code, 11h Quiet period and scanning. */
2437 /* only suspend if not already suspended */
2438 if ((wlc_hw
->suspended_fifos
& fifo
) == fifo
)
2441 /* force the core awake only if not already */
2442 if (wlc_hw
->suspended_fifos
== 0)
2443 brcms_c_ucode_wake_override_set(wlc_hw
,
2444 BRCMS_WAKE_OVERRIDE_TXFIFO
);
2446 wlc_hw
->suspended_fifos
|= fifo
;
2448 if (wlc_hw
->di
[tx_fifo
]) {
2450 * Suspending AMPDU transmissions in the middle can cause
2451 * underflow which may result in mismatch between ucode and
2452 * driver so suspend the mac before suspending the FIFO
2454 if (BRCMS_PHY_11N_CAP(wlc_hw
->band
))
2455 brcms_c_suspend_mac_and_wait(wlc_hw
->wlc
);
2457 dma_txsuspend(wlc_hw
->di
[tx_fifo
]);
2459 if (BRCMS_PHY_11N_CAP(wlc_hw
->band
))
2460 brcms_c_enable_mac(wlc_hw
->wlc
);
2464 static void brcms_b_tx_fifo_resume(struct brcms_hardware
*wlc_hw
,
2467 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2468 * but need to be done here for PIO otherwise the watchdog will catch
2469 * the inconsistency and fire
2471 /* Two clients of this code, 11h Quiet period and scanning. */
2472 if (wlc_hw
->di
[tx_fifo
])
2473 dma_txresume(wlc_hw
->di
[tx_fifo
]);
2475 /* allow core to sleep again */
2476 if (wlc_hw
->suspended_fifos
== 0)
2479 wlc_hw
->suspended_fifos
&= ~(1 << tx_fifo
);
2480 if (wlc_hw
->suspended_fifos
== 0)
2481 brcms_c_ucode_wake_override_clear(wlc_hw
,
2482 BRCMS_WAKE_OVERRIDE_TXFIFO
);
2486 /* precondition: requires the mac core to be enabled */
2487 static void brcms_b_mute(struct brcms_hardware
*wlc_hw
, bool mute_tx
)
2489 static const u8 null_ether_addr
[ETH_ALEN
] = {0, 0, 0, 0, 0, 0};
2492 /* suspend tx fifos */
2493 brcms_b_tx_fifo_suspend(wlc_hw
, TX_DATA_FIFO
);
2494 brcms_b_tx_fifo_suspend(wlc_hw
, TX_CTL_FIFO
);
2495 brcms_b_tx_fifo_suspend(wlc_hw
, TX_AC_BK_FIFO
);
2496 brcms_b_tx_fifo_suspend(wlc_hw
, TX_AC_VI_FIFO
);
2498 /* zero the address match register so we do not send ACKs */
2499 brcms_b_set_addrmatch(wlc_hw
, RCM_MAC_OFFSET
,
2502 /* resume tx fifos */
2503 brcms_b_tx_fifo_resume(wlc_hw
, TX_DATA_FIFO
);
2504 brcms_b_tx_fifo_resume(wlc_hw
, TX_CTL_FIFO
);
2505 brcms_b_tx_fifo_resume(wlc_hw
, TX_AC_BK_FIFO
);
2506 brcms_b_tx_fifo_resume(wlc_hw
, TX_AC_VI_FIFO
);
2508 /* Restore address */
2509 brcms_b_set_addrmatch(wlc_hw
, RCM_MAC_OFFSET
,
2513 wlc_phy_mute_upd(wlc_hw
->band
->pi
, mute_tx
, 0);
2516 brcms_c_ucode_mute_override_set(wlc_hw
);
2518 brcms_c_ucode_mute_override_clear(wlc_hw
);
2522 brcms_c_mute(struct brcms_c_info
*wlc
, bool mute_tx
)
2524 brcms_b_mute(wlc
->hw
, mute_tx
);
2528 * Read and clear macintmask and macintstatus and intstatus registers.
2529 * This routine should be called with interrupts off
2531 * -1 if brcms_deviceremoved(wlc) evaluates to true;
2532 * 0 if the interrupt is not for us, or we are in some special cases;
2533 * device interrupt status bits otherwise.
2535 static inline u32
wlc_intstatus(struct brcms_c_info
*wlc
, bool in_isr
)
2537 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2538 struct bcma_device
*core
= wlc_hw
->d11core
;
2541 /* macintstatus includes a DMA interrupt summary bit */
2542 macintstatus
= bcma_read32(core
, D11REGOFFS(macintstatus
));
2544 BCMMSG(wlc
->wiphy
, "wl%d: macintstatus: 0x%x\n", wlc_hw
->unit
,
2547 /* detect cardbus removed, in power down(suspend) and in reset */
2548 if (brcms_deviceremoved(wlc
))
2551 /* brcms_deviceremoved() succeeds even when the core is still resetting,
2552 * handle that case here.
2554 if (macintstatus
== 0xffffffff)
2557 /* defer unsolicited interrupts */
2558 macintstatus
&= (in_isr
? wlc
->macintmask
: wlc
->defmacintmask
);
2561 if (macintstatus
== 0)
2564 /* interrupts are already turned off for CFE build
2565 * Caution: For CFE Turning off the interrupts again has some undesired
2568 /* turn off the interrupts */
2569 bcma_write32(core
, D11REGOFFS(macintmask
), 0);
2570 (void)bcma_read32(core
, D11REGOFFS(macintmask
));
2571 wlc
->macintmask
= 0;
2573 /* clear device interrupts */
2574 bcma_write32(core
, D11REGOFFS(macintstatus
), macintstatus
);
2576 /* MI_DMAINT is indication of non-zero intstatus */
2577 if (macintstatus
& MI_DMAINT
)
2579 * only fifo interrupt enabled is I_RI in
2580 * RX_FIFO. If MI_DMAINT is set, assume it
2581 * is set and clear the interrupt.
2583 bcma_write32(core
, D11REGOFFS(intctrlregs
[RX_FIFO
].intstatus
),
2586 return macintstatus
;
2589 /* Update wlc->macintstatus and wlc->intstatus[]. */
2590 /* Return true if they are updated successfully. false otherwise */
2591 bool brcms_c_intrsupd(struct brcms_c_info
*wlc
)
2595 /* read and clear macintstatus and intstatus registers */
2596 macintstatus
= wlc_intstatus(wlc
, false);
2598 /* device is removed */
2599 if (macintstatus
== 0xffffffff)
2602 /* update interrupt status in software */
2603 wlc
->macintstatus
|= macintstatus
;
2609 * First-level interrupt processing.
2610 * Return true if this was our interrupt, false otherwise.
2611 * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
2614 bool brcms_c_isr(struct brcms_c_info
*wlc
, bool *wantdpc
)
2616 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2621 if (!wlc_hw
->up
|| !wlc
->macintmask
)
2624 /* read and clear macintstatus and intstatus registers */
2625 macintstatus
= wlc_intstatus(wlc
, true);
2627 if (macintstatus
== 0xffffffff)
2628 brcms_err(wlc_hw
->d11core
,
2629 "DEVICEREMOVED detected in the ISR code path\n");
2631 /* it is not for us */
2632 if (macintstatus
== 0)
2637 /* save interrupt status bits */
2638 wlc
->macintstatus
= macintstatus
;
2644 void brcms_c_suspend_mac_and_wait(struct brcms_c_info
*wlc
)
2646 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2647 struct bcma_device
*core
= wlc_hw
->d11core
;
2650 brcms_dbg_mac80211(core
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
2651 wlc_hw
->band
->bandunit
);
2654 * Track overlapping suspend requests
2656 wlc_hw
->mac_suspend_depth
++;
2657 if (wlc_hw
->mac_suspend_depth
> 1)
2660 /* force the core awake */
2661 brcms_c_ucode_wake_override_set(wlc_hw
, BRCMS_WAKE_OVERRIDE_MACSUSPEND
);
2663 mc
= bcma_read32(core
, D11REGOFFS(maccontrol
));
2665 if (mc
== 0xffffffff) {
2666 brcms_err(core
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
2668 brcms_down(wlc
->wl
);
2671 WARN_ON(mc
& MCTL_PSM_JMP_0
);
2672 WARN_ON(!(mc
& MCTL_PSM_RUN
));
2673 WARN_ON(!(mc
& MCTL_EN_MAC
));
2675 mi
= bcma_read32(core
, D11REGOFFS(macintstatus
));
2676 if (mi
== 0xffffffff) {
2677 brcms_err(core
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
2679 brcms_down(wlc
->wl
);
2682 WARN_ON(mi
& MI_MACSSPNDD
);
2684 brcms_b_mctrl(wlc_hw
, MCTL_EN_MAC
, 0);
2686 SPINWAIT(!(bcma_read32(core
, D11REGOFFS(macintstatus
)) & MI_MACSSPNDD
),
2687 BRCMS_MAX_MAC_SUSPEND
);
2689 if (!(bcma_read32(core
, D11REGOFFS(macintstatus
)) & MI_MACSSPNDD
)) {
2690 brcms_err(core
, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2691 " and MI_MACSSPNDD is still not on.\n",
2692 wlc_hw
->unit
, BRCMS_MAX_MAC_SUSPEND
);
2693 brcms_err(core
, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2694 "psm_brc 0x%04x\n", wlc_hw
->unit
,
2695 bcma_read32(core
, D11REGOFFS(psmdebug
)),
2696 bcma_read32(core
, D11REGOFFS(phydebug
)),
2697 bcma_read16(core
, D11REGOFFS(psm_brc
)));
2700 mc
= bcma_read32(core
, D11REGOFFS(maccontrol
));
2701 if (mc
== 0xffffffff) {
2702 brcms_err(core
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
2704 brcms_down(wlc
->wl
);
2707 WARN_ON(mc
& MCTL_PSM_JMP_0
);
2708 WARN_ON(!(mc
& MCTL_PSM_RUN
));
2709 WARN_ON(mc
& MCTL_EN_MAC
);
2712 void brcms_c_enable_mac(struct brcms_c_info
*wlc
)
2714 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2715 struct bcma_device
*core
= wlc_hw
->d11core
;
2718 brcms_dbg_mac80211(core
, "wl%d: bandunit %d\n", wlc_hw
->unit
,
2719 wlc
->band
->bandunit
);
2722 * Track overlapping suspend requests
2724 wlc_hw
->mac_suspend_depth
--;
2725 if (wlc_hw
->mac_suspend_depth
> 0)
2728 mc
= bcma_read32(core
, D11REGOFFS(maccontrol
));
2729 WARN_ON(mc
& MCTL_PSM_JMP_0
);
2730 WARN_ON(mc
& MCTL_EN_MAC
);
2731 WARN_ON(!(mc
& MCTL_PSM_RUN
));
2733 brcms_b_mctrl(wlc_hw
, MCTL_EN_MAC
, MCTL_EN_MAC
);
2734 bcma_write32(core
, D11REGOFFS(macintstatus
), MI_MACSSPNDD
);
2736 mc
= bcma_read32(core
, D11REGOFFS(maccontrol
));
2737 WARN_ON(mc
& MCTL_PSM_JMP_0
);
2738 WARN_ON(!(mc
& MCTL_EN_MAC
));
2739 WARN_ON(!(mc
& MCTL_PSM_RUN
));
2741 mi
= bcma_read32(core
, D11REGOFFS(macintstatus
));
2742 WARN_ON(mi
& MI_MACSSPNDD
);
2744 brcms_c_ucode_wake_override_clear(wlc_hw
,
2745 BRCMS_WAKE_OVERRIDE_MACSUSPEND
);
2748 void brcms_b_band_stf_ss_set(struct brcms_hardware
*wlc_hw
, u8 stf_mode
)
2750 wlc_hw
->hw_stf_ss_opmode
= stf_mode
;
2753 brcms_upd_ofdm_pctl1_table(wlc_hw
);
2756 static bool brcms_b_validate_chip_access(struct brcms_hardware
*wlc_hw
)
2758 struct bcma_device
*core
= wlc_hw
->d11core
;
2760 struct wiphy
*wiphy
= wlc_hw
->wlc
->wiphy
;
2762 /* Validate dchip register access */
2764 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2765 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2766 w
= bcma_read32(core
, D11REGOFFS(objdata
));
2768 /* Can we write and read back a 32bit register? */
2769 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2770 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2771 bcma_write32(core
, D11REGOFFS(objdata
), (u32
) 0xaa5555aa);
2773 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2774 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2775 val
= bcma_read32(core
, D11REGOFFS(objdata
));
2776 if (val
!= (u32
) 0xaa5555aa) {
2777 wiphy_err(wiphy
, "wl%d: validate_chip_access: SHM = 0x%x, "
2778 "expected 0xaa5555aa\n", wlc_hw
->unit
, val
);
2782 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2783 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2784 bcma_write32(core
, D11REGOFFS(objdata
), (u32
) 0x55aaaa55);
2786 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2787 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2788 val
= bcma_read32(core
, D11REGOFFS(objdata
));
2789 if (val
!= (u32
) 0x55aaaa55) {
2790 wiphy_err(wiphy
, "wl%d: validate_chip_access: SHM = 0x%x, "
2791 "expected 0x55aaaa55\n", wlc_hw
->unit
, val
);
2795 bcma_write32(core
, D11REGOFFS(objaddr
), OBJADDR_SHM_SEL
| 0);
2796 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2797 bcma_write32(core
, D11REGOFFS(objdata
), w
);
2799 /* clear CFPStart */
2800 bcma_write32(core
, D11REGOFFS(tsf_cfpstart
), 0);
2802 w
= bcma_read32(core
, D11REGOFFS(maccontrol
));
2803 if ((w
!= (MCTL_IHR_EN
| MCTL_WAKE
)) &&
2804 (w
!= (MCTL_IHR_EN
| MCTL_GMODE
| MCTL_WAKE
))) {
2805 wiphy_err(wiphy
, "wl%d: validate_chip_access: maccontrol = "
2806 "0x%x, expected 0x%x or 0x%x\n", wlc_hw
->unit
, w
,
2807 (MCTL_IHR_EN
| MCTL_WAKE
),
2808 (MCTL_IHR_EN
| MCTL_GMODE
| MCTL_WAKE
));
2815 #define PHYPLL_WAIT_US 100000
2817 void brcms_b_core_phypll_ctl(struct brcms_hardware
*wlc_hw
, bool on
)
2819 struct bcma_device
*core
= wlc_hw
->d11core
;
2822 brcms_dbg_info(core
, "wl%d\n", wlc_hw
->unit
);
2827 if ((ai_get_chip_id(wlc_hw
->sih
) == BCMA_CHIP_ID_BCM4313
)) {
2828 bcma_set32(core
, D11REGOFFS(clk_ctl_st
),
2830 CCS_ERSRC_REQ_D11PLL
|
2831 CCS_ERSRC_REQ_PHYPLL
);
2832 SPINWAIT((bcma_read32(core
, D11REGOFFS(clk_ctl_st
)) &
2833 CCS_ERSRC_AVAIL_HT
) != CCS_ERSRC_AVAIL_HT
,
2836 tmp
= bcma_read32(core
, D11REGOFFS(clk_ctl_st
));
2837 if ((tmp
& CCS_ERSRC_AVAIL_HT
) != CCS_ERSRC_AVAIL_HT
)
2838 brcms_err(core
, "%s: turn on PHY PLL failed\n",
2841 bcma_set32(core
, D11REGOFFS(clk_ctl_st
),
2842 tmp
| CCS_ERSRC_REQ_D11PLL
|
2843 CCS_ERSRC_REQ_PHYPLL
);
2844 SPINWAIT((bcma_read32(core
, D11REGOFFS(clk_ctl_st
)) &
2845 (CCS_ERSRC_AVAIL_D11PLL
|
2846 CCS_ERSRC_AVAIL_PHYPLL
)) !=
2847 (CCS_ERSRC_AVAIL_D11PLL
|
2848 CCS_ERSRC_AVAIL_PHYPLL
), PHYPLL_WAIT_US
);
2850 tmp
= bcma_read32(core
, D11REGOFFS(clk_ctl_st
));
2852 (CCS_ERSRC_AVAIL_D11PLL
| CCS_ERSRC_AVAIL_PHYPLL
))
2854 (CCS_ERSRC_AVAIL_D11PLL
| CCS_ERSRC_AVAIL_PHYPLL
))
2855 brcms_err(core
, "%s: turn on PHY PLL failed\n",
2860 * Since the PLL may be shared, other cores can still
2861 * be requesting it; so we'll deassert the request but
2862 * not wait for status to comply.
2864 bcma_mask32(core
, D11REGOFFS(clk_ctl_st
),
2865 ~CCS_ERSRC_REQ_PHYPLL
);
2866 (void)bcma_read32(core
, D11REGOFFS(clk_ctl_st
));
2870 static void brcms_c_coredisable(struct brcms_hardware
*wlc_hw
)
2874 brcms_dbg_info(wlc_hw
->d11core
, "wl%d: disable core\n", wlc_hw
->unit
);
2876 dev_gone
= brcms_deviceremoved(wlc_hw
->wlc
);
2881 if (wlc_hw
->noreset
)
2885 wlc_phy_switch_radio(wlc_hw
->band
->pi
, OFF
);
2887 /* turn off analog core */
2888 wlc_phy_anacore(wlc_hw
->band
->pi
, OFF
);
2890 /* turn off PHYPLL to save power */
2891 brcms_b_core_phypll_ctl(wlc_hw
, false);
2893 wlc_hw
->clk
= false;
2894 bcma_core_disable(wlc_hw
->d11core
, 0);
2895 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
2898 static void brcms_c_flushqueues(struct brcms_c_info
*wlc
)
2900 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
2903 /* free any posted tx packets */
2904 for (i
= 0; i
< NFIFO
; i
++) {
2905 if (wlc_hw
->di
[i
]) {
2906 dma_txreclaim(wlc_hw
->di
[i
], DMA_RANGE_ALL
);
2907 if (i
< TX_BCMC_FIFO
)
2908 ieee80211_wake_queue(wlc
->pub
->ieee_hw
,
2909 brcms_fifo_to_ac(i
));
2913 /* free any posted rx packets */
2914 dma_rxreclaim(wlc_hw
->di
[RX_FIFO
]);
2918 brcms_b_read_objmem(struct brcms_hardware
*wlc_hw
, uint offset
, u32 sel
)
2920 struct bcma_device
*core
= wlc_hw
->d11core
;
2921 u16 objoff
= D11REGOFFS(objdata
);
2923 bcma_write32(core
, D11REGOFFS(objaddr
), sel
| (offset
>> 2));
2924 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2928 return bcma_read16(core
, objoff
);
2932 brcms_b_write_objmem(struct brcms_hardware
*wlc_hw
, uint offset
, u16 v
,
2935 struct bcma_device
*core
= wlc_hw
->d11core
;
2936 u16 objoff
= D11REGOFFS(objdata
);
2938 bcma_write32(core
, D11REGOFFS(objaddr
), sel
| (offset
>> 2));
2939 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
2943 bcma_write16(core
, objoff
, v
);
2947 * Read a single u16 from shared memory.
2948 * SHM 'offset' needs to be an even address
2950 u16
brcms_b_read_shm(struct brcms_hardware
*wlc_hw
, uint offset
)
2952 return brcms_b_read_objmem(wlc_hw
, offset
, OBJADDR_SHM_SEL
);
2956 * Write a single u16 to shared memory.
2957 * SHM 'offset' needs to be an even address
2959 void brcms_b_write_shm(struct brcms_hardware
*wlc_hw
, uint offset
, u16 v
)
2961 brcms_b_write_objmem(wlc_hw
, offset
, v
, OBJADDR_SHM_SEL
);
2965 * Copy a buffer to shared memory of specified type .
2966 * SHM 'offset' needs to be an even address and
2967 * Buffer length 'len' must be an even number of bytes
2968 * 'sel' selects the type of memory
2971 brcms_b_copyto_objmem(struct brcms_hardware
*wlc_hw
, uint offset
,
2972 const void *buf
, int len
, u32 sel
)
2975 const u8
*p
= (const u8
*)buf
;
2978 if (len
<= 0 || (offset
& 1) || (len
& 1))
2981 for (i
= 0; i
< len
; i
+= 2) {
2982 v
= p
[i
] | (p
[i
+ 1] << 8);
2983 brcms_b_write_objmem(wlc_hw
, offset
+ i
, v
, sel
);
2988 * Copy a piece of shared memory of specified type to a buffer .
2989 * SHM 'offset' needs to be an even address and
2990 * Buffer length 'len' must be an even number of bytes
2991 * 'sel' selects the type of memory
2994 brcms_b_copyfrom_objmem(struct brcms_hardware
*wlc_hw
, uint offset
, void *buf
,
3001 if (len
<= 0 || (offset
& 1) || (len
& 1))
3004 for (i
= 0; i
< len
; i
+= 2) {
3005 v
= brcms_b_read_objmem(wlc_hw
, offset
+ i
, sel
);
3007 p
[i
+ 1] = (v
>> 8) & 0xFF;
3011 /* Copy a buffer to shared memory.
3012 * SHM 'offset' needs to be an even address and
3013 * Buffer length 'len' must be an even number of bytes
3015 static void brcms_c_copyto_shm(struct brcms_c_info
*wlc
, uint offset
,
3016 const void *buf
, int len
)
3018 brcms_b_copyto_objmem(wlc
->hw
, offset
, buf
, len
, OBJADDR_SHM_SEL
);
3021 static void brcms_b_retrylimit_upd(struct brcms_hardware
*wlc_hw
,
3027 /* write retry limit to SCR, shouldn't need to suspend */
3029 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objaddr
),
3030 OBJADDR_SCR_SEL
| S_DOT11_SRC_LMT
);
3031 (void)bcma_read32(wlc_hw
->d11core
, D11REGOFFS(objaddr
));
3032 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objdata
), wlc_hw
->SRL
);
3033 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objaddr
),
3034 OBJADDR_SCR_SEL
| S_DOT11_LRC_LMT
);
3035 (void)bcma_read32(wlc_hw
->d11core
, D11REGOFFS(objaddr
));
3036 bcma_write32(wlc_hw
->d11core
, D11REGOFFS(objdata
), wlc_hw
->LRL
);
3040 static void brcms_b_pllreq(struct brcms_hardware
*wlc_hw
, bool set
, u32 req_bit
)
3043 if (mboolisset(wlc_hw
->pllreq
, req_bit
))
3046 mboolset(wlc_hw
->pllreq
, req_bit
);
3048 if (mboolisset(wlc_hw
->pllreq
, BRCMS_PLLREQ_FLIP
)) {
3050 brcms_b_xtal(wlc_hw
, ON
);
3053 if (!mboolisset(wlc_hw
->pllreq
, req_bit
))
3056 mboolclr(wlc_hw
->pllreq
, req_bit
);
3058 if (mboolisset(wlc_hw
->pllreq
, BRCMS_PLLREQ_FLIP
)) {
3060 brcms_b_xtal(wlc_hw
, OFF
);
3065 static void brcms_b_antsel_set(struct brcms_hardware
*wlc_hw
, u32 antsel_avail
)
3067 wlc_hw
->antsel_avail
= antsel_avail
;
3071 * conditions under which the PM bit should be set in outgoing frames
3072 * and STAY_AWAKE is meaningful
3074 static bool brcms_c_ps_allowed(struct brcms_c_info
*wlc
)
3076 struct brcms_bss_cfg
*cfg
= wlc
->bsscfg
;
3078 /* disallow PS when one of the following global conditions meets */
3079 if (!wlc
->pub
->associated
)
3082 /* disallow PS when one of these meets when not scanning */
3083 if (wlc
->filter_flags
& FIF_PROMISC_IN_BSS
)
3086 if (cfg
->associated
) {
3088 * disallow PS when one of the following
3089 * bsscfg specific conditions meets
3100 static void brcms_c_statsupd(struct brcms_c_info
*wlc
)
3103 struct macstat macstats
;
3110 /* if driver down, make no sense to update stats */
3115 /* save last rx fifo 0 overflow count */
3116 rxf0ovfl
= wlc
->core
->macstat_snapshot
->rxf0ovfl
;
3118 /* save last tx fifo underflow count */
3119 for (i
= 0; i
< NFIFO
; i
++)
3120 txfunfl
[i
] = wlc
->core
->macstat_snapshot
->txfunfl
[i
];
3123 /* Read mac stats from contiguous shared memory */
3124 brcms_b_copyfrom_objmem(wlc
->hw
, M_UCODE_MACSTAT
, &macstats
,
3125 sizeof(struct macstat
), OBJADDR_SHM_SEL
);
3128 /* check for rx fifo 0 overflow */
3129 delta
= (u16
) (wlc
->core
->macstat_snapshot
->rxf0ovfl
- rxf0ovfl
);
3131 brcms_err(wlc
->hw
->d11core
, "wl%d: %u rx fifo 0 overflows!\n",
3132 wlc
->pub
->unit
, delta
);
3134 /* check for tx fifo underflows */
3135 for (i
= 0; i
< NFIFO
; i
++) {
3137 (u16
) (wlc
->core
->macstat_snapshot
->txfunfl
[i
] -
3140 brcms_err(wlc
->hw
->d11core
,
3141 "wl%d: %u tx fifo %d underflows!\n",
3142 wlc
->pub
->unit
, delta
, i
);
3146 /* merge counters from dma module */
3147 for (i
= 0; i
< NFIFO
; i
++) {
3149 dma_counterreset(wlc
->hw
->di
[i
]);
3153 static void brcms_b_reset(struct brcms_hardware
*wlc_hw
)
3155 /* reset the core */
3156 if (!brcms_deviceremoved(wlc_hw
->wlc
))
3157 brcms_b_corereset(wlc_hw
, BRCMS_USE_COREFLAGS
);
3159 /* purge the dma rings */
3160 brcms_c_flushqueues(wlc_hw
->wlc
);
3163 void brcms_c_reset(struct brcms_c_info
*wlc
)
3165 brcms_dbg_info(wlc
->hw
->d11core
, "wl%d\n", wlc
->pub
->unit
);
3167 /* slurp up hw mac counters before core reset */
3168 brcms_c_statsupd(wlc
);
3170 /* reset our snapshot of macstat counters */
3171 memset((char *)wlc
->core
->macstat_snapshot
, 0,
3172 sizeof(struct macstat
));
3174 brcms_b_reset(wlc
->hw
);
3177 void brcms_c_init_scb(struct scb
*scb
)
3181 memset(scb
, 0, sizeof(struct scb
));
3182 scb
->flags
= SCB_WMECAP
| SCB_HTCAP
;
3183 for (i
= 0; i
< NUMPRIO
; i
++) {
3185 scb
->seqctl
[i
] = 0xFFFF;
3188 scb
->seqctl_nonqos
= 0xFFFF;
3189 scb
->magic
= SCB_MAGIC
;
3194 * download ucode/PCM
3195 * let ucode run to suspended
3196 * download ucode inits
3197 * config other core registers
3200 static void brcms_b_coreinit(struct brcms_c_info
*wlc
)
3202 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
3203 struct bcma_device
*core
= wlc_hw
->d11core
;
3207 bool fifosz_fixup
= false;
3210 struct brcms_ucode
*ucode
= &wlc_hw
->wlc
->wl
->ucode
;
3212 brcms_dbg_info(core
, "wl%d: core init\n", wlc_hw
->unit
);
3215 brcms_b_mctrl(wlc_hw
, ~0, (MCTL_IHR_EN
| MCTL_PSM_JMP_0
| MCTL_WAKE
));
3217 brcms_ucode_download(wlc_hw
);
3219 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3221 fifosz_fixup
= true;
3223 /* let the PSM run to the suspended state, set mode to BSS STA */
3224 bcma_write32(core
, D11REGOFFS(macintstatus
), -1);
3225 brcms_b_mctrl(wlc_hw
, ~0,
3226 (MCTL_IHR_EN
| MCTL_INFRA
| MCTL_PSM_RUN
| MCTL_WAKE
));
3228 /* wait for ucode to self-suspend after auto-init */
3229 SPINWAIT(((bcma_read32(core
, D11REGOFFS(macintstatus
)) &
3230 MI_MACSSPNDD
) == 0), 1000 * 1000);
3231 if ((bcma_read32(core
, D11REGOFFS(macintstatus
)) & MI_MACSSPNDD
) == 0)
3232 brcms_err(core
, "wl%d: wlc_coreinit: ucode did not self-"
3233 "suspend!\n", wlc_hw
->unit
);
3235 brcms_c_gpio_init(wlc
);
3237 sflags
= bcma_aread32(core
, BCMA_IOST
);
3239 if (D11REV_IS(wlc_hw
->corerev
, 23)) {
3240 if (BRCMS_ISNPHY(wlc_hw
->band
))
3241 brcms_c_write_inits(wlc_hw
, ucode
->d11n0initvals16
);
3243 brcms_err(core
, "%s: wl%d: unsupported phy in corerev"
3244 " %d\n", __func__
, wlc_hw
->unit
,
3246 } else if (D11REV_IS(wlc_hw
->corerev
, 24)) {
3247 if (BRCMS_ISLCNPHY(wlc_hw
->band
))
3248 brcms_c_write_inits(wlc_hw
, ucode
->d11lcn0initvals24
);
3250 brcms_err(core
, "%s: wl%d: unsupported phy in corerev"
3251 " %d\n", __func__
, wlc_hw
->unit
,
3254 brcms_err(core
, "%s: wl%d: unsupported corerev %d\n",
3255 __func__
, wlc_hw
->unit
, wlc_hw
->corerev
);
3258 /* For old ucode, txfifo sizes needs to be modified(increased) */
3260 brcms_b_corerev_fifofixup(wlc_hw
);
3262 /* check txfifo allocations match between ucode and driver */
3263 buf
[TX_AC_BE_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE0
);
3264 if (buf
[TX_AC_BE_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_BE_FIFO
]) {
3268 buf
[TX_AC_VI_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE1
);
3269 if (buf
[TX_AC_VI_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_VI_FIFO
]) {
3273 buf
[TX_AC_BK_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE2
);
3274 buf
[TX_AC_VO_FIFO
] = (buf
[TX_AC_BK_FIFO
] >> 8) & 0xff;
3275 buf
[TX_AC_BK_FIFO
] &= 0xff;
3276 if (buf
[TX_AC_BK_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_BK_FIFO
]) {
3280 if (buf
[TX_AC_VO_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_AC_VO_FIFO
]) {
3284 buf
[TX_BCMC_FIFO
] = brcms_b_read_shm(wlc_hw
, M_FIFOSIZE3
);
3285 buf
[TX_ATIM_FIFO
] = (buf
[TX_BCMC_FIFO
] >> 8) & 0xff;
3286 buf
[TX_BCMC_FIFO
] &= 0xff;
3287 if (buf
[TX_BCMC_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_BCMC_FIFO
]) {
3291 if (buf
[TX_ATIM_FIFO
] != wlc_hw
->xmtfifo_sz
[TX_ATIM_FIFO
]) {
3296 brcms_err(core
, "wlc_coreinit: txfifo mismatch: ucode size %d"
3297 " driver size %d index %d\n", buf
[i
],
3298 wlc_hw
->xmtfifo_sz
[i
], i
);
3300 /* make sure we can still talk to the mac */
3301 WARN_ON(bcma_read32(core
, D11REGOFFS(maccontrol
)) == 0xffffffff);
3303 /* band-specific inits done by wlc_bsinit() */
3305 /* Set up frame burst size and antenna swap threshold init values */
3306 brcms_b_write_shm(wlc_hw
, M_MBURST_SIZE
, MAXTXFRAMEBURST
);
3307 brcms_b_write_shm(wlc_hw
, M_MAX_ANTCNT
, ANTCNT
);
3309 /* enable one rx interrupt per received frame */
3310 bcma_write32(core
, D11REGOFFS(intrcvlazy
[0]), (1 << IRL_FC_SHIFT
));
3312 /* set the station mode (BSS STA) */
3313 brcms_b_mctrl(wlc_hw
,
3314 (MCTL_INFRA
| MCTL_DISCARD_PMQ
| MCTL_AP
),
3315 (MCTL_INFRA
| MCTL_DISCARD_PMQ
));
3317 /* set up Beacon interval */
3318 bcnint_us
= 0x8000 << 10;
3319 bcma_write32(core
, D11REGOFFS(tsf_cfprep
),
3320 (bcnint_us
<< CFPREP_CBI_SHIFT
));
3321 bcma_write32(core
, D11REGOFFS(tsf_cfpstart
), bcnint_us
);
3322 bcma_write32(core
, D11REGOFFS(macintstatus
), MI_GP1
);
3324 /* write interrupt mask */
3325 bcma_write32(core
, D11REGOFFS(intctrlregs
[RX_FIFO
].intmask
),
3328 /* allow the MAC to control the PHY clock (dynamic on/off) */
3329 brcms_b_macphyclk_set(wlc_hw
, ON
);
3331 /* program dynamic clock control fast powerup delay register */
3332 wlc
->fastpwrup_dly
= ai_clkctl_fast_pwrup_delay(wlc_hw
->sih
);
3333 bcma_write16(core
, D11REGOFFS(scc_fastpwrup_dly
), wlc
->fastpwrup_dly
);
3335 /* tell the ucode the corerev */
3336 brcms_b_write_shm(wlc_hw
, M_MACHW_VER
, (u16
) wlc_hw
->corerev
);
3338 /* tell the ucode MAC capabilities */
3339 brcms_b_write_shm(wlc_hw
, M_MACHW_CAP_L
,
3340 (u16
) (wlc_hw
->machwcap
& 0xffff));
3341 brcms_b_write_shm(wlc_hw
, M_MACHW_CAP_H
,
3343 machwcap
>> 16) & 0xffff));
3345 /* write retry limits to SCR, this done after PSM init */
3346 bcma_write32(core
, D11REGOFFS(objaddr
),
3347 OBJADDR_SCR_SEL
| S_DOT11_SRC_LMT
);
3348 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
3349 bcma_write32(core
, D11REGOFFS(objdata
), wlc_hw
->SRL
);
3350 bcma_write32(core
, D11REGOFFS(objaddr
),
3351 OBJADDR_SCR_SEL
| S_DOT11_LRC_LMT
);
3352 (void)bcma_read32(core
, D11REGOFFS(objaddr
));
3353 bcma_write32(core
, D11REGOFFS(objdata
), wlc_hw
->LRL
);
3355 /* write rate fallback retry limits */
3356 brcms_b_write_shm(wlc_hw
, M_SFRMTXCNTFBRTHSD
, wlc_hw
->SFBL
);
3357 brcms_b_write_shm(wlc_hw
, M_LFRMTXCNTFBRTHSD
, wlc_hw
->LFBL
);
3359 bcma_mask16(core
, D11REGOFFS(ifs_ctl
), 0x0FFF);
3360 bcma_write16(core
, D11REGOFFS(ifs_aifsn
), EDCF_AIFSN_MIN
);
3362 /* init the tx dma engines */
3363 for (i
= 0; i
< NFIFO
; i
++) {
3365 dma_txinit(wlc_hw
->di
[i
]);
3368 /* init the rx dma engine(s) and post receive buffers */
3369 dma_rxinit(wlc_hw
->di
[RX_FIFO
]);
3370 dma_rxfill(wlc_hw
->di
[RX_FIFO
]);
3374 static brcms_b_init(struct brcms_hardware
*wlc_hw
, u16 chanspec
) {
3377 struct brcms_c_info
*wlc
= wlc_hw
->wlc
;
3379 /* request FAST clock if not on */
3380 fastclk
= wlc_hw
->forcefastclk
;
3382 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
3384 /* disable interrupts */
3385 macintmask
= brcms_intrsoff(wlc
->wl
);
3387 /* set up the specified band and chanspec */
3388 brcms_c_setxband(wlc_hw
, chspec_bandunit(chanspec
));
3389 wlc_phy_chanspec_radio_set(wlc_hw
->band
->pi
, chanspec
);
3391 /* do one-time phy inits and calibration */
3392 wlc_phy_cal_init(wlc_hw
->band
->pi
);
3394 /* core-specific initialization */
3395 brcms_b_coreinit(wlc
);
3397 /* band-specific inits */
3398 brcms_b_bsinit(wlc
, chanspec
);
3400 /* restore macintmask */
3401 brcms_intrsrestore(wlc
->wl
, macintmask
);
3403 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3404 * is suspended and brcms_c_enable_mac() will clear this override bit.
3406 mboolset(wlc_hw
->wake_override
, BRCMS_WAKE_OVERRIDE_MACSUSPEND
);
3409 * initialize mac_suspend_depth to 1 to match ucode
3410 * initial suspended state
3412 wlc_hw
->mac_suspend_depth
= 1;
3414 /* restore the clk */
3416 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_DYNAMIC
);
3419 static void brcms_c_set_phy_chanspec(struct brcms_c_info
*wlc
,
3422 /* Save our copy of the chanspec */
3423 wlc
->chanspec
= chanspec
;
3425 /* Set the chanspec and power limits for this locale */
3426 brcms_c_channel_set_chanspec(wlc
->cmi
, chanspec
, BRCMS_TXPWR_MAX
);
3428 if (wlc
->stf
->ss_algosel_auto
)
3429 brcms_c_stf_ss_algo_channel_get(wlc
, &wlc
->stf
->ss_algo_channel
,
3432 brcms_c_stf_ss_update(wlc
, wlc
->band
);
3436 brcms_default_rateset(struct brcms_c_info
*wlc
, struct brcms_c_rateset
*rs
)
3438 brcms_c_rateset_default(rs
, NULL
, wlc
->band
->phytype
,
3439 wlc
->band
->bandtype
, false, BRCMS_RATE_MASK_FULL
,
3440 (bool) (wlc
->pub
->_n_enab
& SUPPORT_11N
),
3441 brcms_chspec_bw(wlc
->default_bss
->chanspec
),
3442 wlc
->stf
->txstreams
);
3445 /* derive wlc->band->basic_rate[] table from 'rateset' */
3446 static void brcms_c_rate_lookup_init(struct brcms_c_info
*wlc
,
3447 struct brcms_c_rateset
*rateset
)
3453 u8
*br
= wlc
->band
->basic_rate
;
3456 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3457 memset(br
, 0, BRCM_MAXRATE
+ 1);
3459 /* For each basic rate in the rates list, make an entry in the
3460 * best basic lookup.
3462 for (i
= 0; i
< rateset
->count
; i
++) {
3463 /* only make an entry for a basic rate */
3464 if (!(rateset
->rates
[i
] & BRCMS_RATE_FLAG
))
3467 /* mask off basic bit */
3468 rate
= (rateset
->rates
[i
] & BRCMS_RATE_MASK
);
3470 if (rate
> BRCM_MAXRATE
) {
3471 brcms_err(wlc
->hw
->d11core
, "brcms_c_rate_lookup_init: "
3472 "invalid rate 0x%X in rate set\n",
3480 /* The rate lookup table now has non-zero entries for each
3481 * basic rate, equal to the basic rate: br[basicN] = basicN
3483 * To look up the best basic rate corresponding to any
3484 * particular rate, code can use the basic_rate table
3487 * basic_rate = wlc->band->basic_rate[tx_rate]
3489 * Make sure there is a best basic rate entry for
3490 * every rate by walking up the table from low rates
3491 * to high, filling in holes in the lookup table
3494 for (i
= 0; i
< wlc
->band
->hw_rateset
.count
; i
++) {
3495 rate
= wlc
->band
->hw_rateset
.rates
[i
];
3497 if (br
[rate
] != 0) {
3498 /* This rate is a basic rate.
3499 * Keep track of the best basic rate so far by
3502 if (is_ofdm_rate(rate
))
3510 /* This rate is not a basic rate so figure out the
3511 * best basic rate less than this rate and fill in
3512 * the hole in the table
3515 br
[rate
] = is_ofdm_rate(rate
) ? ofdm_basic
: cck_basic
;
3520 if (is_ofdm_rate(rate
)) {
3522 * In 11g and 11a, the OFDM mandatory rates
3523 * are 6, 12, and 24 Mbps
3525 if (rate
>= BRCM_RATE_24M
)
3526 mandatory
= BRCM_RATE_24M
;
3527 else if (rate
>= BRCM_RATE_12M
)
3528 mandatory
= BRCM_RATE_12M
;
3530 mandatory
= BRCM_RATE_6M
;
3532 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3536 br
[rate
] = mandatory
;
3540 static void brcms_c_bandinit_ordered(struct brcms_c_info
*wlc
,
3543 struct brcms_c_rateset default_rateset
;
3545 uint i
, band_order
[2];
3548 * We might have been bandlocked during down and the chip
3549 * power-cycled (hibernate). Figure out the right band to park on
3551 if (wlc
->bandlocked
|| wlc
->pub
->_nbands
== 1) {
3552 /* updated in brcms_c_bandlock() */
3553 parkband
= wlc
->band
->bandunit
;
3554 band_order
[0] = band_order
[1] = parkband
;
3556 /* park on the band of the specified chanspec */
3557 parkband
= chspec_bandunit(chanspec
);
3559 /* order so that parkband initialize last */
3560 band_order
[0] = parkband
^ 1;
3561 band_order
[1] = parkband
;
3564 /* make each band operational, software state init */
3565 for (i
= 0; i
< wlc
->pub
->_nbands
; i
++) {
3566 uint j
= band_order
[i
];
3568 wlc
->band
= wlc
->bandstate
[j
];
3570 brcms_default_rateset(wlc
, &default_rateset
);
3572 /* fill in hw_rate */
3573 brcms_c_rateset_filter(&default_rateset
, &wlc
->band
->hw_rateset
,
3574 false, BRCMS_RATES_CCK_OFDM
, BRCMS_RATE_MASK
,
3575 (bool) (wlc
->pub
->_n_enab
& SUPPORT_11N
));
3577 /* init basic rate lookup */
3578 brcms_c_rate_lookup_init(wlc
, &default_rateset
);
3581 /* sync up phy/radio chanspec */
3582 brcms_c_set_phy_chanspec(wlc
, chanspec
);
3586 * Set or clear filtering related maccontrol bits based on
3587 * specified filter flags
3589 void brcms_c_mac_promisc(struct brcms_c_info
*wlc
, uint filter_flags
)
3591 u32 promisc_bits
= 0;
3593 wlc
->filter_flags
= filter_flags
;
3595 if (filter_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
))
3596 promisc_bits
|= MCTL_PROMISC
;
3598 if (filter_flags
& FIF_BCN_PRBRESP_PROMISC
)
3599 promisc_bits
|= MCTL_BCNS_PROMISC
;
3601 if (filter_flags
& FIF_FCSFAIL
)
3602 promisc_bits
|= MCTL_KEEPBADFCS
;
3604 if (filter_flags
& (FIF_CONTROL
| FIF_PSPOLL
))
3605 promisc_bits
|= MCTL_KEEPCONTROL
;
3607 brcms_b_mctrl(wlc
->hw
,
3608 MCTL_PROMISC
| MCTL_BCNS_PROMISC
|
3609 MCTL_KEEPCONTROL
| MCTL_KEEPBADFCS
,
3614 * ucode, hwmac update
3615 * Channel dependent updates for ucode and hw
3617 static void brcms_c_ucode_mac_upd(struct brcms_c_info
*wlc
)
3619 /* enable or disable any active IBSSs depending on whether or not
3620 * we are on the home channel
3622 if (wlc
->home_chanspec
== wlc_phy_chanspec_get(wlc
->band
->pi
)) {
3623 if (wlc
->pub
->associated
) {
3625 * BMAC_NOTE: This is something that should be fixed
3626 * in ucode inits. I think that the ucode inits set
3627 * up the bcn templates and shm values with a bogus
3628 * beacon. This should not be done in the inits. If
3629 * ucode needs to set up a beacon for testing, the
3630 * test routines should write it down, not expect the
3631 * inits to populate a bogus beacon.
3633 if (BRCMS_PHY_11N_CAP(wlc
->band
))
3634 brcms_b_write_shm(wlc
->hw
,
3635 M_BCN_TXTSF_OFFSET
, 0);
3638 /* disable an active IBSS if we are not on the home channel */
3642 static void brcms_c_write_rate_shm(struct brcms_c_info
*wlc
, u8 rate
,
3646 u8 basic_phy_rate
, basic_index
;
3647 u16 dir_table
, basic_table
;
3650 /* Shared memory address for the table we are reading */
3651 dir_table
= is_ofdm_rate(basic_rate
) ? M_RT_DIRMAP_A
: M_RT_DIRMAP_B
;
3653 /* Shared memory address for the table we are writing */
3654 basic_table
= is_ofdm_rate(rate
) ? M_RT_BBRSMAP_A
: M_RT_BBRSMAP_B
;
3657 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3658 * the index into the rate table.
3660 phy_rate
= rate_info
[rate
] & BRCMS_RATE_MASK
;
3661 basic_phy_rate
= rate_info
[basic_rate
] & BRCMS_RATE_MASK
;
3662 index
= phy_rate
& 0xf;
3663 basic_index
= basic_phy_rate
& 0xf;
3665 /* Find the SHM pointer to the ACK rate entry by looking in the
3668 basic_ptr
= brcms_b_read_shm(wlc
->hw
, (dir_table
+ basic_index
* 2));
3670 /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3671 * to the correct basic rate for the given incoming rate
3673 brcms_b_write_shm(wlc
->hw
, (basic_table
+ index
* 2), basic_ptr
);
3676 static const struct brcms_c_rateset
*
3677 brcms_c_rateset_get_hwrs(struct brcms_c_info
*wlc
)
3679 const struct brcms_c_rateset
*rs_dflt
;
3681 if (BRCMS_PHY_11N_CAP(wlc
->band
)) {
3682 if (wlc
->band
->bandtype
== BRCM_BAND_5G
)
3683 rs_dflt
= &ofdm_mimo_rates
;
3685 rs_dflt
= &cck_ofdm_mimo_rates
;
3686 } else if (wlc
->band
->gmode
)
3687 rs_dflt
= &cck_ofdm_rates
;
3689 rs_dflt
= &cck_rates
;
3694 static void brcms_c_set_ratetable(struct brcms_c_info
*wlc
)
3696 const struct brcms_c_rateset
*rs_dflt
;
3697 struct brcms_c_rateset rs
;
3698 u8 rate
, basic_rate
;
3701 rs_dflt
= brcms_c_rateset_get_hwrs(wlc
);
3703 brcms_c_rateset_copy(rs_dflt
, &rs
);
3704 brcms_c_rateset_mcs_upd(&rs
, wlc
->stf
->txstreams
);
3706 /* walk the phy rate table and update SHM basic rate lookup table */
3707 for (i
= 0; i
< rs
.count
; i
++) {
3708 rate
= rs
.rates
[i
] & BRCMS_RATE_MASK
;
3710 /* for a given rate brcms_basic_rate returns the rate at
3711 * which a response ACK/CTS should be sent.
3713 basic_rate
= brcms_basic_rate(wlc
, rate
);
3714 if (basic_rate
== 0)
3715 /* This should only happen if we are using a
3716 * restricted rateset.
3718 basic_rate
= rs
.rates
[0] & BRCMS_RATE_MASK
;
3720 brcms_c_write_rate_shm(wlc
, rate
, basic_rate
);
3724 /* band-specific init */
3725 static void brcms_c_bsinit(struct brcms_c_info
*wlc
)
3727 brcms_dbg_info(wlc
->hw
->d11core
, "wl%d: bandunit %d\n",
3728 wlc
->pub
->unit
, wlc
->band
->bandunit
);
3730 /* write ucode ACK/CTS rate table */
3731 brcms_c_set_ratetable(wlc
);
3733 /* update some band specific mac configuration */
3734 brcms_c_ucode_mac_upd(wlc
);
3736 /* init antenna selection */
3737 brcms_c_antsel_init(wlc
->asi
);
3741 /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3743 brcms_c_duty_cycle_set(struct brcms_c_info
*wlc
, int duty_cycle
, bool isOFDM
,
3746 int idle_busy_ratio_x_16
= 0;
3748 isOFDM
? M_TX_IDLE_BUSY_RATIO_X_16_OFDM
:
3749 M_TX_IDLE_BUSY_RATIO_X_16_CCK
;
3750 if (duty_cycle
> 100 || duty_cycle
< 0) {
3751 brcms_err(wlc
->hw
->d11core
,
3752 "wl%d: duty cycle value off limit\n",
3757 idle_busy_ratio_x_16
= (100 - duty_cycle
) * 16 / duty_cycle
;
3758 /* Only write to shared memory when wl is up */
3760 brcms_b_write_shm(wlc
->hw
, offset
, (u16
) idle_busy_ratio_x_16
);
3763 wlc
->tx_duty_cycle_ofdm
= (u16
) duty_cycle
;
3765 wlc
->tx_duty_cycle_cck
= (u16
) duty_cycle
;
3770 /* push sw hps and wake state through hardware */
3771 static void brcms_c_set_ps_ctrl(struct brcms_c_info
*wlc
)
3777 hps
= brcms_c_ps_allowed(wlc
);
3779 brcms_dbg_mac80211(wlc
->hw
->d11core
, "wl%d: hps %d\n", wlc
->pub
->unit
,
3782 v1
= bcma_read32(wlc
->hw
->d11core
, D11REGOFFS(maccontrol
));
3787 brcms_b_mctrl(wlc
->hw
, MCTL_WAKE
| MCTL_HPS
, v2
);
3789 awake_before
= ((v1
& MCTL_WAKE
) || ((v1
& MCTL_HPS
) == 0));
3792 brcms_b_wait_for_wake(wlc
->hw
);
3796 * Write this BSS config's MAC address to core.
3797 * Updates RXE match engine.
3799 static int brcms_c_set_mac(struct brcms_bss_cfg
*bsscfg
)
3802 struct brcms_c_info
*wlc
= bsscfg
->wlc
;
3804 /* enter the MAC addr into the RXE match registers */
3805 brcms_c_set_addrmatch(wlc
, RCM_MAC_OFFSET
, bsscfg
->cur_etheraddr
);
3807 brcms_c_ampdu_macaddr_upd(wlc
);
3812 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3813 * Updates RXE match engine.
3815 static void brcms_c_set_bssid(struct brcms_bss_cfg
*bsscfg
)
3817 /* we need to update BSSID in RXE match registers */
3818 brcms_c_set_addrmatch(bsscfg
->wlc
, RCM_BSSID_OFFSET
, bsscfg
->BSSID
);
3821 static void brcms_b_set_shortslot(struct brcms_hardware
*wlc_hw
, bool shortslot
)
3823 wlc_hw
->shortslot
= shortslot
;
3825 if (wlc_hw
->band
->bandtype
== BRCM_BAND_2G
&& wlc_hw
->up
) {
3826 brcms_c_suspend_mac_and_wait(wlc_hw
->wlc
);
3827 brcms_b_update_slot_timing(wlc_hw
, shortslot
);
3828 brcms_c_enable_mac(wlc_hw
->wlc
);
3833 * Suspend the the MAC and update the slot timing
3834 * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3836 static void brcms_c_switch_shortslot(struct brcms_c_info
*wlc
, bool shortslot
)
3838 /* use the override if it is set */
3839 if (wlc
->shortslot_override
!= BRCMS_SHORTSLOT_AUTO
)
3840 shortslot
= (wlc
->shortslot_override
== BRCMS_SHORTSLOT_ON
);
3842 if (wlc
->shortslot
== shortslot
)
3845 wlc
->shortslot
= shortslot
;
3847 brcms_b_set_shortslot(wlc
->hw
, shortslot
);
3850 static void brcms_c_set_home_chanspec(struct brcms_c_info
*wlc
, u16 chanspec
)
3852 if (wlc
->home_chanspec
!= chanspec
) {
3853 wlc
->home_chanspec
= chanspec
;
3855 if (wlc
->bsscfg
->associated
)
3856 wlc
->bsscfg
->current_bss
->chanspec
= chanspec
;
3861 brcms_b_set_chanspec(struct brcms_hardware
*wlc_hw
, u16 chanspec
,
3862 bool mute_tx
, struct txpwr_limits
*txpwr
)
3866 brcms_dbg_mac80211(wlc_hw
->d11core
, "wl%d: 0x%x\n", wlc_hw
->unit
,
3869 wlc_hw
->chanspec
= chanspec
;
3871 /* Switch bands if necessary */
3872 if (wlc_hw
->_nbands
> 1) {
3873 bandunit
= chspec_bandunit(chanspec
);
3874 if (wlc_hw
->band
->bandunit
!= bandunit
) {
3875 /* brcms_b_setband disables other bandunit,
3876 * use light band switch if not up yet
3879 wlc_phy_chanspec_radio_set(wlc_hw
->
3880 bandstate
[bandunit
]->
3882 brcms_b_setband(wlc_hw
, bandunit
, chanspec
);
3884 brcms_c_setxband(wlc_hw
, bandunit
);
3889 wlc_phy_initcal_enable(wlc_hw
->band
->pi
, !mute_tx
);
3893 wlc_phy_txpower_limit_set(wlc_hw
->band
->pi
, txpwr
,
3895 wlc_phy_chanspec_radio_set(wlc_hw
->band
->pi
, chanspec
);
3897 wlc_phy_chanspec_set(wlc_hw
->band
->pi
, chanspec
);
3898 wlc_phy_txpower_limit_set(wlc_hw
->band
->pi
, txpwr
, chanspec
);
3900 /* Update muting of the channel */
3901 brcms_b_mute(wlc_hw
, mute_tx
);
3905 /* switch to and initialize new band */
3906 static void brcms_c_setband(struct brcms_c_info
*wlc
,
3909 wlc
->band
= wlc
->bandstate
[bandunit
];
3914 /* wait for at least one beacon before entering sleeping state */
3915 brcms_c_set_ps_ctrl(wlc
);
3917 /* band-specific initializations */
3918 brcms_c_bsinit(wlc
);
3921 static void brcms_c_set_chanspec(struct brcms_c_info
*wlc
, u16 chanspec
)
3924 bool switchband
= false;
3925 u16 old_chanspec
= wlc
->chanspec
;
3927 if (!brcms_c_valid_chanspec_db(wlc
->cmi
, chanspec
)) {
3928 brcms_err(wlc
->hw
->d11core
, "wl%d: %s: Bad channel %d\n",
3929 wlc
->pub
->unit
, __func__
, CHSPEC_CHANNEL(chanspec
));
3933 /* Switch bands if necessary */
3934 if (wlc
->pub
->_nbands
> 1) {
3935 bandunit
= chspec_bandunit(chanspec
);
3936 if (wlc
->band
->bandunit
!= bandunit
|| wlc
->bandinit_pending
) {
3938 if (wlc
->bandlocked
) {
3939 brcms_err(wlc
->hw
->d11core
,
3940 "wl%d: %s: chspec %d band is locked!\n",
3941 wlc
->pub
->unit
, __func__
,
3942 CHSPEC_CHANNEL(chanspec
));
3946 * should the setband call come after the
3947 * brcms_b_chanspec() ? if the setband updates
3948 * (brcms_c_bsinit) use low level calls to inspect and
3949 * set state, the state inspected may be from the wrong
3950 * band, or the following brcms_b_set_chanspec() may
3953 brcms_c_setband(wlc
, bandunit
);
3957 /* sync up phy/radio chanspec */
3958 brcms_c_set_phy_chanspec(wlc
, chanspec
);
3960 /* init antenna selection */
3961 if (brcms_chspec_bw(old_chanspec
) != brcms_chspec_bw(chanspec
)) {
3962 brcms_c_antsel_init(wlc
->asi
);
3964 /* Fix the hardware rateset based on bw.
3965 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3967 brcms_c_rateset_bw_mcs_filter(&wlc
->band
->hw_rateset
,
3968 wlc
->band
->mimo_cap_40
? brcms_chspec_bw(chanspec
) : 0);
3971 /* update some mac configuration since chanspec changed */
3972 brcms_c_ucode_mac_upd(wlc
);
3976 * This function changes the phytxctl for beacon based on current
3977 * beacon ratespec AND txant setting as per this table:
3978 * ratespec CCK ant = wlc->stf->txant
3981 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info
*wlc
,
3985 u16 phytxant
= wlc
->stf
->phytxant
;
3986 u16 mask
= PHY_TXC_ANT_MASK
;
3988 /* for non-siso rates or default setting, use the available chains */
3989 if (BRCMS_PHY_11N_CAP(wlc
->band
))
3990 phytxant
= brcms_c_stf_phytxchain_sel(wlc
, bcn_rspec
);
3992 phyctl
= brcms_b_read_shm(wlc
->hw
, M_BCN_PCTLWD
);
3993 phyctl
= (phyctl
& ~mask
) | phytxant
;
3994 brcms_b_write_shm(wlc
->hw
, M_BCN_PCTLWD
, phyctl
);
3998 * centralized protection config change function to simplify debugging, no
3999 * consistency checking this should be called only on changes to avoid overhead
4000 * in periodic function
4002 void brcms_c_protection_upd(struct brcms_c_info
*wlc
, uint idx
, int val
)
4005 * Cannot use brcms_dbg_* here because this function is called
4006 * before wlc is sufficiently initialized.
4008 BCMMSG(wlc
->wiphy
, "idx %d, val %d\n", idx
, val
);
4011 case BRCMS_PROT_G_SPEC
:
4012 wlc
->protection
->_g
= (bool) val
;
4014 case BRCMS_PROT_G_OVR
:
4015 wlc
->protection
->g_override
= (s8
) val
;
4017 case BRCMS_PROT_G_USER
:
4018 wlc
->protection
->gmode_user
= (u8
) val
;
4020 case BRCMS_PROT_OVERLAP
:
4021 wlc
->protection
->overlap
= (s8
) val
;
4023 case BRCMS_PROT_N_USER
:
4024 wlc
->protection
->nmode_user
= (s8
) val
;
4026 case BRCMS_PROT_N_CFG
:
4027 wlc
->protection
->n_cfg
= (s8
) val
;
4029 case BRCMS_PROT_N_CFG_OVR
:
4030 wlc
->protection
->n_cfg_override
= (s8
) val
;
4032 case BRCMS_PROT_N_NONGF
:
4033 wlc
->protection
->nongf
= (bool) val
;
4035 case BRCMS_PROT_N_NONGF_OVR
:
4036 wlc
->protection
->nongf_override
= (s8
) val
;
4038 case BRCMS_PROT_N_PAM_OVR
:
4039 wlc
->protection
->n_pam_override
= (s8
) val
;
4041 case BRCMS_PROT_N_OBSS
:
4042 wlc
->protection
->n_obss
= (bool) val
;
4051 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info
*wlc
, int val
)
4054 brcms_c_update_beacon(wlc
);
4055 brcms_c_update_probe_resp(wlc
, true);
4059 static void brcms_c_ht_update_ldpc(struct brcms_c_info
*wlc
, s8 val
)
4061 wlc
->stf
->ldpc
= val
;
4064 brcms_c_update_beacon(wlc
);
4065 brcms_c_update_probe_resp(wlc
, true);
4066 wlc_phy_ldpc_override_set(wlc
->band
->pi
, (val
? true : false));
4070 void brcms_c_wme_setparams(struct brcms_c_info
*wlc
, u16 aci
,
4071 const struct ieee80211_tx_queue_params
*params
,
4075 struct shm_acparams acp_shm
;
4078 /* Only apply params if the core is out of reset and has clocks */
4080 brcms_err(wlc
->hw
->d11core
, "wl%d: %s : no-clock\n",
4081 wlc
->pub
->unit
, __func__
);
4085 memset((char *)&acp_shm
, 0, sizeof(struct shm_acparams
));
4086 /* fill in shm ac params struct */
4087 acp_shm
.txop
= params
->txop
;
4088 /* convert from units of 32us to us for ucode */
4089 wlc
->edcf_txop
[aci
& 0x3] = acp_shm
.txop
=
4090 EDCF_TXOP2USEC(acp_shm
.txop
);
4091 acp_shm
.aifs
= (params
->aifs
& EDCF_AIFSN_MASK
);
4093 if (aci
== IEEE80211_AC_VI
&& acp_shm
.txop
== 0
4094 && acp_shm
.aifs
< EDCF_AIFSN_MAX
)
4097 if (acp_shm
.aifs
< EDCF_AIFSN_MIN
4098 || acp_shm
.aifs
> EDCF_AIFSN_MAX
) {
4099 brcms_err(wlc
->hw
->d11core
, "wl%d: edcf_setparams: bad "
4100 "aifs %d\n", wlc
->pub
->unit
, acp_shm
.aifs
);
4102 acp_shm
.cwmin
= params
->cw_min
;
4103 acp_shm
.cwmax
= params
->cw_max
;
4104 acp_shm
.cwcur
= acp_shm
.cwmin
;
4106 bcma_read16(wlc
->hw
->d11core
, D11REGOFFS(tsf_random
)) &
4108 acp_shm
.reggap
= acp_shm
.bslots
+ acp_shm
.aifs
;
4109 /* Indicate the new params to the ucode */
4110 acp_shm
.status
= brcms_b_read_shm(wlc
->hw
, (M_EDCF_QINFO
+
4113 M_EDCF_STATUS_OFF
));
4114 acp_shm
.status
|= WME_STATUS_NEWAC
;
4116 /* Fill in shm acparam table */
4117 shm_entry
= (u16
*) &acp_shm
;
4118 for (i
= 0; i
< (int)sizeof(struct shm_acparams
); i
+= 2)
4119 brcms_b_write_shm(wlc
->hw
,
4121 wme_ac2fifo
[aci
] * M_EDCF_QLEN
+ i
,
4126 brcms_c_suspend_mac_and_wait(wlc
);
4127 brcms_c_enable_mac(wlc
);
4131 static void brcms_c_edcf_setparams(struct brcms_c_info
*wlc
, bool suspend
)
4135 struct ieee80211_tx_queue_params txq_pars
;
4136 static const struct edcf_acparam default_edcf_acparams
[] = {
4137 {EDCF_AC_BE_ACI_STA
, EDCF_AC_BE_ECW_STA
, EDCF_AC_BE_TXOP_STA
},
4138 {EDCF_AC_BK_ACI_STA
, EDCF_AC_BK_ECW_STA
, EDCF_AC_BK_TXOP_STA
},
4139 {EDCF_AC_VI_ACI_STA
, EDCF_AC_VI_ECW_STA
, EDCF_AC_VI_TXOP_STA
},
4140 {EDCF_AC_VO_ACI_STA
, EDCF_AC_VO_ECW_STA
, EDCF_AC_VO_TXOP_STA
}
4141 }; /* ucode needs these parameters during its initialization */
4142 const struct edcf_acparam
*edcf_acp
= &default_edcf_acparams
[0];
4144 for (i_ac
= 0; i_ac
< IEEE80211_NUM_ACS
; i_ac
++, edcf_acp
++) {
4145 /* find out which ac this set of params applies to */
4146 aci
= (edcf_acp
->ACI
& EDCF_ACI_MASK
) >> EDCF_ACI_SHIFT
;
4148 /* fill in shm ac params struct */
4149 txq_pars
.txop
= edcf_acp
->TXOP
;
4150 txq_pars
.aifs
= edcf_acp
->ACI
;
4152 /* CWmin = 2^(ECWmin) - 1 */
4153 txq_pars
.cw_min
= EDCF_ECW2CW(edcf_acp
->ECW
& EDCF_ECWMIN_MASK
);
4154 /* CWmax = 2^(ECWmax) - 1 */
4155 txq_pars
.cw_max
= EDCF_ECW2CW((edcf_acp
->ECW
& EDCF_ECWMAX_MASK
)
4156 >> EDCF_ECWMAX_SHIFT
);
4157 brcms_c_wme_setparams(wlc
, aci
, &txq_pars
, suspend
);
4161 brcms_c_suspend_mac_and_wait(wlc
);
4162 brcms_c_enable_mac(wlc
);
4166 static void brcms_c_radio_monitor_start(struct brcms_c_info
*wlc
)
4168 /* Don't start the timer if HWRADIO feature is disabled */
4169 if (wlc
->radio_monitor
)
4172 wlc
->radio_monitor
= true;
4173 brcms_b_pllreq(wlc
->hw
, true, BRCMS_PLLREQ_RADIO_MON
);
4174 brcms_add_timer(wlc
->radio_timer
, TIMER_INTERVAL_RADIOCHK
, true);
4177 static bool brcms_c_radio_monitor_stop(struct brcms_c_info
*wlc
)
4179 if (!wlc
->radio_monitor
)
4182 wlc
->radio_monitor
= false;
4183 brcms_b_pllreq(wlc
->hw
, false, BRCMS_PLLREQ_RADIO_MON
);
4184 return brcms_del_timer(wlc
->radio_timer
);
4187 /* read hwdisable state and propagate to wlc flag */
4188 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info
*wlc
)
4190 if (wlc
->pub
->hw_off
)
4193 if (brcms_b_radio_read_hwdisabled(wlc
->hw
))
4194 mboolset(wlc
->pub
->radio_disabled
, WL_RADIO_HW_DISABLE
);
4196 mboolclr(wlc
->pub
->radio_disabled
, WL_RADIO_HW_DISABLE
);
4199 /* update hwradio status and return it */
4200 bool brcms_c_check_radio_disabled(struct brcms_c_info
*wlc
)
4202 brcms_c_radio_hwdisable_upd(wlc
);
4204 return mboolisset(wlc
->pub
->radio_disabled
, WL_RADIO_HW_DISABLE
) ?
4208 /* periodical query hw radio button while driver is "down" */
4209 static void brcms_c_radio_timer(void *arg
)
4211 struct brcms_c_info
*wlc
= (struct brcms_c_info
*) arg
;
4213 if (brcms_deviceremoved(wlc
)) {
4214 brcms_err(wlc
->hw
->d11core
, "wl%d: %s: dead chip\n",
4215 wlc
->pub
->unit
, __func__
);
4216 brcms_down(wlc
->wl
);
4220 brcms_c_radio_hwdisable_upd(wlc
);
4223 /* common low-level watchdog code */
4224 static void brcms_b_watchdog(struct brcms_c_info
*wlc
)
4226 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
4231 /* increment second count */
4234 /* Check for FIFO error interrupts */
4235 brcms_b_fifoerrors(wlc_hw
);
4237 /* make sure RX dma has buffers */
4238 dma_rxfill(wlc
->hw
->di
[RX_FIFO
]);
4240 wlc_phy_watchdog(wlc_hw
->band
->pi
);
4243 /* common watchdog code */
4244 static void brcms_c_watchdog(struct brcms_c_info
*wlc
)
4246 brcms_dbg_info(wlc
->hw
->d11core
, "wl%d\n", wlc
->pub
->unit
);
4251 if (brcms_deviceremoved(wlc
)) {
4252 brcms_err(wlc
->hw
->d11core
, "wl%d: %s: dead chip\n",
4253 wlc
->pub
->unit
, __func__
);
4254 brcms_down(wlc
->wl
);
4258 /* increment second count */
4261 brcms_c_radio_hwdisable_upd(wlc
);
4262 /* if radio is disable, driver may be down, quit here */
4263 if (wlc
->pub
->radio_disabled
)
4266 brcms_b_watchdog(wlc
);
4269 * occasionally sample mac stat counters to
4270 * detect 16-bit counter wrap
4272 if ((wlc
->pub
->now
% SW_TIMER_MAC_STAT_UPD
) == 0)
4273 brcms_c_statsupd(wlc
);
4275 if (BRCMS_ISNPHY(wlc
->band
) &&
4276 ((wlc
->pub
->now
- wlc
->tempsense_lasttime
) >=
4277 BRCMS_TEMPSENSE_PERIOD
)) {
4278 wlc
->tempsense_lasttime
= wlc
->pub
->now
;
4279 brcms_c_tempsense_upd(wlc
);
4283 static void brcms_c_watchdog_by_timer(void *arg
)
4285 struct brcms_c_info
*wlc
= (struct brcms_c_info
*) arg
;
4287 brcms_c_watchdog(wlc
);
4290 static bool brcms_c_timers_init(struct brcms_c_info
*wlc
, int unit
)
4292 wlc
->wdtimer
= brcms_init_timer(wlc
->wl
, brcms_c_watchdog_by_timer
,
4294 if (!wlc
->wdtimer
) {
4295 wiphy_err(wlc
->wiphy
, "wl%d: wl_init_timer for wdtimer "
4300 wlc
->radio_timer
= brcms_init_timer(wlc
->wl
, brcms_c_radio_timer
,
4302 if (!wlc
->radio_timer
) {
4303 wiphy_err(wlc
->wiphy
, "wl%d: wl_init_timer for radio_timer "
4315 * Initialize brcms_c_info default values ...
4316 * may get overrides later in this function
4318 static void brcms_c_info_init(struct brcms_c_info
*wlc
, int unit
)
4322 /* Save our copy of the chanspec */
4323 wlc
->chanspec
= ch20mhz_chspec(1);
4325 /* various 802.11g modes */
4326 wlc
->shortslot
= false;
4327 wlc
->shortslot_override
= BRCMS_SHORTSLOT_AUTO
;
4329 brcms_c_protection_upd(wlc
, BRCMS_PROT_G_OVR
, BRCMS_PROTECTION_AUTO
);
4330 brcms_c_protection_upd(wlc
, BRCMS_PROT_G_SPEC
, false);
4332 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_CFG_OVR
,
4333 BRCMS_PROTECTION_AUTO
);
4334 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_CFG
, BRCMS_N_PROTECTION_OFF
);
4335 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_NONGF_OVR
,
4336 BRCMS_PROTECTION_AUTO
);
4337 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_NONGF
, false);
4338 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_PAM_OVR
, AUTO
);
4340 brcms_c_protection_upd(wlc
, BRCMS_PROT_OVERLAP
,
4341 BRCMS_PROTECTION_CTL_OVERLAP
);
4343 /* 802.11g draft 4.0 NonERP elt advertisement */
4344 wlc
->include_legacy_erp
= true;
4346 wlc
->stf
->ant_rx_ovr
= ANT_RX_DIV_DEF
;
4347 wlc
->stf
->txant
= ANT_TX_DEF
;
4349 wlc
->prb_resp_timeout
= BRCMS_PRB_RESP_TIMEOUT
;
4351 wlc
->usr_fragthresh
= DOT11_DEFAULT_FRAG_LEN
;
4352 for (i
= 0; i
< NFIFO
; i
++)
4353 wlc
->fragthresh
[i
] = DOT11_DEFAULT_FRAG_LEN
;
4354 wlc
->RTSThresh
= DOT11_DEFAULT_RTS_LEN
;
4356 /* default rate fallback retry limits */
4357 wlc
->SFBL
= RETRY_SHORT_FB
;
4358 wlc
->LFBL
= RETRY_LONG_FB
;
4360 /* default mac retry limits */
4361 wlc
->SRL
= RETRY_SHORT_DEF
;
4362 wlc
->LRL
= RETRY_LONG_DEF
;
4364 /* WME QoS mode is Auto by default */
4365 wlc
->pub
->_ampdu
= AMPDU_AGG_HOST
;
4366 wlc
->pub
->bcmerror
= 0;
4369 static uint
brcms_c_attach_module(struct brcms_c_info
*wlc
)
4373 unit
= wlc
->pub
->unit
;
4375 wlc
->asi
= brcms_c_antsel_attach(wlc
);
4376 if (wlc
->asi
== NULL
) {
4377 wiphy_err(wlc
->wiphy
, "wl%d: attach: antsel_attach "
4383 wlc
->ampdu
= brcms_c_ampdu_attach(wlc
);
4384 if (wlc
->ampdu
== NULL
) {
4385 wiphy_err(wlc
->wiphy
, "wl%d: attach: ampdu_attach "
4391 if ((brcms_c_stf_attach(wlc
) != 0)) {
4392 wiphy_err(wlc
->wiphy
, "wl%d: attach: stf_attach "
4401 struct brcms_pub
*brcms_c_pub(struct brcms_c_info
*wlc
)
4407 * run backplane attach, init nvram
4409 * initialize software state for each core and band
4410 * put the whole chip in reset(driver down state), no clock
4412 static int brcms_b_attach(struct brcms_c_info
*wlc
, struct bcma_device
*core
,
4413 uint unit
, bool piomode
)
4415 struct brcms_hardware
*wlc_hw
;
4419 struct shared_phy_params sha_params
;
4420 struct wiphy
*wiphy
= wlc
->wiphy
;
4421 struct pci_dev
*pcidev
= core
->bus
->host_pci
;
4422 struct ssb_sprom
*sprom
= &core
->bus
->sprom
;
4424 if (core
->bus
->hosttype
== BCMA_HOSTTYPE_PCI
)
4425 brcms_dbg_info(core
, "wl%d: vendor 0x%x device 0x%x\n", unit
,
4429 brcms_dbg_info(core
, "wl%d: vendor 0x%x device 0x%x\n", unit
,
4430 core
->bus
->boardinfo
.vendor
,
4431 core
->bus
->boardinfo
.type
);
4437 wlc_hw
->unit
= unit
;
4438 wlc_hw
->band
= wlc_hw
->bandstate
[0];
4439 wlc_hw
->_piomode
= piomode
;
4441 /* populate struct brcms_hardware with default values */
4442 brcms_b_info_init(wlc_hw
);
4445 * Do the hardware portion of the attach. Also initialize software
4446 * state that depends on the particular hardware we are running.
4448 wlc_hw
->sih
= ai_attach(core
->bus
);
4449 if (wlc_hw
->sih
== NULL
) {
4450 wiphy_err(wiphy
, "wl%d: brcms_b_attach: si_attach failed\n",
4456 /* verify again the device is supported */
4457 if (!brcms_c_chipmatch(core
)) {
4458 wiphy_err(wiphy
, "wl%d: brcms_b_attach: Unsupported device\n",
4464 if (core
->bus
->hosttype
== BCMA_HOSTTYPE_PCI
) {
4465 wlc_hw
->vendorid
= pcidev
->vendor
;
4466 wlc_hw
->deviceid
= pcidev
->device
;
4468 wlc_hw
->vendorid
= core
->bus
->boardinfo
.vendor
;
4469 wlc_hw
->deviceid
= core
->bus
->boardinfo
.type
;
4472 wlc_hw
->d11core
= core
;
4473 wlc_hw
->corerev
= core
->id
.rev
;
4475 /* validate chip, chiprev and corerev */
4476 if (!brcms_c_isgoodchip(wlc_hw
)) {
4481 /* initialize power control registers */
4482 ai_clkctl_init(wlc_hw
->sih
);
4484 /* request fastclock and force fastclock for the rest of attach
4485 * bring the d11 core out of reset.
4486 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4487 * is still false; But it will be called again inside wlc_corereset,
4488 * after d11 is out of reset.
4490 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
4491 brcms_b_corereset(wlc_hw
, BRCMS_USE_COREFLAGS
);
4493 if (!brcms_b_validate_chip_access(wlc_hw
)) {
4494 wiphy_err(wiphy
, "wl%d: brcms_b_attach: validate_chip_access "
4500 /* get the board rev, used just below */
4501 j
= sprom
->board_rev
;
4502 /* promote srom boardrev of 0xFF to 1 */
4503 if (j
== BOARDREV_PROMOTABLE
)
4504 j
= BOARDREV_PROMOTED
;
4505 wlc_hw
->boardrev
= (u16
) j
;
4506 if (!brcms_c_validboardtype(wlc_hw
)) {
4507 wiphy_err(wiphy
, "wl%d: brcms_b_attach: Unsupported Broadcom "
4508 "board type (0x%x)" " or revision level (0x%x)\n",
4509 unit
, ai_get_boardtype(wlc_hw
->sih
),
4514 wlc_hw
->sromrev
= sprom
->revision
;
4515 wlc_hw
->boardflags
= sprom
->boardflags_lo
+ (sprom
->boardflags_hi
<< 16);
4516 wlc_hw
->boardflags2
= sprom
->boardflags2_lo
+ (sprom
->boardflags2_hi
<< 16);
4518 if (wlc_hw
->boardflags
& BFL_NOPLLDOWN
)
4519 brcms_b_pllreq(wlc_hw
, true, BRCMS_PLLREQ_SHARED
);
4521 /* check device id(srom, nvram etc.) to set bands */
4522 if (wlc_hw
->deviceid
== BCM43224_D11N_ID
||
4523 wlc_hw
->deviceid
== BCM43224_D11N_ID_VEN1
)
4524 /* Dualband boards */
4525 wlc_hw
->_nbands
= 2;
4527 wlc_hw
->_nbands
= 1;
4529 if ((ai_get_chip_id(wlc_hw
->sih
) == BCMA_CHIP_ID_BCM43225
))
4530 wlc_hw
->_nbands
= 1;
4532 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4533 * unconditionally does the init of these values
4535 wlc
->vendorid
= wlc_hw
->vendorid
;
4536 wlc
->deviceid
= wlc_hw
->deviceid
;
4537 wlc
->pub
->sih
= wlc_hw
->sih
;
4538 wlc
->pub
->corerev
= wlc_hw
->corerev
;
4539 wlc
->pub
->sromrev
= wlc_hw
->sromrev
;
4540 wlc
->pub
->boardrev
= wlc_hw
->boardrev
;
4541 wlc
->pub
->boardflags
= wlc_hw
->boardflags
;
4542 wlc
->pub
->boardflags2
= wlc_hw
->boardflags2
;
4543 wlc
->pub
->_nbands
= wlc_hw
->_nbands
;
4545 wlc_hw
->physhim
= wlc_phy_shim_attach(wlc_hw
, wlc
->wl
, wlc
);
4547 if (wlc_hw
->physhim
== NULL
) {
4548 wiphy_err(wiphy
, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4554 /* pass all the parameters to wlc_phy_shared_attach in one struct */
4555 sha_params
.sih
= wlc_hw
->sih
;
4556 sha_params
.physhim
= wlc_hw
->physhim
;
4557 sha_params
.unit
= unit
;
4558 sha_params
.corerev
= wlc_hw
->corerev
;
4559 sha_params
.vid
= wlc_hw
->vendorid
;
4560 sha_params
.did
= wlc_hw
->deviceid
;
4561 sha_params
.chip
= ai_get_chip_id(wlc_hw
->sih
);
4562 sha_params
.chiprev
= ai_get_chiprev(wlc_hw
->sih
);
4563 sha_params
.chippkg
= ai_get_chippkg(wlc_hw
->sih
);
4564 sha_params
.sromrev
= wlc_hw
->sromrev
;
4565 sha_params
.boardtype
= ai_get_boardtype(wlc_hw
->sih
);
4566 sha_params
.boardrev
= wlc_hw
->boardrev
;
4567 sha_params
.boardflags
= wlc_hw
->boardflags
;
4568 sha_params
.boardflags2
= wlc_hw
->boardflags2
;
4570 /* alloc and save pointer to shared phy state area */
4571 wlc_hw
->phy_sh
= wlc_phy_shared_attach(&sha_params
);
4572 if (!wlc_hw
->phy_sh
) {
4577 /* initialize software state for each core and band */
4578 for (j
= 0; j
< wlc_hw
->_nbands
; j
++) {
4580 * band0 is always 2.4Ghz
4581 * band1, if present, is 5Ghz
4584 brcms_c_setxband(wlc_hw
, j
);
4586 wlc_hw
->band
->bandunit
= j
;
4587 wlc_hw
->band
->bandtype
= j
? BRCM_BAND_5G
: BRCM_BAND_2G
;
4588 wlc
->band
->bandunit
= j
;
4589 wlc
->band
->bandtype
= j
? BRCM_BAND_5G
: BRCM_BAND_2G
;
4590 wlc
->core
->coreidx
= core
->core_index
;
4592 wlc_hw
->machwcap
= bcma_read32(core
, D11REGOFFS(machwcap
));
4593 wlc_hw
->machwcap_backup
= wlc_hw
->machwcap
;
4595 /* init tx fifo size */
4596 WARN_ON((wlc_hw
->corerev
- XMTFIFOTBL_STARTREV
) < 0 ||
4597 (wlc_hw
->corerev
- XMTFIFOTBL_STARTREV
) >
4598 ARRAY_SIZE(xmtfifo_sz
));
4599 wlc_hw
->xmtfifo_sz
=
4600 xmtfifo_sz
[(wlc_hw
->corerev
- XMTFIFOTBL_STARTREV
)];
4601 WARN_ON(!wlc_hw
->xmtfifo_sz
[0]);
4603 /* Get a phy for this band */
4605 wlc_phy_attach(wlc_hw
->phy_sh
, core
,
4606 wlc_hw
->band
->bandtype
,
4608 if (wlc_hw
->band
->pi
== NULL
) {
4609 wiphy_err(wiphy
, "wl%d: brcms_b_attach: wlc_phy_"
4610 "attach failed\n", unit
);
4615 wlc_phy_machwcap_set(wlc_hw
->band
->pi
, wlc_hw
->machwcap
);
4617 wlc_phy_get_phyversion(wlc_hw
->band
->pi
, &wlc_hw
->band
->phytype
,
4618 &wlc_hw
->band
->phyrev
,
4619 &wlc_hw
->band
->radioid
,
4620 &wlc_hw
->band
->radiorev
);
4621 wlc_hw
->band
->abgphy_encore
=
4622 wlc_phy_get_encore(wlc_hw
->band
->pi
);
4623 wlc
->band
->abgphy_encore
= wlc_phy_get_encore(wlc_hw
->band
->pi
);
4624 wlc_hw
->band
->core_flags
=
4625 wlc_phy_get_coreflags(wlc_hw
->band
->pi
);
4627 /* verify good phy_type & supported phy revision */
4628 if (BRCMS_ISNPHY(wlc_hw
->band
)) {
4629 if (NCONF_HAS(wlc_hw
->band
->phyrev
))
4633 } else if (BRCMS_ISLCNPHY(wlc_hw
->band
)) {
4634 if (LCNCONF_HAS(wlc_hw
->band
->phyrev
))
4640 wiphy_err(wiphy
, "wl%d: brcms_b_attach: unsupported "
4641 "phy type/rev (%d/%d)\n", unit
,
4642 wlc_hw
->band
->phytype
, wlc_hw
->band
->phyrev
);
4649 * BMAC_NOTE: wlc->band->pi should not be set below and should
4650 * be done in the high level attach. However we can not make
4651 * that change until all low level access is changed to
4652 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4653 * keeping wlc_hw->band->pi as well for incremental update of
4654 * low level fns, and cut over low only init when all fns
4657 wlc
->band
->pi
= wlc_hw
->band
->pi
;
4658 wlc
->band
->phytype
= wlc_hw
->band
->phytype
;
4659 wlc
->band
->phyrev
= wlc_hw
->band
->phyrev
;
4660 wlc
->band
->radioid
= wlc_hw
->band
->radioid
;
4661 wlc
->band
->radiorev
= wlc_hw
->band
->radiorev
;
4663 /* default contention windows size limits */
4664 wlc_hw
->band
->CWmin
= APHY_CWMIN
;
4665 wlc_hw
->band
->CWmax
= PHY_CWMAX
;
4667 if (!brcms_b_attach_dmapio(wlc
, j
, wme
)) {
4673 /* disable core to match driver "down" state */
4674 brcms_c_coredisable(wlc_hw
);
4676 /* Match driver "down" state */
4677 ai_pci_down(wlc_hw
->sih
);
4679 /* turn off pll and xtal to match driver "down" state */
4680 brcms_b_xtal(wlc_hw
, OFF
);
4682 /* *******************************************************************
4683 * The hardware is in the DOWN state at this point. D11 core
4684 * or cores are in reset with clocks off, and the board PLLs
4685 * are off if possible.
4687 * Beyond this point, wlc->sbclk == false and chip registers
4688 * should not be touched.
4689 *********************************************************************
4692 /* init etheraddr state variables */
4693 brcms_c_get_macaddr(wlc_hw
, wlc_hw
->etheraddr
);
4695 if (is_broadcast_ether_addr(wlc_hw
->etheraddr
) ||
4696 is_zero_ether_addr(wlc_hw
->etheraddr
)) {
4697 wiphy_err(wiphy
, "wl%d: brcms_b_attach: bad macaddr\n",
4703 brcms_dbg_info(wlc_hw
->d11core
, "deviceid 0x%x nbands %d board 0x%x\n",
4704 wlc_hw
->deviceid
, wlc_hw
->_nbands
,
4705 ai_get_boardtype(wlc_hw
->sih
));
4710 wiphy_err(wiphy
, "wl%d: brcms_b_attach: failed with err %d\n", unit
,
4715 static void brcms_c_attach_antgain_init(struct brcms_c_info
*wlc
)
4718 unit
= wlc
->pub
->unit
;
4720 if ((wlc
->band
->antgain
== -1) && (wlc
->pub
->sromrev
== 1)) {
4721 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4722 wlc
->band
->antgain
= 8;
4723 } else if (wlc
->band
->antgain
== -1) {
4724 wiphy_err(wlc
->wiphy
, "wl%d: %s: Invalid antennas available in"
4725 " srom, using 2dB\n", unit
, __func__
);
4726 wlc
->band
->antgain
= 8;
4729 /* Older sroms specified gain in whole dbm only. In order
4730 * be able to specify qdbm granularity and remain backward
4731 * compatible the whole dbms are now encoded in only
4732 * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4733 * 6 bit signed number ranges from -32 - 31.
4737 * 0xc1 = 1.75 db (1 + 3 quarters),
4738 * 0x3f = -1 (-1 + 0 quarters),
4739 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4740 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4742 gain
= wlc
->band
->antgain
& 0x3f;
4743 gain
<<= 2; /* Sign extend */
4745 fract
= (wlc
->band
->antgain
& 0xc0) >> 6;
4746 wlc
->band
->antgain
= 4 * gain
+ fract
;
4750 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info
*wlc
)
4755 struct ssb_sprom
*sprom
= &wlc
->hw
->d11core
->bus
->sprom
;
4757 unit
= wlc
->pub
->unit
;
4758 bandtype
= wlc
->band
->bandtype
;
4760 /* get antennas available */
4761 if (bandtype
== BRCM_BAND_5G
)
4762 aa
= sprom
->ant_available_a
;
4764 aa
= sprom
->ant_available_bg
;
4766 if ((aa
< 1) || (aa
> 15)) {
4767 wiphy_err(wlc
->wiphy
, "wl%d: %s: Invalid antennas available in"
4768 " srom (0x%x), using 3\n", unit
, __func__
, aa
);
4772 /* reset the defaults if we have a single antenna */
4774 wlc
->stf
->ant_rx_ovr
= ANT_RX_DIV_FORCE_0
;
4775 wlc
->stf
->txant
= ANT_TX_FORCE_0
;
4776 } else if (aa
== 2) {
4777 wlc
->stf
->ant_rx_ovr
= ANT_RX_DIV_FORCE_1
;
4778 wlc
->stf
->txant
= ANT_TX_FORCE_1
;
4782 /* Compute Antenna Gain */
4783 if (bandtype
== BRCM_BAND_5G
)
4784 wlc
->band
->antgain
= sprom
->antenna_gain
.a1
;
4786 wlc
->band
->antgain
= sprom
->antenna_gain
.a0
;
4788 brcms_c_attach_antgain_init(wlc
);
4793 static void brcms_c_bss_default_init(struct brcms_c_info
*wlc
)
4796 struct brcms_band
*band
;
4797 struct brcms_bss_info
*bi
= wlc
->default_bss
;
4799 /* init default and target BSS with some sane initial values */
4800 memset((char *)(bi
), 0, sizeof(struct brcms_bss_info
));
4801 bi
->beacon_period
= BEACON_INTERVAL_DEFAULT
;
4803 /* fill the default channel as the first valid channel
4804 * starting from the 2G channels
4806 chanspec
= ch20mhz_chspec(1);
4807 wlc
->home_chanspec
= bi
->chanspec
= chanspec
;
4809 /* find the band of our default channel */
4811 if (wlc
->pub
->_nbands
> 1 &&
4812 band
->bandunit
!= chspec_bandunit(chanspec
))
4813 band
= wlc
->bandstate
[OTHERBANDUNIT(wlc
)];
4815 /* init bss rates to the band specific default rate set */
4816 brcms_c_rateset_default(&bi
->rateset
, NULL
, band
->phytype
,
4817 band
->bandtype
, false, BRCMS_RATE_MASK_FULL
,
4818 (bool) (wlc
->pub
->_n_enab
& SUPPORT_11N
),
4819 brcms_chspec_bw(chanspec
), wlc
->stf
->txstreams
);
4821 if (wlc
->pub
->_n_enab
& SUPPORT_11N
)
4822 bi
->flags
|= BRCMS_BSS_HT
;
4825 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info
*wlc
, u8 bwcap
)
4828 struct brcms_band
*band
;
4830 for (i
= 0; i
< wlc
->pub
->_nbands
; i
++) {
4831 band
= wlc
->bandstate
[i
];
4832 if (band
->bandtype
== BRCM_BAND_5G
) {
4833 if ((bwcap
== BRCMS_N_BW_40ALL
)
4834 || (bwcap
== BRCMS_N_BW_20IN2G_40IN5G
))
4835 band
->mimo_cap_40
= true;
4837 band
->mimo_cap_40
= false;
4839 if (bwcap
== BRCMS_N_BW_40ALL
)
4840 band
->mimo_cap_40
= true;
4842 band
->mimo_cap_40
= false;
4847 static void brcms_c_timers_deinit(struct brcms_c_info
*wlc
)
4849 /* free timer state */
4851 brcms_free_timer(wlc
->wdtimer
);
4852 wlc
->wdtimer
= NULL
;
4854 if (wlc
->radio_timer
) {
4855 brcms_free_timer(wlc
->radio_timer
);
4856 wlc
->radio_timer
= NULL
;
4860 static void brcms_c_detach_module(struct brcms_c_info
*wlc
)
4863 brcms_c_antsel_detach(wlc
->asi
);
4868 brcms_c_ampdu_detach(wlc
->ampdu
);
4872 brcms_c_stf_detach(wlc
);
4878 static int brcms_b_detach(struct brcms_c_info
*wlc
)
4881 struct brcms_hw_band
*band
;
4882 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
4887 brcms_b_detach_dmapio(wlc_hw
);
4889 band
= wlc_hw
->band
;
4890 for (i
= 0; i
< wlc_hw
->_nbands
; i
++) {
4892 /* Detach this band's phy */
4893 wlc_phy_detach(band
->pi
);
4896 band
= wlc_hw
->bandstate
[OTHERBANDUNIT(wlc
)];
4899 /* Free shared phy state */
4900 kfree(wlc_hw
->phy_sh
);
4902 wlc_phy_shim_detach(wlc_hw
->physhim
);
4905 ai_detach(wlc_hw
->sih
);
4914 * Return a count of the number of driver callbacks still pending.
4916 * General policy is that brcms_c_detach can only dealloc/free software states.
4917 * It can NOT touch hardware registers since the d11core may be in reset and
4918 * clock may not be available.
4919 * One exception is sb register access, which is possible if crystal is turned
4920 * on after "down" state, driver should avoid software timer with the exception
4923 uint
brcms_c_detach(struct brcms_c_info
*wlc
)
4930 BCMMSG(wlc
->wiphy
, "wl%d\n", wlc
->pub
->unit
);
4932 callbacks
+= brcms_b_detach(wlc
);
4934 /* delete software timers */
4935 if (!brcms_c_radio_monitor_stop(wlc
))
4938 brcms_c_channel_mgr_detach(wlc
->cmi
);
4940 brcms_c_timers_deinit(wlc
);
4942 brcms_c_detach_module(wlc
);
4944 brcms_c_detach_mfree(wlc
);
4948 /* update state that depends on the current value of "ap" */
4949 static void brcms_c_ap_upd(struct brcms_c_info
*wlc
)
4951 /* STA-BSS; short capable */
4952 wlc
->PLCPHdr_override
= BRCMS_PLCP_SHORT
;
4955 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4956 static void brcms_b_hw_up(struct brcms_hardware
*wlc_hw
)
4958 if (wlc_hw
->wlc
->pub
->hw_up
)
4961 brcms_dbg_info(wlc_hw
->d11core
, "wl%d\n", wlc_hw
->unit
);
4964 * Enable pll and xtal, initialize the power control registers,
4965 * and force fastclock for the remainder of brcms_c_up().
4967 brcms_b_xtal(wlc_hw
, ON
);
4968 ai_clkctl_init(wlc_hw
->sih
);
4969 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
4972 * TODO: test suspend/resume
4974 * AI chip doesn't restore bar0win2 on
4975 * hibernation/resume, need sw fixup
4979 * Inform phy that a POR reset has occurred so
4980 * it does a complete phy init
4982 wlc_phy_por_inform(wlc_hw
->band
->pi
);
4984 wlc_hw
->ucode_loaded
= false;
4985 wlc_hw
->wlc
->pub
->hw_up
= true;
4987 if ((wlc_hw
->boardflags
& BFL_FEM
)
4988 && (ai_get_chip_id(wlc_hw
->sih
) == BCMA_CHIP_ID_BCM4313
)) {
4990 (wlc_hw
->boardrev
>= 0x1250
4991 && (wlc_hw
->boardflags
& BFL_FEM_BT
)))
4992 ai_epa_4313war(wlc_hw
->sih
);
4996 static int brcms_b_up_prep(struct brcms_hardware
*wlc_hw
)
4998 brcms_dbg_info(wlc_hw
->d11core
, "wl%d\n", wlc_hw
->unit
);
5001 * Enable pll and xtal, initialize the power control registers,
5002 * and force fastclock for the remainder of brcms_c_up().
5004 brcms_b_xtal(wlc_hw
, ON
);
5005 ai_clkctl_init(wlc_hw
->sih
);
5006 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
5009 * Configure pci/pcmcia here instead of in brcms_c_attach()
5010 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
5012 bcma_core_pci_irq_ctl(&wlc_hw
->d11core
->bus
->drv_pci
[0], wlc_hw
->d11core
,
5016 * Need to read the hwradio status here to cover the case where the
5017 * system is loaded with the hw radio disabled. We do not want to
5018 * bring the driver up in this case.
5020 if (brcms_b_radio_read_hwdisabled(wlc_hw
)) {
5021 /* put SB PCI in down state again */
5022 ai_pci_down(wlc_hw
->sih
);
5023 brcms_b_xtal(wlc_hw
, OFF
);
5027 ai_pci_up(wlc_hw
->sih
);
5029 /* reset the d11 core */
5030 brcms_b_corereset(wlc_hw
, BRCMS_USE_COREFLAGS
);
5035 static int brcms_b_up_finish(struct brcms_hardware
*wlc_hw
)
5038 wlc_phy_hw_state_upd(wlc_hw
->band
->pi
, true);
5040 /* FULLY enable dynamic power control and d11 core interrupt */
5041 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_DYNAMIC
);
5042 brcms_intrson(wlc_hw
->wlc
->wl
);
5047 * Write WME tunable parameters for retransmit/max rate
5048 * from wlc struct to ucode
5050 static void brcms_c_wme_retries_write(struct brcms_c_info
*wlc
)
5054 /* Need clock to do this */
5058 for (ac
= 0; ac
< IEEE80211_NUM_ACS
; ac
++)
5059 brcms_b_write_shm(wlc
->hw
, M_AC_TXLMT_ADDR(ac
),
5060 wlc
->wme_retries
[ac
]);
5063 /* make interface operational */
5064 int brcms_c_up(struct brcms_c_info
*wlc
)
5066 struct ieee80211_channel
*ch
;
5068 brcms_dbg_info(wlc
->hw
->d11core
, "wl%d\n", wlc
->pub
->unit
);
5070 /* HW is turned off so don't try to access it */
5071 if (wlc
->pub
->hw_off
|| brcms_deviceremoved(wlc
))
5074 if (!wlc
->pub
->hw_up
) {
5075 brcms_b_hw_up(wlc
->hw
);
5076 wlc
->pub
->hw_up
= true;
5079 if ((wlc
->pub
->boardflags
& BFL_FEM
)
5080 && (ai_get_chip_id(wlc
->hw
->sih
) == BCMA_CHIP_ID_BCM4313
)) {
5081 if (wlc
->pub
->boardrev
>= 0x1250
5082 && (wlc
->pub
->boardflags
& BFL_FEM_BT
))
5083 brcms_b_mhf(wlc
->hw
, MHF5
, MHF5_4313_GPIOCTRL
,
5084 MHF5_4313_GPIOCTRL
, BRCM_BAND_ALL
);
5086 brcms_b_mhf(wlc
->hw
, MHF4
, MHF4_EXTPA_ENABLE
,
5087 MHF4_EXTPA_ENABLE
, BRCM_BAND_ALL
);
5091 * Need to read the hwradio status here to cover the case where the
5092 * system is loaded with the hw radio disabled. We do not want to bring
5093 * the driver up in this case. If radio is disabled, abort up, lower
5094 * power, start radio timer and return 0(for NDIS) don't call
5095 * radio_update to avoid looping brcms_c_up.
5097 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5099 if (!wlc
->pub
->radio_disabled
) {
5100 int status
= brcms_b_up_prep(wlc
->hw
);
5101 if (status
== -ENOMEDIUM
) {
5103 (wlc
->pub
->radio_disabled
, WL_RADIO_HW_DISABLE
)) {
5104 struct brcms_bss_cfg
*bsscfg
= wlc
->bsscfg
;
5105 mboolset(wlc
->pub
->radio_disabled
,
5106 WL_RADIO_HW_DISABLE
);
5108 if (bsscfg
->enable
&& bsscfg
->BSS
)
5109 brcms_err(wlc
->hw
->d11core
,
5110 "wl%d: up: rfdisable -> "
5111 "bsscfg_disable()\n",
5117 if (wlc
->pub
->radio_disabled
) {
5118 brcms_c_radio_monitor_start(wlc
);
5122 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5125 brcms_c_radio_monitor_stop(wlc
);
5127 /* Set EDCF hostflags */
5128 brcms_b_mhf(wlc
->hw
, MHF1
, MHF1_EDCF
, MHF1_EDCF
, BRCM_BAND_ALL
);
5130 brcms_init(wlc
->wl
);
5131 wlc
->pub
->up
= true;
5133 if (wlc
->bandinit_pending
) {
5134 ch
= wlc
->pub
->ieee_hw
->conf
.channel
;
5135 brcms_c_suspend_mac_and_wait(wlc
);
5136 brcms_c_set_chanspec(wlc
, ch20mhz_chspec(ch
->hw_value
));
5137 wlc
->bandinit_pending
= false;
5138 brcms_c_enable_mac(wlc
);
5141 brcms_b_up_finish(wlc
->hw
);
5143 /* Program the TX wme params with the current settings */
5144 brcms_c_wme_retries_write(wlc
);
5146 /* start one second watchdog timer */
5147 brcms_add_timer(wlc
->wdtimer
, TIMER_INTERVAL_WATCHDOG
, true);
5148 wlc
->WDarmed
= true;
5150 /* ensure antenna config is up to date */
5151 brcms_c_stf_phy_txant_upd(wlc
);
5152 /* ensure LDPC config is in sync */
5153 brcms_c_ht_update_ldpc(wlc
, wlc
->stf
->ldpc
);
5158 static uint
brcms_c_down_del_timer(struct brcms_c_info
*wlc
)
5165 static int brcms_b_bmac_down_prep(struct brcms_hardware
*wlc_hw
)
5173 dev_gone
= brcms_deviceremoved(wlc_hw
->wlc
);
5175 /* disable interrupts */
5177 wlc_hw
->wlc
->macintmask
= 0;
5179 /* now disable interrupts */
5180 brcms_intrsoff(wlc_hw
->wlc
->wl
);
5182 /* ensure we're running on the pll clock again */
5183 brcms_b_clkctl_clk(wlc_hw
, BCMA_CLKMODE_FAST
);
5185 /* down phy at the last of this stage */
5186 callbacks
+= wlc_phy_down(wlc_hw
->band
->pi
);
5191 static int brcms_b_down_finish(struct brcms_hardware
*wlc_hw
)
5200 wlc_phy_hw_state_upd(wlc_hw
->band
->pi
, false);
5202 dev_gone
= brcms_deviceremoved(wlc_hw
->wlc
);
5205 wlc_hw
->sbclk
= false;
5206 wlc_hw
->clk
= false;
5207 wlc_phy_hw_clk_state_upd(wlc_hw
->band
->pi
, false);
5209 /* reclaim any posted packets */
5210 brcms_c_flushqueues(wlc_hw
->wlc
);
5213 /* Reset and disable the core */
5214 if (bcma_core_is_enabled(wlc_hw
->d11core
)) {
5215 if (bcma_read32(wlc_hw
->d11core
,
5216 D11REGOFFS(maccontrol
)) & MCTL_EN_MAC
)
5217 brcms_c_suspend_mac_and_wait(wlc_hw
->wlc
);
5218 callbacks
+= brcms_reset(wlc_hw
->wlc
->wl
);
5219 brcms_c_coredisable(wlc_hw
);
5222 /* turn off primary xtal and pll */
5223 if (!wlc_hw
->noreset
) {
5224 ai_pci_down(wlc_hw
->sih
);
5225 brcms_b_xtal(wlc_hw
, OFF
);
5233 * Mark the interface nonoperational, stop the software mechanisms,
5234 * disable the hardware, free any transient buffer state.
5235 * Return a count of the number of driver callbacks still pending.
5237 uint
brcms_c_down(struct brcms_c_info
*wlc
)
5242 bool dev_gone
= false;
5244 brcms_dbg_info(wlc
->hw
->d11core
, "wl%d\n", wlc
->pub
->unit
);
5246 /* check if we are already in the going down path */
5247 if (wlc
->going_down
) {
5248 brcms_err(wlc
->hw
->d11core
,
5249 "wl%d: %s: Driver going down so return\n",
5250 wlc
->pub
->unit
, __func__
);
5256 wlc
->going_down
= true;
5258 callbacks
+= brcms_b_bmac_down_prep(wlc
->hw
);
5260 dev_gone
= brcms_deviceremoved(wlc
);
5262 /* Call any registered down handlers */
5263 for (i
= 0; i
< BRCMS_MAXMODULES
; i
++) {
5264 if (wlc
->modulecb
[i
].down_fn
)
5266 wlc
->modulecb
[i
].down_fn(wlc
->modulecb
[i
].hdl
);
5269 /* cancel the watchdog timer */
5271 if (!brcms_del_timer(wlc
->wdtimer
))
5273 wlc
->WDarmed
= false;
5275 /* cancel all other timers */
5276 callbacks
+= brcms_c_down_del_timer(wlc
);
5278 wlc
->pub
->up
= false;
5280 wlc_phy_mute_upd(wlc
->band
->pi
, false, PHY_MUTE_ALL
);
5282 callbacks
+= brcms_b_down_finish(wlc
->hw
);
5284 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5287 wlc
->going_down
= false;
5291 /* Set the current gmode configuration */
5292 int brcms_c_set_gmode(struct brcms_c_info
*wlc
, u8 gmode
, bool config
)
5296 struct brcms_c_rateset rs
;
5297 /* Default to 54g Auto */
5298 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5299 s8 shortslot
= BRCMS_SHORTSLOT_AUTO
;
5300 bool shortslot_restrict
= false; /* Restrict association to stations
5301 * that support shortslot
5303 bool ofdm_basic
= false; /* Make 6, 12, and 24 basic rates */
5304 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5305 int preamble
= BRCMS_PLCP_LONG
;
5306 bool preamble_restrict
= false; /* Restrict association to stations
5307 * that support short preambles
5309 struct brcms_band
*band
;
5311 /* if N-support is enabled, allow Gmode set as long as requested
5312 * Gmode is not GMODE_LEGACY_B
5314 if ((wlc
->pub
->_n_enab
& SUPPORT_11N
) && gmode
== GMODE_LEGACY_B
)
5317 /* verify that we are dealing with 2G band and grab the band pointer */
5318 if (wlc
->band
->bandtype
== BRCM_BAND_2G
)
5320 else if ((wlc
->pub
->_nbands
> 1) &&
5321 (wlc
->bandstate
[OTHERBANDUNIT(wlc
)]->bandtype
== BRCM_BAND_2G
))
5322 band
= wlc
->bandstate
[OTHERBANDUNIT(wlc
)];
5326 /* update configuration value */
5328 brcms_c_protection_upd(wlc
, BRCMS_PROT_G_USER
, gmode
);
5330 /* Clear rateset override */
5331 memset(&rs
, 0, sizeof(struct brcms_c_rateset
));
5334 case GMODE_LEGACY_B
:
5335 shortslot
= BRCMS_SHORTSLOT_OFF
;
5336 brcms_c_rateset_copy(&gphy_legacy_rates
, &rs
);
5344 /* Accept defaults */
5349 preamble
= BRCMS_PLCP_SHORT
;
5350 preamble_restrict
= true;
5353 case GMODE_PERFORMANCE
:
5354 shortslot
= BRCMS_SHORTSLOT_ON
;
5355 shortslot_restrict
= true;
5357 preamble
= BRCMS_PLCP_SHORT
;
5358 preamble_restrict
= true;
5363 brcms_err(wlc
->hw
->d11core
, "wl%d: %s: invalid gmode %d\n",
5364 wlc
->pub
->unit
, __func__
, gmode
);
5368 band
->gmode
= gmode
;
5370 wlc
->shortslot_override
= shortslot
;
5372 /* Use the default 11g rateset */
5374 brcms_c_rateset_copy(&cck_ofdm_rates
, &rs
);
5377 for (i
= 0; i
< rs
.count
; i
++) {
5378 if (rs
.rates
[i
] == BRCM_RATE_6M
5379 || rs
.rates
[i
] == BRCM_RATE_12M
5380 || rs
.rates
[i
] == BRCM_RATE_24M
)
5381 rs
.rates
[i
] |= BRCMS_RATE_FLAG
;
5385 /* Set default bss rateset */
5386 wlc
->default_bss
->rateset
.count
= rs
.count
;
5387 memcpy(wlc
->default_bss
->rateset
.rates
, rs
.rates
,
5388 sizeof(wlc
->default_bss
->rateset
.rates
));
5393 int brcms_c_set_nmode(struct brcms_c_info
*wlc
)
5398 if (wlc
->stf
->txstreams
== WL_11N_3x3
)
5403 /* force GMODE_AUTO if NMODE is ON */
5404 brcms_c_set_gmode(wlc
, GMODE_AUTO
, true);
5405 if (nmode
== WL_11N_3x3
)
5406 wlc
->pub
->_n_enab
= SUPPORT_HT
;
5408 wlc
->pub
->_n_enab
= SUPPORT_11N
;
5409 wlc
->default_bss
->flags
|= BRCMS_BSS_HT
;
5410 /* add the mcs rates to the default and hw ratesets */
5411 brcms_c_rateset_mcs_build(&wlc
->default_bss
->rateset
,
5412 wlc
->stf
->txstreams
);
5413 for (i
= 0; i
< wlc
->pub
->_nbands
; i
++)
5414 memcpy(wlc
->bandstate
[i
]->hw_rateset
.mcs
,
5415 wlc
->default_bss
->rateset
.mcs
, MCSSET_LEN
);
5421 brcms_c_set_internal_rateset(struct brcms_c_info
*wlc
,
5422 struct brcms_c_rateset
*rs_arg
)
5424 struct brcms_c_rateset rs
, new;
5427 memcpy(&rs
, rs_arg
, sizeof(struct brcms_c_rateset
));
5429 /* check for bad count value */
5430 if ((rs
.count
== 0) || (rs
.count
> BRCMS_NUMRATES
))
5433 /* try the current band */
5434 bandunit
= wlc
->band
->bandunit
;
5435 memcpy(&new, &rs
, sizeof(struct brcms_c_rateset
));
5436 if (brcms_c_rate_hwrs_filter_sort_validate
5437 (&new, &wlc
->bandstate
[bandunit
]->hw_rateset
, true,
5438 wlc
->stf
->txstreams
))
5441 /* try the other band */
5442 if (brcms_is_mband_unlocked(wlc
)) {
5443 bandunit
= OTHERBANDUNIT(wlc
);
5444 memcpy(&new, &rs
, sizeof(struct brcms_c_rateset
));
5445 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5447 bandstate
[bandunit
]->
5449 wlc
->stf
->txstreams
))
5456 /* apply new rateset */
5457 memcpy(&wlc
->default_bss
->rateset
, &new,
5458 sizeof(struct brcms_c_rateset
));
5459 memcpy(&wlc
->bandstate
[bandunit
]->defrateset
, &new,
5460 sizeof(struct brcms_c_rateset
));
5464 static void brcms_c_ofdm_rateset_war(struct brcms_c_info
*wlc
)
5469 if (wlc
->bsscfg
->associated
)
5470 r
= wlc
->bsscfg
->current_bss
->rateset
.rates
[0];
5472 r
= wlc
->default_bss
->rateset
.rates
[0];
5474 wlc_phy_ofdm_rateset_war(wlc
->band
->pi
, war
);
5477 int brcms_c_set_channel(struct brcms_c_info
*wlc
, u16 channel
)
5479 u16 chspec
= ch20mhz_chspec(channel
);
5481 if (channel
< 0 || channel
> MAXCHANNEL
)
5484 if (!brcms_c_valid_chanspec_db(wlc
->cmi
, chspec
))
5488 if (!wlc
->pub
->up
&& brcms_is_mband_unlocked(wlc
)) {
5489 if (wlc
->band
->bandunit
!= chspec_bandunit(chspec
))
5490 wlc
->bandinit_pending
= true;
5492 wlc
->bandinit_pending
= false;
5495 wlc
->default_bss
->chanspec
= chspec
;
5496 /* brcms_c_BSSinit() will sanitize the rateset before
5498 if (wlc
->pub
->up
&& (wlc_phy_chanspec_get(wlc
->band
->pi
) != chspec
)) {
5499 brcms_c_set_home_chanspec(wlc
, chspec
);
5500 brcms_c_suspend_mac_and_wait(wlc
);
5501 brcms_c_set_chanspec(wlc
, chspec
);
5502 brcms_c_enable_mac(wlc
);
5507 int brcms_c_set_rate_limit(struct brcms_c_info
*wlc
, u16 srl
, u16 lrl
)
5511 if (srl
< 1 || srl
> RETRY_SHORT_MAX
||
5512 lrl
< 1 || lrl
> RETRY_SHORT_MAX
)
5518 brcms_b_retrylimit_upd(wlc
->hw
, wlc
->SRL
, wlc
->LRL
);
5520 for (ac
= 0; ac
< IEEE80211_NUM_ACS
; ac
++) {
5521 wlc
->wme_retries
[ac
] = SFIELD(wlc
->wme_retries
[ac
],
5522 EDCF_SHORT
, wlc
->SRL
);
5523 wlc
->wme_retries
[ac
] = SFIELD(wlc
->wme_retries
[ac
],
5524 EDCF_LONG
, wlc
->LRL
);
5526 brcms_c_wme_retries_write(wlc
);
5531 void brcms_c_get_current_rateset(struct brcms_c_info
*wlc
,
5532 struct brcm_rateset
*currs
)
5534 struct brcms_c_rateset
*rs
;
5536 if (wlc
->pub
->associated
)
5537 rs
= &wlc
->bsscfg
->current_bss
->rateset
;
5539 rs
= &wlc
->default_bss
->rateset
;
5541 /* Copy only legacy rateset section */
5542 currs
->count
= rs
->count
;
5543 memcpy(&currs
->rates
, &rs
->rates
, rs
->count
);
5546 int brcms_c_set_rateset(struct brcms_c_info
*wlc
, struct brcm_rateset
*rs
)
5548 struct brcms_c_rateset internal_rs
;
5551 if (rs
->count
> BRCMS_NUMRATES
)
5554 memset(&internal_rs
, 0, sizeof(struct brcms_c_rateset
));
5556 /* Copy only legacy rateset section */
5557 internal_rs
.count
= rs
->count
;
5558 memcpy(&internal_rs
.rates
, &rs
->rates
, internal_rs
.count
);
5560 /* merge rateset coming in with the current mcsset */
5561 if (wlc
->pub
->_n_enab
& SUPPORT_11N
) {
5562 struct brcms_bss_info
*mcsset_bss
;
5563 if (wlc
->bsscfg
->associated
)
5564 mcsset_bss
= wlc
->bsscfg
->current_bss
;
5566 mcsset_bss
= wlc
->default_bss
;
5567 memcpy(internal_rs
.mcs
, &mcsset_bss
->rateset
.mcs
[0],
5571 bcmerror
= brcms_c_set_internal_rateset(wlc
, &internal_rs
);
5573 brcms_c_ofdm_rateset_war(wlc
);
5578 int brcms_c_set_beacon_period(struct brcms_c_info
*wlc
, u16 period
)
5580 if (period
< DOT11_MIN_BEACON_PERIOD
||
5581 period
> DOT11_MAX_BEACON_PERIOD
)
5584 wlc
->default_bss
->beacon_period
= period
;
5588 u16
brcms_c_get_phy_type(struct brcms_c_info
*wlc
, int phyidx
)
5590 return wlc
->band
->phytype
;
5593 void brcms_c_set_shortslot_override(struct brcms_c_info
*wlc
, s8 sslot_override
)
5595 wlc
->shortslot_override
= sslot_override
;
5598 * shortslot is an 11g feature, so no more work if we are
5599 * currently on the 5G band
5601 if (wlc
->band
->bandtype
== BRCM_BAND_5G
)
5604 if (wlc
->pub
->up
&& wlc
->pub
->associated
) {
5605 /* let watchdog or beacon processing update shortslot */
5606 } else if (wlc
->pub
->up
) {
5607 /* unassociated shortslot is off */
5608 brcms_c_switch_shortslot(wlc
, false);
5610 /* driver is down, so just update the brcms_c_info
5612 if (wlc
->shortslot_override
== BRCMS_SHORTSLOT_AUTO
)
5613 wlc
->shortslot
= false;
5616 (wlc
->shortslot_override
==
5617 BRCMS_SHORTSLOT_ON
);
5622 * register watchdog and down handlers.
5624 int brcms_c_module_register(struct brcms_pub
*pub
,
5625 const char *name
, struct brcms_info
*hdl
,
5626 int (*d_fn
)(void *handle
))
5628 struct brcms_c_info
*wlc
= (struct brcms_c_info
*) pub
->wlc
;
5631 /* find an empty entry and just add, no duplication check! */
5632 for (i
= 0; i
< BRCMS_MAXMODULES
; i
++) {
5633 if (wlc
->modulecb
[i
].name
[0] == '\0') {
5634 strncpy(wlc
->modulecb
[i
].name
, name
,
5635 sizeof(wlc
->modulecb
[i
].name
) - 1);
5636 wlc
->modulecb
[i
].hdl
= hdl
;
5637 wlc
->modulecb
[i
].down_fn
= d_fn
;
5645 /* unregister module callbacks */
5646 int brcms_c_module_unregister(struct brcms_pub
*pub
, const char *name
,
5647 struct brcms_info
*hdl
)
5649 struct brcms_c_info
*wlc
= (struct brcms_c_info
*) pub
->wlc
;
5655 for (i
= 0; i
< BRCMS_MAXMODULES
; i
++) {
5656 if (!strcmp(wlc
->modulecb
[i
].name
, name
) &&
5657 (wlc
->modulecb
[i
].hdl
== hdl
)) {
5658 memset(&wlc
->modulecb
[i
], 0, sizeof(struct modulecb
));
5663 /* table not found! */
5667 void brcms_c_print_txstatus(struct tx_status
*txs
)
5669 pr_debug("\ntxpkt (MPDU) Complete\n");
5671 pr_debug("FrameID: %04x TxStatus: %04x\n", txs
->frameid
, txs
->status
);
5673 pr_debug("[15:12] %d frame attempts\n",
5674 (txs
->status
& TX_STATUS_FRM_RTX_MASK
) >>
5675 TX_STATUS_FRM_RTX_SHIFT
);
5676 pr_debug(" [11:8] %d rts attempts\n",
5677 (txs
->status
& TX_STATUS_RTS_RTX_MASK
) >>
5678 TX_STATUS_RTS_RTX_SHIFT
);
5679 pr_debug(" [7] %d PM mode indicated\n",
5680 txs
->status
& TX_STATUS_PMINDCTD
? 1 : 0);
5681 pr_debug(" [6] %d intermediate status\n",
5682 txs
->status
& TX_STATUS_INTERMEDIATE
? 1 : 0);
5683 pr_debug(" [5] %d AMPDU\n",
5684 txs
->status
& TX_STATUS_AMPDU
? 1 : 0);
5685 pr_debug(" [4:2] %d Frame Suppressed Reason (%s)\n",
5686 (txs
->status
& TX_STATUS_SUPR_MASK
) >> TX_STATUS_SUPR_SHIFT
,
5691 "Previous frag failure",
5695 } [(txs
->status
& TX_STATUS_SUPR_MASK
) >>
5696 TX_STATUS_SUPR_SHIFT
]);
5697 pr_debug(" [1] %d acked\n",
5698 txs
->status
& TX_STATUS_ACK_RCV
? 1 : 0);
5700 pr_debug("LastTxTime: %04x Seq: %04x PHYTxStatus: %04x RxAckRSSI: %04x RxAckSQ: %04x\n",
5701 txs
->lasttxtime
, txs
->sequence
, txs
->phyerr
,
5702 (txs
->ackphyrxsh
& PRXS1_JSSI_MASK
) >> PRXS1_JSSI_SHIFT
,
5703 (txs
->ackphyrxsh
& PRXS1_SQ_MASK
) >> PRXS1_SQ_SHIFT
);
5706 static bool brcms_c_chipmatch_pci(struct bcma_device
*core
)
5708 struct pci_dev
*pcidev
= core
->bus
->host_pci
;
5709 u16 vendor
= pcidev
->vendor
;
5710 u16 device
= pcidev
->device
;
5712 if (vendor
!= PCI_VENDOR_ID_BROADCOM
) {
5713 pr_err("unknown vendor id %04x\n", vendor
);
5717 if (device
== BCM43224_D11N_ID_VEN1
)
5719 if ((device
== BCM43224_D11N_ID
) || (device
== BCM43225_D11N2G_ID
))
5721 if (device
== BCM4313_D11N2G_ID
)
5723 if ((device
== BCM43236_D11N_ID
) || (device
== BCM43236_D11N2G_ID
))
5726 pr_err("unknown device id %04x\n", device
);
5730 static bool brcms_c_chipmatch_soc(struct bcma_device
*core
)
5732 struct bcma_chipinfo
*chipinfo
= &core
->bus
->chipinfo
;
5734 if (chipinfo
->id
== BCMA_CHIP_ID_BCM4716
)
5737 pr_err("unknown chip id %04x\n", chipinfo
->id
);
5741 bool brcms_c_chipmatch(struct bcma_device
*core
)
5743 switch (core
->bus
->hosttype
) {
5744 case BCMA_HOSTTYPE_PCI
:
5745 return brcms_c_chipmatch_pci(core
);
5746 case BCMA_HOSTTYPE_SOC
:
5747 return brcms_c_chipmatch_soc(core
);
5749 pr_err("unknown host type: %i\n", core
->bus
->hosttype
);
5755 void brcms_c_print_txdesc(struct d11txh
*txh
)
5757 u16 mtcl
= le16_to_cpu(txh
->MacTxControlLow
);
5758 u16 mtch
= le16_to_cpu(txh
->MacTxControlHigh
);
5759 u16 mfc
= le16_to_cpu(txh
->MacFrameControl
);
5760 u16 tfest
= le16_to_cpu(txh
->TxFesTimeNormal
);
5761 u16 ptcw
= le16_to_cpu(txh
->PhyTxControlWord
);
5762 u16 ptcw_1
= le16_to_cpu(txh
->PhyTxControlWord_1
);
5763 u16 ptcw_1_Fbr
= le16_to_cpu(txh
->PhyTxControlWord_1_Fbr
);
5764 u16 ptcw_1_Rts
= le16_to_cpu(txh
->PhyTxControlWord_1_Rts
);
5765 u16 ptcw_1_FbrRts
= le16_to_cpu(txh
->PhyTxControlWord_1_FbrRts
);
5766 u16 mainrates
= le16_to_cpu(txh
->MainRates
);
5767 u16 xtraft
= le16_to_cpu(txh
->XtraFrameTypes
);
5769 u8
*ra
= txh
->TxFrameRA
;
5770 u16 tfestfb
= le16_to_cpu(txh
->TxFesTimeFallback
);
5771 u8
*rtspfb
= txh
->RTSPLCPFallback
;
5772 u16 rtsdfb
= le16_to_cpu(txh
->RTSDurFallback
);
5773 u8
*fragpfb
= txh
->FragPLCPFallback
;
5774 u16 fragdfb
= le16_to_cpu(txh
->FragDurFallback
);
5775 u16 mmodelen
= le16_to_cpu(txh
->MModeLen
);
5776 u16 mmodefbrlen
= le16_to_cpu(txh
->MModeFbrLen
);
5777 u16 tfid
= le16_to_cpu(txh
->TxFrameID
);
5778 u16 txs
= le16_to_cpu(txh
->TxStatus
);
5779 u16 mnmpdu
= le16_to_cpu(txh
->MaxNMpdus
);
5780 u16 mabyte
= le16_to_cpu(txh
->MaxABytes_MRT
);
5781 u16 mabyte_f
= le16_to_cpu(txh
->MaxABytes_FBR
);
5782 u16 mmbyte
= le16_to_cpu(txh
->MinMBytes
);
5784 u8
*rtsph
= txh
->RTSPhyHeader
;
5785 struct ieee80211_rts rts
= txh
->rts_frame
;
5787 /* add plcp header along with txh descriptor */
5788 brcmu_dbg_hex_dump(txh
, sizeof(struct d11txh
) + 48,
5789 "Raw TxDesc + plcp header:\n");
5791 pr_debug("TxCtlLow: %04x ", mtcl
);
5792 pr_debug("TxCtlHigh: %04x ", mtch
);
5793 pr_debug("FC: %04x ", mfc
);
5794 pr_debug("FES Time: %04x\n", tfest
);
5795 pr_debug("PhyCtl: %04x%s ", ptcw
,
5796 (ptcw
& PHY_TXC_SHORT_HDR
) ? " short" : "");
5797 pr_debug("PhyCtl_1: %04x ", ptcw_1
);
5798 pr_debug("PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr
);
5799 pr_debug("PhyCtl_1_Rts: %04x ", ptcw_1_Rts
);
5800 pr_debug("PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts
);
5801 pr_debug("MainRates: %04x ", mainrates
);
5802 pr_debug("XtraFrameTypes: %04x ", xtraft
);
5805 print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET
, iv
, sizeof(txh
->IV
));
5806 print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET
,
5807 ra
, sizeof(txh
->TxFrameRA
));
5809 pr_debug("Fb FES Time: %04x ", tfestfb
);
5810 print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET
,
5811 rtspfb
, sizeof(txh
->RTSPLCPFallback
));
5812 pr_debug("RTS DUR: %04x ", rtsdfb
);
5813 print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET
,
5814 fragpfb
, sizeof(txh
->FragPLCPFallback
));
5815 pr_debug("DUR: %04x", fragdfb
);
5818 pr_debug("MModeLen: %04x ", mmodelen
);
5819 pr_debug("MModeFbrLen: %04x\n", mmodefbrlen
);
5821 pr_debug("FrameID: %04x\n", tfid
);
5822 pr_debug("TxStatus: %04x\n", txs
);
5824 pr_debug("MaxNumMpdu: %04x\n", mnmpdu
);
5825 pr_debug("MaxAggbyte: %04x\n", mabyte
);
5826 pr_debug("MaxAggbyte_fb: %04x\n", mabyte_f
);
5827 pr_debug("MinByte: %04x\n", mmbyte
);
5829 print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET
,
5830 rtsph
, sizeof(txh
->RTSPhyHeader
));
5831 print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET
,
5832 (u8
*)&rts
, sizeof(txh
->rts_frame
));
5835 #endif /* defined(DEBUG) */
5839 brcms_c_format_flags(const struct brcms_c_bit_desc
*bd
, u32 flags
, char *buf
,
5845 int slen
= 0, nlen
= 0;
5849 if (len
< 2 || !buf
)
5854 for (i
= 0; flags
!= 0; i
++) {
5857 if (bit
== 0 && flags
!= 0) {
5858 /* print any unnamed bits */
5859 snprintf(hexstr
, 16, "0x%X", flags
);
5861 flags
= 0; /* exit loop */
5862 } else if ((flags
& bit
) == 0)
5865 nlen
= strlen(name
);
5867 /* count btwn flag space */
5870 /* need NULL char as well */
5873 /* copy NULL char but don't count it */
5874 strncpy(p
, name
, nlen
+ 1);
5876 /* copy btwn flag space and NULL char */
5878 p
+= snprintf(p
, 2, " ");
5882 /* indicate the str was too short */
5885 p
-= 2 - len
; /* overwrite last char */
5886 p
+= snprintf(p
, 2, ">");
5889 return (int)(p
- buf
);
5891 #endif /* defined(DEBUG) */
5894 void brcms_c_print_rxh(struct d11rxhdr
*rxh
)
5896 u16 len
= rxh
->RxFrameSize
;
5897 u16 phystatus_0
= rxh
->PhyRxStatus_0
;
5898 u16 phystatus_1
= rxh
->PhyRxStatus_1
;
5899 u16 phystatus_2
= rxh
->PhyRxStatus_2
;
5900 u16 phystatus_3
= rxh
->PhyRxStatus_3
;
5901 u16 macstatus1
= rxh
->RxStatus1
;
5902 u16 macstatus2
= rxh
->RxStatus2
;
5905 static const struct brcms_c_bit_desc macstat_flags
[] = {
5906 {RXS_FCSERR
, "FCSErr"},
5907 {RXS_RESPFRAMETX
, "Reply"},
5908 {RXS_PBPRES
, "PADDING"},
5909 {RXS_DECATMPT
, "DeCr"},
5910 {RXS_DECERR
, "DeCrErr"},
5911 {RXS_BCNSENT
, "Bcn"},
5915 brcmu_dbg_hex_dump(rxh
, sizeof(struct d11rxhdr
), "Raw RxDesc:\n");
5917 brcms_c_format_flags(macstat_flags
, macstatus1
, flagstr
, 64);
5919 snprintf(lenbuf
, sizeof(lenbuf
), "0x%x", len
);
5921 pr_debug("RxFrameSize: %6s (%d)%s\n", lenbuf
, len
,
5922 (rxh
->PhyRxStatus_0
& PRXS0_SHORTH
) ? " short preamble" : "");
5923 pr_debug("RxPHYStatus: %04x %04x %04x %04x\n",
5924 phystatus_0
, phystatus_1
, phystatus_2
, phystatus_3
);
5925 pr_debug("RxMACStatus: %x %s\n", macstatus1
, flagstr
);
5926 pr_debug("RXMACaggtype: %x\n",
5927 (macstatus2
& RXS_AGGTYPE_MASK
));
5928 pr_debug("RxTSFTime: %04x\n", rxh
->RxTSFTime
);
5930 #endif /* defined(DEBUG) */
5932 u16
brcms_b_rate_shm_offset(struct brcms_hardware
*wlc_hw
, u8 rate
)
5937 /* get the phy specific rate encoding for the PLCP SIGNAL field */
5938 if (is_ofdm_rate(rate
))
5939 table_ptr
= M_RT_DIRMAP_A
;
5941 table_ptr
= M_RT_DIRMAP_B
;
5943 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5944 * the index into the rate table.
5946 phy_rate
= rate_info
[rate
] & BRCMS_RATE_MASK
;
5947 index
= phy_rate
& 0xf;
5949 /* Find the SHM pointer to the rate table entry by looking in the
5952 return 2 * brcms_b_read_shm(wlc_hw
, table_ptr
+ (index
* 2));
5956 * bcmc_fid_generate:
5957 * Generate frame ID for a BCMC packet. The frag field is not used
5958 * for MC frames so is used as part of the sequence number.
5961 bcmc_fid_generate(struct brcms_c_info
*wlc
, struct brcms_bss_cfg
*bsscfg
,
5966 frameid
= le16_to_cpu(txh
->TxFrameID
) & ~(TXFID_SEQ_MASK
|
5970 mc_fid_counter
++) << TXFID_SEQ_SHIFT
) & TXFID_SEQ_MASK
) |
5977 brcms_c_calc_ack_time(struct brcms_c_info
*wlc
, u32 rspec
,
5982 brcms_dbg_mac80211(wlc
->hw
->d11core
,
5983 "wl%d: rspec 0x%x, preamble_type %d\n",
5984 wlc
->pub
->unit
, rspec
, preamble_type
);
5986 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
5987 * is less than or equal to the rate of the immediately previous
5990 rspec
= brcms_basic_rate(wlc
, rspec
);
5991 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
5993 brcms_c_calc_frame_time(wlc
, rspec
, preamble_type
,
5994 (DOT11_ACK_LEN
+ FCS_LEN
));
5999 brcms_c_calc_cts_time(struct brcms_c_info
*wlc
, u32 rspec
,
6002 brcms_dbg_mac80211(wlc
->hw
->d11core
,
6003 "wl%d: ratespec 0x%x, preamble_type %d\n",
6004 wlc
->pub
->unit
, rspec
, preamble_type
);
6005 return brcms_c_calc_ack_time(wlc
, rspec
, preamble_type
);
6009 brcms_c_calc_ba_time(struct brcms_c_info
*wlc
, u32 rspec
,
6012 brcms_dbg_mac80211(wlc
->hw
->d11core
,
6013 "wl%d: rspec 0x%x, preamble_type %d\n",
6014 wlc
->pub
->unit
, rspec
, preamble_type
);
6016 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
6017 * is less than or equal to the rate of the immediately previous
6020 rspec
= brcms_basic_rate(wlc
, rspec
);
6021 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
6022 return brcms_c_calc_frame_time(wlc
, rspec
, preamble_type
,
6023 (DOT11_BA_LEN
+ DOT11_BA_BITMAP_LEN
+
6027 /* brcms_c_compute_frame_dur()
6029 * Calculate the 802.11 MAC header DUR field for MPDU
6030 * DUR for a single frame = 1 SIFS + 1 ACK
6031 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
6033 * rate MPDU rate in unit of 500kbps
6034 * next_frag_len next MPDU length in bytes
6035 * preamble_type use short/GF or long/MM PLCP header
6038 brcms_c_compute_frame_dur(struct brcms_c_info
*wlc
, u32 rate
,
6039 u8 preamble_type
, uint next_frag_len
)
6043 sifs
= get_sifs(wlc
->band
);
6046 dur
+= (u16
) brcms_c_calc_ack_time(wlc
, rate
, preamble_type
);
6048 if (next_frag_len
) {
6049 /* Double the current DUR to get 2 SIFS + 2 ACKs */
6051 /* add another SIFS and the frag time */
6054 (u16
) brcms_c_calc_frame_time(wlc
, rate
, preamble_type
,
6060 /* The opposite of brcms_c_calc_frame_time */
6062 brcms_c_calc_frame_len(struct brcms_c_info
*wlc
, u32 ratespec
,
6063 u8 preamble_type
, uint dur
)
6065 uint nsyms
, mac_len
, Ndps
, kNdps
;
6066 uint rate
= rspec2rate(ratespec
);
6068 brcms_dbg_mac80211(wlc
->hw
->d11core
,
6069 "wl%d: rspec 0x%x, preamble_type %d, dur %d\n",
6070 wlc
->pub
->unit
, ratespec
, preamble_type
, dur
);
6072 if (is_mcs_rate(ratespec
)) {
6073 uint mcs
= ratespec
& RSPEC_RATE_MASK
;
6074 int tot_streams
= mcs_2_txstreams(mcs
) + rspec_stc(ratespec
);
6075 dur
-= PREN_PREAMBLE
+ (tot_streams
* PREN_PREAMBLE_EXT
);
6076 /* payload calculation matches that of regular ofdm */
6077 if (wlc
->band
->bandtype
== BRCM_BAND_2G
)
6078 dur
-= DOT11_OFDM_SIGNAL_EXTENSION
;
6079 /* kNdbps = kbps * 4 */
6080 kNdps
= mcs_2_rate(mcs
, rspec_is40mhz(ratespec
),
6081 rspec_issgi(ratespec
)) * 4;
6082 nsyms
= dur
/ APHY_SYMBOL_TIME
;
6085 ((APHY_SERVICE_NBITS
+ APHY_TAIL_NBITS
) * 1000)) / 8000;
6086 } else if (is_ofdm_rate(ratespec
)) {
6087 dur
-= APHY_PREAMBLE_TIME
;
6088 dur
-= APHY_SIGNAL_TIME
;
6089 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
6091 nsyms
= dur
/ APHY_SYMBOL_TIME
;
6094 (APHY_SERVICE_NBITS
+ APHY_TAIL_NBITS
)) / 8;
6096 if (preamble_type
& BRCMS_SHORT_PREAMBLE
)
6097 dur
-= BPHY_PLCP_SHORT_TIME
;
6099 dur
-= BPHY_PLCP_TIME
;
6100 mac_len
= dur
* rate
;
6101 /* divide out factor of 2 in rate (1/2 mbps) */
6102 mac_len
= mac_len
/ 8 / 2;
6108 * Return true if the specified rate is supported by the specified band.
6109 * BRCM_BAND_AUTO indicates the current band.
6111 static bool brcms_c_valid_rate(struct brcms_c_info
*wlc
, u32 rspec
, int band
,
6114 struct brcms_c_rateset
*hw_rateset
;
6117 if ((band
== BRCM_BAND_AUTO
) || (band
== wlc
->band
->bandtype
))
6118 hw_rateset
= &wlc
->band
->hw_rateset
;
6119 else if (wlc
->pub
->_nbands
> 1)
6120 hw_rateset
= &wlc
->bandstate
[OTHERBANDUNIT(wlc
)]->hw_rateset
;
6122 /* other band specified and we are a single band device */
6125 /* check if this is a mimo rate */
6126 if (is_mcs_rate(rspec
)) {
6127 if ((rspec
& RSPEC_RATE_MASK
) >= MCS_TABLE_SIZE
)
6130 return isset(hw_rateset
->mcs
, (rspec
& RSPEC_RATE_MASK
));
6133 for (i
= 0; i
< hw_rateset
->count
; i
++)
6134 if (hw_rateset
->rates
[i
] == rspec2rate(rspec
))
6138 brcms_err(wlc
->hw
->d11core
, "wl%d: valid_rate: rate spec 0x%x "
6139 "not in hw_rateset\n", wlc
->pub
->unit
, rspec
);
6145 mac80211_wlc_set_nrate(struct brcms_c_info
*wlc
, struct brcms_band
*cur_band
,
6148 struct bcma_device
*core
= wlc
->hw
->d11core
;
6149 u8 stf
= (int_val
& NRATE_STF_MASK
) >> NRATE_STF_SHIFT
;
6150 u8 rate
= int_val
& NRATE_RATE_MASK
;
6152 bool ismcs
= ((int_val
& NRATE_MCS_INUSE
) == NRATE_MCS_INUSE
);
6153 bool issgi
= ((int_val
& NRATE_SGI_MASK
) >> NRATE_SGI_SHIFT
);
6154 bool override_mcs_only
= ((int_val
& NRATE_OVERRIDE_MCS_ONLY
)
6155 == NRATE_OVERRIDE_MCS_ONLY
);
6161 /* validate the combination of rate/mcs/stf is allowed */
6162 if ((wlc
->pub
->_n_enab
& SUPPORT_11N
) && ismcs
) {
6163 /* mcs only allowed when nmode */
6164 if (stf
> PHY_TXC1_MODE_SDM
) {
6165 brcms_err(core
, "wl%d: %s: Invalid stf\n",
6166 wlc
->pub
->unit
, __func__
);
6171 /* mcs 32 is a special case, DUP mode 40 only */
6173 if (!CHSPEC_IS40(wlc
->home_chanspec
) ||
6174 ((stf
!= PHY_TXC1_MODE_SISO
)
6175 && (stf
!= PHY_TXC1_MODE_CDD
))) {
6176 brcms_err(core
, "wl%d: %s: Invalid mcs 32\n",
6177 wlc
->pub
->unit
, __func__
);
6181 /* mcs > 7 must use stf SDM */
6182 } else if (rate
> HIGHEST_SINGLE_STREAM_MCS
) {
6183 /* mcs > 7 must use stf SDM */
6184 if (stf
!= PHY_TXC1_MODE_SDM
) {
6185 brcms_dbg_mac80211(core
, "wl%d: enabling "
6186 "SDM mode for mcs %d\n",
6187 wlc
->pub
->unit
, rate
);
6188 stf
= PHY_TXC1_MODE_SDM
;
6192 * MCS 0-7 may use SISO, CDD, and for
6195 if ((stf
> PHY_TXC1_MODE_STBC
) ||
6196 (!BRCMS_STBC_CAP_PHY(wlc
)
6197 && (stf
== PHY_TXC1_MODE_STBC
))) {
6198 brcms_err(core
, "wl%d: %s: Invalid STBC\n",
6199 wlc
->pub
->unit
, __func__
);
6204 } else if (is_ofdm_rate(rate
)) {
6205 if ((stf
!= PHY_TXC1_MODE_CDD
) && (stf
!= PHY_TXC1_MODE_SISO
)) {
6206 brcms_err(core
, "wl%d: %s: Invalid OFDM\n",
6207 wlc
->pub
->unit
, __func__
);
6211 } else if (is_cck_rate(rate
)) {
6212 if ((cur_band
->bandtype
!= BRCM_BAND_2G
)
6213 || (stf
!= PHY_TXC1_MODE_SISO
)) {
6214 brcms_err(core
, "wl%d: %s: Invalid CCK\n",
6215 wlc
->pub
->unit
, __func__
);
6220 brcms_err(core
, "wl%d: %s: Unknown rate type\n",
6221 wlc
->pub
->unit
, __func__
);
6225 /* make sure multiple antennae are available for non-siso rates */
6226 if ((stf
!= PHY_TXC1_MODE_SISO
) && (wlc
->stf
->txstreams
== 1)) {
6227 brcms_err(core
, "wl%d: %s: SISO antenna but !SISO "
6228 "request\n", wlc
->pub
->unit
, __func__
);
6235 rspec
|= RSPEC_MIMORATE
;
6236 /* For STBC populate the STC field of the ratespec */
6237 if (stf
== PHY_TXC1_MODE_STBC
) {
6239 stc
= 1; /* Nss for single stream is always 1 */
6240 rspec
|= (stc
<< RSPEC_STC_SHIFT
);
6244 rspec
|= (stf
<< RSPEC_STF_SHIFT
);
6246 if (override_mcs_only
)
6247 rspec
|= RSPEC_OVERRIDE_MCS_ONLY
;
6250 rspec
|= RSPEC_SHORT_GI
;
6253 && !brcms_c_valid_rate(wlc
, rspec
, cur_band
->bandtype
, true))
6262 * Compute PLCP, but only requires actual rate and length of pkt.
6263 * Rate is given in the driver standard multiple of 500 kbps.
6264 * le is set for 11 Mbps rate if necessary.
6265 * Broken out for PRQ.
6268 static void brcms_c_cck_plcp_set(struct brcms_c_info
*wlc
, int rate_500
,
6269 uint length
, u8
*plcp
)
6282 usec
= (length
<< 4) / 11;
6283 if ((length
<< 4) - (usec
* 11) > 0)
6287 usec
= (length
<< 3) / 11;
6288 if ((length
<< 3) - (usec
* 11) > 0) {
6290 if ((usec
* 11) - (length
<< 3) >= 8)
6291 le
= D11B_PLCP_SIGNAL_LE
;
6296 brcms_err(wlc
->hw
->d11core
,
6297 "brcms_c_cck_plcp_set: unsupported rate %d\n",
6299 rate_500
= BRCM_RATE_1M
;
6303 /* PLCP signal byte */
6304 plcp
[0] = rate_500
* 5; /* r (500kbps) * 5 == r (100kbps) */
6305 /* PLCP service byte */
6306 plcp
[1] = (u8
) (le
| D11B_PLCP_SIGNAL_LOCKED
);
6307 /* PLCP length u16, little endian */
6308 plcp
[2] = usec
& 0xff;
6309 plcp
[3] = (usec
>> 8) & 0xff;
6315 /* Rate: 802.11 rate code, length: PSDU length in octets */
6316 static void brcms_c_compute_mimo_plcp(u32 rspec
, uint length
, u8
*plcp
)
6318 u8 mcs
= (u8
) (rspec
& RSPEC_RATE_MASK
);
6320 if (rspec_is40mhz(rspec
) || (mcs
== 32))
6321 plcp
[0] |= MIMO_PLCP_40MHZ
;
6322 BRCMS_SET_MIMO_PLCP_LEN(plcp
, length
);
6323 plcp
[3] = rspec_mimoplcp3(rspec
); /* rspec already holds this byte */
6324 plcp
[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6325 plcp
[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6329 /* Rate: 802.11 rate code, length: PSDU length in octets */
6331 brcms_c_compute_ofdm_plcp(u32 rspec
, u32 length
, u8
*plcp
)
6335 int rate
= rspec2rate(rspec
);
6338 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6341 rate_signal
= rate_info
[rate
] & BRCMS_RATE_MASK
;
6342 memset(plcp
, 0, D11_PHY_HDR_LEN
);
6343 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr
*) plcp
, rate_signal
);
6345 tmp
= (length
& 0xfff) << 5;
6346 plcp
[2] |= (tmp
>> 16) & 0xff;
6347 plcp
[1] |= (tmp
>> 8) & 0xff;
6348 plcp
[0] |= tmp
& 0xff;
6351 /* Rate: 802.11 rate code, length: PSDU length in octets */
6352 static void brcms_c_compute_cck_plcp(struct brcms_c_info
*wlc
, u32 rspec
,
6353 uint length
, u8
*plcp
)
6355 int rate
= rspec2rate(rspec
);
6357 brcms_c_cck_plcp_set(wlc
, rate
, length
, plcp
);
6361 brcms_c_compute_plcp(struct brcms_c_info
*wlc
, u32 rspec
,
6362 uint length
, u8
*plcp
)
6364 if (is_mcs_rate(rspec
))
6365 brcms_c_compute_mimo_plcp(rspec
, length
, plcp
);
6366 else if (is_ofdm_rate(rspec
))
6367 brcms_c_compute_ofdm_plcp(rspec
, length
, plcp
);
6369 brcms_c_compute_cck_plcp(wlc
, rspec
, length
, plcp
);
6372 /* brcms_c_compute_rtscts_dur()
6374 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6375 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6376 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
6378 * cts cts-to-self or rts/cts
6379 * rts_rate rts or cts rate in unit of 500kbps
6380 * rate next MPDU rate in unit of 500kbps
6381 * frame_len next MPDU frame length in bytes
6384 brcms_c_compute_rtscts_dur(struct brcms_c_info
*wlc
, bool cts_only
,
6386 u32 frame_rate
, u8 rts_preamble_type
,
6387 u8 frame_preamble_type
, uint frame_len
, bool ba
)
6391 sifs
= get_sifs(wlc
->band
);
6397 (u16
) brcms_c_calc_cts_time(wlc
, rts_rate
,
6405 (u16
) brcms_c_calc_frame_time(wlc
, frame_rate
, frame_preamble_type
,
6409 (u16
) brcms_c_calc_ba_time(wlc
, frame_rate
,
6410 BRCMS_SHORT_PREAMBLE
);
6413 (u16
) brcms_c_calc_ack_time(wlc
, frame_rate
,
6414 frame_preamble_type
);
6418 static u16
brcms_c_phytxctl1_calc(struct brcms_c_info
*wlc
, u32 rspec
)
6423 if (BRCMS_ISLCNPHY(wlc
->band
)) {
6424 bw
= PHY_TXC1_BW_20MHZ
;
6426 bw
= rspec_get_bw(rspec
);
6427 /* 10Mhz is not supported yet */
6428 if (bw
< PHY_TXC1_BW_20MHZ
) {
6429 brcms_err(wlc
->hw
->d11core
, "phytxctl1_calc: bw %d is "
6430 "not supported yet, set to 20L\n", bw
);
6431 bw
= PHY_TXC1_BW_20MHZ
;
6435 if (is_mcs_rate(rspec
)) {
6436 uint mcs
= rspec
& RSPEC_RATE_MASK
;
6438 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6439 phyctl1
= rspec_phytxbyte2(rspec
);
6440 /* set the upper byte of phyctl1 */
6441 phyctl1
|= (mcs_table
[mcs
].tx_phy_ctl3
<< 8);
6442 } else if (is_cck_rate(rspec
) && !BRCMS_ISLCNPHY(wlc
->band
)
6443 && !BRCMS_ISSSLPNPHY(wlc
->band
)) {
6445 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6446 * Data Rate. Eventually MIMOPHY would also be converted to
6449 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6450 phyctl1
= (bw
| (rspec_stf(rspec
) << PHY_TXC1_MODE_SHIFT
));
6451 } else { /* legacy OFDM/CCK */
6453 /* get the phyctl byte from rate phycfg table */
6454 phycfg
= brcms_c_rate_legacy_phyctl(rspec2rate(rspec
));
6456 brcms_err(wlc
->hw
->d11core
, "phytxctl1_calc: wrong "
6457 "legacy OFDM/CCK rate\n");
6460 /* set the upper byte of phyctl1 */
6462 (bw
| (phycfg
<< 8) |
6463 (rspec_stf(rspec
) << PHY_TXC1_MODE_SHIFT
));
6469 * Add struct d11txh, struct cck_phy_hdr.
6471 * 'p' data must start with 802.11 MAC header
6472 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6474 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6478 brcms_c_d11hdrs_mac80211(struct brcms_c_info
*wlc
, struct ieee80211_hw
*hw
,
6479 struct sk_buff
*p
, struct scb
*scb
, uint frag
,
6480 uint nfrags
, uint queue
, uint next_frag_len
)
6482 struct ieee80211_hdr
*h
;
6484 u8
*plcp
, plcp_fallback
[D11_PHY_HDR_LEN
];
6485 int len
, phylen
, rts_phylen
;
6486 u16 mch
, phyctl
, xfts
, mainrates
;
6487 u16 seq
= 0, mcl
= 0, status
= 0, frameid
= 0;
6488 u32 rspec
[2] = { BRCM_RATE_1M
, BRCM_RATE_1M
};
6489 u32 rts_rspec
[2] = { BRCM_RATE_1M
, BRCM_RATE_1M
};
6490 bool use_rts
= false;
6491 bool use_cts
= false;
6492 bool use_rifs
= false;
6493 bool short_preamble
[2] = { false, false };
6494 u8 preamble_type
[2] = { BRCMS_LONG_PREAMBLE
, BRCMS_LONG_PREAMBLE
};
6495 u8 rts_preamble_type
[2] = { BRCMS_LONG_PREAMBLE
, BRCMS_LONG_PREAMBLE
};
6496 u8
*rts_plcp
, rts_plcp_fallback
[D11_PHY_HDR_LEN
];
6497 struct ieee80211_rts
*rts
= NULL
;
6500 bool hwtkmic
= false;
6501 u16 mimo_ctlchbw
= PHY_TXC1_BW_20MHZ
;
6502 #define ANTCFG_NONE 0xFF
6503 u8 antcfg
= ANTCFG_NONE
;
6504 u8 fbantcfg
= ANTCFG_NONE
;
6505 uint phyctl1_stf
= 0;
6507 struct ieee80211_tx_rate
*txrate
[2];
6509 struct ieee80211_tx_info
*tx_info
;
6512 u8 mimo_preamble_type
;
6514 /* locate 802.11 MAC header */
6515 h
= (struct ieee80211_hdr
*)(p
->data
);
6516 qos
= ieee80211_is_data_qos(h
->frame_control
);
6518 /* compute length of frame in bytes for use in PLCP computations */
6520 phylen
= len
+ FCS_LEN
;
6523 tx_info
= IEEE80211_SKB_CB(p
);
6526 plcp
= skb_push(p
, D11_PHY_HDR_LEN
);
6528 /* add Broadcom tx descriptor header */
6529 txh
= (struct d11txh
*) skb_push(p
, D11_TXH_LEN
);
6530 memset(txh
, 0, D11_TXH_LEN
);
6533 if (tx_info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
6534 /* non-AP STA should never use BCMC queue */
6535 if (queue
== TX_BCMC_FIFO
) {
6536 brcms_err(wlc
->hw
->d11core
,
6537 "wl%d: %s: ASSERT queue == TX_BCMC!\n",
6538 wlc
->pub
->unit
, __func__
);
6539 frameid
= bcmc_fid_generate(wlc
, NULL
, txh
);
6541 /* Increment the counter for first fragment */
6542 if (tx_info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
6543 scb
->seqnum
[p
->priority
]++;
6545 /* extract fragment number from frame first */
6546 seq
= le16_to_cpu(h
->seq_ctrl
) & FRAGNUM_MASK
;
6547 seq
|= (scb
->seqnum
[p
->priority
] << SEQNUM_SHIFT
);
6548 h
->seq_ctrl
= cpu_to_le16(seq
);
6550 frameid
= ((seq
<< TXFID_SEQ_SHIFT
) & TXFID_SEQ_MASK
) |
6551 (queue
& TXFID_QUEUE_MASK
);
6554 frameid
|= queue
& TXFID_QUEUE_MASK
;
6556 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6557 if (ieee80211_is_beacon(h
->frame_control
))
6558 mcl
|= TXC_IGNOREPMQ
;
6560 txrate
[0] = tx_info
->control
.rates
;
6561 txrate
[1] = txrate
[0] + 1;
6564 * if rate control algorithm didn't give us a fallback
6565 * rate, use the primary rate
6567 if (txrate
[1]->idx
< 0)
6568 txrate
[1] = txrate
[0];
6570 for (k
= 0; k
< hw
->max_rates
; k
++) {
6571 is_mcs
= txrate
[k
]->flags
& IEEE80211_TX_RC_MCS
? true : false;
6573 if ((txrate
[k
]->idx
>= 0)
6574 && (txrate
[k
]->idx
<
6575 hw
->wiphy
->bands
[tx_info
->band
]->n_bitrates
)) {
6577 hw
->wiphy
->bands
[tx_info
->band
]->
6578 bitrates
[txrate
[k
]->idx
].hw_value
;
6581 flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
?
6584 rspec
[k
] = BRCM_RATE_1M
;
6587 rspec
[k
] = mac80211_wlc_set_nrate(wlc
, wlc
->band
,
6588 NRATE_MCS_INUSE
| txrate
[k
]->idx
);
6592 * Currently only support same setting for primay and
6593 * fallback rates. Unify flags for each rate into a
6594 * single value for the frame
6598 flags
& IEEE80211_TX_RC_USE_RTS_CTS
? true : false;
6601 flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
? true : false;
6606 * determine and validate primary rate
6607 * and fallback rates
6609 if (!rspec_active(rspec
[k
])) {
6610 rspec
[k
] = BRCM_RATE_1M
;
6612 if (!is_multicast_ether_addr(h
->addr1
)) {
6613 /* set tx antenna config */
6614 brcms_c_antsel_antcfg_get(wlc
->asi
, false,
6615 false, 0, 0, &antcfg
, &fbantcfg
);
6620 phyctl1_stf
= wlc
->stf
->ss_opmode
;
6622 if (wlc
->pub
->_n_enab
& SUPPORT_11N
) {
6623 for (k
= 0; k
< hw
->max_rates
; k
++) {
6625 * apply siso/cdd to single stream mcs's or ofdm
6626 * if rspec is auto selected
6628 if (((is_mcs_rate(rspec
[k
]) &&
6629 is_single_stream(rspec
[k
] & RSPEC_RATE_MASK
)) ||
6630 is_ofdm_rate(rspec
[k
]))
6631 && ((rspec
[k
] & RSPEC_OVERRIDE_MCS_ONLY
)
6632 || !(rspec
[k
] & RSPEC_OVERRIDE
))) {
6633 rspec
[k
] &= ~(RSPEC_STF_MASK
| RSPEC_STC_MASK
);
6635 /* For SISO MCS use STBC if possible */
6636 if (is_mcs_rate(rspec
[k
])
6637 && BRCMS_STF_SS_STBC_TX(wlc
, scb
)) {
6640 /* Nss for single stream is always 1 */
6642 rspec
[k
] |= (PHY_TXC1_MODE_STBC
<<
6644 (stc
<< RSPEC_STC_SHIFT
);
6647 (phyctl1_stf
<< RSPEC_STF_SHIFT
);
6651 * Is the phy configured to use 40MHZ frames? If
6652 * so then pick the desired txbw
6654 if (brcms_chspec_bw(wlc
->chanspec
) == BRCMS_40_MHZ
) {
6655 /* default txbw is 20in40 SB */
6656 mimo_ctlchbw
= mimo_txbw
=
6657 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6659 ? PHY_TXC1_BW_20MHZ_UP
: PHY_TXC1_BW_20MHZ
;
6661 if (is_mcs_rate(rspec
[k
])) {
6662 /* mcs 32 must be 40b/w DUP */
6663 if ((rspec
[k
] & RSPEC_RATE_MASK
)
6666 PHY_TXC1_BW_40MHZ_DUP
;
6668 } else if (wlc
->mimo_40txbw
!= AUTO
)
6669 mimo_txbw
= wlc
->mimo_40txbw
;
6670 /* else check if dst is using 40 Mhz */
6671 else if (scb
->flags
& SCB_IS40
)
6672 mimo_txbw
= PHY_TXC1_BW_40MHZ
;
6673 } else if (is_ofdm_rate(rspec
[k
])) {
6674 if (wlc
->ofdm_40txbw
!= AUTO
)
6675 mimo_txbw
= wlc
->ofdm_40txbw
;
6676 } else if (wlc
->cck_40txbw
!= AUTO
) {
6677 mimo_txbw
= wlc
->cck_40txbw
;
6681 * mcs32 is 40 b/w only.
6682 * This is possible for probe packets on
6685 if ((rspec
[k
] & RSPEC_RATE_MASK
) == 32)
6687 rspec
[k
] = RSPEC_MIMORATE
;
6689 mimo_txbw
= PHY_TXC1_BW_20MHZ
;
6692 /* Set channel width */
6693 rspec
[k
] &= ~RSPEC_BW_MASK
;
6694 if ((k
== 0) || ((k
> 0) && is_mcs_rate(rspec
[k
])))
6695 rspec
[k
] |= (mimo_txbw
<< RSPEC_BW_SHIFT
);
6697 rspec
[k
] |= (mimo_ctlchbw
<< RSPEC_BW_SHIFT
);
6699 /* Disable short GI, not supported yet */
6700 rspec
[k
] &= ~RSPEC_SHORT_GI
;
6702 mimo_preamble_type
= BRCMS_MM_PREAMBLE
;
6703 if (txrate
[k
]->flags
& IEEE80211_TX_RC_GREEN_FIELD
)
6704 mimo_preamble_type
= BRCMS_GF_PREAMBLE
;
6706 if ((txrate
[k
]->flags
& IEEE80211_TX_RC_MCS
)
6707 && (!is_mcs_rate(rspec
[k
]))) {
6708 brcms_err(wlc
->hw
->d11core
,
6709 "wl%d: %s: IEEE80211_TX_"
6710 "RC_MCS != is_mcs_rate(rspec)\n",
6711 wlc
->pub
->unit
, __func__
);
6714 if (is_mcs_rate(rspec
[k
])) {
6715 preamble_type
[k
] = mimo_preamble_type
;
6718 * if SGI is selected, then forced mm
6721 if ((rspec
[k
] & RSPEC_SHORT_GI
)
6722 && is_single_stream(rspec
[k
] &
6724 preamble_type
[k
] = BRCMS_MM_PREAMBLE
;
6727 /* should be better conditionalized */
6728 if (!is_mcs_rate(rspec
[0])
6729 && (tx_info
->control
.rates
[0].
6730 flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
))
6731 preamble_type
[k
] = BRCMS_SHORT_PREAMBLE
;
6734 for (k
= 0; k
< hw
->max_rates
; k
++) {
6735 /* Set ctrlchbw as 20Mhz */
6736 rspec
[k
] &= ~RSPEC_BW_MASK
;
6737 rspec
[k
] |= (PHY_TXC1_BW_20MHZ
<< RSPEC_BW_SHIFT
);
6739 /* for nphy, stf of ofdm frames must follow policies */
6740 if (BRCMS_ISNPHY(wlc
->band
) && is_ofdm_rate(rspec
[k
])) {
6741 rspec
[k
] &= ~RSPEC_STF_MASK
;
6742 rspec
[k
] |= phyctl1_stf
<< RSPEC_STF_SHIFT
;
6747 /* Reset these for use with AMPDU's */
6748 txrate
[0]->count
= 0;
6749 txrate
[1]->count
= 0;
6751 /* (2) PROTECTION, may change rspec */
6752 if ((ieee80211_is_data(h
->frame_control
) ||
6753 ieee80211_is_mgmt(h
->frame_control
)) &&
6754 (phylen
> wlc
->RTSThresh
) && !is_multicast_ether_addr(h
->addr1
))
6757 /* (3) PLCP: determine PLCP header and MAC duration,
6758 * fill struct d11txh */
6759 brcms_c_compute_plcp(wlc
, rspec
[0], phylen
, plcp
);
6760 brcms_c_compute_plcp(wlc
, rspec
[1], phylen
, plcp_fallback
);
6761 memcpy(&txh
->FragPLCPFallback
,
6762 plcp_fallback
, sizeof(txh
->FragPLCPFallback
));
6764 /* Length field now put in CCK FBR CRC field */
6765 if (is_cck_rate(rspec
[1])) {
6766 txh
->FragPLCPFallback
[4] = phylen
& 0xff;
6767 txh
->FragPLCPFallback
[5] = (phylen
& 0xff00) >> 8;
6770 /* MIMO-RATE: need validation ?? */
6771 mainrates
= is_ofdm_rate(rspec
[0]) ?
6772 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr
*) plcp
) :
6775 /* DUR field for main rate */
6776 if (!ieee80211_is_pspoll(h
->frame_control
) &&
6777 !is_multicast_ether_addr(h
->addr1
) && !use_rifs
) {
6779 brcms_c_compute_frame_dur(wlc
, rspec
[0], preamble_type
[0],
6781 h
->duration_id
= cpu_to_le16(durid
);
6782 } else if (use_rifs
) {
6783 /* NAV protect to end of next max packet size */
6785 (u16
) brcms_c_calc_frame_time(wlc
, rspec
[0],
6787 DOT11_MAX_FRAG_LEN
);
6788 durid
+= RIFS_11N_TIME
;
6789 h
->duration_id
= cpu_to_le16(durid
);
6792 /* DUR field for fallback rate */
6793 if (ieee80211_is_pspoll(h
->frame_control
))
6794 txh
->FragDurFallback
= h
->duration_id
;
6795 else if (is_multicast_ether_addr(h
->addr1
) || use_rifs
)
6796 txh
->FragDurFallback
= 0;
6798 durid
= brcms_c_compute_frame_dur(wlc
, rspec
[1],
6799 preamble_type
[1], next_frag_len
);
6800 txh
->FragDurFallback
= cpu_to_le16(durid
);
6803 /* (4) MAC-HDR: MacTxControlLow */
6805 mcl
|= TXC_STARTMSDU
;
6807 if (!is_multicast_ether_addr(h
->addr1
))
6808 mcl
|= TXC_IMMEDACK
;
6810 if (wlc
->band
->bandtype
== BRCM_BAND_5G
)
6811 mcl
|= TXC_FREQBAND_5G
;
6813 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc
->band
->pi
)))
6816 /* set AMIC bit if using hardware TKIP MIC */
6820 txh
->MacTxControlLow
= cpu_to_le16(mcl
);
6822 /* MacTxControlHigh */
6825 /* Set fallback rate preamble type */
6826 if ((preamble_type
[1] == BRCMS_SHORT_PREAMBLE
) ||
6827 (preamble_type
[1] == BRCMS_GF_PREAMBLE
)) {
6828 if (rspec2rate(rspec
[1]) != BRCM_RATE_1M
)
6829 mch
|= TXC_PREAMBLE_DATA_FB_SHORT
;
6832 /* MacFrameControl */
6833 memcpy(&txh
->MacFrameControl
, &h
->frame_control
, sizeof(u16
));
6834 txh
->TxFesTimeNormal
= cpu_to_le16(0);
6836 txh
->TxFesTimeFallback
= cpu_to_le16(0);
6839 memcpy(&txh
->TxFrameRA
, &h
->addr1
, ETH_ALEN
);
6842 txh
->TxFrameID
= cpu_to_le16(frameid
);
6845 * TxStatus, Note the case of recreating the first frag of a suppressed
6846 * frame then we may need to reset the retry cnt's via the status reg
6848 txh
->TxStatus
= cpu_to_le16(status
);
6851 * extra fields for ucode AMPDU aggregation, the new fields are added to
6852 * the END of previous structure so that it's compatible in driver.
6854 txh
->MaxNMpdus
= cpu_to_le16(0);
6855 txh
->MaxABytes_MRT
= cpu_to_le16(0);
6856 txh
->MaxABytes_FBR
= cpu_to_le16(0);
6857 txh
->MinMBytes
= cpu_to_le16(0);
6859 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6860 * furnish struct d11txh */
6861 /* RTS PLCP header and RTS frame */
6862 if (use_rts
|| use_cts
) {
6863 if (use_rts
&& use_cts
)
6866 for (k
= 0; k
< 2; k
++) {
6867 rts_rspec
[k
] = brcms_c_rspec_to_rts_rspec(wlc
, rspec
[k
],
6872 if (!is_ofdm_rate(rts_rspec
[0]) &&
6873 !((rspec2rate(rts_rspec
[0]) == BRCM_RATE_1M
) ||
6874 (wlc
->PLCPHdr_override
== BRCMS_PLCP_LONG
))) {
6875 rts_preamble_type
[0] = BRCMS_SHORT_PREAMBLE
;
6876 mch
|= TXC_PREAMBLE_RTS_MAIN_SHORT
;
6879 if (!is_ofdm_rate(rts_rspec
[1]) &&
6880 !((rspec2rate(rts_rspec
[1]) == BRCM_RATE_1M
) ||
6881 (wlc
->PLCPHdr_override
== BRCMS_PLCP_LONG
))) {
6882 rts_preamble_type
[1] = BRCMS_SHORT_PREAMBLE
;
6883 mch
|= TXC_PREAMBLE_RTS_FB_SHORT
;
6886 /* RTS/CTS additions to MacTxControlLow */
6888 txh
->MacTxControlLow
|= cpu_to_le16(TXC_SENDCTS
);
6890 txh
->MacTxControlLow
|= cpu_to_le16(TXC_SENDRTS
);
6891 txh
->MacTxControlLow
|= cpu_to_le16(TXC_LONGFRAME
);
6894 /* RTS PLCP header */
6895 rts_plcp
= txh
->RTSPhyHeader
;
6897 rts_phylen
= DOT11_CTS_LEN
+ FCS_LEN
;
6899 rts_phylen
= DOT11_RTS_LEN
+ FCS_LEN
;
6901 brcms_c_compute_plcp(wlc
, rts_rspec
[0], rts_phylen
, rts_plcp
);
6903 /* fallback rate version of RTS PLCP header */
6904 brcms_c_compute_plcp(wlc
, rts_rspec
[1], rts_phylen
,
6906 memcpy(&txh
->RTSPLCPFallback
, rts_plcp_fallback
,
6907 sizeof(txh
->RTSPLCPFallback
));
6909 /* RTS frame fields... */
6910 rts
= (struct ieee80211_rts
*)&txh
->rts_frame
;
6912 durid
= brcms_c_compute_rtscts_dur(wlc
, use_cts
, rts_rspec
[0],
6913 rspec
[0], rts_preamble_type
[0],
6914 preamble_type
[0], phylen
, false);
6915 rts
->duration
= cpu_to_le16(durid
);
6916 /* fallback rate version of RTS DUR field */
6917 durid
= brcms_c_compute_rtscts_dur(wlc
, use_cts
,
6918 rts_rspec
[1], rspec
[1],
6919 rts_preamble_type
[1],
6920 preamble_type
[1], phylen
, false);
6921 txh
->RTSDurFallback
= cpu_to_le16(durid
);
6924 rts
->frame_control
= cpu_to_le16(IEEE80211_FTYPE_CTL
|
6925 IEEE80211_STYPE_CTS
);
6927 memcpy(&rts
->ra
, &h
->addr2
, ETH_ALEN
);
6929 rts
->frame_control
= cpu_to_le16(IEEE80211_FTYPE_CTL
|
6930 IEEE80211_STYPE_RTS
);
6932 memcpy(&rts
->ra
, &h
->addr1
, 2 * ETH_ALEN
);
6936 * low 8 bits: main frag rate/mcs,
6937 * high 8 bits: rts/cts rate/mcs
6939 mainrates
|= (is_ofdm_rate(rts_rspec
[0]) ?
6941 (struct ofdm_phy_hdr
*) rts_plcp
) :
6944 memset((char *)txh
->RTSPhyHeader
, 0, D11_PHY_HDR_LEN
);
6945 memset((char *)&txh
->rts_frame
, 0,
6946 sizeof(struct ieee80211_rts
));
6947 memset((char *)txh
->RTSPLCPFallback
, 0,
6948 sizeof(txh
->RTSPLCPFallback
));
6949 txh
->RTSDurFallback
= 0;
6952 #ifdef SUPPORT_40MHZ
6953 /* add null delimiter count */
6954 if ((tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) && is_mcs_rate(rspec
))
6955 txh
->RTSPLCPFallback
[AMPDU_FBR_NULL_DELIM
] =
6956 brcm_c_ampdu_null_delim_cnt(wlc
->ampdu
, scb
, rspec
, phylen
);
6961 * Now that RTS/RTS FB preamble types are updated, write
6964 txh
->MacTxControlHigh
= cpu_to_le16(mch
);
6967 * MainRates (both the rts and frag plcp rates have
6968 * been calculated now)
6970 txh
->MainRates
= cpu_to_le16(mainrates
);
6972 /* XtraFrameTypes */
6973 xfts
= frametype(rspec
[1], wlc
->mimoft
);
6974 xfts
|= (frametype(rts_rspec
[0], wlc
->mimoft
) << XFTS_RTS_FT_SHIFT
);
6975 xfts
|= (frametype(rts_rspec
[1], wlc
->mimoft
) << XFTS_FBRRTS_FT_SHIFT
);
6976 xfts
|= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc
->band
->pi
)) <<
6978 txh
->XtraFrameTypes
= cpu_to_le16(xfts
);
6980 /* PhyTxControlWord */
6981 phyctl
= frametype(rspec
[0], wlc
->mimoft
);
6982 if ((preamble_type
[0] == BRCMS_SHORT_PREAMBLE
) ||
6983 (preamble_type
[0] == BRCMS_GF_PREAMBLE
)) {
6984 if (rspec2rate(rspec
[0]) != BRCM_RATE_1M
)
6985 phyctl
|= PHY_TXC_SHORT_HDR
;
6988 /* phytxant is properly bit shifted */
6989 phyctl
|= brcms_c_stf_d11hdrs_phyctl_txant(wlc
, rspec
[0]);
6990 txh
->PhyTxControlWord
= cpu_to_le16(phyctl
);
6992 /* PhyTxControlWord_1 */
6993 if (BRCMS_PHY_11N_CAP(wlc
->band
)) {
6996 phyctl1
= brcms_c_phytxctl1_calc(wlc
, rspec
[0]);
6997 txh
->PhyTxControlWord_1
= cpu_to_le16(phyctl1
);
6998 phyctl1
= brcms_c_phytxctl1_calc(wlc
, rspec
[1]);
6999 txh
->PhyTxControlWord_1_Fbr
= cpu_to_le16(phyctl1
);
7001 if (use_rts
|| use_cts
) {
7002 phyctl1
= brcms_c_phytxctl1_calc(wlc
, rts_rspec
[0]);
7003 txh
->PhyTxControlWord_1_Rts
= cpu_to_le16(phyctl1
);
7004 phyctl1
= brcms_c_phytxctl1_calc(wlc
, rts_rspec
[1]);
7005 txh
->PhyTxControlWord_1_FbrRts
= cpu_to_le16(phyctl1
);
7009 * For mcs frames, if mixedmode(overloaded with long preamble)
7010 * is going to be set, fill in non-zero MModeLen and/or
7011 * MModeFbrLen it will be unnecessary if they are separated
7013 if (is_mcs_rate(rspec
[0]) &&
7014 (preamble_type
[0] == BRCMS_MM_PREAMBLE
)) {
7016 brcms_c_calc_lsig_len(wlc
, rspec
[0], phylen
);
7017 txh
->MModeLen
= cpu_to_le16(mmodelen
);
7020 if (is_mcs_rate(rspec
[1]) &&
7021 (preamble_type
[1] == BRCMS_MM_PREAMBLE
)) {
7023 brcms_c_calc_lsig_len(wlc
, rspec
[1], phylen
);
7024 txh
->MModeFbrLen
= cpu_to_le16(mmodefbrlen
);
7028 ac
= skb_get_queue_mapping(p
);
7029 if ((scb
->flags
& SCB_WMECAP
) && qos
&& wlc
->edcf_txop
[ac
]) {
7030 uint frag_dur
, dur
, dur_fallback
;
7032 /* WME: Update TXOP threshold */
7033 if (!(tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) && frag
== 0) {
7035 brcms_c_calc_frame_time(wlc
, rspec
[0],
7036 preamble_type
[0], phylen
);
7039 /* 1 RTS or CTS-to-self frame */
7041 brcms_c_calc_cts_time(wlc
, rts_rspec
[0],
7042 rts_preamble_type
[0]);
7044 brcms_c_calc_cts_time(wlc
, rts_rspec
[1],
7045 rts_preamble_type
[1]);
7046 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
7047 dur
+= le16_to_cpu(rts
->duration
);
7049 le16_to_cpu(txh
->RTSDurFallback
);
7050 } else if (use_rifs
) {
7054 /* frame + SIFS + ACK */
7057 brcms_c_compute_frame_dur(wlc
, rspec
[0],
7058 preamble_type
[0], 0);
7061 brcms_c_calc_frame_time(wlc
, rspec
[1],
7065 brcms_c_compute_frame_dur(wlc
, rspec
[1],
7066 preamble_type
[1], 0);
7068 /* NEED to set TxFesTimeNormal (hard) */
7069 txh
->TxFesTimeNormal
= cpu_to_le16((u16
) dur
);
7071 * NEED to set fallback rate version of
7072 * TxFesTimeNormal (hard)
7074 txh
->TxFesTimeFallback
=
7075 cpu_to_le16((u16
) dur_fallback
);
7078 * update txop byte threshold (txop minus intraframe
7081 if (wlc
->edcf_txop
[ac
] >= (dur
- frag_dur
)) {
7085 brcms_c_calc_frame_len(wlc
,
7086 rspec
[0], preamble_type
[0],
7087 (wlc
->edcf_txop
[ac
] -
7089 /* range bound the fragthreshold */
7090 if (newfragthresh
< DOT11_MIN_FRAG_LEN
)
7093 else if (newfragthresh
>
7094 wlc
->usr_fragthresh
)
7096 wlc
->usr_fragthresh
;
7097 /* update the fragthresh and do txc update */
7098 if (wlc
->fragthresh
[queue
] !=
7099 (u16
) newfragthresh
)
7100 wlc
->fragthresh
[queue
] =
7101 (u16
) newfragthresh
;
7103 brcms_err(wlc
->hw
->d11core
,
7104 "wl%d: %s txop invalid "
7106 wlc
->pub
->unit
, fifo_names
[queue
],
7107 rspec2rate(rspec
[0]));
7110 if (dur
> wlc
->edcf_txop
[ac
])
7111 brcms_err(wlc
->hw
->d11core
,
7112 "wl%d: %s: %s txop "
7113 "exceeded phylen %d/%d dur %d/%d\n",
7114 wlc
->pub
->unit
, __func__
,
7116 phylen
, wlc
->fragthresh
[queue
],
7117 dur
, wlc
->edcf_txop
[ac
]);
7124 static int brcms_c_tx(struct brcms_c_info
*wlc
, struct sk_buff
*skb
)
7126 struct dma_pub
*dma
;
7127 int fifo
, ret
= -ENOSPC
;
7129 u16 frameid
= INVALIDFID
;
7131 fifo
= brcms_ac_to_fifo(skb_get_queue_mapping(skb
));
7132 dma
= wlc
->hw
->di
[fifo
];
7133 txh
= (struct d11txh
*)(skb
->data
);
7135 if (dma
->txavail
== 0) {
7137 * We sometimes get a frame from mac80211 after stopping
7138 * the queues. This only ever seems to be a single frame
7139 * and is seems likely to be a race. TX_HEADROOM should
7140 * ensure that we have enough space to handle these stray
7141 * packets, so warn if there isn't. If we're out of space
7142 * in the tx ring and the tx queue isn't stopped then
7143 * we've really got a bug; warn loudly if that happens.
7145 brcms_warn(wlc
->hw
->d11core
,
7146 "Received frame for tx with no space in DMA ring\n");
7147 WARN_ON(!ieee80211_queue_stopped(wlc
->pub
->ieee_hw
,
7148 skb_get_queue_mapping(skb
)));
7152 /* When a BC/MC frame is being committed to the BCMC fifo
7153 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
7155 if (fifo
== TX_BCMC_FIFO
)
7156 frameid
= le16_to_cpu(txh
->TxFrameID
);
7158 /* Commit BCMC sequence number in the SHM frame ID location */
7159 if (frameid
!= INVALIDFID
) {
7161 * To inform the ucode of the last mcast frame posted
7162 * so that it can clear moredata bit
7164 brcms_b_write_shm(wlc
->hw
, M_BCMC_FID
, frameid
);
7167 ret
= brcms_c_txfifo(wlc
, fifo
, skb
);
7169 * The only reason for brcms_c_txfifo to fail is because
7170 * there weren't any DMA descriptors, but we've already
7171 * checked for that. So if it does fail yell loudly.
7178 void brcms_c_sendpkt_mac80211(struct brcms_c_info
*wlc
, struct sk_buff
*sdu
,
7179 struct ieee80211_hw
*hw
)
7182 struct scb
*scb
= &wlc
->pri_scb
;
7184 fifo
= brcms_ac_to_fifo(skb_get_queue_mapping(sdu
));
7185 if (brcms_c_d11hdrs_mac80211(wlc
, hw
, sdu
, scb
, 0, 1, fifo
, 0))
7187 if (brcms_c_tx(wlc
, sdu
))
7188 dev_kfree_skb_any(sdu
);
7192 brcms_c_txfifo(struct brcms_c_info
*wlc
, uint fifo
, struct sk_buff
*p
)
7194 struct dma_pub
*dma
= wlc
->hw
->di
[fifo
];
7198 ret
= dma_txfast(wlc
, dma
, p
);
7200 wiphy_err(wlc
->wiphy
, "txfifo: fatal, toss frames !!!\n");
7203 * Stop queue if DMA ring is full. Reserve some free descriptors,
7204 * as we sometimes receive a frame from mac80211 after the queues
7207 queue
= skb_get_queue_mapping(p
);
7208 if (dma
->txavail
<= TX_HEADROOM
&& fifo
< TX_BCMC_FIFO
&&
7209 !ieee80211_queue_stopped(wlc
->pub
->ieee_hw
, queue
))
7210 ieee80211_stop_queue(wlc
->pub
->ieee_hw
, queue
);
7216 brcms_c_rspec_to_rts_rspec(struct brcms_c_info
*wlc
, u32 rspec
,
7217 bool use_rspec
, u16 mimo_ctlchbw
)
7222 /* use frame rate as rts rate */
7224 else if (wlc
->band
->gmode
&& wlc
->protection
->_g
&& !is_cck_rate(rspec
))
7225 /* Use 11Mbps as the g protection RTS target rate and fallback.
7226 * Use the brcms_basic_rate() lookup to find the best basic rate
7227 * under the target in case 11 Mbps is not Basic.
7228 * 6 and 9 Mbps are not usually selected by rate selection, but
7229 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
7232 rts_rspec
= brcms_basic_rate(wlc
, BRCM_RATE_11M
);
7234 /* calculate RTS rate and fallback rate based on the frame rate
7235 * RTS must be sent at a basic rate since it is a
7236 * control frame, sec 9.6 of 802.11 spec
7238 rts_rspec
= brcms_basic_rate(wlc
, rspec
);
7240 if (BRCMS_PHY_11N_CAP(wlc
->band
)) {
7241 /* set rts txbw to correct side band */
7242 rts_rspec
&= ~RSPEC_BW_MASK
;
7245 * if rspec/rspec_fallback is 40MHz, then send RTS on both
7246 * 20MHz channel (DUP), otherwise send RTS on control channel
7248 if (rspec_is40mhz(rspec
) && !is_cck_rate(rts_rspec
))
7249 rts_rspec
|= (PHY_TXC1_BW_40MHZ_DUP
<< RSPEC_BW_SHIFT
);
7251 rts_rspec
|= (mimo_ctlchbw
<< RSPEC_BW_SHIFT
);
7253 /* pick siso/cdd as default for ofdm */
7254 if (is_ofdm_rate(rts_rspec
)) {
7255 rts_rspec
&= ~RSPEC_STF_MASK
;
7256 rts_rspec
|= (wlc
->stf
->ss_opmode
<< RSPEC_STF_SHIFT
);
7262 /* Update beacon listen interval in shared memory */
7263 static void brcms_c_bcn_li_upd(struct brcms_c_info
*wlc
)
7265 /* wake up every DTIM is the default */
7266 if (wlc
->bcn_li_dtim
== 1)
7267 brcms_b_write_shm(wlc
->hw
, M_BCN_LI
, 0);
7269 brcms_b_write_shm(wlc
->hw
, M_BCN_LI
,
7270 (wlc
->bcn_li_dtim
<< 8) | wlc
->bcn_li_bcn
);
7274 brcms_b_read_tsf(struct brcms_hardware
*wlc_hw
, u32
*tsf_l_ptr
,
7277 struct bcma_device
*core
= wlc_hw
->d11core
;
7279 /* read the tsf timer low, then high to get an atomic read */
7280 *tsf_l_ptr
= bcma_read32(core
, D11REGOFFS(tsf_timerlow
));
7281 *tsf_h_ptr
= bcma_read32(core
, D11REGOFFS(tsf_timerhigh
));
7285 * recover 64bit TSF value from the 16bit TSF value in the rx header
7286 * given the assumption that the TSF passed in header is within 65ms
7287 * of the current tsf.
7290 * 3.......6.......8.......0.......2.......4.......6.......8......0
7291 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7293 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7294 * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7295 * receive call sequence after rx interrupt. Only the higher 16 bits
7296 * are used. Finally, the tsf_h is read from the tsf register.
7298 static u64
brcms_c_recover_tsf64(struct brcms_c_info
*wlc
,
7299 struct d11rxhdr
*rxh
)
7302 u16 rx_tsf_0_15
, rx_tsf_16_31
;
7304 brcms_b_read_tsf(wlc
->hw
, &tsf_l
, &tsf_h
);
7306 rx_tsf_16_31
= (u16
)(tsf_l
>> 16);
7307 rx_tsf_0_15
= rxh
->RxTSFTime
;
7310 * a greater tsf time indicates the low 16 bits of
7311 * tsf_l wrapped, so decrement the high 16 bits.
7313 if ((u16
)tsf_l
< rx_tsf_0_15
) {
7315 if (rx_tsf_16_31
== 0xffff)
7319 return ((u64
)tsf_h
<< 32) | (((u32
)rx_tsf_16_31
<< 16) + rx_tsf_0_15
);
7323 prep_mac80211_status(struct brcms_c_info
*wlc
, struct d11rxhdr
*rxh
,
7325 struct ieee80211_rx_status
*rx_status
)
7330 unsigned char *plcp
;
7332 /* fill in TSF and flag its presence */
7333 rx_status
->mactime
= brcms_c_recover_tsf64(wlc
, rxh
);
7334 rx_status
->flag
|= RX_FLAG_MACTIME_MPDU
;
7336 channel
= BRCMS_CHAN_CHANNEL(rxh
->RxChan
);
7339 channel
> 14 ? IEEE80211_BAND_5GHZ
: IEEE80211_BAND_2GHZ
;
7341 ieee80211_channel_to_frequency(channel
, rx_status
->band
);
7343 rx_status
->signal
= wlc_phy_rssi_compute(wlc
->hw
->band
->pi
, rxh
);
7347 rx_status
->antenna
=
7348 (rxh
->PhyRxStatus_0
& PRXS0_RXANT_UPSUBBAND
) ? 1 : 0;
7352 rspec
= brcms_c_compute_rspec(rxh
, plcp
);
7353 if (is_mcs_rate(rspec
)) {
7354 rx_status
->rate_idx
= rspec
& RSPEC_RATE_MASK
;
7355 rx_status
->flag
|= RX_FLAG_HT
;
7356 if (rspec_is40mhz(rspec
))
7357 rx_status
->flag
|= RX_FLAG_40MHZ
;
7359 switch (rspec2rate(rspec
)) {
7361 rx_status
->rate_idx
= 0;
7364 rx_status
->rate_idx
= 1;
7367 rx_status
->rate_idx
= 2;
7370 rx_status
->rate_idx
= 3;
7373 rx_status
->rate_idx
= 4;
7376 rx_status
->rate_idx
= 5;
7379 rx_status
->rate_idx
= 6;
7382 rx_status
->rate_idx
= 7;
7385 rx_status
->rate_idx
= 8;
7388 rx_status
->rate_idx
= 9;
7391 rx_status
->rate_idx
= 10;
7394 rx_status
->rate_idx
= 11;
7397 brcms_err(wlc
->hw
->d11core
,
7398 "%s: Unknown rate\n", __func__
);
7402 * For 5GHz, we should decrease the index as it is
7403 * a subset of the 2.4G rates. See bitrates field
7404 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7406 if (rx_status
->band
== IEEE80211_BAND_5GHZ
)
7407 rx_status
->rate_idx
-= BRCMS_LEGACY_5G_RATE_OFFSET
;
7409 /* Determine short preamble and rate_idx */
7411 if (is_cck_rate(rspec
)) {
7412 if (rxh
->PhyRxStatus_0
& PRXS0_SHORTH
)
7413 rx_status
->flag
|= RX_FLAG_SHORTPRE
;
7414 } else if (is_ofdm_rate(rspec
)) {
7415 rx_status
->flag
|= RX_FLAG_SHORTPRE
;
7417 brcms_err(wlc
->hw
->d11core
, "%s: Unknown modulation\n",
7422 if (plcp3_issgi(plcp
[3]))
7423 rx_status
->flag
|= RX_FLAG_SHORT_GI
;
7425 if (rxh
->RxStatus1
& RXS_DECERR
) {
7426 rx_status
->flag
|= RX_FLAG_FAILED_PLCP_CRC
;
7427 brcms_err(wlc
->hw
->d11core
, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
7430 if (rxh
->RxStatus1
& RXS_FCSERR
) {
7431 rx_status
->flag
|= RX_FLAG_FAILED_FCS_CRC
;
7432 brcms_err(wlc
->hw
->d11core
, "%s: RX_FLAG_FAILED_FCS_CRC\n",
7438 brcms_c_recvctl(struct brcms_c_info
*wlc
, struct d11rxhdr
*rxh
,
7442 struct ieee80211_rx_status rx_status
;
7443 struct ieee80211_hdr
*hdr
;
7445 memset(&rx_status
, 0, sizeof(rx_status
));
7446 prep_mac80211_status(wlc
, rxh
, p
, &rx_status
);
7448 /* mac header+body length, exclude CRC and plcp header */
7449 len_mpdu
= p
->len
- D11_PHY_HDR_LEN
- FCS_LEN
;
7450 skb_pull(p
, D11_PHY_HDR_LEN
);
7451 __skb_trim(p
, len_mpdu
);
7453 /* unmute transmit */
7454 if (wlc
->hw
->suspended_fifos
) {
7455 hdr
= (struct ieee80211_hdr
*)p
->data
;
7456 if (ieee80211_is_beacon(hdr
->frame_control
))
7457 brcms_b_mute(wlc
->hw
, false);
7460 memcpy(IEEE80211_SKB_RXCB(p
), &rx_status
, sizeof(rx_status
));
7461 ieee80211_rx_irqsafe(wlc
->pub
->ieee_hw
, p
);
7464 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7465 * number of bytes goes in the length field
7467 * Formula given by HT PHY Spec v 1.13
7468 * len = 3(nsyms + nstream + 3) - 3
7471 brcms_c_calc_lsig_len(struct brcms_c_info
*wlc
, u32 ratespec
,
7474 uint nsyms
, len
= 0, kNdps
;
7476 brcms_dbg_mac80211(wlc
->hw
->d11core
, "wl%d: rate %d, len%d\n",
7477 wlc
->pub
->unit
, rspec2rate(ratespec
), mac_len
);
7479 if (is_mcs_rate(ratespec
)) {
7480 uint mcs
= ratespec
& RSPEC_RATE_MASK
;
7481 int tot_streams
= (mcs_2_txstreams(mcs
) + 1) +
7482 rspec_stc(ratespec
);
7485 * the payload duration calculation matches that
7488 /* 1000Ndbps = kbps * 4 */
7489 kNdps
= mcs_2_rate(mcs
, rspec_is40mhz(ratespec
),
7490 rspec_issgi(ratespec
)) * 4;
7492 if (rspec_stc(ratespec
) == 0)
7494 CEIL((APHY_SERVICE_NBITS
+ 8 * mac_len
+
7495 APHY_TAIL_NBITS
) * 1000, kNdps
);
7497 /* STBC needs to have even number of symbols */
7500 CEIL((APHY_SERVICE_NBITS
+ 8 * mac_len
+
7501 APHY_TAIL_NBITS
) * 1000, 2 * kNdps
);
7503 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7504 nsyms
+= (tot_streams
+ 3);
7506 * 3 bytes/symbol @ legacy 6Mbps rate
7507 * (-3) excluding service bits and tail bits
7509 len
= (3 * nsyms
) - 3;
7516 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info
*wlc
, uint frame_len
)
7518 const struct brcms_c_rateset
*rs_dflt
;
7519 struct brcms_c_rateset rs
;
7522 u8 plcp
[D11_PHY_HDR_LEN
];
7526 sifs
= get_sifs(wlc
->band
);
7528 rs_dflt
= brcms_c_rateset_get_hwrs(wlc
);
7530 brcms_c_rateset_copy(rs_dflt
, &rs
);
7531 brcms_c_rateset_mcs_upd(&rs
, wlc
->stf
->txstreams
);
7534 * walk the phy rate table and update MAC core SHM
7535 * basic rate table entries
7537 for (i
= 0; i
< rs
.count
; i
++) {
7538 rate
= rs
.rates
[i
] & BRCMS_RATE_MASK
;
7540 entry_ptr
= brcms_b_rate_shm_offset(wlc
->hw
, rate
);
7542 /* Calculate the Probe Response PLCP for the given rate */
7543 brcms_c_compute_plcp(wlc
, rate
, frame_len
, plcp
);
7546 * Calculate the duration of the Probe Response
7547 * frame plus SIFS for the MAC
7549 dur
= (u16
) brcms_c_calc_frame_time(wlc
, rate
,
7550 BRCMS_LONG_PREAMBLE
, frame_len
);
7553 /* Update the SHM Rate Table entry Probe Response values */
7554 brcms_b_write_shm(wlc
->hw
, entry_ptr
+ M_RT_PRS_PLCP_POS
,
7555 (u16
) (plcp
[0] + (plcp
[1] << 8)));
7556 brcms_b_write_shm(wlc
->hw
, entry_ptr
+ M_RT_PRS_PLCP_POS
+ 2,
7557 (u16
) (plcp
[2] + (plcp
[3] << 8)));
7558 brcms_b_write_shm(wlc
->hw
, entry_ptr
+ M_RT_PRS_DUR_POS
, dur
);
7562 /* Max buffering needed for beacon template/prb resp template is 142 bytes.
7564 * PLCP header is 6 bytes.
7565 * 802.11 A3 header is 24 bytes.
7566 * Max beacon frame body template length is 112 bytes.
7567 * Max probe resp frame body template length is 110 bytes.
7569 * *len on input contains the max length of the packet available.
7571 * The *len value is set to the number of bytes in buf used, and starts
7572 * with the PLCP and included up to, but not including, the 4 byte FCS.
7575 brcms_c_bcn_prb_template(struct brcms_c_info
*wlc
, u16 type
,
7577 struct brcms_bss_cfg
*cfg
, u16
*buf
, int *len
)
7579 static const u8 ether_bcast
[ETH_ALEN
] = {255, 255, 255, 255, 255, 255};
7580 struct cck_phy_hdr
*plcp
;
7581 struct ieee80211_mgmt
*h
;
7582 int hdr_len
, body_len
;
7584 hdr_len
= D11_PHY_HDR_LEN
+ DOT11_MAC_HDR_LEN
;
7586 /* calc buffer size provided for frame body */
7587 body_len
= *len
- hdr_len
;
7588 /* return actual size */
7589 *len
= hdr_len
+ body_len
;
7591 /* format PHY and MAC headers */
7592 memset((char *)buf
, 0, hdr_len
);
7594 plcp
= (struct cck_phy_hdr
*) buf
;
7597 * PLCP for Probe Response frames are filled in from
7600 if (type
== IEEE80211_STYPE_BEACON
)
7602 brcms_c_compute_plcp(wlc
, bcn_rspec
,
7603 (DOT11_MAC_HDR_LEN
+ body_len
+ FCS_LEN
),
7606 /* "Regular" and 16 MBSS but not for 4 MBSS */
7607 /* Update the phytxctl for the beacon based on the rspec */
7608 brcms_c_beacon_phytxctl_txant_upd(wlc
, bcn_rspec
);
7610 h
= (struct ieee80211_mgmt
*)&plcp
[1];
7612 /* fill in 802.11 header */
7613 h
->frame_control
= cpu_to_le16(IEEE80211_FTYPE_MGMT
| type
);
7615 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
7616 /* A1 filled in by MAC for prb resp, broadcast for bcn */
7617 if (type
== IEEE80211_STYPE_BEACON
)
7618 memcpy(&h
->da
, ðer_bcast
, ETH_ALEN
);
7619 memcpy(&h
->sa
, &cfg
->cur_etheraddr
, ETH_ALEN
);
7620 memcpy(&h
->bssid
, &cfg
->BSSID
, ETH_ALEN
);
7622 /* SEQ filled in by MAC */
7625 int brcms_c_get_header_len(void)
7631 * Update all beacons for the system.
7633 void brcms_c_update_beacon(struct brcms_c_info
*wlc
)
7635 struct brcms_bss_cfg
*bsscfg
= wlc
->bsscfg
;
7637 if (bsscfg
->up
&& !bsscfg
->BSS
)
7638 /* Clear the soft intmask */
7639 wlc
->defmacintmask
&= ~MI_BCNTPL
;
7642 /* Write ssid into shared memory */
7644 brcms_c_shm_ssid_upd(struct brcms_c_info
*wlc
, struct brcms_bss_cfg
*cfg
)
7646 u8
*ssidptr
= cfg
->SSID
;
7648 u8 ssidbuf
[IEEE80211_MAX_SSID_LEN
];
7650 /* padding the ssid with zero and copy it into shm */
7651 memset(ssidbuf
, 0, IEEE80211_MAX_SSID_LEN
);
7652 memcpy(ssidbuf
, ssidptr
, cfg
->SSID_len
);
7654 brcms_c_copyto_shm(wlc
, base
, ssidbuf
, IEEE80211_MAX_SSID_LEN
);
7655 brcms_b_write_shm(wlc
->hw
, M_SSIDLEN
, (u16
) cfg
->SSID_len
);
7659 brcms_c_bss_update_probe_resp(struct brcms_c_info
*wlc
,
7660 struct brcms_bss_cfg
*cfg
,
7663 u16 prb_resp
[BCN_TMPL_LEN
/ 2];
7664 int len
= BCN_TMPL_LEN
;
7667 * write the probe response to hardware, or save in
7668 * the config structure
7671 /* create the probe response template */
7672 brcms_c_bcn_prb_template(wlc
, IEEE80211_STYPE_PROBE_RESP
, 0,
7673 cfg
, prb_resp
, &len
);
7676 brcms_c_suspend_mac_and_wait(wlc
);
7678 /* write the probe response into the template region */
7679 brcms_b_write_template_ram(wlc
->hw
, T_PRS_TPL_BASE
,
7680 (len
+ 3) & ~3, prb_resp
);
7682 /* write the length of the probe response frame (+PLCP/-FCS) */
7683 brcms_b_write_shm(wlc
->hw
, M_PRB_RESP_FRM_LEN
, (u16
) len
);
7685 /* write the SSID and SSID length */
7686 brcms_c_shm_ssid_upd(wlc
, cfg
);
7689 * Write PLCP headers and durations for probe response frames
7690 * at all rates. Use the actual frame length covered by the
7691 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7692 * by subtracting the PLCP len and adding the FCS.
7694 len
+= (-D11_PHY_HDR_LEN
+ FCS_LEN
);
7695 brcms_c_mod_prb_rsp_rate_table(wlc
, (u16
) len
);
7698 brcms_c_enable_mac(wlc
);
7701 void brcms_c_update_probe_resp(struct brcms_c_info
*wlc
, bool suspend
)
7703 struct brcms_bss_cfg
*bsscfg
= wlc
->bsscfg
;
7705 /* update AP or IBSS probe responses */
7706 if (bsscfg
->up
&& !bsscfg
->BSS
)
7707 brcms_c_bss_update_probe_resp(wlc
, bsscfg
, suspend
);
7710 int brcms_b_xmtfifo_sz_get(struct brcms_hardware
*wlc_hw
, uint fifo
,
7716 *blocks
= wlc_hw
->xmtfifo_sz
[fifo
];
7722 brcms_c_set_addrmatch(struct brcms_c_info
*wlc
, int match_reg_offset
,
7725 brcms_b_set_addrmatch(wlc
->hw
, match_reg_offset
, addr
);
7726 if (match_reg_offset
== RCM_BSSID_OFFSET
)
7727 memcpy(wlc
->bsscfg
->BSSID
, addr
, ETH_ALEN
);
7731 * Flag 'scan in progress' to withhold dynamic phy calibration
7733 void brcms_c_scan_start(struct brcms_c_info
*wlc
)
7735 wlc_phy_hold_upd(wlc
->band
->pi
, PHY_HOLD_FOR_SCAN
, true);
7738 void brcms_c_scan_stop(struct brcms_c_info
*wlc
)
7740 wlc_phy_hold_upd(wlc
->band
->pi
, PHY_HOLD_FOR_SCAN
, false);
7743 void brcms_c_associate_upd(struct brcms_c_info
*wlc
, bool state
)
7745 wlc
->pub
->associated
= state
;
7746 wlc
->bsscfg
->associated
= state
;
7750 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7751 * AMPDU traffic, packets pending in hardware have to be invalidated so that
7752 * when later on hardware releases them, they can be handled appropriately.
7754 void brcms_c_inval_dma_pkts(struct brcms_hardware
*hw
,
7755 struct ieee80211_sta
*sta
,
7756 void (*dma_callback_fn
))
7758 struct dma_pub
*dmah
;
7760 for (i
= 0; i
< NFIFO
; i
++) {
7763 dma_walk_packets(dmah
, dma_callback_fn
, sta
);
7767 int brcms_c_get_curband(struct brcms_c_info
*wlc
)
7769 return wlc
->band
->bandunit
;
7772 void brcms_c_wait_for_tx_completion(struct brcms_c_info
*wlc
, bool drop
)
7777 /* Kick DMA to send any pending AMPDU */
7778 for (i
= 0; i
< ARRAY_SIZE(wlc
->hw
->di
); i
++)
7780 dma_txflush(wlc
->hw
->di
[i
]);
7782 /* wait for queue and DMA fifos to run dry */
7783 while (brcms_txpktpendtot(wlc
) > 0) {
7784 brcms_msleep(wlc
->wl
, 1);
7790 WARN_ON_ONCE(timeout
== 0);
7793 void brcms_c_set_beacon_listen_interval(struct brcms_c_info
*wlc
, u8 interval
)
7795 wlc
->bcn_li_bcn
= interval
;
7797 brcms_c_bcn_li_upd(wlc
);
7800 int brcms_c_set_tx_power(struct brcms_c_info
*wlc
, int txpwr
)
7804 /* Remove override bit and clip to max qdbm value */
7805 qdbm
= min_t(uint
, txpwr
* BRCMS_TXPWR_DB_FACTOR
, 0xff);
7806 return wlc_phy_txpower_set(wlc
->band
->pi
, qdbm
, false);
7809 int brcms_c_get_tx_power(struct brcms_c_info
*wlc
)
7814 wlc_phy_txpower_get(wlc
->band
->pi
, &qdbm
, &override
);
7816 /* Return qdbm units */
7817 return (int)(qdbm
/ BRCMS_TXPWR_DB_FACTOR
);
7820 /* Process received frames */
7822 * Return true if more frames need to be processed. false otherwise.
7823 * Param 'bound' indicates max. # frames to process before break out.
7825 static void brcms_c_recv(struct brcms_c_info
*wlc
, struct sk_buff
*p
)
7827 struct d11rxhdr
*rxh
;
7828 struct ieee80211_hdr
*h
;
7832 brcms_dbg_rx(wlc
->hw
->d11core
, "wl%d\n", wlc
->pub
->unit
);
7834 /* frame starts with rxhdr */
7835 rxh
= (struct d11rxhdr
*) (p
->data
);
7837 /* strip off rxhdr */
7838 skb_pull(p
, BRCMS_HWRXOFF
);
7840 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7841 if (rxh
->RxStatus1
& RXS_PBPRES
) {
7843 brcms_err(wlc
->hw
->d11core
,
7844 "wl%d: recv: rcvd runt of len %d\n",
7845 wlc
->pub
->unit
, p
->len
);
7851 h
= (struct ieee80211_hdr
*)(p
->data
+ D11_PHY_HDR_LEN
);
7854 if (rxh
->RxStatus1
& RXS_FCSERR
) {
7855 if (!(wlc
->filter_flags
& FIF_FCSFAIL
))
7859 /* check received pkt has at least frame control field */
7860 if (len
< D11_PHY_HDR_LEN
+ sizeof(h
->frame_control
))
7863 /* not supporting A-MSDU */
7864 is_amsdu
= rxh
->RxStatus2
& RXS_AMSDU_MASK
;
7868 brcms_c_recvctl(wlc
, rxh
, p
);
7872 brcmu_pkt_buf_free_skb(p
);
7875 /* Process received frames */
7877 * Return true if more frames need to be processed. false otherwise.
7878 * Param 'bound' indicates max. # frames to process before break out.
7881 brcms_b_recv(struct brcms_hardware
*wlc_hw
, uint fifo
, bool bound
)
7884 struct sk_buff
*next
= NULL
;
7885 struct sk_buff_head recv_frames
;
7888 uint bound_limit
= bound
? RXBND
: -1;
7890 brcms_dbg_rx(wlc_hw
->d11core
, "wl%d\n", wlc_hw
->unit
);
7891 skb_queue_head_init(&recv_frames
);
7893 /* gather received frames */
7894 while (dma_rx(wlc_hw
->di
[fifo
], &recv_frames
)) {
7896 /* !give others some time to run! */
7897 if (++n
>= bound_limit
)
7901 /* post more rbufs */
7902 dma_rxfill(wlc_hw
->di
[fifo
]);
7904 /* process each frame */
7905 skb_queue_walk_safe(&recv_frames
, p
, next
) {
7906 struct d11rxhdr_le
*rxh_le
;
7907 struct d11rxhdr
*rxh
;
7909 skb_unlink(p
, &recv_frames
);
7910 rxh_le
= (struct d11rxhdr_le
*)p
->data
;
7911 rxh
= (struct d11rxhdr
*)p
->data
;
7913 /* fixup rx header endianness */
7914 rxh
->RxFrameSize
= le16_to_cpu(rxh_le
->RxFrameSize
);
7915 rxh
->PhyRxStatus_0
= le16_to_cpu(rxh_le
->PhyRxStatus_0
);
7916 rxh
->PhyRxStatus_1
= le16_to_cpu(rxh_le
->PhyRxStatus_1
);
7917 rxh
->PhyRxStatus_2
= le16_to_cpu(rxh_le
->PhyRxStatus_2
);
7918 rxh
->PhyRxStatus_3
= le16_to_cpu(rxh_le
->PhyRxStatus_3
);
7919 rxh
->PhyRxStatus_4
= le16_to_cpu(rxh_le
->PhyRxStatus_4
);
7920 rxh
->PhyRxStatus_5
= le16_to_cpu(rxh_le
->PhyRxStatus_5
);
7921 rxh
->RxStatus1
= le16_to_cpu(rxh_le
->RxStatus1
);
7922 rxh
->RxStatus2
= le16_to_cpu(rxh_le
->RxStatus2
);
7923 rxh
->RxTSFTime
= le16_to_cpu(rxh_le
->RxTSFTime
);
7924 rxh
->RxChan
= le16_to_cpu(rxh_le
->RxChan
);
7926 brcms_c_recv(wlc_hw
->wlc
, p
);
7929 return n
>= bound_limit
;
7932 /* second-level interrupt processing
7933 * Return true if another dpc needs to be re-scheduled. false otherwise.
7934 * Param 'bounded' indicates if applicable loops should be bounded.
7936 bool brcms_c_dpc(struct brcms_c_info
*wlc
, bool bounded
)
7939 struct brcms_hardware
*wlc_hw
= wlc
->hw
;
7940 struct bcma_device
*core
= wlc_hw
->d11core
;
7942 if (brcms_deviceremoved(wlc
)) {
7943 brcms_err(core
, "wl%d: %s: dead chip\n", wlc_hw
->unit
,
7945 brcms_down(wlc
->wl
);
7949 /* grab and clear the saved software intstatus bits */
7950 macintstatus
= wlc
->macintstatus
;
7951 wlc
->macintstatus
= 0;
7953 BCMMSG(wlc
->wiphy
, "wl%d: macintstatus 0x%x\n",
7954 wlc_hw
->unit
, macintstatus
);
7956 WARN_ON(macintstatus
& MI_PRQ
); /* PRQ Interrupt in non-MBSS */
7959 if (macintstatus
& MI_TFS
) {
7961 if (brcms_b_txstatus(wlc
->hw
, bounded
, &fatal
))
7962 wlc
->macintstatus
|= MI_TFS
;
7964 brcms_err(core
, "MI_TFS: fatal\n");
7969 if (macintstatus
& (MI_TBTT
| MI_DTIM_TBTT
))
7972 /* ATIM window end */
7973 if (macintstatus
& MI_ATIMWINEND
) {
7974 brcms_dbg_info(core
, "end of ATIM window\n");
7975 bcma_set32(core
, D11REGOFFS(maccommand
), wlc
->qvalid
);
7980 * received data or control frame, MI_DMAINT is
7981 * indication of RX_FIFO interrupt
7983 if (macintstatus
& MI_DMAINT
)
7984 if (brcms_b_recv(wlc_hw
, RX_FIFO
, bounded
))
7985 wlc
->macintstatus
|= MI_DMAINT
;
7987 /* noise sample collected */
7988 if (macintstatus
& MI_BG_NOISE
)
7989 wlc_phy_noise_sample_intr(wlc_hw
->band
->pi
);
7991 if (macintstatus
& MI_GP0
) {
7992 brcms_err(core
, "wl%d: PSM microcode watchdog fired at %d "
7993 "(seconds). Resetting.\n", wlc_hw
->unit
, wlc_hw
->now
);
7995 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
7996 __func__
, ai_get_chip_id(wlc_hw
->sih
),
7997 ai_get_chiprev(wlc_hw
->sih
));
7998 brcms_fatal_error(wlc_hw
->wlc
->wl
);
8001 /* gptimer timeout */
8002 if (macintstatus
& MI_TO
)
8003 bcma_write32(core
, D11REGOFFS(gptimer
), 0);
8005 if (macintstatus
& MI_RFDISABLE
) {
8006 brcms_dbg_info(core
, "wl%d: BMAC Detected a change on the"
8007 " RF Disable Input\n", wlc_hw
->unit
);
8008 brcms_rfkill_set_hw_state(wlc
->wl
);
8011 /* it isn't done and needs to be resched if macintstatus is non-zero */
8012 return wlc
->macintstatus
!= 0;
8015 brcms_fatal_error(wlc_hw
->wlc
->wl
);
8016 return wlc
->macintstatus
!= 0;
8019 void brcms_c_init(struct brcms_c_info
*wlc
, bool mute_tx
)
8021 struct bcma_device
*core
= wlc
->hw
->d11core
;
8022 struct ieee80211_channel
*ch
= wlc
->pub
->ieee_hw
->conf
.channel
;
8025 brcms_dbg_info(core
, "wl%d\n", wlc
->pub
->unit
);
8027 chanspec
= ch20mhz_chspec(ch
->hw_value
);
8029 brcms_b_init(wlc
->hw
, chanspec
);
8031 /* update beacon listen interval */
8032 brcms_c_bcn_li_upd(wlc
);
8034 /* write ethernet address to core */
8035 brcms_c_set_mac(wlc
->bsscfg
);
8036 brcms_c_set_bssid(wlc
->bsscfg
);
8038 /* Update tsf_cfprep if associated and up */
8039 if (wlc
->pub
->associated
&& wlc
->bsscfg
->up
) {
8042 /* get beacon period and convert to uS */
8043 bi
= wlc
->bsscfg
->current_bss
->beacon_period
<< 10;
8045 * update since init path would reset
8048 bcma_write32(core
, D11REGOFFS(tsf_cfprep
),
8049 bi
<< CFPREP_CBI_SHIFT
);
8051 /* Update maccontrol PM related bits */
8052 brcms_c_set_ps_ctrl(wlc
);
8055 brcms_c_bandinit_ordered(wlc
, chanspec
);
8057 /* init probe response timeout */
8058 brcms_b_write_shm(wlc
->hw
, M_PRS_MAXTIME
, wlc
->prb_resp_timeout
);
8060 /* init max burst txop (framebursting) */
8061 brcms_b_write_shm(wlc
->hw
, M_MBURST_TXOP
,
8063 _rifs
? (EDCF_AC_VO_TXOP_AP
<< 5) : MAXFRAMEBURST_TXOP
));
8065 /* initialize maximum allowed duty cycle */
8066 brcms_c_duty_cycle_set(wlc
, wlc
->tx_duty_cycle_ofdm
, true, true);
8067 brcms_c_duty_cycle_set(wlc
, wlc
->tx_duty_cycle_cck
, false, true);
8070 * Update some shared memory locations related to
8071 * max AMPDU size allowed to received
8073 brcms_c_ampdu_shm_upd(wlc
->ampdu
);
8075 /* band-specific inits */
8076 brcms_c_bsinit(wlc
);
8078 /* Enable EDCF mode (while the MAC is suspended) */
8079 bcma_set16(core
, D11REGOFFS(ifs_ctl
), IFS_USEEDCF
);
8080 brcms_c_edcf_setparams(wlc
, false);
8082 /* read the ucode version if we have not yet done so */
8083 if (wlc
->ucode_rev
== 0) {
8085 brcms_b_read_shm(wlc
->hw
, M_BOM_REV_MAJOR
) << NBITS(u16
);
8086 wlc
->ucode_rev
|= brcms_b_read_shm(wlc
->hw
, M_BOM_REV_MINOR
);
8089 /* ..now really unleash hell (allow the MAC out of suspend) */
8090 brcms_c_enable_mac(wlc
);
8092 /* suspend the tx fifos and mute the phy for preism cac time */
8094 brcms_b_mute(wlc
->hw
, true);
8096 /* enable the RF Disable Delay timer */
8097 bcma_write32(core
, D11REGOFFS(rfdisabledly
), RFDISABLE_DEFAULT
);
8100 * Initialize WME parameters; if they haven't been set by some other
8101 * mechanism (IOVar, etc) then read them from the hardware.
8103 if (GFIELD(wlc
->wme_retries
[0], EDCF_SHORT
) == 0) {
8104 /* Uninitialized; read from HW */
8107 for (ac
= 0; ac
< IEEE80211_NUM_ACS
; ac
++)
8108 wlc
->wme_retries
[ac
] =
8109 brcms_b_read_shm(wlc
->hw
, M_AC_TXLMT_ADDR(ac
));
8114 * The common driver entry routine. Error codes should be unique
8116 struct brcms_c_info
*
8117 brcms_c_attach(struct brcms_info
*wl
, struct bcma_device
*core
, uint unit
,
8118 bool piomode
, uint
*perr
)
8120 struct brcms_c_info
*wlc
;
8123 struct brcms_pub
*pub
;
8125 /* allocate struct brcms_c_info state and its substructures */
8126 wlc
= brcms_c_attach_malloc(unit
, &err
, 0);
8129 wlc
->wiphy
= wl
->wiphy
;
8136 wlc
->band
= wlc
->bandstate
[0];
8137 wlc
->core
= wlc
->corestate
;
8140 pub
->_piomode
= piomode
;
8141 wlc
->bandinit_pending
= false;
8143 /* populate struct brcms_c_info with default values */
8144 brcms_c_info_init(wlc
, unit
);
8146 /* update sta/ap related parameters */
8147 brcms_c_ap_upd(wlc
);
8150 * low level attach steps(all hw accesses go
8151 * inside, no more in rest of the attach)
8153 err
= brcms_b_attach(wlc
, core
, unit
, piomode
);
8157 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_PAM_OVR
, OFF
);
8159 pub
->phy_11ncapable
= BRCMS_PHY_11N_CAP(wlc
->band
);
8161 /* disable allowed duty cycle */
8162 wlc
->tx_duty_cycle_ofdm
= 0;
8163 wlc
->tx_duty_cycle_cck
= 0;
8165 brcms_c_stf_phy_chain_calc(wlc
);
8167 /* txchain 1: txant 0, txchain 2: txant 1 */
8168 if (BRCMS_ISNPHY(wlc
->band
) && (wlc
->stf
->txstreams
== 1))
8169 wlc
->stf
->txant
= wlc
->stf
->hw_txchain
- 1;
8171 /* push to BMAC driver */
8172 wlc_phy_stf_chain_init(wlc
->band
->pi
, wlc
->stf
->hw_txchain
,
8173 wlc
->stf
->hw_rxchain
);
8175 /* pull up some info resulting from the low attach */
8176 for (i
= 0; i
< NFIFO
; i
++)
8177 wlc
->core
->txavail
[i
] = wlc
->hw
->txavail
[i
];
8179 memcpy(&wlc
->perm_etheraddr
, &wlc
->hw
->etheraddr
, ETH_ALEN
);
8180 memcpy(&pub
->cur_etheraddr
, &wlc
->hw
->etheraddr
, ETH_ALEN
);
8182 for (j
= 0; j
< wlc
->pub
->_nbands
; j
++) {
8183 wlc
->band
= wlc
->bandstate
[j
];
8185 if (!brcms_c_attach_stf_ant_init(wlc
)) {
8190 /* default contention windows size limits */
8191 wlc
->band
->CWmin
= APHY_CWMIN
;
8192 wlc
->band
->CWmax
= PHY_CWMAX
;
8194 /* init gmode value */
8195 if (wlc
->band
->bandtype
== BRCM_BAND_2G
) {
8196 wlc
->band
->gmode
= GMODE_AUTO
;
8197 brcms_c_protection_upd(wlc
, BRCMS_PROT_G_USER
,
8201 /* init _n_enab supported mode */
8202 if (BRCMS_PHY_11N_CAP(wlc
->band
)) {
8203 pub
->_n_enab
= SUPPORT_11N
;
8204 brcms_c_protection_upd(wlc
, BRCMS_PROT_N_USER
,
8206 SUPPORT_11N
) ? WL_11N_2x2
:
8210 /* init per-band default rateset, depend on band->gmode */
8211 brcms_default_rateset(wlc
, &wlc
->band
->defrateset
);
8213 /* fill in hw_rateset */
8214 brcms_c_rateset_filter(&wlc
->band
->defrateset
,
8215 &wlc
->band
->hw_rateset
, false,
8216 BRCMS_RATES_CCK_OFDM
, BRCMS_RATE_MASK
,
8217 (bool) (wlc
->pub
->_n_enab
& SUPPORT_11N
));
8221 * update antenna config due to
8222 * wlc->stf->txant/txchain/ant_rx_ovr change
8224 brcms_c_stf_phy_txant_upd(wlc
);
8226 /* attach each modules */
8227 err
= brcms_c_attach_module(wlc
);
8231 if (!brcms_c_timers_init(wlc
, unit
)) {
8232 wiphy_err(wl
->wiphy
, "wl%d: %s: init_timer failed\n", unit
,
8238 /* depend on rateset, gmode */
8239 wlc
->cmi
= brcms_c_channel_mgr_attach(wlc
);
8241 wiphy_err(wl
->wiphy
, "wl%d: %s: channel_mgr_attach failed"
8242 "\n", unit
, __func__
);
8247 /* init default when all parameters are ready, i.e. ->rateset */
8248 brcms_c_bss_default_init(wlc
);
8251 * Complete the wlc default state initializations..
8254 wlc
->bsscfg
->wlc
= wlc
;
8256 wlc
->mimoft
= FT_HT
;
8257 wlc
->mimo_40txbw
= AUTO
;
8258 wlc
->ofdm_40txbw
= AUTO
;
8259 wlc
->cck_40txbw
= AUTO
;
8260 brcms_c_update_mimo_band_bwcap(wlc
, BRCMS_N_BW_20IN2G_40IN5G
);
8262 /* Set default values of SGI */
8263 if (BRCMS_SGI_CAP_PHY(wlc
)) {
8264 brcms_c_ht_update_sgi_rx(wlc
, (BRCMS_N_SGI_20
|
8266 } else if (BRCMS_ISSSLPNPHY(wlc
->band
)) {
8267 brcms_c_ht_update_sgi_rx(wlc
, (BRCMS_N_SGI_20
|
8270 brcms_c_ht_update_sgi_rx(wlc
, 0);
8273 brcms_b_antsel_set(wlc
->hw
, wlc
->asi
->antsel_avail
);
8281 wiphy_err(wl
->wiphy
, "wl%d: %s: failed with err %d\n",
8282 unit
, __func__
, err
);
8284 brcms_c_detach(wlc
);